Arnold Schwaighofer | 48abc5c | 2007-10-12 21:30:57 +0000 | [diff] [blame] | 1 | //====- X86InstrX86-64.td - Describe the X86 Instr. Set ----*- tablegen -*-===// |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 2 | // |
| 3 | // The LLVM Compiler Infrastructure |
| 4 | // |
Chris Lattner | 4ee451d | 2007-12-29 20:36:04 +0000 | [diff] [blame^] | 5 | // This file is distributed under the University of Illinois Open Source |
| 6 | // License. See LICENSE.TXT for details. |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 7 | // |
| 8 | //===----------------------------------------------------------------------===// |
| 9 | // |
| 10 | // This file describes the X86-64 instruction set, defining the instructions, |
| 11 | // and properties of the instructions which are needed for code generation, |
| 12 | // machine code emission, and analysis. |
| 13 | // |
| 14 | //===----------------------------------------------------------------------===// |
| 15 | |
| 16 | //===----------------------------------------------------------------------===// |
| 17 | // Operand Definitions... |
| 18 | // |
| 19 | |
| 20 | // 64-bits but only 32 bits are significant. |
| 21 | def i64i32imm : Operand<i64>; |
| 22 | // 64-bits but only 8 bits are significant. |
| 23 | def i64i8imm : Operand<i64>; |
| 24 | |
| 25 | def lea64mem : Operand<i64> { |
| 26 | let PrintMethod = "printi64mem"; |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 27 | let MIOperandInfo = (ops GR64, i8imm, GR64, i32imm); |
| 28 | } |
| 29 | |
| 30 | def lea64_32mem : Operand<i32> { |
| 31 | let PrintMethod = "printlea64_32mem"; |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 32 | let MIOperandInfo = (ops GR32, i8imm, GR32, i32imm); |
| 33 | } |
| 34 | |
| 35 | //===----------------------------------------------------------------------===// |
| 36 | // Complex Pattern Definitions... |
| 37 | // |
| 38 | def lea64addr : ComplexPattern<i64, 4, "SelectLEAAddr", |
Evan Cheng | 19f2ffc | 2006-12-05 04:01:03 +0000 | [diff] [blame] | 39 | [add, mul, shl, or, frameindex, X86Wrapper], |
Evan Cheng | 0085a28 | 2006-11-30 21:55:46 +0000 | [diff] [blame] | 40 | []>; |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 41 | |
| 42 | //===----------------------------------------------------------------------===// |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 43 | // Pattern fragments... |
| 44 | // |
| 45 | |
| 46 | def i64immSExt32 : PatLeaf<(i64 imm), [{ |
| 47 | // i64immSExt32 predicate - True if the 64-bit immediate fits in a 32-bit |
| 48 | // sign extended field. |
| 49 | return (int64_t)N->getValue() == (int32_t)N->getValue(); |
| 50 | }]>; |
| 51 | |
| 52 | def i64immZExt32 : PatLeaf<(i64 imm), [{ |
| 53 | // i64immZExt32 predicate - True if the 64-bit immediate fits in a 32-bit |
| 54 | // unsignedsign extended field. |
| 55 | return (uint64_t)N->getValue() == (uint32_t)N->getValue(); |
| 56 | }]>; |
| 57 | |
| 58 | def i64immSExt8 : PatLeaf<(i64 imm), [{ |
| 59 | // i64immSExt8 predicate - True if the 64-bit immediate fits in a 8-bit |
| 60 | // sign extended field. |
| 61 | return (int64_t)N->getValue() == (int8_t)N->getValue(); |
| 62 | }]>; |
| 63 | |
Evan Cheng | 466685d | 2006-10-09 20:57:25 +0000 | [diff] [blame] | 64 | def sextloadi64i1 : PatFrag<(ops node:$ptr), (i64 (sextloadi1 node:$ptr))>; |
| 65 | def sextloadi64i8 : PatFrag<(ops node:$ptr), (i64 (sextloadi8 node:$ptr))>; |
| 66 | def sextloadi64i16 : PatFrag<(ops node:$ptr), (i64 (sextloadi16 node:$ptr))>; |
| 67 | def sextloadi64i32 : PatFrag<(ops node:$ptr), (i64 (sextloadi32 node:$ptr))>; |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 68 | |
Evan Cheng | 466685d | 2006-10-09 20:57:25 +0000 | [diff] [blame] | 69 | def zextloadi64i1 : PatFrag<(ops node:$ptr), (i64 (zextloadi1 node:$ptr))>; |
| 70 | def zextloadi64i8 : PatFrag<(ops node:$ptr), (i64 (zextloadi8 node:$ptr))>; |
| 71 | def zextloadi64i16 : PatFrag<(ops node:$ptr), (i64 (zextloadi16 node:$ptr))>; |
| 72 | def zextloadi64i32 : PatFrag<(ops node:$ptr), (i64 (zextloadi32 node:$ptr))>; |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 73 | |
Evan Cheng | 466685d | 2006-10-09 20:57:25 +0000 | [diff] [blame] | 74 | def extloadi64i1 : PatFrag<(ops node:$ptr), (i64 (extloadi1 node:$ptr))>; |
| 75 | def extloadi64i8 : PatFrag<(ops node:$ptr), (i64 (extloadi8 node:$ptr))>; |
| 76 | def extloadi64i16 : PatFrag<(ops node:$ptr), (i64 (extloadi16 node:$ptr))>; |
| 77 | def extloadi64i32 : PatFrag<(ops node:$ptr), (i64 (extloadi32 node:$ptr))>; |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 78 | |
| 79 | //===----------------------------------------------------------------------===// |
| 80 | // Instruction list... |
| 81 | // |
| 82 | |
Evan Cheng | 6e141fd | 2007-12-12 23:12:09 +0000 | [diff] [blame] | 83 | let isImplicitDef = 1 in |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 84 | def IMPLICIT_DEF_GR64 : I<0, Pseudo, (outs GR64:$dst), (ins), |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 85 | "#IMPLICIT_DEF $dst", |
| 86 | [(set GR64:$dst, (undef))]>; |
| 87 | |
| 88 | //===----------------------------------------------------------------------===// |
| 89 | // Call Instructions... |
| 90 | // |
Evan Cheng | ffbacca | 2007-07-21 00:34:19 +0000 | [diff] [blame] | 91 | let isCall = 1 in |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 92 | // All calls clobber the non-callee saved registers... |
| 93 | let Defs = [RAX, RCX, RDX, RSI, RDI, R8, R9, R10, R11, |
| 94 | FP0, FP1, FP2, FP3, FP4, FP5, FP6, ST0, |
Bill Wendling | bff35d1 | 2007-04-26 21:06:48 +0000 | [diff] [blame] | 95 | MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7, |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 96 | XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7, |
Evan Cheng | 1ed37fd | 2007-09-27 19:01:55 +0000 | [diff] [blame] | 97 | XMM8, XMM9, XMM10, XMM11, XMM12, XMM13, XMM14, XMM15, EFLAGS] in { |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 98 | def CALL64pcrel32 : I<0xE8, RawFrm, (outs), (ins i64imm:$dst, variable_ops), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 99 | "call\t${dst:call}", []>; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 100 | def CALL64r : I<0xFF, MRM2r, (outs), (ins GR64:$dst, variable_ops), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 101 | "call\t{*}$dst", [(X86call GR64:$dst)]>; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 102 | def CALL64m : I<0xFF, MRM2m, (outs), (ins i64mem:$dst, variable_ops), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 103 | "call\t{*}$dst", []>; |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 104 | } |
| 105 | |
Arnold Schwaighofer | c85e171 | 2007-10-11 19:40:01 +0000 | [diff] [blame] | 106 | |
| 107 | |
| 108 | let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in |
| 109 | def TCRETURNdi64 : I<0, Pseudo, (outs), (ins i64imm:$dst, i32imm:$offset), |
| 110 | "#TC_RETURN $dst $offset", |
| 111 | []>; |
| 112 | |
| 113 | let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in |
| 114 | def TCRETURNri64 : I<0, Pseudo, (outs), (ins GR64:$dst, i32imm:$offset), |
| 115 | "#TC_RETURN $dst $offset", |
| 116 | []>; |
| 117 | |
| 118 | |
| 119 | let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in |
| 120 | def TAILJMPr64 : I<0xFF, MRM4r, (outs), (ins GR64:$dst), "jmp{q}\t{*}$dst # TAILCALL", |
| 121 | []>; |
| 122 | |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 123 | // Branches |
Owen Anderson | 20ab290 | 2007-11-12 07:39:39 +0000 | [diff] [blame] | 124 | let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in { |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 125 | def JMP64r : I<0xFF, MRM4r, (outs), (ins GR64:$dst), "jmp{q}\t{*}$dst", |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 126 | [(brind GR64:$dst)]>; |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 127 | def JMP64m : I<0xFF, MRM4m, (outs), (ins i64mem:$dst), "jmp{q}\t{*}$dst", |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 128 | [(brind (loadi64 addr:$dst))]>; |
| 129 | } |
| 130 | |
| 131 | //===----------------------------------------------------------------------===// |
| 132 | // Miscellaneous Instructions... |
| 133 | // |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 134 | let Defs = [RBP,RSP], Uses = [RBP,RSP] in |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 135 | def LEAVE64 : I<0xC9, RawFrm, |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 136 | (outs), (ins), "leave", []>; |
| 137 | let Defs = [RSP], Uses = [RSP] in { |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 138 | def POP64r : I<0x58, AddRegFrm, |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 139 | (outs GR64:$reg), (ins), "pop{q}\t$reg", []>; |
Dan Gohman | 638c96d | 2007-06-18 14:12:56 +0000 | [diff] [blame] | 140 | def PUSH64r : I<0x50, AddRegFrm, |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 141 | (outs), (ins GR64:$reg), "push{q}\t$reg", []>; |
| 142 | } |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 143 | |
Evan Cheng | 2f245ba | 2007-09-26 01:29:06 +0000 | [diff] [blame] | 144 | let Defs = [RSP, EFLAGS], Uses = [RSP] in |
Evan Cheng | bf4f89d | 2007-09-26 21:28:00 +0000 | [diff] [blame] | 145 | def POPFQ : I<0x9D, RawFrm, (outs), (ins), "popf", []>, REX_W; |
Evan Cheng | 2f245ba | 2007-09-26 01:29:06 +0000 | [diff] [blame] | 146 | let Defs = [RSP], Uses = [RSP, EFLAGS] in |
Evan Cheng | bf4f89d | 2007-09-26 21:28:00 +0000 | [diff] [blame] | 147 | def PUSHFQ : I<0x9C, RawFrm, (outs), (ins), "pushf", []>; |
Evan Cheng | 2f245ba | 2007-09-26 01:29:06 +0000 | [diff] [blame] | 148 | |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 149 | def LEA64_32r : I<0x8D, MRMSrcMem, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 150 | (outs GR32:$dst), (ins lea64_32mem:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 151 | "lea{l}\t{$src|$dst}, {$dst|$src}", |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 152 | [(set GR32:$dst, lea32addr:$src)]>, Requires<[In64BitMode]>; |
| 153 | |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 154 | def LEA64r : RI<0x8D, MRMSrcMem, (outs GR64:$dst), (ins lea64mem:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 155 | "lea{q}\t{$src|$dst}, {$dst|$src}", |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 156 | [(set GR64:$dst, lea64addr:$src)]>; |
| 157 | |
| 158 | let isTwoAddress = 1 in |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 159 | def BSWAP64r : RI<0xC8, AddRegFrm, (outs GR64:$dst), (ins GR64:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 160 | "bswap{q}\t$dst", |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 161 | [(set GR64:$dst, (bswap GR64:$src))]>, TB; |
| 162 | // Exchange |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 163 | def XCHG64rr : RI<0x87, MRMDestReg, (outs), (ins GR64:$src1, GR64:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 164 | "xchg{q}\t{$src2|$src1}, {$src1|$src2}", []>; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 165 | def XCHG64mr : RI<0x87, MRMDestMem, (outs), (ins i64mem:$src1, GR64:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 166 | "xchg{q}\t{$src2|$src1}, {$src1|$src2}", []>; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 167 | def XCHG64rm : RI<0x87, MRMSrcMem, (outs), (ins GR64:$src1, i64mem:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 168 | "xchg{q}\t{$src2|$src1}, {$src1|$src2}", []>; |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 169 | |
Evan Cheng | 18efe26 | 2007-12-14 02:13:44 +0000 | [diff] [blame] | 170 | // Bit scan instructions. |
| 171 | let Defs = [EFLAGS] in { |
Evan Cheng | fd9e473 | 2007-12-14 18:49:43 +0000 | [diff] [blame] | 172 | def BSF64rr : RI<0xBC, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src), |
Dan Gohman | 1a8001e | 2007-12-14 15:10:00 +0000 | [diff] [blame] | 173 | "bsf{q}\t{$src, $dst|$dst, $src}", |
Evan Cheng | 8ec8611 | 2007-12-14 18:25:34 +0000 | [diff] [blame] | 174 | [(set GR64:$dst, (X86bsf GR64:$src)), (implicit EFLAGS)]>, TB; |
Evan Cheng | 18efe26 | 2007-12-14 02:13:44 +0000 | [diff] [blame] | 175 | def BSF64rm : RI<0xBC, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src), |
Dan Gohman | 1a8001e | 2007-12-14 15:10:00 +0000 | [diff] [blame] | 176 | "bsf{q}\t{$src, $dst|$dst, $src}", |
Evan Cheng | 8ec8611 | 2007-12-14 18:25:34 +0000 | [diff] [blame] | 177 | [(set GR64:$dst, (X86bsf (loadi64 addr:$src))), |
| 178 | (implicit EFLAGS)]>, TB; |
Evan Cheng | 18efe26 | 2007-12-14 02:13:44 +0000 | [diff] [blame] | 179 | |
Evan Cheng | fd9e473 | 2007-12-14 18:49:43 +0000 | [diff] [blame] | 180 | def BSR64rr : RI<0xBD, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src), |
Dan Gohman | 1a8001e | 2007-12-14 15:10:00 +0000 | [diff] [blame] | 181 | "bsr{q}\t{$src, $dst|$dst, $src}", |
Evan Cheng | 8ec8611 | 2007-12-14 18:25:34 +0000 | [diff] [blame] | 182 | [(set GR64:$dst, (X86bsr GR64:$src)), (implicit EFLAGS)]>, TB; |
Evan Cheng | 18efe26 | 2007-12-14 02:13:44 +0000 | [diff] [blame] | 183 | def BSR64rm : RI<0xBD, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src), |
Dan Gohman | 1a8001e | 2007-12-14 15:10:00 +0000 | [diff] [blame] | 184 | "bsr{q}\t{$src, $dst|$dst, $src}", |
Evan Cheng | 8ec8611 | 2007-12-14 18:25:34 +0000 | [diff] [blame] | 185 | [(set GR64:$dst, (X86bsr (loadi64 addr:$src))), |
| 186 | (implicit EFLAGS)]>, TB; |
Evan Cheng | 18efe26 | 2007-12-14 02:13:44 +0000 | [diff] [blame] | 187 | } // Defs = [EFLAGS] |
| 188 | |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 189 | // Repeat string ops |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 190 | let Defs = [RCX,RDI,RSI], Uses = [RCX,RDI,RSI] in |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 191 | def REP_MOVSQ : RI<0xA5, RawFrm, (outs), (ins), "{rep;movsq|rep movsq}", |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 192 | [(X86rep_movs i64)]>, REP; |
| 193 | let Defs = [RCX,RDI], Uses = [RAX,RCX,RDI] in |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 194 | def REP_STOSQ : RI<0xAB, RawFrm, (outs), (ins), "{rep;stosq|rep stosq}", |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 195 | [(X86rep_stos i64)]>, REP; |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 196 | |
| 197 | //===----------------------------------------------------------------------===// |
| 198 | // Move Instructions... |
| 199 | // |
| 200 | |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 201 | def MOV64rr : RI<0x89, MRMDestReg, (outs GR64:$dst), (ins GR64:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 202 | "mov{q}\t{$src, $dst|$dst, $src}", []>; |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 203 | |
Bill Wendling | 627c00b | 2007-12-17 23:07:56 +0000 | [diff] [blame] | 204 | let isReMaterializable = 1, neverHasSideEffects = 1 in { |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 205 | def MOV64ri : RIi64<0xB8, AddRegFrm, (outs GR64:$dst), (ins i64imm:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 206 | "movabs{q}\t{$src, $dst|$dst, $src}", |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 207 | [(set GR64:$dst, imm:$src)]>; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 208 | def MOV64ri32 : RIi32<0xC7, MRM0r, (outs GR64:$dst), (ins i64i32imm:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 209 | "mov{q}\t{$src, $dst|$dst, $src}", |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 210 | [(set GR64:$dst, i64immSExt32:$src)]>; |
Dan Gohman | 1ab7989 | 2007-09-07 21:32:51 +0000 | [diff] [blame] | 211 | } |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 212 | |
Evan Cheng | 2f39426 | 2007-08-30 05:49:43 +0000 | [diff] [blame] | 213 | let isLoad = 1 in |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 214 | def MOV64rm : RI<0x8B, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 215 | "mov{q}\t{$src, $dst|$dst, $src}", |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 216 | [(set GR64:$dst, (load addr:$src))]>; |
| 217 | |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 218 | def MOV64mr : RI<0x89, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 219 | "mov{q}\t{$src, $dst|$dst, $src}", |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 220 | [(store GR64:$src, addr:$dst)]>; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 221 | def MOV64mi32 : RIi32<0xC7, MRM0m, (outs), (ins i64mem:$dst, i64i32imm:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 222 | "mov{q}\t{$src, $dst|$dst, $src}", |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 223 | [(store i64immSExt32:$src, addr:$dst)]>; |
| 224 | |
| 225 | // Sign/Zero extenders |
| 226 | |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 227 | def MOVSX64rr8 : RI<0xBE, MRMSrcReg, (outs GR64:$dst), (ins GR8 :$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 228 | "movs{bq|x}\t{$src, $dst|$dst, $src}", |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 229 | [(set GR64:$dst, (sext GR8:$src))]>, TB; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 230 | def MOVSX64rm8 : RI<0xBE, MRMSrcMem, (outs GR64:$dst), (ins i8mem :$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 231 | "movs{bq|x}\t{$src, $dst|$dst, $src}", |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 232 | [(set GR64:$dst, (sextloadi64i8 addr:$src))]>, TB; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 233 | def MOVSX64rr16: RI<0xBF, MRMSrcReg, (outs GR64:$dst), (ins GR16:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 234 | "movs{wq|x}\t{$src, $dst|$dst, $src}", |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 235 | [(set GR64:$dst, (sext GR16:$src))]>, TB; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 236 | def MOVSX64rm16: RI<0xBF, MRMSrcMem, (outs GR64:$dst), (ins i16mem:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 237 | "movs{wq|x}\t{$src, $dst|$dst, $src}", |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 238 | [(set GR64:$dst, (sextloadi64i16 addr:$src))]>, TB; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 239 | def MOVSX64rr32: RI<0x63, MRMSrcReg, (outs GR64:$dst), (ins GR32:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 240 | "movs{lq|xd}\t{$src, $dst|$dst, $src}", |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 241 | [(set GR64:$dst, (sext GR32:$src))]>; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 242 | def MOVSX64rm32: RI<0x63, MRMSrcMem, (outs GR64:$dst), (ins i32mem:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 243 | "movs{lq|xd}\t{$src, $dst|$dst, $src}", |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 244 | [(set GR64:$dst, (sextloadi64i32 addr:$src))]>; |
| 245 | |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 246 | def MOVZX64rr8 : RI<0xB6, MRMSrcReg, (outs GR64:$dst), (ins GR8 :$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 247 | "movz{bq|x}\t{$src, $dst|$dst, $src}", |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 248 | [(set GR64:$dst, (zext GR8:$src))]>, TB; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 249 | def MOVZX64rm8 : RI<0xB6, MRMSrcMem, (outs GR64:$dst), (ins i8mem :$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 250 | "movz{bq|x}\t{$src, $dst|$dst, $src}", |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 251 | [(set GR64:$dst, (zextloadi64i8 addr:$src))]>, TB; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 252 | def MOVZX64rr16: RI<0xB7, MRMSrcReg, (outs GR64:$dst), (ins GR16:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 253 | "movz{wq|x}\t{$src, $dst|$dst, $src}", |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 254 | [(set GR64:$dst, (zext GR16:$src))]>, TB; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 255 | def MOVZX64rm16: RI<0xB7, MRMSrcMem, (outs GR64:$dst), (ins i16mem:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 256 | "movz{wq|x}\t{$src, $dst|$dst, $src}", |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 257 | [(set GR64:$dst, (zextloadi64i16 addr:$src))]>, TB; |
| 258 | |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 259 | let Defs = [RAX], Uses = [EAX] in |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 260 | def CDQE : RI<0x98, RawFrm, (outs), (ins), |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 261 | "{cltq|cdqe}", []>; // RAX = signext(EAX) |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 262 | |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 263 | let Defs = [RAX,RDX], Uses = [RAX] in |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 264 | def CQO : RI<0x99, RawFrm, (outs), (ins), |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 265 | "{cqto|cqo}", []>; // RDX:RAX = signext(RAX) |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 266 | |
| 267 | //===----------------------------------------------------------------------===// |
| 268 | // Arithmetic Instructions... |
| 269 | // |
| 270 | |
Evan Cheng | 24f2ea3 | 2007-09-14 21:48:26 +0000 | [diff] [blame] | 271 | let Defs = [EFLAGS] in { |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 272 | let isTwoAddress = 1 in { |
| 273 | let isConvertibleToThreeAddress = 1 in { |
| 274 | let isCommutable = 1 in |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 275 | def ADD64rr : RI<0x01, MRMDestReg, (outs GR64:$dst), (ins GR64:$src1, GR64:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 276 | "add{q}\t{$src2, $dst|$dst, $src2}", |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 277 | [(set GR64:$dst, (add GR64:$src1, GR64:$src2))]>; |
| 278 | |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 279 | def ADD64ri32 : RIi32<0x81, MRM0r, (outs GR64:$dst), (ins GR64:$src1, i64i32imm:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 280 | "add{q}\t{$src2, $dst|$dst, $src2}", |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 281 | [(set GR64:$dst, (add GR64:$src1, i64immSExt32:$src2))]>; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 282 | def ADD64ri8 : RIi8<0x83, MRM0r, (outs GR64:$dst), (ins GR64:$src1, i64i8imm:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 283 | "add{q}\t{$src2, $dst|$dst, $src2}", |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 284 | [(set GR64:$dst, (add GR64:$src1, i64immSExt8:$src2))]>; |
| 285 | } // isConvertibleToThreeAddress |
| 286 | |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 287 | def ADD64rm : RI<0x03, MRMSrcMem, (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 288 | "add{q}\t{$src2, $dst|$dst, $src2}", |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 289 | [(set GR64:$dst, (add GR64:$src1, (load addr:$src2)))]>; |
| 290 | } // isTwoAddress |
| 291 | |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 292 | def ADD64mr : RI<0x01, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 293 | "add{q}\t{$src2, $dst|$dst, $src2}", |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 294 | [(store (add (load addr:$dst), GR64:$src2), addr:$dst)]>; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 295 | def ADD64mi32 : RIi32<0x81, MRM0m, (outs), (ins i64mem:$dst, i64i32imm :$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 296 | "add{q}\t{$src2, $dst|$dst, $src2}", |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 297 | [(store (add (load addr:$dst), i64immSExt32:$src2), addr:$dst)]>; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 298 | def ADD64mi8 : RIi8<0x83, MRM0m, (outs), (ins i64mem:$dst, i64i8imm :$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 299 | "add{q}\t{$src2, $dst|$dst, $src2}", |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 300 | [(store (add (load addr:$dst), i64immSExt8:$src2), addr:$dst)]>; |
| 301 | |
Evan Cheng | 3154cb6 | 2007-10-05 17:59:57 +0000 | [diff] [blame] | 302 | let Uses = [EFLAGS] in { |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 303 | let isTwoAddress = 1 in { |
| 304 | let isCommutable = 1 in |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 305 | def ADC64rr : RI<0x11, MRMDestReg, (outs GR64:$dst), (ins GR64:$src1, GR64:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 306 | "adc{q}\t{$src2, $dst|$dst, $src2}", |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 307 | [(set GR64:$dst, (adde GR64:$src1, GR64:$src2))]>; |
| 308 | |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 309 | def ADC64rm : RI<0x13, MRMSrcMem , (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 310 | "adc{q}\t{$src2, $dst|$dst, $src2}", |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 311 | [(set GR64:$dst, (adde GR64:$src1, (load addr:$src2)))]>; |
| 312 | |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 313 | def ADC64ri32 : RIi32<0x81, MRM2r, (outs GR64:$dst), (ins GR64:$src1, i64i32imm:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 314 | "adc{q}\t{$src2, $dst|$dst, $src2}", |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 315 | [(set GR64:$dst, (adde GR64:$src1, i64immSExt32:$src2))]>; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 316 | def ADC64ri8 : RIi8<0x83, MRM2r, (outs GR64:$dst), (ins GR64:$src1, i64i8imm:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 317 | "adc{q}\t{$src2, $dst|$dst, $src2}", |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 318 | [(set GR64:$dst, (adde GR64:$src1, i64immSExt8:$src2))]>; |
| 319 | } // isTwoAddress |
| 320 | |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 321 | def ADC64mr : RI<0x11, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 322 | "adc{q}\t{$src2, $dst|$dst, $src2}", |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 323 | [(store (adde (load addr:$dst), GR64:$src2), addr:$dst)]>; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 324 | def ADC64mi32 : RIi32<0x81, MRM2m, (outs), (ins i64mem:$dst, i64i32imm:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 325 | "adc{q}\t{$src2, $dst|$dst, $src2}", |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 326 | [(store (adde (load addr:$dst), i64immSExt8:$src2), addr:$dst)]>; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 327 | def ADC64mi8 : RIi8<0x83, MRM2m, (outs), (ins i64mem:$dst, i64i8imm :$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 328 | "adc{q}\t{$src2, $dst|$dst, $src2}", |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 329 | [(store (adde (load addr:$dst), i64immSExt8:$src2), addr:$dst)]>; |
Evan Cheng | 3154cb6 | 2007-10-05 17:59:57 +0000 | [diff] [blame] | 330 | } // Uses = [EFLAGS] |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 331 | |
| 332 | let isTwoAddress = 1 in { |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 333 | def SUB64rr : RI<0x29, MRMDestReg, (outs GR64:$dst), (ins GR64:$src1, GR64:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 334 | "sub{q}\t{$src2, $dst|$dst, $src2}", |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 335 | [(set GR64:$dst, (sub GR64:$src1, GR64:$src2))]>; |
| 336 | |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 337 | def SUB64rm : RI<0x2B, MRMSrcMem, (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 338 | "sub{q}\t{$src2, $dst|$dst, $src2}", |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 339 | [(set GR64:$dst, (sub GR64:$src1, (load addr:$src2)))]>; |
| 340 | |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 341 | def SUB64ri32 : RIi32<0x81, MRM5r, (outs GR64:$dst), (ins GR64:$src1, i64i32imm:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 342 | "sub{q}\t{$src2, $dst|$dst, $src2}", |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 343 | [(set GR64:$dst, (sub GR64:$src1, i64immSExt32:$src2))]>; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 344 | def SUB64ri8 : RIi8<0x83, MRM5r, (outs GR64:$dst), (ins GR64:$src1, i64i8imm:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 345 | "sub{q}\t{$src2, $dst|$dst, $src2}", |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 346 | [(set GR64:$dst, (sub GR64:$src1, i64immSExt8:$src2))]>; |
| 347 | } // isTwoAddress |
| 348 | |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 349 | def SUB64mr : RI<0x29, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 350 | "sub{q}\t{$src2, $dst|$dst, $src2}", |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 351 | [(store (sub (load addr:$dst), GR64:$src2), addr:$dst)]>; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 352 | def SUB64mi32 : RIi32<0x81, MRM5m, (outs), (ins i64mem:$dst, i64i32imm:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 353 | "sub{q}\t{$src2, $dst|$dst, $src2}", |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 354 | [(store (sub (load addr:$dst), i64immSExt32:$src2), addr:$dst)]>; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 355 | def SUB64mi8 : RIi8<0x83, MRM5m, (outs), (ins i64mem:$dst, i64i8imm :$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 356 | "sub{q}\t{$src2, $dst|$dst, $src2}", |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 357 | [(store (sub (load addr:$dst), i64immSExt8:$src2), addr:$dst)]>; |
| 358 | |
Evan Cheng | 3154cb6 | 2007-10-05 17:59:57 +0000 | [diff] [blame] | 359 | let Uses = [EFLAGS] in { |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 360 | let isTwoAddress = 1 in { |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 361 | def SBB64rr : RI<0x19, MRMDestReg, (outs GR64:$dst), (ins GR64:$src1, GR64:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 362 | "sbb{q}\t{$src2, $dst|$dst, $src2}", |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 363 | [(set GR64:$dst, (sube GR64:$src1, GR64:$src2))]>; |
| 364 | |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 365 | def SBB64rm : RI<0x1B, MRMSrcMem, (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 366 | "sbb{q}\t{$src2, $dst|$dst, $src2}", |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 367 | [(set GR64:$dst, (sube GR64:$src1, (load addr:$src2)))]>; |
| 368 | |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 369 | def SBB64ri32 : RIi32<0x81, MRM3r, (outs GR64:$dst), (ins GR64:$src1, i64i32imm:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 370 | "sbb{q}\t{$src2, $dst|$dst, $src2}", |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 371 | [(set GR64:$dst, (sube GR64:$src1, i64immSExt32:$src2))]>; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 372 | def SBB64ri8 : RIi8<0x83, MRM3r, (outs GR64:$dst), (ins GR64:$src1, i64i8imm:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 373 | "sbb{q}\t{$src2, $dst|$dst, $src2}", |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 374 | [(set GR64:$dst, (sube GR64:$src1, i64immSExt8:$src2))]>; |
| 375 | } // isTwoAddress |
| 376 | |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 377 | def SBB64mr : RI<0x19, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 378 | "sbb{q}\t{$src2, $dst|$dst, $src2}", |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 379 | [(store (sube (load addr:$dst), GR64:$src2), addr:$dst)]>; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 380 | def SBB64mi32 : RIi32<0x81, MRM3m, (outs), (ins i64mem:$dst, i64i32imm:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 381 | "sbb{q}\t{$src2, $dst|$dst, $src2}", |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 382 | [(store (sube (load addr:$dst), i64immSExt32:$src2), addr:$dst)]>; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 383 | def SBB64mi8 : RIi8<0x83, MRM3m, (outs), (ins i64mem:$dst, i64i8imm :$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 384 | "sbb{q}\t{$src2, $dst|$dst, $src2}", |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 385 | [(store (sube (load addr:$dst), i64immSExt8:$src2), addr:$dst)]>; |
Evan Cheng | 3154cb6 | 2007-10-05 17:59:57 +0000 | [diff] [blame] | 386 | } // Uses = [EFLAGS] |
Evan Cheng | 24f2ea3 | 2007-09-14 21:48:26 +0000 | [diff] [blame] | 387 | } // Defs = [EFLAGS] |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 388 | |
| 389 | // Unsigned multiplication |
Evan Cheng | 24f2ea3 | 2007-09-14 21:48:26 +0000 | [diff] [blame] | 390 | let Defs = [RAX,RDX,EFLAGS], Uses = [RAX] in { |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 391 | def MUL64r : RI<0xF7, MRM4r, (outs), (ins GR64:$src), |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 392 | "mul{q}\t$src", []>; // RAX,RDX = RAX*GR64 |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 393 | def MUL64m : RI<0xF7, MRM4m, (outs), (ins i64mem:$src), |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 394 | "mul{q}\t$src", []>; // RAX,RDX = RAX*[mem64] |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 395 | |
| 396 | // Signed multiplication |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 397 | def IMUL64r : RI<0xF7, MRM5r, (outs), (ins GR64:$src), |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 398 | "imul{q}\t$src", []>; // RAX,RDX = RAX*GR64 |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 399 | def IMUL64m : RI<0xF7, MRM5m, (outs), (ins i64mem:$src), |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 400 | "imul{q}\t$src", []>; // RAX,RDX = RAX*[mem64] |
| 401 | } |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 402 | |
Evan Cheng | 24f2ea3 | 2007-09-14 21:48:26 +0000 | [diff] [blame] | 403 | let Defs = [EFLAGS] in { |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 404 | let isTwoAddress = 1 in { |
| 405 | let isCommutable = 1 in |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 406 | def IMUL64rr : RI<0xAF, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src1, GR64:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 407 | "imul{q}\t{$src2, $dst|$dst, $src2}", |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 408 | [(set GR64:$dst, (mul GR64:$src1, GR64:$src2))]>, TB; |
| 409 | |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 410 | def IMUL64rm : RI<0xAF, MRMSrcMem, (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 411 | "imul{q}\t{$src2, $dst|$dst, $src2}", |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 412 | [(set GR64:$dst, (mul GR64:$src1, (load addr:$src2)))]>, TB; |
| 413 | } // isTwoAddress |
| 414 | |
| 415 | // Suprisingly enough, these are not two address instructions! |
| 416 | def IMUL64rri32 : RIi32<0x69, MRMSrcReg, // GR64 = GR64*I32 |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 417 | (outs GR64:$dst), (ins GR64:$src1, i64i32imm:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 418 | "imul{q}\t{$src2, $src1, $dst|$dst, $src1, $src2}", |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 419 | [(set GR64:$dst, (mul GR64:$src1, i64immSExt32:$src2))]>; |
| 420 | def IMUL64rri8 : RIi8<0x6B, MRMSrcReg, // GR64 = GR64*I8 |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 421 | (outs GR64:$dst), (ins GR64:$src1, i64i8imm:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 422 | "imul{q}\t{$src2, $src1, $dst|$dst, $src1, $src2}", |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 423 | [(set GR64:$dst, (mul GR64:$src1, i64immSExt8:$src2))]>; |
| 424 | def IMUL64rmi32 : RIi32<0x69, MRMSrcMem, // GR64 = [mem64]*I32 |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 425 | (outs GR64:$dst), (ins i64mem:$src1, i64i32imm:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 426 | "imul{q}\t{$src2, $src1, $dst|$dst, $src1, $src2}", |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 427 | [(set GR64:$dst, (mul (load addr:$src1), i64immSExt32:$src2))]>; |
| 428 | def IMUL64rmi8 : RIi8<0x6B, MRMSrcMem, // GR64 = [mem64]*I8 |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 429 | (outs GR64:$dst), (ins i64mem:$src1, i64i8imm: $src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 430 | "imul{q}\t{$src2, $src1, $dst|$dst, $src1, $src2}", |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 431 | [(set GR64:$dst, (mul (load addr:$src1), i64immSExt8:$src2))]>; |
Evan Cheng | 24f2ea3 | 2007-09-14 21:48:26 +0000 | [diff] [blame] | 432 | } // Defs = [EFLAGS] |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 433 | |
| 434 | // Unsigned division / remainder |
Evan Cheng | 24f2ea3 | 2007-09-14 21:48:26 +0000 | [diff] [blame] | 435 | let Defs = [RAX,RDX,EFLAGS], Uses = [RAX,RDX] in { |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 436 | def DIV64r : RI<0xF7, MRM6r, (outs), (ins GR64:$src), // RDX:RAX/r64 = RAX,RDX |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 437 | "div{q}\t$src", []>; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 438 | def DIV64m : RI<0xF7, MRM6m, (outs), (ins i64mem:$src), // RDX:RAX/[mem64] = RAX,RDX |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 439 | "div{q}\t$src", []>; |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 440 | |
| 441 | // Signed division / remainder |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 442 | def IDIV64r: RI<0xF7, MRM7r, (outs), (ins GR64:$src), // RDX:RAX/r64 = RAX,RDX |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 443 | "idiv{q}\t$src", []>; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 444 | def IDIV64m: RI<0xF7, MRM7m, (outs), (ins i64mem:$src), // RDX:RAX/[mem64] = RAX,RDX |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 445 | "idiv{q}\t$src", []>; |
| 446 | } |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 447 | |
| 448 | // Unary instructions |
Evan Cheng | 24f2ea3 | 2007-09-14 21:48:26 +0000 | [diff] [blame] | 449 | let Defs = [EFLAGS], CodeSize = 2 in { |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 450 | let isTwoAddress = 1 in |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 451 | def NEG64r : RI<0xF7, MRM3r, (outs GR64:$dst), (ins GR64:$src), "neg{q}\t$dst", |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 452 | [(set GR64:$dst, (ineg GR64:$src))]>; |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 453 | def NEG64m : RI<0xF7, MRM3m, (outs), (ins i64mem:$dst), "neg{q}\t$dst", |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 454 | [(store (ineg (loadi64 addr:$dst)), addr:$dst)]>; |
| 455 | |
| 456 | let isTwoAddress = 1, isConvertibleToThreeAddress = 1 in |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 457 | def INC64r : RI<0xFF, MRM0r, (outs GR64:$dst), (ins GR64:$src), "inc{q}\t$dst", |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 458 | [(set GR64:$dst, (add GR64:$src, 1))]>; |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 459 | def INC64m : RI<0xFF, MRM0m, (outs), (ins i64mem:$dst), "inc{q}\t$dst", |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 460 | [(store (add (loadi64 addr:$dst), 1), addr:$dst)]>; |
| 461 | |
| 462 | let isTwoAddress = 1, isConvertibleToThreeAddress = 1 in |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 463 | def DEC64r : RI<0xFF, MRM1r, (outs GR64:$dst), (ins GR64:$src), "dec{q}\t$dst", |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 464 | [(set GR64:$dst, (add GR64:$src, -1))]>; |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 465 | def DEC64m : RI<0xFF, MRM1m, (outs), (ins i64mem:$dst), "dec{q}\t$dst", |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 466 | [(store (add (loadi64 addr:$dst), -1), addr:$dst)]>; |
| 467 | |
| 468 | // In 64-bit mode, single byte INC and DEC cannot be encoded. |
| 469 | let isTwoAddress = 1, isConvertibleToThreeAddress = 1 in { |
| 470 | // Can transform into LEA. |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 471 | def INC64_16r : I<0xFF, MRM0r, (outs GR16:$dst), (ins GR16:$src), "inc{w}\t$dst", |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 472 | [(set GR16:$dst, (add GR16:$src, 1))]>, |
| 473 | OpSize, Requires<[In64BitMode]>; |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 474 | def INC64_32r : I<0xFF, MRM0r, (outs GR32:$dst), (ins GR32:$src), "inc{l}\t$dst", |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 475 | [(set GR32:$dst, (add GR32:$src, 1))]>, |
| 476 | Requires<[In64BitMode]>; |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 477 | def DEC64_16r : I<0xFF, MRM1r, (outs GR16:$dst), (ins GR16:$src), "dec{w}\t$dst", |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 478 | [(set GR16:$dst, (add GR16:$src, -1))]>, |
| 479 | OpSize, Requires<[In64BitMode]>; |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 480 | def DEC64_32r : I<0xFF, MRM1r, (outs GR32:$dst), (ins GR32:$src), "dec{l}\t$dst", |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 481 | [(set GR32:$dst, (add GR32:$src, -1))]>, |
| 482 | Requires<[In64BitMode]>; |
| 483 | } // isConvertibleToThreeAddress |
Evan Cheng | 66f7163 | 2007-10-19 21:23:22 +0000 | [diff] [blame] | 484 | |
| 485 | // These are duplicates of their 32-bit counterparts. Only needed so X86 knows |
| 486 | // how to unfold them. |
| 487 | let isTwoAddress = 0, CodeSize = 2 in { |
| 488 | def INC64_16m : I<0xFF, MRM0m, (outs), (ins i16mem:$dst), "inc{w}\t$dst", |
| 489 | [(store (add (loadi16 addr:$dst), 1), addr:$dst)]>, |
| 490 | OpSize, Requires<[In64BitMode]>; |
| 491 | def INC64_32m : I<0xFF, MRM0m, (outs), (ins i32mem:$dst), "inc{l}\t$dst", |
| 492 | [(store (add (loadi32 addr:$dst), 1), addr:$dst)]>, |
| 493 | Requires<[In64BitMode]>; |
| 494 | def DEC64_16m : I<0xFF, MRM1m, (outs), (ins i16mem:$dst), "dec{w}\t$dst", |
| 495 | [(store (add (loadi16 addr:$dst), -1), addr:$dst)]>, |
| 496 | OpSize, Requires<[In64BitMode]>; |
| 497 | def DEC64_32m : I<0xFF, MRM1m, (outs), (ins i32mem:$dst), "dec{l}\t$dst", |
| 498 | [(store (add (loadi32 addr:$dst), -1), addr:$dst)]>, |
| 499 | Requires<[In64BitMode]>; |
| 500 | } |
Evan Cheng | 24f2ea3 | 2007-09-14 21:48:26 +0000 | [diff] [blame] | 501 | } // Defs = [EFLAGS], CodeSize |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 502 | |
| 503 | |
Evan Cheng | 24f2ea3 | 2007-09-14 21:48:26 +0000 | [diff] [blame] | 504 | let Defs = [EFLAGS] in { |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 505 | // Shift instructions |
| 506 | let isTwoAddress = 1 in { |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 507 | let Uses = [CL] in |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 508 | def SHL64rCL : RI<0xD3, MRM4r, (outs GR64:$dst), (ins GR64:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 509 | "shl{q}\t{%cl, $dst|$dst, %CL}", |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 510 | [(set GR64:$dst, (shl GR64:$src, CL))]>; |
Evan Cheng | b952d1f | 2007-10-05 18:20:36 +0000 | [diff] [blame] | 511 | let isConvertibleToThreeAddress = 1 in // Can transform into LEA. |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 512 | def SHL64ri : RIi8<0xC1, MRM4r, (outs GR64:$dst), (ins GR64:$src1, i8imm:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 513 | "shl{q}\t{$src2, $dst|$dst, $src2}", |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 514 | [(set GR64:$dst, (shl GR64:$src1, (i8 imm:$src2)))]>; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 515 | def SHL64r1 : RI<0xD1, MRM4r, (outs GR64:$dst), (ins GR64:$src1), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 516 | "shl{q}\t$dst", []>; |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 517 | } // isTwoAddress |
| 518 | |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 519 | let Uses = [CL] in |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 520 | def SHL64mCL : RI<0xD3, MRM4m, (outs), (ins i64mem:$dst), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 521 | "shl{q}\t{%cl, $dst|$dst, %CL}", |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 522 | [(store (shl (loadi64 addr:$dst), CL), addr:$dst)]>; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 523 | def SHL64mi : RIi8<0xC1, MRM4m, (outs), (ins i64mem:$dst, i8imm:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 524 | "shl{q}\t{$src, $dst|$dst, $src}", |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 525 | [(store (shl (loadi64 addr:$dst), (i8 imm:$src)), addr:$dst)]>; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 526 | def SHL64m1 : RI<0xD1, MRM4m, (outs), (ins i64mem:$dst), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 527 | "shl{q}\t$dst", |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 528 | [(store (shl (loadi64 addr:$dst), (i8 1)), addr:$dst)]>; |
| 529 | |
| 530 | let isTwoAddress = 1 in { |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 531 | let Uses = [CL] in |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 532 | def SHR64rCL : RI<0xD3, MRM5r, (outs GR64:$dst), (ins GR64:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 533 | "shr{q}\t{%cl, $dst|$dst, %CL}", |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 534 | [(set GR64:$dst, (srl GR64:$src, CL))]>; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 535 | def SHR64ri : RIi8<0xC1, MRM5r, (outs GR64:$dst), (ins GR64:$src1, i8imm:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 536 | "shr{q}\t{$src2, $dst|$dst, $src2}", |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 537 | [(set GR64:$dst, (srl GR64:$src1, (i8 imm:$src2)))]>; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 538 | def SHR64r1 : RI<0xD1, MRM5r, (outs GR64:$dst), (ins GR64:$src1), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 539 | "shr{q}\t$dst", |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 540 | [(set GR64:$dst, (srl GR64:$src1, (i8 1)))]>; |
| 541 | } // isTwoAddress |
| 542 | |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 543 | let Uses = [CL] in |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 544 | def SHR64mCL : RI<0xD3, MRM5m, (outs), (ins i64mem:$dst), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 545 | "shr{q}\t{%cl, $dst|$dst, %CL}", |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 546 | [(store (srl (loadi64 addr:$dst), CL), addr:$dst)]>; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 547 | def SHR64mi : RIi8<0xC1, MRM5m, (outs), (ins i64mem:$dst, i8imm:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 548 | "shr{q}\t{$src, $dst|$dst, $src}", |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 549 | [(store (srl (loadi64 addr:$dst), (i8 imm:$src)), addr:$dst)]>; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 550 | def SHR64m1 : RI<0xD1, MRM5m, (outs), (ins i64mem:$dst), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 551 | "shr{q}\t$dst", |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 552 | [(store (srl (loadi64 addr:$dst), (i8 1)), addr:$dst)]>; |
| 553 | |
| 554 | let isTwoAddress = 1 in { |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 555 | let Uses = [CL] in |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 556 | def SAR64rCL : RI<0xD3, MRM7r, (outs GR64:$dst), (ins GR64:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 557 | "sar{q}\t{%cl, $dst|$dst, %CL}", |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 558 | [(set GR64:$dst, (sra GR64:$src, CL))]>; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 559 | def SAR64ri : RIi8<0xC1, MRM7r, (outs GR64:$dst), (ins GR64:$src1, i8imm:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 560 | "sar{q}\t{$src2, $dst|$dst, $src2}", |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 561 | [(set GR64:$dst, (sra GR64:$src1, (i8 imm:$src2)))]>; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 562 | def SAR64r1 : RI<0xD1, MRM7r, (outs GR64:$dst), (ins GR64:$src1), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 563 | "sar{q}\t$dst", |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 564 | [(set GR64:$dst, (sra GR64:$src1, (i8 1)))]>; |
| 565 | } // isTwoAddress |
| 566 | |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 567 | let Uses = [CL] in |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 568 | def SAR64mCL : RI<0xD3, MRM7m, (outs), (ins i64mem:$dst), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 569 | "sar{q}\t{%cl, $dst|$dst, %CL}", |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 570 | [(store (sra (loadi64 addr:$dst), CL), addr:$dst)]>; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 571 | def SAR64mi : RIi8<0xC1, MRM7m, (outs), (ins i64mem:$dst, i8imm:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 572 | "sar{q}\t{$src, $dst|$dst, $src}", |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 573 | [(store (sra (loadi64 addr:$dst), (i8 imm:$src)), addr:$dst)]>; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 574 | def SAR64m1 : RI<0xD1, MRM7m, (outs), (ins i64mem:$dst), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 575 | "sar{q}\t$dst", |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 576 | [(store (sra (loadi64 addr:$dst), (i8 1)), addr:$dst)]>; |
| 577 | |
| 578 | // Rotate instructions |
| 579 | let isTwoAddress = 1 in { |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 580 | let Uses = [CL] in |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 581 | def ROL64rCL : RI<0xD3, MRM0r, (outs GR64:$dst), (ins GR64:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 582 | "rol{q}\t{%cl, $dst|$dst, %CL}", |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 583 | [(set GR64:$dst, (rotl GR64:$src, CL))]>; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 584 | def ROL64ri : RIi8<0xC1, MRM0r, (outs GR64:$dst), (ins GR64:$src1, i8imm:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 585 | "rol{q}\t{$src2, $dst|$dst, $src2}", |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 586 | [(set GR64:$dst, (rotl GR64:$src1, (i8 imm:$src2)))]>; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 587 | def ROL64r1 : RI<0xD1, MRM0r, (outs GR64:$dst), (ins GR64:$src1), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 588 | "rol{q}\t$dst", |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 589 | [(set GR64:$dst, (rotl GR64:$src1, (i8 1)))]>; |
| 590 | } // isTwoAddress |
| 591 | |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 592 | let Uses = [CL] in |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 593 | def ROL64mCL : I<0xD3, MRM0m, (outs), (ins i64mem:$dst), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 594 | "rol{q}\t{%cl, $dst|$dst, %CL}", |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 595 | [(store (rotl (loadi64 addr:$dst), CL), addr:$dst)]>; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 596 | def ROL64mi : RIi8<0xC1, MRM0m, (outs), (ins i64mem:$dst, i8imm:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 597 | "rol{q}\t{$src, $dst|$dst, $src}", |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 598 | [(store (rotl (loadi64 addr:$dst), (i8 imm:$src)), addr:$dst)]>; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 599 | def ROL64m1 : RI<0xD1, MRM0m, (outs), (ins i64mem:$dst), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 600 | "rol{q}\t$dst", |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 601 | [(store (rotl (loadi64 addr:$dst), (i8 1)), addr:$dst)]>; |
| 602 | |
| 603 | let isTwoAddress = 1 in { |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 604 | let Uses = [CL] in |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 605 | def ROR64rCL : RI<0xD3, MRM1r, (outs GR64:$dst), (ins GR64:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 606 | "ror{q}\t{%cl, $dst|$dst, %CL}", |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 607 | [(set GR64:$dst, (rotr GR64:$src, CL))]>; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 608 | def ROR64ri : RIi8<0xC1, MRM1r, (outs GR64:$dst), (ins GR64:$src1, i8imm:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 609 | "ror{q}\t{$src2, $dst|$dst, $src2}", |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 610 | [(set GR64:$dst, (rotr GR64:$src1, (i8 imm:$src2)))]>; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 611 | def ROR64r1 : RI<0xD1, MRM1r, (outs GR64:$dst), (ins GR64:$src1), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 612 | "ror{q}\t$dst", |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 613 | [(set GR64:$dst, (rotr GR64:$src1, (i8 1)))]>; |
| 614 | } // isTwoAddress |
| 615 | |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 616 | let Uses = [CL] in |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 617 | def ROR64mCL : RI<0xD3, MRM1m, (outs), (ins i64mem:$dst), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 618 | "ror{q}\t{%cl, $dst|$dst, %CL}", |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 619 | [(store (rotr (loadi64 addr:$dst), CL), addr:$dst)]>; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 620 | def ROR64mi : RIi8<0xC1, MRM1m, (outs), (ins i64mem:$dst, i8imm:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 621 | "ror{q}\t{$src, $dst|$dst, $src}", |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 622 | [(store (rotr (loadi64 addr:$dst), (i8 imm:$src)), addr:$dst)]>; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 623 | def ROR64m1 : RI<0xD1, MRM1m, (outs), (ins i64mem:$dst), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 624 | "ror{q}\t$dst", |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 625 | [(store (rotr (loadi64 addr:$dst), (i8 1)), addr:$dst)]>; |
| 626 | |
| 627 | // Double shift instructions (generalizations of rotate) |
| 628 | let isTwoAddress = 1 in { |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 629 | let Uses = [CL] in { |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 630 | def SHLD64rrCL : RI<0xA5, MRMDestReg, (outs GR64:$dst), (ins GR64:$src1, GR64:$src2), |
Dan Gohman | e47f1f9 | 2007-09-14 23:17:45 +0000 | [diff] [blame] | 631 | "shld{q}\t{%cl, $src2, $dst|$dst, $src2, %CL}", |
| 632 | [(set GR64:$dst, (X86shld GR64:$src1, GR64:$src2, CL))]>, TB; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 633 | def SHRD64rrCL : RI<0xAD, MRMDestReg, (outs GR64:$dst), (ins GR64:$src1, GR64:$src2), |
Dan Gohman | e47f1f9 | 2007-09-14 23:17:45 +0000 | [diff] [blame] | 634 | "shrd{q}\t{%cl, $src2, $dst|$dst, $src2, %CL}", |
| 635 | [(set GR64:$dst, (X86shrd GR64:$src1, GR64:$src2, CL))]>, TB; |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 636 | } |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 637 | |
| 638 | let isCommutable = 1 in { // FIXME: Update X86InstrInfo::commuteInstruction |
| 639 | def SHLD64rri8 : RIi8<0xA4, MRMDestReg, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 640 | (outs GR64:$dst), (ins GR64:$src1, GR64:$src2, i8imm:$src3), |
Dan Gohman | e47f1f9 | 2007-09-14 23:17:45 +0000 | [diff] [blame] | 641 | "shld{q}\t{$src3, $src2, $dst|$dst, $src2, $src3}", |
| 642 | [(set GR64:$dst, (X86shld GR64:$src1, GR64:$src2, |
| 643 | (i8 imm:$src3)))]>, |
| 644 | TB; |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 645 | def SHRD64rri8 : RIi8<0xAC, MRMDestReg, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 646 | (outs GR64:$dst), (ins GR64:$src1, GR64:$src2, i8imm:$src3), |
Dan Gohman | e47f1f9 | 2007-09-14 23:17:45 +0000 | [diff] [blame] | 647 | "shrd{q}\t{$src3, $src2, $dst|$dst, $src2, $src3}", |
| 648 | [(set GR64:$dst, (X86shrd GR64:$src1, GR64:$src2, |
| 649 | (i8 imm:$src3)))]>, |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 650 | TB; |
| 651 | } // isCommutable |
| 652 | } // isTwoAddress |
| 653 | |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 654 | let Uses = [CL] in { |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 655 | def SHLD64mrCL : RI<0xA5, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src2), |
Dan Gohman | e47f1f9 | 2007-09-14 23:17:45 +0000 | [diff] [blame] | 656 | "shld{q}\t{%cl, $src2, $dst|$dst, $src2, %CL}", |
| 657 | [(store (X86shld (loadi64 addr:$dst), GR64:$src2, CL), |
| 658 | addr:$dst)]>, TB; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 659 | def SHRD64mrCL : RI<0xAD, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src2), |
Dan Gohman | e47f1f9 | 2007-09-14 23:17:45 +0000 | [diff] [blame] | 660 | "shrd{q}\t{%cl, $src2, $dst|$dst, $src2, %CL}", |
| 661 | [(store (X86shrd (loadi64 addr:$dst), GR64:$src2, CL), |
| 662 | addr:$dst)]>, TB; |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 663 | } |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 664 | def SHLD64mri8 : RIi8<0xA4, MRMDestMem, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 665 | (outs), (ins i64mem:$dst, GR64:$src2, i8imm:$src3), |
Dan Gohman | e47f1f9 | 2007-09-14 23:17:45 +0000 | [diff] [blame] | 666 | "shld{q}\t{$src3, $src2, $dst|$dst, $src2, $src3}", |
| 667 | [(store (X86shld (loadi64 addr:$dst), GR64:$src2, |
| 668 | (i8 imm:$src3)), addr:$dst)]>, |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 669 | TB; |
| 670 | def SHRD64mri8 : RIi8<0xAC, MRMDestMem, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 671 | (outs), (ins i64mem:$dst, GR64:$src2, i8imm:$src3), |
Dan Gohman | e47f1f9 | 2007-09-14 23:17:45 +0000 | [diff] [blame] | 672 | "shrd{q}\t{$src3, $src2, $dst|$dst, $src2, $src3}", |
| 673 | [(store (X86shrd (loadi64 addr:$dst), GR64:$src2, |
| 674 | (i8 imm:$src3)), addr:$dst)]>, |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 675 | TB; |
Evan Cheng | 24f2ea3 | 2007-09-14 21:48:26 +0000 | [diff] [blame] | 676 | } // Defs = [EFLAGS] |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 677 | |
| 678 | //===----------------------------------------------------------------------===// |
| 679 | // Logical Instructions... |
| 680 | // |
| 681 | |
| 682 | let isTwoAddress = 1 in |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 683 | def NOT64r : RI<0xF7, MRM2r, (outs GR64:$dst), (ins GR64:$src), "not{q}\t$dst", |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 684 | [(set GR64:$dst, (not GR64:$src))]>; |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 685 | def NOT64m : RI<0xF7, MRM2m, (outs), (ins i64mem:$dst), "not{q}\t$dst", |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 686 | [(store (not (loadi64 addr:$dst)), addr:$dst)]>; |
| 687 | |
Evan Cheng | 24f2ea3 | 2007-09-14 21:48:26 +0000 | [diff] [blame] | 688 | let Defs = [EFLAGS] in { |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 689 | let isTwoAddress = 1 in { |
| 690 | let isCommutable = 1 in |
| 691 | def AND64rr : RI<0x21, MRMDestReg, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 692 | (outs GR64:$dst), (ins GR64:$src1, GR64:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 693 | "and{q}\t{$src2, $dst|$dst, $src2}", |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 694 | [(set GR64:$dst, (and GR64:$src1, GR64:$src2))]>; |
| 695 | def AND64rm : RI<0x23, MRMSrcMem, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 696 | (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 697 | "and{q}\t{$src2, $dst|$dst, $src2}", |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 698 | [(set GR64:$dst, (and GR64:$src1, (load addr:$src2)))]>; |
| 699 | def AND64ri32 : RIi32<0x81, MRM4r, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 700 | (outs GR64:$dst), (ins GR64:$src1, i64i32imm:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 701 | "and{q}\t{$src2, $dst|$dst, $src2}", |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 702 | [(set GR64:$dst, (and GR64:$src1, i64immSExt32:$src2))]>; |
| 703 | def AND64ri8 : RIi8<0x83, MRM4r, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 704 | (outs GR64:$dst), (ins GR64:$src1, i64i8imm:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 705 | "and{q}\t{$src2, $dst|$dst, $src2}", |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 706 | [(set GR64:$dst, (and GR64:$src1, i64immSExt8:$src2))]>; |
| 707 | } // isTwoAddress |
| 708 | |
| 709 | def AND64mr : RI<0x21, MRMDestMem, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 710 | (outs), (ins i64mem:$dst, GR64:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 711 | "and{q}\t{$src, $dst|$dst, $src}", |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 712 | [(store (and (load addr:$dst), GR64:$src), addr:$dst)]>; |
| 713 | def AND64mi32 : RIi32<0x81, MRM4m, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 714 | (outs), (ins i64mem:$dst, i64i32imm:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 715 | "and{q}\t{$src, $dst|$dst, $src}", |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 716 | [(store (and (loadi64 addr:$dst), i64immSExt32:$src), addr:$dst)]>; |
| 717 | def AND64mi8 : RIi8<0x83, MRM4m, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 718 | (outs), (ins i64mem:$dst, i64i8imm :$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 719 | "and{q}\t{$src, $dst|$dst, $src}", |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 720 | [(store (and (load addr:$dst), i64immSExt8:$src), addr:$dst)]>; |
| 721 | |
| 722 | let isTwoAddress = 1 in { |
| 723 | let isCommutable = 1 in |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 724 | def OR64rr : RI<0x09, MRMDestReg, (outs GR64:$dst), (ins GR64:$src1, GR64:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 725 | "or{q}\t{$src2, $dst|$dst, $src2}", |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 726 | [(set GR64:$dst, (or GR64:$src1, GR64:$src2))]>; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 727 | def OR64rm : RI<0x0B, MRMSrcMem , (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 728 | "or{q}\t{$src2, $dst|$dst, $src2}", |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 729 | [(set GR64:$dst, (or GR64:$src1, (load addr:$src2)))]>; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 730 | def OR64ri32 : RIi32<0x81, MRM1r, (outs GR64:$dst), (ins GR64:$src1, i64i32imm:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 731 | "or{q}\t{$src2, $dst|$dst, $src2}", |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 732 | [(set GR64:$dst, (or GR64:$src1, i64immSExt32:$src2))]>; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 733 | def OR64ri8 : RIi8<0x83, MRM1r, (outs GR64:$dst), (ins GR64:$src1, i64i8imm:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 734 | "or{q}\t{$src2, $dst|$dst, $src2}", |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 735 | [(set GR64:$dst, (or GR64:$src1, i64immSExt8:$src2))]>; |
| 736 | } // isTwoAddress |
| 737 | |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 738 | def OR64mr : RI<0x09, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 739 | "or{q}\t{$src, $dst|$dst, $src}", |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 740 | [(store (or (load addr:$dst), GR64:$src), addr:$dst)]>; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 741 | def OR64mi32 : RIi32<0x81, MRM1m, (outs), (ins i64mem:$dst, i64i32imm:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 742 | "or{q}\t{$src, $dst|$dst, $src}", |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 743 | [(store (or (loadi64 addr:$dst), i64immSExt32:$src), addr:$dst)]>; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 744 | def OR64mi8 : RIi8<0x83, MRM1m, (outs), (ins i64mem:$dst, i64i8imm:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 745 | "or{q}\t{$src, $dst|$dst, $src}", |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 746 | [(store (or (load addr:$dst), i64immSExt8:$src), addr:$dst)]>; |
| 747 | |
| 748 | let isTwoAddress = 1 in { |
| 749 | let isCommutable = 1 in |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 750 | def XOR64rr : RI<0x31, MRMDestReg, (outs GR64:$dst), (ins GR64:$src1, GR64:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 751 | "xor{q}\t{$src2, $dst|$dst, $src2}", |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 752 | [(set GR64:$dst, (xor GR64:$src1, GR64:$src2))]>; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 753 | def XOR64rm : RI<0x33, MRMSrcMem, (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 754 | "xor{q}\t{$src2, $dst|$dst, $src2}", |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 755 | [(set GR64:$dst, (xor GR64:$src1, (load addr:$src2)))]>; |
| 756 | def XOR64ri32 : RIi32<0x81, MRM6r, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 757 | (outs GR64:$dst), (ins GR64:$src1, i64i32imm:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 758 | "xor{q}\t{$src2, $dst|$dst, $src2}", |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 759 | [(set GR64:$dst, (xor GR64:$src1, i64immSExt32:$src2))]>; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 760 | def XOR64ri8 : RIi8<0x83, MRM6r, (outs GR64:$dst), (ins GR64:$src1, i64i8imm:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 761 | "xor{q}\t{$src2, $dst|$dst, $src2}", |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 762 | [(set GR64:$dst, (xor GR64:$src1, i64immSExt8:$src2))]>; |
| 763 | } // isTwoAddress |
| 764 | |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 765 | def XOR64mr : RI<0x31, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 766 | "xor{q}\t{$src, $dst|$dst, $src}", |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 767 | [(store (xor (load addr:$dst), GR64:$src), addr:$dst)]>; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 768 | def XOR64mi32 : RIi32<0x81, MRM6m, (outs), (ins i64mem:$dst, i64i32imm:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 769 | "xor{q}\t{$src, $dst|$dst, $src}", |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 770 | [(store (xor (loadi64 addr:$dst), i64immSExt32:$src), addr:$dst)]>; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 771 | def XOR64mi8 : RIi8<0x83, MRM6m, (outs), (ins i64mem:$dst, i64i8imm :$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 772 | "xor{q}\t{$src, $dst|$dst, $src}", |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 773 | [(store (xor (load addr:$dst), i64immSExt8:$src), addr:$dst)]>; |
Evan Cheng | 24f2ea3 | 2007-09-14 21:48:26 +0000 | [diff] [blame] | 774 | } // Defs = [EFLAGS] |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 775 | |
| 776 | //===----------------------------------------------------------------------===// |
| 777 | // Comparison Instructions... |
| 778 | // |
| 779 | |
| 780 | // Integer comparison |
Evan Cheng | 24f2ea3 | 2007-09-14 21:48:26 +0000 | [diff] [blame] | 781 | let Defs = [EFLAGS] in { |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 782 | let isCommutable = 1 in |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 783 | def TEST64rr : RI<0x85, MRMDestReg, (outs), (ins GR64:$src1, GR64:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 784 | "test{q}\t{$src2, $src1|$src1, $src2}", |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 785 | [(X86cmp (and GR64:$src1, GR64:$src2), 0), |
| 786 | (implicit EFLAGS)]>; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 787 | def TEST64rm : RI<0x85, MRMSrcMem, (outs), (ins GR64:$src1, i64mem:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 788 | "test{q}\t{$src2, $src1|$src1, $src2}", |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 789 | [(X86cmp (and GR64:$src1, (loadi64 addr:$src2)), 0), |
| 790 | (implicit EFLAGS)]>; |
| 791 | def TEST64ri32 : RIi32<0xF7, MRM0r, (outs), |
| 792 | (ins GR64:$src1, i64i32imm:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 793 | "test{q}\t{$src2, $src1|$src1, $src2}", |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 794 | [(X86cmp (and GR64:$src1, i64immSExt32:$src2), 0), |
| 795 | (implicit EFLAGS)]>; |
| 796 | def TEST64mi32 : RIi32<0xF7, MRM0m, (outs), |
| 797 | (ins i64mem:$src1, i64i32imm:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 798 | "test{q}\t{$src2, $src1|$src1, $src2}", |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 799 | [(X86cmp (and (loadi64 addr:$src1), i64immSExt32:$src2), 0), |
| 800 | (implicit EFLAGS)]>; |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 801 | |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 802 | def CMP64rr : RI<0x39, MRMDestReg, (outs), (ins GR64:$src1, GR64:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 803 | "cmp{q}\t{$src2, $src1|$src1, $src2}", |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 804 | [(X86cmp GR64:$src1, GR64:$src2), |
| 805 | (implicit EFLAGS)]>; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 806 | def CMP64mr : RI<0x39, MRMDestMem, (outs), (ins i64mem:$src1, GR64:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 807 | "cmp{q}\t{$src2, $src1|$src1, $src2}", |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 808 | [(X86cmp (loadi64 addr:$src1), GR64:$src2), |
| 809 | (implicit EFLAGS)]>; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 810 | def CMP64rm : RI<0x3B, MRMSrcMem, (outs), (ins GR64:$src1, i64mem:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 811 | "cmp{q}\t{$src2, $src1|$src1, $src2}", |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 812 | [(X86cmp GR64:$src1, (loadi64 addr:$src2)), |
| 813 | (implicit EFLAGS)]>; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 814 | def CMP64ri32 : RIi32<0x81, MRM7r, (outs), (ins GR64:$src1, i64i32imm:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 815 | "cmp{q}\t{$src2, $src1|$src1, $src2}", |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 816 | [(X86cmp GR64:$src1, i64immSExt32:$src2), |
Evan Cheng | 0488db9 | 2007-09-25 01:57:46 +0000 | [diff] [blame] | 817 | (implicit EFLAGS)]>; |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 818 | def CMP64mi32 : RIi32<0x81, MRM7m, (outs), |
Evan Cheng | 0488db9 | 2007-09-25 01:57:46 +0000 | [diff] [blame] | 819 | (ins i64mem:$src1, i64i32imm:$src2), |
| 820 | "cmp{q}\t{$src2, $src1|$src1, $src2}", |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 821 | [(X86cmp (loadi64 addr:$src1), i64immSExt32:$src2), |
Evan Cheng | 0488db9 | 2007-09-25 01:57:46 +0000 | [diff] [blame] | 822 | (implicit EFLAGS)]>; |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 823 | def CMP64mi8 : RIi8<0x83, MRM7m, (outs), (ins i64mem:$src1, i64i8imm:$src2), |
Evan Cheng | 0488db9 | 2007-09-25 01:57:46 +0000 | [diff] [blame] | 824 | "cmp{q}\t{$src2, $src1|$src1, $src2}", |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 825 | [(X86cmp (loadi64 addr:$src1), i64immSExt8:$src2), |
Evan Cheng | 0488db9 | 2007-09-25 01:57:46 +0000 | [diff] [blame] | 826 | (implicit EFLAGS)]>; |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 827 | def CMP64ri8 : RIi8<0x83, MRM7r, (outs), (ins GR64:$src1, i64i8imm:$src2), |
Evan Cheng | 0488db9 | 2007-09-25 01:57:46 +0000 | [diff] [blame] | 828 | "cmp{q}\t{$src2, $src1|$src1, $src2}", |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 829 | [(X86cmp GR64:$src1, i64immSExt8:$src2), |
Evan Cheng | 0488db9 | 2007-09-25 01:57:46 +0000 | [diff] [blame] | 830 | (implicit EFLAGS)]>; |
| 831 | } // Defs = [EFLAGS] |
| 832 | |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 833 | // Conditional moves |
Evan Cheng | 0488db9 | 2007-09-25 01:57:46 +0000 | [diff] [blame] | 834 | let Uses = [EFLAGS], isTwoAddress = 1 in { |
Evan Cheng | 7ad42d9 | 2007-10-05 23:13:21 +0000 | [diff] [blame] | 835 | let isCommutable = 1 in { |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 836 | def CMOVB64rr : RI<0x42, MRMSrcReg, // if <u, GR64 = GR64 |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 837 | (outs GR64:$dst), (ins GR64:$src1, GR64:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 838 | "cmovb\t{$src2, $dst|$dst, $src2}", |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 839 | [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2, |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 840 | X86_COND_B, EFLAGS))]>, TB; |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 841 | def CMOVAE64rr: RI<0x43, MRMSrcReg, // if >=u, GR64 = GR64 |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 842 | (outs GR64:$dst), (ins GR64:$src1, GR64:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 843 | "cmovae\t{$src2, $dst|$dst, $src2}", |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 844 | [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2, |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 845 | X86_COND_AE, EFLAGS))]>, TB; |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 846 | def CMOVE64rr : RI<0x44, MRMSrcReg, // if ==, GR64 = GR64 |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 847 | (outs GR64:$dst), (ins GR64:$src1, GR64:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 848 | "cmove\t{$src2, $dst|$dst, $src2}", |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 849 | [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2, |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 850 | X86_COND_E, EFLAGS))]>, TB; |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 851 | def CMOVNE64rr: RI<0x45, MRMSrcReg, // if !=, GR64 = GR64 |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 852 | (outs GR64:$dst), (ins GR64:$src1, GR64:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 853 | "cmovne\t{$src2, $dst|$dst, $src2}", |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 854 | [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2, |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 855 | X86_COND_NE, EFLAGS))]>, TB; |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 856 | def CMOVBE64rr: RI<0x46, MRMSrcReg, // if <=u, GR64 = GR64 |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 857 | (outs GR64:$dst), (ins GR64:$src1, GR64:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 858 | "cmovbe\t{$src2, $dst|$dst, $src2}", |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 859 | [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2, |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 860 | X86_COND_BE, EFLAGS))]>, TB; |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 861 | def CMOVA64rr : RI<0x47, MRMSrcReg, // if >u, GR64 = GR64 |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 862 | (outs GR64:$dst), (ins GR64:$src1, GR64:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 863 | "cmova\t{$src2, $dst|$dst, $src2}", |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 864 | [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2, |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 865 | X86_COND_A, EFLAGS))]>, TB; |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 866 | def CMOVL64rr : RI<0x4C, MRMSrcReg, // if <s, GR64 = GR64 |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 867 | (outs GR64:$dst), (ins GR64:$src1, GR64:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 868 | "cmovl\t{$src2, $dst|$dst, $src2}", |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 869 | [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2, |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 870 | X86_COND_L, EFLAGS))]>, TB; |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 871 | def CMOVGE64rr: RI<0x4D, MRMSrcReg, // if >=s, GR64 = GR64 |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 872 | (outs GR64:$dst), (ins GR64:$src1, GR64:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 873 | "cmovge\t{$src2, $dst|$dst, $src2}", |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 874 | [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2, |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 875 | X86_COND_GE, EFLAGS))]>, TB; |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 876 | def CMOVLE64rr: RI<0x4E, MRMSrcReg, // if <=s, GR64 = GR64 |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 877 | (outs GR64:$dst), (ins GR64:$src1, GR64:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 878 | "cmovle\t{$src2, $dst|$dst, $src2}", |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 879 | [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2, |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 880 | X86_COND_LE, EFLAGS))]>, TB; |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 881 | def CMOVG64rr : RI<0x4F, MRMSrcReg, // if >s, GR64 = GR64 |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 882 | (outs GR64:$dst), (ins GR64:$src1, GR64:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 883 | "cmovg\t{$src2, $dst|$dst, $src2}", |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 884 | [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2, |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 885 | X86_COND_G, EFLAGS))]>, TB; |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 886 | def CMOVS64rr : RI<0x48, MRMSrcReg, // if signed, GR64 = GR64 |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 887 | (outs GR64:$dst), (ins GR64:$src1, GR64:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 888 | "cmovs\t{$src2, $dst|$dst, $src2}", |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 889 | [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2, |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 890 | X86_COND_S, EFLAGS))]>, TB; |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 891 | def CMOVNS64rr: RI<0x49, MRMSrcReg, // if !signed, GR64 = GR64 |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 892 | (outs GR64:$dst), (ins GR64:$src1, GR64:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 893 | "cmovns\t{$src2, $dst|$dst, $src2}", |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 894 | [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2, |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 895 | X86_COND_NS, EFLAGS))]>, TB; |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 896 | def CMOVP64rr : RI<0x4A, MRMSrcReg, // if parity, GR64 = GR64 |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 897 | (outs GR64:$dst), (ins GR64:$src1, GR64:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 898 | "cmovp\t{$src2, $dst|$dst, $src2}", |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 899 | [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2, |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 900 | X86_COND_P, EFLAGS))]>, TB; |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 901 | def CMOVNP64rr : RI<0x4B, MRMSrcReg, // if !parity, GR64 = GR64 |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 902 | (outs GR64:$dst), (ins GR64:$src1, GR64:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 903 | "cmovnp\t{$src2, $dst|$dst, $src2}", |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 904 | [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2, |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 905 | X86_COND_NP, EFLAGS))]>, TB; |
Evan Cheng | 7ad42d9 | 2007-10-05 23:13:21 +0000 | [diff] [blame] | 906 | } // isCommutable = 1 |
| 907 | |
| 908 | def CMOVB64rm : RI<0x42, MRMSrcMem, // if <u, GR64 = [mem64] |
| 909 | (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2), |
| 910 | "cmovb\t{$src2, $dst|$dst, $src2}", |
| 911 | [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2), |
| 912 | X86_COND_B, EFLAGS))]>, TB; |
| 913 | def CMOVAE64rm: RI<0x43, MRMSrcMem, // if >=u, GR64 = [mem64] |
| 914 | (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2), |
| 915 | "cmovae\t{$src2, $dst|$dst, $src2}", |
| 916 | [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2), |
| 917 | X86_COND_AE, EFLAGS))]>, TB; |
| 918 | def CMOVE64rm : RI<0x44, MRMSrcMem, // if ==, GR64 = [mem64] |
| 919 | (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2), |
| 920 | "cmove\t{$src2, $dst|$dst, $src2}", |
| 921 | [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2), |
| 922 | X86_COND_E, EFLAGS))]>, TB; |
| 923 | def CMOVNE64rm: RI<0x45, MRMSrcMem, // if !=, GR64 = [mem64] |
| 924 | (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2), |
| 925 | "cmovne\t{$src2, $dst|$dst, $src2}", |
| 926 | [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2), |
| 927 | X86_COND_NE, EFLAGS))]>, TB; |
| 928 | def CMOVBE64rm: RI<0x46, MRMSrcMem, // if <=u, GR64 = [mem64] |
| 929 | (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2), |
| 930 | "cmovbe\t{$src2, $dst|$dst, $src2}", |
| 931 | [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2), |
| 932 | X86_COND_BE, EFLAGS))]>, TB; |
| 933 | def CMOVA64rm : RI<0x47, MRMSrcMem, // if >u, GR64 = [mem64] |
| 934 | (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2), |
| 935 | "cmova\t{$src2, $dst|$dst, $src2}", |
| 936 | [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2), |
| 937 | X86_COND_A, EFLAGS))]>, TB; |
| 938 | def CMOVL64rm : RI<0x4C, MRMSrcMem, // if <s, GR64 = [mem64] |
| 939 | (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2), |
| 940 | "cmovl\t{$src2, $dst|$dst, $src2}", |
| 941 | [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2), |
| 942 | X86_COND_L, EFLAGS))]>, TB; |
| 943 | def CMOVGE64rm: RI<0x4D, MRMSrcMem, // if >=s, GR64 = [mem64] |
| 944 | (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2), |
| 945 | "cmovge\t{$src2, $dst|$dst, $src2}", |
| 946 | [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2), |
| 947 | X86_COND_GE, EFLAGS))]>, TB; |
| 948 | def CMOVLE64rm: RI<0x4E, MRMSrcMem, // if <=s, GR64 = [mem64] |
| 949 | (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2), |
| 950 | "cmovle\t{$src2, $dst|$dst, $src2}", |
| 951 | [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2), |
| 952 | X86_COND_LE, EFLAGS))]>, TB; |
| 953 | def CMOVG64rm : RI<0x4F, MRMSrcMem, // if >s, GR64 = [mem64] |
| 954 | (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2), |
| 955 | "cmovg\t{$src2, $dst|$dst, $src2}", |
| 956 | [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2), |
| 957 | X86_COND_G, EFLAGS))]>, TB; |
| 958 | def CMOVS64rm : RI<0x48, MRMSrcMem, // if signed, GR64 = [mem64] |
| 959 | (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2), |
| 960 | "cmovs\t{$src2, $dst|$dst, $src2}", |
| 961 | [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2), |
| 962 | X86_COND_S, EFLAGS))]>, TB; |
| 963 | def CMOVNS64rm: RI<0x49, MRMSrcMem, // if !signed, GR64 = [mem64] |
| 964 | (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2), |
| 965 | "cmovns\t{$src2, $dst|$dst, $src2}", |
| 966 | [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2), |
| 967 | X86_COND_NS, EFLAGS))]>, TB; |
| 968 | def CMOVP64rm : RI<0x4A, MRMSrcMem, // if parity, GR64 = [mem64] |
| 969 | (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2), |
| 970 | "cmovp\t{$src2, $dst|$dst, $src2}", |
| 971 | [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2), |
| 972 | X86_COND_P, EFLAGS))]>, TB; |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 973 | def CMOVNP64rm : RI<0x4B, MRMSrcMem, // if !parity, GR64 = [mem64] |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 974 | (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 975 | "cmovnp\t{$src2, $dst|$dst, $src2}", |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 976 | [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2), |
Evan Cheng | 0488db9 | 2007-09-25 01:57:46 +0000 | [diff] [blame] | 977 | X86_COND_NP, EFLAGS))]>, TB; |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 978 | } // isTwoAddress |
| 979 | |
| 980 | //===----------------------------------------------------------------------===// |
| 981 | // Conversion Instructions... |
| 982 | // |
| 983 | |
| 984 | // f64 -> signed i64 |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 985 | def Int_CVTSD2SI64rr: RSDI<0x2D, MRMSrcReg, (outs GR64:$dst), (ins VR128:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 986 | "cvtsd2si{q}\t{$src, $dst|$dst, $src}", |
Bill Wendling | 6a20cf0 | 2007-07-23 03:07:27 +0000 | [diff] [blame] | 987 | [(set GR64:$dst, |
| 988 | (int_x86_sse2_cvtsd2si64 VR128:$src))]>; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 989 | def Int_CVTSD2SI64rm: RSDI<0x2D, MRMSrcMem, (outs GR64:$dst), (ins f128mem:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 990 | "cvtsd2si{q}\t{$src, $dst|$dst, $src}", |
Bill Wendling | 6a20cf0 | 2007-07-23 03:07:27 +0000 | [diff] [blame] | 991 | [(set GR64:$dst, (int_x86_sse2_cvtsd2si64 |
| 992 | (load addr:$src)))]>; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 993 | def CVTTSD2SI64rr: RSDI<0x2C, MRMSrcReg, (outs GR64:$dst), (ins FR64:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 994 | "cvttsd2si{q}\t{$src, $dst|$dst, $src}", |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 995 | [(set GR64:$dst, (fp_to_sint FR64:$src))]>; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 996 | def CVTTSD2SI64rm: RSDI<0x2C, MRMSrcMem, (outs GR64:$dst), (ins f64mem:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 997 | "cvttsd2si{q}\t{$src, $dst|$dst, $src}", |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 998 | [(set GR64:$dst, (fp_to_sint (loadf64 addr:$src)))]>; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 999 | def Int_CVTTSD2SI64rr: RSDI<0x2C, MRMSrcReg, (outs GR64:$dst), (ins VR128:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1000 | "cvttsd2si{q}\t{$src, $dst|$dst, $src}", |
Bill Wendling | 6a20cf0 | 2007-07-23 03:07:27 +0000 | [diff] [blame] | 1001 | [(set GR64:$dst, |
| 1002 | (int_x86_sse2_cvttsd2si64 VR128:$src))]>; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1003 | def Int_CVTTSD2SI64rm: RSDI<0x2C, MRMSrcMem, (outs GR64:$dst), (ins f128mem:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1004 | "cvttsd2si{q}\t{$src, $dst|$dst, $src}", |
Bill Wendling | 6a20cf0 | 2007-07-23 03:07:27 +0000 | [diff] [blame] | 1005 | [(set GR64:$dst, |
| 1006 | (int_x86_sse2_cvttsd2si64 |
| 1007 | (load addr:$src)))]>; |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 1008 | |
| 1009 | // Signed i64 -> f64 |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1010 | def CVTSI2SD64rr: RSDI<0x2A, MRMSrcReg, (outs FR64:$dst), (ins GR64:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1011 | "cvtsi2sd{q}\t{$src, $dst|$dst, $src}", |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 1012 | [(set FR64:$dst, (sint_to_fp GR64:$src))]>; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1013 | def CVTSI2SD64rm: RSDI<0x2A, MRMSrcMem, (outs FR64:$dst), (ins i64mem:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1014 | "cvtsi2sd{q}\t{$src, $dst|$dst, $src}", |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 1015 | [(set FR64:$dst, (sint_to_fp (loadi64 addr:$src)))]>; |
| 1016 | let isTwoAddress = 1 in { |
| 1017 | def Int_CVTSI2SD64rr: RSDI<0x2A, MRMSrcReg, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1018 | (outs VR128:$dst), (ins VR128:$src1, GR64:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1019 | "cvtsi2sd{q}\t{$src2, $dst|$dst, $src2}", |
Bill Wendling | 6a20cf0 | 2007-07-23 03:07:27 +0000 | [diff] [blame] | 1020 | [(set VR128:$dst, |
| 1021 | (int_x86_sse2_cvtsi642sd VR128:$src1, |
| 1022 | GR64:$src2))]>; |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 1023 | def Int_CVTSI2SD64rm: RSDI<0x2A, MRMSrcMem, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1024 | (outs VR128:$dst), (ins VR128:$src1, i64mem:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1025 | "cvtsi2sd{q}\t{$src2, $dst|$dst, $src2}", |
Bill Wendling | 6a20cf0 | 2007-07-23 03:07:27 +0000 | [diff] [blame] | 1026 | [(set VR128:$dst, |
| 1027 | (int_x86_sse2_cvtsi642sd VR128:$src1, |
| 1028 | (loadi64 addr:$src2)))]>; |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 1029 | } // isTwoAddress |
| 1030 | |
| 1031 | // Signed i64 -> f32 |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1032 | def CVTSI2SS64rr: RSSI<0x2A, MRMSrcReg, (outs FR32:$dst), (ins GR64:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1033 | "cvtsi2ss{q}\t{$src, $dst|$dst, $src}", |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 1034 | [(set FR32:$dst, (sint_to_fp GR64:$src))]>; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1035 | def CVTSI2SS64rm: RSSI<0x2A, MRMSrcMem, (outs FR32:$dst), (ins i64mem:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1036 | "cvtsi2ss{q}\t{$src, $dst|$dst, $src}", |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 1037 | [(set FR32:$dst, (sint_to_fp (loadi64 addr:$src)))]>; |
| 1038 | let isTwoAddress = 1 in { |
| 1039 | def Int_CVTSI2SS64rr: RSSI<0x2A, MRMSrcReg, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1040 | (outs VR128:$dst), (ins VR128:$src1, GR64:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1041 | "cvtsi2ss{q}\t{$src2, $dst|$dst, $src2}", |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 1042 | []>; // TODO: add intrinsic |
| 1043 | def Int_CVTSI2SS64rm: RSSI<0x2A, MRMSrcMem, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1044 | (outs VR128:$dst), (ins VR128:$src1, i64mem:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1045 | "cvtsi2ss{q}\t{$src2, $dst|$dst, $src2}", |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 1046 | []>; // TODO: add intrinsic |
| 1047 | } // isTwoAddress |
| 1048 | |
| 1049 | // f32 -> signed i64 |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1050 | def Int_CVTSS2SI64rr: RSSI<0x2D, MRMSrcReg, (outs GR64:$dst), (ins VR128:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1051 | "cvtss2si{q}\t{$src, $dst|$dst, $src}", |
Bill Wendling | 6a20cf0 | 2007-07-23 03:07:27 +0000 | [diff] [blame] | 1052 | [(set GR64:$dst, |
| 1053 | (int_x86_sse_cvtss2si64 VR128:$src))]>; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1054 | def Int_CVTSS2SI64rm: RSSI<0x2D, MRMSrcMem, (outs GR64:$dst), (ins f32mem:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1055 | "cvtss2si{q}\t{$src, $dst|$dst, $src}", |
Bill Wendling | 6a20cf0 | 2007-07-23 03:07:27 +0000 | [diff] [blame] | 1056 | [(set GR64:$dst, (int_x86_sse_cvtss2si64 |
| 1057 | (load addr:$src)))]>; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1058 | def CVTTSS2SI64rr: RSSI<0x2C, MRMSrcReg, (outs GR64:$dst), (ins FR32:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1059 | "cvttss2si{q}\t{$src, $dst|$dst, $src}", |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 1060 | [(set GR64:$dst, (fp_to_sint FR32:$src))]>; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1061 | def CVTTSS2SI64rm: RSSI<0x2C, MRMSrcMem, (outs GR64:$dst), (ins f32mem:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1062 | "cvttss2si{q}\t{$src, $dst|$dst, $src}", |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 1063 | [(set GR64:$dst, (fp_to_sint (loadf32 addr:$src)))]>; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1064 | def Int_CVTTSS2SI64rr: RSSI<0x2C, MRMSrcReg, (outs GR64:$dst), (ins VR128:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1065 | "cvttss2si{q}\t{$src, $dst|$dst, $src}", |
Bill Wendling | 6a20cf0 | 2007-07-23 03:07:27 +0000 | [diff] [blame] | 1066 | [(set GR64:$dst, |
| 1067 | (int_x86_sse_cvttss2si64 VR128:$src))]>; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1068 | def Int_CVTTSS2SI64rm: RSSI<0x2C, MRMSrcMem, (outs GR64:$dst), (ins f32mem:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1069 | "cvttss2si{q}\t{$src, $dst|$dst, $src}", |
Bill Wendling | 6a20cf0 | 2007-07-23 03:07:27 +0000 | [diff] [blame] | 1070 | [(set GR64:$dst, |
| 1071 | (int_x86_sse_cvttss2si64 (load addr:$src)))]>; |
| 1072 | |
| 1073 | let isTwoAddress = 1 in { |
| 1074 | def Int_CVTSI642SSrr : RSSI<0x2A, MRMSrcReg, |
| 1075 | (outs VR128:$dst), (ins VR128:$src1, GR64:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1076 | "cvtsi2ss{q}\t{$src2, $dst|$dst, $src2}", |
Bill Wendling | 6a20cf0 | 2007-07-23 03:07:27 +0000 | [diff] [blame] | 1077 | [(set VR128:$dst, |
| 1078 | (int_x86_sse_cvtsi642ss VR128:$src1, |
| 1079 | GR64:$src2))]>; |
| 1080 | def Int_CVTSI642SSrm : RSSI<0x2A, MRMSrcMem, |
| 1081 | (outs VR128:$dst), (ins VR128:$src1, i64mem:$src2), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1082 | "cvtsi2ss{q}\t{$src2, $dst|$dst, $src2}", |
Bill Wendling | 6a20cf0 | 2007-07-23 03:07:27 +0000 | [diff] [blame] | 1083 | [(set VR128:$dst, |
| 1084 | (int_x86_sse_cvtsi642ss VR128:$src1, |
| 1085 | (loadi64 addr:$src2)))]>; |
| 1086 | } |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 1087 | |
| 1088 | //===----------------------------------------------------------------------===// |
| 1089 | // Alias Instructions |
| 1090 | //===----------------------------------------------------------------------===// |
| 1091 | |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 1092 | // Zero-extension |
| 1093 | // TODO: Remove this after proper i32 -> i64 zext support. |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1094 | def PsMOVZX64rr32: I<0x89, MRMDestReg, (outs GR64:$dst), (ins GR32:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1095 | "mov{l}\t{$src, ${dst:subreg32}|${dst:subreg32}, $src}", |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 1096 | [(set GR64:$dst, (zext GR32:$src))]>; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1097 | def PsMOVZX64rm32: I<0x8B, MRMSrcMem, (outs GR64:$dst), (ins i32mem:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1098 | "mov{l}\t{$src, ${dst:subreg32}|${dst:subreg32}, $src}", |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 1099 | [(set GR64:$dst, (zextloadi64i32 addr:$src))]>; |
| 1100 | |
| 1101 | |
Dan Gohman | 9590624 | 2007-09-17 14:55:08 +0000 | [diff] [blame] | 1102 | // Alias instructions that map movr0 to xor. Use xorl instead of xorq; it's |
| 1103 | // equivalent due to implicit zero-extending, and it sometimes has a smaller |
| 1104 | // encoding. |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 1105 | // FIXME: remove when we can teach regalloc that xor reg, reg is ok. |
| 1106 | // FIXME: AddedComplexity gives MOV64r0 a higher priority than MOV64ri32. Remove |
| 1107 | // when we have a better way to specify isel priority. |
Bill Wendling | 627c00b | 2007-12-17 23:07:56 +0000 | [diff] [blame] | 1108 | let Defs = [EFLAGS], AddedComplexity = 1, isReMaterializable = 1, |
| 1109 | neverHasSideEffects = 1 in |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1110 | def MOV64r0 : RI<0x31, MRMInitReg, (outs GR64:$dst), (ins), |
Dan Gohman | 9590624 | 2007-09-17 14:55:08 +0000 | [diff] [blame] | 1111 | "xor{l}\t${dst:subreg32}, ${dst:subreg32}", |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 1112 | [(set GR64:$dst, 0)]>; |
| 1113 | |
| 1114 | // Materialize i64 constant where top 32-bits are zero. |
Bill Wendling | 627c00b | 2007-12-17 23:07:56 +0000 | [diff] [blame] | 1115 | let AddedComplexity = 1, isReMaterializable = 1, neverHasSideEffects = 1 in |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1116 | def MOV64ri64i32 : Ii32<0xB8, AddRegFrm, (outs GR64:$dst), (ins i64i32imm:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1117 | "mov{l}\t{$src, ${dst:subreg32}|${dst:subreg32}, $src}", |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 1118 | [(set GR64:$dst, i64immZExt32:$src)]>; |
| 1119 | |
| 1120 | //===----------------------------------------------------------------------===// |
| 1121 | // Non-Instruction Patterns |
| 1122 | //===----------------------------------------------------------------------===// |
| 1123 | |
Evan Cheng | 0085a28 | 2006-11-30 21:55:46 +0000 | [diff] [blame] | 1124 | // ConstantPool GlobalAddress, ExternalSymbol, and JumpTable |
| 1125 | def : Pat<(i64 (X86Wrapper tconstpool :$dst)), |
Evan Cheng | 0085a28 | 2006-11-30 21:55:46 +0000 | [diff] [blame] | 1126 | (MOV64ri tconstpool :$dst)>, Requires<[NotSmallCode]>; |
| 1127 | def : Pat<(i64 (X86Wrapper tjumptable :$dst)), |
| 1128 | (MOV64ri tjumptable :$dst)>, Requires<[NotSmallCode]>; |
| 1129 | def : Pat<(i64 (X86Wrapper tglobaladdr :$dst)), |
| 1130 | (MOV64ri tglobaladdr :$dst)>, Requires<[NotSmallCode]>; |
| 1131 | def : Pat<(i64 (X86Wrapper texternalsym:$dst)), |
| 1132 | (MOV64ri texternalsym:$dst)>, Requires<[NotSmallCode]>; |
| 1133 | |
Evan Cheng | 28b51439 | 2006-12-05 19:50:18 +0000 | [diff] [blame] | 1134 | def : Pat<(store (i64 (X86Wrapper tconstpool:$src)), addr:$dst), |
| 1135 | (MOV64mi32 addr:$dst, tconstpool:$src)>, |
Evan Cheng | 0db079e | 2007-08-01 23:46:10 +0000 | [diff] [blame] | 1136 | Requires<[SmallCode, HasLow4G, IsStatic]>; |
Evan Cheng | 28b51439 | 2006-12-05 19:50:18 +0000 | [diff] [blame] | 1137 | def : Pat<(store (i64 (X86Wrapper tjumptable:$src)), addr:$dst), |
| 1138 | (MOV64mi32 addr:$dst, tjumptable:$src)>, |
Evan Cheng | 0db079e | 2007-08-01 23:46:10 +0000 | [diff] [blame] | 1139 | Requires<[SmallCode, HasLow4G, IsStatic]>; |
Evan Cheng | 0085a28 | 2006-11-30 21:55:46 +0000 | [diff] [blame] | 1140 | def : Pat<(store (i64 (X86Wrapper tglobaladdr:$src)), addr:$dst), |
Evan Cheng | 28b51439 | 2006-12-05 19:50:18 +0000 | [diff] [blame] | 1141 | (MOV64mi32 addr:$dst, tglobaladdr:$src)>, |
Evan Cheng | 0db079e | 2007-08-01 23:46:10 +0000 | [diff] [blame] | 1142 | Requires<[SmallCode, HasLow4G, IsStatic]>; |
Evan Cheng | 0085a28 | 2006-11-30 21:55:46 +0000 | [diff] [blame] | 1143 | def : Pat<(store (i64 (X86Wrapper texternalsym:$src)), addr:$dst), |
Evan Cheng | 28b51439 | 2006-12-05 19:50:18 +0000 | [diff] [blame] | 1144 | (MOV64mi32 addr:$dst, texternalsym:$src)>, |
Evan Cheng | 0db079e | 2007-08-01 23:46:10 +0000 | [diff] [blame] | 1145 | Requires<[SmallCode, HasLow4G, IsStatic]>; |
Evan Cheng | 0085a28 | 2006-11-30 21:55:46 +0000 | [diff] [blame] | 1146 | |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 1147 | // Calls |
| 1148 | // Direct PC relative function call for small code model. 32-bit displacement |
| 1149 | // sign extended to 64-bit. |
| 1150 | def : Pat<(X86call (i64 tglobaladdr:$dst)), |
| 1151 | (CALL64pcrel32 tglobaladdr:$dst)>; |
| 1152 | def : Pat<(X86call (i64 texternalsym:$dst)), |
| 1153 | (CALL64pcrel32 texternalsym:$dst)>; |
| 1154 | |
| 1155 | def : Pat<(X86tailcall (i64 tglobaladdr:$dst)), |
| 1156 | (CALL64pcrel32 tglobaladdr:$dst)>; |
| 1157 | def : Pat<(X86tailcall (i64 texternalsym:$dst)), |
| 1158 | (CALL64pcrel32 texternalsym:$dst)>; |
| 1159 | |
| 1160 | def : Pat<(X86tailcall GR64:$dst), |
| 1161 | (CALL64r GR64:$dst)>; |
| 1162 | |
Arnold Schwaighofer | c85e171 | 2007-10-11 19:40:01 +0000 | [diff] [blame] | 1163 | |
| 1164 | // tailcall stuff |
| 1165 | def : Pat<(X86tailcall GR32:$dst), |
| 1166 | (TAILCALL)>; |
| 1167 | def : Pat<(X86tailcall (i64 tglobaladdr:$dst)), |
| 1168 | (TAILCALL)>; |
| 1169 | def : Pat<(X86tailcall (i64 texternalsym:$dst)), |
| 1170 | (TAILCALL)>; |
| 1171 | |
| 1172 | def : Pat<(X86tcret GR64:$dst, imm:$off), |
| 1173 | (TCRETURNri64 GR64:$dst, imm:$off)>; |
| 1174 | |
| 1175 | def : Pat<(X86tcret (i64 tglobaladdr:$dst), imm:$off), |
| 1176 | (TCRETURNdi64 texternalsym:$dst, imm:$off)>; |
| 1177 | |
| 1178 | def : Pat<(X86tcret (i64 texternalsym:$dst), imm:$off), |
| 1179 | (TCRETURNdi64 texternalsym:$dst, imm:$off)>; |
| 1180 | |
Dan Gohman | 11f7bfb | 2007-09-17 14:35:24 +0000 | [diff] [blame] | 1181 | // Comparisons. |
| 1182 | |
| 1183 | // TEST R,R is smaller than CMP R,0 |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 1184 | def : Pat<(parallel (X86cmp GR64:$src1, 0), (implicit EFLAGS)), |
Dan Gohman | 11f7bfb | 2007-09-17 14:35:24 +0000 | [diff] [blame] | 1185 | (TEST64rr GR64:$src1, GR64:$src1)>; |
| 1186 | |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 1187 | // {s|z}extload bool -> {s|z}extload byte |
| 1188 | def : Pat<(sextloadi64i1 addr:$src), (MOVSX64rm8 addr:$src)>; |
| 1189 | def : Pat<(zextloadi64i1 addr:$src), (MOVZX64rm8 addr:$src)>; |
| 1190 | |
| 1191 | // extload |
| 1192 | def : Pat<(extloadi64i1 addr:$src), (MOVZX64rm8 addr:$src)>; |
| 1193 | def : Pat<(extloadi64i8 addr:$src), (MOVZX64rm8 addr:$src)>; |
| 1194 | def : Pat<(extloadi64i16 addr:$src), (MOVZX64rm16 addr:$src)>; |
| 1195 | def : Pat<(extloadi64i32 addr:$src), (PsMOVZX64rm32 addr:$src)>; |
| 1196 | |
| 1197 | // anyext -> zext |
| 1198 | def : Pat<(i64 (anyext GR8 :$src)), (MOVZX64rr8 GR8 :$src)>; |
| 1199 | def : Pat<(i64 (anyext GR16:$src)), (MOVZX64rr16 GR16:$src)>; |
| 1200 | def : Pat<(i64 (anyext GR32:$src)), (PsMOVZX64rr32 GR32:$src)>; |
| 1201 | def : Pat<(i64 (anyext (loadi8 addr:$src))), (MOVZX64rm8 addr:$src)>; |
| 1202 | def : Pat<(i64 (anyext (loadi16 addr:$src))), (MOVZX64rm16 addr:$src)>; |
| 1203 | def : Pat<(i64 (anyext (loadi32 addr:$src))), (PsMOVZX64rm32 addr:$src)>; |
| 1204 | |
| 1205 | //===----------------------------------------------------------------------===// |
| 1206 | // Some peepholes |
| 1207 | //===----------------------------------------------------------------------===// |
| 1208 | |
| 1209 | // (shl x, 1) ==> (add x, x) |
| 1210 | def : Pat<(shl GR64:$src1, (i8 1)), (ADD64rr GR64:$src1, GR64:$src1)>; |
| 1211 | |
| 1212 | // (or (x >> c) | (y << (64 - c))) ==> (shrd64 x, y, c) |
| 1213 | def : Pat<(or (srl GR64:$src1, CL:$amt), |
| 1214 | (shl GR64:$src2, (sub 64, CL:$amt))), |
| 1215 | (SHRD64rrCL GR64:$src1, GR64:$src2)>; |
| 1216 | |
| 1217 | def : Pat<(store (or (srl (loadi64 addr:$dst), CL:$amt), |
| 1218 | (shl GR64:$src2, (sub 64, CL:$amt))), addr:$dst), |
| 1219 | (SHRD64mrCL addr:$dst, GR64:$src2)>; |
| 1220 | |
| 1221 | // (or (x << c) | (y >> (64 - c))) ==> (shld64 x, y, c) |
| 1222 | def : Pat<(or (shl GR64:$src1, CL:$amt), |
| 1223 | (srl GR64:$src2, (sub 64, CL:$amt))), |
| 1224 | (SHLD64rrCL GR64:$src1, GR64:$src2)>; |
| 1225 | |
| 1226 | def : Pat<(store (or (shl (loadi64 addr:$dst), CL:$amt), |
| 1227 | (srl GR64:$src2, (sub 64, CL:$amt))), addr:$dst), |
| 1228 | (SHLD64mrCL addr:$dst, GR64:$src2)>; |
Evan Cheng | ebf01d6 | 2006-11-16 23:33:25 +0000 | [diff] [blame] | 1229 | |
Chris Lattner | a066810 | 2007-05-17 06:35:11 +0000 | [diff] [blame] | 1230 | // X86 specific add which produces a flag. |
| 1231 | def : Pat<(addc GR64:$src1, GR64:$src2), |
| 1232 | (ADD64rr GR64:$src1, GR64:$src2)>; |
| 1233 | def : Pat<(addc GR64:$src1, (load addr:$src2)), |
| 1234 | (ADD64rm GR64:$src1, addr:$src2)>; |
| 1235 | def : Pat<(addc GR64:$src1, i64immSExt32:$src2), |
| 1236 | (ADD64ri32 GR64:$src1, imm:$src2)>; |
| 1237 | def : Pat<(addc GR64:$src1, i64immSExt8:$src2), |
| 1238 | (ADD64ri8 GR64:$src1, i64immSExt8:$src2)>; |
| 1239 | |
| 1240 | def : Pat<(subc GR64:$src1, GR64:$src2), |
| 1241 | (SUB64rr GR64:$src1, GR64:$src2)>; |
| 1242 | def : Pat<(subc GR64:$src1, (load addr:$src2)), |
| 1243 | (SUB64rm GR64:$src1, addr:$src2)>; |
| 1244 | def : Pat<(subc GR64:$src1, imm:$src2), |
| 1245 | (SUB64ri32 GR64:$src1, i64immSExt32:$src2)>; |
| 1246 | def : Pat<(subc GR64:$src1, i64immSExt8:$src2), |
| 1247 | (SUB64ri8 GR64:$src1, i64immSExt8:$src2)>; |
| 1248 | |
| 1249 | |
Evan Cheng | ebf01d6 | 2006-11-16 23:33:25 +0000 | [diff] [blame] | 1250 | //===----------------------------------------------------------------------===// |
| 1251 | // X86-64 SSE Instructions |
| 1252 | //===----------------------------------------------------------------------===// |
| 1253 | |
| 1254 | // Move instructions... |
| 1255 | |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1256 | def MOV64toPQIrr : RPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1257 | "mov{d|q}\t{$src, $dst|$dst, $src}", |
Evan Cheng | ebf01d6 | 2006-11-16 23:33:25 +0000 | [diff] [blame] | 1258 | [(set VR128:$dst, |
| 1259 | (v2i64 (scalar_to_vector GR64:$src)))]>; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1260 | def MOVPQIto64rr : RPDI<0x7E, MRMDestReg, (outs GR64:$dst), (ins VR128:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1261 | "mov{d|q}\t{$src, $dst|$dst, $src}", |
Evan Cheng | ebf01d6 | 2006-11-16 23:33:25 +0000 | [diff] [blame] | 1262 | [(set GR64:$dst, (vector_extract (v2i64 VR128:$src), |
| 1263 | (iPTR 0)))]>; |
Evan Cheng | 21b7612 | 2006-12-14 21:55:39 +0000 | [diff] [blame] | 1264 | |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1265 | def MOV64toSDrr : RPDI<0x6E, MRMSrcReg, (outs FR64:$dst), (ins GR64:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1266 | "mov{d|q}\t{$src, $dst|$dst, $src}", |
Evan Cheng | 21b7612 | 2006-12-14 21:55:39 +0000 | [diff] [blame] | 1267 | [(set FR64:$dst, (bitconvert GR64:$src))]>; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1268 | def MOV64toSDrm : RPDI<0x6E, MRMSrcMem, (outs FR64:$dst), (ins i64mem:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1269 | "mov{d|q}\t{$src, $dst|$dst, $src}", |
Evan Cheng | 21b7612 | 2006-12-14 21:55:39 +0000 | [diff] [blame] | 1270 | [(set FR64:$dst, (bitconvert (loadi64 addr:$src)))]>; |
| 1271 | |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1272 | def MOVSDto64rr : RPDI<0x7E, MRMDestReg, (outs GR64:$dst), (ins FR64:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1273 | "mov{d|q}\t{$src, $dst|$dst, $src}", |
Evan Cheng | 21b7612 | 2006-12-14 21:55:39 +0000 | [diff] [blame] | 1274 | [(set GR64:$dst, (bitconvert FR64:$src))]>; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1275 | def MOVSDto64mr : RPDI<0x7E, MRMDestMem, (outs), (ins i64mem:$dst, FR64:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1276 | "mov{d|q}\t{$src, $dst|$dst, $src}", |
Evan Cheng | 21b7612 | 2006-12-14 21:55:39 +0000 | [diff] [blame] | 1277 | [(store (i64 (bitconvert FR64:$src)), addr:$dst)]>; |