blob: 46f177d4f5c67f36c396dd3d3e0d6946f7cd5c59 [file] [log] [blame]
Dan Gohmanf17a25c2007-07-18 16:29:46 +00001//===-- llvm/CodeGen/VirtRegMap.h - Virtual Register Map -*- C++ -*--------===//
2//
3// The LLVM Compiler Infrastructure
4//
Chris Lattner081ce942007-12-29 20:36:04 +00005// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
Dan Gohmanf17a25c2007-07-18 16:29:46 +00007//
8//===----------------------------------------------------------------------===//
9//
10// This file implements a virtual register map. This maps virtual registers to
11// physical registers and virtual registers to stack slots. It is created and
12// updated by a register allocator and then used by a machine code rewriter that
13// adds spill code and rewrites virtual into physical register references.
14//
15//===----------------------------------------------------------------------===//
16
17#ifndef LLVM_CODEGEN_VIRTREGMAP_H
18#define LLVM_CODEGEN_VIRTREGMAP_H
19
Dan Gohman1e57df32008-02-10 18:45:23 +000020#include "llvm/Target/TargetRegisterInfo.h"
Evan Cheng7b88cbc2008-04-11 17:53:36 +000021#include "llvm/ADT/BitVector.h"
Evan Chengcecc8222007-11-17 00:40:40 +000022#include "llvm/ADT/DenseMap.h"
Dan Gohmanf17a25c2007-07-18 16:29:46 +000023#include "llvm/ADT/IndexedMap.h"
Evan Chengda872532008-02-27 03:04:06 +000024#include "llvm/ADT/SmallPtrSet.h"
Dan Gohmanf17a25c2007-07-18 16:29:46 +000025#include "llvm/Support/Streams.h"
26#include <map>
27
28namespace llvm {
29 class MachineInstr;
David Greene44a3bfb2007-08-07 16:34:05 +000030 class MachineFunction;
Dan Gohmanf17a25c2007-07-18 16:29:46 +000031 class TargetInstrInfo;
32
33 class VirtRegMap {
34 public:
35 enum {
36 NO_PHYS_REG = 0,
37 NO_STACK_SLOT = (1L << 30)-1,
38 MAX_STACK_SLOT = (1L << 18)-1
39 };
40
41 enum ModRef { isRef = 1, isMod = 2, isModRef = 3 };
42 typedef std::multimap<MachineInstr*,
43 std::pair<unsigned, ModRef> > MI2VirtMapTy;
44
45 private:
46 const TargetInstrInfo &TII;
47
48 MachineFunction &MF;
49 /// Virt2PhysMap - This is a virtual to physical register
50 /// mapping. Each virtual register is required to have an entry in
51 /// it; even spilled virtual registers (the register mapped to a
52 /// spilled register is the temporary used to load it from the
53 /// stack).
54 IndexedMap<unsigned, VirtReg2IndexFunctor> Virt2PhysMap;
Evan Chengcecc8222007-11-17 00:40:40 +000055
Dan Gohmanf17a25c2007-07-18 16:29:46 +000056 /// Virt2StackSlotMap - This is virtual register to stack slot
57 /// mapping. Each spilled virtual register has an entry in it
58 /// which corresponds to the stack slot this register is spilled
59 /// at.
60 IndexedMap<int, VirtReg2IndexFunctor> Virt2StackSlotMap;
Evan Chengcecc8222007-11-17 00:40:40 +000061
Dan Gohman7d45f4d2008-03-12 20:50:04 +000062 /// Virt2ReMatIdMap - This is virtual register to rematerialization id
Evan Chengcecc8222007-11-17 00:40:40 +000063 /// mapping. Each spilled virtual register that should be remat'd has an
64 /// entry in it which corresponds to the remat id.
Evan Cheng1204d172007-08-13 23:45:17 +000065 IndexedMap<int, VirtReg2IndexFunctor> Virt2ReMatIdMap;
Evan Chengcecc8222007-11-17 00:40:40 +000066
67 /// Virt2SplitMap - This is virtual register to splitted virtual register
68 /// mapping.
69 IndexedMap<unsigned, VirtReg2IndexFunctor> Virt2SplitMap;
70
Evan Cheng6f522672007-12-05 09:51:10 +000071 /// Virt2SplitKillMap - This is splitted virtual register to its last use
Evan Chengd9731042007-12-05 10:24:35 +000072 /// (kill) index mapping.
73 IndexedMap<unsigned> Virt2SplitKillMap;
Evan Cheng6f522672007-12-05 09:51:10 +000074
Evan Chengcecc8222007-11-17 00:40:40 +000075 /// ReMatMap - This is virtual register to re-materialized instruction
76 /// mapping. Each virtual register whose definition is going to be
77 /// re-materialized has an entry in it.
78 IndexedMap<MachineInstr*, VirtReg2IndexFunctor> ReMatMap;
79
Dan Gohmanf17a25c2007-07-18 16:29:46 +000080 /// MI2VirtMap - This is MachineInstr to virtual register
81 /// mapping. In the case of memory spill code being folded into
82 /// instructions, we need to know which virtual register was
83 /// read/written by this instruction.
84 MI2VirtMapTy MI2VirtMap;
85
Evan Chengcecc8222007-11-17 00:40:40 +000086 /// SpillPt2VirtMap - This records the virtual registers which should
87 /// be spilled right after the MachineInstr due to live interval
88 /// splitting.
Evan Chenged17a892007-12-05 08:16:32 +000089 std::map<MachineInstr*, std::vector<std::pair<unsigned,bool> > >
90 SpillPt2VirtMap;
Dan Gohmanf17a25c2007-07-18 16:29:46 +000091
Evan Cheng96c61312007-11-29 01:06:25 +000092 /// RestorePt2VirtMap - This records the virtual registers which should
93 /// be restored right before the MachineInstr due to live interval
94 /// splitting.
95 std::map<MachineInstr*, std::vector<unsigned> > RestorePt2VirtMap;
96
Evan Cheng14cc83f2008-03-11 07:19:34 +000097 /// EmergencySpillMap - This records the physical registers that should
98 /// be spilled / restored around the MachineInstr since the register
99 /// allocator has run out of registers.
100 std::map<MachineInstr*, std::vector<unsigned> > EmergencySpillMap;
101
102 /// EmergencySpillSlots - This records emergency spill slots used to
103 /// spill physical registers when the register allocator runs out of
104 /// registers. Ideally only one stack slot is used per function per
105 /// register class.
106 std::map<const TargetRegisterClass*, int> EmergencySpillSlots;
107
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000108 /// ReMatId - Instead of assigning a stack slot to a to be rematerialized
109 /// virtual register, an unique id is being assigned. This keeps track of
110 /// the highest id used so far. Note, this starts at (1<<18) to avoid
111 /// conflicts with stack slot numbers.
112 int ReMatId;
113
Evan Chengda872532008-02-27 03:04:06 +0000114 /// LowSpillSlot, HighSpillSlot - Lowest and highest spill slot indexes.
115 int LowSpillSlot, HighSpillSlot;
116
117 /// SpillSlotToUsesMap - Records uses for each register spill slot.
118 SmallVector<SmallPtrSet<MachineInstr*, 4>, 8> SpillSlotToUsesMap;
119
Evan Cheng7b88cbc2008-04-11 17:53:36 +0000120 /// ImplicitDefed - One bit for each virtual register. If set it indicates
121 /// the register is implicitly defined.
122 BitVector ImplicitDefed;
123
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000124 VirtRegMap(const VirtRegMap&); // DO NOT IMPLEMENT
125 void operator=(const VirtRegMap&); // DO NOT IMPLEMENT
126
127 public:
Dan Gohman3a78bbf2007-08-02 21:21:54 +0000128 explicit VirtRegMap(MachineFunction &mf);
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000129
130 void grow();
131
132 /// @brief returns true if the specified virtual register is
133 /// mapped to a physical register
134 bool hasPhys(unsigned virtReg) const {
135 return getPhys(virtReg) != NO_PHYS_REG;
136 }
137
138 /// @brief returns the physical register mapped to the specified
139 /// virtual register
140 unsigned getPhys(unsigned virtReg) const {
Dan Gohman1e57df32008-02-10 18:45:23 +0000141 assert(TargetRegisterInfo::isVirtualRegister(virtReg));
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000142 return Virt2PhysMap[virtReg];
143 }
144
145 /// @brief creates a mapping for the specified virtual register to
146 /// the specified physical register
147 void assignVirt2Phys(unsigned virtReg, unsigned physReg) {
Dan Gohman1e57df32008-02-10 18:45:23 +0000148 assert(TargetRegisterInfo::isVirtualRegister(virtReg) &&
149 TargetRegisterInfo::isPhysicalRegister(physReg));
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000150 assert(Virt2PhysMap[virtReg] == NO_PHYS_REG &&
151 "attempt to assign physical register to already mapped "
152 "virtual register");
153 Virt2PhysMap[virtReg] = physReg;
154 }
155
156 /// @brief clears the specified virtual register's, physical
157 /// register mapping
158 void clearVirt(unsigned virtReg) {
Dan Gohman1e57df32008-02-10 18:45:23 +0000159 assert(TargetRegisterInfo::isVirtualRegister(virtReg));
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000160 assert(Virt2PhysMap[virtReg] != NO_PHYS_REG &&
161 "attempt to clear a not assigned virtual register");
162 Virt2PhysMap[virtReg] = NO_PHYS_REG;
163 }
164
165 /// @brief clears all virtual to physical register mappings
166 void clearAllVirt() {
167 Virt2PhysMap.clear();
168 grow();
169 }
170
Evan Chengcecc8222007-11-17 00:40:40 +0000171 /// @brief records virtReg is a split live interval from SReg.
172 void setIsSplitFromReg(unsigned virtReg, unsigned SReg) {
173 Virt2SplitMap[virtReg] = SReg;
174 }
175
176 /// @brief returns the live interval virtReg is split from.
177 unsigned getPreSplitReg(unsigned virtReg) {
178 return Virt2SplitMap[virtReg];
179 }
180
Dan Gohman7d45f4d2008-03-12 20:50:04 +0000181 /// @brief returns true if the specified virtual register is not
Evan Cheng1204d172007-08-13 23:45:17 +0000182 /// mapped to a stack slot or rematerialized.
183 bool isAssignedReg(unsigned virtReg) const {
Evan Chengcecc8222007-11-17 00:40:40 +0000184 if (getStackSlot(virtReg) == NO_STACK_SLOT &&
185 getReMatId(virtReg) == NO_STACK_SLOT)
186 return true;
187 // Split register can be assigned a physical register as well as a
188 // stack slot or remat id.
189 return (Virt2SplitMap[virtReg] && Virt2PhysMap[virtReg] != NO_PHYS_REG);
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000190 }
191
192 /// @brief returns the stack slot mapped to the specified virtual
193 /// register
194 int getStackSlot(unsigned virtReg) const {
Dan Gohman1e57df32008-02-10 18:45:23 +0000195 assert(TargetRegisterInfo::isVirtualRegister(virtReg));
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000196 return Virt2StackSlotMap[virtReg];
197 }
198
Evan Cheng1204d172007-08-13 23:45:17 +0000199 /// @brief returns the rematerialization id mapped to the specified virtual
200 /// register
201 int getReMatId(unsigned virtReg) const {
Dan Gohman1e57df32008-02-10 18:45:23 +0000202 assert(TargetRegisterInfo::isVirtualRegister(virtReg));
Evan Cheng1204d172007-08-13 23:45:17 +0000203 return Virt2ReMatIdMap[virtReg];
204 }
205
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000206 /// @brief create a mapping for the specifed virtual register to
207 /// the next available stack slot
208 int assignVirt2StackSlot(unsigned virtReg);
209 /// @brief create a mapping for the specified virtual register to
210 /// the specified stack slot
211 void assignVirt2StackSlot(unsigned virtReg, int frameIndex);
212
213 /// @brief assign an unique re-materialization id to the specified
214 /// virtual register.
215 int assignVirtReMatId(unsigned virtReg);
Evan Cheng1204d172007-08-13 23:45:17 +0000216 /// @brief assign an unique re-materialization id to the specified
217 /// virtual register.
218 void assignVirtReMatId(unsigned virtReg, int id);
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000219
220 /// @brief returns true if the specified virtual register is being
221 /// re-materialized.
222 bool isReMaterialized(unsigned virtReg) const {
Evan Cheng1204d172007-08-13 23:45:17 +0000223 return ReMatMap[virtReg] != NULL;
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000224 }
225
226 /// @brief returns the original machine instruction being re-issued
227 /// to re-materialize the specified virtual register.
Evan Cheng1204d172007-08-13 23:45:17 +0000228 MachineInstr *getReMaterializedMI(unsigned virtReg) const {
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000229 return ReMatMap[virtReg];
230 }
231
232 /// @brief records the specified virtual register will be
233 /// re-materialized and the original instruction which will be re-issed
Evan Cheng1204d172007-08-13 23:45:17 +0000234 /// for this purpose. If parameter all is true, then all uses of the
235 /// registers are rematerialized and it's safe to delete the definition.
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000236 void setVirtIsReMaterialized(unsigned virtReg, MachineInstr *def) {
237 ReMatMap[virtReg] = def;
238 }
239
Evan Cheng6f522672007-12-05 09:51:10 +0000240 /// @brief record the last use (kill) of a split virtual register.
Evan Chengd9731042007-12-05 10:24:35 +0000241 void addKillPoint(unsigned virtReg, unsigned index) {
242 Virt2SplitKillMap[virtReg] = index;
Evan Cheng6f522672007-12-05 09:51:10 +0000243 }
244
Evan Chengd9731042007-12-05 10:24:35 +0000245 unsigned getKillPoint(unsigned virtReg) const {
246 return Virt2SplitKillMap[virtReg];
247 }
248
249 /// @brief remove the last use (kill) of a split virtual register.
Evan Cheng6f522672007-12-05 09:51:10 +0000250 void removeKillPoint(unsigned virtReg) {
Evan Chengd9731042007-12-05 10:24:35 +0000251 Virt2SplitKillMap[virtReg] = 0;
Evan Cheng6f522672007-12-05 09:51:10 +0000252 }
253
Evan Cheng91e32d02007-11-28 01:28:46 +0000254 /// @brief returns true if the specified MachineInstr is a spill point.
255 bool isSpillPt(MachineInstr *Pt) const {
256 return SpillPt2VirtMap.find(Pt) != SpillPt2VirtMap.end();
257 }
258
Evan Chengcecc8222007-11-17 00:40:40 +0000259 /// @brief returns the virtual registers that should be spilled due to
260 /// splitting right after the specified MachineInstr.
Evan Chenged17a892007-12-05 08:16:32 +0000261 std::vector<std::pair<unsigned,bool> > &getSpillPtSpills(MachineInstr *Pt) {
Evan Chengcecc8222007-11-17 00:40:40 +0000262 return SpillPt2VirtMap[Pt];
263 }
264
265 /// @brief records the specified MachineInstr as a spill point for virtReg.
Evan Chenged17a892007-12-05 08:16:32 +0000266 void addSpillPoint(unsigned virtReg, bool isKill, MachineInstr *Pt) {
Evan Cheng91e32d02007-11-28 01:28:46 +0000267 if (SpillPt2VirtMap.find(Pt) != SpillPt2VirtMap.end())
Evan Chenged17a892007-12-05 08:16:32 +0000268 SpillPt2VirtMap[Pt].push_back(std::make_pair(virtReg, isKill));
Evan Cheng91e32d02007-11-28 01:28:46 +0000269 else {
Evan Chenged17a892007-12-05 08:16:32 +0000270 std::vector<std::pair<unsigned,bool> > Virts;
271 Virts.push_back(std::make_pair(virtReg, isKill));
Evan Cheng91e32d02007-11-28 01:28:46 +0000272 SpillPt2VirtMap.insert(std::make_pair(Pt, Virts));
273 }
Evan Chengcecc8222007-11-17 00:40:40 +0000274 }
275
Evan Cheng1eeb2ef2008-03-11 21:34:46 +0000276 /// @brief - transfer spill point information from one instruction to
277 /// another.
Evan Chengcecc8222007-11-17 00:40:40 +0000278 void transferSpillPts(MachineInstr *Old, MachineInstr *New) {
Evan Chenged17a892007-12-05 08:16:32 +0000279 std::map<MachineInstr*,std::vector<std::pair<unsigned,bool> > >::iterator
280 I = SpillPt2VirtMap.find(Old);
Evan Cheng91e32d02007-11-28 01:28:46 +0000281 if (I == SpillPt2VirtMap.end())
282 return;
283 while (!I->second.empty()) {
Evan Chenged17a892007-12-05 08:16:32 +0000284 unsigned virtReg = I->second.back().first;
285 bool isKill = I->second.back().second;
Evan Cheng91e32d02007-11-28 01:28:46 +0000286 I->second.pop_back();
Evan Chenged17a892007-12-05 08:16:32 +0000287 addSpillPoint(virtReg, isKill, New);
Evan Chengcecc8222007-11-17 00:40:40 +0000288 }
Evan Cheng91e32d02007-11-28 01:28:46 +0000289 SpillPt2VirtMap.erase(I);
Evan Chengcecc8222007-11-17 00:40:40 +0000290 }
291
Evan Cheng96c61312007-11-29 01:06:25 +0000292 /// @brief returns true if the specified MachineInstr is a restore point.
293 bool isRestorePt(MachineInstr *Pt) const {
294 return RestorePt2VirtMap.find(Pt) != RestorePt2VirtMap.end();
295 }
296
297 /// @brief returns the virtual registers that should be restoreed due to
298 /// splitting right after the specified MachineInstr.
299 std::vector<unsigned> &getRestorePtRestores(MachineInstr *Pt) {
300 return RestorePt2VirtMap[Pt];
301 }
302
303 /// @brief records the specified MachineInstr as a restore point for virtReg.
304 void addRestorePoint(unsigned virtReg, MachineInstr *Pt) {
305 if (RestorePt2VirtMap.find(Pt) != RestorePt2VirtMap.end())
306 RestorePt2VirtMap[Pt].push_back(virtReg);
307 else {
308 std::vector<unsigned> Virts;
309 Virts.push_back(virtReg);
310 RestorePt2VirtMap.insert(std::make_pair(Pt, Virts));
311 }
312 }
313
Evan Cheng14cc83f2008-03-11 07:19:34 +0000314 /// @brief - transfer restore point information from one instruction to
315 /// another.
Evan Cheng96c61312007-11-29 01:06:25 +0000316 void transferRestorePts(MachineInstr *Old, MachineInstr *New) {
317 std::map<MachineInstr*,std::vector<unsigned> >::iterator I =
318 RestorePt2VirtMap.find(Old);
319 if (I == RestorePt2VirtMap.end())
320 return;
321 while (!I->second.empty()) {
322 unsigned virtReg = I->second.back();
323 I->second.pop_back();
324 addRestorePoint(virtReg, New);
325 }
326 RestorePt2VirtMap.erase(I);
327 }
328
Evan Cheng14cc83f2008-03-11 07:19:34 +0000329 /// @brief records that the specified physical register must be spilled
330 /// around the specified machine instr.
331 void addEmergencySpill(unsigned PhysReg, MachineInstr *MI) {
332 if (EmergencySpillMap.find(MI) != EmergencySpillMap.end())
333 EmergencySpillMap[MI].push_back(PhysReg);
334 else {
335 std::vector<unsigned> PhysRegs;
336 PhysRegs.push_back(PhysReg);
337 EmergencySpillMap.insert(std::make_pair(MI, PhysRegs));
338 }
339 }
340
341 /// @brief returns true if one or more physical registers must be spilled
342 /// around the specified instruction.
343 bool hasEmergencySpills(MachineInstr *MI) const {
344 return EmergencySpillMap.find(MI) != EmergencySpillMap.end();
345 }
346
347 /// @brief returns the physical registers to be spilled and restored around
348 /// the instruction.
349 std::vector<unsigned> &getEmergencySpills(MachineInstr *MI) {
350 return EmergencySpillMap[MI];
351 }
352
Evan Cheng1eeb2ef2008-03-11 21:34:46 +0000353 /// @brief - transfer emergency spill information from one instruction to
354 /// another.
355 void transferEmergencySpills(MachineInstr *Old, MachineInstr *New) {
356 std::map<MachineInstr*,std::vector<unsigned> >::iterator I =
357 EmergencySpillMap.find(Old);
358 if (I == EmergencySpillMap.end())
359 return;
360 while (!I->second.empty()) {
361 unsigned virtReg = I->second.back();
362 I->second.pop_back();
363 addEmergencySpill(virtReg, New);
364 }
365 EmergencySpillMap.erase(I);
366 }
367
Evan Cheng14cc83f2008-03-11 07:19:34 +0000368 /// @brief return or get a emergency spill slot for the register class.
369 int getEmergencySpillSlot(const TargetRegisterClass *RC);
370
Evan Chengda872532008-02-27 03:04:06 +0000371 /// @brief Return lowest spill slot index.
372 int getLowSpillSlot() const {
373 return LowSpillSlot;
374 }
375
376 /// @brief Return highest spill slot index.
377 int getHighSpillSlot() const {
378 return HighSpillSlot;
379 }
380
381 /// @brief Records a spill slot use.
382 void addSpillSlotUse(int FrameIndex, MachineInstr *MI);
383
384 /// @brief Returns true if spill slot has been used.
385 bool isSpillSlotUsed(int FrameIndex) const {
386 assert(FrameIndex >= 0 && "Spill slot index should not be negative!");
387 return !SpillSlotToUsesMap[FrameIndex-LowSpillSlot].empty();
388 }
389
Evan Cheng7b88cbc2008-04-11 17:53:36 +0000390 /// @brief Mark the specified register as being implicitly defined.
391 void setIsImplicitlyDefined(unsigned VirtReg) {
392 ImplicitDefed.set(VirtReg-TargetRegisterInfo::FirstVirtualRegister);
393 }
394
395 /// @brief Returns true if the virtual register is implicitly defined.
396 bool isImplicitlyDefined(unsigned VirtReg) const {
397 return ImplicitDefed[VirtReg-TargetRegisterInfo::FirstVirtualRegister];
398 }
399
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000400 /// @brief Updates information about the specified virtual register's value
Evan Chengfd0bd3c2007-12-02 08:30:39 +0000401 /// folded into newMI machine instruction.
402 void virtFolded(unsigned VirtReg, MachineInstr *OldMI, MachineInstr *NewMI,
403 ModRef MRInfo);
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000404
Evan Chengf3255842007-10-13 02:50:24 +0000405 /// @brief Updates information about the specified virtual register's value
406 /// folded into the specified machine instruction.
407 void virtFolded(unsigned VirtReg, MachineInstr *MI, ModRef MRInfo);
408
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000409 /// @brief returns the virtual registers' values folded in memory
410 /// operands of this instruction
411 std::pair<MI2VirtMapTy::const_iterator, MI2VirtMapTy::const_iterator>
412 getFoldedVirts(MachineInstr* MI) const {
413 return MI2VirtMap.equal_range(MI);
414 }
415
Evan Cheng91e32d02007-11-28 01:28:46 +0000416 /// RemoveMachineInstrFromMaps - MI is being erased, remove it from the
417 /// the folded instruction map and spill point map.
Evan Chengda872532008-02-27 03:04:06 +0000418 void RemoveMachineInstrFromMaps(MachineInstr *MI);
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000419
420 void print(std::ostream &OS) const;
421 void print(std::ostream *OS) const { if (OS) print(*OS); }
422 void dump() const;
423 };
424
425 inline std::ostream *operator<<(std::ostream *OS, const VirtRegMap &VRM) {
426 VRM.print(OS);
427 return OS;
428 }
429 inline std::ostream &operator<<(std::ostream &OS, const VirtRegMap &VRM) {
430 VRM.print(OS);
431 return OS;
432 }
433
434 /// Spiller interface: Implementations of this interface assign spilled
435 /// virtual registers to stack slots, rewriting the code.
436 struct Spiller {
437 virtual ~Spiller();
438 virtual bool runOnMachineFunction(MachineFunction &MF,
439 VirtRegMap &VRM) = 0;
440 };
441
442 /// createSpiller - Create an return a spiller object, as specified on the
443 /// command line.
444 Spiller* createSpiller();
445
446} // End llvm namespace
447
448#endif