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Chris Lattnera3b8b5c2004-07-23 17:56:30 +00001//===-- LiveIntervalAnalysis.cpp - Live Interval Analysis -----------------===//
Alkis Evlogimenosff0cbe12003-11-20 03:32:25 +00002//
3// The LLVM Compiler Infrastructure
4//
Chris Lattner4ee451d2007-12-29 20:36:04 +00005// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
Alkis Evlogimenosff0cbe12003-11-20 03:32:25 +00007//
8//===----------------------------------------------------------------------===//
9//
10// This file implements the LiveInterval analysis pass which is used
11// by the Linear Scan Register allocator. This pass linearizes the
12// basic blocks of the function in DFS order and uses the
13// LiveVariables pass to conservatively compute live intervals for
14// each virtual and physical register.
15//
16//===----------------------------------------------------------------------===//
17
Jakob Stoklund Olesen4281e202012-01-07 07:39:47 +000018#define DEBUG_TYPE "regalloc"
Chris Lattner3c3fe462005-09-21 04:19:09 +000019#include "llvm/CodeGen/LiveIntervalAnalysis.h"
Chris Lattner015959e2004-05-01 21:24:39 +000020#include "llvm/Value.h"
Dan Gohman6d69ba82008-07-25 00:02:30 +000021#include "llvm/Analysis/AliasAnalysis.h"
Alkis Evlogimenosff0cbe12003-11-20 03:32:25 +000022#include "llvm/CodeGen/LiveVariables.h"
Alkis Evlogimenosff0cbe12003-11-20 03:32:25 +000023#include "llvm/CodeGen/MachineInstr.h"
Chris Lattner84bc5422007-12-31 04:13:23 +000024#include "llvm/CodeGen/MachineRegisterInfo.h"
Alkis Evlogimenosff0cbe12003-11-20 03:32:25 +000025#include "llvm/CodeGen/Passes.h"
Dan Gohman6f0d0242008-02-10 18:45:23 +000026#include "llvm/Target/TargetRegisterInfo.h"
Alkis Evlogimenosff0cbe12003-11-20 03:32:25 +000027#include "llvm/Target/TargetInstrInfo.h"
28#include "llvm/Target/TargetMachine.h"
Reid Spencer551ccae2004-09-01 22:55:40 +000029#include "llvm/Support/CommandLine.h"
30#include "llvm/Support/Debug.h"
Torok Edwin7d696d82009-07-11 13:10:19 +000031#include "llvm/Support/ErrorHandling.h"
32#include "llvm/Support/raw_ostream.h"
Andrew Trickd35576b2012-02-13 20:44:42 +000033#include "llvm/ADT/DenseSet.h"
Reid Spencer551ccae2004-09-01 22:55:40 +000034#include "llvm/ADT/Statistic.h"
35#include "llvm/ADT/STLExtras.h"
Alkis Evlogimenos20aa4742004-09-03 18:19:51 +000036#include <algorithm>
Lang Hamesf41538d2009-06-02 16:53:25 +000037#include <limits>
Jeff Cohen97af7512006-12-02 02:22:01 +000038#include <cmath>
Alkis Evlogimenosff0cbe12003-11-20 03:32:25 +000039using namespace llvm;
40
Dan Gohman844731a2008-05-13 00:00:25 +000041// Hidden options for help debugging.
Jakob Stoklund Olesen1b293202010-08-12 20:01:23 +000042static cl::opt<bool> DisableReMat("disable-rematerialization",
Dan Gohman844731a2008-05-13 00:00:25 +000043 cl::init(false), cl::Hidden);
Evan Cheng81a03822007-11-17 00:40:40 +000044
Evan Cheng752195e2009-09-14 21:33:42 +000045STATISTIC(numIntervals , "Number of original intervals");
Chris Lattnercd3245a2006-12-19 22:41:21 +000046
Devang Patel19974732007-05-03 01:11:54 +000047char LiveIntervals::ID = 0;
Owen Anderson2ab36d32010-10-12 19:48:12 +000048INITIALIZE_PASS_BEGIN(LiveIntervals, "liveintervals",
49 "Live Interval Analysis", false, false)
Andrew Trick8dd26252012-02-10 04:10:36 +000050INITIALIZE_AG_DEPENDENCY(AliasAnalysis)
Owen Anderson2ab36d32010-10-12 19:48:12 +000051INITIALIZE_PASS_DEPENDENCY(LiveVariables)
Andrew Trick8dd26252012-02-10 04:10:36 +000052INITIALIZE_PASS_DEPENDENCY(MachineDominatorTree)
Owen Anderson2ab36d32010-10-12 19:48:12 +000053INITIALIZE_PASS_DEPENDENCY(SlotIndexes)
Owen Anderson2ab36d32010-10-12 19:48:12 +000054INITIALIZE_PASS_END(LiveIntervals, "liveintervals",
Owen Andersonce665bd2010-10-07 22:25:06 +000055 "Live Interval Analysis", false, false)
Alkis Evlogimenosff0cbe12003-11-20 03:32:25 +000056
Chris Lattnerf7da2c72006-08-24 22:43:55 +000057void LiveIntervals::getAnalysisUsage(AnalysisUsage &AU) const {
Dan Gohman845012e2009-07-31 23:37:33 +000058 AU.setPreservesCFG();
Dan Gohman6d69ba82008-07-25 00:02:30 +000059 AU.addRequired<AliasAnalysis>();
60 AU.addPreserved<AliasAnalysis>();
Alkis Evlogimenos1a8ea012004-08-04 09:46:26 +000061 AU.addRequired<LiveVariables>();
Evan Cheng148341c2010-08-17 21:00:37 +000062 AU.addPreserved<LiveVariables>();
Andrew Trickd35576b2012-02-13 20:44:42 +000063 AU.addPreservedID(MachineLoopInfoID);
Bill Wendling67d65bb2008-01-04 20:54:55 +000064 AU.addPreservedID(MachineDominatorsID);
Lang Hames233a60e2009-11-03 23:52:08 +000065 AU.addPreserved<SlotIndexes>();
66 AU.addRequiredTransitive<SlotIndexes>();
Alkis Evlogimenos1a8ea012004-08-04 09:46:26 +000067 MachineFunctionPass::getAnalysisUsage(AU);
Alkis Evlogimenosff0cbe12003-11-20 03:32:25 +000068}
69
Chris Lattnerf7da2c72006-08-24 22:43:55 +000070void LiveIntervals::releaseMemory() {
Owen Anderson03857b22008-08-13 21:49:13 +000071 // Free the live intervals themselves.
Owen Anderson20e28392008-08-13 22:08:30 +000072 for (DenseMap<unsigned, LiveInterval*>::iterator I = r2iMap_.begin(),
Bob Wilsond6a6b3b2010-03-24 20:25:25 +000073 E = r2iMap_.end(); I != E; ++I)
Owen Anderson03857b22008-08-13 21:49:13 +000074 delete I->second;
Jakob Stoklund Olesen1b293202010-08-12 20:01:23 +000075
Alkis Evlogimenos1a8ea012004-08-04 09:46:26 +000076 r2iMap_.clear();
Jakob Stoklund Olesen3fd3a842012-02-08 17:33:45 +000077 RegMaskSlots.clear();
78 RegMaskBits.clear();
Jakob Stoklund Olesen34e85d02012-02-10 01:26:29 +000079 RegMaskBlocks.clear();
Lang Hamesffd13262009-07-09 03:57:02 +000080
Benjamin Kramerce9a20b2010-06-26 11:30:59 +000081 // Release VNInfo memory regions, VNInfo objects don't need to be dtor'd.
82 VNInfoAllocator.Reset();
Alkis Evlogimenos08cec002004-01-31 19:59:32 +000083}
84
Owen Anderson80b3ce62008-05-28 20:54:50 +000085/// runOnMachineFunction - Register allocate the whole function
86///
87bool LiveIntervals::runOnMachineFunction(MachineFunction &fn) {
88 mf_ = &fn;
89 mri_ = &mf_->getRegInfo();
90 tm_ = &fn.getTarget();
91 tri_ = tm_->getRegisterInfo();
92 tii_ = tm_->getInstrInfo();
Dan Gohman6d69ba82008-07-25 00:02:30 +000093 aa_ = &getAnalysis<AliasAnalysis>();
Owen Anderson80b3ce62008-05-28 20:54:50 +000094 lv_ = &getAnalysis<LiveVariables>();
Lang Hames233a60e2009-11-03 23:52:08 +000095 indexes_ = &getAnalysis<SlotIndexes>();
Owen Anderson80b3ce62008-05-28 20:54:50 +000096 allocatableRegs_ = tri_->getAllocatableSet(fn);
Lang Hames342c64c2012-02-14 18:51:53 +000097 reservedRegs_ = tri_->getReservedRegs(fn);
Owen Anderson80b3ce62008-05-28 20:54:50 +000098
Alkis Evlogimenos1a8ea012004-08-04 09:46:26 +000099 computeIntervals();
Alkis Evlogimenos843b1602004-02-15 10:24:21 +0000100
Alkis Evlogimenos1a8ea012004-08-04 09:46:26 +0000101 numIntervals += getNumIntervals();
102
Chris Lattner70ca3582004-09-30 15:59:17 +0000103 DEBUG(dump());
Alkis Evlogimenos1a8ea012004-08-04 09:46:26 +0000104 return true;
Alkis Evlogimenosff0cbe12003-11-20 03:32:25 +0000105}
106
Chris Lattner70ca3582004-09-30 15:59:17 +0000107/// print - Implement the dump method.
Chris Lattner45cfe542009-08-23 06:03:38 +0000108void LiveIntervals::print(raw_ostream &OS, const Module* ) const {
Chris Lattner705e07f2009-08-23 03:41:05 +0000109 OS << "********** INTERVALS **********\n";
Jakob Stoklund Olesenf658af52012-02-14 23:46:21 +0000110
111 // Dump the physregs.
112 for (unsigned Reg = 1, RegE = tri_->getNumRegs(); Reg != RegE; ++Reg)
113 if (const LiveInterval *LI = r2iMap_.lookup(Reg)) {
114 LI->print(OS, tri_);
115 OS << '\n';
116 }
117
118 // Dump the virtregs.
119 for (unsigned Reg = 0, RegE = mri_->getNumVirtRegs(); Reg != RegE; ++Reg)
120 if (const LiveInterval *LI =
121 r2iMap_.lookup(TargetRegisterInfo::index2VirtReg(Reg))) {
122 LI->print(OS, tri_);
123 OS << '\n';
124 }
Chris Lattner70ca3582004-09-30 15:59:17 +0000125
Evan Cheng752195e2009-09-14 21:33:42 +0000126 printInstrs(OS);
127}
128
129void LiveIntervals::printInstrs(raw_ostream &OS) const {
Chris Lattner705e07f2009-08-23 03:41:05 +0000130 OS << "********** MACHINEINSTRS **********\n";
Jakob Stoklund Olesenf4a1e1a2010-10-26 20:21:46 +0000131 mf_->print(OS, indexes_);
Chris Lattner70ca3582004-09-30 15:59:17 +0000132}
133
Evan Cheng752195e2009-09-14 21:33:42 +0000134void LiveIntervals::dumpInstrs() const {
David Greene8a342292010-01-04 22:49:02 +0000135 printInstrs(dbgs());
Evan Cheng752195e2009-09-14 21:33:42 +0000136}
137
Evan Chengafff40a2010-05-04 20:26:52 +0000138static
Evan Cheng37499432010-05-05 18:27:40 +0000139bool MultipleDefsBySameMI(const MachineInstr &MI, unsigned MOIdx) {
Evan Chengafff40a2010-05-04 20:26:52 +0000140 unsigned Reg = MI.getOperand(MOIdx).getReg();
141 for (unsigned i = MOIdx+1, e = MI.getNumOperands(); i < e; ++i) {
142 const MachineOperand &MO = MI.getOperand(i);
143 if (!MO.isReg())
144 continue;
145 if (MO.getReg() == Reg && MO.isDef()) {
146 assert(MI.getOperand(MOIdx).getSubReg() != MO.getSubReg() &&
147 MI.getOperand(MOIdx).getSubReg() &&
Jakob Stoklund Olesened2185e2010-07-06 23:26:25 +0000148 (MO.getSubReg() || MO.isImplicit()));
Evan Chengafff40a2010-05-04 20:26:52 +0000149 return true;
150 }
151 }
152 return false;
153}
154
Evan Cheng37499432010-05-05 18:27:40 +0000155/// isPartialRedef - Return true if the specified def at the specific index is
156/// partially re-defining the specified live interval. A common case of this is
Jakob Stoklund Olesen1b293202010-08-12 20:01:23 +0000157/// a definition of the sub-register.
Evan Cheng37499432010-05-05 18:27:40 +0000158bool LiveIntervals::isPartialRedef(SlotIndex MIIdx, MachineOperand &MO,
159 LiveInterval &interval) {
160 if (!MO.getSubReg() || MO.isEarlyClobber())
161 return false;
162
Jakob Stoklund Olesen2debd482011-11-13 20:45:27 +0000163 SlotIndex RedefIndex = MIIdx.getRegSlot();
Evan Cheng37499432010-05-05 18:27:40 +0000164 const LiveRange *OldLR =
Jakob Stoklund Olesen2debd482011-11-13 20:45:27 +0000165 interval.getLiveRangeContaining(RedefIndex.getRegSlot(true));
Lang Hames6e2968c2010-09-25 12:04:16 +0000166 MachineInstr *DefMI = getInstructionFromIndex(OldLR->valno->def);
167 if (DefMI != 0) {
Evan Cheng37499432010-05-05 18:27:40 +0000168 return DefMI->findRegisterDefOperandIdx(interval.reg) != -1;
169 }
170 return false;
171}
172
Chris Lattnerbe4f88a2006-08-22 18:19:46 +0000173void LiveIntervals::handleVirtualRegisterDef(MachineBasicBlock *mbb,
Alkis Evlogimenosff0cbe12003-11-20 03:32:25 +0000174 MachineBasicBlock::iterator mi,
Lang Hames233a60e2009-11-03 23:52:08 +0000175 SlotIndex MIIdx,
Lang Hames86511252009-09-04 20:41:11 +0000176 MachineOperand& MO,
Evan Chengef0732d2008-07-10 07:35:43 +0000177 unsigned MOIdx,
Chris Lattnerbe4f88a2006-08-22 18:19:46 +0000178 LiveInterval &interval) {
Jakob Stoklund Olesen43142682011-01-09 03:05:53 +0000179 DEBUG(dbgs() << "\t\tregister: " << PrintReg(interval.reg, tri_));
Evan Cheng419852c2008-04-03 16:39:43 +0000180
Alkis Evlogimenos70651572004-08-04 09:46:56 +0000181 // Virtual registers may be defined multiple times (due to phi
182 // elimination and 2-addr elimination). Much of what we do only has to be
183 // done once for the vreg. We use an empty interval to detect the first
Alkis Evlogimenos1a8ea012004-08-04 09:46:26 +0000184 // time we see a vreg.
Evan Chengd129d732009-07-17 19:43:40 +0000185 LiveVariables::VarInfo& vi = lv_->getVarInfo(interval.reg);
Alkis Evlogimenos1a8ea012004-08-04 09:46:26 +0000186 if (interval.empty()) {
187 // Get the Idx of the defining instructions.
Jakob Stoklund Olesend14614e2011-11-13 22:05:42 +0000188 SlotIndex defIndex = MIIdx.getRegSlot(MO.isEarlyClobber());
Jakob Stoklund Olesen63e6a482010-05-21 16:32:16 +0000189
190 // Make sure the first definition is not a partial redefinition. Add an
191 // <imp-def> of the full register.
Jakob Stoklund Olesenb0e1bc72011-10-05 16:51:21 +0000192 // FIXME: LiveIntervals shouldn't modify the code like this. Whoever
193 // created the machine instruction should annotate it with <undef> flags
194 // as needed. Then we can simply assert here. The REG_SEQUENCE lowering
195 // is the main suspect.
Jakob Stoklund Olesen7016cf62011-10-04 21:49:33 +0000196 if (MO.getSubReg()) {
Jakob Stoklund Olesen63e6a482010-05-21 16:32:16 +0000197 mi->addRegisterDefined(interval.reg);
Jakob Stoklund Olesen7016cf62011-10-04 21:49:33 +0000198 // Mark all defs of interval.reg on this instruction as reading <undef>.
199 for (unsigned i = MOIdx, e = mi->getNumOperands(); i != e; ++i) {
200 MachineOperand &MO2 = mi->getOperand(i);
201 if (MO2.isReg() && MO2.getReg() == interval.reg && MO2.getSubReg())
202 MO2.setIsUndef();
203 }
204 }
Jakob Stoklund Olesen63e6a482010-05-21 16:32:16 +0000205
Jakob Stoklund Olesen3b1088a2012-02-04 05:20:49 +0000206 VNInfo *ValNo = interval.getNextValue(defIndex, VNInfoAllocator);
Evan Cheng7ecb38b2007-08-29 20:45:00 +0000207 assert(ValNo->id == 0 && "First value in interval is not 0?");
Chris Lattner7ac2d312004-07-24 02:59:07 +0000208
Alkis Evlogimenos1a8ea012004-08-04 09:46:26 +0000209 // Loop over all of the blocks that the vreg is defined in. There are
210 // two cases we have to handle here. The most common case is a vreg
211 // whose lifetime is contained within a basic block. In this case there
212 // will be a single kill, in MBB, which comes after the definition.
213 if (vi.Kills.size() == 1 && vi.Kills[0]->getParent() == mbb) {
214 // FIXME: what about dead vars?
Lang Hames233a60e2009-11-03 23:52:08 +0000215 SlotIndex killIdx;
Alkis Evlogimenos1a8ea012004-08-04 09:46:26 +0000216 if (vi.Kills[0] != mi)
Jakob Stoklund Olesen2debd482011-11-13 20:45:27 +0000217 killIdx = getInstructionIndex(vi.Kills[0]).getRegSlot();
Alkis Evlogimenos1a8ea012004-08-04 09:46:26 +0000218 else
Jakob Stoklund Olesen2debd482011-11-13 20:45:27 +0000219 killIdx = defIndex.getDeadSlot();
Chris Lattner6097d132004-07-19 02:15:56 +0000220
Alkis Evlogimenos1a8ea012004-08-04 09:46:26 +0000221 // If the kill happens after the definition, we have an intra-block
222 // live range.
223 if (killIdx > defIndex) {
Jeffrey Yasskin493a3d02009-05-26 18:27:15 +0000224 assert(vi.AliveBlocks.empty() &&
Alkis Evlogimenos1a8ea012004-08-04 09:46:26 +0000225 "Shouldn't be alive across any blocks!");
Evan Cheng7ecb38b2007-08-29 20:45:00 +0000226 LiveRange LR(defIndex, killIdx, ValNo);
Alkis Evlogimenos1a8ea012004-08-04 09:46:26 +0000227 interval.addRange(LR);
David Greene8a342292010-01-04 22:49:02 +0000228 DEBUG(dbgs() << " +" << LR << "\n");
Alkis Evlogimenos1a8ea012004-08-04 09:46:26 +0000229 return;
230 }
Alkis Evlogimenosdd2cc652003-12-18 08:48:48 +0000231 }
Alkis Evlogimenosff0cbe12003-11-20 03:32:25 +0000232
Alkis Evlogimenos1a8ea012004-08-04 09:46:26 +0000233 // The other case we handle is when a virtual register lives to the end
234 // of the defining block, potentially live across some blocks, then is
235 // live into some number of blocks, but gets killed. Start by adding a
236 // range that goes from this definition to the end of the defining block.
Lang Hames74ab5ee2009-12-22 00:11:50 +0000237 LiveRange NewLR(defIndex, getMBBEndIdx(mbb), ValNo);
David Greene8a342292010-01-04 22:49:02 +0000238 DEBUG(dbgs() << " +" << NewLR);
Alkis Evlogimenos1a8ea012004-08-04 09:46:26 +0000239 interval.addRange(NewLR);
240
Jakob Stoklund Olesendcfe5f32010-02-23 22:43:58 +0000241 bool PHIJoin = lv_->isPHIJoin(interval.reg);
242
243 if (PHIJoin) {
244 // A phi join register is killed at the end of the MBB and revived as a new
245 // valno in the killing blocks.
246 assert(vi.AliveBlocks.empty() && "Phi join can't pass through blocks");
247 DEBUG(dbgs() << " phi-join");
Jakob Stoklund Olesendcfe5f32010-02-23 22:43:58 +0000248 ValNo->setHasPHIKill(true);
249 } else {
250 // Iterate over all of the blocks that the variable is completely
251 // live in, adding [insrtIndex(begin), instrIndex(end)+4) to the
252 // live interval.
253 for (SparseBitVector<>::iterator I = vi.AliveBlocks.begin(),
254 E = vi.AliveBlocks.end(); I != E; ++I) {
255 MachineBasicBlock *aliveBlock = mf_->getBlockNumbered(*I);
256 LiveRange LR(getMBBStartIdx(aliveBlock), getMBBEndIdx(aliveBlock), ValNo);
257 interval.addRange(LR);
258 DEBUG(dbgs() << " +" << LR);
259 }
Alkis Evlogimenos1a8ea012004-08-04 09:46:26 +0000260 }
261
262 // Finally, this virtual register is live from the start of any killing
263 // block to the 'use' slot of the killing instruction.
264 for (unsigned i = 0, e = vi.Kills.size(); i != e; ++i) {
265 MachineInstr *Kill = vi.Kills[i];
Jakob Stoklund Olesendcfe5f32010-02-23 22:43:58 +0000266 SlotIndex Start = getMBBStartIdx(Kill->getParent());
Jakob Stoklund Olesen2debd482011-11-13 20:45:27 +0000267 SlotIndex killIdx = getInstructionIndex(Kill).getRegSlot();
Jakob Stoklund Olesendcfe5f32010-02-23 22:43:58 +0000268
269 // Create interval with one of a NEW value number. Note that this value
270 // number isn't actually defined by an instruction, weird huh? :)
271 if (PHIJoin) {
Lang Hames6e2968c2010-09-25 12:04:16 +0000272 assert(getInstructionFromIndex(Start) == 0 &&
273 "PHI def index points at actual instruction.");
Jakob Stoklund Olesen3b1088a2012-02-04 05:20:49 +0000274 ValNo = interval.getNextValue(Start, VNInfoAllocator);
Jakob Stoklund Olesendcfe5f32010-02-23 22:43:58 +0000275 ValNo->setIsPHIDef(true);
276 }
277 LiveRange LR(Start, killIdx, ValNo);
Alkis Evlogimenos1a8ea012004-08-04 09:46:26 +0000278 interval.addRange(LR);
David Greene8a342292010-01-04 22:49:02 +0000279 DEBUG(dbgs() << " +" << LR);
Alkis Evlogimenos1a8ea012004-08-04 09:46:26 +0000280 }
281
282 } else {
Evan Cheng37499432010-05-05 18:27:40 +0000283 if (MultipleDefsBySameMI(*mi, MOIdx))
Nick Lewycky761fd4c2010-05-20 03:30:09 +0000284 // Multiple defs of the same virtual register by the same instruction.
285 // e.g. %reg1031:5<def>, %reg1031:6<def> = VLD1q16 %reg1024<kill>, ...
Evan Chengafff40a2010-05-04 20:26:52 +0000286 // This is likely due to elimination of REG_SEQUENCE instructions. Return
287 // here since there is nothing to do.
288 return;
289
Alkis Evlogimenos1a8ea012004-08-04 09:46:26 +0000290 // If this is the second time we see a virtual register definition, it
291 // must be due to phi elimination or two addr elimination. If this is
Evan Chengbf105c82006-11-03 03:04:46 +0000292 // the result of two address elimination, then the vreg is one of the
293 // def-and-use register operand.
Evan Cheng37499432010-05-05 18:27:40 +0000294
295 // It may also be partial redef like this:
Jakob Stoklund Olesen1b293202010-08-12 20:01:23 +0000296 // 80 %reg1041:6<def> = VSHRNv4i16 %reg1034<kill>, 12, pred:14, pred:%reg0
297 // 120 %reg1041:5<def> = VSHRNv4i16 %reg1039<kill>, 12, pred:14, pred:%reg0
Evan Cheng37499432010-05-05 18:27:40 +0000298 bool PartReDef = isPartialRedef(MIIdx, MO, interval);
299 if (PartReDef || mi->isRegTiedToUseOperand(MOIdx)) {
Alkis Evlogimenos1a8ea012004-08-04 09:46:26 +0000300 // If this is a two-address definition, then we have already processed
301 // the live range. The only problem is that we didn't realize there
302 // are actually two values in the live interval. Because of this we
303 // need to take the LiveRegion that defines this register and split it
304 // into two values.
Jakob Stoklund Olesend14614e2011-11-13 22:05:42 +0000305 SlotIndex RedefIndex = MIIdx.getRegSlot(MO.isEarlyClobber());
Alkis Evlogimenos1a8ea012004-08-04 09:46:26 +0000306
Lang Hames35f291d2009-09-12 03:34:03 +0000307 const LiveRange *OldLR =
Jakob Stoklund Olesen2debd482011-11-13 20:45:27 +0000308 interval.getLiveRangeContaining(RedefIndex.getRegSlot(true));
Evan Cheng7ecb38b2007-08-29 20:45:00 +0000309 VNInfo *OldValNo = OldLR->valno;
Jakob Stoklund Olesen2debd482011-11-13 20:45:27 +0000310 SlotIndex DefIndex = OldValNo->def.getRegSlot();
Evan Cheng4f8ff162007-08-11 00:59:19 +0000311
Jakob Stoklund Olesenc66d0f22010-06-16 21:29:40 +0000312 // Delete the previous value, which should be short and continuous,
Chris Lattnerbe4f88a2006-08-22 18:19:46 +0000313 // because the 2-addr copy must be in the same MBB as the redef.
Alkis Evlogimenos1a8ea012004-08-04 09:46:26 +0000314 interval.removeRange(DefIndex, RedefIndex);
Alkis Evlogimenos70651572004-08-04 09:46:56 +0000315
Chris Lattner91725b72006-08-31 05:54:43 +0000316 // The new value number (#1) is defined by the instruction we claimed
317 // defined value #0.
Lang Hames6e2968c2010-09-25 12:04:16 +0000318 VNInfo *ValNo = interval.createValueCopy(OldValNo, VNInfoAllocator);
Lang Hames857c4e02009-06-17 21:01:20 +0000319
Chris Lattner91725b72006-08-31 05:54:43 +0000320 // Value#0 is now defined by the 2-addr instruction.
Jakob Stoklund Olesen3b1088a2012-02-04 05:20:49 +0000321 OldValNo->def = RedefIndex;
Jakob Stoklund Olesen1b293202010-08-12 20:01:23 +0000322
Chris Lattnerbe4f88a2006-08-22 18:19:46 +0000323 // Add the new live interval which replaces the range for the input copy.
324 LiveRange LR(DefIndex, RedefIndex, ValNo);
David Greene8a342292010-01-04 22:49:02 +0000325 DEBUG(dbgs() << " replace range with " << LR);
Alkis Evlogimenos1a8ea012004-08-04 09:46:26 +0000326 interval.addRange(LR);
327
328 // If this redefinition is dead, we need to add a dummy unit live
329 // range covering the def slot.
Owen Anderson6b098de2008-06-25 23:39:39 +0000330 if (MO.isDead())
Jakob Stoklund Olesen2debd482011-11-13 20:45:27 +0000331 interval.addRange(LiveRange(RedefIndex, RedefIndex.getDeadSlot(),
Lang Hames233a60e2009-11-03 23:52:08 +0000332 OldValNo));
Alkis Evlogimenos1a8ea012004-08-04 09:46:26 +0000333
Bill Wendling8e6179f2009-08-22 20:18:03 +0000334 DEBUG({
David Greene8a342292010-01-04 22:49:02 +0000335 dbgs() << " RESULT: ";
336 interval.print(dbgs(), tri_);
Bill Wendling8e6179f2009-08-22 20:18:03 +0000337 });
Evan Cheng37499432010-05-05 18:27:40 +0000338 } else if (lv_->isPHIJoin(interval.reg)) {
Alkis Evlogimenos1a8ea012004-08-04 09:46:26 +0000339 // In the case of PHI elimination, each variable definition is only
340 // live until the end of the block. We've already taken care of the
341 // rest of the live range.
Jakob Stoklund Olesendcfe5f32010-02-23 22:43:58 +0000342
Jakob Stoklund Olesen2debd482011-11-13 20:45:27 +0000343 SlotIndex defIndex = MIIdx.getRegSlot();
Evan Chengfb112882009-03-23 08:01:15 +0000344 if (MO.isEarlyClobber())
Jakob Stoklund Olesen2debd482011-11-13 20:45:27 +0000345 defIndex = MIIdx.getRegSlot(true);
Evan Cheng752195e2009-09-14 21:33:42 +0000346
Jakob Stoklund Olesen3b1088a2012-02-04 05:20:49 +0000347 VNInfo *ValNo = interval.getNextValue(defIndex, VNInfoAllocator);
Jakob Stoklund Olesen1b293202010-08-12 20:01:23 +0000348
Lang Hames74ab5ee2009-12-22 00:11:50 +0000349 SlotIndex killIndex = getMBBEndIdx(mbb);
Evan Cheng7ecb38b2007-08-29 20:45:00 +0000350 LiveRange LR(defIndex, killIndex, ValNo);
Alkis Evlogimenos1a8ea012004-08-04 09:46:26 +0000351 interval.addRange(LR);
Lang Hames857c4e02009-06-17 21:01:20 +0000352 ValNo->setHasPHIKill(true);
Jakob Stoklund Olesendcfe5f32010-02-23 22:43:58 +0000353 DEBUG(dbgs() << " phi-join +" << LR);
Evan Cheng37499432010-05-05 18:27:40 +0000354 } else {
355 llvm_unreachable("Multiply defined register");
Alkis Evlogimenos1a8ea012004-08-04 09:46:26 +0000356 }
357 }
358
David Greene8a342292010-01-04 22:49:02 +0000359 DEBUG(dbgs() << '\n');
Alkis Evlogimenosff0cbe12003-11-20 03:32:25 +0000360}
361
Lang Hames342c64c2012-02-14 18:51:53 +0000362#ifndef NDEBUG
Lang Hamesaf8b34d2012-02-17 00:18:18 +0000363static bool isRegLiveIntoSuccessor(const MachineBasicBlock *MBB, unsigned Reg) {
Lang Hames342c64c2012-02-14 18:51:53 +0000364 for (MachineBasicBlock::const_succ_iterator SI = MBB->succ_begin(),
365 SE = MBB->succ_end();
366 SI != SE; ++SI) {
367 const MachineBasicBlock* succ = *SI;
368 if (succ->isLiveIn(Reg))
369 return true;
370 }
371 return false;
372}
373#endif
374
Chris Lattnerf35fef72004-07-23 21:24:19 +0000375void LiveIntervals::handlePhysicalRegisterDef(MachineBasicBlock *MBB,
Alkis Evlogimenosff0cbe12003-11-20 03:32:25 +0000376 MachineBasicBlock::iterator mi,
Lang Hames233a60e2009-11-03 23:52:08 +0000377 SlotIndex MIIdx,
Owen Anderson6b098de2008-06-25 23:39:39 +0000378 MachineOperand& MO,
Jakob Stoklund Olesen3b1088a2012-02-04 05:20:49 +0000379 LiveInterval &interval) {
Jakob Stoklund Olesen43142682011-01-09 03:05:53 +0000380 DEBUG(dbgs() << "\t\tregister: " << PrintReg(interval.reg, tri_));
Alkis Evlogimenos02ba13c2004-01-31 23:13:30 +0000381
Lang Hames233a60e2009-11-03 23:52:08 +0000382 SlotIndex baseIndex = MIIdx;
Jakob Stoklund Olesend14614e2011-11-13 22:05:42 +0000383 SlotIndex start = baseIndex.getRegSlot(MO.isEarlyClobber());
Lang Hames233a60e2009-11-03 23:52:08 +0000384 SlotIndex end = start;
Alkis Evlogimenosff0cbe12003-11-20 03:32:25 +0000385
Alkis Evlogimenos1a8ea012004-08-04 09:46:26 +0000386 // If it is not used after definition, it is considered dead at
387 // the instruction defining it. Hence its interval is:
388 // [defSlot(def), defSlot(def)+1)
Dale Johannesen39faac22009-09-20 00:36:41 +0000389 // For earlyclobbers, the defSlot was pushed back one; the extra
390 // advance below compensates.
Owen Anderson6b098de2008-06-25 23:39:39 +0000391 if (MO.isDead()) {
David Greene8a342292010-01-04 22:49:02 +0000392 DEBUG(dbgs() << " dead");
Jakob Stoklund Olesen2debd482011-11-13 20:45:27 +0000393 end = start.getDeadSlot();
Chris Lattnerab4b66d2005-08-23 22:51:41 +0000394 goto exit;
Alkis Evlogimenos1a8ea012004-08-04 09:46:26 +0000395 }
396
397 // If it is not dead on definition, it must be killed by a
398 // subsequent instruction. Hence its interval is:
399 // [defSlot(def), useSlot(kill)+1)
Lang Hames233a60e2009-11-03 23:52:08 +0000400 baseIndex = baseIndex.getNextIndex();
Chris Lattner5ab6f5f2005-09-02 00:20:32 +0000401 while (++mi != MBB->end()) {
Lang Hames233a60e2009-11-03 23:52:08 +0000402
Dale Johannesenbd635202010-02-10 00:55:42 +0000403 if (mi->isDebugValue())
404 continue;
Lang Hames233a60e2009-11-03 23:52:08 +0000405 if (getInstructionFromIndex(baseIndex) == 0)
406 baseIndex = indexes_->getNextNonNullIndex(baseIndex);
407
Evan Cheng6130f662008-03-05 00:59:57 +0000408 if (mi->killsRegister(interval.reg, tri_)) {
David Greene8a342292010-01-04 22:49:02 +0000409 DEBUG(dbgs() << " killed");
Jakob Stoklund Olesen2debd482011-11-13 20:45:27 +0000410 end = baseIndex.getRegSlot();
Chris Lattnerab4b66d2005-08-23 22:51:41 +0000411 goto exit;
Evan Chengc45288e2009-04-27 20:42:46 +0000412 } else {
Evan Cheng1015ba72010-05-21 20:53:24 +0000413 int DefIdx = mi->findRegisterDefOperandIdx(interval.reg,false,false,tri_);
Evan Chengc45288e2009-04-27 20:42:46 +0000414 if (DefIdx != -1) {
415 if (mi->isRegTiedToUseOperand(DefIdx)) {
416 // Two-address instruction.
Jakob Stoklund Olesen7e899cb2012-02-04 05:41:20 +0000417 end = baseIndex.getRegSlot(mi->getOperand(DefIdx).isEarlyClobber());
Evan Chengc45288e2009-04-27 20:42:46 +0000418 } else {
419 // Another instruction redefines the register before it is ever read.
Dale Johannesenbd635202010-02-10 00:55:42 +0000420 // Then the register is essentially dead at the instruction that
421 // defines it. Hence its interval is:
Evan Chengc45288e2009-04-27 20:42:46 +0000422 // [defSlot(def), defSlot(def)+1)
David Greene8a342292010-01-04 22:49:02 +0000423 DEBUG(dbgs() << " dead");
Jakob Stoklund Olesen2debd482011-11-13 20:45:27 +0000424 end = start.getDeadSlot();
Evan Chengc45288e2009-04-27 20:42:46 +0000425 }
426 goto exit;
427 }
Alkis Evlogimenosaf254732004-01-13 22:26:14 +0000428 }
Jakob Stoklund Olesen1b293202010-08-12 20:01:23 +0000429
Lang Hames233a60e2009-11-03 23:52:08 +0000430 baseIndex = baseIndex.getNextIndex();
Alkis Evlogimenos1a8ea012004-08-04 09:46:26 +0000431 }
Jakob Stoklund Olesen1b293202010-08-12 20:01:23 +0000432
Lang Hames342c64c2012-02-14 18:51:53 +0000433 // If we get here the register *should* be live out.
434 assert(!isAllocatable(interval.reg) && "Physregs shouldn't be live out!");
Alkis Evlogimenos02ba13c2004-01-31 23:13:30 +0000435
Lang Hames342c64c2012-02-14 18:51:53 +0000436 // FIXME: We need saner rules for reserved regs.
437 if (isReserved(interval.reg)) {
Lang Hames342c64c2012-02-14 18:51:53 +0000438 end = start.getDeadSlot();
439 } else {
440 // Unreserved, unallocable registers like EFLAGS can be live across basic
441 // block boundaries.
Lang Hamesaf8b34d2012-02-17 00:18:18 +0000442 assert(isRegLiveIntoSuccessor(MBB, interval.reg) &&
443 "Unreserved reg not live-out?");
Lang Hames342c64c2012-02-14 18:51:53 +0000444 end = getMBBEndIdx(MBB);
445 }
Alkis Evlogimenosff0cbe12003-11-20 03:32:25 +0000446exit:
Alkis Evlogimenos1a8ea012004-08-04 09:46:26 +0000447 assert(start < end && "did not find end of interval?");
Chris Lattnerf768bba2005-03-09 23:05:19 +0000448
Evan Cheng24a3cc42007-04-25 07:30:23 +0000449 // Already exists? Extend old live interval.
Jakob Stoklund Olesen31cc3ec2010-10-11 21:45:03 +0000450 VNInfo *ValNo = interval.getVNInfoAt(start);
451 bool Extend = ValNo != 0;
452 if (!Extend)
Jakob Stoklund Olesen3b1088a2012-02-04 05:20:49 +0000453 ValNo = interval.getNextValue(start, VNInfoAllocator);
Evan Cheng7ecb38b2007-08-29 20:45:00 +0000454 LiveRange LR(start, end, ValNo);
Alkis Evlogimenos1a8ea012004-08-04 09:46:26 +0000455 interval.addRange(LR);
David Greene8a342292010-01-04 22:49:02 +0000456 DEBUG(dbgs() << " +" << LR << '\n');
Alkis Evlogimenosff0cbe12003-11-20 03:32:25 +0000457}
458
Chris Lattnerf35fef72004-07-23 21:24:19 +0000459void LiveIntervals::handleRegisterDef(MachineBasicBlock *MBB,
460 MachineBasicBlock::iterator MI,
Lang Hames233a60e2009-11-03 23:52:08 +0000461 SlotIndex MIIdx,
Evan Chengef0732d2008-07-10 07:35:43 +0000462 MachineOperand& MO,
463 unsigned MOIdx) {
Owen Anderson6b098de2008-06-25 23:39:39 +0000464 if (TargetRegisterInfo::isVirtualRegister(MO.getReg()))
Evan Chengef0732d2008-07-10 07:35:43 +0000465 handleVirtualRegisterDef(MBB, MI, MIIdx, MO, MOIdx,
Owen Anderson6b098de2008-06-25 23:39:39 +0000466 getOrCreateInterval(MO.getReg()));
Jakob Stoklund Olesen3b1088a2012-02-04 05:20:49 +0000467 else
Evan Chengc45288e2009-04-27 20:42:46 +0000468 handlePhysicalRegisterDef(MBB, MI, MIIdx, MO,
Jakob Stoklund Olesen3b1088a2012-02-04 05:20:49 +0000469 getOrCreateInterval(MO.getReg()));
Alkis Evlogimenos4d46e1e2004-01-31 14:37:41 +0000470}
471
Evan Chengb371f452007-02-19 21:49:54 +0000472void LiveIntervals::handleLiveInRegister(MachineBasicBlock *MBB,
Lang Hames233a60e2009-11-03 23:52:08 +0000473 SlotIndex MIIdx,
Lang Hames4465b6f2012-02-10 03:19:36 +0000474 LiveInterval &interval) {
Lang Hames342c64c2012-02-14 18:51:53 +0000475 assert(TargetRegisterInfo::isPhysicalRegister(interval.reg) &&
476 "Only physical registers can be live in.");
477 assert((!isAllocatable(interval.reg) || MBB->getParent()->begin() ||
478 MBB->isLandingPad()) &&
479 "Allocatable live-ins only valid for entry blocks and landing pads.");
480
Jakob Stoklund Olesen43142682011-01-09 03:05:53 +0000481 DEBUG(dbgs() << "\t\tlivein register: " << PrintReg(interval.reg, tri_));
Evan Chengb371f452007-02-19 21:49:54 +0000482
483 // Look for kills, if it reaches a def before it's killed, then it shouldn't
484 // be considered a livein.
485 MachineBasicBlock::iterator mi = MBB->begin();
Evan Cheng4507f082010-03-16 21:51:27 +0000486 MachineBasicBlock::iterator E = MBB->end();
487 // Skip over DBG_VALUE at the start of the MBB.
488 if (mi != E && mi->isDebugValue()) {
489 while (++mi != E && mi->isDebugValue())
490 ;
491 if (mi == E)
492 // MBB is empty except for DBG_VALUE's.
493 return;
494 }
495
Lang Hames233a60e2009-11-03 23:52:08 +0000496 SlotIndex baseIndex = MIIdx;
497 SlotIndex start = baseIndex;
498 if (getInstructionFromIndex(baseIndex) == 0)
499 baseIndex = indexes_->getNextNonNullIndex(baseIndex);
500
501 SlotIndex end = baseIndex;
Evan Cheng0076c612009-03-05 03:34:26 +0000502 bool SeenDefUse = false;
Evan Chengb371f452007-02-19 21:49:54 +0000503
Dale Johannesenbd635202010-02-10 00:55:42 +0000504 while (mi != E) {
Dale Johannesen1d0aeab2010-02-10 01:31:26 +0000505 if (mi->killsRegister(interval.reg, tri_)) {
506 DEBUG(dbgs() << " killed");
Jakob Stoklund Olesen2debd482011-11-13 20:45:27 +0000507 end = baseIndex.getRegSlot();
Dale Johannesen1d0aeab2010-02-10 01:31:26 +0000508 SeenDefUse = true;
509 break;
Jakob Stoklund Olesen6b791382012-02-14 23:46:24 +0000510 } else if (mi->modifiesRegister(interval.reg, tri_)) {
Dale Johannesen1d0aeab2010-02-10 01:31:26 +0000511 // Another instruction redefines the register before it is ever read.
512 // Then the register is essentially dead at the instruction that defines
513 // it. Hence its interval is:
514 // [defSlot(def), defSlot(def)+1)
515 DEBUG(dbgs() << " dead");
Jakob Stoklund Olesen2debd482011-11-13 20:45:27 +0000516 end = start.getDeadSlot();
Dale Johannesen1d0aeab2010-02-10 01:31:26 +0000517 SeenDefUse = true;
518 break;
519 }
520
Evan Cheng4507f082010-03-16 21:51:27 +0000521 while (++mi != E && mi->isDebugValue())
522 // Skip over DBG_VALUE.
523 ;
524 if (mi != E)
Lang Hames233a60e2009-11-03 23:52:08 +0000525 baseIndex = indexes_->getNextNonNullIndex(baseIndex);
Evan Chengb371f452007-02-19 21:49:54 +0000526 }
527
Evan Cheng75611fb2007-06-27 01:16:36 +0000528 // Live-in register might not be used at all.
Evan Cheng0076c612009-03-05 03:34:26 +0000529 if (!SeenDefUse) {
Lang Hamesaf8b34d2012-02-17 00:18:18 +0000530 if (isAllocatable(interval.reg) ||
531 !isRegLiveIntoSuccessor(MBB, interval.reg)) {
532 // Allocatable registers are never live through.
533 // Non-allocatable registers that aren't live into any successors also
534 // aren't live through.
Lang Hames342c64c2012-02-14 18:51:53 +0000535 DEBUG(dbgs() << " dead");
Lang Hamesf58e37f2012-02-15 01:31:10 +0000536 return;
Lang Hames342c64c2012-02-14 18:51:53 +0000537 } else {
Lang Hamesaf8b34d2012-02-17 00:18:18 +0000538 // If we get here the register is non-allocatable and live into some
539 // successor. We'll conservatively assume it's live-through.
Lang Hames342c64c2012-02-14 18:51:53 +0000540 DEBUG(dbgs() << " live through");
541 end = getMBBEndIdx(MBB);
542 }
Evan Cheng24a3cc42007-04-25 07:30:23 +0000543 }
544
Lang Hames6e2968c2010-09-25 12:04:16 +0000545 SlotIndex defIdx = getMBBStartIdx(MBB);
546 assert(getInstructionFromIndex(defIdx) == 0 &&
547 "PHI def index points at actual instruction.");
Jakob Stoklund Olesen3b1088a2012-02-04 05:20:49 +0000548 VNInfo *vni = interval.getNextValue(defIdx, VNInfoAllocator);
Lang Hamesd21c3162009-06-18 22:01:47 +0000549 vni->setIsPHIDef(true);
550 LiveRange LR(start, end, vni);
Jakob Stoklund Olesen3de23e62009-11-07 01:58:40 +0000551
Jim Laskey9b25b8c2007-02-21 22:41:17 +0000552 interval.addRange(LR);
David Greene8a342292010-01-04 22:49:02 +0000553 DEBUG(dbgs() << " +" << LR << '\n');
Evan Chengb371f452007-02-19 21:49:54 +0000554}
555
Alkis Evlogimenosff0cbe12003-11-20 03:32:25 +0000556/// computeIntervals - computes the live intervals for virtual
Alkis Evlogimenos4d46e1e2004-01-31 14:37:41 +0000557/// registers. for some ordering of the machine instructions [1,N] a
Alkis Evlogimenos08cec002004-01-31 19:59:32 +0000558/// live interval is an interval [i, j) where 1 <= i <= j < N for
Alkis Evlogimenosff0cbe12003-11-20 03:32:25 +0000559/// which a variable is live
Jakob Stoklund Olesen1b293202010-08-12 20:01:23 +0000560void LiveIntervals::computeIntervals() {
David Greene8a342292010-01-04 22:49:02 +0000561 DEBUG(dbgs() << "********** COMPUTING LIVE INTERVALS **********\n"
Bill Wendling8e6179f2009-08-22 20:18:03 +0000562 << "********** Function: "
563 << ((Value*)mf_->getFunction())->getName() << '\n');
Evan Chengd129d732009-07-17 19:43:40 +0000564
Jakob Stoklund Olesen34e85d02012-02-10 01:26:29 +0000565 RegMaskBlocks.resize(mf_->getNumBlockIDs());
566
Evan Chengd129d732009-07-17 19:43:40 +0000567 SmallVector<unsigned, 8> UndefUses;
Chris Lattner428b92e2006-09-15 03:57:23 +0000568 for (MachineFunction::iterator MBBI = mf_->begin(), E = mf_->end();
569 MBBI != E; ++MBBI) {
570 MachineBasicBlock *MBB = MBBI;
Jakob Stoklund Olesen34e85d02012-02-10 01:26:29 +0000571 RegMaskBlocks[MBB->getNumber()].first = RegMaskSlots.size();
572
Evan Cheng00a99a32010-02-06 09:07:11 +0000573 if (MBB->empty())
574 continue;
575
Owen Anderson134eb732008-09-21 20:43:24 +0000576 // Track the index of the current machine instr.
Lang Hames233a60e2009-11-03 23:52:08 +0000577 SlotIndex MIIndex = getMBBStartIdx(MBB);
Bob Wilsonad98f792010-05-03 21:38:11 +0000578 DEBUG(dbgs() << "BB#" << MBB->getNumber()
579 << ":\t\t# derived from " << MBB->getName() << "\n");
Alkis Evlogimenos6b4edba2003-12-21 20:19:10 +0000580
Dan Gohmancb406c22007-10-03 19:26:29 +0000581 // Create intervals for live-ins to this BB first.
Dan Gohman81bf03e2010-04-13 16:57:55 +0000582 for (MachineBasicBlock::livein_iterator LI = MBB->livein_begin(),
Dan Gohmancb406c22007-10-03 19:26:29 +0000583 LE = MBB->livein_end(); LI != LE; ++LI) {
584 handleLiveInRegister(MBB, MIIndex, getOrCreateInterval(*LI));
Chris Lattnerdffb2e82006-09-04 18:27:40 +0000585 }
Jakob Stoklund Olesen1b293202010-08-12 20:01:23 +0000586
Owen Anderson99500ae2008-09-15 22:00:38 +0000587 // Skip over empty initial indices.
Lang Hames233a60e2009-11-03 23:52:08 +0000588 if (getInstructionFromIndex(MIIndex) == 0)
589 MIIndex = indexes_->getNextNonNullIndex(MIIndex);
Jakob Stoklund Olesen1b293202010-08-12 20:01:23 +0000590
Dale Johannesen1caedd02010-01-22 22:38:21 +0000591 for (MachineBasicBlock::iterator MI = MBB->begin(), miEnd = MBB->end();
592 MI != miEnd; ++MI) {
David Greene8a342292010-01-04 22:49:02 +0000593 DEBUG(dbgs() << MIIndex << "\t" << *MI);
Chris Lattner518bb532010-02-09 19:54:29 +0000594 if (MI->isDebugValue())
Dale Johannesen1caedd02010-01-22 22:38:21 +0000595 continue;
Jakob Stoklund Olesen3fd3a842012-02-08 17:33:45 +0000596 assert(indexes_->getInstructionFromIndex(MIIndex) == MI &&
597 "Lost SlotIndex synchronization");
Alkis Evlogimenosff0cbe12003-11-20 03:32:25 +0000598
Evan Cheng438f7bc2006-11-10 08:43:01 +0000599 // Handle defs.
Chris Lattner428b92e2006-09-15 03:57:23 +0000600 for (int i = MI->getNumOperands() - 1; i >= 0; --i) {
601 MachineOperand &MO = MI->getOperand(i);
Jakob Stoklund Olesen3fd3a842012-02-08 17:33:45 +0000602
603 // Collect register masks.
604 if (MO.isRegMask()) {
605 RegMaskSlots.push_back(MIIndex.getRegSlot());
606 RegMaskBits.push_back(MO.getRegMask());
607 continue;
608 }
609
Evan Chengd129d732009-07-17 19:43:40 +0000610 if (!MO.isReg() || !MO.getReg())
611 continue;
612
Alkis Evlogimenos1a8ea012004-08-04 09:46:26 +0000613 // handle register defs - build intervals
Evan Chengd129d732009-07-17 19:43:40 +0000614 if (MO.isDef())
Evan Chengef0732d2008-07-10 07:35:43 +0000615 handleRegisterDef(MBB, MI, MIIndex, MO, i);
Evan Chengd129d732009-07-17 19:43:40 +0000616 else if (MO.isUndef())
617 UndefUses.push_back(MO.getReg());
Alkis Evlogimenos1a8ea012004-08-04 09:46:26 +0000618 }
Jakob Stoklund Olesen1b293202010-08-12 20:01:23 +0000619
Lang Hames233a60e2009-11-03 23:52:08 +0000620 // Move to the next instr slot.
621 MIIndex = indexes_->getNextNonNullIndex(MIIndex);
Alkis Evlogimenosff0cbe12003-11-20 03:32:25 +0000622 }
Jakob Stoklund Olesen34e85d02012-02-10 01:26:29 +0000623
624 // Compute the number of register mask instructions in this block.
625 std::pair<unsigned, unsigned> &RMB = RegMaskBlocks[MBB->getNumber()];
626 RMB.second = RegMaskSlots.size() - RMB.first;;
Alkis Evlogimenos1a8ea012004-08-04 09:46:26 +0000627 }
Evan Chengd129d732009-07-17 19:43:40 +0000628
629 // Create empty intervals for registers defined by implicit_def's (except
630 // for those implicit_def that define values which are liveout of their
631 // blocks.
632 for (unsigned i = 0, e = UndefUses.size(); i != e; ++i) {
633 unsigned UndefReg = UndefUses[i];
634 (void)getOrCreateInterval(UndefReg);
635 }
Alkis Evlogimenosff0cbe12003-11-20 03:32:25 +0000636}
Alkis Evlogimenosb27ef242003-12-05 10:38:28 +0000637
Owen Anderson03857b22008-08-13 21:49:13 +0000638LiveInterval* LiveIntervals::createInterval(unsigned reg) {
Evan Cheng0a1fcce2009-02-08 11:04:35 +0000639 float Weight = TargetRegisterInfo::isPhysicalRegister(reg) ? HUGE_VALF : 0.0F;
Owen Anderson03857b22008-08-13 21:49:13 +0000640 return new LiveInterval(reg, Weight);
Alkis Evlogimenos9a8b4902004-04-09 18:07:57 +0000641}
Evan Chengf2fbca62007-11-12 06:35:08 +0000642
Evan Cheng0a1fcce2009-02-08 11:04:35 +0000643/// dupInterval - Duplicate a live interval. The caller is responsible for
644/// managing the allocated memory.
645LiveInterval* LiveIntervals::dupInterval(LiveInterval *li) {
646 LiveInterval *NewLI = createInterval(li->reg);
Evan Cheng90f95f82009-06-14 20:22:55 +0000647 NewLI->Copy(*li, mri_, getVNInfoAllocator());
Evan Cheng0a1fcce2009-02-08 11:04:35 +0000648 return NewLI;
649}
650
Jakob Stoklund Olesen11513e52011-02-08 00:03:05 +0000651/// shrinkToUses - After removing some uses of a register, shrink its live
652/// range to just the remaining uses. This method does not compute reaching
653/// defs for new uses, and it doesn't remove dead defs.
Jakob Stoklund Olesen6a3dbd32011-03-17 20:37:07 +0000654bool LiveIntervals::shrinkToUses(LiveInterval *li,
Jakob Stoklund Olesen0d8ccaa2011-03-07 23:29:10 +0000655 SmallVectorImpl<MachineInstr*> *dead) {
Jakob Stoklund Olesen11513e52011-02-08 00:03:05 +0000656 DEBUG(dbgs() << "Shrink: " << *li << '\n');
657 assert(TargetRegisterInfo::isVirtualRegister(li->reg)
Lang Hames567cdba2012-01-03 20:05:57 +0000658 && "Can only shrink virtual registers");
Jakob Stoklund Olesen11513e52011-02-08 00:03:05 +0000659 // Find all the values used, including PHI kills.
660 SmallVector<std::pair<SlotIndex, VNInfo*>, 16> WorkList;
661
Jakob Stoklund Olesen031432f2011-09-15 15:24:16 +0000662 // Blocks that have already been added to WorkList as live-out.
663 SmallPtrSet<MachineBasicBlock*, 16> LiveOut;
664
Jakob Stoklund Olesen11513e52011-02-08 00:03:05 +0000665 // Visit all instructions reading li->reg.
666 for (MachineRegisterInfo::reg_iterator I = mri_->reg_begin(li->reg);
667 MachineInstr *UseMI = I.skipInstruction();) {
668 if (UseMI->isDebugValue() || !UseMI->readsVirtualRegister(li->reg))
669 continue;
Jakob Stoklund Olesen6c9cc212011-11-13 23:53:25 +0000670 SlotIndex Idx = getInstructionIndex(UseMI).getRegSlot();
Jakob Stoklund Olesenf054e192011-11-14 18:45:38 +0000671 // Note: This intentionally picks up the wrong VNI in case of an EC redef.
672 // See below.
673 VNInfo *VNI = li->getVNInfoBefore(Idx);
Jakob Stoklund Olesen9ef931e2011-03-18 03:06:04 +0000674 if (!VNI) {
675 // This shouldn't happen: readsVirtualRegister returns true, but there is
676 // no live value. It is likely caused by a target getting <undef> flags
677 // wrong.
678 DEBUG(dbgs() << Idx << '\t' << *UseMI
679 << "Warning: Instr claims to read non-existent value in "
680 << *li << '\n');
681 continue;
682 }
Jakob Stoklund Olesenf054e192011-11-14 18:45:38 +0000683 // Special case: An early-clobber tied operand reads and writes the
684 // register one slot early. The getVNInfoBefore call above would have
685 // picked up the value defined by UseMI. Adjust the kill slot and value.
686 if (SlotIndex::isSameInstr(VNI->def, Idx)) {
687 Idx = VNI->def;
Jakob Stoklund Olesen6c9cc212011-11-13 23:53:25 +0000688 VNI = li->getVNInfoBefore(Idx);
Jakob Stoklund Olesen11513e52011-02-08 00:03:05 +0000689 assert(VNI && "Early-clobber tied value not available");
690 }
691 WorkList.push_back(std::make_pair(Idx, VNI));
692 }
693
694 // Create a new live interval with only minimal live segments per def.
695 LiveInterval NewLI(li->reg, 0);
696 for (LiveInterval::vni_iterator I = li->vni_begin(), E = li->vni_end();
697 I != E; ++I) {
698 VNInfo *VNI = *I;
699 if (VNI->isUnused())
700 continue;
Jakob Stoklund Olesen1f81e312011-11-13 22:42:13 +0000701 NewLI.addRange(LiveRange(VNI->def, VNI->def.getDeadSlot(), VNI));
Jakob Stoklund Olesen11513e52011-02-08 00:03:05 +0000702 }
703
Jakob Stoklund Olesene0ab2452011-03-02 00:33:03 +0000704 // Keep track of the PHIs that are in use.
705 SmallPtrSet<VNInfo*, 8> UsedPHIs;
706
Jakob Stoklund Olesen11513e52011-02-08 00:03:05 +0000707 // Extend intervals to reach all uses in WorkList.
708 while (!WorkList.empty()) {
709 SlotIndex Idx = WorkList.back().first;
710 VNInfo *VNI = WorkList.back().second;
711 WorkList.pop_back();
Jakob Stoklund Olesen6c9cc212011-11-13 23:53:25 +0000712 const MachineBasicBlock *MBB = getMBBFromIndex(Idx.getPrevSlot());
Jakob Stoklund Olesen11513e52011-02-08 00:03:05 +0000713 SlotIndex BlockStart = getMBBStartIdx(MBB);
Jakob Stoklund Olesene0ab2452011-03-02 00:33:03 +0000714
715 // Extend the live range for VNI to be live at Idx.
Jakob Stoklund Olesen6c9cc212011-11-13 23:53:25 +0000716 if (VNInfo *ExtVNI = NewLI.extendInBlock(BlockStart, Idx)) {
Nick Lewycky4b11a702011-03-02 01:43:30 +0000717 (void)ExtVNI;
Jakob Stoklund Olesene0ab2452011-03-02 00:33:03 +0000718 assert(ExtVNI == VNI && "Unexpected existing value number");
719 // Is this a PHIDef we haven't seen before?
Jakob Stoklund Olesenc29d9b32011-03-03 00:20:51 +0000720 if (!VNI->isPHIDef() || VNI->def != BlockStart || !UsedPHIs.insert(VNI))
Jakob Stoklund Olesene0ab2452011-03-02 00:33:03 +0000721 continue;
722 // The PHI is live, make sure the predecessors are live-out.
723 for (MachineBasicBlock::const_pred_iterator PI = MBB->pred_begin(),
724 PE = MBB->pred_end(); PI != PE; ++PI) {
Jakob Stoklund Olesen031432f2011-09-15 15:24:16 +0000725 if (!LiveOut.insert(*PI))
726 continue;
Jakob Stoklund Olesen6c9cc212011-11-13 23:53:25 +0000727 SlotIndex Stop = getMBBEndIdx(*PI);
Jakob Stoklund Olesene0ab2452011-03-02 00:33:03 +0000728 // A predecessor is not required to have a live-out value for a PHI.
Jakob Stoklund Olesen6c9cc212011-11-13 23:53:25 +0000729 if (VNInfo *PVNI = li->getVNInfoBefore(Stop))
Jakob Stoklund Olesene0ab2452011-03-02 00:33:03 +0000730 WorkList.push_back(std::make_pair(Stop, PVNI));
Jakob Stoklund Olesen11513e52011-02-08 00:03:05 +0000731 }
Jakob Stoklund Olesen11513e52011-02-08 00:03:05 +0000732 continue;
733 }
734
735 // VNI is live-in to MBB.
736 DEBUG(dbgs() << " live-in at " << BlockStart << '\n');
Jakob Stoklund Olesen6c9cc212011-11-13 23:53:25 +0000737 NewLI.addRange(LiveRange(BlockStart, Idx, VNI));
Jakob Stoklund Olesen11513e52011-02-08 00:03:05 +0000738
739 // Make sure VNI is live-out from the predecessors.
740 for (MachineBasicBlock::const_pred_iterator PI = MBB->pred_begin(),
741 PE = MBB->pred_end(); PI != PE; ++PI) {
Jakob Stoklund Olesen031432f2011-09-15 15:24:16 +0000742 if (!LiveOut.insert(*PI))
743 continue;
Jakob Stoklund Olesen6c9cc212011-11-13 23:53:25 +0000744 SlotIndex Stop = getMBBEndIdx(*PI);
745 assert(li->getVNInfoBefore(Stop) == VNI &&
746 "Wrong value out of predecessor");
Jakob Stoklund Olesen11513e52011-02-08 00:03:05 +0000747 WorkList.push_back(std::make_pair(Stop, VNI));
748 }
749 }
750
751 // Handle dead values.
Jakob Stoklund Olesen6a3dbd32011-03-17 20:37:07 +0000752 bool CanSeparate = false;
Jakob Stoklund Olesen11513e52011-02-08 00:03:05 +0000753 for (LiveInterval::vni_iterator I = li->vni_begin(), E = li->vni_end();
754 I != E; ++I) {
755 VNInfo *VNI = *I;
756 if (VNI->isUnused())
757 continue;
758 LiveInterval::iterator LII = NewLI.FindLiveRangeContaining(VNI->def);
759 assert(LII != NewLI.end() && "Missing live range for PHI");
Jakob Stoklund Olesen1f81e312011-11-13 22:42:13 +0000760 if (LII->end != VNI->def.getDeadSlot())
Jakob Stoklund Olesen11513e52011-02-08 00:03:05 +0000761 continue;
Jakob Stoklund Olesena4d34732011-03-02 00:33:01 +0000762 if (VNI->isPHIDef()) {
Jakob Stoklund Olesen11513e52011-02-08 00:03:05 +0000763 // This is a dead PHI. Remove it.
764 VNI->setIsUnused(true);
765 NewLI.removeRange(*LII);
Jakob Stoklund Olesen6a3dbd32011-03-17 20:37:07 +0000766 DEBUG(dbgs() << "Dead PHI at " << VNI->def << " may separate interval\n");
767 CanSeparate = true;
Jakob Stoklund Olesen11513e52011-02-08 00:03:05 +0000768 } else {
769 // This is a dead def. Make sure the instruction knows.
770 MachineInstr *MI = getInstructionFromIndex(VNI->def);
771 assert(MI && "No instruction defining live value");
772 MI->addRegisterDead(li->reg, tri_);
Jakob Stoklund Olesen0d8ccaa2011-03-07 23:29:10 +0000773 if (dead && MI->allDefsAreDead()) {
Jakob Stoklund Olesenc46570d2011-03-16 22:56:08 +0000774 DEBUG(dbgs() << "All defs dead: " << VNI->def << '\t' << *MI);
Jakob Stoklund Olesen0d8ccaa2011-03-07 23:29:10 +0000775 dead->push_back(MI);
776 }
Jakob Stoklund Olesen11513e52011-02-08 00:03:05 +0000777 }
778 }
779
780 // Move the trimmed ranges back.
781 li->ranges.swap(NewLI.ranges);
Jakob Stoklund Olesenc46570d2011-03-16 22:56:08 +0000782 DEBUG(dbgs() << "Shrunk: " << *li << '\n');
Jakob Stoklund Olesen6a3dbd32011-03-17 20:37:07 +0000783 return CanSeparate;
Jakob Stoklund Olesen11513e52011-02-08 00:03:05 +0000784}
785
786
Evan Chengf2fbca62007-11-12 06:35:08 +0000787//===----------------------------------------------------------------------===//
788// Register allocator hooks.
789//
790
Jakob Stoklund Olesen8a61da82011-02-08 21:13:03 +0000791void LiveIntervals::addKillFlags() {
792 for (iterator I = begin(), E = end(); I != E; ++I) {
793 unsigned Reg = I->first;
794 if (TargetRegisterInfo::isPhysicalRegister(Reg))
795 continue;
796 if (mri_->reg_nodbg_empty(Reg))
797 continue;
798 LiveInterval *LI = I->second;
799
800 // Every instruction that kills Reg corresponds to a live range end point.
801 for (LiveInterval::iterator RI = LI->begin(), RE = LI->end(); RI != RE;
802 ++RI) {
Jakob Stoklund Olesen2debd482011-11-13 20:45:27 +0000803 // A block index indicates an MBB edge.
804 if (RI->end.isBlock())
Jakob Stoklund Olesen8a61da82011-02-08 21:13:03 +0000805 continue;
806 MachineInstr *MI = getInstructionFromIndex(RI->end);
807 if (!MI)
808 continue;
809 MI->addRegisterKilled(Reg, NULL);
810 }
811 }
812}
813
Matt Beaumont-Gaybaffe7a2012-01-30 19:26:20 +0000814#ifndef NDEBUG
Lang Hames907cc8f2012-01-27 22:36:19 +0000815static bool intervalRangesSane(const LiveInterval& li) {
816 if (li.empty()) {
817 return true;
818 }
819
820 SlotIndex lastEnd = li.begin()->start;
821 for (LiveInterval::const_iterator lrItr = li.begin(), lrEnd = li.end();
822 lrItr != lrEnd; ++lrItr) {
823 const LiveRange& lr = *lrItr;
824 if (lastEnd > lr.start || lr.start >= lr.end)
825 return false;
826 lastEnd = lr.end;
827 }
828
829 return true;
830}
Matt Beaumont-Gaybaffe7a2012-01-30 19:26:20 +0000831#endif
Lang Hames907cc8f2012-01-27 22:36:19 +0000832
833template <typename DefSetT>
834static void handleMoveDefs(LiveIntervals& lis, SlotIndex origIdx,
835 SlotIndex miIdx, const DefSetT& defs) {
836 for (typename DefSetT::const_iterator defItr = defs.begin(),
837 defEnd = defs.end();
838 defItr != defEnd; ++defItr) {
839 unsigned def = *defItr;
840 LiveInterval& li = lis.getInterval(def);
841 LiveRange* lr = li.getLiveRangeContaining(origIdx.getRegSlot());
842 assert(lr != 0 && "No range for def?");
843 lr->start = miIdx.getRegSlot();
844 lr->valno->def = miIdx.getRegSlot();
845 assert(intervalRangesSane(li) && "Broke live interval moving def.");
846 }
847}
848
849template <typename DeadDefSetT>
850static void handleMoveDeadDefs(LiveIntervals& lis, SlotIndex origIdx,
851 SlotIndex miIdx, const DeadDefSetT& deadDefs) {
852 for (typename DeadDefSetT::const_iterator deadDefItr = deadDefs.begin(),
853 deadDefEnd = deadDefs.end();
854 deadDefItr != deadDefEnd; ++deadDefItr) {
855 unsigned deadDef = *deadDefItr;
856 LiveInterval& li = lis.getInterval(deadDef);
857 LiveRange* lr = li.getLiveRangeContaining(origIdx.getRegSlot());
858 assert(lr != 0 && "No range for dead def?");
859 assert(lr->start == origIdx.getRegSlot() && "Bad dead range start?");
860 assert(lr->end == origIdx.getDeadSlot() && "Bad dead range end?");
861 assert(lr->valno->def == origIdx.getRegSlot() && "Bad dead valno def.");
862 LiveRange t(*lr);
863 t.start = miIdx.getRegSlot();
864 t.valno->def = miIdx.getRegSlot();
865 t.end = miIdx.getDeadSlot();
866 li.removeRange(*lr);
867 li.addRange(t);
868 assert(intervalRangesSane(li) && "Broke live interval moving dead def.");
869 }
870}
871
872template <typename ECSetT>
873static void handleMoveECs(LiveIntervals& lis, SlotIndex origIdx,
874 SlotIndex miIdx, const ECSetT& ecs) {
875 for (typename ECSetT::const_iterator ecItr = ecs.begin(), ecEnd = ecs.end();
876 ecItr != ecEnd; ++ecItr) {
877 unsigned ec = *ecItr;
878 LiveInterval& li = lis.getInterval(ec);
879 LiveRange* lr = li.getLiveRangeContaining(origIdx.getRegSlot(true));
880 assert(lr != 0 && "No range for early clobber?");
881 assert(lr->start == origIdx.getRegSlot(true) && "Bad EC range start?");
882 assert(lr->end == origIdx.getRegSlot() && "Bad EC range end.");
883 assert(lr->valno->def == origIdx.getRegSlot(true) && "Bad EC valno def.");
884 LiveRange t(*lr);
885 t.start = miIdx.getRegSlot(true);
886 t.valno->def = miIdx.getRegSlot(true);
887 t.end = miIdx.getRegSlot();
888 li.removeRange(*lr);
889 li.addRange(t);
890 assert(intervalRangesSane(li) && "Broke live interval moving EC.");
891 }
892}
893
Lang Hamesfb08b902012-02-09 04:45:38 +0000894static void moveKillFlags(unsigned reg, SlotIndex oldIdx, SlotIndex newIdx,
895 LiveIntervals& lis,
896 const TargetRegisterInfo& tri) {
897 MachineInstr* oldKillMI = lis.getInstructionFromIndex(oldIdx);
898 MachineInstr* newKillMI = lis.getInstructionFromIndex(newIdx);
899 assert(oldKillMI->killsRegister(reg) && "Old 'kill' instr isn't a kill.");
900 assert(!newKillMI->killsRegister(reg) && "New kill instr is already a kill.");
901 oldKillMI->clearRegisterKills(reg, &tri);
902 newKillMI->addRegisterKilled(reg, &tri);
903}
904
Lang Hames907cc8f2012-01-27 22:36:19 +0000905template <typename UseSetT>
906static void handleMoveUses(const MachineBasicBlock *mbb,
907 const MachineRegisterInfo& mri,
Lang Hamesfb08b902012-02-09 04:45:38 +0000908 const TargetRegisterInfo& tri,
Lang Hames907cc8f2012-01-27 22:36:19 +0000909 const BitVector& reservedRegs, LiveIntervals &lis,
910 SlotIndex origIdx, SlotIndex miIdx,
911 const UseSetT &uses) {
912 bool movingUp = miIdx < origIdx;
913 for (typename UseSetT::const_iterator usesItr = uses.begin(),
914 usesEnd = uses.end();
915 usesItr != usesEnd; ++usesItr) {
916 unsigned use = *usesItr;
917 if (!lis.hasInterval(use))
918 continue;
919 if (TargetRegisterInfo::isPhysicalRegister(use) && reservedRegs.test(use))
920 continue;
921 LiveInterval& li = lis.getInterval(use);
922 LiveRange* lr = li.getLiveRangeBefore(origIdx.getRegSlot());
923 assert(lr != 0 && "No range for use?");
924 bool liveThrough = lr->end > origIdx.getRegSlot();
925
926 if (movingUp) {
927 // If moving up and liveThrough - nothing to do.
928 // If not live through we need to extend the range to the last use
929 // between the old location and the new one.
930 if (!liveThrough) {
931 SlotIndex lastUseInRange = miIdx.getRegSlot();
932 for (MachineRegisterInfo::use_iterator useI = mri.use_begin(use),
933 useE = mri.use_end();
934 useI != useE; ++useI) {
935 const MachineInstr* mopI = &*useI;
936 const MachineOperand& mop = useI.getOperand();
937 SlotIndex instSlot = lis.getSlotIndexes()->getInstructionIndex(mopI);
938 SlotIndex opSlot = instSlot.getRegSlot(mop.isEarlyClobber());
Lang Hamesfb08b902012-02-09 04:45:38 +0000939 if (opSlot > lastUseInRange && opSlot < origIdx)
Lang Hames907cc8f2012-01-27 22:36:19 +0000940 lastUseInRange = opSlot;
Lang Hames907cc8f2012-01-27 22:36:19 +0000941 }
Lang Hamesfb08b902012-02-09 04:45:38 +0000942
943 // If we found a new instr endpoint update the kill flags.
944 if (lastUseInRange != miIdx.getRegSlot())
945 moveKillFlags(use, miIdx, lastUseInRange, lis, tri);
946
947 // Fix up the range end.
Lang Hames907cc8f2012-01-27 22:36:19 +0000948 lr->end = lastUseInRange;
949 }
950 } else {
951 // Moving down is easy - the existing live range end tells us where
952 // the last kill is.
953 if (!liveThrough) {
954 // Easy fix - just update the range endpoint.
955 lr->end = miIdx.getRegSlot();
956 } else {
957 bool liveOut = lr->end >= lis.getSlotIndexes()->getMBBEndIdx(mbb);
958 if (!liveOut && miIdx.getRegSlot() > lr->end) {
Lang Hamesfb08b902012-02-09 04:45:38 +0000959 moveKillFlags(use, lr->end, miIdx, lis, tri);
Lang Hames907cc8f2012-01-27 22:36:19 +0000960 lr->end = miIdx.getRegSlot();
961 }
962 }
963 }
964 assert(intervalRangesSane(li) && "Broke live interval moving use.");
965 }
966}
967
Lang Hamescc2037b2012-02-15 23:21:33 +0000968
969
970void LiveIntervals::handleMove(MachineInstr* mi) {
Lang Hames907cc8f2012-01-27 22:36:19 +0000971 SlotIndex origIdx = indexes_->getInstructionIndex(mi);
Lang Hames907cc8f2012-01-27 22:36:19 +0000972 indexes_->removeMachineInstrFromMaps(mi);
Lang Hamescc2037b2012-02-15 23:21:33 +0000973 SlotIndex miIdx = mi->isInsideBundle() ?
974 indexes_->getInstructionIndex(mi->getBundleStart()) :
975 indexes_->insertMachineInstrInMaps(mi);
Lang Hamesda7984f2012-02-15 01:23:52 +0000976 MachineBasicBlock* mbb = mi->getParent();
Lang Hamescc729132012-02-15 22:45:51 +0000977 assert(getMBBStartIdx(mbb) <= origIdx && origIdx < getMBBEndIdx(mbb) &&
Lang Hamesda7984f2012-02-15 01:23:52 +0000978 "Cannot handle moves across basic block boundaries.");
979 assert(!mi->isBundled() && "Can't handle bundled instructions yet.");
980
Lang Hames907cc8f2012-01-27 22:36:19 +0000981 // Pick the direction.
982 bool movingUp = miIdx < origIdx;
983
984 // Collect the operands.
985 DenseSet<unsigned> uses, defs, deadDefs, ecs;
986 for (MachineInstr::mop_iterator mopItr = mi->operands_begin(),
987 mopEnd = mi->operands_end();
988 mopItr != mopEnd; ++mopItr) {
989 const MachineOperand& mop = *mopItr;
990
991 if (!mop.isReg() || mop.getReg() == 0)
992 continue;
993 unsigned reg = mop.getReg();
Lang Hames907cc8f2012-01-27 22:36:19 +0000994
995 if (mop.readsReg() && !ecs.count(reg)) {
996 uses.insert(reg);
997 }
998 if (mop.isDef()) {
999 if (mop.isDead()) {
1000 assert(!defs.count(reg) && "Can't mix defs with dead-defs.");
1001 deadDefs.insert(reg);
1002 } else if (mop.isEarlyClobber()) {
1003 uses.erase(reg);
1004 ecs.insert(reg);
1005 } else {
1006 assert(!deadDefs.count(reg) && "Can't mix defs with dead-defs.");
1007 defs.insert(reg);
1008 }
1009 }
1010 }
1011
Lang Hames907cc8f2012-01-27 22:36:19 +00001012 if (movingUp) {
Lang Hames94b6e142012-02-14 23:06:12 +00001013 handleMoveUses(mbb, *mri_, *tri_, reservedRegs_, *this, origIdx, miIdx, uses);
Lang Hames907cc8f2012-01-27 22:36:19 +00001014 handleMoveECs(*this, origIdx, miIdx, ecs);
1015 handleMoveDeadDefs(*this, origIdx, miIdx, deadDefs);
1016 handleMoveDefs(*this, origIdx, miIdx, defs);
1017 } else {
1018 handleMoveDefs(*this, origIdx, miIdx, defs);
1019 handleMoveDeadDefs(*this, origIdx, miIdx, deadDefs);
1020 handleMoveECs(*this, origIdx, miIdx, ecs);
Lang Hames94b6e142012-02-14 23:06:12 +00001021 handleMoveUses(mbb, *mri_, *tri_, reservedRegs_, *this, origIdx, miIdx, uses);
Lang Hames907cc8f2012-01-27 22:36:19 +00001022 }
1023}
1024
Evan Chengd70dbb52008-02-22 09:24:50 +00001025/// getReMatImplicitUse - If the remat definition MI has one (for now, we only
1026/// allow one) virtual register operand, then its uses are implicitly using
1027/// the register. Returns the virtual register.
1028unsigned LiveIntervals::getReMatImplicitUse(const LiveInterval &li,
1029 MachineInstr *MI) const {
1030 unsigned RegOp = 0;
1031 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
1032 MachineOperand &MO = MI->getOperand(i);
Dan Gohmand735b802008-10-03 15:45:36 +00001033 if (!MO.isReg() || !MO.isUse())
Evan Chengd70dbb52008-02-22 09:24:50 +00001034 continue;
1035 unsigned Reg = MO.getReg();
1036 if (Reg == 0 || Reg == li.reg)
1037 continue;
Jakob Stoklund Olesen1b293202010-08-12 20:01:23 +00001038
Lang Hamescd339b72012-02-14 03:04:29 +00001039 if (TargetRegisterInfo::isPhysicalRegister(Reg) && !isAllocatable(Reg))
Chris Lattner1873d0c2009-06-27 04:06:41 +00001040 continue;
Evan Chengd70dbb52008-02-22 09:24:50 +00001041 RegOp = MO.getReg();
Lang Hames6c76e802012-01-25 21:53:23 +00001042 break; // Found vreg operand - leave the loop.
Evan Chengd70dbb52008-02-22 09:24:50 +00001043 }
1044 return RegOp;
1045}
1046
1047/// isValNoAvailableAt - Return true if the val# of the specified interval
1048/// which reaches the given instruction also reaches the specified use index.
1049bool LiveIntervals::isValNoAvailableAt(const LiveInterval &li, MachineInstr *MI,
Lang Hames233a60e2009-11-03 23:52:08 +00001050 SlotIndex UseIdx) const {
Jakob Stoklund Olesen31cc3ec2010-10-11 21:45:03 +00001051 VNInfo *UValNo = li.getVNInfoAt(UseIdx);
1052 return UValNo && UValNo == li.getVNInfoAt(getInstructionIndex(MI));
Evan Chengd70dbb52008-02-22 09:24:50 +00001053}
1054
Evan Chengf2fbca62007-11-12 06:35:08 +00001055/// isReMaterializable - Returns true if the definition MI of the specified
1056/// val# of the specified interval is re-materializable.
Andrew Trickf4baeaf2010-11-10 19:18:47 +00001057bool
1058LiveIntervals::isReMaterializable(const LiveInterval &li,
1059 const VNInfo *ValNo, MachineInstr *MI,
Jakob Stoklund Olesen38f6bd02011-03-10 01:21:58 +00001060 const SmallVectorImpl<LiveInterval*> *SpillIs,
Andrew Trickf4baeaf2010-11-10 19:18:47 +00001061 bool &isLoad) {
Evan Chengf2fbca62007-11-12 06:35:08 +00001062 if (DisableReMat)
1063 return false;
1064
Dan Gohmana70dca12009-10-09 23:27:56 +00001065 if (!tii_->isTriviallyReMaterializable(MI, aa_))
1066 return false;
Evan Chengdd3465e2008-02-23 01:44:27 +00001067
Dan Gohmana70dca12009-10-09 23:27:56 +00001068 // Target-specific code can mark an instruction as being rematerializable
1069 // if it has one virtual reg use, though it had better be something like
1070 // a PIC base register which is likely to be live everywhere.
Dan Gohman6d69ba82008-07-25 00:02:30 +00001071 unsigned ImpUse = getReMatImplicitUse(li, MI);
1072 if (ImpUse) {
1073 const LiveInterval &ImpLi = getInterval(ImpUse);
Evan Cheng28a1e482010-03-30 05:49:07 +00001074 for (MachineRegisterInfo::use_nodbg_iterator
1075 ri = mri_->use_nodbg_begin(li.reg), re = mri_->use_nodbg_end();
1076 ri != re; ++ri) {
Dan Gohman6d69ba82008-07-25 00:02:30 +00001077 MachineInstr *UseMI = &*ri;
Lang Hames233a60e2009-11-03 23:52:08 +00001078 SlotIndex UseIdx = getInstructionIndex(UseMI);
Jakob Stoklund Olesen31cc3ec2010-10-11 21:45:03 +00001079 if (li.getVNInfoAt(UseIdx) != ValNo)
Dan Gohman6d69ba82008-07-25 00:02:30 +00001080 continue;
1081 if (!isValNoAvailableAt(ImpLi, MI, UseIdx))
1082 return false;
1083 }
Evan Chengdc377862008-09-30 15:44:16 +00001084
1085 // If a register operand of the re-materialized instruction is going to
1086 // be spilled next, then it's not legal to re-materialize this instruction.
Jakob Stoklund Olesen38f6bd02011-03-10 01:21:58 +00001087 if (SpillIs)
1088 for (unsigned i = 0, e = SpillIs->size(); i != e; ++i)
1089 if (ImpUse == (*SpillIs)[i]->reg)
1090 return false;
Dan Gohman6d69ba82008-07-25 00:02:30 +00001091 }
1092 return true;
Evan Cheng5ef3a042007-12-06 00:01:56 +00001093}
1094
1095/// isReMaterializable - Returns true if every definition of MI of every
1096/// val# of the specified interval is re-materializable.
Andrew Trickf4baeaf2010-11-10 19:18:47 +00001097bool
1098LiveIntervals::isReMaterializable(const LiveInterval &li,
Jakob Stoklund Olesen38f6bd02011-03-10 01:21:58 +00001099 const SmallVectorImpl<LiveInterval*> *SpillIs,
Andrew Trickf4baeaf2010-11-10 19:18:47 +00001100 bool &isLoad) {
Evan Cheng5ef3a042007-12-06 00:01:56 +00001101 isLoad = false;
1102 for (LiveInterval::const_vni_iterator i = li.vni_begin(), e = li.vni_end();
1103 i != e; ++i) {
1104 const VNInfo *VNI = *i;
Lang Hames857c4e02009-06-17 21:01:20 +00001105 if (VNI->isUnused())
Evan Cheng5ef3a042007-12-06 00:01:56 +00001106 continue; // Dead val#.
1107 // Is the def for the val# rematerializable?
Lang Hames857c4e02009-06-17 21:01:20 +00001108 MachineInstr *ReMatDefMI = getInstructionFromIndex(VNI->def);
Lang Hames6e2968c2010-09-25 12:04:16 +00001109 if (!ReMatDefMI)
1110 return false;
Evan Cheng5ef3a042007-12-06 00:01:56 +00001111 bool DefIsLoad = false;
Evan Chengd70dbb52008-02-22 09:24:50 +00001112 if (!ReMatDefMI ||
Evan Chengdc377862008-09-30 15:44:16 +00001113 !isReMaterializable(li, VNI, ReMatDefMI, SpillIs, DefIsLoad))
Evan Cheng5ef3a042007-12-06 00:01:56 +00001114 return false;
1115 isLoad |= DefIsLoad;
Evan Chengf2fbca62007-11-12 06:35:08 +00001116 }
1117 return true;
1118}
1119
Jakob Stoklund Olesenebf27502012-02-10 01:23:55 +00001120MachineBasicBlock*
1121LiveIntervals::intervalIsInOneMBB(const LiveInterval &LI) const {
1122 // A local live range must be fully contained inside the block, meaning it is
1123 // defined and killed at instructions, not at block boundaries. It is not
1124 // live in or or out of any block.
1125 //
1126 // It is technically possible to have a PHI-defined live range identical to a
1127 // single block, but we are going to return false in that case.
Lang Hames233a60e2009-11-03 23:52:08 +00001128
Jakob Stoklund Olesenebf27502012-02-10 01:23:55 +00001129 SlotIndex Start = LI.beginIndex();
1130 if (Start.isBlock())
1131 return NULL;
Lang Hames233a60e2009-11-03 23:52:08 +00001132
Jakob Stoklund Olesenebf27502012-02-10 01:23:55 +00001133 SlotIndex Stop = LI.endIndex();
1134 if (Stop.isBlock())
1135 return NULL;
Lang Hames233a60e2009-11-03 23:52:08 +00001136
Jakob Stoklund Olesenebf27502012-02-10 01:23:55 +00001137 // getMBBFromIndex doesn't need to search the MBB table when both indexes
1138 // belong to proper instructions.
1139 MachineBasicBlock *MBB1 = indexes_->getMBBFromIndex(Start);
1140 MachineBasicBlock *MBB2 = indexes_->getMBBFromIndex(Stop);
1141 return MBB1 == MBB2 ? MBB1 : NULL;
Evan Cheng81a03822007-11-17 00:40:40 +00001142}
1143
Jakob Stoklund Olesene5d90412010-03-01 20:59:38 +00001144float
1145LiveIntervals::getSpillWeight(bool isDef, bool isUse, unsigned loopDepth) {
1146 // Limit the loop depth ridiculousness.
1147 if (loopDepth > 200)
1148 loopDepth = 200;
1149
1150 // The loop depth is used to roughly estimate the number of times the
1151 // instruction is executed. Something like 10^d is simple, but will quickly
1152 // overflow a float. This expression behaves like 10^d for small d, but is
1153 // more tempered for large d. At d=200 we get 6.7e33 which leaves a bit of
1154 // headroom before overflow.
NAKAMURA Takumidc5198b2011-03-31 12:11:33 +00001155 // By the way, powf() might be unavailable here. For consistency,
1156 // We may take pow(double,double).
1157 float lc = std::pow(1 + (100.0 / (loopDepth + 10)), (double)loopDepth);
Jakob Stoklund Olesene5d90412010-03-01 20:59:38 +00001158
1159 return (isDef + isUse) * lc;
1160}
1161
Owen Andersonc4dc1322008-06-05 17:15:43 +00001162LiveRange LiveIntervals::addLiveRangeToEndOfBlock(unsigned reg,
Lang Hamesffd13262009-07-09 03:57:02 +00001163 MachineInstr* startInst) {
Owen Andersonc4dc1322008-06-05 17:15:43 +00001164 LiveInterval& Interval = getOrCreateInterval(reg);
1165 VNInfo* VN = Interval.getNextValue(
Jakob Stoklund Olesen2debd482011-11-13 20:45:27 +00001166 SlotIndex(getInstructionIndex(startInst).getRegSlot()),
Jakob Stoklund Olesen3b1088a2012-02-04 05:20:49 +00001167 getVNInfoAllocator());
Lang Hames857c4e02009-06-17 21:01:20 +00001168 VN->setHasPHIKill(true);
Lang Hames86511252009-09-04 20:41:11 +00001169 LiveRange LR(
Jakob Stoklund Olesen2debd482011-11-13 20:45:27 +00001170 SlotIndex(getInstructionIndex(startInst).getRegSlot()),
Lang Hames74ab5ee2009-12-22 00:11:50 +00001171 getMBBEndIdx(startInst->getParent()), VN);
Owen Andersonc4dc1322008-06-05 17:15:43 +00001172 Interval.addRange(LR);
Jakob Stoklund Olesen1b293202010-08-12 20:01:23 +00001173
Owen Andersonc4dc1322008-06-05 17:15:43 +00001174 return LR;
1175}
Jakob Stoklund Olesen3fd3a842012-02-08 17:33:45 +00001176
1177
1178//===----------------------------------------------------------------------===//
1179// Register mask functions
1180//===----------------------------------------------------------------------===//
1181
1182bool LiveIntervals::checkRegMaskInterference(LiveInterval &LI,
1183 BitVector &UsableRegs) {
1184 if (LI.empty())
1185 return false;
Jakob Stoklund Olesen9f10ac62012-02-10 01:31:31 +00001186 LiveInterval::iterator LiveI = LI.begin(), LiveE = LI.end();
1187
1188 // Use a smaller arrays for local live ranges.
1189 ArrayRef<SlotIndex> Slots;
1190 ArrayRef<const uint32_t*> Bits;
1191 if (MachineBasicBlock *MBB = intervalIsInOneMBB(LI)) {
1192 Slots = getRegMaskSlotsInBlock(MBB->getNumber());
1193 Bits = getRegMaskBitsInBlock(MBB->getNumber());
1194 } else {
1195 Slots = getRegMaskSlots();
1196 Bits = getRegMaskBits();
1197 }
Jakob Stoklund Olesen3fd3a842012-02-08 17:33:45 +00001198
1199 // We are going to enumerate all the register mask slots contained in LI.
1200 // Start with a binary search of RegMaskSlots to find a starting point.
Jakob Stoklund Olesen3fd3a842012-02-08 17:33:45 +00001201 ArrayRef<SlotIndex>::iterator SlotI =
1202 std::lower_bound(Slots.begin(), Slots.end(), LiveI->start);
1203 ArrayRef<SlotIndex>::iterator SlotE = Slots.end();
1204
1205 // No slots in range, LI begins after the last call.
1206 if (SlotI == SlotE)
1207 return false;
1208
1209 bool Found = false;
1210 for (;;) {
1211 assert(*SlotI >= LiveI->start);
1212 // Loop over all slots overlapping this segment.
1213 while (*SlotI < LiveI->end) {
1214 // *SlotI overlaps LI. Collect mask bits.
1215 if (!Found) {
1216 // This is the first overlap. Initialize UsableRegs to all ones.
1217 UsableRegs.clear();
1218 UsableRegs.resize(tri_->getNumRegs(), true);
1219 Found = true;
1220 }
1221 // Remove usable registers clobbered by this mask.
Jakob Stoklund Olesen9f10ac62012-02-10 01:31:31 +00001222 UsableRegs.clearBitsNotInMask(Bits[SlotI-Slots.begin()]);
Jakob Stoklund Olesen3fd3a842012-02-08 17:33:45 +00001223 if (++SlotI == SlotE)
1224 return Found;
1225 }
1226 // *SlotI is beyond the current LI segment.
1227 LiveI = LI.advanceTo(LiveI, *SlotI);
1228 if (LiveI == LiveE)
1229 return Found;
1230 // Advance SlotI until it overlaps.
1231 while (*SlotI < LiveI->start)
1232 if (++SlotI == SlotE)
1233 return Found;
1234 }
1235}