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Chris Lattnerb3c85472009-09-20 07:28:26 +00001//===-- X86IntelInstPrinter.cpp - AT&T assembly instruction printing ------===//
Chris Lattnere895c612009-09-20 07:17:49 +00002//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file includes code for rendering MCInst instances as AT&T-style
11// assembly.
12//
13//===----------------------------------------------------------------------===//
14
15#define DEBUG_TYPE "asm-printer"
16#include "X86IntelInstPrinter.h"
17#include "llvm/MC/MCInst.h"
18#include "llvm/MC/MCAsmInfo.h"
19#include "llvm/MC/MCExpr.h"
20#include "llvm/Support/ErrorHandling.h"
21#include "llvm/Support/FormattedStream.h"
22#include "X86GenInstrNames.inc"
23using namespace llvm;
24
25// Include the auto-generated portion of the assembly writer.
26#define MachineInstr MCInst
Chris Lattner0d7b0aa2010-02-11 22:57:32 +000027#define GET_INSTRUCTION_NAME
Chris Lattnere895c612009-09-20 07:17:49 +000028#include "X86GenAsmWriter1.inc"
29#undef MachineInstr
30
Chris Lattnerd3740872010-04-04 05:04:31 +000031void X86IntelInstPrinter::printInst(const MCInst *MI, raw_ostream &OS) {
32 printInstruction(MI, OS);
Chris Lattner35c33bd2010-04-04 04:47:45 +000033}
Chris Lattner0d7b0aa2010-02-11 22:57:32 +000034StringRef X86IntelInstPrinter::getOpcodeName(unsigned Opcode) const {
35 return getInstructionName(Opcode);
36}
Chris Lattnere895c612009-09-20 07:17:49 +000037
Chris Lattner35c33bd2010-04-04 04:47:45 +000038void X86IntelInstPrinter::printSSECC(const MCInst *MI, unsigned Op,
39 raw_ostream &O) {
Chris Lattnere895c612009-09-20 07:17:49 +000040 switch (MI->getOperand(Op).getImm()) {
Chris Lattner35c33bd2010-04-04 04:47:45 +000041 default: assert(0 && "Invalid ssecc argument!");
Chris Lattnere895c612009-09-20 07:17:49 +000042 case 0: O << "eq"; break;
43 case 1: O << "lt"; break;
44 case 2: O << "le"; break;
45 case 3: O << "unord"; break;
46 case 4: O << "neq"; break;
47 case 5: O << "nlt"; break;
48 case 6: O << "nle"; break;
49 case 7: O << "ord"; break;
50 }
51}
52
Chris Lattnere895c612009-09-20 07:17:49 +000053/// print_pcrel_imm - This is used to print an immediate value that ends up
Chris Lattner70576412009-09-20 07:47:59 +000054/// being encoded as a pc-relative value.
Chris Lattner35c33bd2010-04-04 04:47:45 +000055void X86IntelInstPrinter::print_pcrel_imm(const MCInst *MI, unsigned OpNo,
56 raw_ostream &O) {
Chris Lattnere895c612009-09-20 07:17:49 +000057 const MCOperand &Op = MI->getOperand(OpNo);
58 if (Op.isImm())
59 O << Op.getImm();
60 else {
61 assert(Op.isExpr() && "unknown pcrel immediate operand");
Chris Lattner8cb9a3b2010-01-18 00:37:40 +000062 O << *Op.getExpr();
Chris Lattnere895c612009-09-20 07:17:49 +000063 }
64}
65
66static void PrintRegName(raw_ostream &O, StringRef RegName) {
67 for (unsigned i = 0, e = RegName.size(); i != e; ++i)
68 O << (char)toupper(RegName[i]);
69}
70
71void X86IntelInstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
Chris Lattner35c33bd2010-04-04 04:47:45 +000072 raw_ostream &O) {
Chris Lattnere895c612009-09-20 07:17:49 +000073 const MCOperand &Op = MI->getOperand(OpNo);
74 if (Op.isReg()) {
75 PrintRegName(O, getRegisterName(Op.getReg()));
76 } else if (Op.isImm()) {
77 O << Op.getImm();
78 } else {
79 assert(Op.isExpr() && "unknown operand kind in printOperand");
Chris Lattner8cb9a3b2010-01-18 00:37:40 +000080 O << *Op.getExpr();
Chris Lattnere895c612009-09-20 07:17:49 +000081 }
82}
83
Chris Lattner35c33bd2010-04-04 04:47:45 +000084void X86IntelInstPrinter::printLeaMemReference(const MCInst *MI, unsigned Op,
85 raw_ostream &O) {
Chris Lattnere895c612009-09-20 07:17:49 +000086 const MCOperand &BaseReg = MI->getOperand(Op);
87 unsigned ScaleVal = MI->getOperand(Op+1).getImm();
88 const MCOperand &IndexReg = MI->getOperand(Op+2);
89 const MCOperand &DispSpec = MI->getOperand(Op+3);
90
91 O << '[';
92
93 bool NeedPlus = false;
94 if (BaseReg.getReg()) {
Chris Lattner35c33bd2010-04-04 04:47:45 +000095 printOperand(MI, Op, O);
Chris Lattnere895c612009-09-20 07:17:49 +000096 NeedPlus = true;
97 }
98
99 if (IndexReg.getReg()) {
100 if (NeedPlus) O << " + ";
101 if (ScaleVal != 1)
102 O << ScaleVal << '*';
Chris Lattner35c33bd2010-04-04 04:47:45 +0000103 printOperand(MI, Op+2, O);
Chris Lattnere895c612009-09-20 07:17:49 +0000104 NeedPlus = true;
105 }
106
107
108 if (!DispSpec.isImm()) {
109 if (NeedPlus) O << " + ";
110 assert(DispSpec.isExpr() && "non-immediate displacement for LEA?");
Chris Lattner8cb9a3b2010-01-18 00:37:40 +0000111 O << *DispSpec.getExpr();
Chris Lattnere895c612009-09-20 07:17:49 +0000112 } else {
113 int64_t DispVal = DispSpec.getImm();
114 if (DispVal || (!IndexReg.getReg() && !BaseReg.getReg())) {
115 if (NeedPlus) {
116 if (DispVal > 0)
117 O << " + ";
118 else {
119 O << " - ";
120 DispVal = -DispVal;
121 }
122 }
123 O << DispVal;
124 }
125 }
126
127 O << ']';
128}
129
Chris Lattner35c33bd2010-04-04 04:47:45 +0000130void X86IntelInstPrinter::printMemReference(const MCInst *MI, unsigned Op,
131 raw_ostream &O) {
Chris Lattnere895c612009-09-20 07:17:49 +0000132 // If this has a segment register, print it.
133 if (MI->getOperand(Op+4).getReg()) {
Chris Lattner35c33bd2010-04-04 04:47:45 +0000134 printOperand(MI, Op+4, O);
Chris Lattnere895c612009-09-20 07:17:49 +0000135 O << ':';
136 }
Chris Lattner35c33bd2010-04-04 04:47:45 +0000137 printLeaMemReference(MI, Op, O);
Chris Lattnere895c612009-09-20 07:17:49 +0000138}