Brian Gaeke | 3ca4fcc | 2004-04-25 07:04:49 +0000 | [diff] [blame] | 1 | //===-- SparcV9RegInfo.cpp - SparcV9 Target Register Information ----------===// |
John Criswell | b576c94 | 2003-10-20 19:43:21 +0000 | [diff] [blame] | 2 | // |
| 3 | // The LLVM Compiler Infrastructure |
| 4 | // |
| 5 | // This file was developed by the LLVM research group and is distributed under |
| 6 | // the University of Illinois Open Source License. See LICENSE.TXT for details. |
| 7 | // |
| 8 | //===----------------------------------------------------------------------===// |
Chris Lattner | ed5171e | 2002-02-03 07:52:04 +0000 | [diff] [blame] | 9 | // |
Brian Gaeke | 3ca4fcc | 2004-04-25 07:04:49 +0000 | [diff] [blame] | 10 | // This file contains implementations of SparcV9 specific helper methods |
Chris Lattner | ed5171e | 2002-02-03 07:52:04 +0000 | [diff] [blame] | 11 | // used for register allocation. |
| 12 | // |
| 13 | //===----------------------------------------------------------------------===// |
| 14 | |
Misha Brukman | fce1143 | 2002-10-28 00:28:31 +0000 | [diff] [blame] | 15 | #include "llvm/CodeGen/MachineFunction.h" |
Chris Lattner | 00dca91 | 2003-01-15 17:47:49 +0000 | [diff] [blame] | 16 | #include "llvm/CodeGen/MachineInstrBuilder.h" |
Chris Lattner | 85015a0 | 2004-08-16 21:55:02 +0000 | [diff] [blame] | 17 | #include "MachineFunctionInfo.h" |
| 18 | #include "MachineCodeForInstruction.h" |
Chris Lattner | 08d4963 | 2004-02-29 19:12:51 +0000 | [diff] [blame] | 19 | #include "MachineInstrAnnot.h" |
Chris Lattner | 1d415a9 | 2004-01-09 16:17:09 +0000 | [diff] [blame] | 20 | #include "RegAlloc/LiveRangeInfo.h" |
| 21 | #include "RegAlloc/LiveRange.h" |
Misha Brukman | d71295a | 2003-12-17 22:04:00 +0000 | [diff] [blame] | 22 | #include "llvm/DerivedTypes.h" |
| 23 | #include "llvm/Function.h" |
Chris Lattner | 9670eec | 2004-07-29 17:11:37 +0000 | [diff] [blame] | 24 | #include "llvm/Instructions.h" |
Brian Gaeke | e3d6807 | 2004-02-25 18:44:15 +0000 | [diff] [blame] | 25 | #include "SparcV9Internals.h" |
| 26 | #include "SparcV9RegClassInfo.h" |
| 27 | #include "SparcV9RegInfo.h" |
Chris Lattner | 750d723 | 2004-08-12 18:29:05 +0000 | [diff] [blame] | 28 | #include "SparcV9FrameInfo.h" |
Brian Gaeke | e3d6807 | 2004-02-25 18:44:15 +0000 | [diff] [blame] | 29 | #include "SparcV9TargetMachine.h" |
Brian Gaeke | 98ac7ac | 2004-08-04 07:29:53 +0000 | [diff] [blame] | 30 | #include "SparcV9TmpInstr.h" |
Reid Spencer | 954da37 | 2004-07-04 12:19:56 +0000 | [diff] [blame] | 31 | #include <iostream> |
Chris Lattner | 20b1ea0 | 2001-09-14 03:47:57 +0000 | [diff] [blame] | 32 | |
Brian Gaeke | d0fde30 | 2003-11-11 22:41:34 +0000 | [diff] [blame] | 33 | namespace llvm { |
| 34 | |
Chris Lattner | 92ba2aa | 2003-01-14 23:05:08 +0000 | [diff] [blame] | 35 | enum { |
| 36 | BadRegClass = ~0 |
| 37 | }; |
| 38 | |
Brian Gaeke | e3d6807 | 2004-02-25 18:44:15 +0000 | [diff] [blame] | 39 | SparcV9RegInfo::SparcV9RegInfo(const SparcV9TargetMachine &tgt) |
Brian Gaeke | 498231b | 2004-06-03 02:45:09 +0000 | [diff] [blame] | 40 | : target (tgt), NumOfIntArgRegs (6), NumOfFloatArgRegs (32) |
Vikram S. Adve | d0d06ad | 2003-05-31 07:32:01 +0000 | [diff] [blame] | 41 | { |
Brian Gaeke | e3d6807 | 2004-02-25 18:44:15 +0000 | [diff] [blame] | 42 | MachineRegClassArr.push_back(new SparcV9IntRegClass(IntRegClassID)); |
| 43 | MachineRegClassArr.push_back(new SparcV9FloatRegClass(FloatRegClassID)); |
| 44 | MachineRegClassArr.push_back(new SparcV9IntCCRegClass(IntCCRegClassID)); |
| 45 | MachineRegClassArr.push_back(new SparcV9FloatCCRegClass(FloatCCRegClassID)); |
| 46 | MachineRegClassArr.push_back(new SparcV9SpecialRegClass(SpecialRegClassID)); |
Vikram S. Adve | 76ee6f7 | 2002-07-08 23:23:12 +0000 | [diff] [blame] | 47 | |
Brian Gaeke | e3d6807 | 2004-02-25 18:44:15 +0000 | [diff] [blame] | 48 | assert(SparcV9FloatRegClass::StartOfNonVolatileRegs == 32 && |
Chris Lattner | 699683c | 2002-02-04 05:59:25 +0000 | [diff] [blame] | 49 | "32 Float regs are used for float arg passing"); |
| 50 | } |
| 51 | |
| 52 | |
Vikram S. Adve | f1c15ee | 2002-03-18 03:12:16 +0000 | [diff] [blame] | 53 | // getZeroRegNum - returns the register that contains always zero. |
| 54 | // this is the unified register number |
Chris Lattner | 699683c | 2002-02-04 05:59:25 +0000 | [diff] [blame] | 55 | // |
Brian Gaeke | e3d6807 | 2004-02-25 18:44:15 +0000 | [diff] [blame] | 56 | unsigned SparcV9RegInfo::getZeroRegNum() const { |
| 57 | return getUnifiedRegNum(SparcV9RegInfo::IntRegClassID, |
| 58 | SparcV9IntRegClass::g0); |
Vikram S. Adve | f1c15ee | 2002-03-18 03:12:16 +0000 | [diff] [blame] | 59 | } |
Chris Lattner | 699683c | 2002-02-04 05:59:25 +0000 | [diff] [blame] | 60 | |
| 61 | // getCallAddressReg - returns the reg used for pushing the address when a |
| 62 | // method is called. This can be used for other purposes between calls |
| 63 | // |
Brian Gaeke | e3d6807 | 2004-02-25 18:44:15 +0000 | [diff] [blame] | 64 | unsigned SparcV9RegInfo::getCallAddressReg() const { |
| 65 | return getUnifiedRegNum(SparcV9RegInfo::IntRegClassID, |
| 66 | SparcV9IntRegClass::o7); |
Chris Lattner | 699683c | 2002-02-04 05:59:25 +0000 | [diff] [blame] | 67 | } |
| 68 | |
| 69 | // Returns the register containing the return address. |
| 70 | // It should be made sure that this register contains the return |
| 71 | // value when a return instruction is reached. |
| 72 | // |
Brian Gaeke | e3d6807 | 2004-02-25 18:44:15 +0000 | [diff] [blame] | 73 | unsigned SparcV9RegInfo::getReturnAddressReg() const { |
| 74 | return getUnifiedRegNum(SparcV9RegInfo::IntRegClassID, |
| 75 | SparcV9IntRegClass::i7); |
Chris Lattner | 9568568 | 2002-08-12 21:25:05 +0000 | [diff] [blame] | 76 | } |
| 77 | |
| 78 | // Register get name implementations... |
| 79 | |
Brian Gaeke | e3d6807 | 2004-02-25 18:44:15 +0000 | [diff] [blame] | 80 | // Int register names in same order as enum in class SparcV9IntRegClass |
Chris Lattner | 9568568 | 2002-08-12 21:25:05 +0000 | [diff] [blame] | 81 | static const char * const IntRegNames[] = { |
| 82 | "o0", "o1", "o2", "o3", "o4", "o5", "o7", |
| 83 | "l0", "l1", "l2", "l3", "l4", "l5", "l6", "l7", |
| 84 | "i0", "i1", "i2", "i3", "i4", "i5", |
| 85 | "i6", "i7", |
| 86 | "g0", "g1", "g2", "g3", "g4", "g5", "g6", "g7", |
| 87 | "o6" |
| 88 | }; |
| 89 | |
Brian Gaeke | e3d6807 | 2004-02-25 18:44:15 +0000 | [diff] [blame] | 90 | const char * const SparcV9IntRegClass::getRegName(unsigned reg) const { |
Chris Lattner | 9568568 | 2002-08-12 21:25:05 +0000 | [diff] [blame] | 91 | assert(reg < NumOfAllRegs); |
| 92 | return IntRegNames[reg]; |
| 93 | } |
| 94 | |
| 95 | static const char * const FloatRegNames[] = { |
| 96 | "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", "f8", "f9", |
| 97 | "f10", "f11", "f12", "f13", "f14", "f15", "f16", "f17", "f18", "f19", |
| 98 | "f20", "f21", "f22", "f23", "f24", "f25", "f26", "f27", "f28", "f29", |
| 99 | "f30", "f31", "f32", "f33", "f34", "f35", "f36", "f37", "f38", "f39", |
| 100 | "f40", "f41", "f42", "f43", "f44", "f45", "f46", "f47", "f48", "f49", |
| 101 | "f50", "f51", "f52", "f53", "f54", "f55", "f56", "f57", "f58", "f59", |
| 102 | "f60", "f61", "f62", "f63" |
| 103 | }; |
| 104 | |
Brian Gaeke | e3d6807 | 2004-02-25 18:44:15 +0000 | [diff] [blame] | 105 | const char * const SparcV9FloatRegClass::getRegName(unsigned reg) const { |
Chris Lattner | 9568568 | 2002-08-12 21:25:05 +0000 | [diff] [blame] | 106 | assert (reg < NumOfAllRegs); |
| 107 | return FloatRegNames[reg]; |
| 108 | } |
| 109 | |
Chris Lattner | 9568568 | 2002-08-12 21:25:05 +0000 | [diff] [blame] | 110 | static const char * const IntCCRegNames[] = { |
Vikram S. Adve | 786833a | 2003-07-06 20:13:59 +0000 | [diff] [blame] | 111 | "xcc", "icc", "ccr" |
Chris Lattner | 9568568 | 2002-08-12 21:25:05 +0000 | [diff] [blame] | 112 | }; |
| 113 | |
Brian Gaeke | e3d6807 | 2004-02-25 18:44:15 +0000 | [diff] [blame] | 114 | const char * const SparcV9IntCCRegClass::getRegName(unsigned reg) const { |
Vikram S. Adve | 786833a | 2003-07-06 20:13:59 +0000 | [diff] [blame] | 115 | assert(reg < 3); |
Chris Lattner | 9568568 | 2002-08-12 21:25:05 +0000 | [diff] [blame] | 116 | return IntCCRegNames[reg]; |
| 117 | } |
| 118 | |
| 119 | static const char * const FloatCCRegNames[] = { |
| 120 | "fcc0", "fcc1", "fcc2", "fcc3" |
| 121 | }; |
| 122 | |
Brian Gaeke | e3d6807 | 2004-02-25 18:44:15 +0000 | [diff] [blame] | 123 | const char * const SparcV9FloatCCRegClass::getRegName(unsigned reg) const { |
Brian Gaeke | 03b562a | 2004-04-19 18:53:43 +0000 | [diff] [blame] | 124 | assert (reg < 4); |
Chris Lattner | 9568568 | 2002-08-12 21:25:05 +0000 | [diff] [blame] | 125 | return FloatCCRegNames[reg]; |
Chris Lattner | 699683c | 2002-02-04 05:59:25 +0000 | [diff] [blame] | 126 | } |
| 127 | |
Vikram S. Adve | 78a4f23 | 2003-05-27 00:02:22 +0000 | [diff] [blame] | 128 | static const char * const SpecialRegNames[] = { |
| 129 | "fsr" |
| 130 | }; |
| 131 | |
Brian Gaeke | e3d6807 | 2004-02-25 18:44:15 +0000 | [diff] [blame] | 132 | const char * const SparcV9SpecialRegClass::getRegName(unsigned reg) const { |
Vikram S. Adve | 78a4f23 | 2003-05-27 00:02:22 +0000 | [diff] [blame] | 133 | assert (reg < 1); |
| 134 | return SpecialRegNames[reg]; |
Chris Lattner | 699683c | 2002-02-04 05:59:25 +0000 | [diff] [blame] | 135 | } |
| 136 | |
Vikram S. Adve | f1c15ee | 2002-03-18 03:12:16 +0000 | [diff] [blame] | 137 | // Get unified reg number for frame pointer |
Brian Gaeke | e3d6807 | 2004-02-25 18:44:15 +0000 | [diff] [blame] | 138 | unsigned SparcV9RegInfo::getFramePointer() const { |
| 139 | return getUnifiedRegNum(SparcV9RegInfo::IntRegClassID, |
| 140 | SparcV9IntRegClass::i6); |
Chris Lattner | 699683c | 2002-02-04 05:59:25 +0000 | [diff] [blame] | 141 | } |
| 142 | |
Vikram S. Adve | f1c15ee | 2002-03-18 03:12:16 +0000 | [diff] [blame] | 143 | // Get unified reg number for stack pointer |
Brian Gaeke | e3d6807 | 2004-02-25 18:44:15 +0000 | [diff] [blame] | 144 | unsigned SparcV9RegInfo::getStackPointer() const { |
| 145 | return getUnifiedRegNum(SparcV9RegInfo::IntRegClassID, |
| 146 | SparcV9IntRegClass::o6); |
Chris Lattner | 699683c | 2002-02-04 05:59:25 +0000 | [diff] [blame] | 147 | } |
| 148 | |
| 149 | |
Vikram S. Adve | 31f78c4 | 2002-04-25 04:42:21 +0000 | [diff] [blame] | 150 | //--------------------------------------------------------------------------- |
| 151 | // Finds whether a call is an indirect call |
| 152 | //--------------------------------------------------------------------------- |
| 153 | |
| 154 | inline bool |
| 155 | isVarArgsFunction(const Type *funcType) { |
| 156 | return cast<FunctionType>(cast<PointerType>(funcType) |
| 157 | ->getElementType())->isVarArg(); |
| 158 | } |
| 159 | |
| 160 | inline bool |
| 161 | isVarArgsCall(const MachineInstr *CallMI) { |
| 162 | Value* callee = CallMI->getOperand(0).getVRegValue(); |
| 163 | // const Type* funcType = isa<Function>(callee)? callee->getType() |
| 164 | // : cast<PointerType>(callee->getType())->getElementType(); |
| 165 | const Type* funcType = callee->getType(); |
| 166 | return isVarArgsFunction(funcType); |
| 167 | } |
| 168 | |
| 169 | |
Vikram S. Adve | d0d06ad | 2003-05-31 07:32:01 +0000 | [diff] [blame] | 170 | // Get the register number for the specified argument #argNo, |
Vikram S. Adve | 31f78c4 | 2002-04-25 04:42:21 +0000 | [diff] [blame] | 171 | // |
| 172 | // Return value: |
Vikram S. Adve | d0d06ad | 2003-05-31 07:32:01 +0000 | [diff] [blame] | 173 | // getInvalidRegNum(), if there is no int register available for the arg. |
| 174 | // regNum, otherwise (this is NOT the unified reg. num). |
| 175 | // regClassId is set to the register class ID. |
Vikram S. Adve | 31f78c4 | 2002-04-25 04:42:21 +0000 | [diff] [blame] | 176 | // |
Vikram S. Adve | d0d06ad | 2003-05-31 07:32:01 +0000 | [diff] [blame] | 177 | int |
Brian Gaeke | e3d6807 | 2004-02-25 18:44:15 +0000 | [diff] [blame] | 178 | SparcV9RegInfo::regNumForIntArg(bool inCallee, bool isVarArgsCall, |
Vikram S. Adve | d0d06ad | 2003-05-31 07:32:01 +0000 | [diff] [blame] | 179 | unsigned argNo, unsigned& regClassId) const |
Vikram S. Adve | 31f78c4 | 2002-04-25 04:42:21 +0000 | [diff] [blame] | 180 | { |
Vikram S. Adve | 242a808 | 2002-05-19 15:25:51 +0000 | [diff] [blame] | 181 | regClassId = IntRegClassID; |
Vikram S. Adve | 31f78c4 | 2002-04-25 04:42:21 +0000 | [diff] [blame] | 182 | if (argNo >= NumOfIntArgRegs) |
Vikram S. Adve | d0d06ad | 2003-05-31 07:32:01 +0000 | [diff] [blame] | 183 | return getInvalidRegNum(); |
Vikram S. Adve | 242a808 | 2002-05-19 15:25:51 +0000 | [diff] [blame] | 184 | else |
Brian Gaeke | e3d6807 | 2004-02-25 18:44:15 +0000 | [diff] [blame] | 185 | return argNo + (inCallee? SparcV9IntRegClass::i0 : SparcV9IntRegClass::o0); |
Vikram S. Adve | 31f78c4 | 2002-04-25 04:42:21 +0000 | [diff] [blame] | 186 | } |
| 187 | |
Vikram S. Adve | d0d06ad | 2003-05-31 07:32:01 +0000 | [diff] [blame] | 188 | // Get the register number for the specified FP argument #argNo, |
Vikram S. Adve | 31f78c4 | 2002-04-25 04:42:21 +0000 | [diff] [blame] | 189 | // Use INT regs for FP args if this is a varargs call. |
| 190 | // |
| 191 | // Return value: |
Vikram S. Adve | d0d06ad | 2003-05-31 07:32:01 +0000 | [diff] [blame] | 192 | // getInvalidRegNum(), if there is no int register available for the arg. |
| 193 | // regNum, otherwise (this is NOT the unified reg. num). |
| 194 | // regClassId is set to the register class ID. |
Vikram S. Adve | 31f78c4 | 2002-04-25 04:42:21 +0000 | [diff] [blame] | 195 | // |
Vikram S. Adve | d0d06ad | 2003-05-31 07:32:01 +0000 | [diff] [blame] | 196 | int |
Brian Gaeke | e3d6807 | 2004-02-25 18:44:15 +0000 | [diff] [blame] | 197 | SparcV9RegInfo::regNumForFPArg(unsigned regType, |
Vikram S. Adve | 31f78c4 | 2002-04-25 04:42:21 +0000 | [diff] [blame] | 198 | bool inCallee, bool isVarArgsCall, |
Vikram S. Adve | d0d06ad | 2003-05-31 07:32:01 +0000 | [diff] [blame] | 199 | unsigned argNo, unsigned& regClassId) const |
Vikram S. Adve | 31f78c4 | 2002-04-25 04:42:21 +0000 | [diff] [blame] | 200 | { |
Vikram S. Adve | 242a808 | 2002-05-19 15:25:51 +0000 | [diff] [blame] | 201 | if (isVarArgsCall) |
Vikram S. Adve | d0d06ad | 2003-05-31 07:32:01 +0000 | [diff] [blame] | 202 | return regNumForIntArg(inCallee, isVarArgsCall, argNo, regClassId); |
Vikram S. Adve | 242a808 | 2002-05-19 15:25:51 +0000 | [diff] [blame] | 203 | else |
| 204 | { |
| 205 | regClassId = FloatRegClassID; |
| 206 | if (regType == FPSingleRegType) |
| 207 | return (argNo*2+1 >= NumOfFloatArgRegs)? |
Brian Gaeke | e3d6807 | 2004-02-25 18:44:15 +0000 | [diff] [blame] | 208 | getInvalidRegNum() : SparcV9FloatRegClass::f0 + (argNo * 2 + 1); |
Vikram S. Adve | 242a808 | 2002-05-19 15:25:51 +0000 | [diff] [blame] | 209 | else if (regType == FPDoubleRegType) |
| 210 | return (argNo*2 >= NumOfFloatArgRegs)? |
Brian Gaeke | e3d6807 | 2004-02-25 18:44:15 +0000 | [diff] [blame] | 211 | getInvalidRegNum() : SparcV9FloatRegClass::f0 + (argNo * 2); |
Vikram S. Adve | 242a808 | 2002-05-19 15:25:51 +0000 | [diff] [blame] | 212 | else |
| 213 | assert(0 && "Illegal FP register type"); |
Chris Lattner | b82d97e | 2002-07-25 06:08:32 +0000 | [diff] [blame] | 214 | return 0; |
Vikram S. Adve | 242a808 | 2002-05-19 15:25:51 +0000 | [diff] [blame] | 215 | } |
Vikram S. Adve | a44c6c0 | 2002-03-31 19:04:50 +0000 | [diff] [blame] | 216 | } |
| 217 | |
Ruchira Sasanka | d00982a | 2002-01-07 19:20:28 +0000 | [diff] [blame] | 218 | |
| 219 | //--------------------------------------------------------------------------- |
| 220 | // Finds the return address of a call sparc specific call instruction |
| 221 | //--------------------------------------------------------------------------- |
Ruchira Sasanka | b3b6f53 | 2001-10-21 16:43:41 +0000 | [diff] [blame] | 222 | |
Brian Gaeke | e3d6807 | 2004-02-25 18:44:15 +0000 | [diff] [blame] | 223 | // The following 4 methods are used to find the RegType (SparcV9Internals.h) |
Vikram S. Adve | 242a808 | 2002-05-19 15:25:51 +0000 | [diff] [blame] | 224 | // of a LiveRange, a Value, and for a given register unified reg number. |
Chris Lattner | 699683c | 2002-02-04 05:59:25 +0000 | [diff] [blame] | 225 | // |
Brian Gaeke | e3d6807 | 2004-02-25 18:44:15 +0000 | [diff] [blame] | 226 | int SparcV9RegInfo::getRegTypeForClassAndType(unsigned regClassID, |
Vikram S. Adve | 78a4f23 | 2003-05-27 00:02:22 +0000 | [diff] [blame] | 227 | const Type* type) const |
| 228 | { |
Vikram S. Adve | 242a808 | 2002-05-19 15:25:51 +0000 | [diff] [blame] | 229 | switch (regClassID) { |
Vikram S. Adve | 78a4f23 | 2003-05-27 00:02:22 +0000 | [diff] [blame] | 230 | case IntRegClassID: return IntRegType; |
| 231 | case FloatRegClassID: |
| 232 | if (type == Type::FloatTy) return FPSingleRegType; |
| 233 | else if (type == Type::DoubleTy) return FPDoubleRegType; |
| 234 | assert(0 && "Unknown type in FloatRegClass"); return 0; |
| 235 | case IntCCRegClassID: return IntCCRegType; |
| 236 | case FloatCCRegClassID: return FloatCCRegType; |
| 237 | case SpecialRegClassID: return SpecialRegType; |
Vikram S. Adve | 242a808 | 2002-05-19 15:25:51 +0000 | [diff] [blame] | 238 | default: assert( 0 && "Unknown reg class ID"); return 0; |
Chris Lattner | 699683c | 2002-02-04 05:59:25 +0000 | [diff] [blame] | 239 | } |
| 240 | } |
| 241 | |
Brian Gaeke | e3d6807 | 2004-02-25 18:44:15 +0000 | [diff] [blame] | 242 | int SparcV9RegInfo::getRegTypeForDataType(const Type* type) const |
Vikram S. Adve | 78a4f23 | 2003-05-27 00:02:22 +0000 | [diff] [blame] | 243 | { |
| 244 | return getRegTypeForClassAndType(getRegClassIDOfType(type), type); |
Vikram S. Adve | 242a808 | 2002-05-19 15:25:51 +0000 | [diff] [blame] | 245 | } |
| 246 | |
Brian Gaeke | e3d6807 | 2004-02-25 18:44:15 +0000 | [diff] [blame] | 247 | int SparcV9RegInfo::getRegTypeForLR(const LiveRange *LR) const |
Vikram S. Adve | 78a4f23 | 2003-05-27 00:02:22 +0000 | [diff] [blame] | 248 | { |
| 249 | return getRegTypeForClassAndType(LR->getRegClassID(), LR->getType()); |
| 250 | } |
Chris Lattner | 699683c | 2002-02-04 05:59:25 +0000 | [diff] [blame] | 251 | |
Brian Gaeke | e3d6807 | 2004-02-25 18:44:15 +0000 | [diff] [blame] | 252 | int SparcV9RegInfo::getRegType(int unifiedRegNum) const |
Vikram S. Adve | 78a4f23 | 2003-05-27 00:02:22 +0000 | [diff] [blame] | 253 | { |
Vikram S. Adve | 76ee6f7 | 2002-07-08 23:23:12 +0000 | [diff] [blame] | 254 | if (unifiedRegNum < 32) |
Chris Lattner | 699683c | 2002-02-04 05:59:25 +0000 | [diff] [blame] | 255 | return IntRegType; |
Vikram S. Adve | 76ee6f7 | 2002-07-08 23:23:12 +0000 | [diff] [blame] | 256 | else if (unifiedRegNum < (32 + 32)) |
Chris Lattner | 699683c | 2002-02-04 05:59:25 +0000 | [diff] [blame] | 257 | return FPSingleRegType; |
Vikram S. Adve | 76ee6f7 | 2002-07-08 23:23:12 +0000 | [diff] [blame] | 258 | else if (unifiedRegNum < (64 + 32)) |
Chris Lattner | 699683c | 2002-02-04 05:59:25 +0000 | [diff] [blame] | 259 | return FPDoubleRegType; |
Brian Gaeke | 6896a7d | 2004-04-21 17:53:58 +0000 | [diff] [blame] | 260 | else if (unifiedRegNum < (64+32+3)) |
| 261 | return IntCCRegType; |
| 262 | else if (unifiedRegNum < (64+32+3+4)) |
| 263 | return FloatCCRegType; |
| 264 | else if (unifiedRegNum < (64+32+3+4+1)) |
Brian Gaeke | 3f083d5 | 2004-04-20 20:12:57 +0000 | [diff] [blame] | 265 | return SpecialRegType; |
Chris Lattner | 699683c | 2002-02-04 05:59:25 +0000 | [diff] [blame] | 266 | else |
Vikram S. Adve | 76ee6f7 | 2002-07-08 23:23:12 +0000 | [diff] [blame] | 267 | assert(0 && "Invalid unified register number in getRegType"); |
Chris Lattner | 49b8a9c | 2002-02-24 23:02:40 +0000 | [diff] [blame] | 268 | return 0; |
Chris Lattner | 699683c | 2002-02-04 05:59:25 +0000 | [diff] [blame] | 269 | } |
| 270 | |
| 271 | |
Vikram S. Adve | 76ee6f7 | 2002-07-08 23:23:12 +0000 | [diff] [blame] | 272 | // To find the register class used for a specified Type |
| 273 | // |
Brian Gaeke | e3d6807 | 2004-02-25 18:44:15 +0000 | [diff] [blame] | 274 | unsigned SparcV9RegInfo::getRegClassIDOfType(const Type *type, |
Chris Lattner | b82d97e | 2002-07-25 06:08:32 +0000 | [diff] [blame] | 275 | bool isCCReg) const { |
Chris Lattner | f70c22b | 2004-06-17 18:19:28 +0000 | [diff] [blame] | 276 | Type::TypeID ty = type->getTypeID(); |
Vikram S. Adve | 76ee6f7 | 2002-07-08 23:23:12 +0000 | [diff] [blame] | 277 | unsigned res; |
| 278 | |
| 279 | // FIXME: Comparing types like this isn't very safe... |
| 280 | if ((ty && ty <= Type::LongTyID) || (ty == Type::LabelTyID) || |
| 281 | (ty == Type::FunctionTyID) || (ty == Type::PointerTyID) ) |
| 282 | res = IntRegClassID; // sparc int reg (ty=0: void) |
| 283 | else if (ty <= Type::DoubleTyID) |
| 284 | res = FloatRegClassID; // sparc float reg class |
| 285 | else { |
| 286 | //std::cerr << "TypeID: " << ty << "\n"; |
| 287 | assert(0 && "Cannot resolve register class for type"); |
| 288 | return 0; |
| 289 | } |
| 290 | |
Chris Lattner | 3c3c82d | 2003-01-15 21:14:32 +0000 | [diff] [blame] | 291 | if (isCCReg) |
| 292 | return res + 2; // corresponding condition code register |
Vikram S. Adve | 76ee6f7 | 2002-07-08 23:23:12 +0000 | [diff] [blame] | 293 | else |
| 294 | return res; |
| 295 | } |
| 296 | |
Brian Gaeke | e3d6807 | 2004-02-25 18:44:15 +0000 | [diff] [blame] | 297 | unsigned SparcV9RegInfo::getRegClassIDOfRegType(int regType) const { |
Vikram S. Adve | 76ee6f7 | 2002-07-08 23:23:12 +0000 | [diff] [blame] | 298 | switch(regType) { |
| 299 | case IntRegType: return IntRegClassID; |
| 300 | case FPSingleRegType: |
| 301 | case FPDoubleRegType: return FloatRegClassID; |
| 302 | case IntCCRegType: return IntCCRegClassID; |
| 303 | case FloatCCRegType: return FloatCCRegClassID; |
Brian Gaeke | 6896a7d | 2004-04-21 17:53:58 +0000 | [diff] [blame] | 304 | case SpecialRegType: return SpecialRegClassID; |
Vikram S. Adve | 76ee6f7 | 2002-07-08 23:23:12 +0000 | [diff] [blame] | 305 | default: |
| 306 | assert(0 && "Invalid register type in getRegClassIDOfRegType"); |
| 307 | return 0; |
| 308 | } |
| 309 | } |
| 310 | |
Ruchira Sasanka | d00982a | 2002-01-07 19:20:28 +0000 | [diff] [blame] | 311 | //--------------------------------------------------------------------------- |
Ruchira Sasanka | d00982a | 2002-01-07 19:20:28 +0000 | [diff] [blame] | 312 | // Suggests a register for the ret address in the RET machine instruction. |
| 313 | // We always suggest %i7 by convention. |
| 314 | //--------------------------------------------------------------------------- |
Brian Gaeke | e3d6807 | 2004-02-25 18:44:15 +0000 | [diff] [blame] | 315 | void SparcV9RegInfo::suggestReg4RetAddr(MachineInstr *RetMI, |
Ruchira Sasanka | cc3ccac | 2001-10-15 16:25:28 +0000 | [diff] [blame] | 316 | LiveRangeInfo& LRI) const { |
Ruchira Sasanka | 89fb46b | 2001-09-18 22:52:44 +0000 | [diff] [blame] | 317 | |
Chris Lattner | d029cd2 | 2004-06-02 05:55:25 +0000 | [diff] [blame] | 318 | assert(target.getInstrInfo()->isReturn(RetMI->getOpcode())); |
Vikram S. Adve | 53fec86 | 2001-10-22 13:41:12 +0000 | [diff] [blame] | 319 | |
Vikram S. Adve | 76ee6f7 | 2002-07-08 23:23:12 +0000 | [diff] [blame] | 320 | // return address is always mapped to i7 so set it immediately |
| 321 | RetMI->SetRegForOperand(0, getUnifiedRegNum(IntRegClassID, |
Brian Gaeke | e3d6807 | 2004-02-25 18:44:15 +0000 | [diff] [blame] | 322 | SparcV9IntRegClass::i7)); |
Vikram S. Adve | 53fec86 | 2001-10-22 13:41:12 +0000 | [diff] [blame] | 323 | |
Ruchira Sasanka | d00982a | 2002-01-07 19:20:28 +0000 | [diff] [blame] | 324 | // Possible Optimization: |
Ruchira Sasanka | c4d4b76 | 2001-10-16 01:23:19 +0000 | [diff] [blame] | 325 | // Instead of setting the color, we can suggest one. In that case, |
Ruchira Sasanka | cc3ccac | 2001-10-15 16:25:28 +0000 | [diff] [blame] | 326 | // we have to test later whether it received the suggested color. |
| 327 | // In that case, a LR has to be created at the start of method. |
| 328 | // It has to be done as follows (remove the setRegVal above): |
Ruchira Sasanka | 9144228 | 2001-09-30 23:16:47 +0000 | [diff] [blame] | 329 | |
Vikram S. Adve | 76ee6f7 | 2002-07-08 23:23:12 +0000 | [diff] [blame] | 330 | // MachineOperand & MO = RetMI->getOperand(0); |
Ruchira Sasanka | d00982a | 2002-01-07 19:20:28 +0000 | [diff] [blame] | 331 | // const Value *RetAddrVal = MO.getVRegValue(); |
| 332 | // assert( RetAddrVal && "LR for ret address must be created at start"); |
| 333 | // LiveRange * RetAddrLR = LRI.getLiveRangeForValue( RetAddrVal); |
| 334 | // RetAddrLR->setSuggestedColor(getUnifiedRegNum( IntRegClassID, |
Brian Gaeke | e3d6807 | 2004-02-25 18:44:15 +0000 | [diff] [blame] | 335 | // SparcV9IntRegOrdr::i7) ); |
Ruchira Sasanka | 9144228 | 2001-09-30 23:16:47 +0000 | [diff] [blame] | 336 | } |
| 337 | |
| 338 | |
| 339 | //--------------------------------------------------------------------------- |
Ruchira Sasanka | d00982a | 2002-01-07 19:20:28 +0000 | [diff] [blame] | 340 | // Suggests a register for the ret address in the JMPL/CALL machine instr. |
Brian Gaeke | e3d6807 | 2004-02-25 18:44:15 +0000 | [diff] [blame] | 341 | // SparcV9 ABI dictates that %o7 be used for this purpose. |
Ruchira Sasanka | 9144228 | 2001-09-30 23:16:47 +0000 | [diff] [blame] | 342 | //--------------------------------------------------------------------------- |
Vikram S. Adve | 8781765 | 2002-09-28 16:59:05 +0000 | [diff] [blame] | 343 | void |
Brian Gaeke | e3d6807 | 2004-02-25 18:44:15 +0000 | [diff] [blame] | 344 | SparcV9RegInfo::suggestReg4CallAddr(MachineInstr * CallMI, |
Vikram S. Adve | 8781765 | 2002-09-28 16:59:05 +0000 | [diff] [blame] | 345 | LiveRangeInfo& LRI) const |
| 346 | { |
Vikram S. Adve | 242a808 | 2002-05-19 15:25:51 +0000 | [diff] [blame] | 347 | CallArgsDescriptor* argDesc = CallArgsDescriptor::get(CallMI); |
| 348 | const Value *RetAddrVal = argDesc->getReturnAddrReg(); |
Vikram S. Adve | 8781765 | 2002-09-28 16:59:05 +0000 | [diff] [blame] | 349 | assert(RetAddrVal && "INTERNAL ERROR: Return address value is required"); |
Ruchira Sasanka | 9144228 | 2001-09-30 23:16:47 +0000 | [diff] [blame] | 350 | |
Vikram S. Adve | 8781765 | 2002-09-28 16:59:05 +0000 | [diff] [blame] | 351 | // A LR must already exist for the return address. |
| 352 | LiveRange *RetAddrLR = LRI.getLiveRangeForValue(RetAddrVal); |
| 353 | assert(RetAddrLR && "INTERNAL ERROR: No LR for return address of call!"); |
| 354 | |
Chris Lattner | 3c3c82d | 2003-01-15 21:14:32 +0000 | [diff] [blame] | 355 | unsigned RegClassID = RetAddrLR->getRegClassID(); |
Brian Gaeke | e3d6807 | 2004-02-25 18:44:15 +0000 | [diff] [blame] | 356 | RetAddrLR->setColor(getUnifiedRegNum(IntRegClassID, SparcV9IntRegClass::o7)); |
Vikram S. Adve | 8781765 | 2002-09-28 16:59:05 +0000 | [diff] [blame] | 357 | } |
Ruchira Sasanka | cc3ccac | 2001-10-15 16:25:28 +0000 | [diff] [blame] | 358 | |
| 359 | |
Ruchira Sasanka | 9144228 | 2001-09-30 23:16:47 +0000 | [diff] [blame] | 360 | |
| 361 | //--------------------------------------------------------------------------- |
| 362 | // This method will suggest colors to incoming args to a method. |
Brian Gaeke | e3d6807 | 2004-02-25 18:44:15 +0000 | [diff] [blame] | 363 | // According to the SparcV9 ABI, the first 6 incoming args are in |
Ruchira Sasanka | d00982a | 2002-01-07 19:20:28 +0000 | [diff] [blame] | 364 | // %i0 - %i5 (if they are integer) OR in %f0 - %f31 (if they are float). |
Ruchira Sasanka | 9144228 | 2001-09-30 23:16:47 +0000 | [diff] [blame] | 365 | // If the arg is passed on stack due to the lack of regs, NOTHING will be |
Ruchira Sasanka | d00982a | 2002-01-07 19:20:28 +0000 | [diff] [blame] | 366 | // done - it will be colored (or spilled) as a normal live range. |
Ruchira Sasanka | 9144228 | 2001-09-30 23:16:47 +0000 | [diff] [blame] | 367 | //--------------------------------------------------------------------------- |
Brian Gaeke | e3d6807 | 2004-02-25 18:44:15 +0000 | [diff] [blame] | 368 | void SparcV9RegInfo::suggestRegs4MethodArgs(const Function *Meth, |
Ruchira Sasanka | 9144228 | 2001-09-30 23:16:47 +0000 | [diff] [blame] | 369 | LiveRangeInfo& LRI) const |
Chris Lattner | 20b1ea0 | 2001-09-14 03:47:57 +0000 | [diff] [blame] | 370 | { |
Vikram S. Adve | 7dc7de5 | 2003-07-25 21:12:15 +0000 | [diff] [blame] | 371 | // Check if this is a varArgs function. needed for choosing regs. |
Vikram S. Adve | 31f78c4 | 2002-04-25 04:42:21 +0000 | [diff] [blame] | 372 | bool isVarArgs = isVarArgsFunction(Meth->getType()); |
| 373 | |
Vikram S. Adve | 7dc7de5 | 2003-07-25 21:12:15 +0000 | [diff] [blame] | 374 | // Count the arguments, *ignoring* whether they are int or FP args. |
| 375 | // Use this common arg numbering to pick the right int or fp register. |
| 376 | unsigned argNo=0; |
Chris Lattner | e4d5c44 | 2005-03-15 04:54:21 +0000 | [diff] [blame^] | 377 | for(Function::const_arg_iterator I = Meth->arg_begin(), E = Meth->arg_end(); |
Chris Lattner | 0b12b5f | 2002-06-25 16:13:21 +0000 | [diff] [blame] | 378 | I != E; ++I, ++argNo) { |
Chris Lattner | 0b12b5f | 2002-06-25 16:13:21 +0000 | [diff] [blame] | 379 | LiveRange *LR = LRI.getLiveRangeForValue(I); |
| 380 | assert(LR && "No live range found for method arg"); |
| 381 | |
Vikram S. Adve | 7dc7de5 | 2003-07-25 21:12:15 +0000 | [diff] [blame] | 382 | unsigned regType = getRegTypeForLR(LR); |
| 383 | unsigned regClassIDOfArgReg = BadRegClass; // for chosen reg (unused) |
Chris Lattner | 0b12b5f | 2002-06-25 16:13:21 +0000 | [diff] [blame] | 384 | |
| 385 | int regNum = (regType == IntRegType) |
Vikram S. Adve | 7dc7de5 | 2003-07-25 21:12:15 +0000 | [diff] [blame] | 386 | ? regNumForIntArg(/*inCallee*/ true, isVarArgs, argNo, regClassIDOfArgReg) |
| 387 | : regNumForFPArg(regType, /*inCallee*/ true, isVarArgs, argNo, |
| 388 | regClassIDOfArgReg); |
Chris Lattner | 0b12b5f | 2002-06-25 16:13:21 +0000 | [diff] [blame] | 389 | |
Vikram S. Adve | 7dc7de5 | 2003-07-25 21:12:15 +0000 | [diff] [blame] | 390 | if (regNum != getInvalidRegNum()) |
Chris Lattner | 0b12b5f | 2002-06-25 16:13:21 +0000 | [diff] [blame] | 391 | LR->setSuggestedColor(regNum); |
| 392 | } |
Chris Lattner | 20b1ea0 | 2001-09-14 03:47:57 +0000 | [diff] [blame] | 393 | } |
| 394 | |
Ruchira Sasanka | 9144228 | 2001-09-30 23:16:47 +0000 | [diff] [blame] | 395 | |
Ruchira Sasanka | d00982a | 2002-01-07 19:20:28 +0000 | [diff] [blame] | 396 | //--------------------------------------------------------------------------- |
| 397 | // This method is called after graph coloring to move incoming args to |
| 398 | // the correct hardware registers if they did not receive the correct |
| 399 | // (suggested) color through graph coloring. |
| 400 | //--------------------------------------------------------------------------- |
Brian Gaeke | e3d6807 | 2004-02-25 18:44:15 +0000 | [diff] [blame] | 401 | void SparcV9RegInfo::colorMethodArgs(const Function *Meth, |
Vikram S. Adve | 83d30c8 | 2003-07-29 19:53:21 +0000 | [diff] [blame] | 402 | LiveRangeInfo &LRI, |
| 403 | std::vector<MachineInstr*>& InstrnsBefore, |
| 404 | std::vector<MachineInstr*>& InstrnsAfter) const { |
Ruchira Sasanka | 9144228 | 2001-09-30 23:16:47 +0000 | [diff] [blame] | 405 | |
Vikram S. Adve | 31f78c4 | 2002-04-25 04:42:21 +0000 | [diff] [blame] | 406 | // check if this is a varArgs function. needed for choosing regs. |
| 407 | bool isVarArgs = isVarArgsFunction(Meth->getType()); |
Ruchira Sasanka | 9144228 | 2001-09-30 23:16:47 +0000 | [diff] [blame] | 408 | MachineInstr *AdMI; |
| 409 | |
Ruchira Sasanka | 9144228 | 2001-09-30 23:16:47 +0000 | [diff] [blame] | 410 | // for each argument |
Chris Lattner | 0b12b5f | 2002-06-25 16:13:21 +0000 | [diff] [blame] | 411 | // for each argument. count INT and FP arguments separately. |
| 412 | unsigned argNo=0, intArgNo=0, fpArgNo=0; |
Chris Lattner | e4d5c44 | 2005-03-15 04:54:21 +0000 | [diff] [blame^] | 413 | for(Function::const_arg_iterator I = Meth->arg_begin(), E = Meth->arg_end(); |
Chris Lattner | 0b12b5f | 2002-06-25 16:13:21 +0000 | [diff] [blame] | 414 | I != E; ++I, ++argNo) { |
Ruchira Sasanka | 9144228 | 2001-09-30 23:16:47 +0000 | [diff] [blame] | 415 | // get the LR of arg |
Chris Lattner | 0b12b5f | 2002-06-25 16:13:21 +0000 | [diff] [blame] | 416 | LiveRange *LR = LRI.getLiveRangeForValue(I); |
Ruchira Sasanka | 9144228 | 2001-09-30 23:16:47 +0000 | [diff] [blame] | 417 | assert( LR && "No live range found for method arg"); |
| 418 | |
Vikram S. Adve | 7dc7de5 | 2003-07-25 21:12:15 +0000 | [diff] [blame] | 419 | unsigned regType = getRegTypeForLR(LR); |
Chris Lattner | 3c3c82d | 2003-01-15 21:14:32 +0000 | [diff] [blame] | 420 | unsigned RegClassID = LR->getRegClassID(); |
Vikram S. Adve | 31f78c4 | 2002-04-25 04:42:21 +0000 | [diff] [blame] | 421 | |
Ruchira Sasanka | d00982a | 2002-01-07 19:20:28 +0000 | [diff] [blame] | 422 | // Find whether this argument is coming in a register (if not, on stack) |
Vikram S. Adve | 31f78c4 | 2002-04-25 04:42:21 +0000 | [diff] [blame] | 423 | // Also find the correct register the argument must use (UniArgReg) |
Ruchira Sasanka | d00982a | 2002-01-07 19:20:28 +0000 | [diff] [blame] | 424 | // |
Ruchira Sasanka | 9144228 | 2001-09-30 23:16:47 +0000 | [diff] [blame] | 425 | bool isArgInReg = false; |
Vikram S. Adve | d0d06ad | 2003-05-31 07:32:01 +0000 | [diff] [blame] | 426 | unsigned UniArgReg = getInvalidRegNum(); // reg that LR MUST be colored with |
Chris Lattner | 92ba2aa | 2003-01-14 23:05:08 +0000 | [diff] [blame] | 427 | unsigned regClassIDOfArgReg = BadRegClass; // reg class of chosen reg |
Vikram S. Adve | 31f78c4 | 2002-04-25 04:42:21 +0000 | [diff] [blame] | 428 | |
| 429 | int regNum = (regType == IntRegType) |
Vikram S. Adve | 242a808 | 2002-05-19 15:25:51 +0000 | [diff] [blame] | 430 | ? regNumForIntArg(/*inCallee*/ true, isVarArgs, |
Vikram S. Adve | d0d06ad | 2003-05-31 07:32:01 +0000 | [diff] [blame] | 431 | argNo, regClassIDOfArgReg) |
Vikram S. Adve | 242a808 | 2002-05-19 15:25:51 +0000 | [diff] [blame] | 432 | : regNumForFPArg(regType, /*inCallee*/ true, isVarArgs, |
Vikram S. Adve | d0d06ad | 2003-05-31 07:32:01 +0000 | [diff] [blame] | 433 | argNo, regClassIDOfArgReg); |
Vikram S. Adve | 31f78c4 | 2002-04-25 04:42:21 +0000 | [diff] [blame] | 434 | |
Vikram S. Adve | d0d06ad | 2003-05-31 07:32:01 +0000 | [diff] [blame] | 435 | if(regNum != getInvalidRegNum()) { |
Ruchira Sasanka | 9144228 | 2001-09-30 23:16:47 +0000 | [diff] [blame] | 436 | isArgInReg = true; |
Vikram S. Adve | 31f78c4 | 2002-04-25 04:42:21 +0000 | [diff] [blame] | 437 | UniArgReg = getUnifiedRegNum( regClassIDOfArgReg, regNum); |
Ruchira Sasanka | 9144228 | 2001-09-30 23:16:47 +0000 | [diff] [blame] | 438 | } |
Ruchira Sasanka | 9144228 | 2001-09-30 23:16:47 +0000 | [diff] [blame] | 439 | |
Vikram S. Adve | b15f8d4 | 2003-07-10 19:42:11 +0000 | [diff] [blame] | 440 | if( ! LR->isMarkedForSpill() ) { // if this arg received a register |
Ruchira Sasanka | 9144228 | 2001-09-30 23:16:47 +0000 | [diff] [blame] | 441 | |
Ruchira Sasanka | c74a720 | 2001-10-24 15:56:58 +0000 | [diff] [blame] | 442 | unsigned UniLRReg = getUnifiedRegNum( RegClassID, LR->getColor() ); |
| 443 | |
| 444 | // if LR received the correct color, nothing to do |
Ruchira Sasanka | d00982a | 2002-01-07 19:20:28 +0000 | [diff] [blame] | 445 | // |
Ruchira Sasanka | c74a720 | 2001-10-24 15:56:58 +0000 | [diff] [blame] | 446 | if( UniLRReg == UniArgReg ) |
| 447 | continue; |
| 448 | |
Ruchira Sasanka | d00982a | 2002-01-07 19:20:28 +0000 | [diff] [blame] | 449 | // We are here because the LR did not receive the suggested |
| 450 | // but LR received another register. |
| 451 | // Now we have to copy the %i reg (or stack pos of arg) |
| 452 | // to the register the LR was colored with. |
Ruchira Sasanka | c74a720 | 2001-10-24 15:56:58 +0000 | [diff] [blame] | 453 | |
Ruchira Sasanka | d00982a | 2002-01-07 19:20:28 +0000 | [diff] [blame] | 454 | // if the arg is coming in UniArgReg register, it MUST go into |
Ruchira Sasanka | c74a720 | 2001-10-24 15:56:58 +0000 | [diff] [blame] | 455 | // the UniLRReg register |
Ruchira Sasanka | d00982a | 2002-01-07 19:20:28 +0000 | [diff] [blame] | 456 | // |
Vikram S. Adve | 31f78c4 | 2002-04-25 04:42:21 +0000 | [diff] [blame] | 457 | if( isArgInReg ) { |
Vikram S. Adve | 31f78c4 | 2002-04-25 04:42:21 +0000 | [diff] [blame] | 458 | if( regClassIDOfArgReg != RegClassID ) { |
Brian Gaeke | 2ff1e67 | 2004-08-24 06:41:40 +0000 | [diff] [blame] | 459 | // NOTE: This code has not been well-tested. |
Vikram S. Adve | 31f78c4 | 2002-04-25 04:42:21 +0000 | [diff] [blame] | 460 | |
| 461 | // It is a variable argument call: the float reg must go in a %o reg. |
| 462 | // We have to move an int reg to a float reg via memory. |
| 463 | // |
| 464 | assert(isVarArgs && |
| 465 | RegClassID == FloatRegClassID && |
| 466 | regClassIDOfArgReg == IntRegClassID && |
| 467 | "This should only be an Int register for an FP argument"); |
| 468 | |
Chris Lattner | a1e51ff | 2004-08-18 18:13:37 +0000 | [diff] [blame] | 469 | int TmpOff = MachineFunction::get(Meth).getInfo<SparcV9FunctionInfo>()->pushTempValue( |
Vikram S. Adve | 31f78c4 | 2002-04-25 04:42:21 +0000 | [diff] [blame] | 470 | getSpilledRegSize(regType)); |
Vikram S. Adve | 83d30c8 | 2003-07-29 19:53:21 +0000 | [diff] [blame] | 471 | cpReg2MemMI(InstrnsBefore, |
Vikram S. Adve | 76ee6f7 | 2002-07-08 23:23:12 +0000 | [diff] [blame] | 472 | UniArgReg, getFramePointer(), TmpOff, IntRegType); |
Vikram S. Adve | 31f78c4 | 2002-04-25 04:42:21 +0000 | [diff] [blame] | 473 | |
Vikram S. Adve | 83d30c8 | 2003-07-29 19:53:21 +0000 | [diff] [blame] | 474 | cpMem2RegMI(InstrnsBefore, |
Vikram S. Adve | 76ee6f7 | 2002-07-08 23:23:12 +0000 | [diff] [blame] | 475 | getFramePointer(), TmpOff, UniLRReg, regType); |
Vikram S. Adve | 31f78c4 | 2002-04-25 04:42:21 +0000 | [diff] [blame] | 476 | } |
| 477 | else { |
Vikram S. Adve | 83d30c8 | 2003-07-29 19:53:21 +0000 | [diff] [blame] | 478 | cpReg2RegMI(InstrnsBefore, UniArgReg, UniLRReg, regType); |
Vikram S. Adve | 31f78c4 | 2002-04-25 04:42:21 +0000 | [diff] [blame] | 479 | } |
| 480 | } |
Ruchira Sasanka | 20c82b1 | 2001-10-28 18:15:12 +0000 | [diff] [blame] | 481 | else { |
Ruchira Sasanka | 9144228 | 2001-09-30 23:16:47 +0000 | [diff] [blame] | 482 | |
Misha Brukman | cf00c4a | 2003-10-10 17:57:28 +0000 | [diff] [blame] | 483 | // Now the arg is coming on stack. Since the LR received a register, |
Ruchira Sasanka | 20c82b1 | 2001-10-28 18:15:12 +0000 | [diff] [blame] | 484 | // we just have to load the arg on stack into that register |
Ruchira Sasanka | d00982a | 2002-01-07 19:20:28 +0000 | [diff] [blame] | 485 | // |
Chris Lattner | d029cd2 | 2004-06-02 05:55:25 +0000 | [diff] [blame] | 486 | const TargetFrameInfo& frameInfo = *target.getFrameInfo(); |
Vikram S. Adve | 1c0fba6 | 2001-11-08 04:56:41 +0000 | [diff] [blame] | 487 | int offsetFromFP = |
Misha Brukman | fce1143 | 2002-10-28 00:28:31 +0000 | [diff] [blame] | 488 | frameInfo.getIncomingArgOffset(MachineFunction::get(Meth), |
Vikram S. Adve | 31f78c4 | 2002-04-25 04:42:21 +0000 | [diff] [blame] | 489 | argNo); |
Vikram S. Adve | d0d06ad | 2003-05-31 07:32:01 +0000 | [diff] [blame] | 490 | |
| 491 | // float arguments on stack are right justified so adjust the offset! |
| 492 | // int arguments are also right justified but they are always loaded as |
| 493 | // a full double-word so the offset does not need to be adjusted. |
| 494 | if (regType == FPSingleRegType) { |
| 495 | unsigned argSize = target.getTargetData().getTypeSize(LR->getType()); |
Chris Lattner | 750d723 | 2004-08-12 18:29:05 +0000 | [diff] [blame] | 496 | unsigned slotSize = SparcV9FrameInfo::SizeOfEachArgOnStack; |
Vikram S. Adve | d0d06ad | 2003-05-31 07:32:01 +0000 | [diff] [blame] | 497 | assert(argSize <= slotSize && "Insufficient slot size!"); |
| 498 | offsetFromFP += slotSize - argSize; |
| 499 | } |
| 500 | |
Vikram S. Adve | 83d30c8 | 2003-07-29 19:53:21 +0000 | [diff] [blame] | 501 | cpMem2RegMI(InstrnsBefore, |
Vikram S. Adve | 76ee6f7 | 2002-07-08 23:23:12 +0000 | [diff] [blame] | 502 | getFramePointer(), offsetFromFP, UniLRReg, regType); |
Ruchira Sasanka | 20c82b1 | 2001-10-28 18:15:12 +0000 | [diff] [blame] | 503 | } |
Ruchira Sasanka | 20c82b1 | 2001-10-28 18:15:12 +0000 | [diff] [blame] | 504 | |
| 505 | } // if LR received a color |
| 506 | |
| 507 | else { |
| 508 | |
| 509 | // Now, the LR did not receive a color. But it has a stack offset for |
| 510 | // spilling. |
Ruchira Sasanka | 20c82b1 | 2001-10-28 18:15:12 +0000 | [diff] [blame] | 511 | // So, if the arg is coming in UniArgReg register, we can just move |
| 512 | // that on to the stack pos of LR |
| 513 | |
Ruchira Sasanka | 20c82b1 | 2001-10-28 18:15:12 +0000 | [diff] [blame] | 514 | if( isArgInReg ) { |
Vikram S. Adve | 31f78c4 | 2002-04-25 04:42:21 +0000 | [diff] [blame] | 515 | |
| 516 | if( regClassIDOfArgReg != RegClassID ) { |
| 517 | assert(0 && |
| 518 | "FP arguments to a varargs function should be explicitly " |
| 519 | "copied to/from int registers by instruction selection!"); |
| 520 | |
| 521 | // It must be a float arg for a variable argument call, which |
| 522 | // must come in a %o reg. Move the int reg to the stack. |
| 523 | // |
| 524 | assert(isVarArgs && regClassIDOfArgReg == IntRegClassID && |
| 525 | "This should only be an Int register for an FP argument"); |
| 526 | |
Vikram S. Adve | 83d30c8 | 2003-07-29 19:53:21 +0000 | [diff] [blame] | 527 | cpReg2MemMI(InstrnsBefore, UniArgReg, |
Vikram S. Adve | 76ee6f7 | 2002-07-08 23:23:12 +0000 | [diff] [blame] | 528 | getFramePointer(), LR->getSpillOffFromFP(), IntRegType); |
Vikram S. Adve | 31f78c4 | 2002-04-25 04:42:21 +0000 | [diff] [blame] | 529 | } |
| 530 | else { |
Vikram S. Adve | 83d30c8 | 2003-07-29 19:53:21 +0000 | [diff] [blame] | 531 | cpReg2MemMI(InstrnsBefore, UniArgReg, |
Vikram S. Adve | 76ee6f7 | 2002-07-08 23:23:12 +0000 | [diff] [blame] | 532 | getFramePointer(), LR->getSpillOffFromFP(), regType); |
Vikram S. Adve | 31f78c4 | 2002-04-25 04:42:21 +0000 | [diff] [blame] | 533 | } |
Ruchira Sasanka | 20c82b1 | 2001-10-28 18:15:12 +0000 | [diff] [blame] | 534 | } |
| 535 | |
| 536 | else { |
| 537 | |
| 538 | // Now the arg is coming on stack. Since the LR did NOT |
Misha Brukman | cf00c4a | 2003-10-10 17:57:28 +0000 | [diff] [blame] | 539 | // received a register as well, it is allocated a stack position. We |
Vikram S. Adve | 31f78c4 | 2002-04-25 04:42:21 +0000 | [diff] [blame] | 540 | // can simply change the stack position of the LR. We can do this, |
Ruchira Sasanka | 20c82b1 | 2001-10-28 18:15:12 +0000 | [diff] [blame] | 541 | // since this method is called before any other method that makes |
| 542 | // uses of the stack pos of the LR (e.g., updateMachineInstr) |
Vikram S. Adve | d0d06ad | 2003-05-31 07:32:01 +0000 | [diff] [blame] | 543 | // |
Chris Lattner | d029cd2 | 2004-06-02 05:55:25 +0000 | [diff] [blame] | 544 | const TargetFrameInfo& frameInfo = *target.getFrameInfo(); |
Vikram S. Adve | 1c0fba6 | 2001-11-08 04:56:41 +0000 | [diff] [blame] | 545 | int offsetFromFP = |
Misha Brukman | fce1143 | 2002-10-28 00:28:31 +0000 | [diff] [blame] | 546 | frameInfo.getIncomingArgOffset(MachineFunction::get(Meth), |
Vikram S. Adve | 31f78c4 | 2002-04-25 04:42:21 +0000 | [diff] [blame] | 547 | argNo); |
Vikram S. Adve | d0d06ad | 2003-05-31 07:32:01 +0000 | [diff] [blame] | 548 | |
| 549 | // FP arguments on stack are right justified so adjust offset! |
| 550 | // int arguments are also right justified but they are always loaded as |
| 551 | // a full double-word so the offset does not need to be adjusted. |
| 552 | if (regType == FPSingleRegType) { |
| 553 | unsigned argSize = target.getTargetData().getTypeSize(LR->getType()); |
Chris Lattner | 750d723 | 2004-08-12 18:29:05 +0000 | [diff] [blame] | 554 | unsigned slotSize = SparcV9FrameInfo::SizeOfEachArgOnStack; |
Vikram S. Adve | d0d06ad | 2003-05-31 07:32:01 +0000 | [diff] [blame] | 555 | assert(argSize <= slotSize && "Insufficient slot size!"); |
| 556 | offsetFromFP += slotSize - argSize; |
| 557 | } |
Vikram S. Adve | 1c0fba6 | 2001-11-08 04:56:41 +0000 | [diff] [blame] | 558 | |
| 559 | LR->modifySpillOffFromFP( offsetFromFP ); |
Ruchira Sasanka | 20c82b1 | 2001-10-28 18:15:12 +0000 | [diff] [blame] | 560 | } |
Ruchira Sasanka | 9144228 | 2001-09-30 23:16:47 +0000 | [diff] [blame] | 561 | |
| 562 | } |
| 563 | |
Ruchira Sasanka | 9144228 | 2001-09-30 23:16:47 +0000 | [diff] [blame] | 564 | } // for each incoming argument |
| 565 | |
| 566 | } |
| 567 | |
Chris Lattner | 20b1ea0 | 2001-09-14 03:47:57 +0000 | [diff] [blame] | 568 | |
| 569 | |
Ruchira Sasanka | 9144228 | 2001-09-30 23:16:47 +0000 | [diff] [blame] | 570 | //--------------------------------------------------------------------------- |
| 571 | // This method is called before graph coloring to suggest colors to the |
| 572 | // outgoing call args and the return value of the call. |
| 573 | //--------------------------------------------------------------------------- |
Brian Gaeke | e3d6807 | 2004-02-25 18:44:15 +0000 | [diff] [blame] | 574 | void SparcV9RegInfo::suggestRegs4CallArgs(MachineInstr *CallMI, |
Vikram S. Adve | 8781765 | 2002-09-28 16:59:05 +0000 | [diff] [blame] | 575 | LiveRangeInfo& LRI) const { |
Chris Lattner | d029cd2 | 2004-06-02 05:55:25 +0000 | [diff] [blame] | 576 | assert ( (target.getInstrInfo())->isCall(CallMI->getOpcode()) ); |
Chris Lattner | 20b1ea0 | 2001-09-14 03:47:57 +0000 | [diff] [blame] | 577 | |
Vikram S. Adve | 242a808 | 2002-05-19 15:25:51 +0000 | [diff] [blame] | 578 | CallArgsDescriptor* argDesc = CallArgsDescriptor::get(CallMI); |
Vikram S. Adve | 31f78c4 | 2002-04-25 04:42:21 +0000 | [diff] [blame] | 579 | |
Vikram S. Adve | 8781765 | 2002-09-28 16:59:05 +0000 | [diff] [blame] | 580 | suggestReg4CallAddr(CallMI, LRI); |
Ruchira Sasanka | cc3ccac | 2001-10-15 16:25:28 +0000 | [diff] [blame] | 581 | |
Vikram S. Adve | 8781765 | 2002-09-28 16:59:05 +0000 | [diff] [blame] | 582 | // First color the return value of the call instruction, if any. |
| 583 | // The return value will be in %o0 if the value is an integer type, |
| 584 | // or in %f0 if the value is a float type. |
| 585 | // |
| 586 | if (const Value *RetVal = argDesc->getReturnValue()) { |
| 587 | LiveRange *RetValLR = LRI.getLiveRangeForValue(RetVal); |
| 588 | assert(RetValLR && "No LR for return Value of call!"); |
Ruchira Sasanka | 89fb46b | 2001-09-18 22:52:44 +0000 | [diff] [blame] | 589 | |
Chris Lattner | 3c3c82d | 2003-01-15 21:14:32 +0000 | [diff] [blame] | 590 | unsigned RegClassID = RetValLR->getRegClassID(); |
Ruchira Sasanka | 89fb46b | 2001-09-18 22:52:44 +0000 | [diff] [blame] | 591 | |
Ruchira Sasanka | b3b6f53 | 2001-10-21 16:43:41 +0000 | [diff] [blame] | 592 | // now suggest a register depending on the register class of ret arg |
Ruchira Sasanka | b3b6f53 | 2001-10-21 16:43:41 +0000 | [diff] [blame] | 593 | if( RegClassID == IntRegClassID ) |
Brian Gaeke | e3d6807 | 2004-02-25 18:44:15 +0000 | [diff] [blame] | 594 | RetValLR->setSuggestedColor(SparcV9IntRegClass::o0); |
Ruchira Sasanka | b3b6f53 | 2001-10-21 16:43:41 +0000 | [diff] [blame] | 595 | else if (RegClassID == FloatRegClassID ) |
Brian Gaeke | e3d6807 | 2004-02-25 18:44:15 +0000 | [diff] [blame] | 596 | RetValLR->setSuggestedColor(SparcV9FloatRegClass::f0 ); |
Ruchira Sasanka | b3b6f53 | 2001-10-21 16:43:41 +0000 | [diff] [blame] | 597 | else assert( 0 && "Unknown reg class for return value of call\n"); |
Chris Lattner | 20b1ea0 | 2001-09-14 03:47:57 +0000 | [diff] [blame] | 598 | } |
Ruchira Sasanka | 89fb46b | 2001-09-18 22:52:44 +0000 | [diff] [blame] | 599 | |
Ruchira Sasanka | 9144228 | 2001-09-30 23:16:47 +0000 | [diff] [blame] | 600 | // Now suggest colors for arguments (operands) of the call instruction. |
| 601 | // Colors are suggested only if the arg number is smaller than the |
| 602 | // the number of registers allocated for argument passing. |
Ruchira Sasanka | b3b6f53 | 2001-10-21 16:43:41 +0000 | [diff] [blame] | 603 | // Now, go thru call args - implicit operands of the call MI |
Ruchira Sasanka | 89fb46b | 2001-09-18 22:52:44 +0000 | [diff] [blame] | 604 | |
Vikram S. Adve | 242a808 | 2002-05-19 15:25:51 +0000 | [diff] [blame] | 605 | unsigned NumOfCallArgs = argDesc->getNumArgs(); |
Ruchira Sasanka | 9144228 | 2001-09-30 23:16:47 +0000 | [diff] [blame] | 606 | |
Vikram S. Adve | 31f78c4 | 2002-04-25 04:42:21 +0000 | [diff] [blame] | 607 | for(unsigned argNo=0, i=0, intArgNo=0, fpArgNo=0; |
| 608 | i < NumOfCallArgs; ++i, ++argNo) { |
Ruchira Sasanka | cc3ccac | 2001-10-15 16:25:28 +0000 | [diff] [blame] | 609 | |
Vikram S. Adve | 242a808 | 2002-05-19 15:25:51 +0000 | [diff] [blame] | 610 | const Value *CallArg = argDesc->getArgInfo(i).getArgVal(); |
Ruchira Sasanka | 9144228 | 2001-09-30 23:16:47 +0000 | [diff] [blame] | 611 | |
| 612 | // get the LR of call operand (parameter) |
Ruchira Sasanka | cc3ccac | 2001-10-15 16:25:28 +0000 | [diff] [blame] | 613 | LiveRange *const LR = LRI.getLiveRangeForValue(CallArg); |
Vikram S. Adve | d0d06ad | 2003-05-31 07:32:01 +0000 | [diff] [blame] | 614 | if (!LR) |
| 615 | continue; // no live ranges for constants and labels |
Vikram S. Adve | 8781765 | 2002-09-28 16:59:05 +0000 | [diff] [blame] | 616 | |
Vikram S. Adve | 7dc7de5 | 2003-07-25 21:12:15 +0000 | [diff] [blame] | 617 | unsigned regType = getRegTypeForLR(LR); |
Vikram S. Adve | d0d06ad | 2003-05-31 07:32:01 +0000 | [diff] [blame] | 618 | unsigned regClassIDOfArgReg = BadRegClass; // chosen reg class (unused) |
Vikram S. Adve | 8781765 | 2002-09-28 16:59:05 +0000 | [diff] [blame] | 619 | |
Vikram S. Adve | 31f78c4 | 2002-04-25 04:42:21 +0000 | [diff] [blame] | 620 | // Choose a register for this arg depending on whether it is |
Vikram S. Adve | 242a808 | 2002-05-19 15:25:51 +0000 | [diff] [blame] | 621 | // an INT or FP value. Here we ignore whether or not it is a |
| 622 | // varargs calls, because FP arguments will be explicitly copied |
| 623 | // to an integer Value and handled under (argCopy != NULL) below. |
Vikram S. Adve | 31f78c4 | 2002-04-25 04:42:21 +0000 | [diff] [blame] | 624 | int regNum = (regType == IntRegType) |
Vikram S. Adve | 242a808 | 2002-05-19 15:25:51 +0000 | [diff] [blame] | 625 | ? regNumForIntArg(/*inCallee*/ false, /*isVarArgs*/ false, |
Vikram S. Adve | d0d06ad | 2003-05-31 07:32:01 +0000 | [diff] [blame] | 626 | argNo, regClassIDOfArgReg) |
Vikram S. Adve | 242a808 | 2002-05-19 15:25:51 +0000 | [diff] [blame] | 627 | : regNumForFPArg(regType, /*inCallee*/ false, /*isVarArgs*/ false, |
Vikram S. Adve | d0d06ad | 2003-05-31 07:32:01 +0000 | [diff] [blame] | 628 | argNo, regClassIDOfArgReg); |
Ruchira Sasanka | 9144228 | 2001-09-30 23:16:47 +0000 | [diff] [blame] | 629 | |
Vikram S. Adve | 31f78c4 | 2002-04-25 04:42:21 +0000 | [diff] [blame] | 630 | // If a register could be allocated, use it. |
| 631 | // If not, do NOTHING as this will be colored as a normal value. |
Vikram S. Adve | d0d06ad | 2003-05-31 07:32:01 +0000 | [diff] [blame] | 632 | if(regNum != getInvalidRegNum()) |
Vikram S. Adve | 31f78c4 | 2002-04-25 04:42:21 +0000 | [diff] [blame] | 633 | LR->setSuggestedColor(regNum); |
Ruchira Sasanka | 9144228 | 2001-09-30 23:16:47 +0000 | [diff] [blame] | 634 | } // for all call arguments |
Chris Lattner | 20b1ea0 | 2001-09-14 03:47:57 +0000 | [diff] [blame] | 635 | } |
| 636 | |
| 637 | |
Ruchira Sasanka | 9144228 | 2001-09-30 23:16:47 +0000 | [diff] [blame] | 638 | //--------------------------------------------------------------------------- |
Anand Shukla | 55afc33 | 2003-06-01 02:48:23 +0000 | [diff] [blame] | 639 | // this method is called for an LLVM return instruction to identify which |
Ruchira Sasanka | 9144228 | 2001-09-30 23:16:47 +0000 | [diff] [blame] | 640 | // values will be returned from this method and to suggest colors. |
| 641 | //--------------------------------------------------------------------------- |
Brian Gaeke | e3d6807 | 2004-02-25 18:44:15 +0000 | [diff] [blame] | 642 | void SparcV9RegInfo::suggestReg4RetValue(MachineInstr *RetMI, |
Vikram S. Adve | 83d30c8 | 2003-07-29 19:53:21 +0000 | [diff] [blame] | 643 | LiveRangeInfo& LRI) const { |
Ruchira Sasanka | 89fb46b | 2001-09-18 22:52:44 +0000 | [diff] [blame] | 644 | |
Chris Lattner | d029cd2 | 2004-06-02 05:55:25 +0000 | [diff] [blame] | 645 | assert( target.getInstrInfo()->isReturn( RetMI->getOpcode() ) ); |
Ruchira Sasanka | 89fb46b | 2001-09-18 22:52:44 +0000 | [diff] [blame] | 646 | |
Vikram S. Adve | 76ee6f7 | 2002-07-08 23:23:12 +0000 | [diff] [blame] | 647 | suggestReg4RetAddr(RetMI, LRI); |
Ruchira Sasanka | 89fb46b | 2001-09-18 22:52:44 +0000 | [diff] [blame] | 648 | |
Vikram S. Adve | d0d06ad | 2003-05-31 07:32:01 +0000 | [diff] [blame] | 649 | // To find the return value (if any), we can get the LLVM return instr. |
| 650 | // from the return address register, which is the first operand |
| 651 | Value* tmpI = RetMI->getOperand(0).getVRegValue(); |
| 652 | ReturnInst* retI=cast<ReturnInst>(cast<TmpInstruction>(tmpI)->getOperand(0)); |
| 653 | if (const Value *RetVal = retI->getReturnValue()) |
| 654 | if (LiveRange *const LR = LRI.getLiveRangeForValue(RetVal)) |
| 655 | LR->setSuggestedColor(LR->getRegClassID() == IntRegClassID |
Brian Gaeke | e3d6807 | 2004-02-25 18:44:15 +0000 | [diff] [blame] | 656 | ? (unsigned) SparcV9IntRegClass::i0 |
| 657 | : (unsigned) SparcV9FloatRegClass::f0); |
Ruchira Sasanka | 9144228 | 2001-09-30 23:16:47 +0000 | [diff] [blame] | 658 | } |
| 659 | |
Vikram S. Adve | 76ee6f7 | 2002-07-08 23:23:12 +0000 | [diff] [blame] | 660 | //--------------------------------------------------------------------------- |
| 661 | // Check if a specified register type needs a scratch register to be |
| 662 | // copied to/from memory. If it does, the reg. type that must be used |
| 663 | // for scratch registers is returned in scratchRegType. |
| 664 | // |
| 665 | // Only the int CC register needs such a scratch register. |
| 666 | // The FP CC registers can (and must) be copied directly to/from memory. |
| 667 | //--------------------------------------------------------------------------- |
| 668 | |
| 669 | bool |
Brian Gaeke | e3d6807 | 2004-02-25 18:44:15 +0000 | [diff] [blame] | 670 | SparcV9RegInfo::regTypeNeedsScratchReg(int RegType, |
Vikram S. Adve | 76ee6f7 | 2002-07-08 23:23:12 +0000 | [diff] [blame] | 671 | int& scratchRegType) const |
| 672 | { |
| 673 | if (RegType == IntCCRegType) |
| 674 | { |
| 675 | scratchRegType = IntRegType; |
| 676 | return true; |
| 677 | } |
| 678 | return false; |
| 679 | } |
Ruchira Sasanka | 9144228 | 2001-09-30 23:16:47 +0000 | [diff] [blame] | 680 | |
| 681 | //--------------------------------------------------------------------------- |
| 682 | // Copy from a register to register. Register number must be the unified |
Vikram S. Adve | 76ee6f7 | 2002-07-08 23:23:12 +0000 | [diff] [blame] | 683 | // register number. |
Ruchira Sasanka | 9144228 | 2001-09-30 23:16:47 +0000 | [diff] [blame] | 684 | //--------------------------------------------------------------------------- |
| 685 | |
Vikram S. Adve | 242a808 | 2002-05-19 15:25:51 +0000 | [diff] [blame] | 686 | void |
Brian Gaeke | e3d6807 | 2004-02-25 18:44:15 +0000 | [diff] [blame] | 687 | SparcV9RegInfo::cpReg2RegMI(std::vector<MachineInstr*>& mvec, |
Vikram S. Adve | 76ee6f7 | 2002-07-08 23:23:12 +0000 | [diff] [blame] | 688 | unsigned SrcReg, |
Vikram S. Adve | 242a808 | 2002-05-19 15:25:51 +0000 | [diff] [blame] | 689 | unsigned DestReg, |
Vikram S. Adve | 76ee6f7 | 2002-07-08 23:23:12 +0000 | [diff] [blame] | 690 | int RegType) const { |
Misha Brukman | d36e30e | 2003-06-06 09:52:23 +0000 | [diff] [blame] | 691 | assert( ((int)SrcReg != getInvalidRegNum()) && |
| 692 | ((int)DestReg != getInvalidRegNum()) && |
Ruchira Sasanka | 9144228 | 2001-09-30 23:16:47 +0000 | [diff] [blame] | 693 | "Invalid Register"); |
| 694 | |
| 695 | MachineInstr * MI = NULL; |
Vikram S. Adve | 242a808 | 2002-05-19 15:25:51 +0000 | [diff] [blame] | 696 | |
Ruchira Sasanka | 9144228 | 2001-09-30 23:16:47 +0000 | [diff] [blame] | 697 | switch( RegType ) { |
| 698 | |
Ruchira Sasanka | 735d6e3 | 2001-10-18 22:38:52 +0000 | [diff] [blame] | 699 | case IntCCRegType: |
Misha Brukman | a98cd45 | 2003-05-20 20:32:24 +0000 | [diff] [blame] | 700 | if (getRegType(DestReg) == IntRegType) { |
| 701 | // copy intCC reg to int reg |
Vikram S. Adve | b15f8d4 | 2003-07-10 19:42:11 +0000 | [diff] [blame] | 702 | MI = (BuildMI(V9::RDCCR, 2) |
Brian Gaeke | e3d6807 | 2004-02-25 18:44:15 +0000 | [diff] [blame] | 703 | .addMReg(getUnifiedRegNum(SparcV9RegInfo::IntCCRegClassID, |
| 704 | SparcV9IntCCRegClass::ccr)) |
Alkis Evlogimenos | 890f923 | 2004-02-22 19:23:26 +0000 | [diff] [blame] | 705 | .addMReg(DestReg,MachineOperand::Def)); |
Misha Brukman | a98cd45 | 2003-05-20 20:32:24 +0000 | [diff] [blame] | 706 | } else { |
| 707 | // copy int reg to intCC reg |
Misha Brukman | a98cd45 | 2003-05-20 20:32:24 +0000 | [diff] [blame] | 708 | assert(getRegType(SrcReg) == IntRegType |
| 709 | && "Can only copy CC reg to/from integer reg"); |
Vikram S. Adve | b15f8d4 | 2003-07-10 19:42:11 +0000 | [diff] [blame] | 710 | MI = (BuildMI(V9::WRCCRr, 3) |
| 711 | .addMReg(SrcReg) |
Brian Gaeke | e3d6807 | 2004-02-25 18:44:15 +0000 | [diff] [blame] | 712 | .addMReg(SparcV9IntRegClass::g0) |
| 713 | .addMReg(getUnifiedRegNum(SparcV9RegInfo::IntCCRegClassID, |
| 714 | SparcV9IntCCRegClass::ccr), |
Alkis Evlogimenos | 890f923 | 2004-02-22 19:23:26 +0000 | [diff] [blame] | 715 | MachineOperand::Def)); |
Misha Brukman | a98cd45 | 2003-05-20 20:32:24 +0000 | [diff] [blame] | 716 | } |
Vikram S. Adve | 76ee6f7 | 2002-07-08 23:23:12 +0000 | [diff] [blame] | 717 | break; |
| 718 | |
Ruchira Sasanka | 735d6e3 | 2001-10-18 22:38:52 +0000 | [diff] [blame] | 719 | case FloatCCRegType: |
Vikram S. Adve | 76ee6f7 | 2002-07-08 23:23:12 +0000 | [diff] [blame] | 720 | assert(0 && "Cannot copy FPCC register to any other register"); |
Vikram S. Adve | 242a808 | 2002-05-19 15:25:51 +0000 | [diff] [blame] | 721 | break; |
| 722 | |
| 723 | case IntRegType: |
Misha Brukman | af6f38e | 2003-05-27 22:40:34 +0000 | [diff] [blame] | 724 | MI = BuildMI(V9::ADDr, 3).addMReg(SrcReg).addMReg(getZeroRegNum()) |
Alkis Evlogimenos | 890f923 | 2004-02-22 19:23:26 +0000 | [diff] [blame] | 725 | .addMReg(DestReg, MachineOperand::Def); |
Ruchira Sasanka | 9144228 | 2001-09-30 23:16:47 +0000 | [diff] [blame] | 726 | break; |
Vikram S. Adve | 242a808 | 2002-05-19 15:25:51 +0000 | [diff] [blame] | 727 | |
Ruchira Sasanka | 9144228 | 2001-09-30 23:16:47 +0000 | [diff] [blame] | 728 | case FPSingleRegType: |
Alkis Evlogimenos | 890f923 | 2004-02-22 19:23:26 +0000 | [diff] [blame] | 729 | MI = BuildMI(V9::FMOVS, 2).addMReg(SrcReg) |
| 730 | .addMReg(DestReg, MachineOperand::Def); |
Ruchira Sasanka | 9144228 | 2001-09-30 23:16:47 +0000 | [diff] [blame] | 731 | break; |
| 732 | |
| 733 | case FPDoubleRegType: |
Alkis Evlogimenos | 890f923 | 2004-02-22 19:23:26 +0000 | [diff] [blame] | 734 | MI = BuildMI(V9::FMOVD, 2).addMReg(SrcReg) |
| 735 | .addMReg(DestReg, MachineOperand::Def); |
Ruchira Sasanka | 9144228 | 2001-09-30 23:16:47 +0000 | [diff] [blame] | 736 | break; |
| 737 | |
| 738 | default: |
Vikram S. Adve | 242a808 | 2002-05-19 15:25:51 +0000 | [diff] [blame] | 739 | assert(0 && "Unknown RegType"); |
Vikram S. Adve | 76ee6f7 | 2002-07-08 23:23:12 +0000 | [diff] [blame] | 740 | break; |
Ruchira Sasanka | 89fb46b | 2001-09-18 22:52:44 +0000 | [diff] [blame] | 741 | } |
Vikram S. Adve | 242a808 | 2002-05-19 15:25:51 +0000 | [diff] [blame] | 742 | |
| 743 | if (MI) |
| 744 | mvec.push_back(MI); |
Ruchira Sasanka | 89fb46b | 2001-09-18 22:52:44 +0000 | [diff] [blame] | 745 | } |
Chris Lattner | 20b1ea0 | 2001-09-14 03:47:57 +0000 | [diff] [blame] | 746 | |
Brian Gaeke | 6614992 | 2004-08-18 17:44:14 +0000 | [diff] [blame] | 747 | /// cpReg2MemMI - Generate SparcV9 MachineInstrs to store a register |
| 748 | /// (SrcReg) to memory, at [PtrReg + Offset]. Register numbers must be the |
| 749 | /// unified register numbers. RegType must be the SparcV9 register type |
| 750 | /// of SrcReg. When SrcReg is %ccr, scratchReg must be the |
| 751 | /// number of a free integer register. The newly-generated MachineInstrs |
| 752 | /// are appended to mvec. |
| 753 | /// |
| 754 | void SparcV9RegInfo::cpReg2MemMI(std::vector<MachineInstr*>& mvec, |
| 755 | unsigned SrcReg, unsigned PtrReg, int Offset, |
| 756 | int RegType, int scratchReg) const { |
| 757 | unsigned OffReg = SparcV9::g4; // Use register g4 for holding large offsets |
| 758 | bool useImmediateOffset = true; |
Ruchira Sasanka | c4d4b76 | 2001-10-16 01:23:19 +0000 | [diff] [blame] | 759 | |
Brian Gaeke | 6614992 | 2004-08-18 17:44:14 +0000 | [diff] [blame] | 760 | // If the Offset will not fit in the signed-immediate field, we put it in |
| 761 | // register g4. This takes advantage of the fact that all the opcodes |
| 762 | // used below have the same size immed. field. |
| 763 | if (RegType != IntCCRegType |
| 764 | && !target.getInstrInfo()->constantFitsInImmedField(V9::LDXi, Offset)) { |
| 765 | // Put the offset into a register. We could do this in fewer steps, |
| 766 | // in some cases (see CreateSETSWConst()) but we're being lazy. |
| 767 | MachineInstr *MI = BuildMI(V9::SETHI, 2).addZImm(Offset).addMReg(OffReg, |
| 768 | MachineOperand::Def); |
| 769 | MI->getOperand(0).markHi32(); |
| 770 | mvec.push_back(MI); |
| 771 | MI = BuildMI(V9::ORi,3).addMReg(OffReg).addZImm(Offset).addMReg(OffReg, |
| 772 | MachineOperand::Def); |
| 773 | MI->getOperand(1).markLo32(); |
| 774 | mvec.push_back(MI); |
| 775 | MI = BuildMI(V9::SRAi5,3).addMReg(OffReg).addZImm(0).addMReg(OffReg, |
| 776 | MachineOperand::Def); |
| 777 | mvec.push_back(MI); |
| 778 | useImmediateOffset = false; |
| 779 | } |
Ruchira Sasanka | c4d4b76 | 2001-10-16 01:23:19 +0000 | [diff] [blame] | 780 | |
Brian Gaeke | 6614992 | 2004-08-18 17:44:14 +0000 | [diff] [blame] | 781 | MachineInstr *MI = 0; |
Chris Lattner | 00dca91 | 2003-01-15 17:47:49 +0000 | [diff] [blame] | 782 | switch (RegType) { |
Ruchira Sasanka | c4d4b76 | 2001-10-16 01:23:19 +0000 | [diff] [blame] | 783 | case IntRegType: |
Brian Gaeke | 6614992 | 2004-08-18 17:44:14 +0000 | [diff] [blame] | 784 | if (useImmediateOffset) |
Vikram S. Adve | 83d30c8 | 2003-07-29 19:53:21 +0000 | [diff] [blame] | 785 | MI = BuildMI(V9::STXi,3).addMReg(SrcReg).addMReg(PtrReg).addSImm(Offset); |
| 786 | else |
| 787 | MI = BuildMI(V9::STXr,3).addMReg(SrcReg).addMReg(PtrReg).addMReg(OffReg); |
Ruchira Sasanka | c4d4b76 | 2001-10-16 01:23:19 +0000 | [diff] [blame] | 788 | break; |
| 789 | |
| 790 | case FPSingleRegType: |
Brian Gaeke | 6614992 | 2004-08-18 17:44:14 +0000 | [diff] [blame] | 791 | if (useImmediateOffset) |
Vikram S. Adve | 83d30c8 | 2003-07-29 19:53:21 +0000 | [diff] [blame] | 792 | MI = BuildMI(V9::STFi, 3).addMReg(SrcReg).addMReg(PtrReg).addSImm(Offset); |
| 793 | else |
| 794 | MI = BuildMI(V9::STFr, 3).addMReg(SrcReg).addMReg(PtrReg).addMReg(OffReg); |
Ruchira Sasanka | c4d4b76 | 2001-10-16 01:23:19 +0000 | [diff] [blame] | 795 | break; |
| 796 | |
| 797 | case FPDoubleRegType: |
Brian Gaeke | 6614992 | 2004-08-18 17:44:14 +0000 | [diff] [blame] | 798 | if (useImmediateOffset) |
Vikram S. Adve | 83d30c8 | 2003-07-29 19:53:21 +0000 | [diff] [blame] | 799 | MI = BuildMI(V9::STDFi,3).addMReg(SrcReg).addMReg(PtrReg).addSImm(Offset); |
| 800 | else |
| 801 | MI = BuildMI(V9::STDFr,3).addMReg(SrcReg).addMReg(PtrReg).addSImm(OffReg); |
Ruchira Sasanka | c4d4b76 | 2001-10-16 01:23:19 +0000 | [diff] [blame] | 802 | break; |
| 803 | |
Ruchira Sasanka | 3839e6e | 2001-11-03 19:59:59 +0000 | [diff] [blame] | 804 | case IntCCRegType: |
Brian Gaeke | 6614992 | 2004-08-18 17:44:14 +0000 | [diff] [blame] | 805 | assert(scratchReg >= 0 && getRegType(scratchReg) == IntRegType |
| 806 | && "Need a scratch reg of integer type to load or store %ccr"); |
| 807 | MI = BuildMI(V9::RDCCR, 2).addMReg(SparcV9::ccr) |
| 808 | .addMReg(scratchReg, MachineOperand::Def); |
Vikram S. Adve | 76ee6f7 | 2002-07-08 23:23:12 +0000 | [diff] [blame] | 809 | mvec.push_back(MI); |
Vikram S. Adve | 83d30c8 | 2003-07-29 19:53:21 +0000 | [diff] [blame] | 810 | cpReg2MemMI(mvec, scratchReg, PtrReg, Offset, IntRegType); |
Chris Lattner | 00dca91 | 2003-01-15 17:47:49 +0000 | [diff] [blame] | 811 | return; |
Vikram S. Adve | 83d30c8 | 2003-07-29 19:53:21 +0000 | [diff] [blame] | 812 | |
Brian Gaeke | 0eb6103 | 2004-04-19 19:12:12 +0000 | [diff] [blame] | 813 | case SpecialRegType: // used only for %fsr itself. |
Vikram S. Adve | 78a4f23 | 2003-05-27 00:02:22 +0000 | [diff] [blame] | 814 | case FloatCCRegType: { |
Brian Gaeke | 6614992 | 2004-08-18 17:44:14 +0000 | [diff] [blame] | 815 | if (useImmediateOffset) |
| 816 | MI = BuildMI(V9::STXFSRi,3).addMReg(SparcV9::fsr).addMReg(PtrReg) |
| 817 | .addSImm(Offset); |
Vikram S. Adve | 83d30c8 | 2003-07-29 19:53:21 +0000 | [diff] [blame] | 818 | else |
Brian Gaeke | 6614992 | 2004-08-18 17:44:14 +0000 | [diff] [blame] | 819 | MI = BuildMI(V9::STXFSRr,3).addMReg(SparcV9::fsr).addMReg(PtrReg) |
| 820 | .addMReg(OffReg); |
Vikram S. Adve | 76ee6f7 | 2002-07-08 23:23:12 +0000 | [diff] [blame] | 821 | break; |
Vikram S. Adve | 78a4f23 | 2003-05-27 00:02:22 +0000 | [diff] [blame] | 822 | } |
Ruchira Sasanka | c4d4b76 | 2001-10-16 01:23:19 +0000 | [diff] [blame] | 823 | default: |
Vikram S. Adve | 242a808 | 2002-05-19 15:25:51 +0000 | [diff] [blame] | 824 | assert(0 && "Unknown RegType in cpReg2MemMI"); |
Ruchira Sasanka | c4d4b76 | 2001-10-16 01:23:19 +0000 | [diff] [blame] | 825 | } |
Chris Lattner | 00dca91 | 2003-01-15 17:47:49 +0000 | [diff] [blame] | 826 | mvec.push_back(MI); |
Ruchira Sasanka | c4d4b76 | 2001-10-16 01:23:19 +0000 | [diff] [blame] | 827 | } |
| 828 | |
Brian Gaeke | 6614992 | 2004-08-18 17:44:14 +0000 | [diff] [blame] | 829 | /// cpMem2RegMI - Generate SparcV9 MachineInstrs to load a register |
| 830 | /// (DestReg) from memory, at [PtrReg + Offset]. Register numbers must be the |
| 831 | /// unified register numbers. RegType must be the SparcV9 register type |
| 832 | /// of DestReg. When DestReg is %ccr, scratchReg must be the |
| 833 | /// number of a free integer register. The newly-generated MachineInstrs |
| 834 | /// are appended to mvec. |
| 835 | /// |
| 836 | void SparcV9RegInfo::cpMem2RegMI(std::vector<MachineInstr*>& mvec, |
| 837 | unsigned PtrReg, int Offset, unsigned DestReg, |
| 838 | int RegType, int scratchReg) const { |
| 839 | unsigned OffReg = SparcV9::g4; // Use register g4 for holding large offsets |
| 840 | bool useImmediateOffset = true; |
Ruchira Sasanka | c4d4b76 | 2001-10-16 01:23:19 +0000 | [diff] [blame] | 841 | |
Brian Gaeke | 6614992 | 2004-08-18 17:44:14 +0000 | [diff] [blame] | 842 | // If the Offset will not fit in the signed-immediate field, we put it in |
| 843 | // register g4. This takes advantage of the fact that all the opcodes |
| 844 | // used below have the same size immed. field. |
| 845 | if (RegType != IntCCRegType |
| 846 | && !target.getInstrInfo()->constantFitsInImmedField(V9::LDXi, Offset)) { |
| 847 | MachineInstr *MI = BuildMI(V9::SETHI, 2).addZImm(Offset).addMReg(OffReg, |
| 848 | MachineOperand::Def); |
| 849 | MI->getOperand(0).markHi32(); |
| 850 | mvec.push_back(MI); |
| 851 | MI = BuildMI(V9::ORi,3).addMReg(OffReg).addZImm(Offset).addMReg(OffReg, |
| 852 | MachineOperand::Def); |
| 853 | MI->getOperand(1).markLo32(); |
| 854 | mvec.push_back(MI); |
| 855 | MI = BuildMI(V9::SRAi5,3).addMReg(OffReg).addZImm(0).addMReg(OffReg, |
| 856 | MachineOperand::Def); |
| 857 | mvec.push_back(MI); |
| 858 | useImmediateOffset = false; |
| 859 | } |
Ruchira Sasanka | c4d4b76 | 2001-10-16 01:23:19 +0000 | [diff] [blame] | 860 | |
Brian Gaeke | 6614992 | 2004-08-18 17:44:14 +0000 | [diff] [blame] | 861 | MachineInstr *MI = 0; |
Chris Lattner | 699683c | 2002-02-04 05:59:25 +0000 | [diff] [blame] | 862 | switch (RegType) { |
Ruchira Sasanka | c4d4b76 | 2001-10-16 01:23:19 +0000 | [diff] [blame] | 863 | case IntRegType: |
Brian Gaeke | 6614992 | 2004-08-18 17:44:14 +0000 | [diff] [blame] | 864 | if (useImmediateOffset) |
Alkis Evlogimenos | 890f923 | 2004-02-22 19:23:26 +0000 | [diff] [blame] | 865 | MI = BuildMI(V9::LDXi, 3).addMReg(PtrReg).addSImm(Offset) |
| 866 | .addMReg(DestReg, MachineOperand::Def); |
Vikram S. Adve | 83d30c8 | 2003-07-29 19:53:21 +0000 | [diff] [blame] | 867 | else |
Alkis Evlogimenos | 890f923 | 2004-02-22 19:23:26 +0000 | [diff] [blame] | 868 | MI = BuildMI(V9::LDXr, 3).addMReg(PtrReg).addMReg(OffReg) |
| 869 | .addMReg(DestReg, MachineOperand::Def); |
Ruchira Sasanka | c4d4b76 | 2001-10-16 01:23:19 +0000 | [diff] [blame] | 870 | break; |
| 871 | |
| 872 | case FPSingleRegType: |
Brian Gaeke | 6614992 | 2004-08-18 17:44:14 +0000 | [diff] [blame] | 873 | if (useImmediateOffset) |
Alkis Evlogimenos | 890f923 | 2004-02-22 19:23:26 +0000 | [diff] [blame] | 874 | MI = BuildMI(V9::LDFi, 3).addMReg(PtrReg).addSImm(Offset) |
| 875 | .addMReg(DestReg, MachineOperand::Def); |
Vikram S. Adve | 83d30c8 | 2003-07-29 19:53:21 +0000 | [diff] [blame] | 876 | else |
Alkis Evlogimenos | 890f923 | 2004-02-22 19:23:26 +0000 | [diff] [blame] | 877 | MI = BuildMI(V9::LDFr, 3).addMReg(PtrReg).addMReg(OffReg) |
| 878 | .addMReg(DestReg, MachineOperand::Def); |
Ruchira Sasanka | c4d4b76 | 2001-10-16 01:23:19 +0000 | [diff] [blame] | 879 | break; |
| 880 | |
| 881 | case FPDoubleRegType: |
Brian Gaeke | 6614992 | 2004-08-18 17:44:14 +0000 | [diff] [blame] | 882 | if (useImmediateOffset) |
Alkis Evlogimenos | 890f923 | 2004-02-22 19:23:26 +0000 | [diff] [blame] | 883 | MI= BuildMI(V9::LDDFi, 3).addMReg(PtrReg).addSImm(Offset) |
| 884 | .addMReg(DestReg, MachineOperand::Def); |
Vikram S. Adve | 83d30c8 | 2003-07-29 19:53:21 +0000 | [diff] [blame] | 885 | else |
Alkis Evlogimenos | 890f923 | 2004-02-22 19:23:26 +0000 | [diff] [blame] | 886 | MI= BuildMI(V9::LDDFr, 3).addMReg(PtrReg).addMReg(OffReg) |
| 887 | .addMReg(DestReg, MachineOperand::Def); |
Ruchira Sasanka | c4d4b76 | 2001-10-16 01:23:19 +0000 | [diff] [blame] | 888 | break; |
| 889 | |
Ruchira Sasanka | 3839e6e | 2001-11-03 19:59:59 +0000 | [diff] [blame] | 890 | case IntCCRegType: |
Brian Gaeke | 6614992 | 2004-08-18 17:44:14 +0000 | [diff] [blame] | 891 | assert(scratchReg >= 0 && getRegType(scratchReg) == IntRegType |
| 892 | && "Need a scratch reg of integer type to load or store %ccr"); |
Vikram S. Adve | 83d30c8 | 2003-07-29 19:53:21 +0000 | [diff] [blame] | 893 | cpMem2RegMI(mvec, PtrReg, Offset, scratchReg, IntRegType); |
Brian Gaeke | 6614992 | 2004-08-18 17:44:14 +0000 | [diff] [blame] | 894 | MI = BuildMI(V9::WRCCRr, 3).addMReg(scratchReg).addMReg(SparcV9::g0) |
| 895 | .addMReg(SparcV9::ccr, MachineOperand::Def); |
Vikram S. Adve | 76ee6f7 | 2002-07-08 23:23:12 +0000 | [diff] [blame] | 896 | break; |
| 897 | |
Brian Gaeke | 0eb6103 | 2004-04-19 19:12:12 +0000 | [diff] [blame] | 898 | case SpecialRegType: // used only for %fsr itself |
Vikram S. Adve | 78a4f23 | 2003-05-27 00:02:22 +0000 | [diff] [blame] | 899 | case FloatCCRegType: { |
Brian Gaeke | 6614992 | 2004-08-18 17:44:14 +0000 | [diff] [blame] | 900 | if (useImmediateOffset) |
Vikram S. Adve | 83d30c8 | 2003-07-29 19:53:21 +0000 | [diff] [blame] | 901 | MI = BuildMI(V9::LDXFSRi, 3).addMReg(PtrReg).addSImm(Offset) |
Brian Gaeke | 6614992 | 2004-08-18 17:44:14 +0000 | [diff] [blame] | 902 | .addMReg(SparcV9::fsr, MachineOperand::Def); |
Vikram S. Adve | 83d30c8 | 2003-07-29 19:53:21 +0000 | [diff] [blame] | 903 | else |
| 904 | MI = BuildMI(V9::LDXFSRr, 3).addMReg(PtrReg).addMReg(OffReg) |
Brian Gaeke | 6614992 | 2004-08-18 17:44:14 +0000 | [diff] [blame] | 905 | .addMReg(SparcV9::fsr, MachineOperand::Def); |
Vikram S. Adve | 76ee6f7 | 2002-07-08 23:23:12 +0000 | [diff] [blame] | 906 | break; |
Vikram S. Adve | 78a4f23 | 2003-05-27 00:02:22 +0000 | [diff] [blame] | 907 | } |
Ruchira Sasanka | c4d4b76 | 2001-10-16 01:23:19 +0000 | [diff] [blame] | 908 | default: |
Ruchira Sasanka | ae4bcd7 | 2001-11-10 21:20:43 +0000 | [diff] [blame] | 909 | assert(0 && "Unknown RegType in cpMem2RegMI"); |
Ruchira Sasanka | c4d4b76 | 2001-10-16 01:23:19 +0000 | [diff] [blame] | 910 | } |
Chris Lattner | 00dca91 | 2003-01-15 17:47:49 +0000 | [diff] [blame] | 911 | mvec.push_back(MI); |
Ruchira Sasanka | c4d4b76 | 2001-10-16 01:23:19 +0000 | [diff] [blame] | 912 | } |
| 913 | |
| 914 | |
Ruchira Sasanka | 67a463a | 2001-11-12 14:45:33 +0000 | [diff] [blame] | 915 | //--------------------------------------------------------------------------- |
| 916 | // Generate a copy instruction to copy a value to another. Temporarily |
| 917 | // used by PhiElimination code. |
| 918 | //--------------------------------------------------------------------------- |
| 919 | |
| 920 | |
Vikram S. Adve | 242a808 | 2002-05-19 15:25:51 +0000 | [diff] [blame] | 921 | void |
Brian Gaeke | e3d6807 | 2004-02-25 18:44:15 +0000 | [diff] [blame] | 922 | SparcV9RegInfo::cpValue2Value(Value *Src, Value *Dest, |
Brian Gaeke | e7c7761 | 2004-06-04 20:51:40 +0000 | [diff] [blame] | 923 | std::vector<MachineInstr*>& mvec) const { |
Vikram S. Adve | 7dc7de5 | 2003-07-25 21:12:15 +0000 | [diff] [blame] | 924 | int RegType = getRegTypeForDataType(Src->getType()); |
Ruchira Sasanka | ef1b0cb | 2001-11-03 17:13:27 +0000 | [diff] [blame] | 925 | MachineInstr * MI = NULL; |
| 926 | |
Brian Gaeke | e7c7761 | 2004-06-04 20:51:40 +0000 | [diff] [blame] | 927 | switch (RegType) { |
Ruchira Sasanka | 67a463a | 2001-11-12 14:45:33 +0000 | [diff] [blame] | 928 | case IntRegType: |
Misha Brukman | af6f38e | 2003-05-27 22:40:34 +0000 | [diff] [blame] | 929 | MI = BuildMI(V9::ADDr, 3).addReg(Src).addMReg(getZeroRegNum()) |
Misha Brukman | a98cd45 | 2003-05-20 20:32:24 +0000 | [diff] [blame] | 930 | .addRegDef(Dest); |
Ruchira Sasanka | 67a463a | 2001-11-12 14:45:33 +0000 | [diff] [blame] | 931 | break; |
Ruchira Sasanka | 67a463a | 2001-11-12 14:45:33 +0000 | [diff] [blame] | 932 | case FPSingleRegType: |
Misha Brukman | a98cd45 | 2003-05-20 20:32:24 +0000 | [diff] [blame] | 933 | MI = BuildMI(V9::FMOVS, 2).addReg(Src).addRegDef(Dest); |
Ruchira Sasanka | 67a463a | 2001-11-12 14:45:33 +0000 | [diff] [blame] | 934 | break; |
Ruchira Sasanka | 67a463a | 2001-11-12 14:45:33 +0000 | [diff] [blame] | 935 | case FPDoubleRegType: |
Misha Brukman | a98cd45 | 2003-05-20 20:32:24 +0000 | [diff] [blame] | 936 | MI = BuildMI(V9::FMOVD, 2).addReg(Src).addRegDef(Dest); |
Ruchira Sasanka | 67a463a | 2001-11-12 14:45:33 +0000 | [diff] [blame] | 937 | break; |
Ruchira Sasanka | 67a463a | 2001-11-12 14:45:33 +0000 | [diff] [blame] | 938 | default: |
Brian Gaeke | e7c7761 | 2004-06-04 20:51:40 +0000 | [diff] [blame] | 939 | assert(0 && "Unknown RegType in cpValue2Value"); |
Ruchira Sasanka | 67a463a | 2001-11-12 14:45:33 +0000 | [diff] [blame] | 940 | } |
Ruchira Sasanka | ef1b0cb | 2001-11-03 17:13:27 +0000 | [diff] [blame] | 941 | |
Chris Lattner | 0fa600d | 2002-10-28 20:10:56 +0000 | [diff] [blame] | 942 | mvec.push_back(MI); |
Ruchira Sasanka | ef1b0cb | 2001-11-03 17:13:27 +0000 | [diff] [blame] | 943 | } |
Ruchira Sasanka | c4d4b76 | 2001-10-16 01:23:19 +0000 | [diff] [blame] | 944 | |
| 945 | |
| 946 | |
Ruchira Sasanka | 89fb46b | 2001-09-18 22:52:44 +0000 | [diff] [blame] | 947 | //--------------------------------------------------------------------------- |
| 948 | // Print the register assigned to a LR |
| 949 | //--------------------------------------------------------------------------- |
| 950 | |
Brian Gaeke | e3d6807 | 2004-02-25 18:44:15 +0000 | [diff] [blame] | 951 | void SparcV9RegInfo::printReg(const LiveRange *LR) const { |
Chris Lattner | 3c3c82d | 2003-01-15 21:14:32 +0000 | [diff] [blame] | 952 | unsigned RegClassID = LR->getRegClassID(); |
Chris Lattner | fdba393 | 2003-09-01 19:58:02 +0000 | [diff] [blame] | 953 | std::cerr << " Node "; |
Ruchira Sasanka | 89fb46b | 2001-09-18 22:52:44 +0000 | [diff] [blame] | 954 | |
Chris Lattner | 699683c | 2002-02-04 05:59:25 +0000 | [diff] [blame] | 955 | if (!LR->hasColor()) { |
Misha Brukman | ee563cb | 2003-05-21 17:59:06 +0000 | [diff] [blame] | 956 | std::cerr << " - could not find a color\n"; |
Ruchira Sasanka | 89fb46b | 2001-09-18 22:52:44 +0000 | [diff] [blame] | 957 | return; |
| 958 | } |
| 959 | |
| 960 | // if a color is found |
| 961 | |
Misha Brukman | ee563cb | 2003-05-21 17:59:06 +0000 | [diff] [blame] | 962 | std::cerr << " colored with color "<< LR->getColor(); |
Ruchira Sasanka | 89fb46b | 2001-09-18 22:52:44 +0000 | [diff] [blame] | 963 | |
Vikram S. Adve | 78a4f23 | 2003-05-27 00:02:22 +0000 | [diff] [blame] | 964 | unsigned uRegName = getUnifiedRegNum(RegClassID, LR->getColor()); |
| 965 | |
| 966 | std::cerr << "["; |
| 967 | std::cerr<< getUnifiedRegName(uRegName); |
| 968 | if (RegClassID == FloatRegClassID && LR->getType() == Type::DoubleTy) |
| 969 | std::cerr << "+" << getUnifiedRegName(uRegName+1); |
| 970 | std::cerr << "]\n"; |
Ruchira Sasanka | 89fb46b | 2001-09-18 22:52:44 +0000 | [diff] [blame] | 971 | } |
Brian Gaeke | d0fde30 | 2003-11-11 22:41:34 +0000 | [diff] [blame] | 972 | |
| 973 | } // End llvm namespace |