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gerrit-public.fairphone.software / platform / external / llvm / f463f51161fe65da93ec573f19d2d32353be4116 / . / lib / Target / X86 / X86RegisterInfo.cpp
blob: da468eade44fbeb6b586854781a77415a358bff9 [file] [log] [blame]
Misha Brukmancf2b9ac2002-11-22 22:43:47 +0000[diff] [blame]1//===- X86RegisterInfo.cpp - X86 Register Information -----------*- C++ -*-===//
Alkis Evlogimenos39354c92004-03-14 07:19:51 +0000[diff] [blame]2//
John Criswellb576c942003-10-20 19:43:21 +0000[diff] [blame]3// The LLVM Compiler Infrastructure
4//
5// This file was developed by the LLVM research group and is distributed under
6// the University of Illinois Open Source License. See LICENSE.TXT for details.
Alkis Evlogimenos39354c92004-03-14 07:19:51 +0000[diff] [blame]7//
John Criswellb576c942003-10-20 19:43:21 +0000[diff] [blame]8//===----------------------------------------------------------------------===//
Chris Lattner72614082002-10-25 22:55:53 +0000[diff] [blame]9//
Chris Lattner3c1c03d2002-12-28 20:32:28 +0000[diff] [blame]10// This file contains the X86 implementation of the MRegisterInfo class. This
11// file is responsible for the frame pointer elimination optimization on X86.
Chris Lattner72614082002-10-25 22:55:53 +0000[diff] [blame]12//
13//===----------------------------------------------------------------------===//
14
Misha Brukmanb83b2862002-11-20 18:59:43 +0000[diff] [blame]15#include "X86.h"
Chris Lattner72614082002-10-25 22:55:53 +0000[diff] [blame]16#include "X86RegisterInfo.h"
Misha Brukmancf2b9ac2002-11-22 22:43:47 +0000[diff] [blame]17#include "X86InstrBuilder.h"
Misha Brukmanb83b2862002-11-20 18:59:43 +0000[diff] [blame]18#include "llvm/Constants.h"
19#include "llvm/Type.h"
Chris Lattnerc8c377d2003-07-29 05:14:16 +0000[diff] [blame]20#include "llvm/CodeGen/ValueTypes.h"
Misha Brukmanb83b2862002-11-20 18:59:43 +0000[diff] [blame]21#include "llvm/CodeGen/MachineInstrBuilder.h"
Chris Lattner198ab642002-12-15 20:06:35 +0000[diff] [blame]22#include "llvm/CodeGen/MachineFunction.h"
Chris Lattneraa09b752002-12-28 21:08:28 +0000[diff] [blame]23#include "llvm/CodeGen/MachineFrameInfo.h"
Jim Laskeyf1d78e82006-03-23 18:12:57 +0000[diff] [blame]24#include "llvm/CodeGen/MachineLocation.h"
Chris Lattnerf158da22003-01-16 02:20:12 +0000[diff] [blame]25#include "llvm/Target/TargetFrameInfo.h"
Misha Brukman83eaa0b2004-06-21 21:10:24 +0000[diff] [blame]26#include "llvm/Target/TargetMachine.h"
Chris Lattner0cf0c372004-07-11 04:17:10 +0000[diff] [blame]27#include "llvm/Target/TargetOptions.h"
Reid Spencer551ccae2004-09-01 22:55:40 +0000[diff] [blame]28#include "llvm/Support/CommandLine.h"
29#include "llvm/ADT/STLExtras.h"
Reid Spencer954da372004-07-04 12:19:56 +0000[diff] [blame]30#include <iostream>
31
Chris Lattner300d0ed2004-02-14 06:00:36 +0000[diff] [blame]32using namespace llvm;
Brian Gaeked0fde302003-11-11 22:41:34 +0000[diff] [blame]33
Chris Lattner3c1c03d2002-12-28 20:32:28 +0000[diff] [blame]34namespace {
35 cl::opt<bool>
Chris Lattnera7660be2004-02-17 06:30:34 +0000[diff] [blame]36 NoFusing("disable-spill-fusing",
37 cl::desc("Disable fusing of spill code into instructions"));
Chris Lattneree0919b2004-02-17 08:03:47 +0000[diff] [blame]38 cl::opt<bool>
39 PrintFailedFusing("print-failed-fuse-candidates",
40 cl::desc("Print instructions that the allocator wants to"
41 " fuse, but the X86 backend currently can't"),
42 cl::Hidden);
Chris Lattner3c1c03d2002-12-28 20:32:28 +0000[diff] [blame]43}
Chris Lattner72614082002-10-25 22:55:53 +0000[diff] [blame]44
Chris Lattner7ad3e062003-08-03 15:48:14 +0000[diff] [blame]45X86RegisterInfo::X86RegisterInfo()
46 : X86GenRegisterInfo(X86::ADJCALLSTACKDOWN, X86::ADJCALLSTACKUP) {}
47
Chris Lattner01d0efb2004-08-15 22:15:11 +0000[diff] [blame]48void X86RegisterInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
49 MachineBasicBlock::iterator MI,
Chris Lattner97d5e642005-09-30 01:29:42 +0000[diff] [blame]50 unsigned SrcReg, int FrameIdx,
51 const TargetRegisterClass *RC) const {
Chris Lattner56bcae02005-09-30 17:12:38 +0000[diff] [blame]52 unsigned Opc;
53 if (RC == &X86::R32RegClass) {
54 Opc = X86::MOV32mr;
55 } else if (RC == &X86::R8RegClass) {
56 Opc = X86::MOV8mr;
57 } else if (RC == &X86::R16RegClass) {
58 Opc = X86::MOV16mr;
59 } else if (RC == &X86::RFPRegClass || RC == &X86::RSTRegClass) {
Chris Lattner58fe4592005-12-21 07:47:04 +0000[diff] [blame]60 Opc = X86::FpST64m;
Evan Cheng19ade3b2006-02-16 21:20:26 +0000[diff] [blame]61 } else if (RC == &X86::FR32RegClass) {
Nate Begeman14e2cf62005-10-14 22:06:00 +0000[diff] [blame]62 Opc = X86::MOVSSmr;
Evan Cheng19ade3b2006-02-16 21:20:26 +0000[diff] [blame]63 } else if (RC == &X86::FR64RegClass) {
Chris Lattner56bcae02005-09-30 17:12:38 +0000[diff] [blame]64 Opc = X86::MOVSDmr;
Evan Cheng2246f842006-03-18 01:23:20 +0000[diff] [blame]65 } else if (RC == &X86::VR128RegClass) {
Evan Cheng19ade3b2006-02-16 21:20:26 +0000[diff] [blame]66 Opc = X86::MOVAPDmr;
Chris Lattner56bcae02005-09-30 17:12:38 +0000[diff] [blame]67 } else {
68 assert(0 && "Unknown regclass");
69 abort();
70 }
Nate Begemanf63be7d2005-07-06 18:59:04 +0000[diff] [blame]71 addFrameReference(BuildMI(MBB, MI, Opc, 5), FrameIdx).addReg(SrcReg);
Misha Brukmanb83b2862002-11-20 18:59:43 +0000[diff] [blame]72}
73
Chris Lattner01d0efb2004-08-15 22:15:11 +0000[diff] [blame]74void X86RegisterInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
75 MachineBasicBlock::iterator MI,
Chris Lattner97d5e642005-09-30 01:29:42 +0000[diff] [blame]76 unsigned DestReg, int FrameIdx,
77 const TargetRegisterClass *RC) const{
Chris Lattner56bcae02005-09-30 17:12:38 +0000[diff] [blame]78 unsigned Opc;
79 if (RC == &X86::R32RegClass) {
80 Opc = X86::MOV32rm;
81 } else if (RC == &X86::R8RegClass) {
82 Opc = X86::MOV8rm;
83 } else if (RC == &X86::R16RegClass) {
84 Opc = X86::MOV16rm;
85 } else if (RC == &X86::RFPRegClass || RC == &X86::RSTRegClass) {
Chris Lattner58fe4592005-12-21 07:47:04 +0000[diff] [blame]86 Opc = X86::FpLD64m;
Evan Cheng19ade3b2006-02-16 21:20:26 +0000[diff] [blame]87 } else if (RC == &X86::FR32RegClass) {
Nate Begeman14e2cf62005-10-14 22:06:00 +0000[diff] [blame]88 Opc = X86::MOVSSrm;
Evan Cheng19ade3b2006-02-16 21:20:26 +0000[diff] [blame]89 } else if (RC == &X86::FR64RegClass) {
Chris Lattner56bcae02005-09-30 17:12:38 +0000[diff] [blame]90 Opc = X86::MOVSDrm;
Evan Cheng2246f842006-03-18 01:23:20 +0000[diff] [blame]91 } else if (RC == &X86::VR128RegClass) {
Evan Cheng19ade3b2006-02-16 21:20:26 +0000[diff] [blame]92 Opc = X86::MOVAPDrm;
Chris Lattner56bcae02005-09-30 17:12:38 +0000[diff] [blame]93 } else {
94 assert(0 && "Unknown regclass");
95 abort();
96 }
Nate Begemanf63be7d2005-07-06 18:59:04 +0000[diff] [blame]97 addFrameReference(BuildMI(MBB, MI, Opc, 4, DestReg), FrameIdx);
Misha Brukmanb83b2862002-11-20 18:59:43 +0000[diff] [blame]98}
99
Chris Lattner01d0efb2004-08-15 22:15:11 +0000[diff] [blame]100void X86RegisterInfo::copyRegToReg(MachineBasicBlock &MBB,
101 MachineBasicBlock::iterator MI,
102 unsigned DestReg, unsigned SrcReg,
103 const TargetRegisterClass *RC) const {
Chris Lattner56bcae02005-09-30 17:12:38 +0000[diff] [blame]104 unsigned Opc;
105 if (RC == &X86::R32RegClass) {
106 Opc = X86::MOV32rr;
107 } else if (RC == &X86::R8RegClass) {
108 Opc = X86::MOV8rr;
109 } else if (RC == &X86::R16RegClass) {
110 Opc = X86::MOV16rr;
111 } else if (RC == &X86::RFPRegClass || RC == &X86::RSTRegClass) {
112 Opc = X86::FpMOV;
Evan Cheng933be332006-02-21 01:38:21 +0000[diff] [blame]113 } else if (RC == &X86::FR32RegClass) {
Evan Chengfe5cb192006-02-16 22:45:17 +0000[diff] [blame]114 Opc = X86::FsMOVAPSrr;
Evan Cheng933be332006-02-21 01:38:21 +0000[diff] [blame]115 } else if (RC == &X86::FR64RegClass) {
Evan Chengfe5cb192006-02-16 22:45:17 +0000[diff] [blame]116 Opc = X86::FsMOVAPDrr;
Evan Cheng2246f842006-03-18 01:23:20 +0000[diff] [blame]117 } else if (RC == &X86::VR128RegClass) {
Evan Chenga964ccd2006-04-10 07:21:31 +0000[diff] [blame]118 Opc = X86::MOVAPSrr;
Chris Lattner56bcae02005-09-30 17:12:38 +0000[diff] [blame]119 } else {
120 assert(0 && "Unknown regclass");
121 abort();
122 }
Nate Begemanf63be7d2005-07-06 18:59:04 +0000[diff] [blame]123 BuildMI(MBB, MI, Opc, 1, DestReg).addReg(SrcReg);
Misha Brukman2b46e8e2002-12-13 09:54:12 +0000[diff] [blame]124}
125
Chris Lattnera92aab72005-09-19 05:23:44 +0000[diff] [blame]126
Alkis Evlogimenos89b02142004-02-17 08:49:20 +0000[diff] [blame]127static MachineInstr *MakeMInst(unsigned Opcode, unsigned FrameIndex,
128 MachineInstr *MI) {
Alkis Evlogimenosd886ed92004-02-17 15:58:13 +0000[diff] [blame]129 return addFrameReference(BuildMI(Opcode, 4), FrameIndex);
Alkis Evlogimenos89b02142004-02-17 08:49:20 +0000[diff] [blame]130}
131
Chris Lattner7c035b72004-02-17 05:35:13 +0000[diff] [blame]132static MachineInstr *MakeMRInst(unsigned Opcode, unsigned FrameIndex,
133 MachineInstr *MI) {
134 return addFrameReference(BuildMI(Opcode, 5), FrameIndex)
135 .addReg(MI->getOperand(1).getReg());
136}
137
Alkis Evlogimenose56508e2004-02-27 15:03:18 +0000[diff] [blame]138static MachineInstr *MakeMRIInst(unsigned Opcode, unsigned FrameIndex,
139 MachineInstr *MI) {
Chris Lattner3b5e6e52004-07-17 20:24:05 +0000[diff] [blame]140 return addFrameReference(BuildMI(Opcode, 6), FrameIndex)
Alkis Evlogimenose56508e2004-02-27 15:03:18 +0000[diff] [blame]141 .addReg(MI->getOperand(1).getReg())
142 .addZImm(MI->getOperand(2).getImmedValue());
143}
144
Chris Lattner7c035b72004-02-17 05:35:13 +0000[diff] [blame]145static MachineInstr *MakeMIInst(unsigned Opcode, unsigned FrameIndex,
146 MachineInstr *MI) {
Chris Lattnercc0d2f52004-02-17 18:23:55 +0000[diff] [blame]147 if (MI->getOperand(1).isImmediate())
148 return addFrameReference(BuildMI(Opcode, 5), FrameIndex)
149 .addZImm(MI->getOperand(1).getImmedValue());
150 else if (MI->getOperand(1).isGlobalAddress())
151 return addFrameReference(BuildMI(Opcode, 5), FrameIndex)
Evan Chengcb4a38e2006-02-25 01:37:02 +0000[diff] [blame]152 .addGlobalAddress(MI->getOperand(1).getGlobal(),
153 false, MI->getOperand(1).getOffset());
Chris Lattnercc0d2f52004-02-17 18:23:55 +0000[diff] [blame]154 assert(0 && "Unknown operand for MakeMI!");
155 return 0;
Chris Lattner7c035b72004-02-17 05:35:13 +0000[diff] [blame]156}
157
Evan Cheng8586b952006-03-17 02:36:22 +0000[diff] [blame]158static MachineInstr *MakeM0Inst(unsigned Opcode, unsigned FrameIndex,
159 MachineInstr *MI) {
160 return addFrameReference(BuildMI(Opcode, 5), FrameIndex).addZImm(0);
161}
162
Chris Lattner7c035b72004-02-17 05:35:13 +0000[diff] [blame]163static MachineInstr *MakeRMInst(unsigned Opcode, unsigned FrameIndex,
164 MachineInstr *MI) {
Alkis Evlogimenosf2164212004-02-22 06:54:26 +0000[diff] [blame]165 const MachineOperand& op = MI->getOperand(0);
166 return addFrameReference(BuildMI(Opcode, 5, op.getReg(), op.getUseType()),
Chris Lattner0f9c4912004-02-17 05:46:06 +0000[diff] [blame]167 FrameIndex);
Chris Lattner7c035b72004-02-17 05:35:13 +0000[diff] [blame]168}
169
Chris Lattner0f9c4912004-02-17 05:46:06 +0000[diff] [blame]170static MachineInstr *MakeRMIInst(unsigned Opcode, unsigned FrameIndex,
171 MachineInstr *MI) {
Alkis Evlogimenosf2164212004-02-22 06:54:26 +0000[diff] [blame]172 const MachineOperand& op = MI->getOperand(0);
Chris Lattner3b5e6e52004-07-17 20:24:05 +0000[diff] [blame]173 return addFrameReference(BuildMI(Opcode, 6, op.getReg(), op.getUseType()),
Chris Lattner0f9c4912004-02-17 05:46:06 +0000[diff] [blame]174 FrameIndex).addZImm(MI->getOperand(2).getImmedValue());
175}
176
177
Alkis Evlogimenosa1a71482004-03-14 20:14:27 +0000[diff] [blame]178MachineInstr* X86RegisterInfo::foldMemoryOperand(MachineInstr* MI,
179 unsigned i,
180 int FrameIndex) const {
Alkis Evlogimenos39354c92004-03-14 07:19:51 +0000[diff] [blame]181 if (NoFusing) return NULL;
Chris Lattnera7660be2004-02-17 06:30:34 +0000[diff] [blame]182
Chris Lattner7c035b72004-02-17 05:35:13 +0000[diff] [blame]183 /// FIXME: This should obviously be autogenerated by tablegen when patterns
184 /// are available!
Alkis Evlogimenosb4998662004-02-17 04:33:18 +0000[diff] [blame]185 MachineBasicBlock& MBB = *MI->getParent();
Chris Lattner7c035b72004-02-17 05:35:13 +0000[diff] [blame]186 if (i == 0) {
187 switch(MI->getOpcode()) {
Alkis Evlogimenos39354c92004-03-14 07:19:51 +0000[diff] [blame]188 case X86::XCHG8rr: return MakeMRInst(X86::XCHG8mr ,FrameIndex, MI);
189 case X86::XCHG16rr: return MakeMRInst(X86::XCHG16mr,FrameIndex, MI);
190 case X86::XCHG32rr: return MakeMRInst(X86::XCHG32mr,FrameIndex, MI);
191 case X86::MOV8rr: return MakeMRInst(X86::MOV8mr , FrameIndex, MI);
192 case X86::MOV16rr: return MakeMRInst(X86::MOV16mr, FrameIndex, MI);
193 case X86::MOV32rr: return MakeMRInst(X86::MOV32mr, FrameIndex, MI);
194 case X86::MOV8ri: return MakeMIInst(X86::MOV8mi , FrameIndex, MI);
195 case X86::MOV16ri: return MakeMIInst(X86::MOV16mi, FrameIndex, MI);
196 case X86::MOV32ri: return MakeMIInst(X86::MOV32mi, FrameIndex, MI);
197 case X86::MUL8r: return MakeMInst( X86::MUL8m , FrameIndex, MI);
198 case X86::MUL16r: return MakeMInst( X86::MUL16m, FrameIndex, MI);
199 case X86::MUL32r: return MakeMInst( X86::MUL32m, FrameIndex, MI);
Chris Lattner1e6a7152005-04-06 04:19:22 +0000[diff] [blame]200 case X86::IMUL8r: return MakeMInst( X86::IMUL8m , FrameIndex, MI);
201 case X86::IMUL16r: return MakeMInst( X86::IMUL16m, FrameIndex, MI);
202 case X86::IMUL32r: return MakeMInst( X86::IMUL32m, FrameIndex, MI);
Alkis Evlogimenos39354c92004-03-14 07:19:51 +0000[diff] [blame]203 case X86::DIV8r: return MakeMInst( X86::DIV8m , FrameIndex, MI);
204 case X86::DIV16r: return MakeMInst( X86::DIV16m, FrameIndex, MI);
205 case X86::DIV32r: return MakeMInst( X86::DIV32m, FrameIndex, MI);
206 case X86::IDIV8r: return MakeMInst( X86::IDIV8m , FrameIndex, MI);
207 case X86::IDIV16r: return MakeMInst( X86::IDIV16m, FrameIndex, MI);
208 case X86::IDIV32r: return MakeMInst( X86::IDIV32m, FrameIndex, MI);
209 case X86::NEG8r: return MakeMInst( X86::NEG8m , FrameIndex, MI);
210 case X86::NEG16r: return MakeMInst( X86::NEG16m, FrameIndex, MI);
211 case X86::NEG32r: return MakeMInst( X86::NEG32m, FrameIndex, MI);
212 case X86::NOT8r: return MakeMInst( X86::NOT8m , FrameIndex, MI);
213 case X86::NOT16r: return MakeMInst( X86::NOT16m, FrameIndex, MI);
214 case X86::NOT32r: return MakeMInst( X86::NOT32m, FrameIndex, MI);
215 case X86::INC8r: return MakeMInst( X86::INC8m , FrameIndex, MI);
216 case X86::INC16r: return MakeMInst( X86::INC16m, FrameIndex, MI);
217 case X86::INC32r: return MakeMInst( X86::INC32m, FrameIndex, MI);
218 case X86::DEC8r: return MakeMInst( X86::DEC8m , FrameIndex, MI);
219 case X86::DEC16r: return MakeMInst( X86::DEC16m, FrameIndex, MI);
220 case X86::DEC32r: return MakeMInst( X86::DEC32m, FrameIndex, MI);
221 case X86::ADD8rr: return MakeMRInst(X86::ADD8mr , FrameIndex, MI);
222 case X86::ADD16rr: return MakeMRInst(X86::ADD16mr, FrameIndex, MI);
223 case X86::ADD32rr: return MakeMRInst(X86::ADD32mr, FrameIndex, MI);
Alkis Evlogimenos39354c92004-03-14 07:19:51 +0000[diff] [blame]224 case X86::ADD8ri: return MakeMIInst(X86::ADD8mi , FrameIndex, MI);
225 case X86::ADD16ri: return MakeMIInst(X86::ADD16mi, FrameIndex, MI);
226 case X86::ADD32ri: return MakeMIInst(X86::ADD32mi, FrameIndex, MI);
Evan Cheng5bd4d482006-03-17 02:25:01 +0000[diff] [blame]227 case X86::ADD16ri8: return MakeMIInst(X86::ADD16mi8,FrameIndex, MI);
228 case X86::ADD32ri8: return MakeMIInst(X86::ADD32mi8,FrameIndex, MI);
229 case X86::ADC32rr: return MakeMRInst(X86::ADC32mr, FrameIndex, MI);
230 case X86::ADC32ri: return MakeMIInst(X86::ADC32mi, FrameIndex, MI);
231 case X86::ADC32ri8: return MakeMIInst(X86::ADC32mi8,FrameIndex, MI);
Alkis Evlogimenos39354c92004-03-14 07:19:51 +0000[diff] [blame]232 case X86::SUB8rr: return MakeMRInst(X86::SUB8mr , FrameIndex, MI);
233 case X86::SUB16rr: return MakeMRInst(X86::SUB16mr, FrameIndex, MI);
234 case X86::SUB32rr: return MakeMRInst(X86::SUB32mr, FrameIndex, MI);
Alkis Evlogimenos39354c92004-03-14 07:19:51 +0000[diff] [blame]235 case X86::SUB8ri: return MakeMIInst(X86::SUB8mi , FrameIndex, MI);
236 case X86::SUB16ri: return MakeMIInst(X86::SUB16mi, FrameIndex, MI);
237 case X86::SUB32ri: return MakeMIInst(X86::SUB32mi, FrameIndex, MI);
Evan Cheng5bd4d482006-03-17 02:25:01 +0000[diff] [blame]238 case X86::SUB16ri8: return MakeMIInst(X86::SUB16mi8,FrameIndex, MI);
239 case X86::SUB32ri8: return MakeMIInst(X86::SUB32mi8,FrameIndex, MI);
240 case X86::SBB32rr: return MakeMRInst(X86::SBB32mr, FrameIndex, MI);
241 case X86::SBB32ri: return MakeMIInst(X86::SBB32mi, FrameIndex, MI);
242 case X86::SBB32ri8: return MakeMIInst(X86::SBB32mi8,FrameIndex, MI);
Alkis Evlogimenos39354c92004-03-14 07:19:51 +0000[diff] [blame]243 case X86::AND8rr: return MakeMRInst(X86::AND8mr , FrameIndex, MI);
244 case X86::AND16rr: return MakeMRInst(X86::AND16mr, FrameIndex, MI);
245 case X86::AND32rr: return MakeMRInst(X86::AND32mr, FrameIndex, MI);
246 case X86::AND8ri: return MakeMIInst(X86::AND8mi , FrameIndex, MI);
247 case X86::AND16ri: return MakeMIInst(X86::AND16mi, FrameIndex, MI);
248 case X86::AND32ri: return MakeMIInst(X86::AND32mi, FrameIndex, MI);
Evan Cheng5bd4d482006-03-17 02:25:01 +0000[diff] [blame]249 case X86::AND16ri8: return MakeMIInst(X86::AND16mi8,FrameIndex, MI);
250 case X86::AND32ri8: return MakeMIInst(X86::AND32mi8,FrameIndex, MI);
Alkis Evlogimenos39354c92004-03-14 07:19:51 +0000[diff] [blame]251 case X86::OR8rr: return MakeMRInst(X86::OR8mr , FrameIndex, MI);
252 case X86::OR16rr: return MakeMRInst(X86::OR16mr, FrameIndex, MI);
253 case X86::OR32rr: return MakeMRInst(X86::OR32mr, FrameIndex, MI);
254 case X86::OR8ri: return MakeMIInst(X86::OR8mi , FrameIndex, MI);
255 case X86::OR16ri: return MakeMIInst(X86::OR16mi, FrameIndex, MI);
256 case X86::OR32ri: return MakeMIInst(X86::OR32mi, FrameIndex, MI);
Evan Cheng5bd4d482006-03-17 02:25:01 +0000[diff] [blame]257 case X86::OR16ri8: return MakeMIInst(X86::OR16mi8, FrameIndex, MI);
258 case X86::OR32ri8: return MakeMIInst(X86::OR32mi8, FrameIndex, MI);
Alkis Evlogimenos39354c92004-03-14 07:19:51 +0000[diff] [blame]259 case X86::XOR8rr: return MakeMRInst(X86::XOR8mr , FrameIndex, MI);
260 case X86::XOR16rr: return MakeMRInst(X86::XOR16mr, FrameIndex, MI);
261 case X86::XOR32rr: return MakeMRInst(X86::XOR32mr, FrameIndex, MI);
262 case X86::XOR8ri: return MakeMIInst(X86::XOR8mi , FrameIndex, MI);
263 case X86::XOR16ri: return MakeMIInst(X86::XOR16mi, FrameIndex, MI);
264 case X86::XOR32ri: return MakeMIInst(X86::XOR32mi, FrameIndex, MI);
Evan Cheng5bd4d482006-03-17 02:25:01 +0000[diff] [blame]265 case X86::XOR16ri8: return MakeMIInst(X86::XOR16mi8,FrameIndex, MI);
266 case X86::XOR32ri8: return MakeMIInst(X86::XOR32mi8,FrameIndex, MI);
Alkis Evlogimenos39354c92004-03-14 07:19:51 +0000[diff] [blame]267 case X86::SHL8rCL: return MakeMInst( X86::SHL8mCL ,FrameIndex, MI);
268 case X86::SHL16rCL: return MakeMInst( X86::SHL16mCL,FrameIndex, MI);
269 case X86::SHL32rCL: return MakeMInst( X86::SHL32mCL,FrameIndex, MI);
270 case X86::SHL8ri: return MakeMIInst(X86::SHL8mi , FrameIndex, MI);
271 case X86::SHL16ri: return MakeMIInst(X86::SHL16mi, FrameIndex, MI);
272 case X86::SHL32ri: return MakeMIInst(X86::SHL32mi, FrameIndex, MI);
273 case X86::SHR8rCL: return MakeMInst( X86::SHR8mCL ,FrameIndex, MI);
274 case X86::SHR16rCL: return MakeMInst( X86::SHR16mCL,FrameIndex, MI);
275 case X86::SHR32rCL: return MakeMInst( X86::SHR32mCL,FrameIndex, MI);
276 case X86::SHR8ri: return MakeMIInst(X86::SHR8mi , FrameIndex, MI);
277 case X86::SHR16ri: return MakeMIInst(X86::SHR16mi, FrameIndex, MI);
278 case X86::SHR32ri: return MakeMIInst(X86::SHR32mi, FrameIndex, MI);
279 case X86::SAR8rCL: return MakeMInst( X86::SAR8mCL ,FrameIndex, MI);
280 case X86::SAR16rCL: return MakeMInst( X86::SAR16mCL,FrameIndex, MI);
281 case X86::SAR32rCL: return MakeMInst( X86::SAR32mCL,FrameIndex, MI);
282 case X86::SAR8ri: return MakeMIInst(X86::SAR8mi , FrameIndex, MI);
283 case X86::SAR16ri: return MakeMIInst(X86::SAR16mi, FrameIndex, MI);
284 case X86::SAR32ri: return MakeMIInst(X86::SAR32mi, FrameIndex, MI);
Chris Lattner40ff6332005-01-19 07:50:03 +0000[diff] [blame]285 case X86::ROL8rCL: return MakeMInst( X86::ROL8mCL ,FrameIndex, MI);
286 case X86::ROL16rCL: return MakeMInst( X86::ROL16mCL,FrameIndex, MI);
287 case X86::ROL32rCL: return MakeMInst( X86::ROL32mCL,FrameIndex, MI);
288 case X86::ROL8ri: return MakeMIInst(X86::ROL8mi , FrameIndex, MI);
289 case X86::ROL16ri: return MakeMIInst(X86::ROL16mi, FrameIndex, MI);
290 case X86::ROL32ri: return MakeMIInst(X86::ROL32mi, FrameIndex, MI);
291 case X86::ROR8rCL: return MakeMInst( X86::ROR8mCL ,FrameIndex, MI);
292 case X86::ROR16rCL: return MakeMInst( X86::ROR16mCL,FrameIndex, MI);
293 case X86::ROR32rCL: return MakeMInst( X86::ROR32mCL,FrameIndex, MI);
294 case X86::ROR8ri: return MakeMIInst(X86::ROR8mi , FrameIndex, MI);
295 case X86::ROR16ri: return MakeMIInst(X86::ROR16mi, FrameIndex, MI);
296 case X86::ROR32ri: return MakeMIInst(X86::ROR32mi, FrameIndex, MI);
Alkis Evlogimenos39354c92004-03-14 07:19:51 +0000[diff] [blame]297 case X86::SHLD32rrCL:return MakeMRInst( X86::SHLD32mrCL,FrameIndex, MI);
298 case X86::SHLD32rri8:return MakeMRIInst(X86::SHLD32mri8,FrameIndex, MI);
299 case X86::SHRD32rrCL:return MakeMRInst( X86::SHRD32mrCL,FrameIndex, MI);
300 case X86::SHRD32rri8:return MakeMRIInst(X86::SHRD32mri8,FrameIndex, MI);
Chris Lattner0df53d22005-01-19 07:31:24 +0000[diff] [blame]301 case X86::SHLD16rrCL:return MakeMRInst( X86::SHLD16mrCL,FrameIndex, MI);
302 case X86::SHLD16rri8:return MakeMRIInst(X86::SHLD16mri8,FrameIndex, MI);
303 case X86::SHRD16rrCL:return MakeMRInst( X86::SHRD16mrCL,FrameIndex, MI);
304 case X86::SHRD16rri8:return MakeMRIInst(X86::SHRD16mri8,FrameIndex, MI);
Alkis Evlogimenos39354c92004-03-14 07:19:51 +0000[diff] [blame]305 case X86::SETBr: return MakeMInst( X86::SETBm, FrameIndex, MI);
306 case X86::SETAEr: return MakeMInst( X86::SETAEm, FrameIndex, MI);
307 case X86::SETEr: return MakeMInst( X86::SETEm, FrameIndex, MI);
308 case X86::SETNEr: return MakeMInst( X86::SETNEm, FrameIndex, MI);
309 case X86::SETBEr: return MakeMInst( X86::SETBEm, FrameIndex, MI);
310 case X86::SETAr: return MakeMInst( X86::SETAm, FrameIndex, MI);
311 case X86::SETSr: return MakeMInst( X86::SETSm, FrameIndex, MI);
312 case X86::SETNSr: return MakeMInst( X86::SETNSm, FrameIndex, MI);
Chris Lattner665e6612004-06-11 04:30:06 +0000[diff] [blame]313 case X86::SETPr: return MakeMInst( X86::SETPm, FrameIndex, MI);
Chris Lattnereb96ec52005-01-02 02:37:46 +0000[diff] [blame]314 case X86::SETNPr: return MakeMInst( X86::SETNPm, FrameIndex, MI);
Alkis Evlogimenos39354c92004-03-14 07:19:51 +0000[diff] [blame]315 case X86::SETLr: return MakeMInst( X86::SETLm, FrameIndex, MI);
316 case X86::SETGEr: return MakeMInst( X86::SETGEm, FrameIndex, MI);
317 case X86::SETLEr: return MakeMInst( X86::SETLEm, FrameIndex, MI);
318 case X86::SETGr: return MakeMInst( X86::SETGm, FrameIndex, MI);
Evan Cheng8586b952006-03-17 02:36:22 +0000[diff] [blame]319 // Alias instructions
320 case X86::MOV8r0: return MakeM0Inst(X86::MOV8mi, FrameIndex, MI);
321 case X86::MOV16r0: return MakeM0Inst(X86::MOV16mi, FrameIndex, MI);
322 case X86::MOV32r0: return MakeM0Inst(X86::MOV32mi, FrameIndex, MI);
Evan Chengfe5cb192006-02-16 22:45:17 +0000[diff] [blame]323 // Alias scalar SSE instructions
324 case X86::FsMOVAPSrr: return MakeMRInst(X86::MOVSSmr, FrameIndex, MI);
325 case X86::FsMOVAPDrr: return MakeMRInst(X86::MOVSDmr, FrameIndex, MI);
Evan Chengb1b4e862006-02-01 23:02:25 +0000[diff] [blame]326 // Scalar SSE instructions
327 case X86::MOVSSrr: return MakeMRInst(X86::MOVSSmr, FrameIndex, MI);
328 case X86::MOVSDrr: return MakeMRInst(X86::MOVSDmr, FrameIndex, MI);
Evan Chengb1b4e862006-02-01 23:02:25 +0000[diff] [blame]329 // Packed SSE instructions
Evan Chengb1b4e862006-02-01 23:02:25 +0000[diff] [blame]330 case X86::MOVAPSrr: return MakeMRInst(X86::MOVAPSmr, FrameIndex, MI);
331 case X86::MOVAPDrr: return MakeMRInst(X86::MOVAPDmr, FrameIndex, MI);
Evan Cheng407428e2006-04-14 23:33:27 +0000[diff] [blame]332 case X86::MOVUPSrr: return MakeMRInst(X86::MOVUPSmr, FrameIndex, MI);
333 case X86::MOVUPDrr: return MakeMRInst(X86::MOVUPDmr, FrameIndex, MI);
334 // Alias packed SSE instructions
335 case X86::MOVPS2SSrr:return MakeMRInst(X86::MOVPS2SSmr, FrameIndex, MI);
336 case X86::MOVPDI2DIrr:return MakeMRInst(X86::MOVPDI2DImr, FrameIndex, MI);
Chris Lattner7c035b72004-02-17 05:35:13 +0000[diff] [blame]337 }
338 } else if (i == 1) {
339 switch(MI->getOpcode()) {
Alkis Evlogimenos39354c92004-03-14 07:19:51 +0000[diff] [blame]340 case X86::XCHG8rr: return MakeRMInst(X86::XCHG8rm ,FrameIndex, MI);
341 case X86::XCHG16rr: return MakeRMInst(X86::XCHG16rm,FrameIndex, MI);
342 case X86::XCHG32rr: return MakeRMInst(X86::XCHG32rm,FrameIndex, MI);
343 case X86::MOV8rr: return MakeRMInst(X86::MOV8rm , FrameIndex, MI);
344 case X86::MOV16rr: return MakeRMInst(X86::MOV16rm, FrameIndex, MI);
345 case X86::MOV32rr: return MakeRMInst(X86::MOV32rm, FrameIndex, MI);
Chris Lattner87d3bb52004-03-30 21:29:47 +0000[diff] [blame]346 case X86::CMOVB16rr: return MakeRMInst(X86::CMOVB16rm , FrameIndex, MI);
347 case X86::CMOVB32rr: return MakeRMInst(X86::CMOVB32rm , FrameIndex, MI);
348 case X86::CMOVAE16rr: return MakeRMInst(X86::CMOVAE16rm , FrameIndex, MI);
349 case X86::CMOVAE32rr: return MakeRMInst(X86::CMOVAE32rm , FrameIndex, MI);
Alkis Evlogimenos39354c92004-03-14 07:19:51 +0000[diff] [blame]350 case X86::CMOVE16rr: return MakeRMInst(X86::CMOVE16rm , FrameIndex, MI);
Chris Lattner87d3bb52004-03-30 21:29:47 +0000[diff] [blame]351 case X86::CMOVE32rr: return MakeRMInst(X86::CMOVE32rm , FrameIndex, MI);
352 case X86::CMOVNE16rr:return MakeRMInst(X86::CMOVNE16rm, FrameIndex, MI);
Alkis Evlogimenos39354c92004-03-14 07:19:51 +0000[diff] [blame]353 case X86::CMOVNE32rr:return MakeRMInst(X86::CMOVNE32rm, FrameIndex, MI);
Chris Lattner87d3bb52004-03-30 21:29:47 +0000[diff] [blame]354 case X86::CMOVBE16rr:return MakeRMInst(X86::CMOVBE16rm, FrameIndex, MI);
355 case X86::CMOVBE32rr:return MakeRMInst(X86::CMOVBE32rm, FrameIndex, MI);
356 case X86::CMOVA16rr:return MakeRMInst(X86::CMOVA16rm, FrameIndex, MI);
357 case X86::CMOVA32rr:return MakeRMInst(X86::CMOVA32rm, FrameIndex, MI);
358 case X86::CMOVS16rr: return MakeRMInst(X86::CMOVS16rm , FrameIndex, MI);
Alkis Evlogimenos39354c92004-03-14 07:19:51 +0000[diff] [blame]359 case X86::CMOVS32rr: return MakeRMInst(X86::CMOVS32rm , FrameIndex, MI);
Chris Lattner87d3bb52004-03-30 21:29:47 +0000[diff] [blame]360 case X86::CMOVNS16rr: return MakeRMInst(X86::CMOVNS16rm , FrameIndex, MI);
361 case X86::CMOVNS32rr: return MakeRMInst(X86::CMOVNS32rm , FrameIndex, MI);
Chris Lattner57fbfb52005-01-10 22:09:33 +0000[diff] [blame]362 case X86::CMOVP16rr: return MakeRMInst(X86::CMOVP16rm , FrameIndex, MI);
363 case X86::CMOVP32rr: return MakeRMInst(X86::CMOVP32rm , FrameIndex, MI);
364 case X86::CMOVNP16rr: return MakeRMInst(X86::CMOVNP16rm , FrameIndex, MI);
365 case X86::CMOVNP32rr: return MakeRMInst(X86::CMOVNP32rm , FrameIndex, MI);
Chris Lattner87d3bb52004-03-30 21:29:47 +0000[diff] [blame]366 case X86::CMOVL16rr: return MakeRMInst(X86::CMOVL16rm , FrameIndex, MI);
367 case X86::CMOVL32rr: return MakeRMInst(X86::CMOVL32rm , FrameIndex, MI);
368 case X86::CMOVGE16rr: return MakeRMInst(X86::CMOVGE16rm , FrameIndex, MI);
369 case X86::CMOVGE32rr: return MakeRMInst(X86::CMOVGE32rm , FrameIndex, MI);
370 case X86::CMOVLE16rr: return MakeRMInst(X86::CMOVLE16rm , FrameIndex, MI);
371 case X86::CMOVLE32rr: return MakeRMInst(X86::CMOVLE32rm , FrameIndex, MI);
372 case X86::CMOVG16rr: return MakeRMInst(X86::CMOVG16rm , FrameIndex, MI);
373 case X86::CMOVG32rr: return MakeRMInst(X86::CMOVG32rm , FrameIndex, MI);
Alkis Evlogimenos39354c92004-03-14 07:19:51 +0000[diff] [blame]374 case X86::ADD8rr: return MakeRMInst(X86::ADD8rm , FrameIndex, MI);
375 case X86::ADD16rr: return MakeRMInst(X86::ADD16rm, FrameIndex, MI);
376 case X86::ADD32rr: return MakeRMInst(X86::ADD32rm, FrameIndex, MI);
377 case X86::ADC32rr: return MakeRMInst(X86::ADC32rm, FrameIndex, MI);
378 case X86::SUB8rr: return MakeRMInst(X86::SUB8rm , FrameIndex, MI);
379 case X86::SUB16rr: return MakeRMInst(X86::SUB16rm, FrameIndex, MI);
380 case X86::SUB32rr: return MakeRMInst(X86::SUB32rm, FrameIndex, MI);
381 case X86::SBB32rr: return MakeRMInst(X86::SBB32rm, FrameIndex, MI);
382 case X86::AND8rr: return MakeRMInst(X86::AND8rm , FrameIndex, MI);
383 case X86::AND16rr: return MakeRMInst(X86::AND16rm, FrameIndex, MI);
384 case X86::AND32rr: return MakeRMInst(X86::AND32rm, FrameIndex, MI);
385 case X86::OR8rr: return MakeRMInst(X86::OR8rm , FrameIndex, MI);
386 case X86::OR16rr: return MakeRMInst(X86::OR16rm, FrameIndex, MI);
387 case X86::OR32rr: return MakeRMInst(X86::OR32rm, FrameIndex, MI);
388 case X86::XOR8rr: return MakeRMInst(X86::XOR8rm , FrameIndex, MI);
389 case X86::XOR16rr: return MakeRMInst(X86::XOR16rm, FrameIndex, MI);
390 case X86::XOR32rr: return MakeRMInst(X86::XOR32rm, FrameIndex, MI);
Alkis Evlogimenos39354c92004-03-14 07:19:51 +0000[diff] [blame]391 case X86::IMUL16rr: return MakeRMInst(X86::IMUL16rm,FrameIndex, MI);
392 case X86::IMUL32rr: return MakeRMInst(X86::IMUL32rm,FrameIndex, MI);
393 case X86::IMUL16rri: return MakeRMIInst(X86::IMUL16rmi, FrameIndex, MI);
394 case X86::IMUL32rri: return MakeRMIInst(X86::IMUL32rmi, FrameIndex, MI);
Evan Cheng5bd4d482006-03-17 02:25:01 +0000[diff] [blame]395 case X86::IMUL16rri8:return MakeRMIInst(X86::IMUL16rmi8, FrameIndex, MI);
396 case X86::IMUL32rri8:return MakeRMIInst(X86::IMUL32rmi8, FrameIndex, MI);
Evan Cheng51c9c432006-04-17 18:06:12 +0000[diff] [blame]397 case X86::TEST8rr: return MakeRMInst(X86::TEST8rm ,FrameIndex, MI);
398 case X86::TEST16rr: return MakeRMInst(X86::TEST16rm,FrameIndex, MI);
399 case X86::TEST32rr: return MakeRMInst(X86::TEST32rm,FrameIndex, MI);
400 case X86::TEST8ri: return MakeMIInst(X86::TEST8mi ,FrameIndex, MI);
401 case X86::TEST16ri: return MakeMIInst(X86::TEST16mi,FrameIndex, MI);
402 case X86::TEST32ri: return MakeMIInst(X86::TEST32mi,FrameIndex, MI);
Alkis Evlogimenos39354c92004-03-14 07:19:51 +0000[diff] [blame]403 case X86::CMP8rr: return MakeRMInst(X86::CMP8rm , FrameIndex, MI);
404 case X86::CMP16rr: return MakeRMInst(X86::CMP16rm, FrameIndex, MI);
405 case X86::CMP32rr: return MakeRMInst(X86::CMP32rm, FrameIndex, MI);
Evan Cheng407428e2006-04-14 23:33:27 +0000[diff] [blame]406 case X86::CMP8ri: return MakeRMInst(X86::CMP8mi , FrameIndex, MI);
407 case X86::CMP16ri: return MakeMIInst(X86::CMP16mi, FrameIndex, MI);
408 case X86::CMP32ri: return MakeMIInst(X86::CMP32mi, FrameIndex, MI);
409 case X86::CMP16ri8: return MakeMIInst(X86::CMP16mi8, FrameIndex, MI);
410 case X86::CMP32ri8: return MakeRMInst(X86::CMP32mi8, FrameIndex, MI);
Alkis Evlogimenos39354c92004-03-14 07:19:51 +0000[diff] [blame]411 case X86::MOVSX16rr8:return MakeRMInst(X86::MOVSX16rm8 , FrameIndex, MI);
412 case X86::MOVSX32rr8:return MakeRMInst(X86::MOVSX32rm8, FrameIndex, MI);
413 case X86::MOVSX32rr16:return MakeRMInst(X86::MOVSX32rm16, FrameIndex, MI);
414 case X86::MOVZX16rr8:return MakeRMInst(X86::MOVZX16rm8 , FrameIndex, MI);
Evan Chengb1b4e862006-02-01 23:02:25 +0000[diff] [blame]415 case X86::MOVZX32rr8:return MakeRMInst(X86::MOVZX32rm8, FrameIndex, MI);
Alkis Evlogimenos39354c92004-03-14 07:19:51 +0000[diff] [blame]416 case X86::MOVZX32rr16:return MakeRMInst(X86::MOVZX32rm16, FrameIndex, MI);
Evan Chengfe5cb192006-02-16 22:45:17 +0000[diff] [blame]417 // Alias scalar SSE instructions
418 case X86::FsMOVAPSrr:return MakeRMInst(X86::MOVSSrm, FrameIndex, MI);
419 case X86::FsMOVAPDrr:return MakeRMInst(X86::MOVSDrm, FrameIndex, MI);
Evan Chengb1b4e862006-02-01 23:02:25 +0000[diff] [blame]420 // Scalar SSE instructions
421 case X86::MOVSSrr: return MakeRMInst(X86::MOVSSrm, FrameIndex, MI);
422 case X86::MOVSDrr: return MakeRMInst(X86::MOVSDrm, FrameIndex, MI);
Evan Cheng407428e2006-04-14 23:33:27 +0000[diff] [blame]423 case X86::CVTSS2SIrr:return MakeRMInst(X86::CVTSS2SIrm, FrameIndex, MI);
Evan Chengb1b4e862006-02-01 23:02:25 +0000[diff] [blame]424 case X86::CVTTSS2SIrr:return MakeRMInst(X86::CVTTSS2SIrm, FrameIndex, MI);
Evan Cheng407428e2006-04-14 23:33:27 +0000[diff] [blame]425 case X86::CVTSD2SIrr:return MakeRMInst(X86::CVTSD2SIrm, FrameIndex, MI);
Evan Chengb1b4e862006-02-01 23:02:25 +0000[diff] [blame]426 case X86::CVTTSD2SIrr:return MakeRMInst(X86::CVTTSD2SIrm, FrameIndex, MI);
427 case X86::CVTSS2SDrr:return MakeRMInst(X86::CVTSS2SDrm, FrameIndex, MI);
428 case X86::CVTSD2SSrr:return MakeRMInst(X86::CVTSD2SSrm, FrameIndex, MI);
429 case X86::CVTSI2SSrr:return MakeRMInst(X86::CVTSI2SSrm, FrameIndex, MI);
430 case X86::CVTSI2SDrr:return MakeRMInst(X86::CVTSI2SDrm, FrameIndex, MI);
Evan Cheng407428e2006-04-14 23:33:27 +0000[diff] [blame]431 case X86::Int_CVTTSS2SIrr:
432 return MakeRMInst(X86::Int_CVTTSS2SIrm, FrameIndex, MI);
433 case X86::Int_CVTTSD2SIrr:
434 return MakeRMInst(X86::Int_CVTTSD2SIrm, FrameIndex, MI);
435 case X86::Int_CVTSI2SSrr:
436 return MakeRMInst(X86::Int_CVTSI2SSrm, FrameIndex, MI);
Evan Cheng8703be42006-04-04 19:12:30 +0000[diff] [blame]437 case X86::SQRTSSr: return MakeRMInst(X86::SQRTSSm, FrameIndex, MI);
438 case X86::SQRTSDr: return MakeRMInst(X86::SQRTSDm, FrameIndex, MI);
Evan Chengb1b4e862006-02-01 23:02:25 +0000[diff] [blame]439 case X86::ADDSSrr: return MakeRMInst(X86::ADDSSrm, FrameIndex, MI);
440 case X86::ADDSDrr: return MakeRMInst(X86::ADDSDrm, FrameIndex, MI);
441 case X86::MULSSrr: return MakeRMInst(X86::MULSSrm, FrameIndex, MI);
442 case X86::MULSDrr: return MakeRMInst(X86::MULSDrm, FrameIndex, MI);
443 case X86::DIVSSrr: return MakeRMInst(X86::DIVSSrm, FrameIndex, MI);
444 case X86::DIVSDrr: return MakeRMInst(X86::DIVSDrm, FrameIndex, MI);
445 case X86::SUBSSrr: return MakeRMInst(X86::SUBSSrm, FrameIndex, MI);
446 case X86::SUBSDrr: return MakeRMInst(X86::SUBSDrm, FrameIndex, MI);
447 case X86::CMPSSrr: return MakeRMInst(X86::CMPSSrm, FrameIndex, MI);
448 case X86::CMPSDrr: return MakeRMInst(X86::CMPSDrm, FrameIndex, MI);
Evan Cheng407428e2006-04-14 23:33:27 +0000[diff] [blame]449 case X86::Int_CMPSSrr: return MakeRMInst(X86::Int_CMPSSrm, FrameIndex, MI);
450 case X86::Int_CMPSDrr: return MakeRMInst(X86::Int_CMPSDrm, FrameIndex, MI);
451 case X86::UCOMISSrr: return MakeRMInst(X86::UCOMISSrm, FrameIndex, MI);
452 case X86::UCOMISDrr: return MakeRMInst(X86::UCOMISDrm, FrameIndex, MI);
453 case X86::Int_UCOMISSrr:
454 return MakeRMInst(X86::Int_UCOMISSrm, FrameIndex, MI);
455 case X86::Int_UCOMISDrr:
456 return MakeRMInst(X86::Int_UCOMISDrm, FrameIndex, MI);
457 case X86::Int_COMISSrr:
458 return MakeRMInst(X86::Int_COMISSrm, FrameIndex, MI);
459 case X86::Int_COMISDrr:
460 return MakeRMInst(X86::Int_COMISDrm, FrameIndex, MI);
Evan Chengb1b4e862006-02-01 23:02:25 +0000[diff] [blame]461 // Packed SSE instructions
Evan Cheng407428e2006-04-14 23:33:27 +0000[diff] [blame]462 case X86::MOVAPSrr: return MakeRMInst(X86::MOVAPSrm, FrameIndex, MI);
463 case X86::MOVAPDrr: return MakeRMInst(X86::MOVAPDrm, FrameIndex, MI);
464 case X86::MOVUPSrr: return MakeRMInst(X86::MOVUPSrm, FrameIndex, MI);
465 case X86::MOVUPDrr: return MakeRMInst(X86::MOVUPDrm, FrameIndex, MI);
466 case X86::MOVSHDUPrr:return MakeRMInst(X86::MOVSHDUPrm, FrameIndex, MI);
467 case X86::MOVSLDUPrr:return MakeRMInst(X86::MOVSLDUPrm, FrameIndex, MI);
468 case X86::MOVDDUPrr: return MakeRMInst(X86::MOVDDUPrm, FrameIndex, MI);
469 case X86::CVTDQ2PSrr:return MakeRMInst(X86::CVTDQ2PSrm, FrameIndex, MI);
470 case X86::CVTDQ2PDrr:return MakeRMInst(X86::CVTDQ2PDrm, FrameIndex, MI);
471 case X86::CVTPS2DQrr:return MakeRMInst(X86::CVTPS2DQrm, FrameIndex, MI);
472 case X86::CVTTPS2DQrr:return MakeRMInst(X86::CVTTPS2DQrm, FrameIndex, MI);
473 case X86::CVTPD2DQrr:return MakeRMInst(X86::CVTPD2DQrm, FrameIndex, MI);
474 case X86::CVTTPD2DQrr:return MakeRMInst(X86::CVTTPD2DQrm, FrameIndex, MI);
475 case X86::CVTPS2PDrr:return MakeRMInst(X86::CVTPS2PDrm, FrameIndex, MI);
476 case X86::CVTPD2PSrr:return MakeRMInst(X86::CVTPD2PSrm, FrameIndex, MI);
477 case X86::Int_CVTSI2SDrr:
478 return MakeRMInst(X86::Int_CVTSI2SDrm, FrameIndex, MI);
479 case X86::Int_CVTSD2SSrr:
480 return MakeRMInst(X86::Int_CVTSD2SSrm, FrameIndex, MI);
481 case X86::Int_CVTSS2SDrr:
482 return MakeRMInst(X86::Int_CVTSS2SDrm, FrameIndex, MI);
483 case X86::ADDPSrr: return MakeRMInst(X86::ADDPSrm, FrameIndex, MI);
484 case X86::ADDPDrr: return MakeRMInst(X86::ADDPDrm, FrameIndex, MI);
485 case X86::SUBPSrr: return MakeRMInst(X86::SUBPSrm, FrameIndex, MI);
486 case X86::SUBPDrr: return MakeRMInst(X86::SUBPDrm, FrameIndex, MI);
487 case X86::MULPSrr: return MakeRMInst(X86::MULPSrm, FrameIndex, MI);
488 case X86::MULPDrr: return MakeRMInst(X86::MULPDrm, FrameIndex, MI);
489 case X86::DIVPSrr: return MakeRMInst(X86::DIVPSrm, FrameIndex, MI);
490 case X86::DIVPDrr: return MakeRMInst(X86::DIVPDrm, FrameIndex, MI);
491 case X86::ADDSUBPSrr:return MakeRMInst(X86::ADDSUBPSrm, FrameIndex, MI);
492 case X86::ADDSUBPDrr:return MakeRMInst(X86::ADDSUBPDrm, FrameIndex, MI);
493 case X86::HADDPSrr: return MakeRMInst(X86::HADDPSrm, FrameIndex, MI);
494 case X86::HADDPDrr: return MakeRMInst(X86::HADDPDrm, FrameIndex, MI);
495 case X86::HSUBPSrr: return MakeRMInst(X86::HSUBPSrm, FrameIndex, MI);
496 case X86::HSUBPDrr: return MakeRMInst(X86::HSUBPDrm, FrameIndex, MI);
497 case X86::SQRTPSr: return MakeRMInst(X86::SQRTPSm, FrameIndex, MI);
498 case X86::SQRTPDr: return MakeRMInst(X86::SQRTPDm, FrameIndex, MI);
499 case X86::RSQRTPSr: return MakeRMInst(X86::RSQRTPSm, FrameIndex, MI);
500 case X86::RCPPSr: return MakeRMInst(X86::RCPPSm, FrameIndex, MI);
501 case X86::MAXPSrr: return MakeRMInst(X86::MAXPSrm, FrameIndex, MI);
502 case X86::MAXPDrr: return MakeRMInst(X86::MAXPDrm, FrameIndex, MI);
503 case X86::MINPSrr: return MakeRMInst(X86::MINPSrm, FrameIndex, MI);
504 case X86::MINPDrr: return MakeRMInst(X86::MINPDrm, FrameIndex, MI);
Evan Chengb1b4e862006-02-01 23:02:25 +0000[diff] [blame]505 case X86::ANDPSrr: return MakeRMInst(X86::ANDPSrm, FrameIndex, MI);
506 case X86::ANDPDrr: return MakeRMInst(X86::ANDPDrm, FrameIndex, MI);
507 case X86::ORPSrr: return MakeRMInst(X86::ORPSrm, FrameIndex, MI);
508 case X86::ORPDrr: return MakeRMInst(X86::ORPDrm, FrameIndex, MI);
509 case X86::XORPSrr: return MakeRMInst(X86::XORPSrm, FrameIndex, MI);
510 case X86::XORPDrr: return MakeRMInst(X86::XORPDrm, FrameIndex, MI);
511 case X86::ANDNPSrr: return MakeRMInst(X86::ANDNPSrm, FrameIndex, MI);
512 case X86::ANDNPDrr: return MakeRMInst(X86::ANDNPDrm, FrameIndex, MI);
Evan Chenga52b2142006-04-18 21:31:08 +0000[diff] [blame]513 case X86::CMPPSrri: return MakeRMIInst(X86::CMPPSrmi, FrameIndex, MI);
514 case X86::CMPPDrri: return MakeRMIInst(X86::CMPPDrmi, FrameIndex, MI);
Evan Chengf463f512006-04-18 21:56:36 +0000[diff] [blame^]515 case X86::SHUFPSrri: return MakeRMIInst(X86::SHUFPSrmi, FrameIndex, MI);
516 case X86::SHUFPDrri: return MakeRMIInst(X86::SHUFPDrmi, FrameIndex, MI);
Evan Cheng407428e2006-04-14 23:33:27 +0000[diff] [blame]517 case X86::UNPCKHPSrr:return MakeRMInst(X86::UNPCKHPSrm, FrameIndex, MI);
518 case X86::UNPCKHPDrr:return MakeRMInst(X86::UNPCKHPDrm, FrameIndex, MI);
519 case X86::UNPCKLPSrr:return MakeRMInst(X86::UNPCKLPSrm, FrameIndex, MI);
520 case X86::UNPCKLPDrr:return MakeRMInst(X86::UNPCKLPDrm, FrameIndex, MI);
521 case X86::PADDBrr: return MakeRMInst(X86::PADDBrm, FrameIndex, MI);
522 case X86::PADDWrr: return MakeRMInst(X86::PADDWrm, FrameIndex, MI);
523 case X86::PADDDrr: return MakeRMInst(X86::PADDDrm, FrameIndex, MI);
524 case X86::PADDSBrr: return MakeRMInst(X86::PADDSBrm, FrameIndex, MI);
525 case X86::PADDSWrr: return MakeRMInst(X86::PADDSWrm, FrameIndex, MI);
526 case X86::PSUBBrr: return MakeRMInst(X86::PSUBBrm, FrameIndex, MI);
527 case X86::PSUBWrr: return MakeRMInst(X86::PSUBWrm, FrameIndex, MI);
528 case X86::PSUBDrr: return MakeRMInst(X86::PSUBDrm, FrameIndex, MI);
529 case X86::PSUBSBrr: return MakeRMInst(X86::PSUBSBrm, FrameIndex, MI);
530 case X86::PSUBSWrr: return MakeRMInst(X86::PSUBSWrm, FrameIndex, MI);
531 case X86::PMULHUWrr: return MakeRMInst(X86::PMULHUWrm, FrameIndex, MI);
532 case X86::PMULHWrr: return MakeRMInst(X86::PMULHWrm, FrameIndex, MI);
533 case X86::PMULLWrr: return MakeRMInst(X86::PMULLWrm, FrameIndex, MI);
534 case X86::PMULUDQrr: return MakeRMInst(X86::PMULUDQrm, FrameIndex, MI);
535 case X86::PMADDWDrr: return MakeRMInst(X86::PMADDWDrm, FrameIndex, MI);
536 case X86::PAVGBrr: return MakeRMInst(X86::PAVGBrm, FrameIndex, MI);
537 case X86::PAVGWrr: return MakeRMInst(X86::PAVGWrm, FrameIndex, MI);
538 case X86::PMAXUBrr: return MakeRMInst(X86::PMAXUBrm, FrameIndex, MI);
539 case X86::PMAXSWrr: return MakeRMInst(X86::PMAXSWrm, FrameIndex, MI);
540 case X86::PMINUBrr: return MakeRMInst(X86::PMINUBrm, FrameIndex, MI);
541 case X86::PMINSWrr: return MakeRMInst(X86::PMINSWrm, FrameIndex, MI);
542 case X86::PSADBWrr: return MakeRMInst(X86::PSADBWrm, FrameIndex, MI);
543 case X86::PSLLWrr: return MakeRMInst(X86::PSLLWrm, FrameIndex, MI);
544 case X86::PSLLDrr: return MakeRMInst(X86::PSLLDrm, FrameIndex, MI);
545 case X86::PSLLQrr: return MakeRMInst(X86::PSLLQrm, FrameIndex, MI);
546 case X86::PSRLWrr: return MakeRMInst(X86::PSRLWrm, FrameIndex, MI);
547 case X86::PSRLDrr: return MakeRMInst(X86::PSRLDrm, FrameIndex, MI);
548 case X86::PSRLQrr: return MakeRMInst(X86::PSRLQrm, FrameIndex, MI);
549 case X86::PSRAWrr: return MakeRMInst(X86::PSRAWrm, FrameIndex, MI);
550 case X86::PSRADrr: return MakeRMInst(X86::PSRADrm, FrameIndex, MI);
551 case X86::PANDrr: return MakeRMInst(X86::PANDrm, FrameIndex, MI);
552 case X86::PORrr: return MakeRMInst(X86::PORrm, FrameIndex, MI);
553 case X86::PXORrr: return MakeRMInst(X86::PXORrm, FrameIndex, MI);
554 case X86::PANDNrr: return MakeRMInst(X86::PANDNrm, FrameIndex, MI);
555 case X86::PCMPEQBrr: return MakeRMInst(X86::PCMPEQBrm, FrameIndex, MI);
556 case X86::PCMPEQWrr: return MakeRMInst(X86::PCMPEQWrm, FrameIndex, MI);
557 case X86::PCMPEQDrr: return MakeRMInst(X86::PCMPEQDrm, FrameIndex, MI);
558 case X86::PCMPGTBrr: return MakeRMInst(X86::PCMPGTBrm, FrameIndex, MI);
559 case X86::PCMPGTWrr: return MakeRMInst(X86::PCMPGTWrm, FrameIndex, MI);
560 case X86::PCMPGTDrr: return MakeRMInst(X86::PCMPGTDrm, FrameIndex, MI);
561 case X86::PACKSSWBrr:return MakeRMInst(X86::PACKSSWBrm, FrameIndex, MI);
562 case X86::PACKSSDWrr:return MakeRMInst(X86::PACKSSDWrm, FrameIndex, MI);
563 case X86::PACKUSWBrr:return MakeRMInst(X86::PACKUSWBrm, FrameIndex, MI);
Evan Chengf463f512006-04-18 21:56:36 +0000[diff] [blame^]564 case X86::PSHUFDri: return MakeRMIInst(X86::PSHUFDmi, FrameIndex, MI);
565 case X86::PSHUFHWri: return MakeRMIInst(X86::PSHUFHWmi, FrameIndex, MI);
566 case X86::PSHUFLWri: return MakeRMIInst(X86::PSHUFLWmi, FrameIndex, MI);
Evan Cheng407428e2006-04-14 23:33:27 +0000[diff] [blame]567 case X86::PUNPCKLBWrr:return MakeRMInst(X86::PUNPCKLBWrm, FrameIndex, MI);
568 case X86::PUNPCKLWDrr:return MakeRMInst(X86::PUNPCKLWDrm, FrameIndex, MI);
569 case X86::PUNPCKLDQrr:return MakeRMInst(X86::PUNPCKLDQrm, FrameIndex, MI);
570 case X86::PUNPCKLQDQrr:return MakeRMInst(X86::PUNPCKLQDQrm, FrameIndex, MI);
571 case X86::PUNPCKHBWrr:return MakeRMInst(X86::PUNPCKHBWrm, FrameIndex, MI);
572 case X86::PUNPCKHWDrr:return MakeRMInst(X86::PUNPCKHWDrm, FrameIndex, MI);
573 case X86::PUNPCKHDQrr:return MakeRMInst(X86::PUNPCKHDQrm, FrameIndex, MI);
574 case X86::PUNPCKHQDQrr:return MakeRMInst(X86::PUNPCKHQDQrm, FrameIndex, MI);
575 case X86::PEXTRWri: return MakeRMInst(X86::PEXTRWmi, FrameIndex, MI);
576 case X86::PINSRWrri: return MakeRMInst(X86::PINSRWrmi, FrameIndex, MI);
577 // Alias packed SSE instructions
578 case X86::MOVSS2PSrr:return MakeRMInst(X86::MOVSS2PSrm, FrameIndex, MI);
579 case X86::MOVSD2PDrr:return MakeRMInst(X86::MOVSD2PDrm, FrameIndex, MI);
580 case X86::MOVDI2PDIrr:return MakeRMInst(X86::MOVDI2PDIrm, FrameIndex, MI);
581 case X86::MOVQI2PQIrr:return MakeRMInst(X86::MOVQI2PQIrm, FrameIndex, MI);
Chris Lattner7c035b72004-02-17 05:35:13 +0000[diff] [blame]582 }
Alkis Evlogimenosb4998662004-02-17 04:33:18 +0000[diff] [blame]583 }
Alkis Evlogimenos39354c92004-03-14 07:19:51 +0000[diff] [blame]584 if (PrintFailedFusing)
Evan Cheng407428e2006-04-14 23:33:27 +0000[diff] [blame]585 std::cerr << "We failed to fuse ("
586 << ((i == 1) ? "r" : "s") << "): " << *MI;
Alkis Evlogimenos39354c92004-03-14 07:19:51 +0000[diff] [blame]587 return NULL;
Alkis Evlogimenosb4998662004-02-17 04:33:18 +0000[diff] [blame]588}
589
Chris Lattner3c1c03d2002-12-28 20:32:28 +0000[diff] [blame]590//===----------------------------------------------------------------------===//
591// Stack Frame Processing methods
592//===----------------------------------------------------------------------===//
593
594// hasFP - Return true if the specified function should have a dedicated frame
595// pointer register. This is true if the function has variable sized allocas or
596// if frame pointer elimination is disabled.
597//
598static bool hasFP(MachineFunction &MF) {
Misha Brukman66d6ee42004-06-21 21:17:44 +0000[diff] [blame]599 return NoFramePointerElim || MF.getFrameInfo()->hasVarSizedObjects();
Misha Brukman03c6faf2002-12-03 23:11:21 +0000[diff] [blame]600}
Misha Brukman2adb3952002-12-04 23:57:03 +0000[diff] [blame]601
Chris Lattnerbb07ef92004-02-14 19:49:54 +0000[diff] [blame]602void X86RegisterInfo::
603eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
604 MachineBasicBlock::iterator I) const {
Chris Lattner3c1c03d2002-12-28 20:32:28 +0000[diff] [blame]605 if (hasFP(MF)) {
606 // If we have a frame pointer, turn the adjcallstackup instruction into a
607 // 'sub ESP, <amt>' and the adjcallstackdown instruction into 'add ESP,
608 // <amt>'
Chris Lattnerbb07ef92004-02-14 19:49:54 +0000[diff] [blame]609 MachineInstr *Old = I;
Chris Lattner3c1c03d2002-12-28 20:32:28 +0000[diff] [blame]610 unsigned Amount = Old->getOperand(0).getImmedValue();
611 if (Amount != 0) {
Chris Lattnerf158da22003-01-16 02:20:12 +0000[diff] [blame]612 // We need to keep the stack aligned properly. To do this, we round the
613 // amount of space needed for the outgoing arguments up to the next
614 // alignment boundary.
Chris Lattnerd029cd22004-06-02 05:55:25 +0000[diff] [blame]615 unsigned Align = MF.getTarget().getFrameInfo()->getStackAlignment();
Chris Lattnerf158da22003-01-16 02:20:12 +0000[diff] [blame]616 Amount = (Amount+Align-1)/Align*Align;
617
Chris Lattner3648c672005-05-13 21:44:04 +0000[diff] [blame]618 MachineInstr *New = 0;
Chris Lattner3c1c03d2002-12-28 20:32:28 +0000[diff] [blame]619 if (Old->getOpcode() == X86::ADJCALLSTACKDOWN) {
Jeff Cohen00b168892005-07-27 06:12:32 +0000[diff] [blame]620 New=BuildMI(X86::SUB32ri, 1, X86::ESP, MachineOperand::UseAndDef)
Alkis Evlogimenos890f9232004-02-22 19:23:26 +0000[diff] [blame]621 .addZImm(Amount);
Chris Lattner3c1c03d2002-12-28 20:32:28 +0000[diff] [blame]622 } else {
Jeff Cohen00b168892005-07-27 06:12:32 +0000[diff] [blame]623 assert(Old->getOpcode() == X86::ADJCALLSTACKUP);
Chris Lattner3648c672005-05-13 21:44:04 +0000[diff] [blame]624 // factor out the amount the callee already popped.
625 unsigned CalleeAmt = Old->getOperand(1).getImmedValue();
626 Amount -= CalleeAmt;
Chris Lattnerd77525d2006-02-03 18:20:04 +0000[diff] [blame]627 if (Amount) {
628 unsigned Opc = Amount < 128 ? X86::ADD32ri8 : X86::ADD32ri;
629 New = BuildMI(Opc, 1, X86::ESP,
Chris Lattner3648c672005-05-13 21:44:04 +0000[diff] [blame]630 MachineOperand::UseAndDef).addZImm(Amount);
Chris Lattnerd77525d2006-02-03 18:20:04 +0000[diff] [blame]631 }
Chris Lattner3c1c03d2002-12-28 20:32:28 +0000[diff] [blame]632 }
Chris Lattnerbb07ef92004-02-14 19:49:54 +0000[diff] [blame]633
634 // Replace the pseudo instruction with a new instruction...
Chris Lattner3648c672005-05-13 21:44:04 +0000[diff] [blame]635 if (New) MBB.insert(I, New);
636 }
637 } else if (I->getOpcode() == X86::ADJCALLSTACKUP) {
638 // If we are performing frame pointer elimination and if the callee pops
639 // something off the stack pointer, add it back. We do this until we have
640 // more advanced stack pointer tracking ability.
641 if (unsigned CalleeAmt = I->getOperand(1).getImmedValue()) {
Chris Lattnerd77525d2006-02-03 18:20:04 +0000[diff] [blame]642 unsigned Opc = CalleeAmt < 128 ? X86::SUB32ri8 : X86::SUB32ri;
Jeff Cohen00b168892005-07-27 06:12:32 +0000[diff] [blame]643 MachineInstr *New =
Chris Lattnerd77525d2006-02-03 18:20:04 +0000[diff] [blame]644 BuildMI(Opc, 1, X86::ESP,
Chris Lattner3648c672005-05-13 21:44:04 +0000[diff] [blame]645 MachineOperand::UseAndDef).addZImm(CalleeAmt);
Chris Lattnerbb07ef92004-02-14 19:49:54 +0000[diff] [blame]646 MBB.insert(I, New);
Chris Lattner3c1c03d2002-12-28 20:32:28 +0000[diff] [blame]647 }
648 }
649
Chris Lattnerbb07ef92004-02-14 19:49:54 +0000[diff] [blame]650 MBB.erase(I);
Chris Lattner3c1c03d2002-12-28 20:32:28 +0000[diff] [blame]651}
652
Nate Begemanf8be5e92004-08-14 22:05:10 +0000[diff] [blame]653void X86RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II) const{
Chris Lattnerd264bec2003-01-13 00:50:33 +0000[diff] [blame]654 unsigned i = 0;
Alkis Evlogimenosc0b9dc52004-02-12 02:27:10 +0000[diff] [blame]655 MachineInstr &MI = *II;
Nate Begemanf8be5e92004-08-14 22:05:10 +0000[diff] [blame]656 MachineFunction &MF = *MI.getParent()->getParent();
Chris Lattner3c1c03d2002-12-28 20:32:28 +0000[diff] [blame]657 while (!MI.getOperand(i).isFrameIndex()) {
658 ++i;
659 assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
660 }
661
Chris Lattner3c1c03d2002-12-28 20:32:28 +0000[diff] [blame]662 int FrameIndex = MI.getOperand(i).getFrameIndex();
Chris Lattnerd264bec2003-01-13 00:50:33 +0000[diff] [blame]663
664 // This must be part of a four operand memory reference. Replace the
665 // FrameIndex with base register with EBP. Add add an offset to the offset.
666 MI.SetMachineOperandReg(i, hasFP(MF) ? X86::EBP : X86::ESP);
667
668 // Now add the frame object offset to the offset from EBP.
669 int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex) +
Chris Lattnereafa4232003-01-15 22:57:35 +0000[diff] [blame]670 MI.getOperand(i+3).getImmedValue()+4;
Chris Lattner3c1c03d2002-12-28 20:32:28 +0000[diff] [blame]671
Chris Lattnerd5b7c472003-10-14 18:52:41 +0000[diff] [blame]672 if (!hasFP(MF))
673 Offset += MF.getFrameInfo()->getStackSize();
Chris Lattner96c3d2e2004-02-15 00:15:37 +0000[diff] [blame]674 else
675 Offset += 4; // Skip the saved EBP
Chris Lattner3c1c03d2002-12-28 20:32:28 +0000[diff] [blame]676
Chris Lattnerd264bec2003-01-13 00:50:33 +0000[diff] [blame]677 MI.SetMachineOperandConst(i+3, MachineOperand::MO_SignExtendedImmed, Offset);
Chris Lattner3c1c03d2002-12-28 20:32:28 +0000[diff] [blame]678}
679
Chris Lattnerbb07ef92004-02-14 19:49:54 +0000[diff] [blame]680void
681X86RegisterInfo::processFunctionBeforeFrameFinalized(MachineFunction &MF) const{
Chris Lattner3c1c03d2002-12-28 20:32:28 +0000[diff] [blame]682 if (hasFP(MF)) {
683 // Create a frame entry for the EBP register that must be saved.
Chris Lattner96c3d2e2004-02-15 00:15:37 +0000[diff] [blame]684 int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, -8);
685 assert(FrameIdx == MF.getFrameInfo()->getObjectIndexBegin() &&
686 "Slot for EBP register must be last in order to be found!");
Chris Lattner3c1c03d2002-12-28 20:32:28 +0000[diff] [blame]687 }
688}
689
Chris Lattnerbb07ef92004-02-14 19:49:54 +0000[diff] [blame]690void X86RegisterInfo::emitPrologue(MachineFunction &MF) const {
Chris Lattner198ab642002-12-15 20:06:35 +0000[diff] [blame]691 MachineBasicBlock &MBB = MF.front(); // Prolog goes in entry BB
692 MachineBasicBlock::iterator MBBI = MBB.begin();
Chris Lattnereafa4232003-01-15 22:57:35 +0000[diff] [blame]693 MachineFrameInfo *MFI = MF.getFrameInfo();
Chris Lattner3c1c03d2002-12-28 20:32:28 +0000[diff] [blame]694 MachineInstr *MI;
Misha Brukman2adb3952002-12-04 23:57:03 +0000[diff] [blame]695
Chris Lattner3c1c03d2002-12-28 20:32:28 +0000[diff] [blame]696 // Get the number of bytes to allocate from the FrameInfo
Chris Lattneraa09b752002-12-28 21:08:28 +0000[diff] [blame]697 unsigned NumBytes = MFI->getStackSize();
Evan Chengd9245ca2006-04-14 07:26:43 +0000[diff] [blame]698 if (MFI->hasCalls() || MF.getFrameInfo()->hasVarSizedObjects()) {
699 // When we have no frame pointer, we reserve argument space for call sites
700 // in the function immediately on entry to the current function. This
701 // eliminates the need for add/sub ESP brackets around call sites.
702 //
703 if (!hasFP(MF))
704 NumBytes += MFI->getMaxCallFrameSize();
705
706 // Round the size to a multiple of the alignment (don't forget the 4 byte
707 // offset though).
708 unsigned Align = MF.getTarget().getFrameInfo()->getStackAlignment();
709 NumBytes = ((NumBytes+4)+Align-1)/Align*Align - 4;
710 }
711
712 // Update frame info to pretend that this is part of the stack...
713 MFI->setStackSize(NumBytes);
714
715 if (NumBytes) { // adjust stack pointer: ESP -= numbytes
716 unsigned Opc = NumBytes < 128 ? X86::SUB32ri8 : X86::SUB32ri;
717 MI = BuildMI(Opc, 1, X86::ESP,MachineOperand::UseAndDef).addImm(NumBytes);
718 MBB.insert(MBBI, MI);
719 }
720
Chris Lattner3c1c03d2002-12-28 20:32:28 +0000[diff] [blame]721 if (hasFP(MF)) {
722 // Get the offset of the stack slot for the EBP register... which is
723 // guaranteed to be the last slot by processFunctionBeforeFrameFinalized.
Chris Lattner96c3d2e2004-02-15 00:15:37 +0000[diff] [blame]724 int EBPOffset = MFI->getObjectOffset(MFI->getObjectIndexBegin())+4;
Chris Lattner3bbe7cc2002-12-17 03:15:26 +0000[diff] [blame]725
Chris Lattnerc2b81f62003-10-14 19:09:05 +0000[diff] [blame]726 // Save EBP into the appropriate stack slot...
Alkis Evlogimenos8295f202004-02-29 08:50:03 +0000[diff] [blame]727 MI = addRegOffset(BuildMI(X86::MOV32mr, 5), // mov [ESP-<offset>], EBP
Jeff Cohen00b168892005-07-27 06:12:32 +0000[diff] [blame]728 X86::ESP, EBPOffset+NumBytes).addReg(X86::EBP);
Alkis Evlogimenosc0b9dc52004-02-12 02:27:10 +0000[diff] [blame]729 MBB.insert(MBBI, MI);
Chris Lattnerc2b81f62003-10-14 19:09:05 +0000[diff] [blame]730
731 // Update EBP with the new base value...
Chris Lattner96c3d2e2004-02-15 00:15:37 +0000[diff] [blame]732 if (NumBytes == 4) // mov EBP, ESP
Alkis Evlogimenos8295f202004-02-29 08:50:03 +0000[diff] [blame]733 MI = BuildMI(X86::MOV32rr, 2, X86::EBP).addReg(X86::ESP);
Chris Lattnerc2b81f62003-10-14 19:09:05 +0000[diff] [blame]734 else // lea EBP, [ESP+StackSize]
Alkis Evlogimenos8295f202004-02-29 08:50:03 +0000[diff] [blame]735 MI = addRegOffset(BuildMI(X86::LEA32r, 5, X86::EBP), X86::ESP,NumBytes-4);
Chris Lattnerc2b81f62003-10-14 19:09:05 +0000[diff] [blame]736
Alkis Evlogimenosc0b9dc52004-02-12 02:27:10 +0000[diff] [blame]737 MBB.insert(MBBI, MI);
Chris Lattner3c1c03d2002-12-28 20:32:28 +0000[diff] [blame]738 }
Misha Brukman2adb3952002-12-04 23:57:03 +0000[diff] [blame]739}
740
Chris Lattnerbb07ef92004-02-14 19:49:54 +0000[diff] [blame]741void X86RegisterInfo::emitEpilogue(MachineFunction &MF,
742 MachineBasicBlock &MBB) const {
Chris Lattneraa09b752002-12-28 21:08:28 +0000[diff] [blame]743 const MachineFrameInfo *MFI = MF.getFrameInfo();
Alkis Evlogimenosf81af212004-02-14 01:18:34 +0000[diff] [blame]744 MachineBasicBlock::iterator MBBI = prior(MBB.end());
Chris Lattner2b3d56e2005-05-14 23:35:21 +0000[diff] [blame]745
746 switch (MBBI->getOpcode()) {
747 case X86::RET:
748 case X86::RETI:
749 case X86::TAILJMPd:
750 case X86::TAILJMPr:
751 case X86::TAILJMPm: break; // These are ok
752 default:
753 assert(0 && "Can only insert epilog into returning blocks");
754 }
Misha Brukman2adb3952002-12-04 23:57:03 +0000[diff] [blame]755
Chris Lattner3c1c03d2002-12-28 20:32:28 +0000[diff] [blame]756 if (hasFP(MF)) {
757 // Get the offset of the stack slot for the EBP register... which is
758 // guaranteed to be the last slot by processFunctionBeforeFrameFinalized.
Chris Lattnereafa4232003-01-15 22:57:35 +0000[diff] [blame]759 int EBPOffset = MFI->getObjectOffset(MFI->getObjectIndexEnd()-1)+4;
Alkis Evlogimenos39354c92004-03-14 07:19:51 +0000[diff] [blame]760
Chris Lattner3c1c03d2002-12-28 20:32:28 +0000[diff] [blame]761 // mov ESP, EBP
Chris Lattner69721772005-05-14 23:53:43 +0000[diff] [blame]762 BuildMI(MBB, MBBI, X86::MOV32rr, 1,X86::ESP).addReg(X86::EBP);
Chris Lattner3c1c03d2002-12-28 20:32:28 +0000[diff] [blame]763
Chris Lattner96c3d2e2004-02-15 00:15:37 +0000[diff] [blame]764 // pop EBP
Chris Lattner69721772005-05-14 23:53:43 +0000[diff] [blame]765 BuildMI(MBB, MBBI, X86::POP32r, 0, X86::EBP);
Chris Lattner3c1c03d2002-12-28 20:32:28 +0000[diff] [blame]766 } else {
Chris Lattner3c1c03d2002-12-28 20:32:28 +0000[diff] [blame]767 // Get the number of bytes allocated from the FrameInfo...
Chris Lattneraa09b752002-12-28 21:08:28 +0000[diff] [blame]768 unsigned NumBytes = MFI->getStackSize();
Chris Lattner3c1c03d2002-12-28 20:32:28 +0000[diff] [blame]769
770 if (NumBytes) { // adjust stack pointer back: ESP += numbytes
Chris Lattner69721772005-05-14 23:53:43 +0000[diff] [blame]771 // If there is an ADD32ri or SUB32ri of ESP immediately before this
772 // instruction, merge the two instructions.
773 if (MBBI != MBB.begin()) {
774 MachineBasicBlock::iterator PI = prior(MBBI);
Chris Lattnerd77525d2006-02-03 18:20:04 +0000[diff] [blame]775 if ((PI->getOpcode() == X86::ADD32ri ||
776 PI->getOpcode() == X86::ADD32ri8) &&
Chris Lattner69721772005-05-14 23:53:43 +0000[diff] [blame]777 PI->getOperand(0).getReg() == X86::ESP) {
778 NumBytes += PI->getOperand(1).getImmedValue();
779 MBB.erase(PI);
Chris Lattnerd77525d2006-02-03 18:20:04 +0000[diff] [blame]780 } else if ((PI->getOpcode() == X86::SUB32ri ||
781 PI->getOpcode() == X86::SUB32ri8) &&
Chris Lattner69721772005-05-14 23:53:43 +0000[diff] [blame]782 PI->getOperand(0).getReg() == X86::ESP) {
783 NumBytes -= PI->getOperand(1).getImmedValue();
784 MBB.erase(PI);
Chris Lattner5fae9cc2005-05-15 05:49:58 +0000[diff] [blame]785 } else if (PI->getOpcode() == X86::ADJSTACKPTRri) {
786 NumBytes += PI->getOperand(1).getImmedValue();
787 MBB.erase(PI);
Chris Lattner69721772005-05-14 23:53:43 +0000[diff] [blame]788 }
789 }
790
Chris Lattnerd77525d2006-02-03 18:20:04 +0000[diff] [blame]791 if (NumBytes > 0) {
792 unsigned Opc = NumBytes < 128 ? X86::ADD32ri8 : X86::ADD32ri;
793 BuildMI(MBB, MBBI, Opc, 2)
Chris Lattner69721772005-05-14 23:53:43 +0000[diff] [blame]794 .addReg(X86::ESP, MachineOperand::UseAndDef).addZImm(NumBytes);
Chris Lattnerd77525d2006-02-03 18:20:04 +0000[diff] [blame]795 } else if ((int)NumBytes < 0) {
796 unsigned Opc = -NumBytes < 128 ? X86::SUB32ri8 : X86::SUB32ri;
797 BuildMI(MBB, MBBI, Opc, 2)
Chris Lattner69721772005-05-14 23:53:43 +0000[diff] [blame]798 .addReg(X86::ESP, MachineOperand::UseAndDef).addZImm(-NumBytes);
Chris Lattnerd77525d2006-02-03 18:20:04 +0000[diff] [blame]799 }
Chris Lattner3c1c03d2002-12-28 20:32:28 +0000[diff] [blame]800 }
801 }
802}
803
Jim Laskey41886992006-04-07 16:34:46 +0000[diff] [blame]804unsigned X86RegisterInfo::getRARegister() const {
805 return X86::ST0; // use a non-register register
806}
807
Jim Laskeya9979182006-03-28 13:48:33 +0000[diff] [blame]808unsigned X86RegisterInfo::getFrameRegister(MachineFunction &MF) const {
Jim Laskey41886992006-04-07 16:34:46 +0000[diff] [blame]809 return hasFP(MF) ? X86::EBP : X86::ESP;
Jim Laskeyf1d78e82006-03-23 18:12:57 +0000[diff] [blame]810}
811
Chris Lattner7ad3e062003-08-03 15:48:14 +0000[diff] [blame]812#include "X86GenRegisterInfo.inc"
Chris Lattner3c1c03d2002-12-28 20:32:28 +0000[diff] [blame]813