Tim Rowley | 2b2d368 | 2016-02-16 17:27:28 -0600 | [diff] [blame] | 1 | /**************************************************************************** |
| 2 | * Copyright (C) 2015 Intel Corporation. All Rights Reserved. |
| 3 | * |
| 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 5 | * copy of this software and associated documentation files (the "Software"), |
| 6 | * to deal in the Software without restriction, including without limitation |
| 7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| 8 | * and/or sell copies of the Software, and to permit persons to whom the |
| 9 | * Software is furnished to do so, subject to the following conditions: |
| 10 | * |
| 11 | * The above copyright notice and this permission notice (including the next |
| 12 | * paragraph) shall be included in all copies or substantial portions of the |
| 13 | * Software. |
| 14 | * |
| 15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
| 19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING |
| 20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS |
| 21 | * IN THE SOFTWARE. |
| 22 | ***************************************************************************/ |
| 23 | |
George Kyriazis | 974d280 | 2016-11-11 11:44:05 -0600 | [diff] [blame] | 24 | #include "swr_context.h" |
| 25 | #include "swr_public.h" |
| 26 | #include "swr_screen.h" |
| 27 | #include "swr_resource.h" |
| 28 | #include "swr_fence.h" |
| 29 | #include "gen_knobs.h" |
| 30 | |
Tim Rowley | 2b2d368 | 2016-02-16 17:27:28 -0600 | [diff] [blame] | 31 | #include "pipe/p_screen.h" |
| 32 | #include "pipe/p_defines.h" |
| 33 | #include "util/u_memory.h" |
| 34 | #include "util/u_format.h" |
| 35 | #include "util/u_inlines.h" |
| 36 | #include "util/u_cpu_detect.h" |
Tim Rowley | 2785f2f | 2016-05-12 11:27:57 -0500 | [diff] [blame] | 37 | #include "util/u_format_s3tc.h" |
Tim Rowley | efc3ca6 | 2016-12-05 11:32:19 -0600 | [diff] [blame] | 38 | #include "util/u_string.h" |
Tim Rowley | 2b2d368 | 2016-02-16 17:27:28 -0600 | [diff] [blame] | 39 | |
| 40 | #include "state_tracker/sw_winsys.h" |
| 41 | |
Tim Rowley | 2b2d368 | 2016-02-16 17:27:28 -0600 | [diff] [blame] | 42 | #include "jit_api.h" |
| 43 | |
Ilia Mirkin | 7cfb364 | 2016-11-09 17:16:36 -0500 | [diff] [blame] | 44 | #include "memory/TilingFunctions.h" |
| 45 | |
Tim Rowley | 2b2d368 | 2016-02-16 17:27:28 -0600 | [diff] [blame] | 46 | #include <stdio.h> |
Tim Rowley | 50842e8 | 2016-09-20 11:15:55 -0500 | [diff] [blame] | 47 | #include <map> |
Tim Rowley | 2b2d368 | 2016-02-16 17:27:28 -0600 | [diff] [blame] | 48 | |
Tim Rowley | 2b2d368 | 2016-02-16 17:27:28 -0600 | [diff] [blame] | 49 | /* |
| 50 | * Max texture sizes |
| 51 | * XXX Check max texture size values against core and sampler. |
| 52 | */ |
Tim Rowley | 7514e32 | 2016-08-17 10:12:04 -0500 | [diff] [blame] | 53 | #define SWR_MAX_TEXTURE_SIZE (4 * 1024 * 1024 * 1024ULL) /* 4GB */ |
Tim Rowley | 2b2d368 | 2016-02-16 17:27:28 -0600 | [diff] [blame] | 54 | #define SWR_MAX_TEXTURE_2D_LEVELS 14 /* 8K x 8K for now */ |
| 55 | #define SWR_MAX_TEXTURE_3D_LEVELS 12 /* 2K x 2K x 2K for now */ |
| 56 | #define SWR_MAX_TEXTURE_CUBE_LEVELS 14 /* 8K x 8K for now */ |
| 57 | #define SWR_MAX_TEXTURE_ARRAY_LAYERS 512 /* 8K x 512 / 8K x 8K x 512 */ |
| 58 | |
Bruce Cherniak | 02735e6 | 2017-07-12 15:04:47 -0500 | [diff] [blame] | 59 | /* Default max client_copy_limit */ |
| 60 | #define SWR_CLIENT_COPY_LIMIT 32768 |
| 61 | |
Bruce Cherniak | 1832ef6 | 2017-04-13 17:40:11 -0500 | [diff] [blame] | 62 | /* Flag indicates creation of alternate surface, to prevent recursive loop |
| 63 | * in resource creation when msaa_force_enable is set. */ |
| 64 | #define SWR_RESOURCE_FLAG_ALT_SURFACE (PIPE_RESOURCE_FLAG_DRV_PRIV << 0) |
| 65 | |
| 66 | |
Tim Rowley | 2b2d368 | 2016-02-16 17:27:28 -0600 | [diff] [blame] | 67 | static const char * |
| 68 | swr_get_name(struct pipe_screen *screen) |
| 69 | { |
Tim Rowley | efc3ca6 | 2016-12-05 11:32:19 -0600 | [diff] [blame] | 70 | static char buf[100]; |
| 71 | util_snprintf(buf, sizeof(buf), "SWR (LLVM %u.%u, %u bits)", |
| 72 | HAVE_LLVM >> 8, HAVE_LLVM & 0xff, |
| 73 | lp_native_vector_width ); |
| 74 | return buf; |
Tim Rowley | 2b2d368 | 2016-02-16 17:27:28 -0600 | [diff] [blame] | 75 | } |
| 76 | |
| 77 | static const char * |
| 78 | swr_get_vendor(struct pipe_screen *screen) |
| 79 | { |
| 80 | return "Intel Corporation"; |
| 81 | } |
| 82 | |
| 83 | static boolean |
Bruce Cherniak | 1832ef6 | 2017-04-13 17:40:11 -0500 | [diff] [blame] | 84 | swr_is_format_supported(struct pipe_screen *_screen, |
Tim Rowley | 2b2d368 | 2016-02-16 17:27:28 -0600 | [diff] [blame] | 85 | enum pipe_format format, |
| 86 | enum pipe_texture_target target, |
| 87 | unsigned sample_count, |
| 88 | unsigned bind) |
| 89 | { |
Bruce Cherniak | 1832ef6 | 2017-04-13 17:40:11 -0500 | [diff] [blame] | 90 | struct swr_screen *screen = swr_screen(_screen); |
| 91 | struct sw_winsys *winsys = screen->winsys; |
Tim Rowley | 2b2d368 | 2016-02-16 17:27:28 -0600 | [diff] [blame] | 92 | const struct util_format_description *format_desc; |
| 93 | |
| 94 | assert(target == PIPE_BUFFER || target == PIPE_TEXTURE_1D |
| 95 | || target == PIPE_TEXTURE_1D_ARRAY |
| 96 | || target == PIPE_TEXTURE_2D |
| 97 | || target == PIPE_TEXTURE_2D_ARRAY |
| 98 | || target == PIPE_TEXTURE_RECT |
| 99 | || target == PIPE_TEXTURE_3D |
| 100 | || target == PIPE_TEXTURE_CUBE |
| 101 | || target == PIPE_TEXTURE_CUBE_ARRAY); |
| 102 | |
| 103 | format_desc = util_format_description(format); |
| 104 | if (!format_desc) |
| 105 | return FALSE; |
| 106 | |
Bruce Cherniak | 1832ef6 | 2017-04-13 17:40:11 -0500 | [diff] [blame] | 107 | if ((sample_count > screen->msaa_max_count) |
| 108 | || !util_is_power_of_two(sample_count)) |
Tim Rowley | 2b2d368 | 2016-02-16 17:27:28 -0600 | [diff] [blame] | 109 | return FALSE; |
| 110 | |
Bruce Cherniak | 91a7f0b | 2017-04-12 18:53:01 -0500 | [diff] [blame] | 111 | if (bind & PIPE_BIND_DISPLAY_TARGET) { |
Tim Rowley | 2b2d368 | 2016-02-16 17:27:28 -0600 | [diff] [blame] | 112 | if (!winsys->is_displaytarget_format_supported(winsys, bind, format)) |
| 113 | return FALSE; |
| 114 | } |
| 115 | |
| 116 | if (bind & PIPE_BIND_RENDER_TARGET) { |
| 117 | if (format_desc->colorspace == UTIL_FORMAT_COLORSPACE_ZS) |
| 118 | return FALSE; |
| 119 | |
| 120 | if (mesa_to_swr_format(format) == (SWR_FORMAT)-1) |
| 121 | return FALSE; |
| 122 | |
| 123 | /* |
| 124 | * Although possible, it is unnatural to render into compressed or YUV |
| 125 | * surfaces. So disable these here to avoid going into weird paths |
| 126 | * inside the state trackers. |
| 127 | */ |
| 128 | if (format_desc->block.width != 1 || format_desc->block.height != 1) |
| 129 | return FALSE; |
| 130 | } |
| 131 | |
| 132 | if (bind & PIPE_BIND_DEPTH_STENCIL) { |
| 133 | if (format_desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS) |
| 134 | return FALSE; |
| 135 | |
| 136 | if (mesa_to_swr_format(format) == (SWR_FORMAT)-1) |
| 137 | return FALSE; |
| 138 | } |
| 139 | |
Tim Rowley | 2785f2f | 2016-05-12 11:27:57 -0500 | [diff] [blame] | 140 | if (format_desc->layout == UTIL_FORMAT_LAYOUT_BPTC || |
| 141 | format_desc->layout == UTIL_FORMAT_LAYOUT_ASTC) { |
| 142 | return FALSE; |
| 143 | } |
| 144 | |
| 145 | if (format_desc->layout == UTIL_FORMAT_LAYOUT_ETC && |
| 146 | format != PIPE_FORMAT_ETC1_RGB8) { |
| 147 | return FALSE; |
| 148 | } |
| 149 | |
| 150 | if (format_desc->layout == UTIL_FORMAT_LAYOUT_S3TC) { |
| 151 | return util_format_s3tc_enabled; |
| 152 | } |
| 153 | |
Tim Rowley | 2b2d368 | 2016-02-16 17:27:28 -0600 | [diff] [blame] | 154 | return TRUE; |
| 155 | } |
| 156 | |
| 157 | static int |
| 158 | swr_get_param(struct pipe_screen *screen, enum pipe_cap param) |
| 159 | { |
| 160 | switch (param) { |
Ilia Mirkin | 8dd98535 | 2016-11-20 13:31:43 -0500 | [diff] [blame] | 161 | /* limits */ |
Tim Rowley | 2b2d368 | 2016-02-16 17:27:28 -0600 | [diff] [blame] | 162 | case PIPE_CAP_MAX_RENDER_TARGETS: |
| 163 | return PIPE_MAX_COLOR_BUFS; |
Tim Rowley | 2b2d368 | 2016-02-16 17:27:28 -0600 | [diff] [blame] | 164 | case PIPE_CAP_MAX_TEXTURE_2D_LEVELS: |
| 165 | return SWR_MAX_TEXTURE_2D_LEVELS; |
| 166 | case PIPE_CAP_MAX_TEXTURE_3D_LEVELS: |
| 167 | return SWR_MAX_TEXTURE_3D_LEVELS; |
| 168 | case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS: |
| 169 | return SWR_MAX_TEXTURE_CUBE_LEVELS; |
Tim Rowley | 2b2d368 | 2016-02-16 17:27:28 -0600 | [diff] [blame] | 170 | case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS: |
| 171 | return MAX_SO_STREAMS; |
| 172 | case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS: |
| 173 | case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS: |
Ilia Mirkin | 02b2efa | 2016-11-27 00:45:17 -0500 | [diff] [blame] | 174 | return MAX_ATTRIBUTES * 4; |
Tim Rowley | 2b2d368 | 2016-02-16 17:27:28 -0600 | [diff] [blame] | 175 | case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES: |
| 176 | case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS: |
| 177 | return 1024; |
| 178 | case PIPE_CAP_MAX_VERTEX_STREAMS: |
| 179 | return 1; |
| 180 | case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE: |
| 181 | return 2048; |
Tim Rowley | 2b2d368 | 2016-02-16 17:27:28 -0600 | [diff] [blame] | 182 | case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS: |
| 183 | return SWR_MAX_TEXTURE_ARRAY_LAYERS; |
| 184 | case PIPE_CAP_MIN_TEXEL_OFFSET: |
| 185 | return -8; |
| 186 | case PIPE_CAP_MAX_TEXEL_OFFSET: |
| 187 | return 7; |
Tim Rowley | 2b2d368 | 2016-02-16 17:27:28 -0600 | [diff] [blame] | 188 | case PIPE_CAP_GLSL_FEATURE_LEVEL: |
| 189 | return 330; |
Ilia Mirkin | 8dd98535 | 2016-11-20 13:31:43 -0500 | [diff] [blame] | 190 | case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT: |
| 191 | return 16; |
| 192 | case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT: |
| 193 | return 64; |
| 194 | case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE: |
| 195 | return 65536; |
| 196 | case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT: |
Tim Rowley | 2b2d368 | 2016-02-16 17:27:28 -0600 | [diff] [blame] | 197 | return 0; |
Ilia Mirkin | 8dd98535 | 2016-11-20 13:31:43 -0500 | [diff] [blame] | 198 | case PIPE_CAP_MAX_VIEWPORTS: |
| 199 | return 1; |
| 200 | case PIPE_CAP_ENDIANNESS: |
| 201 | return PIPE_ENDIAN_NATIVE; |
| 202 | case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET: |
| 203 | case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET: |
| 204 | return 0; |
| 205 | |
| 206 | /* supported features */ |
| 207 | case PIPE_CAP_NPOT_TEXTURES: |
| 208 | case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES: |
| 209 | case PIPE_CAP_MIXED_COLOR_DEPTH_BITS: |
| 210 | case PIPE_CAP_TWO_SIDED_STENCIL: |
| 211 | case PIPE_CAP_SM3: |
| 212 | case PIPE_CAP_POINT_SPRITE: |
| 213 | case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS: |
| 214 | case PIPE_CAP_OCCLUSION_QUERY: |
| 215 | case PIPE_CAP_QUERY_TIME_ELAPSED: |
| 216 | case PIPE_CAP_QUERY_PIPELINE_STATISTICS: |
| 217 | case PIPE_CAP_TEXTURE_MIRROR_CLAMP: |
| 218 | case PIPE_CAP_TEXTURE_SHADOW_MAP: |
| 219 | case PIPE_CAP_TEXTURE_SWIZZLE: |
| 220 | case PIPE_CAP_BLEND_EQUATION_SEPARATE: |
| 221 | case PIPE_CAP_INDEP_BLEND_ENABLE: |
| 222 | case PIPE_CAP_INDEP_BLEND_FUNC: |
| 223 | case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT: |
| 224 | case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER: |
| 225 | case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER: |
| 226 | case PIPE_CAP_DEPTH_CLIP_DISABLE: |
| 227 | case PIPE_CAP_PRIMITIVE_RESTART: |
| 228 | case PIPE_CAP_TGSI_INSTANCEID: |
| 229 | case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR: |
| 230 | case PIPE_CAP_START_INSTANCE: |
| 231 | case PIPE_CAP_SEAMLESS_CUBE_MAP: |
| 232 | case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE: |
| 233 | case PIPE_CAP_CONDITIONAL_RENDER: |
| 234 | case PIPE_CAP_VERTEX_COLOR_UNCLAMPED: |
| 235 | case PIPE_CAP_MIXED_COLORBUFFER_FORMATS: |
| 236 | case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION: |
Tim Rowley | 2b2d368 | 2016-02-16 17:27:28 -0600 | [diff] [blame] | 237 | case PIPE_CAP_USER_VERTEX_BUFFERS: |
Tim Rowley | 2b2d368 | 2016-02-16 17:27:28 -0600 | [diff] [blame] | 238 | case PIPE_CAP_USER_CONSTANT_BUFFERS: |
Ilia Mirkin | 3fdeb7c | 2016-10-14 00:03:12 -0400 | [diff] [blame] | 239 | case PIPE_CAP_STREAM_OUTPUT_INTERLEAVE_BUFFERS: |
Ilia Mirkin | 8dd98535 | 2016-11-20 13:31:43 -0500 | [diff] [blame] | 240 | case PIPE_CAP_QUERY_TIMESTAMP: |
| 241 | case PIPE_CAP_TEXTURE_BUFFER_OBJECTS: |
| 242 | case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT: |
Ilia Mirkin | 8dd98535 | 2016-11-20 13:31:43 -0500 | [diff] [blame] | 243 | case PIPE_CAP_DRAW_INDIRECT: |
| 244 | case PIPE_CAP_UMA: |
| 245 | case PIPE_CAP_CONDITIONAL_RENDER_INVERTED: |
| 246 | case PIPE_CAP_CLIP_HALFZ: |
| 247 | case PIPE_CAP_POLYGON_OFFSET_CLAMP: |
| 248 | case PIPE_CAP_DEPTH_BOUNDS_TEST: |
Bruce Cherniak | dd649a5 | 2017-02-25 21:09:57 -0600 | [diff] [blame] | 249 | case PIPE_CAP_CLEAR_TEXTURE: |
Ilia Mirkin | 8dd98535 | 2016-11-20 13:31:43 -0500 | [diff] [blame] | 250 | case PIPE_CAP_TEXTURE_FLOAT_LINEAR: |
| 251 | case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR: |
| 252 | case PIPE_CAP_CULL_DISTANCE: |
Ilia Mirkin | 86f7932 | 2016-11-20 13:33:04 -0500 | [diff] [blame] | 253 | case PIPE_CAP_CUBE_MAP_ARRAY: |
Tim Rowley | 9a7b257 | 2017-04-11 11:50:23 -0500 | [diff] [blame] | 254 | case PIPE_CAP_DOUBLES: |
Tim Rowley | 2b2d368 | 2016-02-16 17:27:28 -0600 | [diff] [blame] | 255 | return 1; |
Ilia Mirkin | 8dd98535 | 2016-11-20 13:31:43 -0500 | [diff] [blame] | 256 | |
Bruce Cherniak | 1832ef6 | 2017-04-13 17:40:11 -0500 | [diff] [blame] | 257 | /* MSAA support |
| 258 | * If user has explicitly set max_sample_count = 0 (via SWR_MSAA_MAX_COUNT) |
| 259 | * then disable all MSAA support and go back to old caps. */ |
| 260 | case PIPE_CAP_TEXTURE_MULTISAMPLE: |
| 261 | case PIPE_CAP_MULTISAMPLE_Z_RESOLVE: |
| 262 | return swr_screen(screen)->msaa_max_count ? 1 : 0; |
| 263 | case PIPE_CAP_FAKE_SW_MSAA: |
| 264 | return swr_screen(screen)->msaa_max_count ? 0 : 1; |
| 265 | |
Ilia Mirkin | 8dd98535 | 2016-11-20 13:31:43 -0500 | [diff] [blame] | 266 | /* unsupported features */ |
| 267 | case PIPE_CAP_ANISOTROPIC_FILTER: |
| 268 | case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK: |
| 269 | case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT: |
| 270 | case PIPE_CAP_SHADER_STENCIL_EXPORT: |
| 271 | case PIPE_CAP_TEXTURE_BARRIER: |
| 272 | case PIPE_CAP_FRAGMENT_COLOR_CLAMPED: |
| 273 | case PIPE_CAP_VERTEX_COLOR_CLAMPED: |
| 274 | case PIPE_CAP_COMPUTE: |
Ilia Mirkin | c3dd5b2 | 2016-11-20 13:13:12 -0500 | [diff] [blame] | 275 | case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT: |
Tim Rowley | 2b2d368 | 2016-02-16 17:27:28 -0600 | [diff] [blame] | 276 | case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS: |
| 277 | case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY: |
| 278 | case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY: |
| 279 | case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY: |
Tim Rowley | 2b2d368 | 2016-02-16 17:27:28 -0600 | [diff] [blame] | 280 | case PIPE_CAP_TGSI_TEXCOORD: |
| 281 | case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER: |
Tim Rowley | 2b2d368 | 2016-02-16 17:27:28 -0600 | [diff] [blame] | 282 | case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS: |
| 283 | case PIPE_CAP_TEXTURE_GATHER_SM5: |
Tim Rowley | 2b2d368 | 2016-02-16 17:27:28 -0600 | [diff] [blame] | 284 | case PIPE_CAP_TEXTURE_QUERY_LOD: |
| 285 | case PIPE_CAP_SAMPLE_SHADING: |
| 286 | case PIPE_CAP_TEXTURE_GATHER_OFFSETS: |
| 287 | case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION: |
| 288 | case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE: |
| 289 | case PIPE_CAP_SAMPLER_VIEW_TARGET: |
Tim Rowley | 2b2d368 | 2016-02-16 17:27:28 -0600 | [diff] [blame] | 290 | case PIPE_CAP_VERTEXID_NOBASE: |
Tim Rowley | 2b2d368 | 2016-02-16 17:27:28 -0600 | [diff] [blame] | 291 | case PIPE_CAP_RESOURCE_FROM_USER_MEMORY: |
Tim Rowley | 2b2d368 | 2016-02-16 17:27:28 -0600 | [diff] [blame] | 292 | case PIPE_CAP_DEVICE_RESET_STATUS_QUERY: |
Tim Rowley | 2b2d368 | 2016-02-16 17:27:28 -0600 | [diff] [blame] | 293 | case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS: |
Tim Rowley | 2b2d368 | 2016-02-16 17:27:28 -0600 | [diff] [blame] | 294 | case PIPE_CAP_TGSI_TXQS: |
| 295 | case PIPE_CAP_FORCE_PERSAMPLE_INTERP: |
| 296 | case PIPE_CAP_SHAREABLE_SHADERS: |
| 297 | case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS: |
Tim Rowley | 2b2d368 | 2016-02-16 17:27:28 -0600 | [diff] [blame] | 298 | case PIPE_CAP_DRAW_PARAMETERS: |
| 299 | case PIPE_CAP_TGSI_PACK_HALF_FLOAT: |
| 300 | case PIPE_CAP_MULTI_DRAW_INDIRECT: |
| 301 | case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS: |
| 302 | case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL: |
| 303 | case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL: |
| 304 | case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT: |
| 305 | case PIPE_CAP_INVALIDATE_BUFFER: |
| 306 | case PIPE_CAP_GENERATE_MIPMAP: |
| 307 | case PIPE_CAP_STRING_MARKER: |
| 308 | case PIPE_CAP_BUFFER_SAMPLER_VIEW_RGBA_ONLY: |
| 309 | case PIPE_CAP_SURFACE_REINTERPRET_BLOCKS: |
| 310 | case PIPE_CAP_QUERY_BUFFER_OBJECT: |
| 311 | case PIPE_CAP_QUERY_MEMORY_INFO: |
Bas Nieuwenhuizen | 70dcd84 | 2016-04-12 15:00:31 +0200 | [diff] [blame] | 312 | case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR: |
Tim Rowley | b9294bc | 2016-04-01 19:58:29 -0500 | [diff] [blame] | 313 | case PIPE_CAP_PCI_GROUP: |
| 314 | case PIPE_CAP_PCI_BUS: |
| 315 | case PIPE_CAP_PCI_DEVICE: |
| 316 | case PIPE_CAP_PCI_FUNCTION: |
Tim Rowley | 81c1c48 | 2016-04-21 11:10:29 -0500 | [diff] [blame] | 317 | case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT: |
Kenneth Graunke | 70048eb | 2016-05-20 21:05:34 -0700 | [diff] [blame] | 318 | case PIPE_CAP_PRIMITIVE_RESTART_FOR_PATCHES: |
Ilia Mirkin | edfa7a4 | 2016-05-29 11:39:52 -0400 | [diff] [blame] | 319 | case PIPE_CAP_TGSI_VOTE: |
Ilia Mirkin | 07fcb06 | 2016-06-11 15:26:45 -0400 | [diff] [blame] | 320 | case PIPE_CAP_MAX_WINDOW_RECTANGLES: |
Axel Davy | 59a6929 | 2016-06-13 22:28:32 +0200 | [diff] [blame] | 321 | case PIPE_CAP_POLYGON_OFFSET_UNITS_UNSCALED: |
Józef Kucia | 3cd28fe | 2016-07-19 13:07:24 +0200 | [diff] [blame] | 322 | case PIPE_CAP_VIEWPORT_SUBPIXEL_BITS: |
Nicolai Hähnle | 700a571 | 2016-10-07 09:42:55 +0200 | [diff] [blame] | 323 | case PIPE_CAP_TGSI_ARRAY_COMPONENTS: |
Nicolai Hähnle | 611166b | 2016-11-18 20:49:54 +0100 | [diff] [blame] | 324 | case PIPE_CAP_TGSI_CAN_READ_OUTPUTS: |
Ilia Mirkin | d8ce8ac | 2016-11-26 17:35:31 -0500 | [diff] [blame] | 325 | case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME: |
Tim Rowley | 0c70b26 | 2016-12-05 11:35:57 -0600 | [diff] [blame] | 326 | case PIPE_CAP_NATIVE_FENCE_FD: |
Marek Olšák | e51baeb | 2016-12-31 13:34:11 +0100 | [diff] [blame] | 327 | case PIPE_CAP_GLSL_OPTIMIZE_CONSERVATIVELY: |
Ilia Mirkin | ee3ebe6 | 2017-01-01 23:10:00 -0500 | [diff] [blame] | 328 | case PIPE_CAP_TGSI_FS_FBFETCH: |
Ilia Mirkin | 6e40938 | 2017-01-16 22:14:38 -0500 | [diff] [blame] | 329 | case PIPE_CAP_TGSI_MUL_ZERO_WINS: |
Dave Airlie | f804506 | 2016-06-09 10:13:03 +1000 | [diff] [blame] | 330 | case PIPE_CAP_INT64: |
Ilia Mirkin | b090033 | 2017-02-04 22:31:29 -0500 | [diff] [blame] | 331 | case PIPE_CAP_INT64_DIVMOD: |
Marek Olšák | bf3cdf0 | 2017-03-07 02:09:03 +0100 | [diff] [blame] | 332 | case PIPE_CAP_TGSI_TEX_TXF_LZ: |
Nicolai Hähnle | d0c7f92 | 2017-03-29 20:44:57 +0200 | [diff] [blame] | 333 | case PIPE_CAP_TGSI_CLOCK: |
Lyude | ffe2bd6 | 2017-03-16 18:00:05 -0400 | [diff] [blame] | 334 | case PIPE_CAP_POLYGON_MODE_FILL_RECTANGLE: |
Nicolai Hähnle | d6e6fa0 | 2017-02-02 21:10:44 +0100 | [diff] [blame] | 335 | case PIPE_CAP_SPARSE_BUFFER_PAGE_SIZE: |
Nicolai Hähnle | d3e6f6d | 2017-03-30 11:16:09 +0200 | [diff] [blame] | 336 | case PIPE_CAP_TGSI_BALLOT: |
Nicolai Hähnle | 17f24a9 | 2017-04-13 21:54:54 +0200 | [diff] [blame] | 337 | case PIPE_CAP_TGSI_TES_LAYER_VIEWPORT: |
Marek Olšák | 70dcb73 | 2017-04-30 01:18:43 +0200 | [diff] [blame] | 338 | case PIPE_CAP_CAN_BIND_CONST_BUFFER_AS_VERTEX: |
Marek Olšák | 5018937 | 2017-05-15 16:30:30 +0200 | [diff] [blame] | 339 | case PIPE_CAP_ALLOW_MAPPED_BUFFERS_DURING_EXECUTION: |
Lyude | 467af44 | 2017-05-24 15:42:39 -0400 | [diff] [blame] | 340 | case PIPE_CAP_POST_DEPTH_COVERAGE: |
Samuel Pitoiset | 973822b | 2017-02-16 13:43:16 +0100 | [diff] [blame] | 341 | case PIPE_CAP_BINDLESS_TEXTURE: |
Nicolai Hähnle | 01f1598 | 2017-06-25 18:31:11 +0200 | [diff] [blame] | 342 | case PIPE_CAP_NIR_SAMPLERS_AS_DEREF: |
Nicolai Hähnle | a677799 | 2017-07-26 19:16:14 +0200 | [diff] [blame] | 343 | case PIPE_CAP_QUERY_SO_OVERFLOW: |
Timothy Arceri | 4e4042d | 2017-08-03 13:54:45 +1000 | [diff] [blame^] | 344 | case PIPE_CAP_MEMOBJ: |
Tim Rowley | 2b2d368 | 2016-02-16 17:27:28 -0600 | [diff] [blame] | 345 | return 0; |
Ilia Mirkin | 8dd98535 | 2016-11-20 13:31:43 -0500 | [diff] [blame] | 346 | |
| 347 | case PIPE_CAP_VENDOR_ID: |
| 348 | return 0xFFFFFFFF; |
| 349 | case PIPE_CAP_DEVICE_ID: |
| 350 | return 0xFFFFFFFF; |
| 351 | case PIPE_CAP_ACCELERATED: |
| 352 | return 0; |
| 353 | case PIPE_CAP_VIDEO_MEMORY: { |
| 354 | /* XXX: Do we want to return the full amount of system memory ? */ |
| 355 | uint64_t system_memory; |
| 356 | |
| 357 | if (!os_get_total_physical_memory(&system_memory)) |
| 358 | return 0; |
| 359 | |
| 360 | return (int)(system_memory >> 20); |
| 361 | } |
Tim Rowley | 2b2d368 | 2016-02-16 17:27:28 -0600 | [diff] [blame] | 362 | } |
| 363 | |
| 364 | /* should only get here on unhandled cases */ |
| 365 | debug_printf("Unexpected PIPE_CAP %d query\n", param); |
| 366 | return 0; |
| 367 | } |
| 368 | |
| 369 | static int |
| 370 | swr_get_shader_param(struct pipe_screen *screen, |
Brian Paul | 637e571 | 2017-03-05 12:13:02 -0700 | [diff] [blame] | 371 | enum pipe_shader_type shader, |
Tim Rowley | 2b2d368 | 2016-02-16 17:27:28 -0600 | [diff] [blame] | 372 | enum pipe_shader_cap param) |
| 373 | { |
Tim Rowley | f1d7284 | 2017-03-02 16:41:02 -0600 | [diff] [blame] | 374 | if (shader == PIPE_SHADER_VERTEX || |
| 375 | shader == PIPE_SHADER_FRAGMENT || |
| 376 | shader == PIPE_SHADER_GEOMETRY) |
Tim Rowley | 2b2d368 | 2016-02-16 17:27:28 -0600 | [diff] [blame] | 377 | return gallivm_get_shader_param(param); |
| 378 | |
Tim Rowley | f1d7284 | 2017-03-02 16:41:02 -0600 | [diff] [blame] | 379 | // Todo: tesselation, compute |
Tim Rowley | 2b2d368 | 2016-02-16 17:27:28 -0600 | [diff] [blame] | 380 | return 0; |
| 381 | } |
| 382 | |
| 383 | |
| 384 | static float |
| 385 | swr_get_paramf(struct pipe_screen *screen, enum pipe_capf param) |
| 386 | { |
| 387 | switch (param) { |
| 388 | case PIPE_CAPF_MAX_LINE_WIDTH: |
| 389 | case PIPE_CAPF_MAX_LINE_WIDTH_AA: |
| 390 | case PIPE_CAPF_MAX_POINT_WIDTH: |
| 391 | return 255.0; /* arbitrary */ |
| 392 | case PIPE_CAPF_MAX_POINT_WIDTH_AA: |
| 393 | return 0.0; |
| 394 | case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY: |
| 395 | return 0.0; |
| 396 | case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS: |
Ilia Mirkin | 2234a43 | 2016-11-19 10:10:47 -0500 | [diff] [blame] | 397 | return 16.0; /* arbitrary */ |
Tim Rowley | 2b2d368 | 2016-02-16 17:27:28 -0600 | [diff] [blame] | 398 | case PIPE_CAPF_GUARD_BAND_LEFT: |
| 399 | case PIPE_CAPF_GUARD_BAND_TOP: |
| 400 | case PIPE_CAPF_GUARD_BAND_RIGHT: |
| 401 | case PIPE_CAPF_GUARD_BAND_BOTTOM: |
| 402 | return 0.0; |
| 403 | } |
| 404 | /* should only get here on unhandled cases */ |
| 405 | debug_printf("Unexpected PIPE_CAPF %d query\n", param); |
| 406 | return 0.0; |
| 407 | } |
| 408 | |
| 409 | SWR_FORMAT |
| 410 | mesa_to_swr_format(enum pipe_format format) |
| 411 | { |
Tim Rowley | 50842e8 | 2016-09-20 11:15:55 -0500 | [diff] [blame] | 412 | static const std::map<pipe_format,SWR_FORMAT> mesa2swr = { |
Ilia Mirkin | d6a06228 | 2016-11-20 17:42:26 -0500 | [diff] [blame] | 413 | /* depth / stencil */ |
Tim Rowley | 50842e8 | 2016-09-20 11:15:55 -0500 | [diff] [blame] | 414 | {PIPE_FORMAT_Z16_UNORM, R16_UNORM}, // z |
Tim Rowley | 50842e8 | 2016-09-20 11:15:55 -0500 | [diff] [blame] | 415 | {PIPE_FORMAT_Z32_FLOAT, R32_FLOAT}, // z |
| 416 | {PIPE_FORMAT_Z24_UNORM_S8_UINT, R24_UNORM_X8_TYPELESS}, // z |
Tim Rowley | 50842e8 | 2016-09-20 11:15:55 -0500 | [diff] [blame] | 417 | {PIPE_FORMAT_Z24X8_UNORM, R24_UNORM_X8_TYPELESS}, // z |
Tim Rowley | 50842e8 | 2016-09-20 11:15:55 -0500 | [diff] [blame] | 418 | {PIPE_FORMAT_Z32_FLOAT_S8X24_UINT, R32_FLOAT_X8X24_TYPELESS}, // z |
Tim Rowley | 50842e8 | 2016-09-20 11:15:55 -0500 | [diff] [blame] | 419 | |
Ilia Mirkin | d6a06228 | 2016-11-20 17:42:26 -0500 | [diff] [blame] | 420 | /* alpha */ |
| 421 | {PIPE_FORMAT_A8_UNORM, A8_UNORM}, |
Tim Rowley | 50842e8 | 2016-09-20 11:15:55 -0500 | [diff] [blame] | 422 | {PIPE_FORMAT_A16_UNORM, A16_UNORM}, |
Tim Rowley | 50842e8 | 2016-09-20 11:15:55 -0500 | [diff] [blame] | 423 | {PIPE_FORMAT_A16_FLOAT, A16_FLOAT}, |
Tim Rowley | 50842e8 | 2016-09-20 11:15:55 -0500 | [diff] [blame] | 424 | {PIPE_FORMAT_A32_FLOAT, A32_FLOAT}, |
Tim Rowley | 50842e8 | 2016-09-20 11:15:55 -0500 | [diff] [blame] | 425 | |
Ilia Mirkin | d6a06228 | 2016-11-20 17:42:26 -0500 | [diff] [blame] | 426 | /* odd sizes, bgr */ |
| 427 | {PIPE_FORMAT_B5G6R5_UNORM, B5G6R5_UNORM}, |
| 428 | {PIPE_FORMAT_B5G6R5_SRGB, B5G6R5_UNORM_SRGB}, |
| 429 | {PIPE_FORMAT_B5G5R5A1_UNORM, B5G5R5A1_UNORM}, |
| 430 | {PIPE_FORMAT_B5G5R5X1_UNORM, B5G5R5X1_UNORM}, |
| 431 | {PIPE_FORMAT_B4G4R4A4_UNORM, B4G4R4A4_UNORM}, |
| 432 | {PIPE_FORMAT_B8G8R8A8_UNORM, B8G8R8A8_UNORM}, |
| 433 | {PIPE_FORMAT_B8G8R8A8_SRGB, B8G8R8A8_UNORM_SRGB}, |
| 434 | {PIPE_FORMAT_B8G8R8X8_UNORM, B8G8R8X8_UNORM}, |
| 435 | {PIPE_FORMAT_B8G8R8X8_SRGB, B8G8R8X8_UNORM_SRGB}, |
Tim Rowley | 50842e8 | 2016-09-20 11:15:55 -0500 | [diff] [blame] | 436 | |
Ilia Mirkin | d6a06228 | 2016-11-20 17:42:26 -0500 | [diff] [blame] | 437 | /* rgb10a2 */ |
| 438 | {PIPE_FORMAT_R10G10B10A2_UNORM, R10G10B10A2_UNORM}, |
| 439 | {PIPE_FORMAT_R10G10B10A2_SNORM, R10G10B10A2_SNORM}, |
| 440 | {PIPE_FORMAT_R10G10B10A2_USCALED, R10G10B10A2_USCALED}, |
| 441 | {PIPE_FORMAT_R10G10B10A2_SSCALED, R10G10B10A2_SSCALED}, |
| 442 | {PIPE_FORMAT_R10G10B10A2_UINT, R10G10B10A2_UINT}, |
| 443 | |
| 444 | /* rgb10x2 */ |
| 445 | {PIPE_FORMAT_R10G10B10X2_USCALED, R10G10B10X2_USCALED}, |
| 446 | |
| 447 | /* bgr10a2 */ |
| 448 | {PIPE_FORMAT_B10G10R10A2_UNORM, B10G10R10A2_UNORM}, |
| 449 | {PIPE_FORMAT_B10G10R10A2_SNORM, B10G10R10A2_SNORM}, |
Tim Rowley | 50842e8 | 2016-09-20 11:15:55 -0500 | [diff] [blame] | 450 | {PIPE_FORMAT_B10G10R10A2_USCALED, B10G10R10A2_USCALED}, |
| 451 | {PIPE_FORMAT_B10G10R10A2_SSCALED, B10G10R10A2_SSCALED}, |
Ilia Mirkin | d6a06228 | 2016-11-20 17:42:26 -0500 | [diff] [blame] | 452 | {PIPE_FORMAT_B10G10R10A2_UINT, B10G10R10A2_UINT}, |
Tim Rowley | 50842e8 | 2016-09-20 11:15:55 -0500 | [diff] [blame] | 453 | |
Ilia Mirkin | d6a06228 | 2016-11-20 17:42:26 -0500 | [diff] [blame] | 454 | /* bgr10x2 */ |
| 455 | {PIPE_FORMAT_B10G10R10X2_UNORM, B10G10R10X2_UNORM}, |
Tim Rowley | 50842e8 | 2016-09-20 11:15:55 -0500 | [diff] [blame] | 456 | |
Ilia Mirkin | d6a06228 | 2016-11-20 17:42:26 -0500 | [diff] [blame] | 457 | /* r11g11b10 */ |
| 458 | {PIPE_FORMAT_R11G11B10_FLOAT, R11G11B10_FLOAT}, |
Tim Rowley | 50842e8 | 2016-09-20 11:15:55 -0500 | [diff] [blame] | 459 | |
Ilia Mirkin | d6a06228 | 2016-11-20 17:42:26 -0500 | [diff] [blame] | 460 | /* 32 bits per component */ |
| 461 | {PIPE_FORMAT_R32_FLOAT, R32_FLOAT}, |
| 462 | {PIPE_FORMAT_R32G32_FLOAT, R32G32_FLOAT}, |
| 463 | {PIPE_FORMAT_R32G32B32_FLOAT, R32G32B32_FLOAT}, |
| 464 | {PIPE_FORMAT_R32G32B32A32_FLOAT, R32G32B32A32_FLOAT}, |
| 465 | {PIPE_FORMAT_R32G32B32X32_FLOAT, R32G32B32X32_FLOAT}, |
Tim Rowley | 50842e8 | 2016-09-20 11:15:55 -0500 | [diff] [blame] | 466 | |
Ilia Mirkin | d6a06228 | 2016-11-20 17:42:26 -0500 | [diff] [blame] | 467 | {PIPE_FORMAT_R32_USCALED, R32_USCALED}, |
| 468 | {PIPE_FORMAT_R32G32_USCALED, R32G32_USCALED}, |
| 469 | {PIPE_FORMAT_R32G32B32_USCALED, R32G32B32_USCALED}, |
| 470 | {PIPE_FORMAT_R32G32B32A32_USCALED, R32G32B32A32_USCALED}, |
| 471 | |
| 472 | {PIPE_FORMAT_R32_SSCALED, R32_SSCALED}, |
| 473 | {PIPE_FORMAT_R32G32_SSCALED, R32G32_SSCALED}, |
| 474 | {PIPE_FORMAT_R32G32B32_SSCALED, R32G32B32_SSCALED}, |
| 475 | {PIPE_FORMAT_R32G32B32A32_SSCALED, R32G32B32A32_SSCALED}, |
Tim Rowley | 50842e8 | 2016-09-20 11:15:55 -0500 | [diff] [blame] | 476 | |
| 477 | {PIPE_FORMAT_R32_UINT, R32_UINT}, |
| 478 | {PIPE_FORMAT_R32G32_UINT, R32G32_UINT}, |
| 479 | {PIPE_FORMAT_R32G32B32_UINT, R32G32B32_UINT}, |
| 480 | {PIPE_FORMAT_R32G32B32A32_UINT, R32G32B32A32_UINT}, |
| 481 | |
| 482 | {PIPE_FORMAT_R32_SINT, R32_SINT}, |
| 483 | {PIPE_FORMAT_R32G32_SINT, R32G32_SINT}, |
| 484 | {PIPE_FORMAT_R32G32B32_SINT, R32G32B32_SINT}, |
| 485 | {PIPE_FORMAT_R32G32B32A32_SINT, R32G32B32A32_SINT}, |
| 486 | |
Ilia Mirkin | d6a06228 | 2016-11-20 17:42:26 -0500 | [diff] [blame] | 487 | /* 16 bits per component */ |
| 488 | {PIPE_FORMAT_R16_UNORM, R16_UNORM}, |
| 489 | {PIPE_FORMAT_R16G16_UNORM, R16G16_UNORM}, |
| 490 | {PIPE_FORMAT_R16G16B16_UNORM, R16G16B16_UNORM}, |
| 491 | {PIPE_FORMAT_R16G16B16A16_UNORM, R16G16B16A16_UNORM}, |
Tim Rowley | 50842e8 | 2016-09-20 11:15:55 -0500 | [diff] [blame] | 492 | {PIPE_FORMAT_R16G16B16X16_UNORM, R16G16B16X16_UNORM}, |
Tim Rowley | 50842e8 | 2016-09-20 11:15:55 -0500 | [diff] [blame] | 493 | |
Ilia Mirkin | d6a06228 | 2016-11-20 17:42:26 -0500 | [diff] [blame] | 494 | {PIPE_FORMAT_R16_USCALED, R16_USCALED}, |
| 495 | {PIPE_FORMAT_R16G16_USCALED, R16G16_USCALED}, |
| 496 | {PIPE_FORMAT_R16G16B16_USCALED, R16G16B16_USCALED}, |
| 497 | {PIPE_FORMAT_R16G16B16A16_USCALED, R16G16B16A16_USCALED}, |
| 498 | |
| 499 | {PIPE_FORMAT_R16_SNORM, R16_SNORM}, |
| 500 | {PIPE_FORMAT_R16G16_SNORM, R16G16_SNORM}, |
| 501 | {PIPE_FORMAT_R16G16B16_SNORM, R16G16B16_SNORM}, |
| 502 | {PIPE_FORMAT_R16G16B16A16_SNORM, R16G16B16A16_SNORM}, |
| 503 | |
| 504 | {PIPE_FORMAT_R16_SSCALED, R16_SSCALED}, |
| 505 | {PIPE_FORMAT_R16G16_SSCALED, R16G16_SSCALED}, |
| 506 | {PIPE_FORMAT_R16G16B16_SSCALED, R16G16B16_SSCALED}, |
| 507 | {PIPE_FORMAT_R16G16B16A16_SSCALED, R16G16B16A16_SSCALED}, |
| 508 | |
| 509 | {PIPE_FORMAT_R16_UINT, R16_UINT}, |
| 510 | {PIPE_FORMAT_R16G16_UINT, R16G16_UINT}, |
| 511 | {PIPE_FORMAT_R16G16B16_UINT, R16G16B16_UINT}, |
| 512 | {PIPE_FORMAT_R16G16B16A16_UINT, R16G16B16A16_UINT}, |
| 513 | |
| 514 | {PIPE_FORMAT_R16_SINT, R16_SINT}, |
| 515 | {PIPE_FORMAT_R16G16_SINT, R16G16_SINT}, |
| 516 | {PIPE_FORMAT_R16G16B16_SINT, R16G16B16_SINT}, |
| 517 | {PIPE_FORMAT_R16G16B16A16_SINT, R16G16B16A16_SINT}, |
| 518 | |
| 519 | {PIPE_FORMAT_R16_FLOAT, R16_FLOAT}, |
| 520 | {PIPE_FORMAT_R16G16_FLOAT, R16G16_FLOAT}, |
| 521 | {PIPE_FORMAT_R16G16B16_FLOAT, R16G16B16_FLOAT}, |
| 522 | {PIPE_FORMAT_R16G16B16A16_FLOAT, R16G16B16A16_FLOAT}, |
| 523 | {PIPE_FORMAT_R16G16B16X16_FLOAT, R16G16B16X16_FLOAT}, |
| 524 | |
| 525 | /* 8 bits per component */ |
| 526 | {PIPE_FORMAT_R8_UNORM, R8_UNORM}, |
| 527 | {PIPE_FORMAT_R8G8_UNORM, R8G8_UNORM}, |
| 528 | {PIPE_FORMAT_R8G8B8_UNORM, R8G8B8_UNORM}, |
| 529 | {PIPE_FORMAT_R8G8B8_SRGB, R8G8B8_UNORM_SRGB}, |
| 530 | {PIPE_FORMAT_R8G8B8A8_UNORM, R8G8B8A8_UNORM}, |
| 531 | {PIPE_FORMAT_R8G8B8A8_SRGB, R8G8B8A8_UNORM_SRGB}, |
| 532 | {PIPE_FORMAT_R8G8B8X8_UNORM, R8G8B8X8_UNORM}, |
Ilia Mirkin | 8ed703c | 2016-11-20 17:51:24 -0500 | [diff] [blame] | 533 | {PIPE_FORMAT_R8G8B8X8_SRGB, R8G8B8X8_UNORM_SRGB}, |
Ilia Mirkin | d6a06228 | 2016-11-20 17:42:26 -0500 | [diff] [blame] | 534 | |
| 535 | {PIPE_FORMAT_R8_USCALED, R8_USCALED}, |
| 536 | {PIPE_FORMAT_R8G8_USCALED, R8G8_USCALED}, |
| 537 | {PIPE_FORMAT_R8G8B8_USCALED, R8G8B8_USCALED}, |
| 538 | {PIPE_FORMAT_R8G8B8A8_USCALED, R8G8B8A8_USCALED}, |
| 539 | |
| 540 | {PIPE_FORMAT_R8_SNORM, R8_SNORM}, |
| 541 | {PIPE_FORMAT_R8G8_SNORM, R8G8_SNORM}, |
| 542 | {PIPE_FORMAT_R8G8B8_SNORM, R8G8B8_SNORM}, |
| 543 | {PIPE_FORMAT_R8G8B8A8_SNORM, R8G8B8A8_SNORM}, |
| 544 | |
| 545 | {PIPE_FORMAT_R8_SSCALED, R8_SSCALED}, |
| 546 | {PIPE_FORMAT_R8G8_SSCALED, R8G8_SSCALED}, |
| 547 | {PIPE_FORMAT_R8G8B8_SSCALED, R8G8B8_SSCALED}, |
| 548 | {PIPE_FORMAT_R8G8B8A8_SSCALED, R8G8B8A8_SSCALED}, |
| 549 | |
| 550 | {PIPE_FORMAT_R8_UINT, R8_UINT}, |
| 551 | {PIPE_FORMAT_R8G8_UINT, R8G8_UINT}, |
| 552 | {PIPE_FORMAT_R8G8B8_UINT, R8G8B8_UINT}, |
| 553 | {PIPE_FORMAT_R8G8B8A8_UINT, R8G8B8A8_UINT}, |
| 554 | |
| 555 | {PIPE_FORMAT_R8_SINT, R8_SINT}, |
| 556 | {PIPE_FORMAT_R8G8_SINT, R8G8_SINT}, |
| 557 | {PIPE_FORMAT_R8G8B8_SINT, R8G8B8_SINT}, |
| 558 | {PIPE_FORMAT_R8G8B8A8_SINT, R8G8B8A8_SINT}, |
Ilia Mirkin | 946a7ab | 2016-11-12 13:09:21 -0500 | [diff] [blame] | 559 | |
Tim Rowley | 2a127b7 | 2016-12-07 17:04:20 -0600 | [diff] [blame] | 560 | /* These formats are valid for vertex data, but should not be used |
| 561 | * for render targets. |
| 562 | */ |
| 563 | |
| 564 | {PIPE_FORMAT_R32_FIXED, R32_SFIXED}, |
| 565 | {PIPE_FORMAT_R32G32_FIXED, R32G32_SFIXED}, |
| 566 | {PIPE_FORMAT_R32G32B32_FIXED, R32G32B32_SFIXED}, |
| 567 | {PIPE_FORMAT_R32G32B32A32_FIXED, R32G32B32A32_SFIXED}, |
| 568 | |
Tim Rowley | 33fa4c9 | 2017-01-05 07:29:22 -0600 | [diff] [blame] | 569 | {PIPE_FORMAT_R64_FLOAT, R64_FLOAT}, |
| 570 | {PIPE_FORMAT_R64G64_FLOAT, R64G64_FLOAT}, |
| 571 | {PIPE_FORMAT_R64G64B64_FLOAT, R64G64B64_FLOAT}, |
| 572 | {PIPE_FORMAT_R64G64B64A64_FLOAT, R64G64B64A64_FLOAT}, |
| 573 | |
Ilia Mirkin | 946a7ab | 2016-11-12 13:09:21 -0500 | [diff] [blame] | 574 | /* These formats have entries in SWR but don't have Load/StoreTile |
| 575 | * implementations. That means these aren't renderable, and thus having |
| 576 | * a mapping entry here is detrimental. |
| 577 | */ |
| 578 | /* |
| 579 | |
| 580 | {PIPE_FORMAT_L8_UNORM, L8_UNORM}, |
| 581 | {PIPE_FORMAT_I8_UNORM, I8_UNORM}, |
| 582 | {PIPE_FORMAT_L8A8_UNORM, L8A8_UNORM}, |
| 583 | {PIPE_FORMAT_L16_UNORM, L16_UNORM}, |
| 584 | {PIPE_FORMAT_UYVY, YCRCB_SWAPUVY}, |
| 585 | |
| 586 | {PIPE_FORMAT_L8_SRGB, L8_UNORM_SRGB}, |
| 587 | {PIPE_FORMAT_L8A8_SRGB, L8A8_UNORM_SRGB}, |
| 588 | |
| 589 | {PIPE_FORMAT_DXT1_RGBA, BC1_UNORM}, |
| 590 | {PIPE_FORMAT_DXT3_RGBA, BC2_UNORM}, |
| 591 | {PIPE_FORMAT_DXT5_RGBA, BC3_UNORM}, |
| 592 | |
| 593 | {PIPE_FORMAT_DXT1_SRGBA, BC1_UNORM_SRGB}, |
| 594 | {PIPE_FORMAT_DXT3_SRGBA, BC2_UNORM_SRGB}, |
| 595 | {PIPE_FORMAT_DXT5_SRGBA, BC3_UNORM_SRGB}, |
| 596 | |
| 597 | {PIPE_FORMAT_RGTC1_UNORM, BC4_UNORM}, |
| 598 | {PIPE_FORMAT_RGTC1_SNORM, BC4_SNORM}, |
| 599 | {PIPE_FORMAT_RGTC2_UNORM, BC5_UNORM}, |
| 600 | {PIPE_FORMAT_RGTC2_SNORM, BC5_SNORM}, |
| 601 | |
| 602 | {PIPE_FORMAT_L16A16_UNORM, L16A16_UNORM}, |
| 603 | {PIPE_FORMAT_I16_UNORM, I16_UNORM}, |
| 604 | {PIPE_FORMAT_L16_FLOAT, L16_FLOAT}, |
| 605 | {PIPE_FORMAT_L16A16_FLOAT, L16A16_FLOAT}, |
| 606 | {PIPE_FORMAT_I16_FLOAT, I16_FLOAT}, |
| 607 | {PIPE_FORMAT_L32_FLOAT, L32_FLOAT}, |
| 608 | {PIPE_FORMAT_L32A32_FLOAT, L32A32_FLOAT}, |
| 609 | {PIPE_FORMAT_I32_FLOAT, I32_FLOAT}, |
| 610 | |
| 611 | {PIPE_FORMAT_I8_UINT, I8_UINT}, |
| 612 | {PIPE_FORMAT_L8_UINT, L8_UINT}, |
| 613 | {PIPE_FORMAT_L8A8_UINT, L8A8_UINT}, |
| 614 | |
| 615 | {PIPE_FORMAT_I8_SINT, I8_SINT}, |
| 616 | {PIPE_FORMAT_L8_SINT, L8_SINT}, |
| 617 | {PIPE_FORMAT_L8A8_SINT, L8A8_SINT}, |
| 618 | |
| 619 | */ |
Tim Rowley | 50842e8 | 2016-09-20 11:15:55 -0500 | [diff] [blame] | 620 | }; |
| 621 | |
Ilia Mirkin | 2b7bdff | 2016-11-12 22:18:48 -0500 | [diff] [blame] | 622 | auto it = mesa2swr.find(format); |
| 623 | if (it == mesa2swr.end()) |
Tim Rowley | 2b2d368 | 2016-02-16 17:27:28 -0600 | [diff] [blame] | 624 | return (SWR_FORMAT)-1; |
Ilia Mirkin | 2b7bdff | 2016-11-12 22:18:48 -0500 | [diff] [blame] | 625 | else |
| 626 | return it->second; |
Tim Rowley | 2b2d368 | 2016-02-16 17:27:28 -0600 | [diff] [blame] | 627 | } |
| 628 | |
| 629 | static boolean |
| 630 | swr_displaytarget_layout(struct swr_screen *screen, struct swr_resource *res) |
| 631 | { |
| 632 | struct sw_winsys *winsys = screen->winsys; |
| 633 | struct sw_displaytarget *dt; |
| 634 | |
Ilia Mirkin | 7cfb364 | 2016-11-09 17:16:36 -0500 | [diff] [blame] | 635 | const unsigned width = align(res->swr.width, res->swr.halign); |
| 636 | const unsigned height = align(res->swr.height, res->swr.valign); |
| 637 | |
Tim Rowley | 2b2d368 | 2016-02-16 17:27:28 -0600 | [diff] [blame] | 638 | UINT stride; |
| 639 | dt = winsys->displaytarget_create(winsys, |
| 640 | res->base.bind, |
| 641 | res->base.format, |
Ilia Mirkin | 7cfb364 | 2016-11-09 17:16:36 -0500 | [diff] [blame] | 642 | width, height, |
Tim Rowley | 2b2d368 | 2016-02-16 17:27:28 -0600 | [diff] [blame] | 643 | 64, NULL, |
| 644 | &stride); |
| 645 | |
| 646 | if (dt == NULL) |
| 647 | return FALSE; |
| 648 | |
| 649 | void *map = winsys->displaytarget_map(winsys, dt, 0); |
| 650 | |
| 651 | res->display_target = dt; |
| 652 | res->swr.pBaseAddress = (uint8_t*) map; |
| 653 | |
| 654 | /* Clear the display target surface */ |
| 655 | if (map) |
Ilia Mirkin | 7cfb364 | 2016-11-09 17:16:36 -0500 | [diff] [blame] | 656 | memset(map, 0, height * stride); |
Tim Rowley | 2b2d368 | 2016-02-16 17:27:28 -0600 | [diff] [blame] | 657 | |
| 658 | winsys->displaytarget_unmap(winsys, dt); |
| 659 | |
| 660 | return TRUE; |
| 661 | } |
| 662 | |
Ilia Mirkin | 7cfb364 | 2016-11-09 17:16:36 -0500 | [diff] [blame] | 663 | static bool |
Tim Rowley | 2b2d368 | 2016-02-16 17:27:28 -0600 | [diff] [blame] | 664 | swr_texture_layout(struct swr_screen *screen, |
| 665 | struct swr_resource *res, |
| 666 | boolean allocate) |
| 667 | { |
| 668 | struct pipe_resource *pt = &res->base; |
| 669 | |
| 670 | pipe_format fmt = pt->format; |
| 671 | const struct util_format_description *desc = util_format_description(fmt); |
| 672 | |
| 673 | res->has_depth = util_format_has_depth(desc); |
| 674 | res->has_stencil = util_format_has_stencil(desc); |
| 675 | |
| 676 | if (res->has_stencil && !res->has_depth) |
| 677 | fmt = PIPE_FORMAT_R8_UINT; |
| 678 | |
Ilia Mirkin | 7cfb364 | 2016-11-09 17:16:36 -0500 | [diff] [blame] | 679 | /* We always use the SWR layout. For 2D and 3D textures this looks like: |
| 680 | * |
| 681 | * |<------- pitch ------->| |
| 682 | * +=======================+------- |
| 683 | * |Array 0 | ^ |
| 684 | * | | | |
| 685 | * | Level 0 | | |
| 686 | * | | | |
| 687 | * | | qpitch |
| 688 | * +-----------+-----------+ | |
| 689 | * | | L2L2L2L2 | | |
| 690 | * | Level 1 | L3L3 | | |
| 691 | * | | L4 | v |
| 692 | * +===========+===========+------- |
| 693 | * |Array 1 | |
| 694 | * | | |
| 695 | * | Level 0 | |
| 696 | * | | |
| 697 | * | | |
| 698 | * +-----------+-----------+ |
| 699 | * | | L2L2L2L2 | |
| 700 | * | Level 1 | L3L3 | |
| 701 | * | | L4 | |
| 702 | * +===========+===========+ |
| 703 | * |
| 704 | * The overall width in bytes is known as the pitch, while the overall |
| 705 | * height in rows is the qpitch. Array slices are laid out logically below |
| 706 | * one another, qpitch rows apart. For 3D surfaces, the "level" values are |
| 707 | * just invalid for the higher array numbers (since depth is also |
| 708 | * minified). 1D and 1D array surfaces are stored effectively the same way, |
| 709 | * except that pitch never plays into it. All the levels are logically |
| 710 | * adjacent to each other on the X axis. The qpitch becomes the number of |
| 711 | * elements between array slices, while the pitch is unused. |
| 712 | * |
| 713 | * Each level's sizes are subject to the valign and halign settings of the |
| 714 | * surface. For compressed formats that swr is unaware of, we will use an |
| 715 | * appropriately-sized uncompressed format, and scale the widths/heights. |
| 716 | * |
| 717 | * This surface is stored inside res->swr. For depth/stencil textures, |
| 718 | * res->secondary will have an identically-laid-out but R8_UINT-formatted |
| 719 | * stencil tree. In the Z32F_S8 case, the primary surface still has 64-bpp |
| 720 | * texels, to simplify map/unmap logic which copies the stencil values |
| 721 | * in/out. |
| 722 | */ |
| 723 | |
Tim Rowley | 2b2d368 | 2016-02-16 17:27:28 -0600 | [diff] [blame] | 724 | res->swr.width = pt->width0; |
| 725 | res->swr.height = pt->height0; |
Tim Rowley | 2b2d368 | 2016-02-16 17:27:28 -0600 | [diff] [blame] | 726 | res->swr.type = swr_convert_target_type(pt->target); |
| 727 | res->swr.tileMode = SWR_TILE_NONE; |
| 728 | res->swr.format = mesa_to_swr_format(fmt); |
Ilia Mirkin | 7cfb364 | 2016-11-09 17:16:36 -0500 | [diff] [blame] | 729 | res->swr.numSamples = std::max(1u, pt->nr_samples); |
Tim Rowley | 2b2d368 | 2016-02-16 17:27:28 -0600 | [diff] [blame] | 730 | |
Ilia Mirkin | 7cfb364 | 2016-11-09 17:16:36 -0500 | [diff] [blame] | 731 | if (pt->bind & (PIPE_BIND_RENDER_TARGET | PIPE_BIND_DEPTH_STENCIL)) { |
| 732 | res->swr.halign = KNOB_MACROTILE_X_DIM; |
| 733 | res->swr.valign = KNOB_MACROTILE_Y_DIM; |
Bruce Cherniak | 1832ef6 | 2017-04-13 17:40:11 -0500 | [diff] [blame] | 734 | |
| 735 | /* If SWR_MSAA_FORCE_ENABLE is set, turn on MSAA and override requested |
| 736 | * surface sample count. */ |
| 737 | if (screen->msaa_force_enable) { |
| 738 | res->swr.numSamples = screen->msaa_max_count; |
| 739 | fprintf(stderr,"swr_texture_layout: forcing sample count: %d\n", |
| 740 | res->swr.numSamples); |
| 741 | } |
Ilia Mirkin | 7cfb364 | 2016-11-09 17:16:36 -0500 | [diff] [blame] | 742 | } else { |
| 743 | res->swr.halign = 1; |
| 744 | res->swr.valign = 1; |
Tim Rowley | 2b2d368 | 2016-02-16 17:27:28 -0600 | [diff] [blame] | 745 | } |
| 746 | |
Ilia Mirkin | 7cfb364 | 2016-11-09 17:16:36 -0500 | [diff] [blame] | 747 | unsigned halign = res->swr.halign * util_format_get_blockwidth(fmt); |
| 748 | unsigned width = align(pt->width0, halign); |
| 749 | if (pt->target == PIPE_TEXTURE_1D || pt->target == PIPE_TEXTURE_1D_ARRAY) { |
| 750 | for (int level = 1; level <= pt->last_level; level++) |
| 751 | width += align(u_minify(pt->width0, level), halign); |
| 752 | res->swr.pitch = util_format_get_blocksize(fmt); |
| 753 | res->swr.qpitch = util_format_get_nblocksx(fmt, width); |
| 754 | } else { |
| 755 | // The pitch is the overall width of the texture in bytes. Most of the |
| 756 | // time this is the pitch of level 0 since all the other levels fit |
| 757 | // underneath it. However in some degenerate situations, the width of |
| 758 | // level1 + level2 may be larger. In that case, we use those |
| 759 | // widths. This can happen if, e.g. halign is 32, and the width of level |
| 760 | // 0 is 32 or less. In that case, the aligned levels 1 and 2 will also |
| 761 | // be 32 each, adding up to 64. |
| 762 | unsigned valign = res->swr.valign * util_format_get_blockheight(fmt); |
| 763 | if (pt->last_level > 1) { |
| 764 | width = std::max<uint32_t>( |
| 765 | width, |
| 766 | align(u_minify(pt->width0, 1), halign) + |
| 767 | align(u_minify(pt->width0, 2), halign)); |
| 768 | } |
| 769 | res->swr.pitch = util_format_get_stride(fmt, width); |
| 770 | |
| 771 | // The qpitch is controlled by either the height of the second LOD, or |
| 772 | // the combination of all the later LODs. |
| 773 | unsigned height = align(pt->height0, valign); |
| 774 | if (pt->last_level == 1) { |
| 775 | height += align(u_minify(pt->height0, 1), valign); |
| 776 | } else if (pt->last_level > 1) { |
| 777 | unsigned level1 = align(u_minify(pt->height0, 1), valign); |
| 778 | unsigned level2 = 0; |
| 779 | for (int level = 2; level <= pt->last_level; level++) { |
| 780 | level2 += align(u_minify(pt->height0, level), valign); |
| 781 | } |
| 782 | height += std::max(level1, level2); |
| 783 | } |
| 784 | res->swr.qpitch = util_format_get_nblocksy(fmt, height); |
| 785 | } |
| 786 | |
| 787 | if (pt->target == PIPE_TEXTURE_3D) |
| 788 | res->swr.depth = pt->depth0; |
| 789 | else |
| 790 | res->swr.depth = pt->array_size; |
| 791 | |
| 792 | // Fix up swr format if necessary so that LOD offset computation works |
| 793 | if (res->swr.format == (SWR_FORMAT)-1) { |
| 794 | switch (util_format_get_blocksize(fmt)) { |
| 795 | default: |
| 796 | unreachable("Unexpected format block size"); |
| 797 | case 1: res->swr.format = R8_UINT; break; |
| 798 | case 2: res->swr.format = R16_UINT; break; |
| 799 | case 4: res->swr.format = R32_UINT; break; |
| 800 | case 8: |
| 801 | if (util_format_is_compressed(fmt)) |
| 802 | res->swr.format = BC4_UNORM; |
| 803 | else |
| 804 | res->swr.format = R32G32_UINT; |
| 805 | break; |
| 806 | case 16: |
| 807 | if (util_format_is_compressed(fmt)) |
| 808 | res->swr.format = BC5_UNORM; |
| 809 | else |
| 810 | res->swr.format = R32G32B32A32_UINT; |
| 811 | break; |
| 812 | } |
| 813 | } |
| 814 | |
| 815 | for (int level = 0; level <= pt->last_level; level++) { |
| 816 | res->mip_offsets[level] = |
| 817 | ComputeSurfaceOffset<false>(0, 0, 0, 0, 0, level, &res->swr); |
| 818 | } |
| 819 | |
Bruce Cherniak | 1832ef6 | 2017-04-13 17:40:11 -0500 | [diff] [blame] | 820 | size_t total_size = res->swr.depth * res->swr.qpitch * res->swr.pitch * |
| 821 | res->swr.numSamples; |
Ilia Mirkin | 7cfb364 | 2016-11-09 17:16:36 -0500 | [diff] [blame] | 822 | if (total_size > SWR_MAX_TEXTURE_SIZE) |
| 823 | return false; |
Tim Rowley | 2b2d368 | 2016-02-16 17:27:28 -0600 | [diff] [blame] | 824 | |
| 825 | if (allocate) { |
Tim Rowley | 4997169 | 2016-05-06 12:49:23 -0600 | [diff] [blame] | 826 | res->swr.pBaseAddress = (uint8_t *)AlignedMalloc(total_size, 64); |
Tim Rowley | 2b2d368 | 2016-02-16 17:27:28 -0600 | [diff] [blame] | 827 | |
| 828 | if (res->has_depth && res->has_stencil) { |
Ilia Mirkin | 7cfb364 | 2016-11-09 17:16:36 -0500 | [diff] [blame] | 829 | res->secondary = res->swr; |
Tim Rowley | 2b2d368 | 2016-02-16 17:27:28 -0600 | [diff] [blame] | 830 | res->secondary.format = R8_UINT; |
Ilia Mirkin | 7cfb364 | 2016-11-09 17:16:36 -0500 | [diff] [blame] | 831 | res->secondary.pitch = res->swr.pitch / util_format_get_blocksize(fmt); |
| 832 | |
| 833 | for (int level = 0; level <= pt->last_level; level++) { |
| 834 | res->secondary_mip_offsets[level] = |
| 835 | ComputeSurfaceOffset<false>(0, 0, 0, 0, 0, level, &res->secondary); |
| 836 | } |
Tim Rowley | 2b2d368 | 2016-02-16 17:27:28 -0600 | [diff] [blame] | 837 | |
Bruce Cherniak | 1832ef6 | 2017-04-13 17:40:11 -0500 | [diff] [blame] | 838 | total_size = res->secondary.depth * res->secondary.qpitch * |
| 839 | res->secondary.pitch * res->secondary.numSamples; |
| 840 | |
| 841 | res->secondary.pBaseAddress = (uint8_t *) AlignedMalloc(total_size, |
| 842 | 64); |
Tim Rowley | 2b2d368 | 2016-02-16 17:27:28 -0600 | [diff] [blame] | 843 | } |
| 844 | } |
| 845 | |
Ilia Mirkin | 7cfb364 | 2016-11-09 17:16:36 -0500 | [diff] [blame] | 846 | return true; |
Tim Rowley | 2b2d368 | 2016-02-16 17:27:28 -0600 | [diff] [blame] | 847 | } |
| 848 | |
| 849 | static boolean |
| 850 | swr_can_create_resource(struct pipe_screen *screen, |
| 851 | const struct pipe_resource *templat) |
| 852 | { |
| 853 | struct swr_resource res; |
| 854 | memset(&res, 0, sizeof(res)); |
| 855 | res.base = *templat; |
| 856 | return swr_texture_layout(swr_screen(screen), &res, false); |
| 857 | } |
| 858 | |
Bruce Cherniak | 1832ef6 | 2017-04-13 17:40:11 -0500 | [diff] [blame] | 859 | /* Helper function that conditionally creates a single-sample resolve resource |
| 860 | * and attaches it to main multisample resource. */ |
| 861 | static boolean |
| 862 | swr_create_resolve_resource(struct pipe_screen *_screen, |
| 863 | struct swr_resource *msaa_res) |
| 864 | { |
| 865 | struct swr_screen *screen = swr_screen(_screen); |
| 866 | |
| 867 | /* If resource is multisample, create a single-sample resolve resource */ |
| 868 | if (msaa_res->base.nr_samples > 1 || (screen->msaa_force_enable && |
| 869 | !(msaa_res->base.flags & SWR_RESOURCE_FLAG_ALT_SURFACE))) { |
| 870 | |
| 871 | /* Create a single-sample copy of the resource. Copy the original |
| 872 | * resource parameters and set flag to prevent recursion when re-calling |
| 873 | * resource_create */ |
| 874 | struct pipe_resource alt_template = msaa_res->base; |
| 875 | alt_template.nr_samples = 0; |
| 876 | alt_template.flags |= SWR_RESOURCE_FLAG_ALT_SURFACE; |
| 877 | |
| 878 | /* Note: Display_target is a special single-sample resource, only the |
| 879 | * display_target has been created already. */ |
| 880 | if (msaa_res->base.bind & (PIPE_BIND_DISPLAY_TARGET | PIPE_BIND_SCANOUT |
| 881 | | PIPE_BIND_SHARED)) { |
| 882 | /* Allocate the multisample buffers. */ |
| 883 | if (!swr_texture_layout(screen, msaa_res, true)) |
| 884 | return false; |
| 885 | |
| 886 | /* Alt resource will only be bound as PIPE_BIND_RENDER_TARGET |
| 887 | * remove the DISPLAY_TARGET, SCANOUT, and SHARED bindings */ |
| 888 | alt_template.bind = PIPE_BIND_RENDER_TARGET; |
| 889 | } |
| 890 | |
| 891 | /* Allocate single-sample resolve surface */ |
| 892 | struct pipe_resource *alt; |
| 893 | alt = _screen->resource_create(_screen, &alt_template); |
| 894 | if (!alt) |
| 895 | return false; |
| 896 | |
| 897 | /* Attach it to the multisample resource */ |
| 898 | msaa_res->resolve_target = alt; |
Bruce Cherniak | f52e630 | 2017-05-04 19:33:36 -0500 | [diff] [blame] | 899 | |
| 900 | /* Hang resolve surface state off the multisample surface state to so |
| 901 | * StoreTiles knows where to resolve the surface. */ |
| 902 | msaa_res->swr.pAuxBaseAddress = (uint8_t *)&swr_resource(alt)->swr; |
Bruce Cherniak | 1832ef6 | 2017-04-13 17:40:11 -0500 | [diff] [blame] | 903 | } |
| 904 | |
| 905 | return true; /* success */ |
| 906 | } |
| 907 | |
Tim Rowley | 2b2d368 | 2016-02-16 17:27:28 -0600 | [diff] [blame] | 908 | static struct pipe_resource * |
| 909 | swr_resource_create(struct pipe_screen *_screen, |
| 910 | const struct pipe_resource *templat) |
| 911 | { |
| 912 | struct swr_screen *screen = swr_screen(_screen); |
| 913 | struct swr_resource *res = CALLOC_STRUCT(swr_resource); |
| 914 | if (!res) |
| 915 | return NULL; |
| 916 | |
| 917 | res->base = *templat; |
| 918 | pipe_reference_init(&res->base.reference, 1); |
| 919 | res->base.screen = &screen->base; |
| 920 | |
| 921 | if (swr_resource_is_texture(&res->base)) { |
| 922 | if (res->base.bind & (PIPE_BIND_DISPLAY_TARGET | PIPE_BIND_SCANOUT |
| 923 | | PIPE_BIND_SHARED)) { |
| 924 | /* displayable surface |
| 925 | * first call swr_texture_layout without allocating to finish |
Bruce Cherniak | 1832ef6 | 2017-04-13 17:40:11 -0500 | [diff] [blame] | 926 | * filling out the SWR_SURFACE_STATE in res */ |
Tim Rowley | 2b2d368 | 2016-02-16 17:27:28 -0600 | [diff] [blame] | 927 | swr_texture_layout(screen, res, false); |
| 928 | if (!swr_displaytarget_layout(screen, res)) |
| 929 | goto fail; |
| 930 | } else { |
| 931 | /* texture map */ |
| 932 | if (!swr_texture_layout(screen, res, true)) |
| 933 | goto fail; |
| 934 | } |
Bruce Cherniak | 1832ef6 | 2017-04-13 17:40:11 -0500 | [diff] [blame] | 935 | |
| 936 | /* If resource was multisample, create resolve resource and attach |
| 937 | * it to multisample resource. */ |
| 938 | if (!swr_create_resolve_resource(_screen, res)) |
| 939 | goto fail; |
| 940 | |
Tim Rowley | 2b2d368 | 2016-02-16 17:27:28 -0600 | [diff] [blame] | 941 | } else { |
| 942 | /* other data (vertex buffer, const buffer, etc) */ |
| 943 | assert(util_format_get_blocksize(templat->format) == 1); |
| 944 | assert(templat->height0 == 1); |
| 945 | assert(templat->depth0 == 1); |
| 946 | assert(templat->last_level == 0); |
| 947 | |
| 948 | /* Easiest to just call swr_texture_layout, as it sets up |
Bruce Cherniak | 1832ef6 | 2017-04-13 17:40:11 -0500 | [diff] [blame] | 949 | * SWR_SURFACE_STATE in res */ |
Tim Rowley | 2b2d368 | 2016-02-16 17:27:28 -0600 | [diff] [blame] | 950 | if (!swr_texture_layout(screen, res, true)) |
| 951 | goto fail; |
| 952 | } |
| 953 | |
| 954 | return &res->base; |
| 955 | |
| 956 | fail: |
| 957 | FREE(res); |
| 958 | return NULL; |
| 959 | } |
| 960 | |
| 961 | static void |
| 962 | swr_resource_destroy(struct pipe_screen *p_screen, struct pipe_resource *pt) |
| 963 | { |
| 964 | struct swr_screen *screen = swr_screen(p_screen); |
Bruce Cherniak | e9d68cc | 2016-03-09 19:30:00 -0600 | [diff] [blame] | 965 | struct swr_resource *spr = swr_resource(pt); |
Tim Rowley | 2b2d368 | 2016-02-16 17:27:28 -0600 | [diff] [blame] | 966 | |
Bruce Cherniak | e9d68cc | 2016-03-09 19:30:00 -0600 | [diff] [blame] | 967 | if (spr->display_target) { |
Bruce Cherniak | 79b66ec | 2016-12-12 19:24:59 -0600 | [diff] [blame] | 968 | /* If resource is display target, winsys manages the buffer and will |
| 969 | * free it on displaytarget_destroy. */ |
| 970 | swr_fence_finish(p_screen, NULL, screen->flush_fence, 0); |
| 971 | |
Tim Rowley | 2b2d368 | 2016-02-16 17:27:28 -0600 | [diff] [blame] | 972 | struct sw_winsys *winsys = screen->winsys; |
Bruce Cherniak | e9d68cc | 2016-03-09 19:30:00 -0600 | [diff] [blame] | 973 | winsys->displaytarget_destroy(winsys, spr->display_target); |
Tim Rowley | 2b2d368 | 2016-02-16 17:27:28 -0600 | [diff] [blame] | 974 | |
Bruce Cherniak | 1832ef6 | 2017-04-13 17:40:11 -0500 | [diff] [blame] | 975 | if (spr->swr.numSamples > 1) { |
| 976 | /* Free an attached resolve resource */ |
| 977 | struct swr_resource *alt = swr_resource(spr->resolve_target); |
| 978 | swr_fence_work_free(screen->flush_fence, alt->swr.pBaseAddress, true); |
| 979 | |
| 980 | /* Free multisample buffer */ |
| 981 | swr_fence_work_free(screen->flush_fence, spr->swr.pBaseAddress, true); |
| 982 | } |
Bruce Cherniak | 79b66ec | 2016-12-12 19:24:59 -0600 | [diff] [blame] | 983 | } else { |
George Kyriazis | a61528f | 2017-01-10 17:12:03 -0600 | [diff] [blame] | 984 | /* For regular resources, defer deletion */ |
| 985 | swr_resource_unused(pt); |
Bruce Cherniak | 1832ef6 | 2017-04-13 17:40:11 -0500 | [diff] [blame] | 986 | |
| 987 | if (spr->swr.numSamples > 1) { |
| 988 | /* Free an attached resolve resource */ |
| 989 | struct swr_resource *alt = swr_resource(spr->resolve_target); |
| 990 | swr_fence_work_free(screen->flush_fence, alt->swr.pBaseAddress, true); |
| 991 | } |
| 992 | |
George Kyriazis | a61528f | 2017-01-10 17:12:03 -0600 | [diff] [blame] | 993 | swr_fence_work_free(screen->flush_fence, spr->swr.pBaseAddress, true); |
| 994 | swr_fence_work_free(screen->flush_fence, |
| 995 | spr->secondary.pBaseAddress, true); |
Bruce Cherniak | 32c1a54 | 2017-06-30 22:24:46 -0500 | [diff] [blame] | 996 | |
| 997 | /* If work queue grows too large, submit a fence to force queue to |
| 998 | * drain. This is mainly to decrease the amount of memory used by the |
| 999 | * piglit streaming-texture-leak test */ |
| 1000 | if (screen->pipe && swr_fence(screen->flush_fence)->work.count > 64) |
| 1001 | swr_fence_submit(swr_context(screen->pipe), screen->flush_fence); |
Bruce Cherniak | 79b66ec | 2016-12-12 19:24:59 -0600 | [diff] [blame] | 1002 | } |
Tim Rowley | 2b2d368 | 2016-02-16 17:27:28 -0600 | [diff] [blame] | 1003 | |
Bruce Cherniak | e9d68cc | 2016-03-09 19:30:00 -0600 | [diff] [blame] | 1004 | FREE(spr); |
Tim Rowley | 2b2d368 | 2016-02-16 17:27:28 -0600 | [diff] [blame] | 1005 | } |
| 1006 | |
| 1007 | |
| 1008 | static void |
| 1009 | swr_flush_frontbuffer(struct pipe_screen *p_screen, |
| 1010 | struct pipe_resource *resource, |
| 1011 | unsigned level, |
| 1012 | unsigned layer, |
| 1013 | void *context_private, |
| 1014 | struct pipe_box *sub_box) |
| 1015 | { |
| 1016 | struct swr_screen *screen = swr_screen(p_screen); |
| 1017 | struct sw_winsys *winsys = screen->winsys; |
Bruce Cherniak | e9d68cc | 2016-03-09 19:30:00 -0600 | [diff] [blame] | 1018 | struct swr_resource *spr = swr_resource(resource); |
George Kyriazis | dd63fa2 | 2016-03-14 17:40:14 -0500 | [diff] [blame] | 1019 | struct pipe_context *pipe = screen->pipe; |
Tim Rowley | 50cd222 | 2017-06-29 14:03:43 -0500 | [diff] [blame] | 1020 | struct swr_context *ctx = swr_context(pipe); |
Tim Rowley | 2b2d368 | 2016-02-16 17:27:28 -0600 | [diff] [blame] | 1021 | |
Bruce Cherniak | e9d68cc | 2016-03-09 19:30:00 -0600 | [diff] [blame] | 1022 | if (pipe) { |
Marek Olšák | 54272e1 | 2016-08-06 16:41:42 +0200 | [diff] [blame] | 1023 | swr_fence_finish(p_screen, NULL, screen->flush_fence, 0); |
George Kyriazis | dd63fa2 | 2016-03-14 17:40:14 -0500 | [diff] [blame] | 1024 | swr_resource_unused(resource); |
Tim Rowley | 50cd222 | 2017-06-29 14:03:43 -0500 | [diff] [blame] | 1025 | ctx->api.pfnSwrEndFrame(ctx->swrContext); |
Bruce Cherniak | e9d68cc | 2016-03-09 19:30:00 -0600 | [diff] [blame] | 1026 | } |
Tim Rowley | 2b2d368 | 2016-02-16 17:27:28 -0600 | [diff] [blame] | 1027 | |
Bruce Cherniak | f52e630 | 2017-05-04 19:33:36 -0500 | [diff] [blame] | 1028 | /* Multisample resolved into resolve_target at flush with store_resource */ |
Bruce Cherniak | 1832ef6 | 2017-04-13 17:40:11 -0500 | [diff] [blame] | 1029 | if (pipe && spr->swr.numSamples > 1) { |
| 1030 | struct pipe_resource *resolve_target = spr->resolve_target; |
| 1031 | |
Bruce Cherniak | 1832ef6 | 2017-04-13 17:40:11 -0500 | [diff] [blame] | 1032 | /* Once resolved, copy into display target */ |
| 1033 | SWR_SURFACE_STATE *resolve = &swr_resource(resolve_target)->swr; |
| 1034 | |
| 1035 | void *map = winsys->displaytarget_map(winsys, spr->display_target, |
| 1036 | PIPE_TRANSFER_WRITE); |
| 1037 | memcpy(map, resolve->pBaseAddress, resolve->pitch * resolve->height); |
| 1038 | winsys->displaytarget_unmap(winsys, spr->display_target); |
| 1039 | } |
| 1040 | |
Bruce Cherniak | e9d68cc | 2016-03-09 19:30:00 -0600 | [diff] [blame] | 1041 | debug_assert(spr->display_target); |
| 1042 | if (spr->display_target) |
Tim Rowley | 2b2d368 | 2016-02-16 17:27:28 -0600 | [diff] [blame] | 1043 | winsys->displaytarget_display( |
Bruce Cherniak | e9d68cc | 2016-03-09 19:30:00 -0600 | [diff] [blame] | 1044 | winsys, spr->display_target, context_private, sub_box); |
Tim Rowley | 2b2d368 | 2016-02-16 17:27:28 -0600 | [diff] [blame] | 1045 | } |
| 1046 | |
| 1047 | |
| 1048 | static void |
| 1049 | swr_destroy_screen(struct pipe_screen *p_screen) |
| 1050 | { |
| 1051 | struct swr_screen *screen = swr_screen(p_screen); |
| 1052 | struct sw_winsys *winsys = screen->winsys; |
| 1053 | |
| 1054 | fprintf(stderr, "SWR destroy screen!\n"); |
| 1055 | |
Marek Olšák | 54272e1 | 2016-08-06 16:41:42 +0200 | [diff] [blame] | 1056 | swr_fence_finish(p_screen, NULL, screen->flush_fence, 0); |
Tim Rowley | 2b2d368 | 2016-02-16 17:27:28 -0600 | [diff] [blame] | 1057 | swr_fence_reference(p_screen, &screen->flush_fence, NULL); |
| 1058 | |
| 1059 | JitDestroyContext(screen->hJitMgr); |
| 1060 | |
| 1061 | if (winsys->destroy) |
| 1062 | winsys->destroy(winsys); |
| 1063 | |
| 1064 | FREE(screen); |
| 1065 | } |
| 1066 | |
Bruce Cherniak | 1520a06 | 2017-07-12 15:04:46 -0500 | [diff] [blame] | 1067 | |
| 1068 | static void |
| 1069 | swr_validate_env_options(struct swr_screen *screen) |
| 1070 | { |
Bruce Cherniak | 02735e6 | 2017-07-12 15:04:47 -0500 | [diff] [blame] | 1071 | /* The client_copy_limit sets a maximum on the amount of user-buffer memory |
| 1072 | * copied to scratch space on a draw. Past this, the draw will access |
| 1073 | * user-buffer directly and then block. This is faster than queuing many |
| 1074 | * large client draws. */ |
| 1075 | screen->client_copy_limit = SWR_CLIENT_COPY_LIMIT; |
| 1076 | int client_copy_limit = |
| 1077 | debug_get_num_option("SWR_CLIENT_COPY_LIMIT", SWR_CLIENT_COPY_LIMIT); |
| 1078 | if (client_copy_limit > 0) |
| 1079 | screen->client_copy_limit = client_copy_limit; |
| 1080 | |
Bruce Cherniak | 1520a06 | 2017-07-12 15:04:46 -0500 | [diff] [blame] | 1081 | /* XXX msaa under development, disable by default for now */ |
| 1082 | screen->msaa_max_count = 0; /* was SWR_MAX_NUM_MULTISAMPLES; */ |
| 1083 | |
| 1084 | /* validate env override values, within range and power of 2 */ |
| 1085 | int msaa_max_count = debug_get_num_option("SWR_MSAA_MAX_COUNT", 0); |
| 1086 | if (msaa_max_count) { |
| 1087 | if ((msaa_max_count < 0) || (msaa_max_count > SWR_MAX_NUM_MULTISAMPLES) |
| 1088 | || !util_is_power_of_two(msaa_max_count)) { |
| 1089 | fprintf(stderr, "SWR_MSAA_MAX_COUNT invalid: %d\n", msaa_max_count); |
| 1090 | fprintf(stderr, "must be power of 2 between 1 and %d" \ |
| 1091 | " (or 0 to disable msaa)\n", |
| 1092 | SWR_MAX_NUM_MULTISAMPLES); |
| 1093 | msaa_max_count = 0; |
| 1094 | } |
| 1095 | |
| 1096 | fprintf(stderr, "SWR_MSAA_MAX_COUNT: %d\n", msaa_max_count); |
| 1097 | if (!msaa_max_count) |
| 1098 | fprintf(stderr, "(msaa disabled)\n"); |
| 1099 | |
| 1100 | screen->msaa_max_count = msaa_max_count; |
| 1101 | } |
| 1102 | |
| 1103 | screen->msaa_force_enable = debug_get_bool_option( |
| 1104 | "SWR_MSAA_FORCE_ENABLE", false); |
| 1105 | if (screen->msaa_force_enable) |
| 1106 | fprintf(stderr, "SWR_MSAA_FORCE_ENABLE: true\n"); |
| 1107 | } |
| 1108 | |
| 1109 | |
Tim Rowley | 2b2d368 | 2016-02-16 17:27:28 -0600 | [diff] [blame] | 1110 | PUBLIC |
| 1111 | struct pipe_screen * |
George Kyriazis | 87bd282 | 2016-11-17 16:21:12 -0600 | [diff] [blame] | 1112 | swr_create_screen_internal(struct sw_winsys *winsys) |
Tim Rowley | 2b2d368 | 2016-02-16 17:27:28 -0600 | [diff] [blame] | 1113 | { |
| 1114 | struct swr_screen *screen = CALLOC_STRUCT(swr_screen); |
| 1115 | |
| 1116 | if (!screen) |
| 1117 | return NULL; |
| 1118 | |
Tim Rowley | efc3ca6 | 2016-12-05 11:32:19 -0600 | [diff] [blame] | 1119 | if (!lp_build_init()) { |
| 1120 | FREE(screen); |
| 1121 | return NULL; |
| 1122 | } |
| 1123 | |
Tim Rowley | 2b2d368 | 2016-02-16 17:27:28 -0600 | [diff] [blame] | 1124 | screen->winsys = winsys; |
| 1125 | screen->base.get_name = swr_get_name; |
| 1126 | screen->base.get_vendor = swr_get_vendor; |
| 1127 | screen->base.is_format_supported = swr_is_format_supported; |
| 1128 | screen->base.context_create = swr_create_context; |
| 1129 | screen->base.can_create_resource = swr_can_create_resource; |
| 1130 | |
| 1131 | screen->base.destroy = swr_destroy_screen; |
| 1132 | screen->base.get_param = swr_get_param; |
| 1133 | screen->base.get_shader_param = swr_get_shader_param; |
| 1134 | screen->base.get_paramf = swr_get_paramf; |
| 1135 | |
| 1136 | screen->base.resource_create = swr_resource_create; |
| 1137 | screen->base.resource_destroy = swr_resource_destroy; |
| 1138 | |
| 1139 | screen->base.flush_frontbuffer = swr_flush_frontbuffer; |
| 1140 | |
Tim Rowley | 8182091 | 2017-07-14 15:01:35 -0500 | [diff] [blame] | 1141 | // Pass in "" for architecture for run-time determination |
| 1142 | screen->hJitMgr = JitCreateContext(KNOB_SIMD_WIDTH, "", "swr"); |
Tim Rowley | 2b2d368 | 2016-02-16 17:27:28 -0600 | [diff] [blame] | 1143 | |
| 1144 | swr_fence_init(&screen->base); |
| 1145 | |
Tim Rowley | 2785f2f | 2016-05-12 11:27:57 -0500 | [diff] [blame] | 1146 | util_format_s3tc_init(); |
| 1147 | |
Bruce Cherniak | 1520a06 | 2017-07-12 15:04:46 -0500 | [diff] [blame] | 1148 | swr_validate_env_options(screen); |
Bruce Cherniak | 1832ef6 | 2017-04-13 17:40:11 -0500 | [diff] [blame] | 1149 | |
Tim Rowley | 2b2d368 | 2016-02-16 17:27:28 -0600 | [diff] [blame] | 1150 | return &screen->base; |
| 1151 | } |
| 1152 | |