Christian König | ca9cf61 | 2012-07-19 15:20:45 +0200 | [diff] [blame] | 1 | /* |
| 2 | * Copyright 2012 Advanced Micro Devices, Inc. |
| 3 | * |
| 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 5 | * copy of this software and associated documentation files (the "Software"), |
| 6 | * to deal in the Software without restriction, including without limitation |
| 7 | * on the rights to use, copy, modify, merge, publish, distribute, sub |
| 8 | * license, and/or sell copies of the Software, and to permit persons to whom |
| 9 | * the Software is furnished to do so, subject to the following conditions: |
| 10 | * |
| 11 | * The above copyright notice and this permission notice (including the next |
| 12 | * paragraph) shall be included in all copies or substantial portions of the |
| 13 | * Software. |
| 14 | * |
| 15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 17 | * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL |
| 18 | * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, |
| 19 | * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR |
| 20 | * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE |
| 21 | * USE OR OTHER DEALINGS IN THE SOFTWARE. |
| 22 | * |
| 23 | * Authors: |
| 24 | * Christian König <christian.koenig@amd.com> |
| 25 | */ |
| 26 | |
Andreas Hartmetz | 786af2f | 2014-01-04 18:44:33 +0100 | [diff] [blame] | 27 | #include "si_pipe.h" |
| 28 | #include "si_shader.h" |
Emil Velikov | a131263 | 2014-08-16 17:58:25 +0100 | [diff] [blame] | 29 | #include "radeon/r600_cs.h" |
Christian König | ca9cf61 | 2012-07-19 15:20:45 +0200 | [diff] [blame] | 30 | #include "sid.h" |
| 31 | |
Marek Olšák | 7209703 | 2014-01-22 18:50:36 +0100 | [diff] [blame] | 32 | #include "util/u_index_modify.h" |
Marek Olšák | 7209703 | 2014-01-22 18:50:36 +0100 | [diff] [blame] | 33 | #include "util/u_upload_mgr.h" |
Marek Olšák | 09d02fa | 2015-02-22 18:06:34 +0100 | [diff] [blame] | 34 | #include "util/u_prim.h" |
Marek Olšák | 7209703 | 2014-01-22 18:50:36 +0100 | [diff] [blame] | 35 | |
Marek Olšák | 20e570d | 2014-12-07 17:53:56 +0100 | [diff] [blame] | 36 | static void si_decompress_textures(struct si_context *sctx) |
Michel Dänzer | 404b29d | 2013-11-21 16:45:28 +0900 | [diff] [blame] | 37 | { |
Marek Olšák | 20e570d | 2014-12-07 17:53:56 +0100 | [diff] [blame] | 38 | if (!sctx->blitter->running) { |
| 39 | /* Flush depth textures which need to be flushed. */ |
| 40 | for (int i = 0; i < SI_NUM_SHADERS; i++) { |
| 41 | if (sctx->samplers[i].depth_texture_mask) { |
| 42 | si_flush_depth_textures(sctx, &sctx->samplers[i]); |
Tom Stellard | 0fb1e68 | 2012-09-06 16:18:11 -0400 | [diff] [blame] | 43 | } |
Marek Olšák | 20e570d | 2014-12-07 17:53:56 +0100 | [diff] [blame] | 44 | if (sctx->samplers[i].compressed_colortex_mask) { |
| 45 | si_decompress_color_textures(sctx, &sctx->samplers[i]); |
| 46 | } |
Tom Stellard | 0fb1e68 | 2012-09-06 16:18:11 -0400 | [diff] [blame] | 47 | } |
Christian König | ca9cf61 | 2012-07-19 15:20:45 +0200 | [diff] [blame] | 48 | } |
Christian König | ca9cf61 | 2012-07-19 15:20:45 +0200 | [diff] [blame] | 49 | } |
| 50 | |
Marek Olšák | 508c1ca | 2014-12-07 16:02:07 +0100 | [diff] [blame] | 51 | static unsigned si_conv_pipe_prim(unsigned mode) |
Christian König | ca9cf61 | 2012-07-19 15:20:45 +0200 | [diff] [blame] | 52 | { |
| 53 | static const unsigned prim_conv[] = { |
| 54 | [PIPE_PRIM_POINTS] = V_008958_DI_PT_POINTLIST, |
| 55 | [PIPE_PRIM_LINES] = V_008958_DI_PT_LINELIST, |
| 56 | [PIPE_PRIM_LINE_LOOP] = V_008958_DI_PT_LINELOOP, |
| 57 | [PIPE_PRIM_LINE_STRIP] = V_008958_DI_PT_LINESTRIP, |
| 58 | [PIPE_PRIM_TRIANGLES] = V_008958_DI_PT_TRILIST, |
| 59 | [PIPE_PRIM_TRIANGLE_STRIP] = V_008958_DI_PT_TRISTRIP, |
| 60 | [PIPE_PRIM_TRIANGLE_FAN] = V_008958_DI_PT_TRIFAN, |
| 61 | [PIPE_PRIM_QUADS] = V_008958_DI_PT_QUADLIST, |
| 62 | [PIPE_PRIM_QUAD_STRIP] = V_008958_DI_PT_QUADSTRIP, |
| 63 | [PIPE_PRIM_POLYGON] = V_008958_DI_PT_POLYGON, |
Michel Dänzer | 2863071 | 2014-01-09 16:35:46 +0900 | [diff] [blame] | 64 | [PIPE_PRIM_LINES_ADJACENCY] = V_008958_DI_PT_LINELIST_ADJ, |
| 65 | [PIPE_PRIM_LINE_STRIP_ADJACENCY] = V_008958_DI_PT_LINESTRIP_ADJ, |
| 66 | [PIPE_PRIM_TRIANGLES_ADJACENCY] = V_008958_DI_PT_TRILIST_ADJ, |
Marek Olšák | db51ab6 | 2014-08-18 00:55:40 +0200 | [diff] [blame] | 67 | [PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY] = V_008958_DI_PT_TRISTRIP_ADJ, |
Marek Olšák | d9d0de4 | 2014-09-18 23:39:44 +0200 | [diff] [blame] | 68 | [PIPE_PRIM_PATCHES] = V_008958_DI_PT_PATCH, |
Marek Olšák | db51ab6 | 2014-08-18 00:55:40 +0200 | [diff] [blame] | 69 | [R600_PRIM_RECTANGLE_LIST] = V_008958_DI_PT_RECTLIST |
Christian König | ca9cf61 | 2012-07-19 15:20:45 +0200 | [diff] [blame] | 70 | }; |
Marek Olšák | 508c1ca | 2014-12-07 16:02:07 +0100 | [diff] [blame] | 71 | assert(mode < Elements(prim_conv)); |
| 72 | return prim_conv[mode]; |
Christian König | ca9cf61 | 2012-07-19 15:20:45 +0200 | [diff] [blame] | 73 | } |
| 74 | |
Andreas Hartmetz | b902298 | 2014-01-07 03:18:25 +0100 | [diff] [blame] | 75 | static unsigned si_conv_prim_to_gs_out(unsigned mode) |
Marek Olšák | e4c5d3e | 2013-08-18 03:05:34 +0200 | [diff] [blame] | 76 | { |
| 77 | static const int prim_conv[] = { |
| 78 | [PIPE_PRIM_POINTS] = V_028A6C_OUTPRIM_TYPE_POINTLIST, |
| 79 | [PIPE_PRIM_LINES] = V_028A6C_OUTPRIM_TYPE_LINESTRIP, |
| 80 | [PIPE_PRIM_LINE_LOOP] = V_028A6C_OUTPRIM_TYPE_LINESTRIP, |
| 81 | [PIPE_PRIM_LINE_STRIP] = V_028A6C_OUTPRIM_TYPE_LINESTRIP, |
| 82 | [PIPE_PRIM_TRIANGLES] = V_028A6C_OUTPRIM_TYPE_TRISTRIP, |
| 83 | [PIPE_PRIM_TRIANGLE_STRIP] = V_028A6C_OUTPRIM_TYPE_TRISTRIP, |
| 84 | [PIPE_PRIM_TRIANGLE_FAN] = V_028A6C_OUTPRIM_TYPE_TRISTRIP, |
| 85 | [PIPE_PRIM_QUADS] = V_028A6C_OUTPRIM_TYPE_TRISTRIP, |
| 86 | [PIPE_PRIM_QUAD_STRIP] = V_028A6C_OUTPRIM_TYPE_TRISTRIP, |
| 87 | [PIPE_PRIM_POLYGON] = V_028A6C_OUTPRIM_TYPE_TRISTRIP, |
| 88 | [PIPE_PRIM_LINES_ADJACENCY] = V_028A6C_OUTPRIM_TYPE_LINESTRIP, |
| 89 | [PIPE_PRIM_LINE_STRIP_ADJACENCY] = V_028A6C_OUTPRIM_TYPE_LINESTRIP, |
| 90 | [PIPE_PRIM_TRIANGLES_ADJACENCY] = V_028A6C_OUTPRIM_TYPE_TRISTRIP, |
Marek Olšák | db51ab6 | 2014-08-18 00:55:40 +0200 | [diff] [blame] | 91 | [PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY] = V_028A6C_OUTPRIM_TYPE_TRISTRIP, |
Marek Olšák | d9d0de4 | 2014-09-18 23:39:44 +0200 | [diff] [blame] | 92 | [PIPE_PRIM_PATCHES] = V_028A6C_OUTPRIM_TYPE_POINTLIST, |
Marek Olšák | db51ab6 | 2014-08-18 00:55:40 +0200 | [diff] [blame] | 93 | [R600_PRIM_RECTANGLE_LIST] = V_028A6C_OUTPRIM_TYPE_TRISTRIP |
Marek Olšák | e4c5d3e | 2013-08-18 03:05:34 +0200 | [diff] [blame] | 94 | }; |
| 95 | assert(mode < Elements(prim_conv)); |
| 96 | |
| 97 | return prim_conv[mode]; |
| 98 | } |
| 99 | |
Marek Olšák | 74c1001 | 2015-02-22 18:01:18 +0100 | [diff] [blame] | 100 | /** |
| 101 | * This calculates the LDS size for tessellation shaders (VS, TCS, TES). |
| 102 | * LS.LDS_SIZE is shared by all 3 shader stages. |
| 103 | * |
| 104 | * The information about LDS and other non-compile-time parameters is then |
| 105 | * written to userdata SGPRs. |
| 106 | */ |
| 107 | static void si_emit_derived_tess_state(struct si_context *sctx, |
| 108 | const struct pipe_draw_info *info, |
| 109 | unsigned *num_patches) |
| 110 | { |
| 111 | struct radeon_winsys_cs *cs = sctx->b.rings.gfx.cs; |
Marek Olšák | 9b54ce3 | 2015-10-07 01:48:18 +0200 | [diff] [blame] | 112 | struct si_shader_ctx_state *ls = &sctx->vs_shader; |
Marek Olšák | 74c1001 | 2015-02-22 18:01:18 +0100 | [diff] [blame] | 113 | /* The TES pointer will only be used for sctx->last_tcs. |
| 114 | * It would be wrong to think that TCS = TES. */ |
| 115 | struct si_shader_selector *tcs = |
Marek Olšák | 9b54ce3 | 2015-10-07 01:48:18 +0200 | [diff] [blame] | 116 | sctx->tcs_shader.cso ? sctx->tcs_shader.cso : sctx->tes_shader.cso; |
Marek Olšák | 74c1001 | 2015-02-22 18:01:18 +0100 | [diff] [blame] | 117 | unsigned tes_sh_base = sctx->shader_userdata.sh_base[PIPE_SHADER_TESS_EVAL]; |
| 118 | unsigned num_tcs_input_cp = info->vertices_per_patch; |
| 119 | unsigned num_tcs_output_cp, num_tcs_inputs, num_tcs_outputs; |
| 120 | unsigned num_tcs_patch_outputs; |
| 121 | unsigned input_vertex_size, output_vertex_size, pervertex_output_patch_size; |
| 122 | unsigned input_patch_size, output_patch_size, output_patch0_offset; |
| 123 | unsigned perpatch_output_offset, lds_size, ls_rsrc2; |
| 124 | unsigned tcs_in_layout, tcs_out_layout, tcs_out_offsets; |
| 125 | |
| 126 | *num_patches = 1; /* TODO: calculate this */ |
| 127 | |
| 128 | if (sctx->last_ls == ls->current && |
| 129 | sctx->last_tcs == tcs && |
| 130 | sctx->last_tes_sh_base == tes_sh_base && |
| 131 | sctx->last_num_tcs_input_cp == num_tcs_input_cp) |
| 132 | return; |
| 133 | |
| 134 | sctx->last_ls = ls->current; |
| 135 | sctx->last_tcs = tcs; |
| 136 | sctx->last_tes_sh_base = tes_sh_base; |
| 137 | sctx->last_num_tcs_input_cp = num_tcs_input_cp; |
| 138 | |
| 139 | /* This calculates how shader inputs and outputs among VS, TCS, and TES |
| 140 | * are laid out in LDS. */ |
Marek Olšák | 9b54ce3 | 2015-10-07 01:48:18 +0200 | [diff] [blame] | 141 | num_tcs_inputs = util_last_bit64(ls->cso->outputs_written); |
Marek Olšák | 74c1001 | 2015-02-22 18:01:18 +0100 | [diff] [blame] | 142 | |
Marek Olšák | 9b54ce3 | 2015-10-07 01:48:18 +0200 | [diff] [blame] | 143 | if (sctx->tcs_shader.cso) { |
Marek Olšák | 74c1001 | 2015-02-22 18:01:18 +0100 | [diff] [blame] | 144 | num_tcs_outputs = util_last_bit64(tcs->outputs_written); |
| 145 | num_tcs_output_cp = tcs->info.properties[TGSI_PROPERTY_TCS_VERTICES_OUT]; |
| 146 | num_tcs_patch_outputs = util_last_bit64(tcs->patch_outputs_written); |
| 147 | } else { |
| 148 | /* No TCS. Route varyings from LS to TES. */ |
| 149 | num_tcs_outputs = num_tcs_inputs; |
| 150 | num_tcs_output_cp = num_tcs_input_cp; |
| 151 | num_tcs_patch_outputs = 2; /* TESSINNER + TESSOUTER */ |
| 152 | } |
| 153 | |
| 154 | input_vertex_size = num_tcs_inputs * 16; |
| 155 | output_vertex_size = num_tcs_outputs * 16; |
| 156 | |
| 157 | input_patch_size = num_tcs_input_cp * input_vertex_size; |
| 158 | |
| 159 | pervertex_output_patch_size = num_tcs_output_cp * output_vertex_size; |
| 160 | output_patch_size = pervertex_output_patch_size + num_tcs_patch_outputs * 16; |
| 161 | |
Marek Olšák | 9b54ce3 | 2015-10-07 01:48:18 +0200 | [diff] [blame] | 162 | output_patch0_offset = sctx->tcs_shader.cso ? input_patch_size * *num_patches : 0; |
Marek Olšák | 74c1001 | 2015-02-22 18:01:18 +0100 | [diff] [blame] | 163 | perpatch_output_offset = output_patch0_offset + pervertex_output_patch_size; |
| 164 | |
| 165 | lds_size = output_patch0_offset + output_patch_size * *num_patches; |
| 166 | ls_rsrc2 = ls->current->ls_rsrc2; |
| 167 | |
| 168 | if (sctx->b.chip_class >= CIK) { |
| 169 | assert(lds_size <= 65536); |
| 170 | ls_rsrc2 |= S_00B52C_LDS_SIZE(align(lds_size, 512) / 512); |
| 171 | } else { |
| 172 | assert(lds_size <= 32768); |
| 173 | ls_rsrc2 |= S_00B52C_LDS_SIZE(align(lds_size, 256) / 256); |
| 174 | } |
| 175 | |
| 176 | /* Due to a hw bug, RSRC2_LS must be written twice with another |
| 177 | * LS register written in between. */ |
| 178 | if (sctx->b.chip_class == CIK && sctx->b.family != CHIP_HAWAII) |
Marek Olšák | d2e63ac | 2015-08-30 01:54:00 +0200 | [diff] [blame] | 179 | radeon_set_sh_reg(cs, R_00B52C_SPI_SHADER_PGM_RSRC2_LS, ls_rsrc2); |
| 180 | radeon_set_sh_reg_seq(cs, R_00B528_SPI_SHADER_PGM_RSRC1_LS, 2); |
Marek Olšák | 74c1001 | 2015-02-22 18:01:18 +0100 | [diff] [blame] | 181 | radeon_emit(cs, ls->current->ls_rsrc1); |
| 182 | radeon_emit(cs, ls_rsrc2); |
| 183 | |
| 184 | /* Compute userdata SGPRs. */ |
| 185 | assert(((input_vertex_size / 4) & ~0xff) == 0); |
| 186 | assert(((output_vertex_size / 4) & ~0xff) == 0); |
| 187 | assert(((input_patch_size / 4) & ~0x1fff) == 0); |
| 188 | assert(((output_patch_size / 4) & ~0x1fff) == 0); |
| 189 | assert(((output_patch0_offset / 16) & ~0xffff) == 0); |
| 190 | assert(((perpatch_output_offset / 16) & ~0xffff) == 0); |
| 191 | assert(num_tcs_input_cp <= 32); |
| 192 | assert(num_tcs_output_cp <= 32); |
| 193 | |
| 194 | tcs_in_layout = (input_patch_size / 4) | |
| 195 | ((input_vertex_size / 4) << 13); |
| 196 | tcs_out_layout = (output_patch_size / 4) | |
| 197 | ((output_vertex_size / 4) << 13); |
| 198 | tcs_out_offsets = (output_patch0_offset / 16) | |
| 199 | ((perpatch_output_offset / 16) << 16); |
| 200 | |
| 201 | /* Set them for LS. */ |
Marek Olšák | d2e63ac | 2015-08-30 01:54:00 +0200 | [diff] [blame] | 202 | radeon_set_sh_reg(cs, |
Marek Olšák | 74c1001 | 2015-02-22 18:01:18 +0100 | [diff] [blame] | 203 | R_00B530_SPI_SHADER_USER_DATA_LS_0 + SI_SGPR_LS_OUT_LAYOUT * 4, |
| 204 | tcs_in_layout); |
| 205 | |
| 206 | /* Set them for TCS. */ |
Marek Olšák | d2e63ac | 2015-08-30 01:54:00 +0200 | [diff] [blame] | 207 | radeon_set_sh_reg_seq(cs, |
Marek Olšák | 74c1001 | 2015-02-22 18:01:18 +0100 | [diff] [blame] | 208 | R_00B430_SPI_SHADER_USER_DATA_HS_0 + SI_SGPR_TCS_OUT_OFFSETS * 4, 3); |
| 209 | radeon_emit(cs, tcs_out_offsets); |
| 210 | radeon_emit(cs, tcs_out_layout | (num_tcs_input_cp << 26)); |
| 211 | radeon_emit(cs, tcs_in_layout); |
| 212 | |
| 213 | /* Set them for TES. */ |
Marek Olšák | d2e63ac | 2015-08-30 01:54:00 +0200 | [diff] [blame] | 214 | radeon_set_sh_reg_seq(cs, tes_sh_base + SI_SGPR_TCS_OUT_OFFSETS * 4, 2); |
Marek Olšák | 74c1001 | 2015-02-22 18:01:18 +0100 | [diff] [blame] | 215 | radeon_emit(cs, tcs_out_offsets); |
| 216 | radeon_emit(cs, tcs_out_layout | (num_tcs_output_cp << 26)); |
| 217 | } |
| 218 | |
Marek Olšák | 94e474f | 2014-08-15 16:32:03 +0200 | [diff] [blame] | 219 | static unsigned si_get_ia_multi_vgt_param(struct si_context *sctx, |
Marek Olšák | 09d02fa | 2015-02-22 18:06:34 +0100 | [diff] [blame] | 220 | const struct pipe_draw_info *info, |
| 221 | unsigned num_patches) |
Marek Olšák | 94e474f | 2014-08-15 16:32:03 +0200 | [diff] [blame] | 222 | { |
| 223 | struct si_state_rasterizer *rs = sctx->queued.named.rasterizer; |
| 224 | unsigned prim = info->mode; |
Marek Olšák | f62f882 | 2014-08-18 23:14:34 +0200 | [diff] [blame] | 225 | unsigned primgroup_size = 128; /* recommended without a GS */ |
Marek Olšák | 94e474f | 2014-08-15 16:32:03 +0200 | [diff] [blame] | 226 | |
| 227 | /* SWITCH_ON_EOP(0) is always preferable. */ |
| 228 | bool wd_switch_on_eop = false; |
| 229 | bool ia_switch_on_eop = false; |
Marek Olšák | 09d02fa | 2015-02-22 18:06:34 +0100 | [diff] [blame] | 230 | bool ia_switch_on_eoi = false; |
Marek Olšák | 4be7ff5 | 2014-08-15 22:45:10 +0200 | [diff] [blame] | 231 | bool partial_vs_wave = false; |
Marek Olšák | 09d02fa | 2015-02-22 18:06:34 +0100 | [diff] [blame] | 232 | bool partial_es_wave = false; |
Marek Olšák | 94e474f | 2014-08-15 16:32:03 +0200 | [diff] [blame] | 233 | |
Marek Olšák | 9b54ce3 | 2015-10-07 01:48:18 +0200 | [diff] [blame] | 234 | if (sctx->gs_shader.cso) |
Marek Olšák | f62f882 | 2014-08-18 23:14:34 +0200 | [diff] [blame] | 235 | primgroup_size = 64; /* recommended with a GS */ |
| 236 | |
Marek Olšák | 9b54ce3 | 2015-10-07 01:48:18 +0200 | [diff] [blame] | 237 | if (sctx->tes_shader.cso) { |
Marek Olšák | 09d02fa | 2015-02-22 18:06:34 +0100 | [diff] [blame] | 238 | unsigned num_cp_out = |
Marek Olšák | 9b54ce3 | 2015-10-07 01:48:18 +0200 | [diff] [blame] | 239 | sctx->tcs_shader.cso ? |
| 240 | sctx->tcs_shader.cso->info.properties[TGSI_PROPERTY_TCS_VERTICES_OUT] : |
Marek Olšák | 09d02fa | 2015-02-22 18:06:34 +0100 | [diff] [blame] | 241 | info->vertices_per_patch; |
| 242 | unsigned max_size = 256 / MAX2(info->vertices_per_patch, num_cp_out); |
| 243 | |
| 244 | primgroup_size = MIN2(primgroup_size, max_size); |
| 245 | |
| 246 | /* primgroup_size must be set to a multiple of NUM_PATCHES */ |
| 247 | primgroup_size = (primgroup_size / num_patches) * num_patches; |
| 248 | |
| 249 | /* SWITCH_ON_EOI must be set if PrimID is used. |
| 250 | * If SWITCH_ON_EOI is set, PARTIAL_ES_WAVE must be set too. */ |
Marek Olšák | 9b54ce3 | 2015-10-07 01:48:18 +0200 | [diff] [blame] | 251 | if ((sctx->tcs_shader.cso && sctx->tcs_shader.cso->info.uses_primid) || |
| 252 | sctx->tes_shader.cso->info.uses_primid) { |
Marek Olšák | 09d02fa | 2015-02-22 18:06:34 +0100 | [diff] [blame] | 253 | ia_switch_on_eoi = true; |
| 254 | partial_es_wave = true; |
| 255 | } |
| 256 | |
| 257 | /* Bug with tessellation and GS on Bonaire and older 2 SE chips. */ |
| 258 | if ((sctx->b.family == CHIP_TAHITI || |
| 259 | sctx->b.family == CHIP_PITCAIRN || |
| 260 | sctx->b.family == CHIP_BONAIRE) && |
Marek Olšák | 9b54ce3 | 2015-10-07 01:48:18 +0200 | [diff] [blame] | 261 | sctx->gs_shader.cso) |
Marek Olšák | 09d02fa | 2015-02-22 18:06:34 +0100 | [diff] [blame] | 262 | partial_vs_wave = true; |
| 263 | } |
| 264 | |
Marek Olšák | 94e474f | 2014-08-15 16:32:03 +0200 | [diff] [blame] | 265 | /* This is a hardware requirement. */ |
| 266 | if ((rs && rs->line_stipple_enable) || |
| 267 | (sctx->b.screen->debug_flags & DBG_SWITCH_ON_EOP)) { |
| 268 | ia_switch_on_eop = true; |
| 269 | wd_switch_on_eop = true; |
| 270 | } |
| 271 | |
Marek Olšák | 4be7ff5 | 2014-08-15 22:45:10 +0200 | [diff] [blame] | 272 | if (sctx->b.streamout.streamout_enabled || |
| 273 | sctx->b.streamout.prims_gen_query_enabled) |
| 274 | partial_vs_wave = true; |
| 275 | |
Marek Olšák | 94e474f | 2014-08-15 16:32:03 +0200 | [diff] [blame] | 276 | if (sctx->b.chip_class >= CIK) { |
| 277 | /* WD_SWITCH_ON_EOP has no effect on GPUs with less than |
| 278 | * 4 shader engines. Set 1 to pass the assertion below. |
| 279 | * The other cases are hardware requirements. */ |
| 280 | if (sctx->b.screen->info.max_se < 4 || |
| 281 | prim == PIPE_PRIM_POLYGON || |
| 282 | prim == PIPE_PRIM_LINE_LOOP || |
| 283 | prim == PIPE_PRIM_TRIANGLE_FAN || |
| 284 | prim == PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY || |
| 285 | info->primitive_restart) |
| 286 | wd_switch_on_eop = true; |
| 287 | |
| 288 | /* Hawaii hangs if instancing is enabled and WD_SWITCH_ON_EOP is 0. |
| 289 | * We don't know that for indirect drawing, so treat it as |
| 290 | * always problematic. */ |
| 291 | if (sctx->b.family == CHIP_HAWAII && |
| 292 | (info->indirect || info->instance_count > 1)) |
| 293 | wd_switch_on_eop = true; |
| 294 | |
Marek Olšák | d3f4f6b | 2015-06-24 11:58:50 +0200 | [diff] [blame] | 295 | /* USE_OPAQUE doesn't work when WD_SWITCH_ON_EOP is 0. */ |
| 296 | if (info->count_from_stream_output) |
| 297 | wd_switch_on_eop = true; |
| 298 | |
Marek Olšák | 94e474f | 2014-08-15 16:32:03 +0200 | [diff] [blame] | 299 | /* If the WD switch is false, the IA switch must be false too. */ |
| 300 | assert(wd_switch_on_eop || !ia_switch_on_eop); |
| 301 | } |
| 302 | |
Marek Olšák | 09d02fa | 2015-02-22 18:06:34 +0100 | [diff] [blame] | 303 | /* Hw bug with single-primitive instances and SWITCH_ON_EOI |
| 304 | * on multi-SE chips. */ |
| 305 | if (sctx->b.screen->info.max_se >= 2 && ia_switch_on_eoi && |
| 306 | (info->indirect || |
| 307 | (info->instance_count > 1 && |
| 308 | u_prims_for_vertices(info->mode, info->count) <= 1))) |
| 309 | sctx->b.flags |= SI_CONTEXT_VGT_FLUSH; |
| 310 | |
| 311 | /* Instancing bug on 2 SE chips. */ |
| 312 | if (sctx->b.screen->info.max_se == 2 && ia_switch_on_eoi && |
| 313 | (info->indirect || info->instance_count > 1)) |
| 314 | partial_vs_wave = true; |
| 315 | |
Marek Olšák | 94e474f | 2014-08-15 16:32:03 +0200 | [diff] [blame] | 316 | return S_028AA8_SWITCH_ON_EOP(ia_switch_on_eop) | |
Marek Olšák | 09d02fa | 2015-02-22 18:06:34 +0100 | [diff] [blame] | 317 | S_028AA8_SWITCH_ON_EOI(ia_switch_on_eoi) | |
Marek Olšák | 4be7ff5 | 2014-08-15 22:45:10 +0200 | [diff] [blame] | 318 | S_028AA8_PARTIAL_VS_WAVE_ON(partial_vs_wave) | |
Marek Olšák | 09d02fa | 2015-02-22 18:06:34 +0100 | [diff] [blame] | 319 | S_028AA8_PARTIAL_ES_WAVE_ON(partial_es_wave) | |
Marek Olšák | 94e474f | 2014-08-15 16:32:03 +0200 | [diff] [blame] | 320 | S_028AA8_PRIMGROUP_SIZE(primgroup_size - 1) | |
Marek Olšák | 2d1952e | 2015-04-16 20:44:54 +0200 | [diff] [blame] | 321 | S_028AA8_WD_SWITCH_ON_EOP(sctx->b.chip_class >= CIK ? wd_switch_on_eop : 0) | |
| 322 | S_028AA8_MAX_PRIMGRP_IN_WAVE(sctx->b.chip_class >= VI ? 2 : 0); |
Marek Olšák | 94e474f | 2014-08-15 16:32:03 +0200 | [diff] [blame] | 323 | } |
| 324 | |
Marek Olšák | 3344699 | 2015-02-22 18:07:51 +0100 | [diff] [blame] | 325 | static unsigned si_get_ls_hs_config(struct si_context *sctx, |
| 326 | const struct pipe_draw_info *info, |
| 327 | unsigned num_patches) |
| 328 | { |
| 329 | unsigned num_output_cp; |
| 330 | |
Marek Olšák | 9b54ce3 | 2015-10-07 01:48:18 +0200 | [diff] [blame] | 331 | if (!sctx->tes_shader.cso) |
Marek Olšák | 3344699 | 2015-02-22 18:07:51 +0100 | [diff] [blame] | 332 | return 0; |
| 333 | |
Marek Olšák | 9b54ce3 | 2015-10-07 01:48:18 +0200 | [diff] [blame] | 334 | num_output_cp = sctx->tcs_shader.cso ? |
| 335 | sctx->tcs_shader.cso->info.properties[TGSI_PROPERTY_TCS_VERTICES_OUT] : |
Marek Olšák | 3344699 | 2015-02-22 18:07:51 +0100 | [diff] [blame] | 336 | info->vertices_per_patch; |
| 337 | |
| 338 | return S_028B58_NUM_PATCHES(num_patches) | |
| 339 | S_028B58_HS_NUM_INPUT_CP(info->vertices_per_patch) | |
| 340 | S_028B58_HS_NUM_OUTPUT_CP(num_output_cp); |
| 341 | } |
| 342 | |
Marek Olšák | dc39413 | 2015-03-15 20:13:52 +0100 | [diff] [blame] | 343 | static void si_emit_scratch_reloc(struct si_context *sctx) |
| 344 | { |
| 345 | struct radeon_winsys_cs *cs = sctx->b.rings.gfx.cs; |
| 346 | |
| 347 | if (!sctx->emit_scratch_reloc) |
| 348 | return; |
| 349 | |
Marek Olšák | d2e63ac | 2015-08-30 01:54:00 +0200 | [diff] [blame] | 350 | radeon_set_context_reg(cs, R_0286E8_SPI_TMPRING_SIZE, |
Marek Olšák | dc39413 | 2015-03-15 20:13:52 +0100 | [diff] [blame] | 351 | sctx->spi_tmpring_size); |
| 352 | |
| 353 | if (sctx->scratch_buffer) { |
Marek Olšák | 7ff2991 | 2015-08-30 02:04:37 +0200 | [diff] [blame] | 354 | radeon_add_to_buffer_list(&sctx->b, &sctx->b.rings.gfx, |
Marek Olšák | dc39413 | 2015-03-15 20:13:52 +0100 | [diff] [blame] | 355 | sctx->scratch_buffer, RADEON_USAGE_READWRITE, |
Marek Olšák | 2edb060 | 2015-09-26 23:18:55 +0200 | [diff] [blame] | 356 | RADEON_PRIO_SCRATCH_BUFFER); |
Marek Olšák | dc39413 | 2015-03-15 20:13:52 +0100 | [diff] [blame] | 357 | |
| 358 | } |
| 359 | sctx->emit_scratch_reloc = false; |
| 360 | } |
| 361 | |
Marek Olšák | 1fe7ba8 | 2015-01-31 20:09:46 +0100 | [diff] [blame] | 362 | /* rast_prim is the primitive type after GS. */ |
Marek Olšák | fdf2c04 | 2015-02-22 17:42:20 +0100 | [diff] [blame] | 363 | static void si_emit_rasterizer_prim_state(struct si_context *sctx) |
Marek Olšák | ca7f1cf | 2014-12-07 16:40:09 +0100 | [diff] [blame] | 364 | { |
| 365 | struct radeon_winsys_cs *cs = sctx->b.rings.gfx.cs; |
Marek Olšák | fdf2c04 | 2015-02-22 17:42:20 +0100 | [diff] [blame] | 366 | unsigned rast_prim = sctx->current_rast_prim; |
Marek Olšák | 1f4bb38 | 2015-03-15 19:21:31 +0100 | [diff] [blame] | 367 | struct si_state_rasterizer *rs = sctx->emitted.named.rasterizer; |
Marek Olšák | ca7f1cf | 2014-12-07 16:40:09 +0100 | [diff] [blame] | 368 | |
Marek Olšák | 567c8d7 | 2015-03-15 19:24:13 +0100 | [diff] [blame] | 369 | /* Skip this if not rendering lines. */ |
| 370 | if (rast_prim != PIPE_PRIM_LINES && |
| 371 | rast_prim != PIPE_PRIM_LINE_LOOP && |
| 372 | rast_prim != PIPE_PRIM_LINE_STRIP && |
| 373 | rast_prim != PIPE_PRIM_LINES_ADJACENCY && |
| 374 | rast_prim != PIPE_PRIM_LINE_STRIP_ADJACENCY) |
| 375 | return; |
| 376 | |
Marek Olšák | 1f4bb38 | 2015-03-15 19:21:31 +0100 | [diff] [blame] | 377 | if (rast_prim == sctx->last_rast_prim && |
| 378 | rs->pa_sc_line_stipple == sctx->last_sc_line_stipple) |
Marek Olšák | 3291eed | 2014-12-08 13:35:36 +0100 | [diff] [blame] | 379 | return; |
| 380 | |
Marek Olšák | d2e63ac | 2015-08-30 01:54:00 +0200 | [diff] [blame] | 381 | radeon_set_context_reg(cs, R_028A0C_PA_SC_LINE_STIPPLE, |
Marek Olšák | 1f4bb38 | 2015-03-15 19:21:31 +0100 | [diff] [blame] | 382 | rs->pa_sc_line_stipple | |
Marek Olšák | 1fe7ba8 | 2015-01-31 20:09:46 +0100 | [diff] [blame] | 383 | S_028A0C_AUTO_RESET_CNTL(rast_prim == PIPE_PRIM_LINES ? 1 : |
| 384 | rast_prim == PIPE_PRIM_LINE_STRIP ? 2 : 0)); |
Marek Olšák | ca7f1cf | 2014-12-07 16:40:09 +0100 | [diff] [blame] | 385 | |
Marek Olšák | 1fe7ba8 | 2015-01-31 20:09:46 +0100 | [diff] [blame] | 386 | sctx->last_rast_prim = rast_prim; |
Marek Olšák | 1f4bb38 | 2015-03-15 19:21:31 +0100 | [diff] [blame] | 387 | sctx->last_sc_line_stipple = rs->pa_sc_line_stipple; |
Marek Olšák | ca7f1cf | 2014-12-07 16:40:09 +0100 | [diff] [blame] | 388 | } |
| 389 | |
| 390 | static void si_emit_draw_registers(struct si_context *sctx, |
Marek Olšák | fdf2c04 | 2015-02-22 17:42:20 +0100 | [diff] [blame] | 391 | const struct pipe_draw_info *info) |
Marek Olšák | ca7f1cf | 2014-12-07 16:40:09 +0100 | [diff] [blame] | 392 | { |
| 393 | struct radeon_winsys_cs *cs = sctx->b.rings.gfx.cs; |
| 394 | unsigned prim = si_conv_pipe_prim(info->mode); |
Marek Olšák | fdf2c04 | 2015-02-22 17:42:20 +0100 | [diff] [blame] | 395 | unsigned gs_out_prim = si_conv_prim_to_gs_out(sctx->current_rast_prim); |
Marek Olšák | 3344699 | 2015-02-22 18:07:51 +0100 | [diff] [blame] | 396 | unsigned ia_multi_vgt_param, ls_hs_config, num_patches = 0; |
Marek Olšák | ca7f1cf | 2014-12-07 16:40:09 +0100 | [diff] [blame] | 397 | |
Marek Olšák | 9b54ce3 | 2015-10-07 01:48:18 +0200 | [diff] [blame] | 398 | if (sctx->tes_shader.cso) |
Marek Olšák | 74c1001 | 2015-02-22 18:01:18 +0100 | [diff] [blame] | 399 | si_emit_derived_tess_state(sctx, info, &num_patches); |
| 400 | |
Marek Olšák | 09d02fa | 2015-02-22 18:06:34 +0100 | [diff] [blame] | 401 | ia_multi_vgt_param = si_get_ia_multi_vgt_param(sctx, info, num_patches); |
Marek Olšák | 3344699 | 2015-02-22 18:07:51 +0100 | [diff] [blame] | 402 | ls_hs_config = si_get_ls_hs_config(sctx, info, num_patches); |
Marek Olšák | 09d02fa | 2015-02-22 18:06:34 +0100 | [diff] [blame] | 403 | |
Marek Olšák | ca7f1cf | 2014-12-07 16:40:09 +0100 | [diff] [blame] | 404 | /* Draw state. */ |
Marek Olšák | 834bee4 | 2014-12-07 20:23:56 +0100 | [diff] [blame] | 405 | if (prim != sctx->last_prim || |
Marek Olšák | 3344699 | 2015-02-22 18:07:51 +0100 | [diff] [blame] | 406 | ia_multi_vgt_param != sctx->last_multi_vgt_param || |
| 407 | ls_hs_config != sctx->last_ls_hs_config) { |
Marek Olšák | 834bee4 | 2014-12-07 20:23:56 +0100 | [diff] [blame] | 408 | if (sctx->b.chip_class >= CIK) { |
| 409 | radeon_emit(cs, PKT3(PKT3_DRAW_PREAMBLE, 2, 0)); |
| 410 | radeon_emit(cs, prim); /* VGT_PRIMITIVE_TYPE */ |
| 411 | radeon_emit(cs, ia_multi_vgt_param); /* IA_MULTI_VGT_PARAM */ |
Marek Olšák | 3344699 | 2015-02-22 18:07:51 +0100 | [diff] [blame] | 412 | radeon_emit(cs, ls_hs_config); /* VGT_LS_HS_CONFIG */ |
Marek Olšák | 834bee4 | 2014-12-07 20:23:56 +0100 | [diff] [blame] | 413 | } else { |
Marek Olšák | d2e63ac | 2015-08-30 01:54:00 +0200 | [diff] [blame] | 414 | radeon_set_config_reg(cs, R_008958_VGT_PRIMITIVE_TYPE, prim); |
| 415 | radeon_set_context_reg(cs, R_028AA8_IA_MULTI_VGT_PARAM, ia_multi_vgt_param); |
| 416 | radeon_set_context_reg(cs, R_028B58_VGT_LS_HS_CONFIG, ls_hs_config); |
Marek Olšák | 834bee4 | 2014-12-07 20:23:56 +0100 | [diff] [blame] | 417 | } |
| 418 | sctx->last_prim = prim; |
| 419 | sctx->last_multi_vgt_param = ia_multi_vgt_param; |
Marek Olšák | 3344699 | 2015-02-22 18:07:51 +0100 | [diff] [blame] | 420 | sctx->last_ls_hs_config = ls_hs_config; |
Marek Olšák | ca7f1cf | 2014-12-07 16:40:09 +0100 | [diff] [blame] | 421 | } |
| 422 | |
Marek Olšák | 6fde194 | 2014-12-07 20:15:49 +0100 | [diff] [blame] | 423 | if (gs_out_prim != sctx->last_gs_out_prim) { |
Marek Olšák | d2e63ac | 2015-08-30 01:54:00 +0200 | [diff] [blame] | 424 | radeon_set_context_reg(cs, R_028A6C_VGT_GS_OUT_PRIM_TYPE, gs_out_prim); |
Marek Olšák | 6fde194 | 2014-12-07 20:15:49 +0100 | [diff] [blame] | 425 | sctx->last_gs_out_prim = gs_out_prim; |
| 426 | } |
Marek Olšák | 3435013 | 2014-12-07 20:14:41 +0100 | [diff] [blame] | 427 | |
| 428 | /* Primitive restart. */ |
| 429 | if (info->primitive_restart != sctx->last_primitive_restart_en) { |
Marek Olšák | d2e63ac | 2015-08-30 01:54:00 +0200 | [diff] [blame] | 430 | radeon_set_context_reg(cs, R_028A94_VGT_MULTI_PRIM_IB_RESET_EN, info->primitive_restart); |
Marek Olšák | 3435013 | 2014-12-07 20:14:41 +0100 | [diff] [blame] | 431 | sctx->last_primitive_restart_en = info->primitive_restart; |
| 432 | |
| 433 | if (info->primitive_restart && |
| 434 | (info->restart_index != sctx->last_restart_index || |
| 435 | sctx->last_restart_index == SI_RESTART_INDEX_UNKNOWN)) { |
Marek Olšák | d2e63ac | 2015-08-30 01:54:00 +0200 | [diff] [blame] | 436 | radeon_set_context_reg(cs, R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX, |
Marek Olšák | 3435013 | 2014-12-07 20:14:41 +0100 | [diff] [blame] | 437 | info->restart_index); |
| 438 | sctx->last_restart_index = info->restart_index; |
| 439 | } |
| 440 | } |
Marek Olšák | ca7f1cf | 2014-12-07 16:40:09 +0100 | [diff] [blame] | 441 | } |
| 442 | |
Marek Olšák | 384213c | 2014-12-07 15:52:15 +0100 | [diff] [blame] | 443 | static void si_emit_draw_packets(struct si_context *sctx, |
| 444 | const struct pipe_draw_info *info, |
| 445 | const struct pipe_index_buffer *ib) |
Christian König | 9f5ff59 | 2012-08-03 10:26:01 +0200 | [diff] [blame] | 446 | { |
Marek Olšák | 384213c | 2014-12-07 15:52:15 +0100 | [diff] [blame] | 447 | struct radeon_winsys_cs *cs = sctx->b.rings.gfx.cs; |
Marek Olšák | 3ce91c7 | 2014-09-15 23:34:28 +0200 | [diff] [blame] | 448 | unsigned sh_base_reg = sctx->shader_userdata.sh_base[PIPE_SHADER_VERTEX]; |
Christian König | 9f5ff59 | 2012-08-03 10:26:01 +0200 | [diff] [blame] | 449 | |
Marek Olšák | 9d16e70 | 2013-08-26 18:17:09 +0200 | [diff] [blame] | 450 | if (info->count_from_stream_output) { |
| 451 | struct r600_so_target *t = |
| 452 | (struct r600_so_target*)info->count_from_stream_output; |
Marek Olšák | 1c03a69 | 2014-08-06 22:29:27 +0200 | [diff] [blame] | 453 | uint64_t va = t->buf_filled_size->gpu_address + |
| 454 | t->buf_filled_size_offset; |
Marek Olšák | 9d16e70 | 2013-08-26 18:17:09 +0200 | [diff] [blame] | 455 | |
Marek Olšák | d2e63ac | 2015-08-30 01:54:00 +0200 | [diff] [blame] | 456 | radeon_set_context_reg(cs, R_028B30_VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE, |
Marek Olšák | 384213c | 2014-12-07 15:52:15 +0100 | [diff] [blame] | 457 | t->stride_in_dw); |
Marek Olšák | 9d16e70 | 2013-08-26 18:17:09 +0200 | [diff] [blame] | 458 | |
Marek Olšák | 384213c | 2014-12-07 15:52:15 +0100 | [diff] [blame] | 459 | radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0)); |
| 460 | radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_MEM) | |
| 461 | COPY_DATA_DST_SEL(COPY_DATA_REG) | |
| 462 | COPY_DATA_WR_CONFIRM); |
| 463 | radeon_emit(cs, va); /* src address lo */ |
| 464 | radeon_emit(cs, va >> 32); /* src address hi */ |
| 465 | radeon_emit(cs, R_028B2C_VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE >> 2); |
| 466 | radeon_emit(cs, 0); /* unused */ |
| 467 | |
Marek Olšák | 7ff2991 | 2015-08-30 02:04:37 +0200 | [diff] [blame] | 468 | radeon_add_to_buffer_list(&sctx->b, &sctx->b.rings.gfx, |
Marek Olšák | 384213c | 2014-12-07 15:52:15 +0100 | [diff] [blame] | 469 | t->buf_filled_size, RADEON_USAGE_READ, |
Marek Olšák | 2edb060 | 2015-09-26 23:18:55 +0200 | [diff] [blame] | 470 | RADEON_PRIO_SO_FILLED_SIZE); |
Marek Olšák | 9d16e70 | 2013-08-26 18:17:09 +0200 | [diff] [blame] | 471 | } |
| 472 | |
Christian König | 9f5ff59 | 2012-08-03 10:26:01 +0200 | [diff] [blame] | 473 | /* draw packet */ |
Marek Olšák | 384213c | 2014-12-07 15:52:15 +0100 | [diff] [blame] | 474 | if (info->indexed) { |
| 475 | radeon_emit(cs, PKT3(PKT3_INDEX_TYPE, 0, 0)); |
| 476 | |
Marek Olšák | 2d1952e | 2015-04-16 20:44:54 +0200 | [diff] [blame] | 477 | /* index type */ |
| 478 | switch (ib->index_size) { |
| 479 | case 1: |
| 480 | radeon_emit(cs, V_028A7C_VGT_INDEX_8); |
| 481 | break; |
| 482 | case 2: |
| 483 | radeon_emit(cs, V_028A7C_VGT_INDEX_16 | |
| 484 | (SI_BIG_ENDIAN && sctx->b.chip_class <= CIK ? |
| 485 | V_028A7C_VGT_DMA_SWAP_16_BIT : 0)); |
| 486 | break; |
| 487 | case 4: |
| 488 | radeon_emit(cs, V_028A7C_VGT_INDEX_32 | |
| 489 | (SI_BIG_ENDIAN && sctx->b.chip_class <= CIK ? |
| 490 | V_028A7C_VGT_DMA_SWAP_32_BIT : 0)); |
| 491 | break; |
| 492 | default: |
| 493 | assert(!"unreachable"); |
| 494 | return; |
Marek Olšák | 384213c | 2014-12-07 15:52:15 +0100 | [diff] [blame] | 495 | } |
Christian König | 9f5ff59 | 2012-08-03 10:26:01 +0200 | [diff] [blame] | 496 | } |
Christian König | 9f5ff59 | 2012-08-03 10:26:01 +0200 | [diff] [blame] | 497 | |
Marek Olšák | 09056b3 | 2014-04-23 16:15:36 +0200 | [diff] [blame] | 498 | if (!info->indirect) { |
Marek Olšák | 3382036 | 2014-12-07 20:04:40 +0100 | [diff] [blame] | 499 | int base_vertex; |
| 500 | |
Marek Olšák | 384213c | 2014-12-07 15:52:15 +0100 | [diff] [blame] | 501 | radeon_emit(cs, PKT3(PKT3_NUM_INSTANCES, 0, 0)); |
| 502 | radeon_emit(cs, info->instance_count); |
Marek Olšák | 2a7b57a | 2014-04-24 03:03:43 +0200 | [diff] [blame] | 503 | |
Marek Olšák | 3382036 | 2014-12-07 20:04:40 +0100 | [diff] [blame] | 504 | /* Base vertex and start instance. */ |
| 505 | base_vertex = info->indexed ? info->index_bias : info->start; |
| 506 | |
| 507 | if (base_vertex != sctx->last_base_vertex || |
| 508 | sctx->last_base_vertex == SI_BASE_VERTEX_UNKNOWN || |
| 509 | info->start_instance != sctx->last_start_instance || |
| 510 | sh_base_reg != sctx->last_sh_base_reg) { |
Marek Olšák | d2e63ac | 2015-08-30 01:54:00 +0200 | [diff] [blame] | 511 | radeon_set_sh_reg_seq(cs, sh_base_reg + SI_SGPR_BASE_VERTEX * 4, 2); |
Marek Olšák | 3382036 | 2014-12-07 20:04:40 +0100 | [diff] [blame] | 512 | radeon_emit(cs, base_vertex); |
| 513 | radeon_emit(cs, info->start_instance); |
| 514 | |
| 515 | sctx->last_base_vertex = base_vertex; |
| 516 | sctx->last_start_instance = info->start_instance; |
| 517 | sctx->last_sh_base_reg = sh_base_reg; |
| 518 | } |
Marek Olšák | 2a7b57a | 2014-04-24 03:03:43 +0200 | [diff] [blame] | 519 | } else { |
Marek Olšák | 3382036 | 2014-12-07 20:04:40 +0100 | [diff] [blame] | 520 | si_invalidate_draw_sh_constants(sctx); |
| 521 | |
Marek Olšák | 7ff2991 | 2015-08-30 02:04:37 +0200 | [diff] [blame] | 522 | radeon_add_to_buffer_list(&sctx->b, &sctx->b.rings.gfx, |
Marek Olšák | 384213c | 2014-12-07 15:52:15 +0100 | [diff] [blame] | 523 | (struct r600_resource *)info->indirect, |
Marek Olšák | 2edb060 | 2015-09-26 23:18:55 +0200 | [diff] [blame] | 524 | RADEON_USAGE_READ, RADEON_PRIO_DRAW_INDIRECT); |
Marek Olšák | 09056b3 | 2014-04-23 16:15:36 +0200 | [diff] [blame] | 525 | } |
| 526 | |
Christian König | 9f5ff59 | 2012-08-03 10:26:01 +0200 | [diff] [blame] | 527 | if (info->indexed) { |
Marek Olšák | 384213c | 2014-12-07 15:52:15 +0100 | [diff] [blame] | 528 | uint32_t index_max_size = (ib->buffer->width0 - ib->offset) / |
| 529 | ib->index_size; |
| 530 | uint64_t index_va = r600_resource(ib->buffer)->gpu_address + ib->offset; |
Christian König | 9f5ff59 | 2012-08-03 10:26:01 +0200 | [diff] [blame] | 531 | |
Marek Olšák | 7ff2991 | 2015-08-30 02:04:37 +0200 | [diff] [blame] | 532 | radeon_add_to_buffer_list(&sctx->b, &sctx->b.rings.gfx, |
Marek Olšák | 384213c | 2014-12-07 15:52:15 +0100 | [diff] [blame] | 533 | (struct r600_resource *)ib->buffer, |
Marek Olšák | 2edb060 | 2015-09-26 23:18:55 +0200 | [diff] [blame] | 534 | RADEON_USAGE_READ, RADEON_PRIO_INDEX_BUFFER); |
Marek Olšák | 2a7b57a | 2014-04-24 03:03:43 +0200 | [diff] [blame] | 535 | |
| 536 | if (info->indirect) { |
Marek Olšák | 1c03a69 | 2014-08-06 22:29:27 +0200 | [diff] [blame] | 537 | uint64_t indirect_va = r600_resource(info->indirect)->gpu_address; |
Marek Olšák | 384213c | 2014-12-07 15:52:15 +0100 | [diff] [blame] | 538 | |
| 539 | assert(indirect_va % 8 == 0); |
| 540 | assert(index_va % 2 == 0); |
| 541 | assert(info->indirect_offset % 4 == 0); |
| 542 | |
| 543 | radeon_emit(cs, PKT3(PKT3_SET_BASE, 2, 0)); |
| 544 | radeon_emit(cs, 1); |
| 545 | radeon_emit(cs, indirect_va); |
| 546 | radeon_emit(cs, indirect_va >> 32); |
| 547 | |
| 548 | radeon_emit(cs, PKT3(PKT3_INDEX_BASE, 1, 0)); |
| 549 | radeon_emit(cs, index_va); |
| 550 | radeon_emit(cs, index_va >> 32); |
| 551 | |
| 552 | radeon_emit(cs, PKT3(PKT3_INDEX_BUFFER_SIZE, 0, 0)); |
| 553 | radeon_emit(cs, index_max_size); |
| 554 | |
| 555 | radeon_emit(cs, PKT3(PKT3_DRAW_INDEX_INDIRECT, 3, sctx->b.predicate_drawing)); |
| 556 | radeon_emit(cs, info->indirect_offset); |
| 557 | radeon_emit(cs, (sh_base_reg + SI_SGPR_BASE_VERTEX * 4 - SI_SH_REG_OFFSET) >> 2); |
| 558 | radeon_emit(cs, (sh_base_reg + SI_SGPR_START_INSTANCE * 4 - SI_SH_REG_OFFSET) >> 2); |
| 559 | radeon_emit(cs, V_0287F0_DI_SRC_SEL_DMA); |
Marek Olšák | 2a7b57a | 2014-04-24 03:03:43 +0200 | [diff] [blame] | 560 | } else { |
Marek Olšák | 384213c | 2014-12-07 15:52:15 +0100 | [diff] [blame] | 561 | index_va += info->start * ib->index_size; |
| 562 | |
| 563 | radeon_emit(cs, PKT3(PKT3_DRAW_INDEX_2, 4, sctx->b.predicate_drawing)); |
| 564 | radeon_emit(cs, index_max_size); |
| 565 | radeon_emit(cs, index_va); |
| 566 | radeon_emit(cs, (index_va >> 32UL) & 0xFF); |
| 567 | radeon_emit(cs, info->count); |
| 568 | radeon_emit(cs, V_0287F0_DI_SRC_SEL_DMA); |
Marek Olšák | 2a7b57a | 2014-04-24 03:03:43 +0200 | [diff] [blame] | 569 | } |
Christian König | 9f5ff59 | 2012-08-03 10:26:01 +0200 | [diff] [blame] | 570 | } else { |
Marek Olšák | 2a7b57a | 2014-04-24 03:03:43 +0200 | [diff] [blame] | 571 | if (info->indirect) { |
Marek Olšák | 1c03a69 | 2014-08-06 22:29:27 +0200 | [diff] [blame] | 572 | uint64_t indirect_va = r600_resource(info->indirect)->gpu_address; |
Marek Olšák | 384213c | 2014-12-07 15:52:15 +0100 | [diff] [blame] | 573 | |
| 574 | assert(indirect_va % 8 == 0); |
| 575 | assert(info->indirect_offset % 4 == 0); |
| 576 | |
| 577 | radeon_emit(cs, PKT3(PKT3_SET_BASE, 2, 0)); |
| 578 | radeon_emit(cs, 1); |
| 579 | radeon_emit(cs, indirect_va); |
| 580 | radeon_emit(cs, indirect_va >> 32); |
| 581 | |
| 582 | radeon_emit(cs, PKT3(PKT3_DRAW_INDIRECT, 3, sctx->b.predicate_drawing)); |
| 583 | radeon_emit(cs, info->indirect_offset); |
| 584 | radeon_emit(cs, (sh_base_reg + SI_SGPR_BASE_VERTEX * 4 - SI_SH_REG_OFFSET) >> 2); |
| 585 | radeon_emit(cs, (sh_base_reg + SI_SGPR_START_INSTANCE * 4 - SI_SH_REG_OFFSET) >> 2); |
| 586 | radeon_emit(cs, V_0287F0_DI_SRC_SEL_AUTO_INDEX); |
Marek Olšák | 2a7b57a | 2014-04-24 03:03:43 +0200 | [diff] [blame] | 587 | } else { |
Marek Olšák | 384213c | 2014-12-07 15:52:15 +0100 | [diff] [blame] | 588 | radeon_emit(cs, PKT3(PKT3_DRAW_INDEX_AUTO, 1, sctx->b.predicate_drawing)); |
| 589 | radeon_emit(cs, info->count); |
| 590 | radeon_emit(cs, V_0287F0_DI_SRC_SEL_AUTO_INDEX | |
| 591 | S_0287F0_USE_OPAQUE(!!info->count_from_stream_output)); |
Marek Olšák | 2a7b57a | 2014-04-24 03:03:43 +0200 | [diff] [blame] | 592 | } |
Christian König | 9f5ff59 | 2012-08-03 10:26:01 +0200 | [diff] [blame] | 593 | } |
Christian König | 9f5ff59 | 2012-08-03 10:26:01 +0200 | [diff] [blame] | 594 | } |
| 595 | |
Marek Olšák | 73c2b0d | 2014-12-28 23:11:38 +0100 | [diff] [blame] | 596 | #define BOTH_ICACHE_KCACHE (SI_CONTEXT_INV_ICACHE | SI_CONTEXT_INV_KCACHE) |
| 597 | |
Marek Olšák | 5bb0ad7 | 2015-08-28 23:52:47 +0200 | [diff] [blame] | 598 | void si_emit_cache_flush(struct si_context *si_ctx, struct r600_atom *atom) |
Marek Olšák | a77ee8b | 2013-08-26 17:19:39 +0200 | [diff] [blame] | 599 | { |
Marek Olšák | 5bb0ad7 | 2015-08-28 23:52:47 +0200 | [diff] [blame] | 600 | struct r600_common_context *sctx = &si_ctx->b; |
Andreas Hartmetz | 8662e66 | 2014-01-11 16:00:50 +0100 | [diff] [blame] | 601 | struct radeon_winsys_cs *cs = sctx->rings.gfx.cs; |
Marek Olšák | a77ee8b | 2013-08-26 17:19:39 +0200 | [diff] [blame] | 602 | uint32_t cp_coher_cntl = 0; |
Marek Olšák | 604b58b | 2014-09-20 11:48:58 +0200 | [diff] [blame] | 603 | uint32_t compute = |
Marek Olšák | 2bfe9d4 | 2014-12-29 14:02:46 +0100 | [diff] [blame] | 604 | PKT3_SHADER_TYPE_S(!!(sctx->flags & SI_CONTEXT_FLAG_COMPUTE)); |
Marek Olšák | a77ee8b | 2013-08-26 17:19:39 +0200 | [diff] [blame] | 605 | |
Marek Olšák | 73c2b0d | 2014-12-28 23:11:38 +0100 | [diff] [blame] | 606 | /* SI has a bug that it always flushes ICACHE and KCACHE if either |
Marek Olšák | 7692704 | 2015-02-19 13:03:54 +0100 | [diff] [blame] | 607 | * bit is set. An alternative way is to write SQC_CACHES, but that |
| 608 | * doesn't seem to work reliably. Since the bug doesn't affect |
| 609 | * correctness (it only does more work than necessary) and |
| 610 | * the performance impact is likely negligible, there is no plan |
| 611 | * to fix it. |
| 612 | */ |
| 613 | |
| 614 | if (sctx->flags & SI_CONTEXT_INV_ICACHE) |
| 615 | cp_coher_cntl |= S_0085F0_SH_ICACHE_ACTION_ENA(1); |
| 616 | if (sctx->flags & SI_CONTEXT_INV_KCACHE) |
| 617 | cp_coher_cntl |= S_0085F0_SH_KCACHE_ACTION_ENA(1); |
Marek Olšák | 2bfe9d4 | 2014-12-29 14:02:46 +0100 | [diff] [blame] | 618 | |
Marek Olšák | ca9c5b2 | 2014-12-30 16:45:51 +0100 | [diff] [blame] | 619 | if (sctx->flags & SI_CONTEXT_INV_TC_L1) |
Marek Olšák | 2bfe9d4 | 2014-12-29 14:02:46 +0100 | [diff] [blame] | 620 | cp_coher_cntl |= S_0085F0_TCL1_ACTION_ENA(1); |
Marek Olšák | 2d1952e | 2015-04-16 20:44:54 +0200 | [diff] [blame] | 621 | if (sctx->flags & SI_CONTEXT_INV_TC_L2) { |
Marek Olšák | 2bfe9d4 | 2014-12-29 14:02:46 +0100 | [diff] [blame] | 622 | cp_coher_cntl |= S_0085F0_TC_ACTION_ENA(1); |
| 623 | |
Marek Olšák | 2d1952e | 2015-04-16 20:44:54 +0200 | [diff] [blame] | 624 | /* TODO: this might not be needed. */ |
| 625 | if (sctx->chip_class >= VI) |
| 626 | cp_coher_cntl |= S_0301F0_TC_WB_ACTION_ENA(1); |
| 627 | } |
| 628 | |
Marek Olšák | 2bfe9d4 | 2014-12-29 14:02:46 +0100 | [diff] [blame] | 629 | if (sctx->flags & SI_CONTEXT_FLUSH_AND_INV_CB) { |
Marek Olšák | a77ee8b | 2013-08-26 17:19:39 +0200 | [diff] [blame] | 630 | cp_coher_cntl |= S_0085F0_CB_ACTION_ENA(1) | |
| 631 | S_0085F0_CB0_DEST_BASE_ENA(1) | |
| 632 | S_0085F0_CB1_DEST_BASE_ENA(1) | |
| 633 | S_0085F0_CB2_DEST_BASE_ENA(1) | |
| 634 | S_0085F0_CB3_DEST_BASE_ENA(1) | |
| 635 | S_0085F0_CB4_DEST_BASE_ENA(1) | |
| 636 | S_0085F0_CB5_DEST_BASE_ENA(1) | |
| 637 | S_0085F0_CB6_DEST_BASE_ENA(1) | |
| 638 | S_0085F0_CB7_DEST_BASE_ENA(1); |
| 639 | } |
Marek Olšák | 2bfe9d4 | 2014-12-29 14:02:46 +0100 | [diff] [blame] | 640 | if (sctx->flags & SI_CONTEXT_FLUSH_AND_INV_DB) { |
Marek Olšák | a77ee8b | 2013-08-26 17:19:39 +0200 | [diff] [blame] | 641 | cp_coher_cntl |= S_0085F0_DB_ACTION_ENA(1) | |
| 642 | S_0085F0_DB_DEST_BASE_ENA(1); |
| 643 | } |
| 644 | |
Marek Olšák | d8185aa | 2014-12-30 18:41:25 +0100 | [diff] [blame] | 645 | if (sctx->flags & SI_CONTEXT_FLUSH_AND_INV_CB_META) { |
| 646 | radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0) | compute); |
| 647 | radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_AND_INV_CB_META) | EVENT_INDEX(0)); |
| 648 | } |
| 649 | if (sctx->flags & SI_CONTEXT_FLUSH_AND_INV_DB_META) { |
| 650 | radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0) | compute); |
| 651 | radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_AND_INV_DB_META) | EVENT_INDEX(0)); |
| 652 | } |
| 653 | if (sctx->flags & SI_CONTEXT_FLUSH_WITH_INV_L2) { |
| 654 | radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0) | compute); |
| 655 | radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_CACHE_FLUSH) | EVENT_INDEX(7) | |
| 656 | EVENT_WRITE_INV_L2); |
| 657 | } |
| 658 | |
| 659 | /* FLUSH_AND_INV events must be emitted before PS_PARTIAL_FLUSH. |
| 660 | * Otherwise, clearing CMASK (CB meta) with CP DMA isn't reliable. |
| 661 | * |
| 662 | * I think the reason is that FLUSH_AND_INV is only added to a queue |
| 663 | * and it is PS_PARTIAL_FLUSH that waits for it to complete. |
| 664 | */ |
| 665 | if (sctx->flags & SI_CONTEXT_PS_PARTIAL_FLUSH) { |
| 666 | radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0) | compute); |
| 667 | radeon_emit(cs, EVENT_TYPE(V_028A90_PS_PARTIAL_FLUSH) | EVENT_INDEX(4)); |
| 668 | } else if (sctx->flags & SI_CONTEXT_VS_PARTIAL_FLUSH) { |
| 669 | radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0) | compute); |
| 670 | radeon_emit(cs, EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH) | EVENT_INDEX(4)); |
| 671 | } |
| 672 | if (sctx->flags & SI_CONTEXT_CS_PARTIAL_FLUSH) { |
| 673 | radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0) | compute); |
| 674 | radeon_emit(cs, EVENT_TYPE(V_028A90_CS_PARTIAL_FLUSH | EVENT_INDEX(4))); |
| 675 | } |
| 676 | if (sctx->flags & SI_CONTEXT_VGT_FLUSH) { |
| 677 | radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0) | compute); |
| 678 | radeon_emit(cs, EVENT_TYPE(V_028A90_VGT_FLUSH) | EVENT_INDEX(0)); |
| 679 | } |
| 680 | if (sctx->flags & SI_CONTEXT_VGT_STREAMOUT_SYNC) { |
| 681 | radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0) | compute); |
| 682 | radeon_emit(cs, EVENT_TYPE(V_028A90_VGT_STREAMOUT_SYNC) | EVENT_INDEX(0)); |
| 683 | } |
| 684 | |
| 685 | /* SURFACE_SYNC must be emitted after partial flushes. |
| 686 | * It looks like SURFACE_SYNC flushes caches immediately and doesn't |
| 687 | * wait for any engines. This should be last. |
| 688 | */ |
Marek Olšák | a77ee8b | 2013-08-26 17:19:39 +0200 | [diff] [blame] | 689 | if (cp_coher_cntl) { |
Andreas Hartmetz | 8662e66 | 2014-01-11 16:00:50 +0100 | [diff] [blame] | 690 | if (sctx->chip_class >= CIK) { |
Marek Olšák | 604b58b | 2014-09-20 11:48:58 +0200 | [diff] [blame] | 691 | radeon_emit(cs, PKT3(PKT3_ACQUIRE_MEM, 5, 0) | compute); |
Marek Olšák | a77ee8b | 2013-08-26 17:19:39 +0200 | [diff] [blame] | 692 | radeon_emit(cs, cp_coher_cntl); /* CP_COHER_CNTL */ |
| 693 | radeon_emit(cs, 0xffffffff); /* CP_COHER_SIZE */ |
| 694 | radeon_emit(cs, 0xff); /* CP_COHER_SIZE_HI */ |
| 695 | radeon_emit(cs, 0); /* CP_COHER_BASE */ |
| 696 | radeon_emit(cs, 0); /* CP_COHER_BASE_HI */ |
| 697 | radeon_emit(cs, 0x0000000A); /* POLL_INTERVAL */ |
| 698 | } else { |
Marek Olšák | 604b58b | 2014-09-20 11:48:58 +0200 | [diff] [blame] | 699 | radeon_emit(cs, PKT3(PKT3_SURFACE_SYNC, 3, 0) | compute); |
Marek Olšák | a77ee8b | 2013-08-26 17:19:39 +0200 | [diff] [blame] | 700 | radeon_emit(cs, cp_coher_cntl); /* CP_COHER_CNTL */ |
| 701 | radeon_emit(cs, 0xffffffff); /* CP_COHER_SIZE */ |
| 702 | radeon_emit(cs, 0); /* CP_COHER_BASE */ |
| 703 | radeon_emit(cs, 0x0000000A); /* POLL_INTERVAL */ |
| 704 | } |
| 705 | } |
| 706 | |
Andreas Hartmetz | 8662e66 | 2014-01-11 16:00:50 +0100 | [diff] [blame] | 707 | sctx->flags = 0; |
Marek Olšák | a77ee8b | 2013-08-26 17:19:39 +0200 | [diff] [blame] | 708 | } |
| 709 | |
Marek Olšák | 2a7b57a | 2014-04-24 03:03:43 +0200 | [diff] [blame] | 710 | static void si_get_draw_start_count(struct si_context *sctx, |
| 711 | const struct pipe_draw_info *info, |
| 712 | unsigned *start, unsigned *count) |
| 713 | { |
| 714 | if (info->indirect) { |
| 715 | struct r600_resource *indirect = |
| 716 | (struct r600_resource*)info->indirect; |
| 717 | int *data = r600_buffer_map_sync_with_rings(&sctx->b, |
| 718 | indirect, PIPE_TRANSFER_READ); |
| 719 | data += info->indirect_offset/sizeof(int); |
| 720 | *start = data[2]; |
| 721 | *count = data[0]; |
| 722 | } else { |
| 723 | *start = info->start; |
| 724 | *count = info->count; |
| 725 | } |
| 726 | } |
| 727 | |
Christian König | 9f5ff59 | 2012-08-03 10:26:01 +0200 | [diff] [blame] | 728 | void si_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *info) |
Christian König | ca9cf61 | 2012-07-19 15:20:45 +0200 | [diff] [blame] | 729 | { |
Andreas Hartmetz | 8662e66 | 2014-01-11 16:00:50 +0100 | [diff] [blame] | 730 | struct si_context *sctx = (struct si_context *)ctx; |
Marek Olšák | 50bb2de | 2015-10-22 22:18:49 +0200 | [diff] [blame^] | 731 | struct si_state_rasterizer *rs = sctx->queued.named.rasterizer; |
Christian König | ca9cf61 | 2012-07-19 15:20:45 +0200 | [diff] [blame] | 732 | struct pipe_index_buffer ib = {}; |
Marek Olšák | 87c1e9e | 2015-08-29 00:49:40 +0200 | [diff] [blame] | 733 | unsigned mask; |
Christian König | ca9cf61 | 2012-07-19 15:20:45 +0200 | [diff] [blame] | 734 | |
Marek Olšák | 2a7b57a | 2014-04-24 03:03:43 +0200 | [diff] [blame] | 735 | if (!info->count && !info->indirect && |
| 736 | (info->indexed || !info->count_from_stream_output)) |
Christian König | ca9cf61 | 2012-07-19 15:20:45 +0200 | [diff] [blame] | 737 | return; |
Christian König | ca9cf61 | 2012-07-19 15:20:45 +0200 | [diff] [blame] | 738 | |
Marek Olšák | 50bb2de | 2015-10-22 22:18:49 +0200 | [diff] [blame^] | 739 | if (!sctx->vs_shader.cso) { |
| 740 | assert(0); |
| 741 | return; |
| 742 | } |
| 743 | if (!sctx->ps_shader.cso && (!rs || !rs->rasterizer_discard)) { |
Marek Olšák | 99bf47f | 2015-02-22 18:10:38 +0100 | [diff] [blame] | 744 | assert(0); |
Christian König | ca9cf61 | 2012-07-19 15:20:45 +0200 | [diff] [blame] | 745 | return; |
Marek Olšák | 99bf47f | 2015-02-22 18:10:38 +0100 | [diff] [blame] | 746 | } |
Marek Olšák | 9b54ce3 | 2015-10-07 01:48:18 +0200 | [diff] [blame] | 747 | if (!!sctx->tes_shader.cso != (info->mode == PIPE_PRIM_PATCHES)) { |
Marek Olšák | 99bf47f | 2015-02-22 18:10:38 +0100 | [diff] [blame] | 748 | assert(0); |
| 749 | return; |
| 750 | } |
Christian König | ca9cf61 | 2012-07-19 15:20:45 +0200 | [diff] [blame] | 751 | |
Marek Olšák | 0b1f31a | 2015-02-22 19:14:42 +0100 | [diff] [blame] | 752 | si_decompress_textures(sctx); |
| 753 | |
| 754 | /* Set the rasterization primitive type. |
| 755 | * |
| 756 | * This must be done after si_decompress_textures, which can call |
| 757 | * draw_vbo recursively, and before si_update_shaders, which uses |
| 758 | * current_rast_prim for this draw_vbo call. */ |
Marek Olšák | 9b54ce3 | 2015-10-07 01:48:18 +0200 | [diff] [blame] | 759 | if (sctx->gs_shader.cso) |
| 760 | sctx->current_rast_prim = sctx->gs_shader.cso->gs_output_prim; |
| 761 | else if (sctx->tes_shader.cso) |
Marek Olšák | 5aa5f90 | 2015-02-22 18:09:18 +0100 | [diff] [blame] | 762 | sctx->current_rast_prim = |
Marek Olšák | 9b54ce3 | 2015-10-07 01:48:18 +0200 | [diff] [blame] | 763 | sctx->tes_shader.cso->info.properties[TGSI_PROPERTY_TES_PRIM_MODE]; |
Marek Olšák | 1fe7ba8 | 2015-01-31 20:09:46 +0100 | [diff] [blame] | 764 | else |
| 765 | sctx->current_rast_prim = info->mode; |
| 766 | |
Marek Olšák | 22d3ccf | 2015-09-10 18:27:53 +0200 | [diff] [blame] | 767 | if (!si_update_shaders(sctx) || |
| 768 | !si_upload_shader_descriptors(sctx)) |
Marek Olšák | b052811 | 2015-07-25 00:53:16 +0200 | [diff] [blame] | 769 | return; |
Christian König | ca9cf61 | 2012-07-19 15:20:45 +0200 | [diff] [blame] | 770 | |
Christian König | 9f5ff59 | 2012-08-03 10:26:01 +0200 | [diff] [blame] | 771 | if (info->indexed) { |
Christian König | ca9cf61 | 2012-07-19 15:20:45 +0200 | [diff] [blame] | 772 | /* Initialize the index buffer struct. */ |
Andreas Hartmetz | 8662e66 | 2014-01-11 16:00:50 +0100 | [diff] [blame] | 773 | pipe_resource_reference(&ib.buffer, sctx->index_buffer.buffer); |
| 774 | ib.user_buffer = sctx->index_buffer.user_buffer; |
| 775 | ib.index_size = sctx->index_buffer.index_size; |
Marek Olšák | 887b69a | 2014-04-24 16:13:54 +0200 | [diff] [blame] | 776 | ib.offset = sctx->index_buffer.offset; |
Christian König | ca9cf61 | 2012-07-19 15:20:45 +0200 | [diff] [blame] | 777 | |
| 778 | /* Translate or upload, if needed. */ |
Marek Olšák | 2d1952e | 2015-04-16 20:44:54 +0200 | [diff] [blame] | 779 | /* 8-bit indices are supported on VI. */ |
| 780 | if (sctx->b.chip_class <= CIK && ib.index_size == 1) { |
Marek Olšák | 9f5c037 | 2014-01-22 03:05:21 +0100 | [diff] [blame] | 781 | struct pipe_resource *out_buffer = NULL; |
Marek Olšák | 887b69a | 2014-04-24 16:13:54 +0200 | [diff] [blame] | 782 | unsigned out_offset, start, count, start_offset; |
Marek Olšák | 9f5c037 | 2014-01-22 03:05:21 +0100 | [diff] [blame] | 783 | void *ptr; |
| 784 | |
Marek Olšák | 2a7b57a | 2014-04-24 03:03:43 +0200 | [diff] [blame] | 785 | si_get_draw_start_count(sctx, info, &start, &count); |
Marek Olšák | 887b69a | 2014-04-24 16:13:54 +0200 | [diff] [blame] | 786 | start_offset = start * ib.index_size; |
| 787 | |
| 788 | u_upload_alloc(sctx->b.uploader, start_offset, count * 2, |
Marek Olšák | 9f5c037 | 2014-01-22 03:05:21 +0100 | [diff] [blame] | 789 | &out_offset, &out_buffer, &ptr); |
Marek Olšák | 29dff6f | 2015-09-10 17:42:31 +0200 | [diff] [blame] | 790 | if (!out_buffer) { |
| 791 | pipe_resource_reference(&ib.buffer, NULL); |
| 792 | return; |
| 793 | } |
Marek Olšák | 9f5c037 | 2014-01-22 03:05:21 +0100 | [diff] [blame] | 794 | |
Marek Olšák | 887b69a | 2014-04-24 16:13:54 +0200 | [diff] [blame] | 795 | util_shorten_ubyte_elts_to_userptr(&sctx->b.b, &ib, 0, |
| 796 | ib.offset + start_offset, |
| 797 | count, ptr); |
Marek Olšák | 9f5c037 | 2014-01-22 03:05:21 +0100 | [diff] [blame] | 798 | |
| 799 | pipe_resource_reference(&ib.buffer, NULL); |
| 800 | ib.user_buffer = NULL; |
| 801 | ib.buffer = out_buffer; |
Marek Olšák | 887b69a | 2014-04-24 16:13:54 +0200 | [diff] [blame] | 802 | /* info->start will be added by the drawing code */ |
| 803 | ib.offset = out_offset - start_offset; |
Marek Olšák | 9f5c037 | 2014-01-22 03:05:21 +0100 | [diff] [blame] | 804 | ib.index_size = 2; |
Marek Olšák | 887b69a | 2014-04-24 16:13:54 +0200 | [diff] [blame] | 805 | } else if (ib.user_buffer && !ib.buffer) { |
| 806 | unsigned start, count, start_offset; |
Christian König | ca9cf61 | 2012-07-19 15:20:45 +0200 | [diff] [blame] | 807 | |
Marek Olšák | 2a7b57a | 2014-04-24 03:03:43 +0200 | [diff] [blame] | 808 | si_get_draw_start_count(sctx, info, &start, &count); |
Marek Olšák | 887b69a | 2014-04-24 16:13:54 +0200 | [diff] [blame] | 809 | start_offset = start * ib.index_size; |
| 810 | |
| 811 | u_upload_data(sctx->b.uploader, start_offset, count * ib.index_size, |
| 812 | (char*)ib.user_buffer + start_offset, |
| 813 | &ib.offset, &ib.buffer); |
Marek Olšák | 29dff6f | 2015-09-10 17:42:31 +0200 | [diff] [blame] | 814 | if (!ib.buffer) |
| 815 | return; |
Marek Olšák | 887b69a | 2014-04-24 16:13:54 +0200 | [diff] [blame] | 816 | /* info->start will be added by the drawing code */ |
| 817 | ib.offset -= start_offset; |
Christian König | ca9cf61 | 2012-07-19 15:20:45 +0200 | [diff] [blame] | 818 | } |
Christian König | ca9cf61 | 2012-07-19 15:20:45 +0200 | [diff] [blame] | 819 | } |
| 820 | |
Marek Olšák | 5749676 | 2015-09-06 15:43:23 +0200 | [diff] [blame] | 821 | /* VI reads index buffers through TC L2. */ |
| 822 | if (info->indexed && sctx->b.chip_class <= CIK && |
| 823 | r600_resource(ib.buffer)->TC_L2_dirty) { |
Marek Olšák | 18a30c9 | 2014-12-29 14:53:11 +0100 | [diff] [blame] | 824 | sctx->b.flags |= SI_CONTEXT_INV_TC_L2; |
| 825 | r600_resource(ib.buffer)->TC_L2_dirty = false; |
| 826 | } |
| 827 | |
Marek Olšák | a77ee8b | 2013-08-26 17:19:39 +0200 | [diff] [blame] | 828 | /* Check flush flags. */ |
Andreas Hartmetz | 8662e66 | 2014-01-11 16:00:50 +0100 | [diff] [blame] | 829 | if (sctx->b.flags) |
Grazvydas Ignotas | 3206d4e | 2015-08-10 00:42:32 +0300 | [diff] [blame] | 830 | si_mark_atom_dirty(sctx, sctx->atoms.s.cache_flush); |
Marek Olšák | a77ee8b | 2013-08-26 17:19:39 +0200 | [diff] [blame] | 831 | |
Marek Olšák | 28b34b4 | 2015-08-30 03:56:13 +0200 | [diff] [blame] | 832 | si_need_cs_space(sctx); |
Christian König | ca9cf61 | 2012-07-19 15:20:45 +0200 | [diff] [blame] | 833 | |
Marek Olšák | a77ee8b | 2013-08-26 17:19:39 +0200 | [diff] [blame] | 834 | /* Emit states. */ |
Marek Olšák | 87c1e9e | 2015-08-29 00:49:40 +0200 | [diff] [blame] | 835 | mask = sctx->dirty_atoms; |
| 836 | while (mask) { |
| 837 | struct r600_atom *atom = sctx->atoms.array[u_bit_scan(&mask)]; |
| 838 | |
| 839 | atom->emit(&sctx->b, atom); |
Marek Olšák | c8e70e6 | 2013-08-06 06:42:22 +0200 | [diff] [blame] | 840 | } |
Marek Olšák | 87c1e9e | 2015-08-29 00:49:40 +0200 | [diff] [blame] | 841 | sctx->dirty_atoms = 0; |
Marek Olšák | c8e70e6 | 2013-08-06 06:42:22 +0200 | [diff] [blame] | 842 | |
Andreas Hartmetz | 8662e66 | 2014-01-11 16:00:50 +0100 | [diff] [blame] | 843 | si_pm4_emit_dirty(sctx); |
Marek Olšák | dc39413 | 2015-03-15 20:13:52 +0100 | [diff] [blame] | 844 | si_emit_scratch_reloc(sctx); |
Marek Olšák | fdf2c04 | 2015-02-22 17:42:20 +0100 | [diff] [blame] | 845 | si_emit_rasterizer_prim_state(sctx); |
| 846 | si_emit_draw_registers(sctx, info); |
Marek Olšák | 384213c | 2014-12-07 15:52:15 +0100 | [diff] [blame] | 847 | si_emit_draw_packets(sctx, info, &ib); |
| 848 | |
Marek Olšák | 2c14a6d | 2015-08-19 11:53:25 +0200 | [diff] [blame] | 849 | if (sctx->trace_buf) |
Andreas Hartmetz | 8662e66 | 2014-01-11 16:00:50 +0100 | [diff] [blame] | 850 | si_trace_emit(sctx); |
Jerome Glisse | 3f7d971 | 2013-03-25 11:46:38 -0400 | [diff] [blame] | 851 | |
Marek Olšák | 0e7f563 | 2014-07-26 03:16:22 +0200 | [diff] [blame] | 852 | /* Workaround for a VGT hang when streamout is enabled. |
| 853 | * It must be done after drawing. */ |
Marek Olšák | 2d1952e | 2015-04-16 20:44:54 +0200 | [diff] [blame] | 854 | if ((sctx->b.family == CHIP_HAWAII || sctx->b.family == CHIP_TONGA) && |
Marek Olšák | 0e7f563 | 2014-07-26 03:16:22 +0200 | [diff] [blame] | 855 | (sctx->b.streamout.streamout_enabled || |
| 856 | sctx->b.streamout.prims_gen_query_enabled)) { |
Marek Olšák | 2bfe9d4 | 2014-12-29 14:02:46 +0100 | [diff] [blame] | 857 | sctx->b.flags |= SI_CONTEXT_VGT_STREAMOUT_SYNC; |
Marek Olšák | 0e7f563 | 2014-07-26 03:16:22 +0200 | [diff] [blame] | 858 | } |
| 859 | |
Marek Olšák | 6f6112a | 2013-01-17 19:36:41 +0100 | [diff] [blame] | 860 | /* Set the depth buffer as dirty. */ |
Marek Olšák | 6a5499b | 2014-03-04 17:49:39 +0100 | [diff] [blame] | 861 | if (sctx->framebuffer.state.zsbuf) { |
| 862 | struct pipe_surface *surf = sctx->framebuffer.state.zsbuf; |
Marek Olšák | 363b280 | 2013-08-05 03:42:11 +0200 | [diff] [blame] | 863 | struct r600_texture *rtex = (struct r600_texture *)surf->texture; |
Marek Olšák | 6f6112a | 2013-01-17 19:36:41 +0100 | [diff] [blame] | 864 | |
Marek Olšák | 0469171 | 2013-08-05 14:40:43 +0200 | [diff] [blame] | 865 | rtex->dirty_level_mask |= 1 << surf->u.tex.level; |
Marek Olšák | 5804c6a | 2015-09-06 17:35:06 +0200 | [diff] [blame] | 866 | |
| 867 | if (rtex->surface.flags & RADEON_SURF_SBUFFER) |
| 868 | rtex->stencil_dirty_level_mask |= 1 << surf->u.tex.level; |
Christian König | ca9cf61 | 2012-07-19 15:20:45 +0200 | [diff] [blame] | 869 | } |
Marek Olšák | 6a5499b | 2014-03-04 17:49:39 +0100 | [diff] [blame] | 870 | if (sctx->framebuffer.compressed_cb_mask) { |
Marek Olšák | 3c3feb3 | 2013-08-06 08:48:07 +0200 | [diff] [blame] | 871 | struct pipe_surface *surf; |
| 872 | struct r600_texture *rtex; |
Marek Olšák | 6a5499b | 2014-03-04 17:49:39 +0100 | [diff] [blame] | 873 | unsigned mask = sctx->framebuffer.compressed_cb_mask; |
Marek Olšák | 3c3feb3 | 2013-08-06 08:48:07 +0200 | [diff] [blame] | 874 | |
| 875 | do { |
| 876 | unsigned i = u_bit_scan(&mask); |
Marek Olšák | 6a5499b | 2014-03-04 17:49:39 +0100 | [diff] [blame] | 877 | surf = sctx->framebuffer.state.cbufs[i]; |
Marek Olšák | 3c3feb3 | 2013-08-06 08:48:07 +0200 | [diff] [blame] | 878 | rtex = (struct r600_texture*)surf->texture; |
| 879 | |
| 880 | rtex->dirty_level_mask |= 1 << surf->u.tex.level; |
| 881 | } while (mask); |
| 882 | } |
Christian König | ca9cf61 | 2012-07-19 15:20:45 +0200 | [diff] [blame] | 883 | |
| 884 | pipe_resource_reference(&ib.buffer, NULL); |
Marek Olšák | ba0c16f | 2014-01-22 01:29:18 +0100 | [diff] [blame] | 885 | sctx->b.num_draw_calls++; |
Christian König | ca9cf61 | 2012-07-19 15:20:45 +0200 | [diff] [blame] | 886 | } |
Marek Olšák | 837907b | 2014-09-05 11:59:10 +0200 | [diff] [blame] | 887 | |
Marek Olšák | 837907b | 2014-09-05 11:59:10 +0200 | [diff] [blame] | 888 | void si_trace_emit(struct si_context *sctx) |
| 889 | { |
Marek Olšák | 837907b | 2014-09-05 11:59:10 +0200 | [diff] [blame] | 890 | struct radeon_winsys_cs *cs = sctx->b.rings.gfx.cs; |
Marek Olšák | 837907b | 2014-09-05 11:59:10 +0200 | [diff] [blame] | 891 | |
Marek Olšák | 2c14a6d | 2015-08-19 11:53:25 +0200 | [diff] [blame] | 892 | sctx->trace_id++; |
Marek Olšák | 7ff2991 | 2015-08-30 02:04:37 +0200 | [diff] [blame] | 893 | radeon_add_to_buffer_list(&sctx->b, &sctx->b.rings.gfx, sctx->trace_buf, |
Marek Olšák | 2edb060 | 2015-09-26 23:18:55 +0200 | [diff] [blame] | 894 | RADEON_USAGE_READWRITE, RADEON_PRIO_TRACE); |
Marek Olšák | 2c14a6d | 2015-08-19 11:53:25 +0200 | [diff] [blame] | 895 | radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 3, 0)); |
Marek Olšák | 16e5d8a | 2015-08-19 18:45:11 +0200 | [diff] [blame] | 896 | radeon_emit(cs, S_370_DST_SEL(V_370_MEMORY_SYNC) | |
| 897 | S_370_WR_CONFIRM(1) | |
| 898 | S_370_ENGINE_SEL(V_370_ME)); |
Marek Olšák | 2c14a6d | 2015-08-19 11:53:25 +0200 | [diff] [blame] | 899 | radeon_emit(cs, sctx->trace_buf->gpu_address); |
| 900 | radeon_emit(cs, sctx->trace_buf->gpu_address >> 32); |
| 901 | radeon_emit(cs, sctx->trace_id); |
| 902 | radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); |
| 903 | radeon_emit(cs, SI_ENCODE_TRACE_POINT(sctx->trace_id)); |
Marek Olšák | 837907b | 2014-09-05 11:59:10 +0200 | [diff] [blame] | 904 | } |