Marek Olšák | ac72a6b | 2018-08-02 17:40:05 -0400 | [diff] [blame] | 1 | /* |
| 2 | * Copyright 2018 Advanced Micro Devices, Inc. |
| 3 | * All Rights Reserved. |
| 4 | * |
| 5 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 6 | * copy of this software and associated documentation files (the "Software"), |
| 7 | * to deal in the Software without restriction, including without limitation |
| 8 | * on the rights to use, copy, modify, merge, publish, distribute, sub |
| 9 | * license, and/or sell copies of the Software, and to permit persons to whom |
| 10 | * the Software is furnished to do so, subject to the following conditions: |
| 11 | * |
| 12 | * The above copyright notice and this permission notice (including the next |
| 13 | * paragraph) shall be included in all copies or substantial portions of the |
| 14 | * Software. |
| 15 | * |
| 16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 18 | * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL |
| 19 | * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, |
| 20 | * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR |
| 21 | * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE |
| 22 | * USE OR OTHER DEALINGS IN THE SOFTWARE. |
| 23 | */ |
| 24 | |
| 25 | #include "si_pipe.h" |
| 26 | #include "tgsi/tgsi_text.h" |
| 27 | #include "tgsi/tgsi_ureg.h" |
| 28 | |
| 29 | void *si_get_blitter_vs(struct si_context *sctx, enum blitter_attrib_type type, |
| 30 | unsigned num_layers) |
| 31 | { |
| 32 | unsigned vs_blit_property; |
| 33 | void **vs; |
| 34 | |
| 35 | switch (type) { |
| 36 | case UTIL_BLITTER_ATTRIB_NONE: |
| 37 | vs = num_layers > 1 ? &sctx->vs_blit_pos_layered : |
| 38 | &sctx->vs_blit_pos; |
| 39 | vs_blit_property = SI_VS_BLIT_SGPRS_POS; |
| 40 | break; |
| 41 | case UTIL_BLITTER_ATTRIB_COLOR: |
| 42 | vs = num_layers > 1 ? &sctx->vs_blit_color_layered : |
| 43 | &sctx->vs_blit_color; |
| 44 | vs_blit_property = SI_VS_BLIT_SGPRS_POS_COLOR; |
| 45 | break; |
| 46 | case UTIL_BLITTER_ATTRIB_TEXCOORD_XY: |
| 47 | case UTIL_BLITTER_ATTRIB_TEXCOORD_XYZW: |
| 48 | assert(num_layers == 1); |
| 49 | vs = &sctx->vs_blit_texcoord; |
| 50 | vs_blit_property = SI_VS_BLIT_SGPRS_POS_TEXCOORD; |
| 51 | break; |
| 52 | default: |
| 53 | assert(0); |
| 54 | return NULL; |
| 55 | } |
| 56 | if (*vs) |
| 57 | return *vs; |
| 58 | |
| 59 | struct ureg_program *ureg = ureg_create(PIPE_SHADER_VERTEX); |
| 60 | if (!ureg) |
| 61 | return NULL; |
| 62 | |
| 63 | /* Tell the shader to load VS inputs from SGPRs: */ |
Marek Olšák | 6a2bdb8 | 2019-07-31 16:45:21 -0400 | [diff] [blame^] | 64 | ureg_property(ureg, TGSI_PROPERTY_VS_BLIT_SGPRS_AMD, vs_blit_property); |
Marek Olšák | ac72a6b | 2018-08-02 17:40:05 -0400 | [diff] [blame] | 65 | ureg_property(ureg, TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION, true); |
| 66 | |
| 67 | /* This is just a pass-through shader with 1-3 MOV instructions. */ |
| 68 | ureg_MOV(ureg, |
| 69 | ureg_DECL_output(ureg, TGSI_SEMANTIC_POSITION, 0), |
| 70 | ureg_DECL_vs_input(ureg, 0)); |
| 71 | |
| 72 | if (type != UTIL_BLITTER_ATTRIB_NONE) { |
| 73 | ureg_MOV(ureg, |
| 74 | ureg_DECL_output(ureg, TGSI_SEMANTIC_GENERIC, 0), |
| 75 | ureg_DECL_vs_input(ureg, 1)); |
| 76 | } |
| 77 | |
| 78 | if (num_layers > 1) { |
| 79 | struct ureg_src instance_id = |
| 80 | ureg_DECL_system_value(ureg, TGSI_SEMANTIC_INSTANCEID, 0); |
| 81 | struct ureg_dst layer = |
| 82 | ureg_DECL_output(ureg, TGSI_SEMANTIC_LAYER, 0); |
| 83 | |
| 84 | ureg_MOV(ureg, ureg_writemask(layer, TGSI_WRITEMASK_X), |
| 85 | ureg_scalar(instance_id, TGSI_SWIZZLE_X)); |
| 86 | } |
| 87 | ureg_END(ureg); |
| 88 | |
| 89 | *vs = ureg_create_shader_and_destroy(ureg, &sctx->b); |
| 90 | return *vs; |
| 91 | } |
| 92 | |
| 93 | /** |
| 94 | * This is used when TCS is NULL in the VS->TCS->TES chain. In this case, |
| 95 | * VS passes its outputs to TES directly, so the fixed-function shader only |
| 96 | * has to write TESSOUTER and TESSINNER. |
| 97 | */ |
| 98 | void *si_create_fixed_func_tcs(struct si_context *sctx) |
| 99 | { |
| 100 | struct ureg_src outer, inner; |
| 101 | struct ureg_dst tessouter, tessinner; |
| 102 | struct ureg_program *ureg = ureg_create(PIPE_SHADER_TESS_CTRL); |
| 103 | |
| 104 | if (!ureg) |
| 105 | return NULL; |
| 106 | |
| 107 | outer = ureg_DECL_system_value(ureg, |
| 108 | TGSI_SEMANTIC_DEFAULT_TESSOUTER_SI, 0); |
| 109 | inner = ureg_DECL_system_value(ureg, |
| 110 | TGSI_SEMANTIC_DEFAULT_TESSINNER_SI, 0); |
| 111 | |
| 112 | tessouter = ureg_DECL_output(ureg, TGSI_SEMANTIC_TESSOUTER, 0); |
| 113 | tessinner = ureg_DECL_output(ureg, TGSI_SEMANTIC_TESSINNER, 0); |
| 114 | |
| 115 | ureg_MOV(ureg, tessouter, outer); |
| 116 | ureg_MOV(ureg, tessinner, inner); |
| 117 | ureg_END(ureg); |
| 118 | |
| 119 | return ureg_create_shader_and_destroy(ureg, &sctx->b); |
| 120 | } |
| 121 | |
Marek Olšák | 93b8b98 | 2018-08-02 18:15:48 -0400 | [diff] [blame] | 122 | /* Create a compute shader implementing clear_buffer or copy_buffer. */ |
| 123 | void *si_create_dma_compute_shader(struct pipe_context *ctx, |
| 124 | unsigned num_dwords_per_thread, |
| 125 | bool dst_stream_cache_policy, bool is_copy) |
| 126 | { |
Marek Olšák | 88efb63 | 2019-07-12 17:37:29 -0400 | [diff] [blame] | 127 | struct si_screen *sscreen = (struct si_screen *)ctx->screen; |
Marek Olšák | 93b8b98 | 2018-08-02 18:15:48 -0400 | [diff] [blame] | 128 | assert(util_is_power_of_two_nonzero(num_dwords_per_thread)); |
| 129 | |
| 130 | unsigned store_qualifier = TGSI_MEMORY_COHERENT | TGSI_MEMORY_RESTRICT; |
| 131 | if (dst_stream_cache_policy) |
| 132 | store_qualifier |= TGSI_MEMORY_STREAM_CACHE_POLICY; |
| 133 | |
| 134 | /* Don't cache loads, because there is no reuse. */ |
| 135 | unsigned load_qualifier = store_qualifier | TGSI_MEMORY_STREAM_CACHE_POLICY; |
| 136 | |
| 137 | unsigned num_mem_ops = MAX2(1, num_dwords_per_thread / 4); |
| 138 | unsigned *inst_dwords = alloca(num_mem_ops * sizeof(unsigned)); |
| 139 | |
| 140 | for (unsigned i = 0; i < num_mem_ops; i++) { |
| 141 | if (i*4 < num_dwords_per_thread) |
| 142 | inst_dwords[i] = MIN2(4, num_dwords_per_thread - i*4); |
| 143 | } |
| 144 | |
| 145 | struct ureg_program *ureg = ureg_create(PIPE_SHADER_COMPUTE); |
| 146 | if (!ureg) |
| 147 | return NULL; |
| 148 | |
Marek Olšák | 88efb63 | 2019-07-12 17:37:29 -0400 | [diff] [blame] | 149 | ureg_property(ureg, TGSI_PROPERTY_CS_FIXED_BLOCK_WIDTH, sscreen->compute_wave_size); |
Marek Olšák | 93b8b98 | 2018-08-02 18:15:48 -0400 | [diff] [blame] | 150 | ureg_property(ureg, TGSI_PROPERTY_CS_FIXED_BLOCK_HEIGHT, 1); |
| 151 | ureg_property(ureg, TGSI_PROPERTY_CS_FIXED_BLOCK_DEPTH, 1); |
| 152 | |
| 153 | struct ureg_src value; |
| 154 | if (!is_copy) { |
| 155 | ureg_property(ureg, TGSI_PROPERTY_CS_USER_DATA_DWORDS, inst_dwords[0]); |
| 156 | value = ureg_DECL_system_value(ureg, TGSI_SEMANTIC_CS_USER_DATA, 0); |
| 157 | } |
| 158 | |
| 159 | struct ureg_src tid = ureg_DECL_system_value(ureg, TGSI_SEMANTIC_THREAD_ID, 0); |
| 160 | struct ureg_src blk = ureg_DECL_system_value(ureg, TGSI_SEMANTIC_BLOCK_ID, 0); |
| 161 | struct ureg_dst store_addr = ureg_writemask(ureg_DECL_temporary(ureg), TGSI_WRITEMASK_X); |
| 162 | struct ureg_dst load_addr = ureg_writemask(ureg_DECL_temporary(ureg), TGSI_WRITEMASK_X); |
| 163 | struct ureg_dst dstbuf = ureg_dst(ureg_DECL_buffer(ureg, 0, false)); |
| 164 | struct ureg_src srcbuf; |
| 165 | struct ureg_src *values = NULL; |
| 166 | |
| 167 | if (is_copy) { |
| 168 | srcbuf = ureg_DECL_buffer(ureg, 1, false); |
| 169 | values = malloc(num_mem_ops * sizeof(struct ureg_src)); |
| 170 | } |
| 171 | |
Marek Olšák | 88efb63 | 2019-07-12 17:37:29 -0400 | [diff] [blame] | 172 | /* If there are multiple stores, the first store writes into 0*wavesize+tid, |
| 173 | * the 2nd store writes into 1*wavesize+tid, the 3rd store writes into 2*wavesize+tid, etc. |
Marek Olšák | 93b8b98 | 2018-08-02 18:15:48 -0400 | [diff] [blame] | 174 | */ |
Marek Olšák | 88efb63 | 2019-07-12 17:37:29 -0400 | [diff] [blame] | 175 | ureg_UMAD(ureg, store_addr, blk, |
| 176 | ureg_imm1u(ureg, sscreen->compute_wave_size * num_mem_ops), tid); |
Marek Olšák | 93b8b98 | 2018-08-02 18:15:48 -0400 | [diff] [blame] | 177 | /* Convert from a "store size unit" into bytes. */ |
| 178 | ureg_UMUL(ureg, store_addr, ureg_src(store_addr), |
| 179 | ureg_imm1u(ureg, 4 * inst_dwords[0])); |
| 180 | ureg_MOV(ureg, load_addr, ureg_src(store_addr)); |
| 181 | |
| 182 | /* Distance between a load and a store for latency hiding. */ |
| 183 | unsigned load_store_distance = is_copy ? 8 : 0; |
| 184 | |
| 185 | for (unsigned i = 0; i < num_mem_ops + load_store_distance; i++) { |
| 186 | int d = i - load_store_distance; |
| 187 | |
| 188 | if (is_copy && i < num_mem_ops) { |
| 189 | if (i) { |
| 190 | ureg_UADD(ureg, load_addr, ureg_src(load_addr), |
Marek Olšák | 88efb63 | 2019-07-12 17:37:29 -0400 | [diff] [blame] | 191 | ureg_imm1u(ureg, 4 * inst_dwords[i] * |
| 192 | sscreen->compute_wave_size)); |
Marek Olšák | 93b8b98 | 2018-08-02 18:15:48 -0400 | [diff] [blame] | 193 | } |
| 194 | |
| 195 | values[i] = ureg_src(ureg_DECL_temporary(ureg)); |
| 196 | struct ureg_dst dst = |
| 197 | ureg_writemask(ureg_dst(values[i]), |
| 198 | u_bit_consecutive(0, inst_dwords[i])); |
| 199 | struct ureg_src srcs[] = {srcbuf, ureg_src(load_addr)}; |
| 200 | ureg_memory_insn(ureg, TGSI_OPCODE_LOAD, &dst, 1, srcs, 2, |
| 201 | load_qualifier, TGSI_TEXTURE_BUFFER, 0); |
| 202 | } |
| 203 | |
| 204 | if (d >= 0) { |
| 205 | if (d) { |
| 206 | ureg_UADD(ureg, store_addr, ureg_src(store_addr), |
Marek Olšák | 88efb63 | 2019-07-12 17:37:29 -0400 | [diff] [blame] | 207 | ureg_imm1u(ureg, 4 * inst_dwords[d] * |
| 208 | sscreen->compute_wave_size)); |
Marek Olšák | 93b8b98 | 2018-08-02 18:15:48 -0400 | [diff] [blame] | 209 | } |
| 210 | |
| 211 | struct ureg_dst dst = |
| 212 | ureg_writemask(dstbuf, u_bit_consecutive(0, inst_dwords[d])); |
| 213 | struct ureg_src srcs[] = |
| 214 | {ureg_src(store_addr), is_copy ? values[d] : value}; |
| 215 | ureg_memory_insn(ureg, TGSI_OPCODE_STORE, &dst, 1, srcs, 2, |
| 216 | store_qualifier, TGSI_TEXTURE_BUFFER, 0); |
| 217 | } |
| 218 | } |
| 219 | ureg_END(ureg); |
| 220 | |
| 221 | struct pipe_compute_state state = {}; |
| 222 | state.ir_type = PIPE_SHADER_IR_TGSI; |
| 223 | state.prog = ureg_get_tokens(ureg, NULL); |
| 224 | |
| 225 | void *cs = ctx->create_compute_state(ctx, &state); |
| 226 | ureg_destroy(ureg); |
Gert Wollny | f1f3640 | 2019-01-31 14:50:41 +0100 | [diff] [blame] | 227 | ureg_free_tokens(state.prog); |
| 228 | |
Marek Olšák | 93b8b98 | 2018-08-02 18:15:48 -0400 | [diff] [blame] | 229 | free(values); |
| 230 | return cs; |
| 231 | } |
| 232 | |
Marek Olšák | 1f21396 | 2019-01-04 19:39:01 -0500 | [diff] [blame] | 233 | /* Create a compute shader that copies DCC from one buffer to another |
| 234 | * where each DCC buffer has a different layout. |
| 235 | * |
| 236 | * image[0]: offset remap table (pairs of <src_offset, dst_offset>), |
| 237 | * 2 pairs are read |
| 238 | * image[1]: DCC source buffer, typed r8_uint |
| 239 | * image[2]: DCC destination buffer, typed r8_uint |
| 240 | */ |
| 241 | void *si_create_dcc_retile_cs(struct pipe_context *ctx) |
| 242 | { |
| 243 | struct ureg_program *ureg = ureg_create(PIPE_SHADER_COMPUTE); |
| 244 | if (!ureg) |
| 245 | return NULL; |
| 246 | |
| 247 | ureg_property(ureg, TGSI_PROPERTY_CS_FIXED_BLOCK_WIDTH, 64); |
| 248 | ureg_property(ureg, TGSI_PROPERTY_CS_FIXED_BLOCK_HEIGHT, 1); |
| 249 | ureg_property(ureg, TGSI_PROPERTY_CS_FIXED_BLOCK_DEPTH, 1); |
| 250 | |
| 251 | /* Compute the global thread ID (in idx). */ |
| 252 | struct ureg_src tid = ureg_DECL_system_value(ureg, TGSI_SEMANTIC_THREAD_ID, 0); |
| 253 | struct ureg_src blk = ureg_DECL_system_value(ureg, TGSI_SEMANTIC_BLOCK_ID, 0); |
| 254 | struct ureg_dst idx = ureg_writemask(ureg_DECL_temporary(ureg), |
| 255 | TGSI_WRITEMASK_X); |
| 256 | ureg_UMAD(ureg, idx, blk, ureg_imm1u(ureg, 64), tid); |
| 257 | |
| 258 | /* Load 2 pairs of offsets for DCC load & store. */ |
| 259 | struct ureg_src map = ureg_DECL_image(ureg, 0, TGSI_TEXTURE_BUFFER, 0, false, false); |
| 260 | struct ureg_dst offsets = ureg_DECL_temporary(ureg); |
| 261 | struct ureg_src map_load_args[] = {map, ureg_src(idx)}; |
| 262 | |
| 263 | ureg_memory_insn(ureg, TGSI_OPCODE_LOAD, &offsets, 1, map_load_args, 2, |
| 264 | TGSI_MEMORY_RESTRICT, TGSI_TEXTURE_BUFFER, 0); |
| 265 | |
| 266 | struct ureg_src dcc_src = ureg_DECL_image(ureg, 1, TGSI_TEXTURE_BUFFER, |
| 267 | 0, false, false); |
| 268 | struct ureg_dst dcc_dst = ureg_dst(ureg_DECL_image(ureg, 2, TGSI_TEXTURE_BUFFER, |
| 269 | 0, true, false)); |
| 270 | struct ureg_dst dcc_value[2]; |
| 271 | |
| 272 | /* Copy DCC values: |
| 273 | * dst[offsets.y] = src[offsets.x]; |
| 274 | * dst[offsets.w] = src[offsets.z]; |
| 275 | */ |
| 276 | for (unsigned i = 0; i < 2; i++) { |
| 277 | dcc_value[i] = ureg_writemask(ureg_DECL_temporary(ureg), TGSI_WRITEMASK_X); |
| 278 | |
| 279 | struct ureg_src load_args[] = |
| 280 | {dcc_src, ureg_scalar(ureg_src(offsets), TGSI_SWIZZLE_X + i*2)}; |
| 281 | ureg_memory_insn(ureg, TGSI_OPCODE_LOAD, &dcc_value[i], 1, load_args, 2, |
| 282 | TGSI_MEMORY_RESTRICT, TGSI_TEXTURE_BUFFER, 0); |
| 283 | } |
| 284 | |
| 285 | dcc_dst = ureg_writemask(dcc_dst, TGSI_WRITEMASK_X); |
| 286 | |
| 287 | for (unsigned i = 0; i < 2; i++) { |
| 288 | struct ureg_src store_args[] = { |
| 289 | ureg_scalar(ureg_src(offsets), TGSI_SWIZZLE_Y + i*2), |
| 290 | ureg_src(dcc_value[i]) |
| 291 | }; |
| 292 | ureg_memory_insn(ureg, TGSI_OPCODE_STORE, &dcc_dst, 1, store_args, 2, |
| 293 | TGSI_MEMORY_RESTRICT, TGSI_TEXTURE_BUFFER, 0); |
| 294 | } |
| 295 | ureg_END(ureg); |
| 296 | |
| 297 | struct pipe_compute_state state = {}; |
| 298 | state.ir_type = PIPE_SHADER_IR_TGSI; |
| 299 | state.prog = ureg_get_tokens(ureg, NULL); |
| 300 | |
| 301 | void *cs = ctx->create_compute_state(ctx, &state); |
| 302 | ureg_destroy(ureg); |
| 303 | return cs; |
| 304 | } |
| 305 | |
Marek Olšák | ac72a6b | 2018-08-02 17:40:05 -0400 | [diff] [blame] | 306 | /* Create the compute shader that is used to collect the results. |
| 307 | * |
| 308 | * One compute grid with a single thread is launched for every query result |
| 309 | * buffer. The thread (optionally) reads a previous summary buffer, then |
| 310 | * accumulates data from the query result buffer, and writes the result either |
| 311 | * to a summary buffer to be consumed by the next grid invocation or to the |
| 312 | * user-supplied buffer. |
| 313 | * |
| 314 | * Data layout: |
| 315 | * |
| 316 | * CONST |
| 317 | * 0.x = end_offset |
| 318 | * 0.y = result_stride |
| 319 | * 0.z = result_count |
| 320 | * 0.w = bit field: |
| 321 | * 1: read previously accumulated values |
| 322 | * 2: write accumulated values for chaining |
| 323 | * 4: write result available |
| 324 | * 8: convert result to boolean (0/1) |
| 325 | * 16: only read one dword and use that as result |
| 326 | * 32: apply timestamp conversion |
| 327 | * 64: store full 64 bits result |
| 328 | * 128: store signed 32 bits result |
| 329 | * 256: SO_OVERFLOW mode: take the difference of two successive half-pairs |
| 330 | * 1.x = fence_offset |
| 331 | * 1.y = pair_stride |
| 332 | * 1.z = pair_count |
| 333 | * |
| 334 | * BUFFER[0] = query result buffer |
| 335 | * BUFFER[1] = previous summary buffer |
| 336 | * BUFFER[2] = next summary buffer or user-supplied buffer |
| 337 | */ |
| 338 | void *si_create_query_result_cs(struct si_context *sctx) |
| 339 | { |
| 340 | /* TEMP[0].xy = accumulated result so far |
| 341 | * TEMP[0].z = result not available |
| 342 | * |
| 343 | * TEMP[1].x = current result index |
| 344 | * TEMP[1].y = current pair index |
| 345 | */ |
| 346 | static const char text_tmpl[] = |
| 347 | "COMP\n" |
| 348 | "PROPERTY CS_FIXED_BLOCK_WIDTH 1\n" |
| 349 | "PROPERTY CS_FIXED_BLOCK_HEIGHT 1\n" |
| 350 | "PROPERTY CS_FIXED_BLOCK_DEPTH 1\n" |
| 351 | "DCL BUFFER[0]\n" |
| 352 | "DCL BUFFER[1]\n" |
| 353 | "DCL BUFFER[2]\n" |
| 354 | "DCL CONST[0][0..1]\n" |
| 355 | "DCL TEMP[0..5]\n" |
| 356 | "IMM[0] UINT32 {0, 31, 2147483647, 4294967295}\n" |
| 357 | "IMM[1] UINT32 {1, 2, 4, 8}\n" |
| 358 | "IMM[2] UINT32 {16, 32, 64, 128}\n" |
| 359 | "IMM[3] UINT32 {1000000, 0, %u, 0}\n" /* for timestamp conversion */ |
| 360 | "IMM[4] UINT32 {256, 0, 0, 0}\n" |
| 361 | |
| 362 | "AND TEMP[5], CONST[0][0].wwww, IMM[2].xxxx\n" |
| 363 | "UIF TEMP[5]\n" |
| 364 | /* Check result availability. */ |
| 365 | "LOAD TEMP[1].x, BUFFER[0], CONST[0][1].xxxx\n" |
| 366 | "ISHR TEMP[0].z, TEMP[1].xxxx, IMM[0].yyyy\n" |
| 367 | "MOV TEMP[1], TEMP[0].zzzz\n" |
| 368 | "NOT TEMP[0].z, TEMP[0].zzzz\n" |
| 369 | |
| 370 | /* Load result if available. */ |
| 371 | "UIF TEMP[1]\n" |
| 372 | "LOAD TEMP[0].xy, BUFFER[0], IMM[0].xxxx\n" |
| 373 | "ENDIF\n" |
| 374 | "ELSE\n" |
| 375 | /* Load previously accumulated result if requested. */ |
| 376 | "MOV TEMP[0], IMM[0].xxxx\n" |
| 377 | "AND TEMP[4], CONST[0][0].wwww, IMM[1].xxxx\n" |
| 378 | "UIF TEMP[4]\n" |
| 379 | "LOAD TEMP[0].xyz, BUFFER[1], IMM[0].xxxx\n" |
| 380 | "ENDIF\n" |
| 381 | |
| 382 | "MOV TEMP[1].x, IMM[0].xxxx\n" |
| 383 | "BGNLOOP\n" |
| 384 | /* Break if accumulated result so far is not available. */ |
| 385 | "UIF TEMP[0].zzzz\n" |
| 386 | "BRK\n" |
| 387 | "ENDIF\n" |
| 388 | |
| 389 | /* Break if result_index >= result_count. */ |
| 390 | "USGE TEMP[5], TEMP[1].xxxx, CONST[0][0].zzzz\n" |
| 391 | "UIF TEMP[5]\n" |
| 392 | "BRK\n" |
| 393 | "ENDIF\n" |
| 394 | |
| 395 | /* Load fence and check result availability */ |
| 396 | "UMAD TEMP[5].x, TEMP[1].xxxx, CONST[0][0].yyyy, CONST[0][1].xxxx\n" |
| 397 | "LOAD TEMP[5].x, BUFFER[0], TEMP[5].xxxx\n" |
| 398 | "ISHR TEMP[0].z, TEMP[5].xxxx, IMM[0].yyyy\n" |
| 399 | "NOT TEMP[0].z, TEMP[0].zzzz\n" |
| 400 | "UIF TEMP[0].zzzz\n" |
| 401 | "BRK\n" |
| 402 | "ENDIF\n" |
| 403 | |
| 404 | "MOV TEMP[1].y, IMM[0].xxxx\n" |
| 405 | "BGNLOOP\n" |
| 406 | /* Load start and end. */ |
| 407 | "UMUL TEMP[5].x, TEMP[1].xxxx, CONST[0][0].yyyy\n" |
| 408 | "UMAD TEMP[5].x, TEMP[1].yyyy, CONST[0][1].yyyy, TEMP[5].xxxx\n" |
| 409 | "LOAD TEMP[2].xy, BUFFER[0], TEMP[5].xxxx\n" |
| 410 | |
| 411 | "UADD TEMP[5].y, TEMP[5].xxxx, CONST[0][0].xxxx\n" |
| 412 | "LOAD TEMP[3].xy, BUFFER[0], TEMP[5].yyyy\n" |
| 413 | |
| 414 | "U64ADD TEMP[4].xy, TEMP[3], -TEMP[2]\n" |
| 415 | |
| 416 | "AND TEMP[5].z, CONST[0][0].wwww, IMM[4].xxxx\n" |
| 417 | "UIF TEMP[5].zzzz\n" |
| 418 | /* Load second start/end half-pair and |
| 419 | * take the difference |
| 420 | */ |
| 421 | "UADD TEMP[5].xy, TEMP[5], IMM[1].wwww\n" |
| 422 | "LOAD TEMP[2].xy, BUFFER[0], TEMP[5].xxxx\n" |
| 423 | "LOAD TEMP[3].xy, BUFFER[0], TEMP[5].yyyy\n" |
| 424 | |
| 425 | "U64ADD TEMP[3].xy, TEMP[3], -TEMP[2]\n" |
| 426 | "U64ADD TEMP[4].xy, TEMP[4], -TEMP[3]\n" |
| 427 | "ENDIF\n" |
| 428 | |
| 429 | "U64ADD TEMP[0].xy, TEMP[0], TEMP[4]\n" |
| 430 | |
| 431 | /* Increment pair index */ |
| 432 | "UADD TEMP[1].y, TEMP[1].yyyy, IMM[1].xxxx\n" |
| 433 | "USGE TEMP[5], TEMP[1].yyyy, CONST[0][1].zzzz\n" |
| 434 | "UIF TEMP[5]\n" |
| 435 | "BRK\n" |
| 436 | "ENDIF\n" |
| 437 | "ENDLOOP\n" |
| 438 | |
| 439 | /* Increment result index */ |
| 440 | "UADD TEMP[1].x, TEMP[1].xxxx, IMM[1].xxxx\n" |
| 441 | "ENDLOOP\n" |
| 442 | "ENDIF\n" |
| 443 | |
| 444 | "AND TEMP[4], CONST[0][0].wwww, IMM[1].yyyy\n" |
| 445 | "UIF TEMP[4]\n" |
| 446 | /* Store accumulated data for chaining. */ |
| 447 | "STORE BUFFER[2].xyz, IMM[0].xxxx, TEMP[0]\n" |
| 448 | "ELSE\n" |
| 449 | "AND TEMP[4], CONST[0][0].wwww, IMM[1].zzzz\n" |
| 450 | "UIF TEMP[4]\n" |
| 451 | /* Store result availability. */ |
| 452 | "NOT TEMP[0].z, TEMP[0]\n" |
| 453 | "AND TEMP[0].z, TEMP[0].zzzz, IMM[1].xxxx\n" |
| 454 | "STORE BUFFER[2].x, IMM[0].xxxx, TEMP[0].zzzz\n" |
| 455 | |
| 456 | "AND TEMP[4], CONST[0][0].wwww, IMM[2].zzzz\n" |
| 457 | "UIF TEMP[4]\n" |
| 458 | "STORE BUFFER[2].y, IMM[0].xxxx, IMM[0].xxxx\n" |
| 459 | "ENDIF\n" |
| 460 | "ELSE\n" |
| 461 | /* Store result if it is available. */ |
| 462 | "NOT TEMP[4], TEMP[0].zzzz\n" |
| 463 | "UIF TEMP[4]\n" |
| 464 | /* Apply timestamp conversion */ |
| 465 | "AND TEMP[4], CONST[0][0].wwww, IMM[2].yyyy\n" |
| 466 | "UIF TEMP[4]\n" |
| 467 | "U64MUL TEMP[0].xy, TEMP[0], IMM[3].xyxy\n" |
| 468 | "U64DIV TEMP[0].xy, TEMP[0], IMM[3].zwzw\n" |
| 469 | "ENDIF\n" |
| 470 | |
| 471 | /* Convert to boolean */ |
| 472 | "AND TEMP[4], CONST[0][0].wwww, IMM[1].wwww\n" |
| 473 | "UIF TEMP[4]\n" |
| 474 | "U64SNE TEMP[0].x, TEMP[0].xyxy, IMM[4].zwzw\n" |
| 475 | "AND TEMP[0].x, TEMP[0].xxxx, IMM[1].xxxx\n" |
| 476 | "MOV TEMP[0].y, IMM[0].xxxx\n" |
| 477 | "ENDIF\n" |
| 478 | |
| 479 | "AND TEMP[4], CONST[0][0].wwww, IMM[2].zzzz\n" |
| 480 | "UIF TEMP[4]\n" |
| 481 | "STORE BUFFER[2].xy, IMM[0].xxxx, TEMP[0].xyxy\n" |
| 482 | "ELSE\n" |
| 483 | /* Clamping */ |
| 484 | "UIF TEMP[0].yyyy\n" |
| 485 | "MOV TEMP[0].x, IMM[0].wwww\n" |
| 486 | "ENDIF\n" |
| 487 | |
| 488 | "AND TEMP[4], CONST[0][0].wwww, IMM[2].wwww\n" |
| 489 | "UIF TEMP[4]\n" |
| 490 | "UMIN TEMP[0].x, TEMP[0].xxxx, IMM[0].zzzz\n" |
| 491 | "ENDIF\n" |
| 492 | |
| 493 | "STORE BUFFER[2].x, IMM[0].xxxx, TEMP[0].xxxx\n" |
| 494 | "ENDIF\n" |
| 495 | "ENDIF\n" |
| 496 | "ENDIF\n" |
| 497 | "ENDIF\n" |
| 498 | |
| 499 | "END\n"; |
| 500 | |
| 501 | char text[sizeof(text_tmpl) + 32]; |
| 502 | struct tgsi_token tokens[1024]; |
| 503 | struct pipe_compute_state state = {}; |
| 504 | |
| 505 | /* Hard code the frequency into the shader so that the backend can |
| 506 | * use the full range of optimizations for divide-by-constant. |
| 507 | */ |
| 508 | snprintf(text, sizeof(text), text_tmpl, |
| 509 | sctx->screen->info.clock_crystal_freq); |
| 510 | |
| 511 | if (!tgsi_text_translate(text, tokens, ARRAY_SIZE(tokens))) { |
| 512 | assert(false); |
| 513 | return NULL; |
| 514 | } |
| 515 | |
| 516 | state.ir_type = PIPE_SHADER_IR_TGSI; |
| 517 | state.prog = tokens; |
| 518 | |
| 519 | return sctx->b.create_compute_state(&sctx->b, &state); |
| 520 | } |
Sonny Jiang | 1b25d34 | 2018-12-03 12:36:33 -0500 | [diff] [blame] | 521 | |
| 522 | /* Create a compute shader implementing copy_image. |
| 523 | * Luckily, this works with all texture targets except 1D_ARRAY. |
| 524 | */ |
| 525 | void *si_create_copy_image_compute_shader(struct pipe_context *ctx) |
| 526 | { |
| 527 | static const char text[] = |
| 528 | "COMP\n" |
| 529 | "PROPERTY CS_FIXED_BLOCK_WIDTH 8\n" |
| 530 | "PROPERTY CS_FIXED_BLOCK_HEIGHT 8\n" |
| 531 | "PROPERTY CS_FIXED_BLOCK_DEPTH 1\n" |
| 532 | "DCL SV[0], THREAD_ID\n" |
| 533 | "DCL SV[1], BLOCK_ID\n" |
| 534 | "DCL IMAGE[0], 2D_ARRAY, PIPE_FORMAT_R32G32B32A32_FLOAT, WR\n" |
| 535 | "DCL IMAGE[1], 2D_ARRAY, PIPE_FORMAT_R32G32B32A32_FLOAT, WR\n" |
| 536 | "DCL CONST[0][0..1]\n" // 0:xyzw 1:xyzw |
| 537 | "DCL TEMP[0..4], LOCAL\n" |
| 538 | "IMM[0] UINT32 {8, 1, 0, 0}\n" |
| 539 | "MOV TEMP[0].xyz, CONST[0][0].xyzw\n" |
| 540 | "UMAD TEMP[1].xyz, SV[1].xyzz, IMM[0].xxyy, SV[0].xyzz\n" |
| 541 | "UADD TEMP[2].xyz, TEMP[1].xyzx, TEMP[0].xyzx\n" |
| 542 | "LOAD TEMP[3], IMAGE[0], TEMP[2].xyzx, 2D_ARRAY, PIPE_FORMAT_R32G32B32A32_FLOAT\n" |
| 543 | "MOV TEMP[4].xyz, CONST[0][1].xyzw\n" |
| 544 | "UADD TEMP[2].xyz, TEMP[1].xyzx, TEMP[4].xyzx\n" |
| 545 | "STORE IMAGE[1], TEMP[2].xyzz, TEMP[3], 2D_ARRAY, PIPE_FORMAT_R32G32B32A32_FLOAT\n" |
| 546 | "END\n"; |
| 547 | |
| 548 | struct tgsi_token tokens[1024]; |
| 549 | struct pipe_compute_state state = {0}; |
| 550 | |
| 551 | if (!tgsi_text_translate(text, tokens, ARRAY_SIZE(tokens))) { |
| 552 | assert(false); |
| 553 | return NULL; |
| 554 | } |
| 555 | |
| 556 | state.ir_type = PIPE_SHADER_IR_TGSI; |
| 557 | state.prog = tokens; |
| 558 | |
| 559 | return ctx->create_compute_state(ctx, &state); |
| 560 | } |
| 561 | |
| 562 | void *si_create_copy_image_compute_shader_1d_array(struct pipe_context *ctx) |
| 563 | { |
| 564 | static const char text[] = |
| 565 | "COMP\n" |
| 566 | "PROPERTY CS_FIXED_BLOCK_WIDTH 64\n" |
| 567 | "PROPERTY CS_FIXED_BLOCK_HEIGHT 1\n" |
| 568 | "PROPERTY CS_FIXED_BLOCK_DEPTH 1\n" |
| 569 | "DCL SV[0], THREAD_ID\n" |
| 570 | "DCL SV[1], BLOCK_ID\n" |
| 571 | "DCL IMAGE[0], 1D_ARRAY, PIPE_FORMAT_R32G32B32A32_FLOAT, WR\n" |
| 572 | "DCL IMAGE[1], 1D_ARRAY, PIPE_FORMAT_R32G32B32A32_FLOAT, WR\n" |
| 573 | "DCL CONST[0][0..1]\n" // 0:xyzw 1:xyzw |
| 574 | "DCL TEMP[0..4], LOCAL\n" |
| 575 | "IMM[0] UINT32 {64, 1, 0, 0}\n" |
| 576 | "MOV TEMP[0].xy, CONST[0][0].xzzw\n" |
| 577 | "UMAD TEMP[1].xy, SV[1].xyzz, IMM[0].xyyy, SV[0].xyzz\n" |
| 578 | "UADD TEMP[2].xy, TEMP[1].xyzx, TEMP[0].xyzx\n" |
| 579 | "LOAD TEMP[3], IMAGE[0], TEMP[2].xyzx, 1D_ARRAY, PIPE_FORMAT_R32G32B32A32_FLOAT\n" |
| 580 | "MOV TEMP[4].xy, CONST[0][1].xzzw\n" |
| 581 | "UADD TEMP[2].xy, TEMP[1].xyzx, TEMP[4].xyzx\n" |
| 582 | "STORE IMAGE[1], TEMP[2].xyzz, TEMP[3], 1D_ARRAY, PIPE_FORMAT_R32G32B32A32_FLOAT\n" |
| 583 | "END\n"; |
| 584 | |
| 585 | struct tgsi_token tokens[1024]; |
| 586 | struct pipe_compute_state state = {0}; |
| 587 | |
| 588 | if (!tgsi_text_translate(text, tokens, ARRAY_SIZE(tokens))) { |
| 589 | assert(false); |
| 590 | return NULL; |
| 591 | } |
| 592 | |
| 593 | state.ir_type = PIPE_SHADER_IR_TGSI; |
| 594 | state.prog = tokens; |
| 595 | |
| 596 | return ctx->create_compute_state(ctx, &state); |
| 597 | } |
Sonny Jiang | 984fd73 | 2019-01-21 18:16:40 -0500 | [diff] [blame] | 598 | |
| 599 | void *si_clear_render_target_shader(struct pipe_context *ctx) |
| 600 | { |
| 601 | static const char text[] = |
| 602 | "COMP\n" |
| 603 | "PROPERTY CS_FIXED_BLOCK_WIDTH 8\n" |
| 604 | "PROPERTY CS_FIXED_BLOCK_HEIGHT 8\n" |
| 605 | "PROPERTY CS_FIXED_BLOCK_DEPTH 1\n" |
| 606 | "DCL SV[0], THREAD_ID\n" |
| 607 | "DCL SV[1], BLOCK_ID\n" |
| 608 | "DCL IMAGE[0], 2D_ARRAY, PIPE_FORMAT_R32G32B32A32_FLOAT, WR\n" |
| 609 | "DCL CONST[0][0..1]\n" // 0:xyzw 1:xyzw |
| 610 | "DCL TEMP[0..3], LOCAL\n" |
| 611 | "IMM[0] UINT32 {8, 1, 0, 0}\n" |
| 612 | "MOV TEMP[0].xyz, CONST[0][0].xyzw\n" |
| 613 | "UMAD TEMP[1].xyz, SV[1].xyzz, IMM[0].xxyy, SV[0].xyzz\n" |
| 614 | "UADD TEMP[2].xyz, TEMP[1].xyzx, TEMP[0].xyzx\n" |
| 615 | "MOV TEMP[3].xyzw, CONST[0][1].xyzw\n" |
| 616 | "STORE IMAGE[0], TEMP[2].xyzz, TEMP[3], 2D_ARRAY, PIPE_FORMAT_R32G32B32A32_FLOAT\n" |
| 617 | "END\n"; |
| 618 | |
| 619 | struct tgsi_token tokens[1024]; |
| 620 | struct pipe_compute_state state = {0}; |
| 621 | |
| 622 | if (!tgsi_text_translate(text, tokens, ARRAY_SIZE(tokens))) { |
| 623 | assert(false); |
| 624 | return NULL; |
| 625 | } |
| 626 | |
| 627 | state.ir_type = PIPE_SHADER_IR_TGSI; |
| 628 | state.prog = tokens; |
| 629 | |
| 630 | return ctx->create_compute_state(ctx, &state); |
| 631 | } |
| 632 | |
| 633 | /* TODO: Didn't really test 1D_ARRAY */ |
| 634 | void *si_clear_render_target_shader_1d_array(struct pipe_context *ctx) |
| 635 | { |
| 636 | static const char text[] = |
| 637 | "COMP\n" |
| 638 | "PROPERTY CS_FIXED_BLOCK_WIDTH 64\n" |
| 639 | "PROPERTY CS_FIXED_BLOCK_HEIGHT 1\n" |
| 640 | "PROPERTY CS_FIXED_BLOCK_DEPTH 1\n" |
| 641 | "DCL SV[0], THREAD_ID\n" |
| 642 | "DCL SV[1], BLOCK_ID\n" |
| 643 | "DCL IMAGE[0], 1D_ARRAY, PIPE_FORMAT_R32G32B32A32_FLOAT, WR\n" |
| 644 | "DCL CONST[0][0..1]\n" // 0:xyzw 1:xyzw |
| 645 | "DCL TEMP[0..3], LOCAL\n" |
| 646 | "IMM[0] UINT32 {64, 1, 0, 0}\n" |
| 647 | "MOV TEMP[0].xy, CONST[0][0].xzzw\n" |
| 648 | "UMAD TEMP[1].xy, SV[1].xyzz, IMM[0].xyyy, SV[0].xyzz\n" |
| 649 | "UADD TEMP[2].xy, TEMP[1].xyzx, TEMP[0].xyzx\n" |
| 650 | "MOV TEMP[3].xyzw, CONST[0][1].xyzw\n" |
| 651 | "STORE IMAGE[0], TEMP[2].xyzz, TEMP[3], 1D_ARRAY, PIPE_FORMAT_R32G32B32A32_FLOAT\n" |
| 652 | "END\n"; |
| 653 | |
| 654 | struct tgsi_token tokens[1024]; |
| 655 | struct pipe_compute_state state = {0}; |
| 656 | |
| 657 | if (!tgsi_text_translate(text, tokens, ARRAY_SIZE(tokens))) { |
| 658 | assert(false); |
| 659 | return NULL; |
| 660 | } |
| 661 | |
| 662 | state.ir_type = PIPE_SHADER_IR_TGSI; |
| 663 | state.prog = tokens; |
| 664 | |
| 665 | return ctx->create_compute_state(ctx, &state); |
| 666 | } |
Nicolai Hähnle | 792a638 | 2018-09-19 14:53:35 +0200 | [diff] [blame] | 667 | |
| 668 | /* Create the compute shader that is used to collect the results of gfx10+ |
| 669 | * shader queries. |
| 670 | * |
| 671 | * One compute grid with a single thread is launched for every query result |
| 672 | * buffer. The thread (optionally) reads a previous summary buffer, then |
| 673 | * accumulates data from the query result buffer, and writes the result either |
| 674 | * to a summary buffer to be consumed by the next grid invocation or to the |
| 675 | * user-supplied buffer. |
| 676 | * |
| 677 | * Data layout: |
| 678 | * |
| 679 | * BUFFER[0] = query result buffer (layout is defined by gfx10_sh_query_buffer_mem) |
| 680 | * BUFFER[1] = previous summary buffer |
| 681 | * BUFFER[2] = next summary buffer or user-supplied buffer |
| 682 | * |
| 683 | * CONST |
| 684 | * 0.x = config; the low 3 bits indicate the mode: |
| 685 | * 0: sum up counts |
| 686 | * 1: determine result availability and write it as a boolean |
| 687 | * 2: SO_OVERFLOW |
| 688 | * 3: SO_ANY_OVERFLOW |
| 689 | * the remaining bits form a bitfield: |
| 690 | * 8: write result as a 64-bit value |
| 691 | * 0.y = offset in bytes to counts or stream for SO_OVERFLOW mode |
| 692 | * 0.z = chain bit field: |
| 693 | * 1: have previous summary buffer |
| 694 | * 2: write next summary buffer |
| 695 | * 0.w = result_count |
| 696 | */ |
| 697 | void *gfx10_create_sh_query_result_cs(struct si_context *sctx) |
| 698 | { |
| 699 | /* TEMP[0].x = accumulated result so far |
| 700 | * TEMP[0].y = result missing |
| 701 | * TEMP[0].z = whether we're in overflow mode |
| 702 | */ |
| 703 | static const char text_tmpl[] = |
| 704 | "COMP\n" |
| 705 | "PROPERTY CS_FIXED_BLOCK_WIDTH 1\n" |
| 706 | "PROPERTY CS_FIXED_BLOCK_HEIGHT 1\n" |
| 707 | "PROPERTY CS_FIXED_BLOCK_DEPTH 1\n" |
| 708 | "DCL BUFFER[0]\n" |
| 709 | "DCL BUFFER[1]\n" |
| 710 | "DCL BUFFER[2]\n" |
| 711 | "DCL CONST[0][0..0]\n" |
| 712 | "DCL TEMP[0..5]\n" |
| 713 | "IMM[0] UINT32 {0, 7, 0, 4294967295}\n" |
| 714 | "IMM[1] UINT32 {1, 2, 4, 8}\n" |
| 715 | "IMM[2] UINT32 {16, 32, 64, 128}\n" |
| 716 | |
| 717 | /* |
| 718 | acc_result = 0; |
| 719 | acc_missing = 0; |
| 720 | if (chain & 1) { |
| 721 | acc_result = buffer[1][0]; |
| 722 | acc_missing = buffer[1][1]; |
| 723 | } |
| 724 | */ |
| 725 | "MOV TEMP[0].xy, IMM[0].xxxx\n" |
| 726 | "AND TEMP[5], CONST[0][0].zzzz, IMM[1].xxxx\n" |
| 727 | "UIF TEMP[5]\n" |
| 728 | "LOAD TEMP[0].xy, BUFFER[1], IMM[0].xxxx\n" |
| 729 | "ENDIF\n" |
| 730 | |
| 731 | /* |
| 732 | is_overflow (TEMP[0].z) = (config & 7) >= 2; |
| 733 | result_remaining (TEMP[1].x) = (is_overflow && acc_result) ? 0 : result_count; |
| 734 | base_offset (TEMP[1].y) = 0; |
| 735 | for (;;) { |
| 736 | if (!result_remaining) |
| 737 | break; |
| 738 | result_remaining--; |
| 739 | */ |
| 740 | "AND TEMP[5].x, CONST[0][0].xxxx, IMM[0].yyyy\n" |
| 741 | "USGE TEMP[0].z, TEMP[5].xxxx, IMM[1].yyyy\n" |
| 742 | |
| 743 | "AND TEMP[5].x, TEMP[0].zzzz, TEMP[0].xxxx\n" |
| 744 | "UCMP TEMP[1].x, TEMP[5].xxxx, IMM[0].xxxx, CONST[0][0].wwww\n" |
| 745 | "MOV TEMP[1].y, IMM[0].xxxx\n" |
| 746 | |
| 747 | "BGNLOOP\n" |
| 748 | "USEQ TEMP[5], TEMP[1].xxxx, IMM[0].xxxx\n" |
| 749 | "UIF TEMP[5]\n" |
| 750 | "BRK\n" |
| 751 | "ENDIF\n" |
| 752 | "UADD TEMP[1].x, TEMP[1].xxxx, IMM[0].wwww\n" |
| 753 | |
| 754 | /* |
| 755 | fence = buffer[0]@(base_offset + 32); |
| 756 | if (!fence) { |
| 757 | acc_missing = ~0u; |
| 758 | break; |
| 759 | } |
| 760 | */ |
| 761 | "UADD TEMP[5].x, TEMP[1].yyyy, IMM[2].yyyy\n" |
| 762 | "LOAD TEMP[5].x, BUFFER[0], TEMP[5].xxxx\n" |
| 763 | "USEQ TEMP[5], TEMP[5].xxxx, IMM[0].xxxx\n" |
| 764 | "UIF TEMP[5]\n" |
| 765 | "MOV TEMP[0].y, TEMP[5].xxxx\n" |
| 766 | "BRK\n" |
| 767 | "ENDIF\n" |
| 768 | |
| 769 | /* |
| 770 | stream_offset (TEMP[2].x) = base_offset + offset; |
| 771 | |
| 772 | if (!(config & 7)) { |
| 773 | acc_result += buffer[0]@stream_offset; |
| 774 | } |
| 775 | */ |
| 776 | "UADD TEMP[2].x, TEMP[1].yyyy, CONST[0][0].yyyy\n" |
| 777 | |
| 778 | "AND TEMP[5].x, CONST[0][0].xxxx, IMM[0].yyyy\n" |
| 779 | "USEQ TEMP[5], TEMP[5].xxxx, IMM[0].xxxx\n" |
| 780 | "UIF TEMP[5]\n" |
| 781 | "LOAD TEMP[5].x, BUFFER[0], TEMP[2].xxxx\n" |
| 782 | "UADD TEMP[0].x, TEMP[0].xxxx, TEMP[5].xxxx\n" |
| 783 | "ENDIF\n" |
| 784 | |
| 785 | /* |
| 786 | if ((config & 7) >= 2) { |
| 787 | count (TEMP[2].y) = (config & 1) ? 4 : 1; |
| 788 | */ |
| 789 | "AND TEMP[5].x, CONST[0][0].xxxx, IMM[0].yyyy\n" |
| 790 | "USGE TEMP[5], TEMP[5].xxxx, IMM[1].yyyy\n" |
| 791 | "UIF TEMP[5]\n" |
| 792 | "AND TEMP[5].x, CONST[0][0].xxxx, IMM[1].xxxx\n" |
| 793 | "UCMP TEMP[2].y, TEMP[5].xxxx, IMM[1].zzzz, IMM[1].xxxx\n" |
| 794 | |
| 795 | /* |
| 796 | do { |
| 797 | generated = buffer[0]@stream_offset; |
| 798 | emitted = buffer[0]@(stream_offset + 16); |
| 799 | if (generated != emitted) { |
| 800 | acc_result = 1; |
| 801 | result_remaining = 0; |
| 802 | break; |
| 803 | } |
| 804 | |
| 805 | stream_offset += 4; |
| 806 | } while (--count); |
| 807 | */ |
| 808 | "BGNLOOP\n" |
| 809 | "UADD TEMP[5].x, TEMP[2].xxxx, IMM[2].xxxx\n" |
| 810 | "LOAD TEMP[4].x, BUFFER[0], TEMP[2].xxxx\n" |
| 811 | "LOAD TEMP[4].y, BUFFER[0], TEMP[5].xxxx\n" |
| 812 | "USNE TEMP[5], TEMP[4].xxxx, TEMP[4].yyyy\n" |
| 813 | "UIF TEMP[5]\n" |
| 814 | "MOV TEMP[0].x, IMM[1].xxxx\n" |
| 815 | "MOV TEMP[1].y, IMM[0].xxxx\n" |
| 816 | "BRK\n" |
| 817 | "ENDIF\n" |
| 818 | |
| 819 | "UADD TEMP[2].y, TEMP[2].yyyy, IMM[0].wwww\n" |
| 820 | "USEQ TEMP[5], TEMP[2].yyyy, IMM[0].xxxx\n" |
| 821 | "UIF TEMP[5]\n" |
| 822 | "BRK\n" |
| 823 | "ENDIF\n" |
| 824 | "UADD TEMP[2].x, TEMP[2].xxxx, IMM[1].zzzz\n" |
| 825 | "ENDLOOP\n" |
| 826 | "ENDIF\n" |
| 827 | |
| 828 | /* |
| 829 | base_offset += 64; |
| 830 | } // end outer loop |
| 831 | */ |
| 832 | "UADD TEMP[1].y, TEMP[1].yyyy, IMM[2].zzzz\n" |
| 833 | "ENDLOOP\n" |
| 834 | |
| 835 | /* |
| 836 | if (chain & 2) { |
| 837 | buffer[2][0] = acc_result; |
| 838 | buffer[2][1] = acc_missing; |
| 839 | } else { |
| 840 | */ |
| 841 | "AND TEMP[5], CONST[0][0].zzzz, IMM[1].yyyy\n" |
| 842 | "UIF TEMP[5]\n" |
| 843 | "STORE BUFFER[2].xy, IMM[0].xxxx, TEMP[0]\n" |
| 844 | "ELSE\n" |
| 845 | |
| 846 | /* |
| 847 | if ((config & 7) == 1) { |
| 848 | acc_result = acc_missing ? 0 : 1; |
| 849 | acc_missing = 0; |
| 850 | } |
| 851 | */ |
| 852 | "AND TEMP[5], CONST[0][0].xxxx, IMM[0].yyyy\n" |
| 853 | "USEQ TEMP[5], TEMP[5].xxxx, IMM[1].xxxx\n" |
| 854 | "UIF TEMP[5]\n" |
| 855 | "UCMP TEMP[0].x, TEMP[0].yyyy, IMM[0].xxxx, IMM[1].xxxx\n" |
| 856 | "MOV TEMP[0].y, IMM[0].xxxx\n" |
| 857 | "ENDIF\n" |
| 858 | |
| 859 | /* |
| 860 | if (!acc_missing) { |
| 861 | buffer[2][0] = acc_result; |
| 862 | if (config & 8) |
| 863 | buffer[2][1] = 0; |
| 864 | } |
| 865 | */ |
| 866 | "USEQ TEMP[5], TEMP[0].yyyy, IMM[0].xxxx\n" |
| 867 | "UIF TEMP[5]\n" |
| 868 | "STORE BUFFER[2].x, IMM[0].xxxx, TEMP[0].xxxx\n" |
| 869 | |
| 870 | "AND TEMP[5], CONST[0][0].xxxx, IMM[1].wwww\n" |
| 871 | "UIF TEMP[5]\n" |
| 872 | "STORE BUFFER[2].x, IMM[1].zzzz, TEMP[0].yyyy\n" |
| 873 | "ENDIF\n" |
| 874 | "ENDIF\n" |
| 875 | "ENDIF\n" |
| 876 | |
| 877 | "END\n"; |
| 878 | |
| 879 | struct tgsi_token tokens[1024]; |
| 880 | struct pipe_compute_state state = {}; |
| 881 | |
| 882 | if (!tgsi_text_translate(text_tmpl, tokens, ARRAY_SIZE(tokens))) { |
| 883 | assert(false); |
| 884 | return NULL; |
| 885 | } |
| 886 | |
| 887 | state.ir_type = PIPE_SHADER_IR_TGSI; |
| 888 | state.prog = tokens; |
| 889 | |
| 890 | return sctx->b.create_compute_state(&sctx->b, &state); |
| 891 | } |