blob: d797bb438585f071147d09a27e0420bdf47455ba [file] [log] [blame]
Rob Clark6173cc12012-10-27 11:07:34 -05001/* -*- mode: C; c-file-style: "k&r"; tab-width 4; indent-tabs-mode: t; -*- */
2
3/*
4 * Copyright (C) 2012 Rob Clark <robclark@freedesktop.org>
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
15 * Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
23 * SOFTWARE.
24 *
25 * Authors:
26 * Rob Clark <robclark@freedesktop.org>
27 */
28
29
30#include "pipe/p_defines.h"
31#include "pipe/p_screen.h"
32#include "pipe/p_state.h"
33
34#include "util/u_memory.h"
35#include "util/u_inlines.h"
36#include "util/u_format.h"
37#include "util/u_format_s3tc.h"
38#include "util/u_string.h"
Rob Clark634fb832013-03-25 14:57:24 -040039#include "util/u_debug.h"
Rob Clark6173cc12012-10-27 11:07:34 -050040
41#include "os/os_time.h"
42
43#include <stdio.h>
44#include <errno.h>
45#include <stdlib.h>
46
Rob Clark6173cc12012-10-27 11:07:34 -050047#include "freedreno_screen.h"
48#include "freedreno_resource.h"
49#include "freedreno_fence.h"
Rob Clark646c16a2014-01-07 21:39:13 -050050#include "freedreno_query.h"
Rob Clark6173cc12012-10-27 11:07:34 -050051#include "freedreno_util.h"
52
Emil Velikov458d03a2014-07-28 19:45:09 +010053#include "a2xx/fd2_screen.h"
54#include "a3xx/fd3_screen.h"
Rob Clark18c317b2013-05-26 17:13:27 -040055
Rob Clark6173cc12012-10-27 11:07:34 -050056/* XXX this should go away */
57#include "state_tracker/drm_driver.h"
58
Rob Clark634fb832013-03-25 14:57:24 -040059static const struct debug_named_value debug_options[] = {
60 {"msgs", FD_DBG_MSGS, "Print debug messages"},
61 {"disasm", FD_DBG_DISASM, "Dump TGSI and adreno shader disassembly"},
Rob Clark9495ee12013-04-24 10:50:51 -040062 {"dclear", FD_DBG_DCLEAR, "Mark all state dirty after clear"},
63 {"dgmem", FD_DBG_DGMEM, "Mark all state dirty after GMEM tile pass"},
Rob Clarkc2babfc2013-05-29 10:16:33 -040064 {"dscis", FD_DBG_DSCIS, "Disable scissor optimization"},
Rob Clark1a42d4e2013-09-06 18:21:25 -040065 {"direct", FD_DBG_DIRECT, "Force inline (SS_DIRECT) state loads"},
Rob Clarkc756a3e2013-09-10 11:35:58 -040066 {"dbypass", FD_DBG_DBYPASS,"Disable GMEM bypass"},
Rob Clarka53fe222013-10-31 09:59:49 -040067 {"fraghalf", FD_DBG_FRAGHALF, "Use half-precision in fragment shader"},
Rob Clark1b886072014-02-03 11:28:30 -050068 {"nobin", FD_DBG_NOBIN, "Disable hw binning"},
69 {"noopt", FD_DBG_NOOPT , "Disable optimization passes in compiler"},
70 {"optmsgs", FD_DBG_OPTMSGS,"Enable optimizater debug messages"},
71 {"optdump", FD_DBG_OPTDUMP,"Dump shader DAG to .dot files"},
Rob Clarke1896942014-05-14 11:06:21 -040072 {"glsl130", FD_DBG_GLSL130,"Temporary flag to enable GLSL 130 on a3xx+"},
Rob Clark634fb832013-03-25 14:57:24 -040073 DEBUG_NAMED_VALUE_END
74};
75
76DEBUG_GET_ONCE_FLAGS_OPTION(fd_mesa_debug, "FD_MESA_DEBUG", debug_options, 0)
77
Rob Clark6173cc12012-10-27 11:07:34 -050078int fd_mesa_debug = 0;
Rob Clark1b886072014-02-03 11:28:30 -050079bool fd_binning_enabled = true;
Rob Clarke1896942014-05-14 11:06:21 -040080static bool glsl130 = false;
Rob Clark6173cc12012-10-27 11:07:34 -050081
82static const char *
83fd_screen_get_name(struct pipe_screen *pscreen)
84{
85 static char buffer[128];
86 util_snprintf(buffer, sizeof(buffer), "FD%03d",
87 fd_screen(pscreen)->device_id);
88 return buffer;
89}
90
91static const char *
92fd_screen_get_vendor(struct pipe_screen *pscreen)
93{
94 return "freedreno";
95}
96
97static uint64_t
98fd_screen_get_timestamp(struct pipe_screen *pscreen)
99{
100 int64_t cpu_time = os_time_get() * 1000;
101 return cpu_time + fd_screen(pscreen)->cpu_gpu_time_delta;
102}
103
104static void
105fd_screen_fence_ref(struct pipe_screen *pscreen,
106 struct pipe_fence_handle **ptr,
107 struct pipe_fence_handle *pfence)
108{
109 fd_fence_ref(fd_fence(pfence), (struct fd_fence **)ptr);
110}
111
112static boolean
113fd_screen_fence_signalled(struct pipe_screen *screen,
114 struct pipe_fence_handle *pfence)
115{
116 return fd_fence_signalled(fd_fence(pfence));
117}
118
119static boolean
120fd_screen_fence_finish(struct pipe_screen *screen,
121 struct pipe_fence_handle *pfence,
122 uint64_t timeout)
123{
124 return fd_fence_wait(fd_fence(pfence));
125}
126
127static void
128fd_screen_destroy(struct pipe_screen *pscreen)
129{
Rob Clark38d8b022013-04-22 13:42:55 -0400130 struct fd_screen *screen = fd_screen(pscreen);
131
132 if (screen->pipe)
133 fd_pipe_del(screen->pipe);
134
135 if (screen->dev)
136 fd_device_del(screen->dev);
137
138 free(screen);
Rob Clark6173cc12012-10-27 11:07:34 -0500139}
140
141/*
Rob Clark18c317b2013-05-26 17:13:27 -0400142TODO either move caps to a2xx/a3xx specific code, or maybe have some
143tables for things that differ if the delta is not too much..
Rob Clark6173cc12012-10-27 11:07:34 -0500144 */
145static int
146fd_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
147{
Rob Clarkf999c132014-05-11 14:15:32 -0400148 struct fd_screen *screen = fd_screen(pscreen);
149
Rob Clark6173cc12012-10-27 11:07:34 -0500150 /* this is probably not totally correct.. but it's a start: */
151 switch (param) {
152 /* Supported features (boolean caps). */
153 case PIPE_CAP_NPOT_TEXTURES:
Ilia Mirkin12d39b42013-10-04 04:32:15 -0400154 case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
Rob Clark6173cc12012-10-27 11:07:34 -0500155 case PIPE_CAP_TWO_SIDED_STENCIL:
156 case PIPE_CAP_ANISOTROPIC_FILTER:
157 case PIPE_CAP_POINT_SPRITE:
158 case PIPE_CAP_TEXTURE_SHADOW_MAP:
159 case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
160 case PIPE_CAP_BLEND_EQUATION_SEPARATE:
161 case PIPE_CAP_TEXTURE_SWIZZLE:
Rob Clark6173cc12012-10-27 11:07:34 -0500162 case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
163 case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
164 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
165 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
Rob Clark6173cc12012-10-27 11:07:34 -0500166 case PIPE_CAP_SEAMLESS_CUBE_MAP:
Rob Clark6173cc12012-10-27 11:07:34 -0500167 case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
168 case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
169 case PIPE_CAP_TGSI_INSTANCEID:
170 case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
171 case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
172 case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
173 case PIPE_CAP_COMPUTE:
174 case PIPE_CAP_START_INSTANCE:
175 case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
Rob Clark6173cc12012-10-27 11:07:34 -0500176 case PIPE_CAP_USER_CONSTANT_BUFFERS:
Rob Clark28686392014-05-24 10:07:13 -0400177 case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
Rob Clark6173cc12012-10-27 11:07:34 -0500178 return 1;
Rob Clark980f1cf2013-03-25 11:55:18 -0400179
Rob Clark8d27be22014-01-14 13:03:20 -0500180 case PIPE_CAP_SHADER_STENCIL_EXPORT:
Christoph Bumiller8acaf862013-03-15 22:11:31 +0100181 case PIPE_CAP_TGSI_TEXCOORD:
Rob Clark980f1cf2013-03-25 11:55:18 -0400182 case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
Rob Clark6f84f642014-05-18 08:02:08 -0400183 case PIPE_CAP_CONDITIONAL_RENDER:
184 case PIPE_CAP_PRIMITIVE_RESTART:
Rob Clark28686392014-05-24 10:07:13 -0400185 case PIPE_CAP_TEXTURE_MULTISAMPLE:
186 case PIPE_CAP_TEXTURE_BARRIER:
187 case PIPE_CAP_SM3:
Christoph Bumiller8acaf862013-03-15 22:11:31 +0100188 return 0;
Rob Clark6173cc12012-10-27 11:07:34 -0500189
190 case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
191 return 256;
192
193 case PIPE_CAP_GLSL_FEATURE_LEVEL:
Rob Clarke1896942014-05-14 11:06:21 -0400194 return ((screen->gpu_id >= 300) && glsl130) ? 130 : 120;
Rob Clark6173cc12012-10-27 11:07:34 -0500195
196 /* Unsupported features. */
197 case PIPE_CAP_INDEP_BLEND_ENABLE:
198 case PIPE_CAP_INDEP_BLEND_FUNC:
199 case PIPE_CAP_DEPTH_CLIP_DISABLE:
200 case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
201 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
202 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
Rob Clark6173cc12012-10-27 11:07:34 -0500203 case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
204 case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
205 case PIPE_CAP_VERTEX_COLOR_CLAMPED:
206 case PIPE_CAP_USER_VERTEX_BUFFERS:
207 case PIPE_CAP_USER_INDEX_BUFFERS:
Christoph Bumillerf35e96d2013-03-29 13:02:49 +0100208 case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
Christoph Bumiller729abfd2013-04-12 13:42:01 +0200209 case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
Ilia Mirkin32b71242014-07-03 11:15:18 -0400210 case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT:
Dave Airlie2fcbec42013-09-21 18:45:43 +1000211 case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
212 case PIPE_CAP_TEXTURE_GATHER_SM5:
Ilia Mirkind95df4f2014-04-26 23:44:57 -0400213 case PIPE_CAP_FAKE_SW_MSAA:
Dave Airliebe5276a2014-02-11 13:26:08 +1000214 case PIPE_CAP_TEXTURE_QUERY_LOD:
Ilia Mirkind95df4f2014-04-26 23:44:57 -0400215 case PIPE_CAP_SAMPLE_SHADING:
216 case PIPE_CAP_TEXTURE_GATHER_OFFSETS:
Christoph Bumiller4b586a22014-05-17 01:20:19 +0200217 case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION:
Christoph Bumillerbc198f82013-04-05 14:29:36 +0200218 case PIPE_CAP_DRAW_INDIRECT:
Ilia Mirkin8ee74ce2014-08-14 00:04:41 -0400219 case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE:
Rob Clark6173cc12012-10-27 11:07:34 -0500220 return 0;
221
222 /* Stream output. */
223 case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
224 case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
225 case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
226 case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
227 return 0;
228
Grigori Goronzyd34d5fd2014-02-09 22:56:20 +0100229 /* Geometry shader output, unsupported. */
230 case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
231 case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
Ilia Mirkin746e5262014-06-26 20:01:50 -0400232 case PIPE_CAP_MAX_VERTEX_STREAMS:
Grigori Goronzyd34d5fd2014-02-09 22:56:20 +0100233 return 0;
234
Rob Clark6173cc12012-10-27 11:07:34 -0500235 /* Texturing. */
236 case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
237 case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
238 case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
Rob Clarkcb9e07a2013-08-31 09:14:27 -0400239 return MAX_MIP_LEVELS;
Rob Clark6173cc12012-10-27 11:07:34 -0500240 case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
Rob Clark57e68a92014-05-20 10:52:56 -0400241 return 0; /* TODO: a3xx+ should support (required in gles3) */
Rob Clark6173cc12012-10-27 11:07:34 -0500242
243 /* Render targets. */
244 case PIPE_CAP_MAX_RENDER_TARGETS:
245 return 1;
246
Rob Clarkf999c132014-05-11 14:15:32 -0400247 /* Queries. */
Rob Clark6173cc12012-10-27 11:07:34 -0500248 case PIPE_CAP_QUERY_TIME_ELAPSED:
Rob Clark6173cc12012-10-27 11:07:34 -0500249 case PIPE_CAP_QUERY_TIMESTAMP:
250 return 0;
Rob Clarkf999c132014-05-11 14:15:32 -0400251 case PIPE_CAP_OCCLUSION_QUERY:
Rob Clarke1896942014-05-14 11:06:21 -0400252 return (screen->gpu_id >= 300) ? 1 : 0;
Rob Clark6173cc12012-10-27 11:07:34 -0500253
Ilia Mirkinc2f9ad52014-04-09 14:58:53 -0400254 case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
Rob Clark6173cc12012-10-27 11:07:34 -0500255 case PIPE_CAP_MIN_TEXEL_OFFSET:
256 return -8;
257
Ilia Mirkinc2f9ad52014-04-09 14:58:53 -0400258 case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
Rob Clark6173cc12012-10-27 11:07:34 -0500259 case PIPE_CAP_MAX_TEXEL_OFFSET:
260 return 7;
261
Tom Stellard4e90bc92013-07-09 21:21:39 -0700262 case PIPE_CAP_ENDIANNESS:
263 return PIPE_ENDIAN_LITTLE;
264
Rob Clarkf999c132014-05-11 14:15:32 -0400265 case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
Ian Romanick25c14f42014-01-22 14:02:42 -0800266 return 64;
267
Emil Velikove9c43b12014-08-14 19:42:39 +0100268 case PIPE_CAP_VENDOR_ID:
269 return 0x5143;
270 case PIPE_CAP_DEVICE_ID:
271 return 0xFFFFFFFF;
272 case PIPE_CAP_ACCELERATED:
273 return 1;
274 case PIPE_CAP_VIDEO_MEMORY:
275 DBG("FINISHME: The value returned is incorrect\n");
276 return 10;
277 case PIPE_CAP_UMA:
278 return 1;
279
Rob Clark6173cc12012-10-27 11:07:34 -0500280 default:
281 DBG("unknown param %d", param);
282 return 0;
283 }
284}
285
286static float
287fd_screen_get_paramf(struct pipe_screen *pscreen, enum pipe_capf param)
288{
289 switch (param) {
290 case PIPE_CAPF_MAX_LINE_WIDTH:
291 case PIPE_CAPF_MAX_LINE_WIDTH_AA:
292 case PIPE_CAPF_MAX_POINT_WIDTH:
293 case PIPE_CAPF_MAX_POINT_WIDTH_AA:
294 return 8192.0f;
295 case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
296 return 16.0f;
297 case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
298 return 16.0f;
299 case PIPE_CAPF_GUARD_BAND_LEFT:
300 case PIPE_CAPF_GUARD_BAND_TOP:
301 case PIPE_CAPF_GUARD_BAND_RIGHT:
302 case PIPE_CAPF_GUARD_BAND_BOTTOM:
303 return 0.0f;
304 default:
305 DBG("unknown paramf %d", param);
306 return 0;
307 }
308}
309
310static int
311fd_screen_get_shader_param(struct pipe_screen *pscreen, unsigned shader,
312 enum pipe_shader_cap param)
313{
Rob Clark4317c4e2013-10-24 17:45:27 -0400314 struct fd_screen *screen = fd_screen(pscreen);
315
Rob Clark6173cc12012-10-27 11:07:34 -0500316 switch(shader)
317 {
318 case PIPE_SHADER_FRAGMENT:
319 case PIPE_SHADER_VERTEX:
320 break;
321 case PIPE_SHADER_COMPUTE:
322 case PIPE_SHADER_GEOMETRY:
323 /* maye we could emulate.. */
324 return 0;
325 default:
326 DBG("unknown shader type %d", shader);
327 return 0;
328 }
329
330 /* this is probably not totally correct.. but it's a start: */
331 switch (param) {
332 case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
333 case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
334 case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
335 case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
336 return 16384;
337 case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
338 return 8; /* XXX */
339 case PIPE_SHADER_CAP_MAX_INPUTS:
Rob Clark5dcf59e2014-05-14 11:15:26 -0400340 return 16;
Rob Clark6173cc12012-10-27 11:07:34 -0500341 case PIPE_SHADER_CAP_MAX_TEMPS:
Rob Clark4317c4e2013-10-24 17:45:27 -0400342 return 64; /* Max native temporaries. */
Marek Olšák04f2c882014-07-24 20:32:08 +0200343 case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
344 return ((screen->gpu_id >= 300) ? 1024 : 64) * sizeof(float[4]);
Rob Clark6173cc12012-10-27 11:07:34 -0500345 case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
Rob Clark4317c4e2013-10-24 17:45:27 -0400346 return 1;
Rob Clark6173cc12012-10-27 11:07:34 -0500347 case PIPE_SHADER_CAP_MAX_PREDS:
348 return 0; /* nothing uses this */
349 case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
350 return 1;
351 case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
352 case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
353 case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
354 case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
355 return 1;
356 case PIPE_SHADER_CAP_SUBROUTINES:
357 return 0;
358 case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
Rob Clark4ddd4e82013-10-25 11:48:24 -0400359 return 1;
Rob Clark6173cc12012-10-27 11:07:34 -0500360 case PIPE_SHADER_CAP_INTEGERS:
Rob Clark4ddd4e82013-10-25 11:48:24 -0400361 /* we should be able to support this on a3xx, but not
362 * implemented yet:
363 */
Rob Clarke1896942014-05-14 11:06:21 -0400364 return ((screen->gpu_id >= 300) && glsl130) ? 1 : 0;
Rob Clark6173cc12012-10-27 11:07:34 -0500365 case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
Roland Scheidegger2983c032013-11-26 02:30:41 +0100366 case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
Rob Clark6173cc12012-10-27 11:07:34 -0500367 return 16;
368 case PIPE_SHADER_CAP_PREFERRED_IR:
369 return PIPE_SHADER_IR_TGSI;
370 default:
371 DBG("unknown shader param %d", param);
372 return 0;
373 }
374 return 0;
375}
376
Rob Clark6173cc12012-10-27 11:07:34 -0500377boolean
378fd_screen_bo_get_handle(struct pipe_screen *pscreen,
379 struct fd_bo *bo,
380 unsigned stride,
381 struct winsys_handle *whandle)
382{
383 whandle->stride = stride;
384
385 if (whandle->type == DRM_API_HANDLE_TYPE_SHARED) {
386 return fd_bo_get_name(bo, &whandle->handle) == 0;
387 } else if (whandle->type == DRM_API_HANDLE_TYPE_KMS) {
388 whandle->handle = fd_bo_handle(bo);
389 return TRUE;
390 } else {
391 return FALSE;
392 }
393}
394
395struct fd_bo *
396fd_screen_bo_from_handle(struct pipe_screen *pscreen,
397 struct winsys_handle *whandle,
398 unsigned *out_stride)
399{
400 struct fd_screen *screen = fd_screen(pscreen);
401 struct fd_bo *bo;
402
Christopher James Halse Rogersd5a3a2d2013-11-21 15:11:39 +1100403 if (whandle->type != DRM_API_HANDLE_TYPE_SHARED) {
404 DBG("Attempt to import unsupported handle type %d", whandle->type);
405 return NULL;
406 }
407
Rob Clark6173cc12012-10-27 11:07:34 -0500408 bo = fd_bo_from_name(screen->dev, whandle->handle);
409 if (!bo) {
410 DBG("ref name 0x%08x failed", whandle->handle);
411 return NULL;
412 }
413
414 *out_stride = whandle->stride;
415
416 return bo;
417}
418
419struct pipe_screen *
420fd_screen_create(struct fd_device *dev)
421{
422 struct fd_screen *screen = CALLOC_STRUCT(fd_screen);
423 struct pipe_screen *pscreen;
424 uint64_t val;
425
Rob Clark634fb832013-03-25 14:57:24 -0400426 fd_mesa_debug = debug_get_option_fd_mesa_debug();
Rob Clark6173cc12012-10-27 11:07:34 -0500427
Rob Clark1b886072014-02-03 11:28:30 -0500428 if (fd_mesa_debug & FD_DBG_NOBIN)
Rob Clarkc0766522014-01-07 10:55:07 -0500429 fd_binning_enabled = false;
430
Rob Clarke1896942014-05-14 11:06:21 -0400431 glsl130 = !!(fd_mesa_debug & FD_DBG_GLSL130);
432
Rob Clark6173cc12012-10-27 11:07:34 -0500433 if (!screen)
434 return NULL;
435
Rob Clark38d8b022013-04-22 13:42:55 -0400436 pscreen = &screen->base;
Rob Clark6173cc12012-10-27 11:07:34 -0500437
438 screen->dev = dev;
439
440 // maybe this should be in context?
441 screen->pipe = fd_pipe_new(screen->dev, FD_PIPE_3D);
Rob Clark38d8b022013-04-22 13:42:55 -0400442 if (!screen->pipe) {
443 DBG("could not create 3d pipe");
444 goto fail;
445 }
Rob Clark6173cc12012-10-27 11:07:34 -0500446
Rob Clark38d8b022013-04-22 13:42:55 -0400447 if (fd_pipe_get_param(screen->pipe, FD_GMEM_SIZE, &val)) {
448 DBG("could not get GMEM size");
449 goto fail;
450 }
Rob Clark6173cc12012-10-27 11:07:34 -0500451 screen->gmemsize_bytes = val;
452
Rob Clark38d8b022013-04-22 13:42:55 -0400453 if (fd_pipe_get_param(screen->pipe, FD_DEVICE_ID, &val)) {
454 DBG("could not get device-id");
455 goto fail;
456 }
Rob Clark6173cc12012-10-27 11:07:34 -0500457 screen->device_id = val;
458
Rob Clark18c317b2013-05-26 17:13:27 -0400459 if (fd_pipe_get_param(screen->pipe, FD_GPU_ID, &val)) {
460 DBG("could not get gpu-id");
461 goto fail;
462 }
463 screen->gpu_id = val;
464
Rob Clarkd48faad2014-06-18 10:24:04 -0400465 if (fd_pipe_get_param(screen->pipe, FD_CHIP_ID, &val)) {
466 DBG("could not get chip-id");
467 /* older kernels may not have this property: */
468 unsigned core = screen->gpu_id / 100;
469 unsigned major = (screen->gpu_id % 100) / 10;
470 unsigned minor = screen->gpu_id % 10;
471 unsigned patch = 0; /* assume the worst */
472 val = (patch & 0xff) | ((minor & 0xff) << 8) |
473 ((major & 0xff) << 16) | ((core & 0xff) << 24);
474 }
475 screen->chip_id = val;
476
477 DBG("Pipe Info:");
478 DBG(" GPU-id: %d", screen->gpu_id);
479 DBG(" Chip-id: 0x%08x", screen->chip_id);
480 DBG(" GMEM size: 0x%08x", screen->gmemsize_bytes);
481
Rob Clark18c317b2013-05-26 17:13:27 -0400482 /* explicitly checking for GPU revisions that are known to work. This
483 * may be overly conservative for a3xx, where spoofing the gpu_id with
484 * the blob driver seems to generate identical cmdstream dumps. But
485 * on a2xx, there seem to be small differences between the GPU revs
486 * so it is probably better to actually test first on real hardware
487 * before enabling:
488 *
489 * If you have a different adreno version, feel free to add it to one
490 * of the two cases below and see what happens. And if it works, please
491 * send a patch ;-)
492 */
493 switch (screen->gpu_id) {
494 case 220:
495 fd2_screen_init(pscreen);
496 break;
Rob Clark2855f3f2013-05-26 17:13:44 -0400497 case 320:
Rob Clarka1d80862013-12-07 08:47:10 -0500498 case 330:
Rob Clark2855f3f2013-05-26 17:13:44 -0400499 fd3_screen_init(pscreen);
500 break;
Rob Clark18c317b2013-05-26 17:13:27 -0400501 default:
502 debug_printf("unsupported GPU: a%03d\n", screen->gpu_id);
503 goto fail;
504 }
Rob Clark6173cc12012-10-27 11:07:34 -0500505
506 pscreen->destroy = fd_screen_destroy;
507 pscreen->get_param = fd_screen_get_param;
508 pscreen->get_paramf = fd_screen_get_paramf;
509 pscreen->get_shader_param = fd_screen_get_shader_param;
Rob Clark6173cc12012-10-27 11:07:34 -0500510
511 fd_resource_screen_init(pscreen);
Rob Clark646c16a2014-01-07 21:39:13 -0500512 fd_query_screen_init(pscreen);
Rob Clark6173cc12012-10-27 11:07:34 -0500513
514 pscreen->get_name = fd_screen_get_name;
515 pscreen->get_vendor = fd_screen_get_vendor;
516
517 pscreen->get_timestamp = fd_screen_get_timestamp;
518
519 pscreen->fence_reference = fd_screen_fence_ref;
520 pscreen->fence_signalled = fd_screen_fence_signalled;
521 pscreen->fence_finish = fd_screen_fence_finish;
522
523 util_format_s3tc_init();
524
525 return pscreen;
Rob Clark38d8b022013-04-22 13:42:55 -0400526
527fail:
528 fd_screen_destroy(pscreen);
529 return NULL;
Rob Clark6173cc12012-10-27 11:07:34 -0500530}