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Zach Reizner85c4c5f2017-10-04 13:15:57 -07001/*
2 * Copyright 2017 The Chromium OS Authors. All rights reserved.
3 * Use of this source code is governed by a BSD-style license that can be
4 * found in the LICENSE file.
5 */
6
Zach Reizner85c4c5f2017-10-04 13:15:57 -07007#include <errno.h>
8#include <stdint.h>
9#include <stdio.h>
10#include <string.h>
11#include <sys/mman.h>
12#include <virtgpu_drm.h>
13#include <xf86drm.h>
14
15#include "drv_priv.h"
16#include "helpers.h"
17#include "util.h"
18#include "virgl_hw.h"
19
Tao Wu33815882018-03-12 18:07:43 -070020#ifndef PAGE_SIZE
Zach Reizner85c4c5f2017-10-04 13:15:57 -070021#define PAGE_SIZE 0x1000
Tao Wu33815882018-03-12 18:07:43 -070022#endif
Zach Reizner85c4c5f2017-10-04 13:15:57 -070023#define PIPE_TEXTURE_2D 2
24
Lepton Wu249e8632018-04-05 12:50:03 -070025#define MESA_LLVMPIPE_TILE_ORDER 6
26#define MESA_LLVMPIPE_TILE_SIZE (1 << MESA_LLVMPIPE_TILE_ORDER)
27
Zach Reizner85c4c5f2017-10-04 13:15:57 -070028static const uint32_t render_target_formats[] = { DRM_FORMAT_ABGR8888, DRM_FORMAT_ARGB8888,
Gurchetan Singh71bc6652018-09-17 17:42:05 -070029 DRM_FORMAT_RGB565, DRM_FORMAT_XBGR8888,
30 DRM_FORMAT_XRGB8888 };
Zach Reizner85c4c5f2017-10-04 13:15:57 -070031
Lepton Wu249e8632018-04-05 12:50:03 -070032static const uint32_t dumb_texture_source_formats[] = { DRM_FORMAT_R8, DRM_FORMAT_YVU420,
Gurchetan Singh3f3e5f92019-07-08 09:50:01 -070033 DRM_FORMAT_YVU420_ANDROID };
Lepton Wu249e8632018-04-05 12:50:03 -070034
Gurchetan Singhf5d280d2019-06-04 19:43:41 -070035static const uint32_t texture_source_formats[] = { DRM_FORMAT_NV12, DRM_FORMAT_R8, DRM_FORMAT_RG88,
36 DRM_FORMAT_YVU420_ANDROID };
Zach Reizner85c4c5f2017-10-04 13:15:57 -070037
Lepton Wu249e8632018-04-05 12:50:03 -070038struct virtio_gpu_priv {
39 int has_3d;
40};
41
Kansho Nishidad97877b2019-06-14 18:28:18 +090042static uint32_t translate_format(uint32_t drm_fourcc)
Zach Reizner85c4c5f2017-10-04 13:15:57 -070043{
44 switch (drm_fourcc) {
45 case DRM_FORMAT_XRGB8888:
46 return VIRGL_FORMAT_B8G8R8X8_UNORM;
47 case DRM_FORMAT_ARGB8888:
48 return VIRGL_FORMAT_B8G8R8A8_UNORM;
49 case DRM_FORMAT_XBGR8888:
50 return VIRGL_FORMAT_R8G8B8X8_UNORM;
51 case DRM_FORMAT_ABGR8888:
52 return VIRGL_FORMAT_R8G8B8A8_UNORM;
53 case DRM_FORMAT_RGB565:
54 return VIRGL_FORMAT_B5G6R5_UNORM;
55 case DRM_FORMAT_R8:
56 return VIRGL_FORMAT_R8_UNORM;
57 case DRM_FORMAT_RG88:
58 return VIRGL_FORMAT_R8G8_UNORM;
Gurchetan Singhf5d280d2019-06-04 19:43:41 -070059 case DRM_FORMAT_NV12:
60 return VIRGL_FORMAT_NV12;
61 case DRM_FORMAT_YVU420:
62 case DRM_FORMAT_YVU420_ANDROID:
63 return VIRGL_FORMAT_YV12;
Zach Reizner85c4c5f2017-10-04 13:15:57 -070064 default:
65 return 0;
66 }
67}
68
Lepton Wu249e8632018-04-05 12:50:03 -070069static int virtio_dumb_bo_create(struct bo *bo, uint32_t width, uint32_t height, uint32_t format,
70 uint64_t use_flags)
Zach Reizner85c4c5f2017-10-04 13:15:57 -070071{
Keiichi Watanabea13dda72018-08-02 22:45:05 +090072 if (bo->format != DRM_FORMAT_R8) {
73 width = ALIGN(width, MESA_LLVMPIPE_TILE_SIZE);
74 height = ALIGN(height, MESA_LLVMPIPE_TILE_SIZE);
75 }
Zach Reizner85c4c5f2017-10-04 13:15:57 -070076
Lepton Wu249e8632018-04-05 12:50:03 -070077 return drv_dumb_bo_create(bo, width, height, format, use_flags);
Zach Reizner85c4c5f2017-10-04 13:15:57 -070078}
79
Lepton Wudbab0832019-04-19 12:26:39 -070080static inline void handle_flag(uint64_t *flag, uint64_t check_flag, uint32_t *bind,
81 uint32_t virgl_bind)
82{
83 if ((*flag) & check_flag) {
84 (*flag) &= ~check_flag;
85 (*bind) |= virgl_bind;
86 }
87}
88
89static uint32_t use_flags_to_bind(uint64_t use_flags)
90{
Kansho Nishidad97877b2019-06-14 18:28:18 +090091 /* In crosvm, VIRGL_BIND_SHARED means minigbm will allocate, not virglrenderer. */
92 uint32_t bind = VIRGL_BIND_SHARED;
Lepton Wudbab0832019-04-19 12:26:39 -070093
94 handle_flag(&use_flags, BO_USE_TEXTURE, &bind, VIRGL_BIND_SAMPLER_VIEW);
95 handle_flag(&use_flags, BO_USE_RENDERING, &bind, VIRGL_BIND_RENDER_TARGET);
96 handle_flag(&use_flags, BO_USE_SCANOUT, &bind, VIRGL_BIND_SCANOUT);
97 // TODO (b/12983436): handle other use flags.
98 if (use_flags) {
99 drv_log("Unhandled bo use flag: %llx\n", (unsigned long long)use_flags);
100 }
Kansho Nishidad97877b2019-06-14 18:28:18 +0900101
Lepton Wudbab0832019-04-19 12:26:39 -0700102 return bind;
103}
104
Lepton Wu249e8632018-04-05 12:50:03 -0700105static int virtio_virgl_bo_create(struct bo *bo, uint32_t width, uint32_t height, uint32_t format,
106 uint64_t use_flags)
Zach Reizner85c4c5f2017-10-04 13:15:57 -0700107{
108 int ret;
Kansho Nishidad97877b2019-06-14 18:28:18 +0900109 uint32_t stride;
110 struct drm_virtgpu_resource_create res_create;
Zach Reizner85c4c5f2017-10-04 13:15:57 -0700111
Kansho Nishidad97877b2019-06-14 18:28:18 +0900112 stride = drv_stride_from_format(format, width, 0);
113 drv_bo_from_format(bo, stride, height, format);
Zach Reizner85c4c5f2017-10-04 13:15:57 -0700114
Kansho Nishidad97877b2019-06-14 18:28:18 +0900115 /*
116 * Setting the target is intended to ensure this resource gets bound as a 2D
117 * texture in the host renderer's GL state. All of these resource properties are
118 * sent unchanged by the kernel to the host, which in turn sends them unchanged to
119 * virglrenderer. When virglrenderer makes a resource, it will convert the target
120 * enum to the equivalent one in GL and then bind the resource to that target.
121 */
122 memset(&res_create, 0, sizeof(res_create));
Zach Reizner85c4c5f2017-10-04 13:15:57 -0700123
Kansho Nishidad97877b2019-06-14 18:28:18 +0900124 res_create.target = PIPE_TEXTURE_2D;
125 res_create.format = translate_format(format);
126 res_create.bind = use_flags_to_bind(use_flags);
127 res_create.width = width;
128 res_create.height = height;
Zach Reizner85c4c5f2017-10-04 13:15:57 -0700129
Kansho Nishidad97877b2019-06-14 18:28:18 +0900130 /* For virgl 3D */
131 res_create.depth = 1;
132 res_create.array_size = 1;
133 res_create.last_level = 0;
134 res_create.nr_samples = 0;
135
136 res_create.size = ALIGN(bo->total_size, PAGE_SIZE); // PAGE_SIZE = 0x1000
137 ret = drmIoctl(bo->drv->fd, DRM_IOCTL_VIRTGPU_RESOURCE_CREATE, &res_create);
138 if (ret) {
139 drv_log("DRM_IOCTL_VIRTGPU_RESOURCE_CREATE failed with %s\n", strerror(errno));
140 return ret;
Zach Reizner85c4c5f2017-10-04 13:15:57 -0700141 }
142
Kansho Nishidad97877b2019-06-14 18:28:18 +0900143 for (uint32_t plane = 0; plane < bo->num_planes; plane++)
144 bo->handles[plane].u32 = res_create.bo_handle;
Zach Reizner85c4c5f2017-10-04 13:15:57 -0700145
146 return 0;
Zach Reizner85c4c5f2017-10-04 13:15:57 -0700147}
148
Lepton Wu249e8632018-04-05 12:50:03 -0700149static void *virtio_virgl_bo_map(struct bo *bo, struct vma *vma, size_t plane, uint32_t map_flags)
Zach Reizner85c4c5f2017-10-04 13:15:57 -0700150{
151 int ret;
152 struct drm_virtgpu_map gem_map;
153
154 memset(&gem_map, 0, sizeof(gem_map));
155 gem_map.handle = bo->handles[0].u32;
156
157 ret = drmIoctl(bo->drv->fd, DRM_IOCTL_VIRTGPU_MAP, &gem_map);
158 if (ret) {
Alistair Strachan0cfaaa52018-03-19 14:03:23 -0700159 drv_log("DRM_IOCTL_VIRTGPU_MAP failed with %s\n", strerror(errno));
Zach Reizner85c4c5f2017-10-04 13:15:57 -0700160 return MAP_FAILED;
161 }
162
Tao Wu33815882018-03-12 18:07:43 -0700163 vma->length = bo->total_size;
Zach Reizner85c4c5f2017-10-04 13:15:57 -0700164 return mmap(0, bo->total_size, drv_get_prot(map_flags), MAP_SHARED, bo->drv->fd,
165 gem_map.offset);
166}
167
Lepton Wu249e8632018-04-05 12:50:03 -0700168static int virtio_gpu_init(struct driver *drv)
169{
170 int ret;
171 struct virtio_gpu_priv *priv;
172 struct drm_virtgpu_getparam args;
173
174 priv = calloc(1, sizeof(*priv));
175 drv->priv = priv;
176
177 memset(&args, 0, sizeof(args));
178 args.param = VIRTGPU_PARAM_3D_FEATURES;
179 args.value = (uint64_t)(uintptr_t)&priv->has_3d;
180 ret = drmIoctl(drv->fd, DRM_IOCTL_VIRTGPU_GETPARAM, &args);
181 if (ret) {
182 drv_log("virtio 3D acceleration is not available\n");
183 /* Be paranoid */
184 priv->has_3d = 0;
185 }
186
Lepton Wudbab0832019-04-19 12:26:39 -0700187 /* This doesn't mean host can scanout everything, it just means host
188 * hypervisor can show it. */
Lepton Wu249e8632018-04-05 12:50:03 -0700189 drv_add_combinations(drv, render_target_formats, ARRAY_SIZE(render_target_formats),
Lepton Wudbab0832019-04-19 12:26:39 -0700190 &LINEAR_METADATA, BO_USE_RENDER_MASK | BO_USE_SCANOUT);
Lepton Wu249e8632018-04-05 12:50:03 -0700191
Gurchetan Singh3f3e5f92019-07-08 09:50:01 -0700192 if (priv->has_3d) {
Lepton Wu249e8632018-04-05 12:50:03 -0700193 drv_add_combinations(drv, texture_source_formats,
194 ARRAY_SIZE(texture_source_formats), &LINEAR_METADATA,
195 BO_USE_TEXTURE_MASK);
Gurchetan Singh3f3e5f92019-07-08 09:50:01 -0700196 } else {
Lepton Wu249e8632018-04-05 12:50:03 -0700197 drv_add_combinations(drv, dumb_texture_source_formats,
198 ARRAY_SIZE(dumb_texture_source_formats), &LINEAR_METADATA,
199 BO_USE_TEXTURE_MASK);
Gurchetan Singh3f3e5f92019-07-08 09:50:01 -0700200 drv_add_combination(drv, DRM_FORMAT_NV12, &LINEAR_METADATA,
David Stevens9f7897f2019-08-09 20:20:23 +0900201 BO_USE_SW_MASK | BO_USE_LINEAR);
Gurchetan Singh3f3e5f92019-07-08 09:50:01 -0700202 }
Lepton Wu249e8632018-04-05 12:50:03 -0700203
Gurchetan Singh71bc6652018-09-17 17:42:05 -0700204 /* Android CTS tests require this. */
205 drv_add_combination(drv, DRM_FORMAT_BGR888, &LINEAR_METADATA, BO_USE_SW_MASK);
206
David Stevens9f7897f2019-08-09 20:20:23 +0900207 drv_modify_combination(drv, DRM_FORMAT_NV12, &LINEAR_METADATA,
David Stevens6116b312019-09-03 10:49:50 +0900208 BO_USE_CAMERA_READ | BO_USE_CAMERA_WRITE | BO_USE_HW_VIDEO_DECODER);
Keiichi Watanabea13dda72018-08-02 22:45:05 +0900209 drv_modify_combination(drv, DRM_FORMAT_R8, &LINEAR_METADATA,
210 BO_USE_CAMERA_READ | BO_USE_CAMERA_WRITE);
211
Lepton Wu249e8632018-04-05 12:50:03 -0700212 return drv_modify_linear_combinations(drv);
213}
214
215static void virtio_gpu_close(struct driver *drv)
216{
217 free(drv->priv);
218 drv->priv = NULL;
219}
220
221static int virtio_gpu_bo_create(struct bo *bo, uint32_t width, uint32_t height, uint32_t format,
222 uint64_t use_flags)
223{
224 struct virtio_gpu_priv *priv = (struct virtio_gpu_priv *)bo->drv->priv;
225 if (priv->has_3d)
226 return virtio_virgl_bo_create(bo, width, height, format, use_flags);
227 else
228 return virtio_dumb_bo_create(bo, width, height, format, use_flags);
229}
230
231static int virtio_gpu_bo_destroy(struct bo *bo)
232{
233 struct virtio_gpu_priv *priv = (struct virtio_gpu_priv *)bo->drv->priv;
234 if (priv->has_3d)
235 return drv_gem_bo_destroy(bo);
236 else
237 return drv_dumb_bo_destroy(bo);
238}
239
240static void *virtio_gpu_bo_map(struct bo *bo, struct vma *vma, size_t plane, uint32_t map_flags)
241{
242 struct virtio_gpu_priv *priv = (struct virtio_gpu_priv *)bo->drv->priv;
243 if (priv->has_3d)
244 return virtio_virgl_bo_map(bo, vma, plane, map_flags);
245 else
246 return drv_dumb_bo_map(bo, vma, plane, map_flags);
247}
248
Zach Reizner85c4c5f2017-10-04 13:15:57 -0700249static int virtio_gpu_bo_invalidate(struct bo *bo, struct mapping *mapping)
250{
251 int ret;
252 struct drm_virtgpu_3d_transfer_from_host xfer;
Lepton Wu249e8632018-04-05 12:50:03 -0700253 struct virtio_gpu_priv *priv = (struct virtio_gpu_priv *)bo->drv->priv;
254
255 if (!priv->has_3d)
256 return 0;
Zach Reizner85c4c5f2017-10-04 13:15:57 -0700257
258 memset(&xfer, 0, sizeof(xfer));
259 xfer.bo_handle = mapping->vma->handle;
260 xfer.box.x = mapping->rect.x;
261 xfer.box.y = mapping->rect.y;
262 xfer.box.w = mapping->rect.width;
263 xfer.box.h = mapping->rect.height;
264 xfer.box.d = 1;
265
Gurchetan Singh05e67cc2019-06-28 17:21:40 -0700266 // Unfortunately, the kernel doesn't actually pass the guest layer_stride and
267 // guest stride to the host (compare virtio_gpu.h and virtgpu_drm.h). We can use
268 // the level to work around this.
269 xfer.level = bo->strides[0];
270
Zach Reizner85c4c5f2017-10-04 13:15:57 -0700271 ret = drmIoctl(bo->drv->fd, DRM_IOCTL_VIRTGPU_TRANSFER_FROM_HOST, &xfer);
272 if (ret) {
Alistair Strachan0cfaaa52018-03-19 14:03:23 -0700273 drv_log("DRM_IOCTL_VIRTGPU_TRANSFER_FROM_HOST failed with %s\n", strerror(errno));
Stéphane Marchesin6ac299f2019-03-21 12:23:29 -0700274 return -errno;
Zach Reizner85c4c5f2017-10-04 13:15:57 -0700275 }
276
277 return 0;
278}
279
280static int virtio_gpu_bo_flush(struct bo *bo, struct mapping *mapping)
281{
282 int ret;
283 struct drm_virtgpu_3d_transfer_to_host xfer;
Lepton Wu249e8632018-04-05 12:50:03 -0700284 struct virtio_gpu_priv *priv = (struct virtio_gpu_priv *)bo->drv->priv;
285
286 if (!priv->has_3d)
287 return 0;
Zach Reizner85c4c5f2017-10-04 13:15:57 -0700288
289 if (!(mapping->vma->map_flags & BO_MAP_WRITE))
290 return 0;
291
292 memset(&xfer, 0, sizeof(xfer));
293 xfer.bo_handle = mapping->vma->handle;
294 xfer.box.x = mapping->rect.x;
295 xfer.box.y = mapping->rect.y;
296 xfer.box.w = mapping->rect.width;
297 xfer.box.h = mapping->rect.height;
298 xfer.box.d = 1;
299
Gurchetan Singh05e67cc2019-06-28 17:21:40 -0700300 // Unfortunately, the kernel doesn't actually pass the guest layer_stride and
301 // guest stride to the host (compare virtio_gpu.h and virtgpu_drm.h). We can use
302 // the level to work around this.
303 xfer.level = bo->strides[0];
304
Zach Reizner85c4c5f2017-10-04 13:15:57 -0700305 ret = drmIoctl(bo->drv->fd, DRM_IOCTL_VIRTGPU_TRANSFER_TO_HOST, &xfer);
306 if (ret) {
Alistair Strachan0cfaaa52018-03-19 14:03:23 -0700307 drv_log("DRM_IOCTL_VIRTGPU_TRANSFER_TO_HOST failed with %s\n", strerror(errno));
Stéphane Marchesin6ac299f2019-03-21 12:23:29 -0700308 return -errno;
Zach Reizner85c4c5f2017-10-04 13:15:57 -0700309 }
310
311 return 0;
312}
313
Gurchetan Singh0d44d482019-06-04 19:39:51 -0700314static uint32_t virtio_gpu_resolve_format(struct driver *drv, uint32_t format, uint64_t use_flags)
Zach Reizner85c4c5f2017-10-04 13:15:57 -0700315{
Gurchetan Singhf5d280d2019-06-04 19:43:41 -0700316 struct virtio_gpu_priv *priv = (struct virtio_gpu_priv *)drv->priv;
317
Zach Reizner85c4c5f2017-10-04 13:15:57 -0700318 switch (format) {
319 case DRM_FORMAT_FLEX_IMPLEMENTATION_DEFINED:
Keiichi Watanabea13dda72018-08-02 22:45:05 +0900320 /* Camera subsystem requires NV12. */
321 if (use_flags & (BO_USE_CAMERA_READ | BO_USE_CAMERA_WRITE))
322 return DRM_FORMAT_NV12;
Zach Reizner85c4c5f2017-10-04 13:15:57 -0700323 /*HACK: See b/28671744 */
324 return DRM_FORMAT_XBGR8888;
Lepton Wu249e8632018-04-05 12:50:03 -0700325 case DRM_FORMAT_FLEX_YCbCr_420_888:
Gurchetan Singhf5d280d2019-06-04 19:43:41 -0700326 /*
327 * All of our host drivers prefer NV12 as their flexible media format.
328 * If that changes, this will need to be modified.
329 */
330 if (priv->has_3d)
331 return DRM_FORMAT_NV12;
332 else
333 return DRM_FORMAT_YVU420;
Zach Reizner85c4c5f2017-10-04 13:15:57 -0700334 default:
335 return format;
336 }
337}
338
Lepton Wu249e8632018-04-05 12:50:03 -0700339const struct backend backend_virtio_gpu = {
Zach Reizner85c4c5f2017-10-04 13:15:57 -0700340 .name = "virtio_gpu",
341 .init = virtio_gpu_init,
Lepton Wu249e8632018-04-05 12:50:03 -0700342 .close = virtio_gpu_close,
Zach Reizner85c4c5f2017-10-04 13:15:57 -0700343 .bo_create = virtio_gpu_bo_create,
Lepton Wu249e8632018-04-05 12:50:03 -0700344 .bo_destroy = virtio_gpu_bo_destroy,
Zach Reizner85c4c5f2017-10-04 13:15:57 -0700345 .bo_import = drv_prime_bo_import,
Lepton Wu249e8632018-04-05 12:50:03 -0700346 .bo_map = virtio_gpu_bo_map,
Zach Reizner85c4c5f2017-10-04 13:15:57 -0700347 .bo_unmap = drv_bo_munmap,
348 .bo_invalidate = virtio_gpu_bo_invalidate,
349 .bo_flush = virtio_gpu_bo_flush,
350 .resolve_format = virtio_gpu_resolve_format,
351};