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JB Tsai0c16a0f2015-03-19 14:30:31 +08001/*
2 * Copyright 2015 The Chromium OS Authors. All rights reserved.
3 * Use of this source code is governed by a BSD-style license that can be
4 * found in the LICENSE file.
5 */
6
Gurchetan Singh46faf6b2016-08-05 14:40:07 -07007#ifdef DRV_MEDIATEK
JB Tsai0c16a0f2015-03-19 14:30:31 +08008
Gurchetan Singh1b1d56a2017-03-10 16:25:23 -08009// clang-format off
Ilja H. Friedelf9d2ab72015-04-09 14:08:36 -070010#include <stdio.h>
JB Tsai0c16a0f2015-03-19 14:30:31 +080011#include <string.h>
Gurchetan Singhef920532016-08-12 16:38:25 -070012#include <sys/mman.h>
JB Tsai0c16a0f2015-03-19 14:30:31 +080013#include <xf86drm.h>
14#include <mediatek_drm.h>
Gurchetan Singh1b1d56a2017-03-10 16:25:23 -080015// clang-format on
Gurchetan Singhef920532016-08-12 16:38:25 -070016
Gurchetan Singh46faf6b2016-08-05 14:40:07 -070017#include "drv_priv.h"
JB Tsai0c16a0f2015-03-19 14:30:31 +080018#include "helpers.h"
Gurchetan Singh179687e2016-10-28 10:07:35 -070019#include "util.h"
20
Gurchetan Singh469a3aa2017-08-03 18:17:34 -070021struct mediatek_private_map_data {
22 void *cached_addr;
23 void *gem_addr;
24};
25
Gurchetan Singh8ac0c9a2017-05-15 09:34:22 -070026static const uint32_t render_target_formats[] = { DRM_FORMAT_ABGR8888, DRM_FORMAT_ARGB8888,
27 DRM_FORMAT_RGB565, DRM_FORMAT_XBGR8888,
28 DRM_FORMAT_XRGB8888 };
29
30static const uint32_t texture_source_formats[] = { DRM_FORMAT_R8, DRM_FORMAT_YVU420,
31 DRM_FORMAT_YVU420_ANDROID };
Gurchetan Singh179687e2016-10-28 10:07:35 -070032
33static int mediatek_init(struct driver *drv)
34{
Gurchetan Singh8ac0c9a2017-05-15 09:34:22 -070035 int ret;
36 ret = drv_add_combinations(drv, render_target_formats, ARRAY_SIZE(render_target_formats),
37 &LINEAR_METADATA, BO_USE_RENDER_MASK);
38 if (ret)
39 return ret;
40
41 ret = drv_add_combinations(drv, texture_source_formats, ARRAY_SIZE(texture_source_formats),
42 &LINEAR_METADATA, BO_USE_TEXTURE_MASK);
43 if (ret)
44 return ret;
45
46 return drv_modify_linear_combinations(drv);
Gurchetan Singh179687e2016-10-28 10:07:35 -070047}
JB Tsai0c16a0f2015-03-19 14:30:31 +080048
Gurchetan Singh1b1d56a2017-03-10 16:25:23 -080049static int mediatek_bo_create(struct bo *bo, uint32_t width, uint32_t height, uint32_t format,
Gurchetan Singha1892b22017-09-28 16:40:52 -070050 uint64_t use_flags)
JB Tsai0c16a0f2015-03-19 14:30:31 +080051{
JB Tsai0c16a0f2015-03-19 14:30:31 +080052 int ret;
Gurchetan Singh42cc6d62016-08-29 18:19:19 -070053 size_t plane;
Gurchetan Singh6423ecb2017-03-29 08:23:40 -070054 uint32_t stride;
Gurchetan Singh42cc6d62016-08-29 18:19:19 -070055 struct drm_mtk_gem_create gem_create;
JB Tsai0c16a0f2015-03-19 14:30:31 +080056
Gurchetan Singh6ea14ba2017-02-08 15:09:13 -080057 /*
58 * Since the ARM L1 cache line size is 64 bytes, align to that as a
59 * performance optimization.
60 */
Gurchetan Singh6423ecb2017-03-29 08:23:40 -070061 stride = drv_stride_from_format(format, width, 0);
62 stride = ALIGN(stride, 64);
63 drv_bo_from_format(bo, stride, height, format);
Yuly Novikov96c7a3b2015-12-08 22:48:29 -050064
JB Tsai0c16a0f2015-03-19 14:30:31 +080065 memset(&gem_create, 0, sizeof(gem_create));
Gurchetan Singha40ca9e2016-08-29 19:51:45 -070066 gem_create.size = bo->total_size;
JB Tsai0c16a0f2015-03-19 14:30:31 +080067
Gurchetan Singh46faf6b2016-08-05 14:40:07 -070068 ret = drmIoctl(bo->drv->fd, DRM_IOCTL_MTK_GEM_CREATE, &gem_create);
Ilja H. Friedelf9d2ab72015-04-09 14:08:36 -070069 if (ret) {
Gurchetan Singh085bff12017-03-20 13:05:49 -070070 fprintf(stderr, "drv: DRM_IOCTL_MTK_GEM_CREATE failed (size=%llu)\n",
Gurchetan Singh1b1d56a2017-03-10 16:25:23 -080071 gem_create.size);
JB Tsai0c16a0f2015-03-19 14:30:31 +080072 return ret;
Ilja H. Friedelf9d2ab72015-04-09 14:08:36 -070073 }
JB Tsai0c16a0f2015-03-19 14:30:31 +080074
Gurchetan Singh42cc6d62016-08-29 18:19:19 -070075 for (plane = 0; plane < bo->num_planes; plane++)
76 bo->handles[plane].u32 = gem_create.handle;
JB Tsai0c16a0f2015-03-19 14:30:31 +080077
78 return 0;
79}
80
Gurchetan Singhcfb88762017-09-28 17:14:50 -070081static void *mediatek_bo_map(struct bo *bo, struct map_info *data, size_t plane, uint32_t map_flags)
Gurchetan Singhef920532016-08-12 16:38:25 -070082{
83 int ret;
84 struct drm_mtk_gem_map_off gem_map;
Gurchetan Singh469a3aa2017-08-03 18:17:34 -070085 struct mediatek_private_map_data *priv;
Gurchetan Singhef920532016-08-12 16:38:25 -070086
87 memset(&gem_map, 0, sizeof(gem_map));
88 gem_map.handle = bo->handles[0].u32;
89
90 ret = drmIoctl(bo->drv->fd, DRM_IOCTL_MTK_GEM_MAP_OFFSET, &gem_map);
91 if (ret) {
Gurchetan Singh1b1d56a2017-03-10 16:25:23 -080092 fprintf(stderr, "drv: DRM_IOCTL_MTK_GEM_MAP_OFFSET failed\n");
Gurchetan Singhef920532016-08-12 16:38:25 -070093 return MAP_FAILED;
94 }
95
Gurchetan Singhcfb88762017-09-28 17:14:50 -070096 void *addr = mmap(0, bo->total_size, drv_get_prot(map_flags), MAP_SHARED, bo->drv->fd,
97 gem_map.offset);
Gurchetan Singh469a3aa2017-08-03 18:17:34 -070098
Gurchetan Singh1a31e602016-10-06 10:58:00 -070099 data->length = bo->total_size;
100
Gurchetan Singha1892b22017-09-28 16:40:52 -0700101 if (bo->use_flags & BO_USE_RENDERSCRIPT) {
Gurchetan Singh469a3aa2017-08-03 18:17:34 -0700102 priv = calloc(1, sizeof(*priv));
103 priv->cached_addr = calloc(1, bo->total_size);
104 priv->gem_addr = addr;
105 memcpy(priv->cached_addr, priv->gem_addr, bo->total_size);
106 data->priv = priv;
107 addr = priv->cached_addr;
108 }
109
110 return addr;
111}
112
113static int mediatek_bo_unmap(struct bo *bo, struct map_info *data)
114{
115 if (data->priv) {
116 struct mediatek_private_map_data *priv = data->priv;
Gurchetan Singh469a3aa2017-08-03 18:17:34 -0700117 data->addr = priv->gem_addr;
118 free(priv->cached_addr);
119 free(priv);
120 data->priv = NULL;
121 }
122
123 return munmap(data->addr, data->length);
Gurchetan Singhef920532016-08-12 16:38:25 -0700124}
125
Gurchetan Singh8e02e052017-09-14 14:18:43 -0700126static int mediatek_bo_flush(struct bo *bo, struct map_info *data)
127{
128 struct mediatek_private_map_data *priv = data->priv;
Gurchetan Singh8e02e052017-09-14 14:18:43 -0700129 if (priv)
130 memcpy(priv->gem_addr, priv->cached_addr, bo->total_size);
131
132 return 0;
133}
134
Gurchetan Singha1892b22017-09-28 16:40:52 -0700135static uint32_t mediatek_resolve_format(uint32_t format, uint64_t use_flags)
Gurchetan Singh42cc6d62016-08-29 18:19:19 -0700136{
137 switch (format) {
Gurchetan Singhf3b22da2016-11-21 10:46:38 -0800138 case DRM_FORMAT_FLEX_IMPLEMENTATION_DEFINED:
Gurchetan Singh42cc6d62016-08-29 18:19:19 -0700139 /*HACK: See b/28671744 */
Gurchetan Singhf3b22da2016-11-21 10:46:38 -0800140 return DRM_FORMAT_XBGR8888;
141 case DRM_FORMAT_FLEX_YCbCr_420_888:
Owen Linbbb69fd2017-06-05 14:33:08 +0800142 return DRM_FORMAT_YVU420;
Gurchetan Singh42cc6d62016-08-29 18:19:19 -0700143 default:
144 return format;
145 }
146}
147
Gurchetan Singh1b1d56a2017-03-10 16:25:23 -0800148struct backend backend_mediatek = {
JB Tsai0c16a0f2015-03-19 14:30:31 +0800149 .name = "mediatek",
Gurchetan Singh179687e2016-10-28 10:07:35 -0700150 .init = mediatek_init,
Gurchetan Singhd7c84fd2016-08-16 18:18:24 -0700151 .bo_create = mediatek_bo_create,
Gurchetan Singh46faf6b2016-08-05 14:40:07 -0700152 .bo_destroy = drv_gem_bo_destroy,
Gurchetan Singh71611d62017-01-03 16:49:56 -0800153 .bo_import = drv_prime_bo_import,
Gurchetan Singhd7c84fd2016-08-16 18:18:24 -0700154 .bo_map = mediatek_bo_map,
Gurchetan Singh469a3aa2017-08-03 18:17:34 -0700155 .bo_unmap = mediatek_bo_unmap,
Gurchetan Singh8e02e052017-09-14 14:18:43 -0700156 .bo_flush = mediatek_bo_flush,
Gurchetan Singh42cc6d62016-08-29 18:19:19 -0700157 .resolve_format = mediatek_resolve_format,
JB Tsai0c16a0f2015-03-19 14:30:31 +0800158};
159
160#endif