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cliechti88641262002-07-29 02:09:04 +00001#pyparallel driver for win32
2#see __init__.py
3#
4#(C) 2002 Chris Liechti <cliechti@gmx.net>
5# this is distributed under a free software license, see license.txt
6#
7# thanks to Dincer Aydin dinceraydin@altavista.net for his work on the
8# winioport module: www.geocities.com/dinceraydin/ the graphic below is
9# borrowed form him ;-)
10
11
12# LPT1 = 0x0378 or 0x03BC
13# LPT2 = 0x0278 or 0x0378
14# LPT3 = 0x0278
15#
16# Data Register (base + 0) ........ outputs
17#
18# 7 6 5 4 3 2 1 0
19# . . . . . . . * D0 ........... (pin 2), 1=High, 0=Low (true)
20# . . . . . . * . D1 ........... (pin 3), 1=High, 0=Low (true)
21# . . . . . * . . D2 ........... (pin 4), 1=High, 0=Low (true)
22# . . . . * . . . D3 ........... (pin 5), 1=High, 0=Low (true)
23# . . . * . . . . D4 ........... (pin 6), 1=High, 0=Low (true)
24# . . * . . . . . D5 ........... (pin 7), 1=High, 0=Low (true)
25# . * . . . . . . D6 ........... (pin 8), 1=High, 0=Low (true)
26# * . . . . . . . D7 ........... (pin 9), 1=High, 0=Low (true)
27#
28# Status Register (base + 1) ...... inputs
29#
30# 7 6 5 4 3 2 1 0
31# . . . . . * * * Undefined
32# . . . . * . . . Error ........ (pin 15), high=1, low=0 (true)
33# . . . * . . . . Selected ..... (pin 13), high=1, low=0 (true)
34# . . * . . . . . No paper ..... (pin 12), high=1, low=0 (true)
35# . * . . . . . . Ack .......... (pin 10), high=1, low=0 (true)
36# * . . . . . . . Busy ......... (pin 11), high=0, low=1 (inverted)
37#
38# ctrl Register (base + 2) ..... outputs
39#
40# 7 6 5 4 3 2 1 0
41# . . . . . . . * Strobe ....... (pin 1), 1=low, 0=high (inverted)
42# . . . . . . * . Auto Feed .... (pin 14), 1=low, 0=high (inverted)
cliechti619e4562002-07-31 00:53:06 +000043# . . . . . * . . Initialize ... (pin 16), 1=high,0=low (true)
cliechti88641262002-07-29 02:09:04 +000044# . . . . * . . . Select ....... (pin 17), 1=low, 0=high (inverted)
45# * * * * . . . . Unused
46
47LPT1 = 0
48LPT2 = 1
49
50LPT1_base = 0x0378
51LPT2_base = 0x0278
52
cliechtia7bafcb2005-01-27 00:47:15 +000053import ctypes
54import os
55#need to patch PATH so that the DLL can be found and loaded
56os.environ['PATH'] = os.environ['PATH'] + ';' + os.path.abspath(os.path.dirname(__file__))
57#fake module, names of the functions are the same as in the old _pyparallel
58#python extension in earlier versions of this modules
59_pyparallel = ctypes.windll.simpleio
60#need to initialize giveio on WinNT based systems
cliechti6c9db232005-03-26 00:06:18 +000061if _pyparallel.init():
62 raise IOError('Could not access the giveio driver which is required on NT based systems.')
cliechtia7bafcb2005-01-27 00:47:15 +000063
cliechti88641262002-07-29 02:09:04 +000064
65class Parallel:
66 def __init__(self, port = LPT1):
67 if port == LPT1:
68 self.dataRegAdr = LPT1_base
cliechti619e4562002-07-31 00:53:06 +000069 elif port == LPT2:
cliechti88641262002-07-29 02:09:04 +000070 self.dataRegAdr = LPT2_base
71 else:
72 raise ValueError("No such port available - expecting a number")
73 self.statusRegAdr = self.dataRegAdr + 1
74 self.ctrlRegAdr = self.dataRegAdr + 2
cliechtie7d23fe2003-05-26 19:42:23 +000075 self.ctrlReg = _pyparallel.inp(self.ctrlRegAdr)
cliechti88641262002-07-29 02:09:04 +000076
77 def setData(self, value):
78 _pyparallel.outp(self.dataRegAdr, value)
79
cliechtia641aec2009-07-22 00:24:41 +000080 def setDataDir( self, level):
81 """set for port as input, clear for output"""
82 if level:
83 self.ctrlReg |= 0x20
84 else:
85 self.ctrlReg &= ~0x20
86 _pyparallel.outp(self.ctrlRegAdr, self.ctrlReg)
87
cliechti88641262002-07-29 02:09:04 +000088 # control register output functions
cliechti619e4562002-07-31 00:53:06 +000089 def setDataStrobe(self, level):
cliechti88641262002-07-29 02:09:04 +000090 """data strobe bit"""
cliechti619e4562002-07-31 00:53:06 +000091 if level:
cliechti88641262002-07-29 02:09:04 +000092 self.ctrlReg = self.ctrlReg & ~0x01
cliechti619e4562002-07-31 00:53:06 +000093 else:
94 self.ctrlReg = self.ctrlReg | 0x01
cliechti88641262002-07-29 02:09:04 +000095 _pyparallel.outp(self.ctrlRegAdr, self.ctrlReg)
96
cliechti619e4562002-07-31 00:53:06 +000097 def setAutoFeed(self, level):
cliechti88641262002-07-29 02:09:04 +000098 """auto feed bit"""
cliechti619e4562002-07-31 00:53:06 +000099 if level:
cliechti88641262002-07-29 02:09:04 +0000100 self.ctrlReg = self.ctrlReg & ~0x02
cliechti619e4562002-07-31 00:53:06 +0000101 else:
102 self.ctrlReg = self.ctrlReg | 0x02
cliechti88641262002-07-29 02:09:04 +0000103 _pyparallel.outp(self.ctrlRegAdr, self.ctrlReg)
104
cliechti619e4562002-07-31 00:53:06 +0000105 def setInitOut(self, level):
cliechti88641262002-07-29 02:09:04 +0000106 """initialize bit"""
cliechti619e4562002-07-31 00:53:06 +0000107 if level:
cliechti88641262002-07-29 02:09:04 +0000108 self.ctrlReg = self.ctrlReg | 0x04
cliechti619e4562002-07-31 00:53:06 +0000109 else:
110 self.ctrlReg = self.ctrlReg & ~0x04
cliechti88641262002-07-29 02:09:04 +0000111 _pyparallel.outp(self.ctrlRegAdr, self.ctrlReg)
cliechtia641aec2009-07-22 00:24:41 +0000112
cliechti619e4562002-07-31 00:53:06 +0000113 def setSelect(self, level):
cliechti88641262002-07-29 02:09:04 +0000114 """select bit"""
cliechti619e4562002-07-31 00:53:06 +0000115 if level:
cliechti88641262002-07-29 02:09:04 +0000116 self.ctrlReg = self.ctrlReg & ~0x08
cliechti619e4562002-07-31 00:53:06 +0000117 else:
118 self.ctrlReg = self.ctrlReg | 0x08
cliechti88641262002-07-29 02:09:04 +0000119 _pyparallel.outp(self.ctrlRegAdr, self.ctrlReg)
120
121 def getInError(self):
122 """Error pin"""
123 return _pyparallel.inp(self.statusRegAdr) & 0x08 and 1
124
cliechtie7d23fe2003-05-26 19:42:23 +0000125 def getInSelected(self):
cliechti88641262002-07-29 02:09:04 +0000126 """select pin"""
127 return _pyparallel.inp(self.statusRegAdr) & 0x10 and 1
128
129 def getInPaperOut(self):
130 """paper out pin"""
131 return _pyparallel.inp(self.statusRegAdr) & 0x20 and 1
132
133 def getInAcknowledge(self):
134 """Acknowledge pin"""
135 return _pyparallel.inp(self.statusRegAdr) & 0x40 and 1
136
137 def getInBusy(self):
138 """input from busy pin"""
cliechti619e4562002-07-31 00:53:06 +0000139 return not (_pyparallel.inp(self.statusRegAdr) & 0x80)