cliechti | 8864126 | 2002-07-29 02:09:04 +0000 | [diff] [blame] | 1 | #pyparallel driver for win32 |
| 2 | #see __init__.py |
| 3 | # |
| 4 | #(C) 2002 Chris Liechti <cliechti@gmx.net> |
| 5 | # this is distributed under a free software license, see license.txt |
| 6 | # |
| 7 | # thanks to Dincer Aydin dinceraydin@altavista.net for his work on the |
| 8 | # winioport module: www.geocities.com/dinceraydin/ the graphic below is |
| 9 | # borrowed form him ;-) |
| 10 | |
| 11 | |
| 12 | # LPT1 = 0x0378 or 0x03BC |
| 13 | # LPT2 = 0x0278 or 0x0378 |
| 14 | # LPT3 = 0x0278 |
| 15 | # |
| 16 | # Data Register (base + 0) ........ outputs |
| 17 | # |
| 18 | # 7 6 5 4 3 2 1 0 |
| 19 | # . . . . . . . * D0 ........... (pin 2), 1=High, 0=Low (true) |
| 20 | # . . . . . . * . D1 ........... (pin 3), 1=High, 0=Low (true) |
| 21 | # . . . . . * . . D2 ........... (pin 4), 1=High, 0=Low (true) |
| 22 | # . . . . * . . . D3 ........... (pin 5), 1=High, 0=Low (true) |
| 23 | # . . . * . . . . D4 ........... (pin 6), 1=High, 0=Low (true) |
| 24 | # . . * . . . . . D5 ........... (pin 7), 1=High, 0=Low (true) |
| 25 | # . * . . . . . . D6 ........... (pin 8), 1=High, 0=Low (true) |
| 26 | # * . . . . . . . D7 ........... (pin 9), 1=High, 0=Low (true) |
| 27 | # |
| 28 | # Status Register (base + 1) ...... inputs |
| 29 | # |
| 30 | # 7 6 5 4 3 2 1 0 |
| 31 | # . . . . . * * * Undefined |
| 32 | # . . . . * . . . Error ........ (pin 15), high=1, low=0 (true) |
| 33 | # . . . * . . . . Selected ..... (pin 13), high=1, low=0 (true) |
| 34 | # . . * . . . . . No paper ..... (pin 12), high=1, low=0 (true) |
| 35 | # . * . . . . . . Ack .......... (pin 10), high=1, low=0 (true) |
| 36 | # * . . . . . . . Busy ......... (pin 11), high=0, low=1 (inverted) |
| 37 | # |
| 38 | # ctrl Register (base + 2) ..... outputs |
| 39 | # |
| 40 | # 7 6 5 4 3 2 1 0 |
| 41 | # . . . . . . . * Strobe ....... (pin 1), 1=low, 0=high (inverted) |
| 42 | # . . . . . . * . Auto Feed .... (pin 14), 1=low, 0=high (inverted) |
cliechti | 619e456 | 2002-07-31 00:53:06 +0000 | [diff] [blame] | 43 | # . . . . . * . . Initialize ... (pin 16), 1=high,0=low (true) |
cliechti | 8864126 | 2002-07-29 02:09:04 +0000 | [diff] [blame] | 44 | # . . . . * . . . Select ....... (pin 17), 1=low, 0=high (inverted) |
| 45 | # * * * * . . . . Unused |
| 46 | |
| 47 | LPT1 = 0 |
| 48 | LPT2 = 1 |
| 49 | |
| 50 | LPT1_base = 0x0378 |
| 51 | LPT2_base = 0x0278 |
| 52 | |
cliechti | a7bafcb | 2005-01-27 00:47:15 +0000 | [diff] [blame] | 53 | import ctypes |
| 54 | import os |
| 55 | #need to patch PATH so that the DLL can be found and loaded |
| 56 | os.environ['PATH'] = os.environ['PATH'] + ';' + os.path.abspath(os.path.dirname(__file__)) |
| 57 | #fake module, names of the functions are the same as in the old _pyparallel |
| 58 | #python extension in earlier versions of this modules |
| 59 | _pyparallel = ctypes.windll.simpleio |
| 60 | #need to initialize giveio on WinNT based systems |
cliechti | 6c9db23 | 2005-03-26 00:06:18 +0000 | [diff] [blame] | 61 | if _pyparallel.init(): |
| 62 | raise IOError('Could not access the giveio driver which is required on NT based systems.') |
cliechti | a7bafcb | 2005-01-27 00:47:15 +0000 | [diff] [blame] | 63 | |
cliechti | 8864126 | 2002-07-29 02:09:04 +0000 | [diff] [blame] | 64 | |
| 65 | class Parallel: |
| 66 | def __init__(self, port = LPT1): |
| 67 | if port == LPT1: |
| 68 | self.dataRegAdr = LPT1_base |
cliechti | 619e456 | 2002-07-31 00:53:06 +0000 | [diff] [blame] | 69 | elif port == LPT2: |
cliechti | 8864126 | 2002-07-29 02:09:04 +0000 | [diff] [blame] | 70 | self.dataRegAdr = LPT2_base |
| 71 | else: |
| 72 | raise ValueError("No such port available - expecting a number") |
| 73 | self.statusRegAdr = self.dataRegAdr + 1 |
| 74 | self.ctrlRegAdr = self.dataRegAdr + 2 |
cliechti | e7d23fe | 2003-05-26 19:42:23 +0000 | [diff] [blame] | 75 | self.ctrlReg = _pyparallel.inp(self.ctrlRegAdr) |
cliechti | 8864126 | 2002-07-29 02:09:04 +0000 | [diff] [blame] | 76 | |
| 77 | def setData(self, value): |
| 78 | _pyparallel.outp(self.dataRegAdr, value) |
| 79 | |
cliechti | a641aec | 2009-07-22 00:24:41 +0000 | [diff] [blame^] | 80 | def setDataDir( self, level): |
| 81 | """set for port as input, clear for output""" |
| 82 | if level: |
| 83 | self.ctrlReg |= 0x20 |
| 84 | else: |
| 85 | self.ctrlReg &= ~0x20 |
| 86 | _pyparallel.outp(self.ctrlRegAdr, self.ctrlReg) |
| 87 | |
cliechti | 8864126 | 2002-07-29 02:09:04 +0000 | [diff] [blame] | 88 | # control register output functions |
cliechti | 619e456 | 2002-07-31 00:53:06 +0000 | [diff] [blame] | 89 | def setDataStrobe(self, level): |
cliechti | 8864126 | 2002-07-29 02:09:04 +0000 | [diff] [blame] | 90 | """data strobe bit""" |
cliechti | 619e456 | 2002-07-31 00:53:06 +0000 | [diff] [blame] | 91 | if level: |
cliechti | 8864126 | 2002-07-29 02:09:04 +0000 | [diff] [blame] | 92 | self.ctrlReg = self.ctrlReg & ~0x01 |
cliechti | 619e456 | 2002-07-31 00:53:06 +0000 | [diff] [blame] | 93 | else: |
| 94 | self.ctrlReg = self.ctrlReg | 0x01 |
cliechti | 8864126 | 2002-07-29 02:09:04 +0000 | [diff] [blame] | 95 | _pyparallel.outp(self.ctrlRegAdr, self.ctrlReg) |
| 96 | |
cliechti | 619e456 | 2002-07-31 00:53:06 +0000 | [diff] [blame] | 97 | def setAutoFeed(self, level): |
cliechti | 8864126 | 2002-07-29 02:09:04 +0000 | [diff] [blame] | 98 | """auto feed bit""" |
cliechti | 619e456 | 2002-07-31 00:53:06 +0000 | [diff] [blame] | 99 | if level: |
cliechti | 8864126 | 2002-07-29 02:09:04 +0000 | [diff] [blame] | 100 | self.ctrlReg = self.ctrlReg & ~0x02 |
cliechti | 619e456 | 2002-07-31 00:53:06 +0000 | [diff] [blame] | 101 | else: |
| 102 | self.ctrlReg = self.ctrlReg | 0x02 |
cliechti | 8864126 | 2002-07-29 02:09:04 +0000 | [diff] [blame] | 103 | _pyparallel.outp(self.ctrlRegAdr, self.ctrlReg) |
| 104 | |
cliechti | 619e456 | 2002-07-31 00:53:06 +0000 | [diff] [blame] | 105 | def setInitOut(self, level): |
cliechti | 8864126 | 2002-07-29 02:09:04 +0000 | [diff] [blame] | 106 | """initialize bit""" |
cliechti | 619e456 | 2002-07-31 00:53:06 +0000 | [diff] [blame] | 107 | if level: |
cliechti | 8864126 | 2002-07-29 02:09:04 +0000 | [diff] [blame] | 108 | self.ctrlReg = self.ctrlReg | 0x04 |
cliechti | 619e456 | 2002-07-31 00:53:06 +0000 | [diff] [blame] | 109 | else: |
| 110 | self.ctrlReg = self.ctrlReg & ~0x04 |
cliechti | 8864126 | 2002-07-29 02:09:04 +0000 | [diff] [blame] | 111 | _pyparallel.outp(self.ctrlRegAdr, self.ctrlReg) |
cliechti | a641aec | 2009-07-22 00:24:41 +0000 | [diff] [blame^] | 112 | |
cliechti | 619e456 | 2002-07-31 00:53:06 +0000 | [diff] [blame] | 113 | def setSelect(self, level): |
cliechti | 8864126 | 2002-07-29 02:09:04 +0000 | [diff] [blame] | 114 | """select bit""" |
cliechti | 619e456 | 2002-07-31 00:53:06 +0000 | [diff] [blame] | 115 | if level: |
cliechti | 8864126 | 2002-07-29 02:09:04 +0000 | [diff] [blame] | 116 | self.ctrlReg = self.ctrlReg & ~0x08 |
cliechti | 619e456 | 2002-07-31 00:53:06 +0000 | [diff] [blame] | 117 | else: |
| 118 | self.ctrlReg = self.ctrlReg | 0x08 |
cliechti | 8864126 | 2002-07-29 02:09:04 +0000 | [diff] [blame] | 119 | _pyparallel.outp(self.ctrlRegAdr, self.ctrlReg) |
| 120 | |
| 121 | def getInError(self): |
| 122 | """Error pin""" |
| 123 | return _pyparallel.inp(self.statusRegAdr) & 0x08 and 1 |
| 124 | |
cliechti | e7d23fe | 2003-05-26 19:42:23 +0000 | [diff] [blame] | 125 | def getInSelected(self): |
cliechti | 8864126 | 2002-07-29 02:09:04 +0000 | [diff] [blame] | 126 | """select pin""" |
| 127 | return _pyparallel.inp(self.statusRegAdr) & 0x10 and 1 |
| 128 | |
| 129 | def getInPaperOut(self): |
| 130 | """paper out pin""" |
| 131 | return _pyparallel.inp(self.statusRegAdr) & 0x20 and 1 |
| 132 | |
| 133 | def getInAcknowledge(self): |
| 134 | """Acknowledge pin""" |
| 135 | return _pyparallel.inp(self.statusRegAdr) & 0x40 and 1 |
| 136 | |
| 137 | def getInBusy(self): |
| 138 | """input from busy pin""" |
cliechti | 619e456 | 2002-07-31 00:53:06 +0000 | [diff] [blame] | 139 | return not (_pyparallel.inp(self.statusRegAdr) & 0x80) |