Jan Voung | b36ad9b | 2015-04-21 17:01:49 -0700 | [diff] [blame] | 1 | //===- subzero/src/IceInstARM32.def - X-Macros for ARM32 insts --*- C++ -*-===// |
| 2 | // |
| 3 | // The Subzero Code Generator |
| 4 | // |
| 5 | // This file is distributed under the University of Illinois Open Source |
| 6 | // License. See LICENSE.TXT for details. |
| 7 | // |
| 8 | //===----------------------------------------------------------------------===// |
| 9 | // |
| 10 | // This file defines properties of ARM32 instructions in the form of x-macros. |
| 11 | // |
| 12 | //===----------------------------------------------------------------------===// |
| 13 | |
| 14 | #ifndef SUBZERO_SRC_ICEINSTARM32_DEF |
| 15 | #define SUBZERO_SRC_ICEINSTARM32_DEF |
| 16 | |
Jim Stichnoth | 5bff61c | 2015-10-28 09:26:00 -0700 | [diff] [blame] | 17 | #include "IceRegList.h" |
| 18 | |
Jan Voung | b36ad9b | 2015-04-21 17:01:49 -0700 | [diff] [blame] | 19 | // NOTE: PC and SP are not considered isInt, to avoid register allocating. |
Jan Voung | 0fa6c5a | 2015-06-01 11:04:04 -0700 | [diff] [blame] | 20 | // |
John Porto | ed2c06b | 2015-10-01 15:27:15 -0700 | [diff] [blame] | 21 | // For the NaCl sandbox we also need to r9 (and the r8-r9 pair) for TLS, so |
| 22 | // just reserve always. |
| 23 | // TODO(jpp): Allow r9 to be isInt when sandboxing is turned off (native mode). |
Jan Voung | 0fa6c5a | 2015-06-01 11:04:04 -0700 | [diff] [blame] | 24 | // |
Jan Voung | 28068ad | 2015-07-31 12:58:46 -0700 | [diff] [blame] | 25 | // IP is not considered isInt to reserve it as a scratch register. A scratch |
| 26 | // register is useful for expanding instructions post-register allocation. |
| 27 | // |
Andrew Scull | 57e1268 | 2015-09-16 11:30:19 -0700 | [diff] [blame] | 28 | // LR is not considered isInt to avoid being allocated as a register. It is |
| 29 | // technically preserved, but save/restore is handled separately, based on |
| 30 | // whether or not the function MaybeLeafFunc. |
John Porto | eb13acc | 2015-12-09 05:10:58 -0800 | [diff] [blame] | 31 | // |
| 32 | // The register tables can be generated using the gen_arm32_reg_tables.py |
| 33 | // script. |
John Porto | 5300bfe | 2015-09-08 09:03:22 -0700 | [diff] [blame] | 34 | |
John Porto | 2187c84 | 2015-12-16 07:48:25 -0800 | [diff] [blame^] | 35 | #include "IceRegistersARM32.def" |
| 36 | // The register tables defined in IceRegistersARM32 use the following x-macro: |
| 37 | //#define X(val, encode, name, cc_arg, scratch, preserved, stackptr, frameptr, |
John Porto | ed2c06b | 2015-10-01 15:27:15 -0700 | [diff] [blame] | 38 | // isInt, isI64Pair, isFP32, isFP64, isVec128, alias_init) |
Jan Voung | b36ad9b | 2015-04-21 17:01:49 -0700 | [diff] [blame] | 39 | |
Andrew Scull | 57e1268 | 2015-09-16 11:30:19 -0700 | [diff] [blame] | 40 | // We also provide a combined table, so that there is a namespace where all of |
| 41 | // the registers are considered and have distinct numberings. This is in |
| 42 | // contrast to the above, where the "encode" is based on how the register |
| 43 | // numbers will be encoded in binaries and values can overlap. |
Jan Voung | 86ebec1 | 2015-08-09 07:58:35 -0700 | [diff] [blame] | 44 | #define REGARM32_TABLE \ |
John Porto | 2187c84 | 2015-12-16 07:48:25 -0800 | [diff] [blame^] | 45 | /* val, encode, name, cc_arg, scratch, preserved, stackptr, frameptr, \ |
| 46 | isInt, isI64Pair, isFP32, isFP64, isVec128, alias_init */ \ |
Jan Voung | 86ebec1 | 2015-08-09 07:58:35 -0700 | [diff] [blame] | 47 | REGARM32_GPR_TABLE \ |
John Porto | ed2c06b | 2015-10-01 15:27:15 -0700 | [diff] [blame] | 48 | REGARM32_I64PAIR_TABLE \ |
Jan Voung | 86ebec1 | 2015-08-09 07:58:35 -0700 | [diff] [blame] | 49 | REGARM32_FP32_TABLE \ |
| 50 | REGARM32_FP64_TABLE \ |
| 51 | REGARM32_VEC128_TABLE |
John Porto | 2187c84 | 2015-12-16 07:48:25 -0800 | [diff] [blame^] | 52 | //#define X(val, encode, name, cc_arg, scratch, preserved, stackptr, frameptr, |
John Porto | 5300bfe | 2015-09-08 09:03:22 -0700 | [diff] [blame] | 53 | // isInt, isFP32, isFP64, isVec128, alias_init) |
Jan Voung | b36ad9b | 2015-04-21 17:01:49 -0700 | [diff] [blame] | 54 | |
Jan Voung | 86ebec1 | 2015-08-09 07:58:35 -0700 | [diff] [blame] | 55 | #define REGARM32_TABLE_BOUNDS \ |
| 56 | /* val, init */ \ |
| 57 | X(Reg_GPR_First, = Reg_r0) \ |
| 58 | X(Reg_GPR_Last, = Reg_pc) \ |
John Porto | ed2c06b | 2015-10-01 15:27:15 -0700 | [diff] [blame] | 59 | X(Reg_I64PAIR_First, = Reg_r0r1) \ |
| 60 | X(Reg_I64PAIR_Last, = Reg_r10fp) \ |
Jan Voung | 86ebec1 | 2015-08-09 07:58:35 -0700 | [diff] [blame] | 61 | X(Reg_SREG_First, = Reg_s0) \ |
| 62 | X(Reg_SREG_Last, = Reg_s31) \ |
| 63 | X(Reg_DREG_First, = Reg_d0) \ |
| 64 | X(Reg_DREG_Last, = Reg_d31) \ |
| 65 | X(Reg_QREG_First, = Reg_q0) \ |
| 66 | X(Reg_QREG_Last, = Reg_q15) |
| 67 | // define X(val, init) |
Jan Voung | b36ad9b | 2015-04-21 17:01:49 -0700 | [diff] [blame] | 68 | |
Jan Voung | 86ebec1 | 2015-08-09 07:58:35 -0700 | [diff] [blame] | 69 | // Load/Store instruction width suffixes and FP/Vector element size suffixes |
Andrew Scull | 57e1268 | 2015-09-16 11:30:19 -0700 | [diff] [blame] | 70 | // the # of offset bits allowed as part of an addressing mode (for sign or zero |
| 71 | // extending load/stores). |
Jan Voung | 86ebec1 | 2015-08-09 07:58:35 -0700 | [diff] [blame] | 72 | #define ICETYPEARM32_TABLE \ |
John Porto | ba6a67c | 2015-09-25 15:19:45 -0700 | [diff] [blame] | 73 | /* tag, element type, int_width, vec_width, addr bits sext, zext, \ |
John Porto | f5f02f7 | 2015-11-09 14:52:40 -0800 | [diff] [blame] | 74 | reg-reg addr allowed, shift allowed, */ \ |
| 75 | X(IceType_void, IceType_void, "" , "" , 0 , 0 , 0, 0) \ |
| 76 | X(IceType_i1, IceType_void, "b", "" , 8 , 12, 1, 1) \ |
| 77 | X(IceType_i8, IceType_void, "b", "" , 8 , 12, 1, 1) \ |
| 78 | X(IceType_i16, IceType_void, "h", "" , 8 , 8 , 1, 0) \ |
| 79 | X(IceType_i32, IceType_void, "" , "" , 12, 12, 1, 1) \ |
| 80 | X(IceType_i64, IceType_void, "d", "" , 12, 12, 1, 1) \ |
| 81 | X(IceType_f32, IceType_void, "" , ".f32", 8, 8 , 0, 0) \ |
| 82 | X(IceType_f64, IceType_void, "" , ".f64", 8, 8 , 0, 0) \ |
| 83 | X(IceType_v4i1, IceType_i32 , "" , ".i32", 0 , 0 , 1, 0) \ |
| 84 | X(IceType_v8i1, IceType_i16 , "" , ".i16", 0 , 0 , 1, 0) \ |
| 85 | X(IceType_v16i1, IceType_i8 , "" , ".i8" , 0 , 0 , 1, 0) \ |
| 86 | X(IceType_v16i8, IceType_i8 , "" , ".i8" , 0 , 0 , 1, 0) \ |
| 87 | X(IceType_v8i16, IceType_i16 , "" , ".i16", 0 , 0 , 1, 0) \ |
| 88 | X(IceType_v4i32, IceType_i32 , "" , ".i32", 0 , 0 , 1, 0) \ |
| 89 | X(IceType_v4f32, IceType_f32 , "" , ".f32", 0 , 0 , 1, 0) |
| 90 | //#define X(tag, elementty, int_width, vec_width, sbits, ubits, rraddr, shaddr) |
Jan Voung | b36ad9b | 2015-04-21 17:01:49 -0700 | [diff] [blame] | 91 | |
Jan Voung | b3401d2 | 2015-05-18 09:38:21 -0700 | [diff] [blame] | 92 | // Shifter types for Data-processing operands as defined in section A5.1.2. |
Jan Voung | 86ebec1 | 2015-08-09 07:58:35 -0700 | [diff] [blame] | 93 | #define ICEINSTARM32SHIFT_TABLE \ |
| 94 | /* enum value, emit */ \ |
| 95 | X(LSL, "lsl") \ |
| 96 | X(LSR, "lsr") \ |
| 97 | X(ASR, "asr") \ |
| 98 | X(ROR, "ror") \ |
| 99 | X(RRX, "rrx") |
Jan Voung | b3401d2 | 2015-05-18 09:38:21 -0700 | [diff] [blame] | 100 | //#define X(tag, emit) |
| 101 | |
Andrew Scull | 57e1268 | 2015-09-16 11:30:19 -0700 | [diff] [blame] | 102 | // Attributes for the condition code 4-bit encoding (that is independent of the |
| 103 | // APSR's NZCV fields). For example, EQ is 0, but corresponds to Z = 1, and NE |
| 104 | // is 1, but corresponds to Z = 0. |
Jan Voung | 86ebec1 | 2015-08-09 07:58:35 -0700 | [diff] [blame] | 105 | #define ICEINSTARM32COND_TABLE \ |
| 106 | /* enum value, encoding, opposite, emit */ \ |
Jim Stichnoth | 5bff61c | 2015-10-28 09:26:00 -0700 | [diff] [blame] | 107 | X(EQ, 0, NE, "eq") /* equal */ \ |
| 108 | X(NE, 1, EQ, "ne") /* not equal */ \ |
| 109 | X(CS, 2, CC, "cs") /* carry set/unsigned (AKA hs: higher or same) */ \ |
| 110 | X(CC, 3, CS, "cc") /* carry clear/unsigned (AKA lo: lower) */ \ |
| 111 | X(MI, 4, PL, "mi") /* minus/negative */ \ |
| 112 | X(PL, 5, MI, "pl") /* plus/positive or zero */ \ |
| 113 | X(VS, 6, VC, "vs") /* overflow (float unordered) */ \ |
| 114 | X(VC, 7, VS, "vc") /* no overflow (float not unordered) */ \ |
| 115 | X(HI, 8, LS, "hi") /* unsigned higher */ \ |
| 116 | X(LS, 9, HI, "ls") /* unsigned lower or same */ \ |
| 117 | X(GE, 10, LT, "ge") /* signed greater than or equal */ \ |
| 118 | X(LT, 11, GE, "lt") /* signed less than */ \ |
| 119 | X(GT, 12, LE, "gt") /* signed greater than */ \ |
| 120 | X(LE, 13, GT, "le") /* signed less than or equal */ \ |
| 121 | X(AL, 14, kNone, "") /* always (unconditional) */ \ |
Jan Voung | 86ebec1 | 2015-08-09 07:58:35 -0700 | [diff] [blame] | 122 | X(kNone, 15, kNone, "??") /* special condition / none */ |
John Porto | ed2c06b | 2015-10-01 15:27:15 -0700 | [diff] [blame] | 123 | //#define X(tag, encode, opp, emit) |
Jan Voung | 3bfd99a | 2015-05-22 16:35:25 -0700 | [diff] [blame] | 124 | |
Jan Voung | b36ad9b | 2015-04-21 17:01:49 -0700 | [diff] [blame] | 125 | #endif // SUBZERO_SRC_ICEINSTARM32_DEF |