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wdenkf4675562002-10-02 14:20:15 +00001/*
Wolfgang Denk29f8f582008-08-09 23:17:32 +02002 * (C) Copyright 2000-2008
wdenkf4675562002-10-02 14:20:15 +00003 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24/*
25 * board/config.h - configuration options, board specific
26 */
27
28#ifndef __CONFIG_H
29#define __CONFIG_H
30
31/*
32 * High Level Configuration Options
33 * (easy to change)
34 */
35
36#define CONFIG_MPC823 1 /* This is a MPC823 CPU */
37#define CONFIG_TQM823L 1 /* ...on a TQM8xxL module */
38
39#ifdef CONFIG_LCD /* with LCD controller ? */
Wolfgang Denk21f971e2008-07-07 01:22:29 +020040#define CONFIG_LCD_LOGO 1 /* print our logo on the LCD */
41#define CONFIG_LCD_INFO 1 /* ... and some board info */
wdenk27b207f2003-07-24 23:38:38 +000042#define CONFIG_SPLASH_SCREEN /* ... with splashscreen support*/
wdenkf4675562002-10-02 14:20:15 +000043#endif
44
45#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
Wolfgang Denk3cb7a482009-07-28 22:13:52 +020046#define CONFIG_SYS_SMC_RXBUFLEN 128
47#define CONFIG_SYS_MAXIDLE 10
wdenkf4675562002-10-02 14:20:15 +000048#define CONFIG_BAUDRATE 115200 /* console baudrate = 115kbps */
wdenkf4675562002-10-02 14:20:15 +000049
wdenkae3af052003-08-07 22:18:11 +000050#define CONFIG_BOOTCOUNT_LIMIT
51
52#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
wdenkf4675562002-10-02 14:20:15 +000053
54#define CONFIG_BOARD_TYPES 1 /* support board types */
55
Wolfgang Denk32bf3d12008-03-03 12:16:44 +010056#define CONFIG_PREBOOT "echo;echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;echo"
wdenkf4675562002-10-02 14:20:15 +000057
58#undef CONFIG_BOOTARGS
wdenk6aff3112002-12-17 01:51:00 +000059
60#define CONFIG_EXTRA_ENV_SETTINGS \
wdenkae3af052003-08-07 22:18:11 +000061 "netdev=eth0\0" \
wdenk6aff3112002-12-17 01:51:00 +000062 "nfsargs=setenv bootargs root=/dev/nfs rw " \
Wolfgang Denkfe126d82005-11-20 21:40:11 +010063 "nfsroot=${serverip}:${rootpath}\0" \
wdenk6aff3112002-12-17 01:51:00 +000064 "ramargs=setenv bootargs root=/dev/ram rw\0" \
Wolfgang Denkfe126d82005-11-20 21:40:11 +010065 "addip=setenv bootargs ${bootargs} " \
66 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
67 ":${hostname}:${netdev}:off panic=1\0" \
wdenk6aff3112002-12-17 01:51:00 +000068 "flash_nfs=run nfsargs addip;" \
Wolfgang Denkfe126d82005-11-20 21:40:11 +010069 "bootm ${kernel_addr}\0" \
wdenk6aff3112002-12-17 01:51:00 +000070 "flash_self=run ramargs addip;" \
Wolfgang Denkfe126d82005-11-20 21:40:11 +010071 "bootm ${kernel_addr} ${ramdisk_addr}\0" \
72 "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \
wdenk6aff3112002-12-17 01:51:00 +000073 "rootpath=/opt/eldk/ppc_8xx\0" \
Wolfgang Denk29f8f582008-08-09 23:17:32 +020074 "hostname=TQM823L\0" \
75 "bootfile=TQM823L/uImage\0" \
Wolfgang Denkeb6da802007-09-16 02:39:35 +020076 "fdt_addr=40040000\0" \
77 "kernel_addr=40060000\0" \
78 "ramdisk_addr=40200000\0" \
Wolfgang Denk29f8f582008-08-09 23:17:32 +020079 "u-boot=TQM823L/u-image.bin\0" \
80 "load=tftp 200000 ${u-boot}\0" \
81 "update=prot off 40000000 +${filesize};" \
82 "era 40000000 +${filesize};" \
83 "cp.b 200000 40000000 ${filesize};" \
84 "sete filesize;save\0" \
wdenk6aff3112002-12-17 01:51:00 +000085 ""
86#define CONFIG_BOOTCOMMAND "run flash_self"
wdenkf4675562002-10-02 14:20:15 +000087
88#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020089#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */
wdenkf4675562002-10-02 14:20:15 +000090
91#undef CONFIG_WATCHDOG /* watchdog disabled */
92
wdenka522fa02004-01-04 22:51:12 +000093#if defined(CONFIG_LCD)
wdenkf4675562002-10-02 14:20:15 +000094# undef CONFIG_STATUS_LED /* disturbs display */
95#else
96# define CONFIG_STATUS_LED 1 /* Status LED enabled */
97#endif /* CONFIG_LCD */
98
wdenka522fa02004-01-04 22:51:12 +000099#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */
wdenkf4675562002-10-02 14:20:15 +0000100
Jon Loeliger37d4bb72007-07-09 21:38:02 -0500101/*
102 * BOOTP options
103 */
104#define CONFIG_BOOTP_SUBNETMASK
105#define CONFIG_BOOTP_GATEWAY
106#define CONFIG_BOOTP_HOSTNAME
107#define CONFIG_BOOTP_BOOTPATH
108#define CONFIG_BOOTP_BOOTFILESIZE
109
wdenkf4675562002-10-02 14:20:15 +0000110
111#define CONFIG_MAC_PARTITION
112#define CONFIG_DOS_PARTITION
113
114#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */
115
Jon Loeliger26946902007-07-04 22:30:50 -0500116
117/*
118 * Command line configuration.
119 */
120#include <config_cmd_default.h>
121
122#define CONFIG_CMD_ASKENV
123#define CONFIG_CMD_DATE
124#define CONFIG_CMD_DHCP
Wolfgang Denk29f8f582008-08-09 23:17:32 +0200125#define CONFIG_CMD_ELF
Wolfgang Denk9a63b7f2009-02-21 21:51:21 +0100126#define CONFIG_CMD_EXT2
Jon Loeliger26946902007-07-04 22:30:50 -0500127#define CONFIG_CMD_IDE
Wolfgang Denk29f8f582008-08-09 23:17:32 +0200128#define CONFIG_CMD_JFFS2
Jon Loeliger26946902007-07-04 22:30:50 -0500129#define CONFIG_CMD_NFS
130#define CONFIG_CMD_SNTP
131
wdenk27b207f2003-07-24 23:38:38 +0000132#ifdef CONFIG_SPLASH_SCREEN
Jon Loeliger26946902007-07-04 22:30:50 -0500133 #define CONFIG_CMD_BMP
wdenk27b207f2003-07-24 23:38:38 +0000134#endif
wdenkf4675562002-10-02 14:20:15 +0000135
wdenkf4675562002-10-02 14:20:15 +0000136
Wolfgang Denk29f8f582008-08-09 23:17:32 +0200137#define CONFIG_NETCONSOLE
138
wdenkf4675562002-10-02 14:20:15 +0000139/*
140 * Miscellaneous configurable options
141 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200142#define CONFIG_SYS_LONGHELP /* undef to save memory */
143#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
wdenk6aff3112002-12-17 01:51:00 +0000144
Wolfgang Denk2751a952006-10-28 02:29:14 +0200145#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200146#define CONFIG_SYS_HUSH_PARSER 1 /* Use the HUSH parser */
147#ifdef CONFIG_SYS_HUSH_PARSER
148#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
wdenk6aff3112002-12-17 01:51:00 +0000149#endif
150
Jon Loeliger26946902007-07-04 22:30:50 -0500151#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200152#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
wdenkf4675562002-10-02 14:20:15 +0000153#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200154#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
wdenkf4675562002-10-02 14:20:15 +0000155#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200156#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
157#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
158#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
wdenkf4675562002-10-02 14:20:15 +0000159
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200160#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
161#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
wdenkf4675562002-10-02 14:20:15 +0000162
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200163#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
wdenkf4675562002-10-02 14:20:15 +0000164
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200165#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
wdenkf4675562002-10-02 14:20:15 +0000166
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200167#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
wdenkf4675562002-10-02 14:20:15 +0000168
169/*
170 * Low Level Configuration Settings
171 * (address mappings, register initial values, etc.)
172 * You should know what you are doing if you make changes here.
173 */
174/*-----------------------------------------------------------------------
175 * Internal Memory Mapped Register
176 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200177#define CONFIG_SYS_IMMR 0xFFF00000
wdenkf4675562002-10-02 14:20:15 +0000178
179/*-----------------------------------------------------------------------
180 * Definitions for initial stack pointer and data area (in DPRAM)
181 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200182#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
183#define CONFIG_SYS_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */
184#define CONFIG_SYS_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
185#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
186#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
wdenkf4675562002-10-02 14:20:15 +0000187
188/*-----------------------------------------------------------------------
189 * Start addresses for the final memory configuration
190 * (Set up by the startup code)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200191 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
wdenkf4675562002-10-02 14:20:15 +0000192 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200193#define CONFIG_SYS_SDRAM_BASE 0x00000000
194#define CONFIG_SYS_FLASH_BASE 0x40000000
195#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
196#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
197#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
wdenkf4675562002-10-02 14:20:15 +0000198
199/*
200 * For booting Linux, the board info and command line data
201 * have to be in the first 8 MB of memory, since this is
202 * the maximum mapped by the Linux kernel during initialization.
203 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200204#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
wdenkf4675562002-10-02 14:20:15 +0000205
206/*-----------------------------------------------------------------------
207 * FLASH organization
208 */
wdenkf4675562002-10-02 14:20:15 +0000209
Martin Krausee318d9e2007-09-27 11:10:08 +0200210/* use CFI flash driver */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200211#define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */
Jean-Christophe PLAGNIOL-VILLARD00b18832008-08-13 01:40:42 +0200212#define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200213#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE+flash_info[0].size }
214#define CONFIG_SYS_FLASH_EMPTY_INFO
215#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1
216#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */
217#define CONFIG_SYS_MAX_FLASH_SECT 71 /* max number of sectors on one chip */
wdenkf4675562002-10-02 14:20:15 +0000218
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200219#define CONFIG_ENV_IS_IN_FLASH 1
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200220#define CONFIG_ENV_OFFSET 0x8000 /* Offset of Environment Sector */
221#define CONFIG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
wdenkf4675562002-10-02 14:20:15 +0000222
223/* Address and size of Redundant Environment Sector */
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200224#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET+CONFIG_ENV_SIZE)
225#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
wdenkf4675562002-10-02 14:20:15 +0000226
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200227#define CONFIG_SYS_USE_PPCENV /* Environment embedded in sect .ppcenv */
Wolfgang Denk67c31032007-09-16 17:10:04 +0200228
Wolfgang Denk7c803be2008-09-16 18:02:19 +0200229#define CONFIG_MISC_INIT_R /* Make sure to remap flashes correctly */
230
wdenkf4675562002-10-02 14:20:15 +0000231/*-----------------------------------------------------------------------
Wolfgang Denk29f8f582008-08-09 23:17:32 +0200232 * Dynamic MTD partition support
233 */
Stefan Roese68d7d652009-03-19 13:30:36 +0100234#define CONFIG_CMD_MTDPARTS
Stefan Roese942556a2009-05-12 14:32:58 +0200235#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */
236#define CONFIG_FLASH_CFI_MTD
Wolfgang Denk29f8f582008-08-09 23:17:32 +0200237#define MTDIDS_DEFAULT "nor0=TQM8xxL-0"
238
239#define MTDPARTS_DEFAULT "mtdparts=TQM8xxL-0:256k(u-boot)," \
240 "128k(dtb)," \
241 "1664k(kernel)," \
242 "2m(rootfs)," \
Wolfgang Denkcd829192008-08-12 16:08:38 +0200243 "4m(data)"
Wolfgang Denk29f8f582008-08-09 23:17:32 +0200244
245/*-----------------------------------------------------------------------
wdenkf4675562002-10-02 14:20:15 +0000246 * Hardware Information Block
247 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200248#define CONFIG_SYS_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */
249#define CONFIG_SYS_HWINFO_SIZE 0x00000040 /* size of HW Info block */
250#define CONFIG_SYS_HWINFO_MAGIC 0x54514D38 /* 'TQM8' */
wdenkf4675562002-10-02 14:20:15 +0000251
252/*-----------------------------------------------------------------------
253 * Cache Configuration
254 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200255#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
Jon Loeliger26946902007-07-04 22:30:50 -0500256#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200257#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */
wdenkf4675562002-10-02 14:20:15 +0000258#endif
259
260/*-----------------------------------------------------------------------
261 * SYPCR - System Protection Control 11-9
262 * SYPCR can only be written once after reset!
263 *-----------------------------------------------------------------------
264 * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
265 */
266#if defined(CONFIG_WATCHDOG)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200267#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
wdenkf4675562002-10-02 14:20:15 +0000268 SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
269#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200270#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
wdenkf4675562002-10-02 14:20:15 +0000271#endif
272
273/*-----------------------------------------------------------------------
274 * SIUMCR - SIU Module Configuration 11-6
275 *-----------------------------------------------------------------------
276 * PCMCIA config., multi-function pin tri-state
277 */
278#ifndef CONFIG_CAN_DRIVER
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200279#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
wdenkf4675562002-10-02 14:20:15 +0000280#else /* we must activate GPL5 in the SIUMCR for CAN */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200281#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
wdenkf4675562002-10-02 14:20:15 +0000282#endif /* CONFIG_CAN_DRIVER */
283
284/*-----------------------------------------------------------------------
285 * TBSCR - Time Base Status and Control 11-26
286 *-----------------------------------------------------------------------
287 * Clear Reference Interrupt Status, Timebase freezing enabled
288 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200289#define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
wdenkf4675562002-10-02 14:20:15 +0000290
291/*-----------------------------------------------------------------------
292 * RTCSC - Real-Time Clock Status and Control Register 11-27
293 *-----------------------------------------------------------------------
294 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200295#define CONFIG_SYS_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
wdenkf4675562002-10-02 14:20:15 +0000296
297/*-----------------------------------------------------------------------
298 * PISCR - Periodic Interrupt Status and Control 11-31
299 *-----------------------------------------------------------------------
300 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
301 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200302#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF)
wdenkf4675562002-10-02 14:20:15 +0000303
304/*-----------------------------------------------------------------------
305 * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
306 *-----------------------------------------------------------------------
307 * Reset PLL lock status sticky bit, timer expired status bit and timer
308 * interrupt status bit
wdenkf4675562002-10-02 14:20:15 +0000309 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200310#define CONFIG_SYS_PLPRCR (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
wdenkf4675562002-10-02 14:20:15 +0000311
312/*-----------------------------------------------------------------------
313 * SCCR - System Clock and reset Control Register 15-27
314 *-----------------------------------------------------------------------
315 * Set clock output, timebase and RTC source and divider,
316 * power management and some other internal clocks
317 */
318#define SCCR_MASK SCCR_EBDF11
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200319#define CONFIG_SYS_SCCR (SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
wdenkf4675562002-10-02 14:20:15 +0000320 SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \
321 SCCR_DFALCD00)
wdenkf4675562002-10-02 14:20:15 +0000322
323/*-----------------------------------------------------------------------
324 * PCMCIA stuff
325 *-----------------------------------------------------------------------
326 *
327 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200328#define CONFIG_SYS_PCMCIA_MEM_ADDR (0xE0000000)
329#define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 )
330#define CONFIG_SYS_PCMCIA_DMA_ADDR (0xE4000000)
331#define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 )
332#define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0xE8000000)
333#define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 )
334#define CONFIG_SYS_PCMCIA_IO_ADDR (0xEC000000)
335#define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 )
wdenkf4675562002-10-02 14:20:15 +0000336
337/*-----------------------------------------------------------------------
338 * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
339 *-----------------------------------------------------------------------
340 */
341
342#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */
343
344#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
345#undef CONFIG_IDE_LED /* LED for ide not supported */
346#undef CONFIG_IDE_RESET /* reset for ide not supported */
347
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200348#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */
349#define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */
wdenkf4675562002-10-02 14:20:15 +0000350
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200351#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
wdenkf4675562002-10-02 14:20:15 +0000352
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200353#define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_PCMCIA_MEM_ADDR
wdenkf4675562002-10-02 14:20:15 +0000354
355/* Offset for data I/O */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200356#define CONFIG_SYS_ATA_DATA_OFFSET (CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
wdenkf4675562002-10-02 14:20:15 +0000357
358/* Offset for normal register accesses */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200359#define CONFIG_SYS_ATA_REG_OFFSET (2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
wdenkf4675562002-10-02 14:20:15 +0000360
361/* Offset for alternate registers */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200362#define CONFIG_SYS_ATA_ALT_OFFSET 0x0100
wdenkf4675562002-10-02 14:20:15 +0000363
364/*-----------------------------------------------------------------------
365 *
366 *-----------------------------------------------------------------------
367 *
368 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200369#define CONFIG_SYS_DER 0
wdenkf4675562002-10-02 14:20:15 +0000370
371/*
372 * Init Memory Controller:
373 *
374 * BR0/1 and OR0/1 (FLASH)
375 */
376
377#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */
378#define FLASH_BASE1_PRELIM 0x60000000 /* FLASH bank #0 */
379
380/* used to re-map FLASH both when starting from SRAM or FLASH:
381 * restrict access enough to keep SRAM working (if any)
382 * but not too much to meddle with FLASH accesses
383 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200384#define CONFIG_SYS_REMAP_OR_AM 0x80000000 /* OR addr mask */
385#define CONFIG_SYS_PRELIM_OR_AM 0xE0000000 /* OR addr mask */
wdenkf4675562002-10-02 14:20:15 +0000386
387/*
388 * FLASH timing:
389 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200390#define CONFIG_SYS_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \
wdenkf4675562002-10-02 14:20:15 +0000391 OR_SCY_3_CLK | OR_EHTR | OR_BI)
wdenkf4675562002-10-02 14:20:15 +0000392
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200393#define CONFIG_SYS_OR0_REMAP (CONFIG_SYS_REMAP_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
394#define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
395#define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V )
wdenkf4675562002-10-02 14:20:15 +0000396
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200397#define CONFIG_SYS_OR1_REMAP CONFIG_SYS_OR0_REMAP
398#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR0_PRELIM
399#define CONFIG_SYS_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V )
wdenkf4675562002-10-02 14:20:15 +0000400
401/*
402 * BR2/3 and OR2/3 (SDRAM)
403 *
404 */
405#define SDRAM_BASE2_PRELIM 0x00000000 /* SDRAM bank #0 */
406#define SDRAM_BASE3_PRELIM 0x20000000 /* SDRAM bank #1 */
407#define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB per bank */
408
409/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200410#define CONFIG_SYS_OR_TIMING_SDRAM 0x00000A00
wdenkf4675562002-10-02 14:20:15 +0000411
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200412#define CONFIG_SYS_OR2_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_SDRAM )
413#define CONFIG_SYS_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
wdenkf4675562002-10-02 14:20:15 +0000414
415#ifndef CONFIG_CAN_DRIVER
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200416#define CONFIG_SYS_OR3_PRELIM CONFIG_SYS_OR2_PRELIM
417#define CONFIG_SYS_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
wdenkf4675562002-10-02 14:20:15 +0000418#else /* CAN uses CS3#, so we can have only one SDRAM bank anyway */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200419#define CONFIG_SYS_CAN_BASE 0xC0000000 /* CAN mapped at 0xC0000000 */
420#define CONFIG_SYS_CAN_OR_AM 0xFFFF8000 /* 32 kB address mask */
421#define CONFIG_SYS_OR3_CAN (CONFIG_SYS_CAN_OR_AM | OR_G5LA | OR_BI)
422#define CONFIG_SYS_BR3_CAN ((CONFIG_SYS_CAN_BASE & BR_BA_MSK) | \
wdenkf4675562002-10-02 14:20:15 +0000423 BR_PS_8 | BR_MS_UPMB | BR_V )
424#endif /* CONFIG_CAN_DRIVER */
425
426/*
427 * Memory Periodic Timer Prescaler
428 *
429 * The Divider for PTA (refresh timer) configuration is based on an
430 * example SDRAM configuration (64 MBit, one bank). The adjustment to
431 * the number of chip selects (NCS) and the actually needed refresh
432 * rate is done by setting MPTPR.
433 *
434 * PTA is calculated from
435 * PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS)
436 *
437 * gclk CPU clock (not bus clock!)
438 * Trefresh Refresh cycle * 4 (four word bursts used)
439 *
440 * 4096 Rows from SDRAM example configuration
441 * 1000 factor s -> ms
442 * 32 PTP (pre-divider from MPTPR) from SDRAM example configuration
443 * 4 Number of refresh cycles per period
444 * 64 Refresh cycle in ms per number of rows
445 * --------------------------------------------
446 * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000
447 *
448 * 50 MHz => 50.000.000 / Divider = 98
449 * 66 Mhz => 66.000.000 / Divider = 129
450 * 80 Mhz => 80.000.000 / Divider = 156
451 */
wdenke9132ea2004-04-24 23:23:30 +0000452
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200453#define CONFIG_SYS_PTA_PER_CLK ((4096 * 32 * 1000) / (4 * 64))
454#define CONFIG_SYS_MAMR_PTA 98
wdenkf4675562002-10-02 14:20:15 +0000455
456/*
457 * For 16 MBit, refresh rates could be 31.3 us
458 * (= 64 ms / 2K = 125 / quad bursts).
459 * For a simpler initialization, 15.6 us is used instead.
460 *
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200461 * #define CONFIG_SYS_MPTPR_2BK_2K MPTPR_PTP_DIV32 for 2 banks
462 * #define CONFIG_SYS_MPTPR_1BK_2K MPTPR_PTP_DIV64 for 1 bank
wdenkf4675562002-10-02 14:20:15 +0000463 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200464#define CONFIG_SYS_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */
465#define CONFIG_SYS_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */
wdenkf4675562002-10-02 14:20:15 +0000466
467/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200468#define CONFIG_SYS_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */
469#define CONFIG_SYS_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */
wdenkf4675562002-10-02 14:20:15 +0000470
471/*
472 * MAMR settings for SDRAM
473 */
474
475/* 8 column SDRAM */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200476#define CONFIG_SYS_MAMR_8COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
wdenkf4675562002-10-02 14:20:15 +0000477 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \
478 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
479/* 9 column SDRAM */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200480#define CONFIG_SYS_MAMR_9COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
wdenkf4675562002-10-02 14:20:15 +0000481 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \
482 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
483
484
485/*
486 * Internal Definitions
487 *
488 * Boot Flags
489 */
490#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
491#define BOOTFLAG_WARM 0x02 /* Software reboot */
492
Heiko Schocher7026ead2010-02-09 15:50:27 +0100493/* pass open firmware flat tree */
494#define CONFIG_OF_LIBFDT 1
495#define CONFIG_OF_BOARD_SETUP 1
496#define CONFIG_HWCONFIG 1
497
wdenkf4675562002-10-02 14:20:15 +0000498#endif /* __CONFIG_H */