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Rajeshwari Birje76dd9b62013-12-26 09:44:26 +05301/*
2 * Copyright (C) 2013 Samsung Electronics
3 *
4 * Configuration settings for the SAMSUNG EXYNOS5 board.
5 *
6 * SPDX-License-Identifier: GPL-2.0+
7 */
8
9#ifndef __CONFIG_H
10#define __CONFIG_H
11
12/* High Level Configuration Options */
13#define CONFIG_SAMSUNG /* in a SAMSUNG core */
14#define CONFIG_S5P /* S5P Family */
15#define CONFIG_EXYNOS5 /* which is in a Exynos5 Family */
16
17#include <asm/arch/cpu.h> /* get chip and board defs */
18
19#define CONFIG_SYS_GENERIC_BOARD
20#define CONFIG_ARCH_CPU_INIT
21#define CONFIG_DISPLAY_CPUINFO
22#define CONFIG_DISPLAY_BOARDINFO
23#define CONFIG_BOARD_COMMON
24#define CONFIG_ARCH_EARLY_INIT_R
25#define CONFIG_EXYNOS_SPL
26
27/* Enable fdt support for Exynos5250 */
28#define CONFIG_OF_CONTROL
29#define CONFIG_OF_SEPARATE
30
31/* Allow tracing to be enabled */
32#define CONFIG_TRACE
33#define CONFIG_CMD_TRACE
34#define CONFIG_TRACE_BUFFER_SIZE (16 << 20)
35#define CONFIG_TRACE_EARLY_SIZE (8 << 20)
36#define CONFIG_TRACE_EARLY
37#define CONFIG_TRACE_EARLY_ADDR 0x50000000
38
39/* Keep L2 Cache Disabled */
40#define CONFIG_SYS_DCACHE_OFF
41#define CONFIG_SYS_CACHELINE_SIZE 64
42
43/* Enable ACE acceleration for SHA1 and SHA256 */
44#define CONFIG_EXYNOS_ACE_SHA
45#define CONFIG_SHA_HW_ACCEL
46
47/* input clock of PLL: SMDK5250 has 24MHz input clock */
48#define CONFIG_SYS_CLK_FREQ 24000000
49
50#define CONFIG_SETUP_MEMORY_TAGS
51#define CONFIG_CMDLINE_TAG
52#define CONFIG_INITRD_TAG
53#define CONFIG_CMDLINE_EDITING
54
55/* Power Down Modes */
56#define S5P_CHECK_SLEEP 0x00000BAD
57#define S5P_CHECK_DIDLE 0xBAD00000
58#define S5P_CHECK_LPA 0xABAD0000
59
60/* Offset for inform registers */
61#define INFORM0_OFFSET 0x800
62#define INFORM1_OFFSET 0x804
63#define INFORM2_OFFSET 0x808
64#define INFORM3_OFFSET 0x80c
65
66/* Size of malloc() pool */
67#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (4 << 20))
68
69/* select serial console configuration */
70#define CONFIG_BAUDRATE 115200
71#define EXYNOS5_DEFAULT_UART_OFFSET 0x010000
72#define CONFIG_SILENT_CONSOLE
73
74/* Enable keyboard */
75#define CONFIG_CROS_EC /* CROS_EC protocol */
76#define CONFIG_CROS_EC_SPI /* Support CROS_EC over SPI */
77#define CONFIG_CROS_EC_I2C /* Support CROS_EC over I2C */
78#define CONFIG_CROS_EC_KEYB /* CROS_EC keyboard input */
79#define CONFIG_CMD_CROS_EC
80#define CONFIG_KEYBOARD
81
82/* Console configuration */
83#define CONFIG_CONSOLE_MUX
84#define CONFIG_SYS_CONSOLE_IS_IN_ENV
85#define EXYNOS_DEVICE_SETTINGS \
86 "stdin=serial,cros-ec-keyb\0" \
87 "stdout=serial,lcd\0" \
88 "stderr=serial,lcd\0"
89
90#define CONFIG_EXTRA_ENV_SETTINGS \
91 EXYNOS_DEVICE_SETTINGS
92
93/* SD/MMC configuration */
94#define CONFIG_GENERIC_MMC
95#define CONFIG_MMC
96#define CONFIG_SDHCI
97#define CONFIG_S5P_SDHCI
98#define CONFIG_DWMMC
99#define CONFIG_EXYNOS_DWMMC
100#define CONFIG_SUPPORT_EMMC_BOOT
Tom Rini7f673c92014-01-10 10:56:00 -0500101#define CONFIG_BOUNCE_BUFFER
Rajeshwari Birje76dd9b62013-12-26 09:44:26 +0530102
103#define CONFIG_BOARD_EARLY_INIT_F
104#define CONFIG_SKIP_LOWLEVEL_INIT
105
106/* PWM */
107#define CONFIG_PWM
108
109/* allow to overwrite serial and ethaddr */
110#define CONFIG_ENV_OVERWRITE
111
112/* Command definition*/
113#include <config_cmd_default.h>
114
115#define CONFIG_CMD_PING
116#define CONFIG_CMD_ELF
117#define CONFIG_CMD_MMC
118#define CONFIG_CMD_EXT2
119#define CONFIG_CMD_FAT
120#define CONFIG_CMD_NET
121#define CONFIG_CMD_HASH
122
123#define CONFIG_BOOTDELAY 3
124#define CONFIG_ZERO_BOOTDELAY_CHECK
125
126/* Thermal Management Unit */
127#define CONFIG_EXYNOS_TMU
128#define CONFIG_CMD_DTT
129#define CONFIG_TMU_CMD_DTT
130
131/* TPM */
132#define CONFIG_TPM
133#define CONFIG_CMD_TPM
134#define CONFIG_TPM_TIS_I2C
135#define CONFIG_TPM_TIS_I2C_BUS_NUMBER 3
136#define CONFIG_TPM_TIS_I2C_SLAVE_ADDR 0x20
137
138/* MMC SPL */
139#define CONFIG_SPL
140#define COPY_BL2_FNPTR_ADDR 0x02020030
141
142#define CONFIG_SPL_LIBCOMMON_SUPPORT
143#define CONFIG_SPL_GPIO_SUPPORT
144
145/* specific .lds file */
146#define CONFIG_SPL_LDSCRIPT "board/samsung/common/exynos-uboot-spl.lds"
147#define CONFIG_SPL_MAX_FOOTPRINT (14 * 1024)
148
149
150/* Miscellaneous configurable options */
151#define CONFIG_SYS_LONGHELP /* undef to save memory */
152#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
153#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
154#define CONFIG_SYS_PBSIZE 384 /* Print Buffer Size */
155#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
156#define CONFIG_DEFAULT_CONSOLE "console=ttySAC1,115200n8\0"
157/* Boot Argument Buffer Size */
158#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
159/* memtest works on */
160#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE
161#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x5E00000)
162#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x3E00000)
163
164#define CONFIG_RD_LVL
165
166#define CONFIG_NR_DRAM_BANKS 8
167#define SDRAM_BANK_SIZE (256UL << 20UL) /* 256 MB */
168#define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE
169#define PHYS_SDRAM_1_SIZE SDRAM_BANK_SIZE
170#define PHYS_SDRAM_2 (CONFIG_SYS_SDRAM_BASE + SDRAM_BANK_SIZE)
171#define PHYS_SDRAM_2_SIZE SDRAM_BANK_SIZE
172#define PHYS_SDRAM_3 (CONFIG_SYS_SDRAM_BASE + (2 * SDRAM_BANK_SIZE))
173#define PHYS_SDRAM_3_SIZE SDRAM_BANK_SIZE
174#define PHYS_SDRAM_4 (CONFIG_SYS_SDRAM_BASE + (3 * SDRAM_BANK_SIZE))
175#define PHYS_SDRAM_4_SIZE SDRAM_BANK_SIZE
176#define PHYS_SDRAM_5 (CONFIG_SYS_SDRAM_BASE + (4 * SDRAM_BANK_SIZE))
177#define PHYS_SDRAM_5_SIZE SDRAM_BANK_SIZE
178#define PHYS_SDRAM_6 (CONFIG_SYS_SDRAM_BASE + (5 * SDRAM_BANK_SIZE))
179#define PHYS_SDRAM_6_SIZE SDRAM_BANK_SIZE
180#define PHYS_SDRAM_7 (CONFIG_SYS_SDRAM_BASE + (6 * SDRAM_BANK_SIZE))
181#define PHYS_SDRAM_7_SIZE SDRAM_BANK_SIZE
182#define PHYS_SDRAM_8 (CONFIG_SYS_SDRAM_BASE + (7 * SDRAM_BANK_SIZE))
183#define PHYS_SDRAM_8_SIZE SDRAM_BANK_SIZE
184
185#define CONFIG_SYS_MONITOR_BASE 0x00000000
186
187/* FLASH and environment organization */
188#define CONFIG_SYS_NO_FLASH
189#undef CONFIG_CMD_IMLS
190
191#define CONFIG_SYS_MMC_ENV_DEV 0
192
193#define CONFIG_SECURE_BL1_ONLY
194
195/* Secure FW size configuration */
196#ifdef CONFIG_SECURE_BL1_ONLY
197#define CONFIG_SEC_FW_SIZE (8 << 10) /* 8KB */
198#else
199#define CONFIG_SEC_FW_SIZE 0
200#endif
201
202/* Configuration of BL1, BL2, ENV Blocks on mmc */
203#define CONFIG_RES_BLOCK_SIZE (512)
204#define CONFIG_BL1_SIZE (16 << 10) /*16 K reserved for BL1*/
205#define CONFIG_BL2_SIZE (512UL << 10UL) /* 512 KB */
206#define CONFIG_ENV_SIZE (16 << 10) /* 16 KB */
207
208#define CONFIG_BL1_OFFSET (CONFIG_RES_BLOCK_SIZE + CONFIG_SEC_FW_SIZE)
209#define CONFIG_BL2_OFFSET (CONFIG_BL1_OFFSET + CONFIG_BL1_SIZE)
210#define CONFIG_ENV_OFFSET (CONFIG_BL2_OFFSET + CONFIG_BL2_SIZE)
211
212/* U-boot copy size from boot Media to DRAM.*/
213#define BL2_START_OFFSET (CONFIG_BL2_OFFSET/512)
214#define BL2_SIZE_BLOC_COUNT (CONFIG_BL2_SIZE/512)
215
216#define CONFIG_SPI_BOOTING
217#define EXYNOS_COPY_SPI_FNPTR_ADDR 0x02020058
218#define SPI_FLASH_UBOOT_POS (CONFIG_SEC_FW_SIZE + CONFIG_BL1_SIZE)
219
220#define CONFIG_DOS_PARTITION
221#define CONFIG_EFI_PARTITION
222#define CONFIG_CMD_PART
223#define CONFIG_PARTITION_UUIDS
224
225/* I2C */
226#define CONFIG_SYS_I2C_INIT_BOARD
227#define CONFIG_SYS_I2C
228#define CONFIG_CMD_I2C
229#define CONFIG_SYS_I2C_S3C24X0_SPEED 100000 /* 100 Kbps */
230#define CONFIG_SYS_I2C_S3C24X0
231#define CONFIG_I2C_MULTI_BUS
232#define CONFIG_SYS_I2C_S3C24X0_SLAVE 0x0
233#define CONFIG_I2C_EDID
234
235/* SPI */
236#define CONFIG_ENV_IS_IN_SPI_FLASH
237#define CONFIG_SPI_FLASH
238#define CONFIG_ENV_SPI_BASE 0x12D30000
239
240#ifdef CONFIG_SPI_FLASH
241#define CONFIG_EXYNOS_SPI
242#define CONFIG_CMD_SF
243#define CONFIG_CMD_SPI
244#define CONFIG_SPI_FLASH_WINBOND
245#define CONFIG_SPI_FLASH_GIGADEVICE
246#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0
247#define CONFIG_SF_DEFAULT_SPEED 50000000
248#define EXYNOS5_SPI_NUM_CONTROLLERS 5
249#define CONFIG_OF_SPI
250#endif
251
252#ifdef CONFIG_ENV_IS_IN_SPI_FLASH
253#define CONFIG_ENV_SPI_MODE SPI_MODE_0
254#define CONFIG_ENV_SECT_SIZE CONFIG_ENV_SIZE
255#define CONFIG_ENV_SPI_BUS 1
256#define CONFIG_ENV_SPI_MAX_HZ 50000000
257#endif
258
259/* PMIC */
260#define CONFIG_POWER
261#define CONFIG_POWER_I2C
262
263/* Ethernet Controllor Driver */
264#ifdef CONFIG_CMD_NET
265#define CONFIG_SMC911X
266#define CONFIG_SMC911X_BASE 0x5000000
267#define CONFIG_SMC911X_16_BIT
268#define CONFIG_ENV_SROM_BANK 1
269#endif /*CONFIG_CMD_NET*/
270
271/* Enable PXE Support */
272#ifdef CONFIG_CMD_NET
273#define CONFIG_CMD_PXE
274#define CONFIG_MENU
275#endif
276
277/* Enable devicetree support */
278#define CONFIG_OF_LIBFDT
279
280/* SHA hashing */
281#define CONFIG_CMD_HASH
282#define CONFIG_HASH_VERIFY
283#define CONFIG_SHA1
284#define CONFIG_SHA256
285
286/* Enable Time Command */
287#define CONFIG_CMD_TIME
288
289#define CONFIG_CMD_BOOTZ
290
Akshay Saraswat9b97b722014-05-13 10:30:15 +0530291#define CONFIG_CMD_GPIO
292
Rajeshwari Birje76dd9b62013-12-26 09:44:26 +0530293#endif /* __CONFIG_H */