blob: 293269c5732dfc96433e8fba18f36086de869088 [file] [log] [blame]
wdenk42d1f032003-10-15 23:53:47 +00001/*
wdenk97d80fc2004-06-09 00:34:46 +00002 * Copyright 2004 Freescale Semiconductor.
wdenk42d1f032003-10-15 23:53:47 +00003 * (C) Copyright 2003 Motorola Inc.
4 * Xianghua Xiao, (X.Xiao@motorola.com)
5 *
6 * (C) Copyright 2000
7 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
8 *
9 * See file CREDITS for list of people who contributed to this
10 * project.
11 *
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License as
14 * published by the Free Software Foundation; either version 2 of
15 * the License, or (at your option) any later version.
16 *
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 * MA 02111-1307 USA
26 */
27
28#include <common.h>
29#include <ppc_asm.tmpl>
30#include <asm/processor.h>
31
Wolfgang Denkd87080b2006-03-31 18:32:53 +020032DECLARE_GLOBAL_DATA_PTR;
33
wdenk42d1f032003-10-15 23:53:47 +000034/* --------------------------------------------------------------- */
35
wdenk42d1f032003-10-15 23:53:47 +000036void get_sys_info (sys_info_t * sysInfo)
37{
Kumar Galaf59b55a2007-11-27 23:25:02 -060038 volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
Andy Fleming66ed6cc2007-04-23 02:37:47 -050039 uint plat_ratio,e500_ratio,half_freqSystemBus;
wdenk42d1f032003-10-15 23:53:47 +000040
41 plat_ratio = (gur->porpllsr) & 0x0000003e;
42 plat_ratio >>= 1;
Andy Fleming66ed6cc2007-04-23 02:37:47 -050043 sysInfo->freqSystemBus = plat_ratio * CONFIG_SYS_CLK_FREQ;
wdenk42d1f032003-10-15 23:53:47 +000044 e500_ratio = (gur->porpllsr) & 0x003f0000;
45 e500_ratio >>= 16;
Andy Fleming66ed6cc2007-04-23 02:37:47 -050046
47 /* Divide before multiply to avoid integer
48 * overflow for processor speeds above 2GHz */
49 half_freqSystemBus = sysInfo->freqSystemBus/2;
50 sysInfo->freqProcessor = e500_ratio*half_freqSystemBus;
wdenk42d1f032003-10-15 23:53:47 +000051}
52
Andy Fleming66ed6cc2007-04-23 02:37:47 -050053
wdenk42d1f032003-10-15 23:53:47 +000054int get_clocks (void)
55{
wdenk42d1f032003-10-15 23:53:47 +000056 sys_info_t sys_info;
Jon Loeliger9c4c5ae2005-07-23 10:37:35 -050057#if defined(CONFIG_CPM2)
Kumar Galaaafeefb2007-11-28 00:36:33 -060058 volatile ccsr_cpm_t *cpm = (ccsr_cpm_t *)CFG_MPC85xx_CPM_ADDR;
wdenk42d1f032003-10-15 23:53:47 +000059 uint sccr, dfbrg;
60
61 /* set VCO = 4 * BRG */
Kumar Galaaafeefb2007-11-28 00:36:33 -060062 cpm->im_cpm_intctl.sccr &= 0xfffffffc;
63 sccr = cpm->im_cpm_intctl.sccr;
wdenk42d1f032003-10-15 23:53:47 +000064 dfbrg = (sccr & SCCR_DFBRG_MSK) >> SCCR_DFBRG_SHIFT;
65#endif
66 get_sys_info (&sys_info);
67 gd->cpu_clk = sys_info.freqProcessor;
68 gd->bus_clk = sys_info.freqSystemBus;
Jon Loeliger9c4c5ae2005-07-23 10:37:35 -050069#if defined(CONFIG_CPM2)
wdenk42d1f032003-10-15 23:53:47 +000070 gd->vco_out = 2*sys_info.freqSystemBus;
71 gd->cpm_clk = gd->vco_out / 2;
72 gd->scc_clk = gd->vco_out / 4;
73 gd->brg_clk = gd->vco_out / (1 << (2 * (dfbrg + 1)));
74#endif
75
76 if(gd->cpu_clk != 0) return (0);
77 else return (1);
78}
79
80
81/********************************************
82 * get_bus_freq
83 * return system bus freq in Hz
84 *********************************************/
85ulong get_bus_freq (ulong dummy)
86{
87 ulong val;
88
89 sys_info_t sys_info;
90
91 get_sys_info (&sys_info);
92 val = sys_info.freqSystemBus;
93
94 return val;
95}