sewardj | c97096c | 2004-06-30 09:28:04 +0000 | [diff] [blame] | 1 | |
| 2 | /*---------------------------------------------------------------*/ |
| 3 | /*--- ---*/ |
sewardj | c0ee2ed | 2004-07-27 10:29:41 +0000 | [diff] [blame] | 4 | /*--- This file (host-x86/hdefs.c) is ---*/ |
sewardj | dbcfae7 | 2005-08-02 11:14:04 +0000 | [diff] [blame] | 5 | /*--- Copyright (C) OpenWorks LLP. All rights reserved. ---*/ |
sewardj | c97096c | 2004-06-30 09:28:04 +0000 | [diff] [blame] | 6 | /*--- ---*/ |
| 7 | /*---------------------------------------------------------------*/ |
| 8 | |
sewardj | f8ed9d8 | 2004-11-12 17:40:23 +0000 | [diff] [blame] | 9 | /* |
| 10 | This file is part of LibVEX, a library for dynamic binary |
| 11 | instrumentation and translation. |
| 12 | |
sewardj | 7bd6ffe | 2005-08-03 16:07:36 +0000 | [diff] [blame] | 13 | Copyright (C) 2004-2005 OpenWorks LLP. All rights reserved. |
sewardj | f8ed9d8 | 2004-11-12 17:40:23 +0000 | [diff] [blame] | 14 | |
sewardj | 7bd6ffe | 2005-08-03 16:07:36 +0000 | [diff] [blame] | 15 | This library is made available under a dual licensing scheme. |
sewardj | f8ed9d8 | 2004-11-12 17:40:23 +0000 | [diff] [blame] | 16 | |
sewardj | 7bd6ffe | 2005-08-03 16:07:36 +0000 | [diff] [blame] | 17 | If you link LibVEX against other code all of which is itself |
| 18 | licensed under the GNU General Public License, version 2 dated June |
| 19 | 1991 ("GPL v2"), then you may use LibVEX under the terms of the GPL |
| 20 | v2, as appearing in the file LICENSE.GPL. If the file LICENSE.GPL |
| 21 | is missing, you can obtain a copy of the GPL v2 from the Free |
| 22 | Software Foundation Inc., 51 Franklin St, Fifth Floor, Boston, MA |
| 23 | 02110-1301, USA. |
| 24 | |
| 25 | For any other uses of LibVEX, you must first obtain a commercial |
| 26 | license from OpenWorks LLP. Please contact info@open-works.co.uk |
| 27 | for information about commercial licensing. |
| 28 | |
| 29 | This software is provided by OpenWorks LLP "as is" and any express |
| 30 | or implied warranties, including, but not limited to, the implied |
| 31 | warranties of merchantability and fitness for a particular purpose |
| 32 | are disclaimed. In no event shall OpenWorks LLP be liable for any |
| 33 | direct, indirect, incidental, special, exemplary, or consequential |
| 34 | damages (including, but not limited to, procurement of substitute |
| 35 | goods or services; loss of use, data, or profits; or business |
| 36 | interruption) however caused and on any theory of liability, |
| 37 | whether in contract, strict liability, or tort (including |
| 38 | negligence or otherwise) arising in any way out of the use of this |
| 39 | software, even if advised of the possibility of such damage. |
sewardj | f8ed9d8 | 2004-11-12 17:40:23 +0000 | [diff] [blame] | 40 | |
| 41 | Neither the names of the U.S. Department of Energy nor the |
| 42 | University of California nor the names of its contributors may be |
| 43 | used to endorse or promote products derived from this software |
| 44 | without prior written permission. |
sewardj | f8ed9d8 | 2004-11-12 17:40:23 +0000 | [diff] [blame] | 45 | */ |
| 46 | |
sewardj | 887a11a | 2004-07-05 17:26:47 +0000 | [diff] [blame] | 47 | #include "libvex_basictypes.h" |
| 48 | #include "libvex.h" |
sewardj | c4278f4 | 2004-11-26 13:18:19 +0000 | [diff] [blame] | 49 | #include "libvex_trc_values.h" |
sewardj | 35421a3 | 2004-07-05 13:12:34 +0000 | [diff] [blame] | 50 | |
sewardj | c0ee2ed | 2004-07-27 10:29:41 +0000 | [diff] [blame] | 51 | #include "main/vex_util.h" |
| 52 | #include "host-generic/h_generic_regs.h" |
| 53 | #include "host-x86/hdefs.h" |
sewardj | c97096c | 2004-06-30 09:28:04 +0000 | [diff] [blame] | 54 | |
| 55 | |
| 56 | /* --------- Registers. --------- */ |
| 57 | |
sewardj | 35421a3 | 2004-07-05 13:12:34 +0000 | [diff] [blame] | 58 | void ppHRegX86 ( HReg reg ) |
sewardj | c97096c | 2004-06-30 09:28:04 +0000 | [diff] [blame] | 59 | { |
| 60 | Int r; |
sewardj | d08f2d7 | 2004-12-01 23:19:36 +0000 | [diff] [blame] | 61 | static HChar* ireg32_names[8] |
sewardj | c97096c | 2004-06-30 09:28:04 +0000 | [diff] [blame] | 62 | = { "%eax", "%ecx", "%edx", "%ebx", "%esp", "%ebp", "%esi", "%edi" }; |
| 63 | /* Be generic for all virtual regs. */ |
| 64 | if (hregIsVirtual(reg)) { |
sewardj | 35421a3 | 2004-07-05 13:12:34 +0000 | [diff] [blame] | 65 | ppHReg(reg); |
sewardj | c97096c | 2004-06-30 09:28:04 +0000 | [diff] [blame] | 66 | return; |
| 67 | } |
| 68 | /* But specific for real regs. */ |
| 69 | switch (hregClass(reg)) { |
sewardj | 4a31b26 | 2004-12-01 02:24:44 +0000 | [diff] [blame] | 70 | case HRcInt32: |
sewardj | c97096c | 2004-06-30 09:28:04 +0000 | [diff] [blame] | 71 | r = hregNumber(reg); |
sewardj | 35421a3 | 2004-07-05 13:12:34 +0000 | [diff] [blame] | 72 | vassert(r >= 0 && r < 8); |
| 73 | vex_printf("%s", ireg32_names[r]); |
sewardj | c97096c | 2004-06-30 09:28:04 +0000 | [diff] [blame] | 74 | return; |
sewardj | 4a31b26 | 2004-12-01 02:24:44 +0000 | [diff] [blame] | 75 | case HRcFlt64: |
sewardj | c97096c | 2004-06-30 09:28:04 +0000 | [diff] [blame] | 76 | r = hregNumber(reg); |
sewardj | d7bd8ac | 2004-10-09 10:06:12 +0000 | [diff] [blame] | 77 | vassert(r >= 0 && r < 6); |
sewardj | 35421a3 | 2004-07-05 13:12:34 +0000 | [diff] [blame] | 78 | vex_printf("%%fake%d", r); |
sewardj | c97096c | 2004-06-30 09:28:04 +0000 | [diff] [blame] | 79 | return; |
sewardj | 4a31b26 | 2004-12-01 02:24:44 +0000 | [diff] [blame] | 80 | case HRcVec128: |
sewardj | d08f2d7 | 2004-12-01 23:19:36 +0000 | [diff] [blame] | 81 | r = hregNumber(reg); |
| 82 | vassert(r >= 0 && r < 8); |
| 83 | vex_printf("%%xmm%d", r); |
| 84 | return; |
| 85 | default: |
sewardj | 35421a3 | 2004-07-05 13:12:34 +0000 | [diff] [blame] | 86 | vpanic("ppHRegX86"); |
sewardj | c97096c | 2004-06-30 09:28:04 +0000 | [diff] [blame] | 87 | } |
| 88 | } |
| 89 | |
sewardj | 4a31b26 | 2004-12-01 02:24:44 +0000 | [diff] [blame] | 90 | HReg hregX86_EAX ( void ) { return mkHReg(0, HRcInt32, False); } |
| 91 | HReg hregX86_ECX ( void ) { return mkHReg(1, HRcInt32, False); } |
| 92 | HReg hregX86_EDX ( void ) { return mkHReg(2, HRcInt32, False); } |
| 93 | HReg hregX86_EBX ( void ) { return mkHReg(3, HRcInt32, False); } |
| 94 | HReg hregX86_ESP ( void ) { return mkHReg(4, HRcInt32, False); } |
| 95 | HReg hregX86_EBP ( void ) { return mkHReg(5, HRcInt32, False); } |
| 96 | HReg hregX86_ESI ( void ) { return mkHReg(6, HRcInt32, False); } |
| 97 | HReg hregX86_EDI ( void ) { return mkHReg(7, HRcInt32, False); } |
sewardj | f13a16a | 2004-07-05 17:10:14 +0000 | [diff] [blame] | 98 | |
sewardj | 4a31b26 | 2004-12-01 02:24:44 +0000 | [diff] [blame] | 99 | HReg hregX86_FAKE0 ( void ) { return mkHReg(0, HRcFlt64, False); } |
| 100 | HReg hregX86_FAKE1 ( void ) { return mkHReg(1, HRcFlt64, False); } |
| 101 | HReg hregX86_FAKE2 ( void ) { return mkHReg(2, HRcFlt64, False); } |
| 102 | HReg hregX86_FAKE3 ( void ) { return mkHReg(3, HRcFlt64, False); } |
| 103 | HReg hregX86_FAKE4 ( void ) { return mkHReg(4, HRcFlt64, False); } |
| 104 | HReg hregX86_FAKE5 ( void ) { return mkHReg(5, HRcFlt64, False); } |
sewardj | d1725d1 | 2004-08-12 20:46:53 +0000 | [diff] [blame] | 105 | |
sewardj | d08f2d7 | 2004-12-01 23:19:36 +0000 | [diff] [blame] | 106 | HReg hregX86_XMM0 ( void ) { return mkHReg(0, HRcVec128, False); } |
| 107 | HReg hregX86_XMM1 ( void ) { return mkHReg(1, HRcVec128, False); } |
| 108 | HReg hregX86_XMM2 ( void ) { return mkHReg(2, HRcVec128, False); } |
| 109 | HReg hregX86_XMM3 ( void ) { return mkHReg(3, HRcVec128, False); } |
| 110 | HReg hregX86_XMM4 ( void ) { return mkHReg(4, HRcVec128, False); } |
| 111 | HReg hregX86_XMM5 ( void ) { return mkHReg(5, HRcVec128, False); } |
| 112 | HReg hregX86_XMM6 ( void ) { return mkHReg(6, HRcVec128, False); } |
| 113 | HReg hregX86_XMM7 ( void ) { return mkHReg(7, HRcVec128, False); } |
| 114 | |
| 115 | |
sewardj | f13a16a | 2004-07-05 17:10:14 +0000 | [diff] [blame] | 116 | void getAllocableRegs_X86 ( Int* nregs, HReg** arr ) |
| 117 | { |
sewardj | d08f2d7 | 2004-12-01 23:19:36 +0000 | [diff] [blame] | 118 | *nregs = 20; |
sewardj | f13a16a | 2004-07-05 17:10:14 +0000 | [diff] [blame] | 119 | *arr = LibVEX_Alloc(*nregs * sizeof(HReg)); |
sewardj | 0a5f5c8 | 2004-07-07 11:56:35 +0000 | [diff] [blame] | 120 | (*arr)[0] = hregX86_EAX(); |
| 121 | (*arr)[1] = hregX86_EBX(); |
| 122 | (*arr)[2] = hregX86_ECX(); |
| 123 | (*arr)[3] = hregX86_EDX(); |
| 124 | (*arr)[4] = hregX86_ESI(); |
| 125 | (*arr)[5] = hregX86_EDI(); |
sewardj | d1725d1 | 2004-08-12 20:46:53 +0000 | [diff] [blame] | 126 | (*arr)[6] = hregX86_FAKE0(); |
| 127 | (*arr)[7] = hregX86_FAKE1(); |
| 128 | (*arr)[8] = hregX86_FAKE2(); |
| 129 | (*arr)[9] = hregX86_FAKE3(); |
sewardj | eafde5a | 2004-10-09 01:36:57 +0000 | [diff] [blame] | 130 | (*arr)[10] = hregX86_FAKE4(); |
| 131 | (*arr)[11] = hregX86_FAKE5(); |
sewardj | d08f2d7 | 2004-12-01 23:19:36 +0000 | [diff] [blame] | 132 | (*arr)[12] = hregX86_XMM0(); |
| 133 | (*arr)[13] = hregX86_XMM1(); |
| 134 | (*arr)[14] = hregX86_XMM2(); |
| 135 | (*arr)[15] = hregX86_XMM3(); |
| 136 | (*arr)[16] = hregX86_XMM4(); |
| 137 | (*arr)[17] = hregX86_XMM5(); |
| 138 | (*arr)[18] = hregX86_XMM6(); |
| 139 | (*arr)[19] = hregX86_XMM7(); |
sewardj | f13a16a | 2004-07-05 17:10:14 +0000 | [diff] [blame] | 140 | } |
sewardj | 53f85a9 | 2004-07-02 13:45:17 +0000 | [diff] [blame] | 141 | |
sewardj | c97096c | 2004-06-30 09:28:04 +0000 | [diff] [blame] | 142 | |
sewardj | 443cd9d | 2004-07-18 23:06:45 +0000 | [diff] [blame] | 143 | /* --------- Condition codes, Intel encoding. --------- */ |
| 144 | |
sewardj | 810dcf0 | 2004-11-22 12:55:45 +0000 | [diff] [blame] | 145 | HChar* showX86CondCode ( X86CondCode cond ) |
sewardj | 443cd9d | 2004-07-18 23:06:45 +0000 | [diff] [blame] | 146 | { |
| 147 | switch (cond) { |
sewardj | 60f4e3c | 2004-07-19 01:56:50 +0000 | [diff] [blame] | 148 | case Xcc_O: return "o"; |
| 149 | case Xcc_NO: return "no"; |
| 150 | case Xcc_B: return "b"; |
| 151 | case Xcc_NB: return "nb"; |
| 152 | case Xcc_Z: return "z"; |
| 153 | case Xcc_NZ: return "nz"; |
| 154 | case Xcc_BE: return "be"; |
| 155 | case Xcc_NBE: return "nbe"; |
| 156 | case Xcc_S: return "s"; |
| 157 | case Xcc_NS: return "ns"; |
| 158 | case Xcc_P: return "p"; |
| 159 | case Xcc_NP: return "np"; |
| 160 | case Xcc_L: return "l"; |
| 161 | case Xcc_NL: return "nl"; |
| 162 | case Xcc_LE: return "le"; |
| 163 | case Xcc_NLE: return "nle"; |
| 164 | case Xcc_ALWAYS: return "ALWAYS"; |
sewardj | 443cd9d | 2004-07-18 23:06:45 +0000 | [diff] [blame] | 165 | default: vpanic("ppX86CondCode"); |
| 166 | } |
| 167 | } |
| 168 | |
| 169 | |
sewardj | c97096c | 2004-06-30 09:28:04 +0000 | [diff] [blame] | 170 | /* --------- X86AMode: memory address expressions. --------- */ |
| 171 | |
| 172 | X86AMode* X86AMode_IR ( UInt imm32, HReg reg ) { |
sewardj | 35421a3 | 2004-07-05 13:12:34 +0000 | [diff] [blame] | 173 | X86AMode* am = LibVEX_Alloc(sizeof(X86AMode)); |
sewardj | c97096c | 2004-06-30 09:28:04 +0000 | [diff] [blame] | 174 | am->tag = Xam_IR; |
| 175 | am->Xam.IR.imm = imm32; |
| 176 | am->Xam.IR.reg = reg; |
| 177 | return am; |
| 178 | } |
sewardj | 0e63b52 | 2004-08-25 13:24:44 +0000 | [diff] [blame] | 179 | X86AMode* X86AMode_IRRS ( UInt imm32, HReg base, HReg indEx, Int shift ) { |
sewardj | 35421a3 | 2004-07-05 13:12:34 +0000 | [diff] [blame] | 180 | X86AMode* am = LibVEX_Alloc(sizeof(X86AMode)); |
sewardj | c97096c | 2004-06-30 09:28:04 +0000 | [diff] [blame] | 181 | am->tag = Xam_IRRS; |
| 182 | am->Xam.IRRS.imm = imm32; |
| 183 | am->Xam.IRRS.base = base; |
sewardj | 0e63b52 | 2004-08-25 13:24:44 +0000 | [diff] [blame] | 184 | am->Xam.IRRS.index = indEx; |
sewardj | c97096c | 2004-06-30 09:28:04 +0000 | [diff] [blame] | 185 | am->Xam.IRRS.shift = shift; |
sewardj | 35421a3 | 2004-07-05 13:12:34 +0000 | [diff] [blame] | 186 | vassert(shift >= 0 && shift <= 3); |
sewardj | c97096c | 2004-06-30 09:28:04 +0000 | [diff] [blame] | 187 | return am; |
| 188 | } |
| 189 | |
sewardj | 218e29f | 2004-11-07 18:45:15 +0000 | [diff] [blame] | 190 | X86AMode* dopyX86AMode ( X86AMode* am ) { |
| 191 | switch (am->tag) { |
| 192 | case Xam_IR: |
| 193 | return X86AMode_IR( am->Xam.IR.imm, am->Xam.IR.reg ); |
| 194 | case Xam_IRRS: |
| 195 | return X86AMode_IRRS( am->Xam.IRRS.imm, am->Xam.IRRS.base, |
| 196 | am->Xam.IRRS.index, am->Xam.IRRS.shift ); |
| 197 | default: |
| 198 | vpanic("dopyX86AMode"); |
| 199 | } |
| 200 | } |
| 201 | |
sewardj | 35421a3 | 2004-07-05 13:12:34 +0000 | [diff] [blame] | 202 | void ppX86AMode ( X86AMode* am ) { |
sewardj | c97096c | 2004-06-30 09:28:04 +0000 | [diff] [blame] | 203 | switch (am->tag) { |
| 204 | case Xam_IR: |
sewardj | ea64e14 | 2004-07-22 16:47:21 +0000 | [diff] [blame] | 205 | if (am->Xam.IR.imm == 0) |
| 206 | vex_printf("("); |
| 207 | else |
| 208 | vex_printf("0x%x(", am->Xam.IR.imm); |
sewardj | 35421a3 | 2004-07-05 13:12:34 +0000 | [diff] [blame] | 209 | ppHRegX86(am->Xam.IR.reg); |
| 210 | vex_printf(")"); |
sewardj | c97096c | 2004-06-30 09:28:04 +0000 | [diff] [blame] | 211 | return; |
| 212 | case Xam_IRRS: |
sewardj | 35421a3 | 2004-07-05 13:12:34 +0000 | [diff] [blame] | 213 | vex_printf("0x%x(", am->Xam.IRRS.imm); |
| 214 | ppHRegX86(am->Xam.IRRS.base); |
| 215 | vex_printf(","); |
| 216 | ppHRegX86(am->Xam.IRRS.index); |
sewardj | ea64e14 | 2004-07-22 16:47:21 +0000 | [diff] [blame] | 217 | vex_printf(",%d)", 1 << am->Xam.IRRS.shift); |
sewardj | c97096c | 2004-06-30 09:28:04 +0000 | [diff] [blame] | 218 | return; |
| 219 | default: |
sewardj | 35421a3 | 2004-07-05 13:12:34 +0000 | [diff] [blame] | 220 | vpanic("ppX86AMode"); |
sewardj | c97096c | 2004-06-30 09:28:04 +0000 | [diff] [blame] | 221 | } |
| 222 | } |
| 223 | |
sewardj | 53f85a9 | 2004-07-02 13:45:17 +0000 | [diff] [blame] | 224 | static void addRegUsage_X86AMode ( HRegUsage* u, X86AMode* am ) { |
| 225 | switch (am->tag) { |
| 226 | case Xam_IR: |
| 227 | addHRegUse(u, HRmRead, am->Xam.IR.reg); |
| 228 | return; |
| 229 | case Xam_IRRS: |
| 230 | addHRegUse(u, HRmRead, am->Xam.IRRS.base); |
| 231 | addHRegUse(u, HRmRead, am->Xam.IRRS.index); |
| 232 | return; |
| 233 | default: |
sewardj | 35421a3 | 2004-07-05 13:12:34 +0000 | [diff] [blame] | 234 | vpanic("addRegUsage_X86AMode"); |
sewardj | 53f85a9 | 2004-07-02 13:45:17 +0000 | [diff] [blame] | 235 | } |
| 236 | } |
| 237 | |
| 238 | static void mapRegs_X86AMode ( HRegRemap* m, X86AMode* am ) { |
| 239 | switch (am->tag) { |
| 240 | case Xam_IR: |
| 241 | am->Xam.IR.reg = lookupHRegRemap(m, am->Xam.IR.reg); |
| 242 | return; |
| 243 | case Xam_IRRS: |
| 244 | am->Xam.IRRS.base = lookupHRegRemap(m, am->Xam.IRRS.base); |
| 245 | am->Xam.IRRS.index = lookupHRegRemap(m, am->Xam.IRRS.index); |
| 246 | return; |
| 247 | default: |
sewardj | 35421a3 | 2004-07-05 13:12:34 +0000 | [diff] [blame] | 248 | vpanic("mapRegs_X86AMode"); |
sewardj | 53f85a9 | 2004-07-02 13:45:17 +0000 | [diff] [blame] | 249 | } |
| 250 | } |
sewardj | c97096c | 2004-06-30 09:28:04 +0000 | [diff] [blame] | 251 | |
sewardj | 66f2f79 | 2004-06-30 16:37:16 +0000 | [diff] [blame] | 252 | /* --------- Operand, which can be reg, immediate or memory. --------- */ |
sewardj | c97096c | 2004-06-30 09:28:04 +0000 | [diff] [blame] | 253 | |
sewardj | 66f2f79 | 2004-06-30 16:37:16 +0000 | [diff] [blame] | 254 | X86RMI* X86RMI_Imm ( UInt imm32 ) { |
sewardj | 35421a3 | 2004-07-05 13:12:34 +0000 | [diff] [blame] | 255 | X86RMI* op = LibVEX_Alloc(sizeof(X86RMI)); |
sewardj | 66f2f79 | 2004-06-30 16:37:16 +0000 | [diff] [blame] | 256 | op->tag = Xrmi_Imm; |
| 257 | op->Xrmi.Imm.imm32 = imm32; |
sewardj | c97096c | 2004-06-30 09:28:04 +0000 | [diff] [blame] | 258 | return op; |
| 259 | } |
sewardj | 66f2f79 | 2004-06-30 16:37:16 +0000 | [diff] [blame] | 260 | X86RMI* X86RMI_Reg ( HReg reg ) { |
sewardj | 35421a3 | 2004-07-05 13:12:34 +0000 | [diff] [blame] | 261 | X86RMI* op = LibVEX_Alloc(sizeof(X86RMI)); |
sewardj | 66f2f79 | 2004-06-30 16:37:16 +0000 | [diff] [blame] | 262 | op->tag = Xrmi_Reg; |
| 263 | op->Xrmi.Reg.reg = reg; |
sewardj | c97096c | 2004-06-30 09:28:04 +0000 | [diff] [blame] | 264 | return op; |
| 265 | } |
sewardj | 66f2f79 | 2004-06-30 16:37:16 +0000 | [diff] [blame] | 266 | X86RMI* X86RMI_Mem ( X86AMode* am ) { |
sewardj | 35421a3 | 2004-07-05 13:12:34 +0000 | [diff] [blame] | 267 | X86RMI* op = LibVEX_Alloc(sizeof(X86RMI)); |
sewardj | 66f2f79 | 2004-06-30 16:37:16 +0000 | [diff] [blame] | 268 | op->tag = Xrmi_Mem; |
| 269 | op->Xrmi.Mem.am = am; |
sewardj | c97096c | 2004-06-30 09:28:04 +0000 | [diff] [blame] | 270 | return op; |
| 271 | } |
| 272 | |
sewardj | 35421a3 | 2004-07-05 13:12:34 +0000 | [diff] [blame] | 273 | void ppX86RMI ( X86RMI* op ) { |
sewardj | c97096c | 2004-06-30 09:28:04 +0000 | [diff] [blame] | 274 | switch (op->tag) { |
sewardj | 66f2f79 | 2004-06-30 16:37:16 +0000 | [diff] [blame] | 275 | case Xrmi_Imm: |
sewardj | 35421a3 | 2004-07-05 13:12:34 +0000 | [diff] [blame] | 276 | vex_printf("$0x%x", op->Xrmi.Imm.imm32); |
sewardj | c97096c | 2004-06-30 09:28:04 +0000 | [diff] [blame] | 277 | return; |
sewardj | 66f2f79 | 2004-06-30 16:37:16 +0000 | [diff] [blame] | 278 | case Xrmi_Reg: |
sewardj | 35421a3 | 2004-07-05 13:12:34 +0000 | [diff] [blame] | 279 | ppHRegX86(op->Xrmi.Reg.reg); |
sewardj | c97096c | 2004-06-30 09:28:04 +0000 | [diff] [blame] | 280 | return; |
sewardj | 66f2f79 | 2004-06-30 16:37:16 +0000 | [diff] [blame] | 281 | case Xrmi_Mem: |
sewardj | 35421a3 | 2004-07-05 13:12:34 +0000 | [diff] [blame] | 282 | ppX86AMode(op->Xrmi.Mem.am); |
sewardj | c97096c | 2004-06-30 09:28:04 +0000 | [diff] [blame] | 283 | return; |
| 284 | default: |
sewardj | 35421a3 | 2004-07-05 13:12:34 +0000 | [diff] [blame] | 285 | vpanic("ppX86RMI"); |
sewardj | 66f2f79 | 2004-06-30 16:37:16 +0000 | [diff] [blame] | 286 | } |
| 287 | } |
| 288 | |
sewardj | 53f85a9 | 2004-07-02 13:45:17 +0000 | [diff] [blame] | 289 | /* An X86RMI can only be used in a "read" context (what would it mean |
| 290 | to write or modify a literal?) and so we enumerate its registers |
| 291 | accordingly. */ |
| 292 | static void addRegUsage_X86RMI ( HRegUsage* u, X86RMI* op ) { |
| 293 | switch (op->tag) { |
| 294 | case Xrmi_Imm: |
| 295 | return; |
| 296 | case Xrmi_Reg: |
| 297 | addHRegUse(u, HRmRead, op->Xrmi.Reg.reg); |
| 298 | return; |
| 299 | case Xrmi_Mem: |
| 300 | addRegUsage_X86AMode(u, op->Xrmi.Mem.am); |
| 301 | return; |
| 302 | default: |
sewardj | 35421a3 | 2004-07-05 13:12:34 +0000 | [diff] [blame] | 303 | vpanic("addRegUsage_X86RMI"); |
sewardj | 53f85a9 | 2004-07-02 13:45:17 +0000 | [diff] [blame] | 304 | } |
| 305 | } |
| 306 | |
| 307 | static void mapRegs_X86RMI ( HRegRemap* m, X86RMI* op ) { |
| 308 | switch (op->tag) { |
| 309 | case Xrmi_Imm: |
| 310 | return; |
| 311 | case Xrmi_Reg: |
| 312 | op->Xrmi.Reg.reg = lookupHRegRemap(m, op->Xrmi.Reg.reg); |
| 313 | return; |
| 314 | case Xrmi_Mem: |
| 315 | mapRegs_X86AMode(m, op->Xrmi.Mem.am); |
| 316 | return; |
| 317 | default: |
sewardj | 35421a3 | 2004-07-05 13:12:34 +0000 | [diff] [blame] | 318 | vpanic("mapRegs_X86RMI"); |
sewardj | 53f85a9 | 2004-07-02 13:45:17 +0000 | [diff] [blame] | 319 | } |
| 320 | } |
| 321 | |
sewardj | 66f2f79 | 2004-06-30 16:37:16 +0000 | [diff] [blame] | 322 | |
| 323 | /* --------- Operand, which can be reg or immediate only. --------- */ |
| 324 | |
| 325 | X86RI* X86RI_Imm ( UInt imm32 ) { |
sewardj | 35421a3 | 2004-07-05 13:12:34 +0000 | [diff] [blame] | 326 | X86RI* op = LibVEX_Alloc(sizeof(X86RI)); |
sewardj | 66f2f79 | 2004-06-30 16:37:16 +0000 | [diff] [blame] | 327 | op->tag = Xri_Imm; |
| 328 | op->Xri.Imm.imm32 = imm32; |
| 329 | return op; |
| 330 | } |
sewardj | 66f2f79 | 2004-06-30 16:37:16 +0000 | [diff] [blame] | 331 | X86RI* X86RI_Reg ( HReg reg ) { |
sewardj | 35421a3 | 2004-07-05 13:12:34 +0000 | [diff] [blame] | 332 | X86RI* op = LibVEX_Alloc(sizeof(X86RI)); |
sewardj | 66f2f79 | 2004-06-30 16:37:16 +0000 | [diff] [blame] | 333 | op->tag = Xri_Reg; |
| 334 | op->Xri.Reg.reg = reg; |
| 335 | return op; |
| 336 | } |
| 337 | |
sewardj | 35421a3 | 2004-07-05 13:12:34 +0000 | [diff] [blame] | 338 | void ppX86RI ( X86RI* op ) { |
sewardj | 66f2f79 | 2004-06-30 16:37:16 +0000 | [diff] [blame] | 339 | switch (op->tag) { |
| 340 | case Xri_Imm: |
sewardj | 35421a3 | 2004-07-05 13:12:34 +0000 | [diff] [blame] | 341 | vex_printf("$0x%x", op->Xri.Imm.imm32); |
sewardj | 66f2f79 | 2004-06-30 16:37:16 +0000 | [diff] [blame] | 342 | return; |
| 343 | case Xri_Reg: |
sewardj | 35421a3 | 2004-07-05 13:12:34 +0000 | [diff] [blame] | 344 | ppHRegX86(op->Xri.Reg.reg); |
sewardj | 66f2f79 | 2004-06-30 16:37:16 +0000 | [diff] [blame] | 345 | return; |
| 346 | default: |
sewardj | 35421a3 | 2004-07-05 13:12:34 +0000 | [diff] [blame] | 347 | vpanic("ppX86RI"); |
sewardj | 66f2f79 | 2004-06-30 16:37:16 +0000 | [diff] [blame] | 348 | } |
| 349 | } |
| 350 | |
sewardj | 53f85a9 | 2004-07-02 13:45:17 +0000 | [diff] [blame] | 351 | /* An X86RI can only be used in a "read" context (what would it mean |
| 352 | to write or modify a literal?) and so we enumerate its registers |
| 353 | accordingly. */ |
| 354 | static void addRegUsage_X86RI ( HRegUsage* u, X86RI* op ) { |
| 355 | switch (op->tag) { |
| 356 | case Xri_Imm: |
| 357 | return; |
| 358 | case Xri_Reg: |
| 359 | addHRegUse(u, HRmRead, op->Xri.Reg.reg); |
| 360 | return; |
| 361 | default: |
sewardj | 35421a3 | 2004-07-05 13:12:34 +0000 | [diff] [blame] | 362 | vpanic("addRegUsage_X86RI"); |
sewardj | 53f85a9 | 2004-07-02 13:45:17 +0000 | [diff] [blame] | 363 | } |
| 364 | } |
| 365 | |
| 366 | static void mapRegs_X86RI ( HRegRemap* m, X86RI* op ) { |
| 367 | switch (op->tag) { |
| 368 | case Xri_Imm: |
| 369 | return; |
| 370 | case Xri_Reg: |
| 371 | op->Xri.Reg.reg = lookupHRegRemap(m, op->Xri.Reg.reg); |
| 372 | return; |
| 373 | default: |
sewardj | 35421a3 | 2004-07-05 13:12:34 +0000 | [diff] [blame] | 374 | vpanic("mapRegs_X86RI"); |
sewardj | 53f85a9 | 2004-07-02 13:45:17 +0000 | [diff] [blame] | 375 | } |
| 376 | } |
| 377 | |
sewardj | 66f2f79 | 2004-06-30 16:37:16 +0000 | [diff] [blame] | 378 | |
| 379 | /* --------- Operand, which can be reg or memory only. --------- */ |
| 380 | |
| 381 | X86RM* X86RM_Reg ( HReg reg ) { |
sewardj | 35421a3 | 2004-07-05 13:12:34 +0000 | [diff] [blame] | 382 | X86RM* op = LibVEX_Alloc(sizeof(X86RM)); |
sewardj | 66f2f79 | 2004-06-30 16:37:16 +0000 | [diff] [blame] | 383 | op->tag = Xrm_Reg; |
| 384 | op->Xrm.Reg.reg = reg; |
| 385 | return op; |
| 386 | } |
sewardj | 66f2f79 | 2004-06-30 16:37:16 +0000 | [diff] [blame] | 387 | X86RM* X86RM_Mem ( X86AMode* am ) { |
sewardj | 35421a3 | 2004-07-05 13:12:34 +0000 | [diff] [blame] | 388 | X86RM* op = LibVEX_Alloc(sizeof(X86RM)); |
sewardj | 66f2f79 | 2004-06-30 16:37:16 +0000 | [diff] [blame] | 389 | op->tag = Xrm_Mem; |
| 390 | op->Xrm.Mem.am = am; |
| 391 | return op; |
| 392 | } |
| 393 | |
sewardj | 35421a3 | 2004-07-05 13:12:34 +0000 | [diff] [blame] | 394 | void ppX86RM ( X86RM* op ) { |
sewardj | 66f2f79 | 2004-06-30 16:37:16 +0000 | [diff] [blame] | 395 | switch (op->tag) { |
| 396 | case Xrm_Mem: |
sewardj | 35421a3 | 2004-07-05 13:12:34 +0000 | [diff] [blame] | 397 | ppX86AMode(op->Xrm.Mem.am); |
sewardj | 66f2f79 | 2004-06-30 16:37:16 +0000 | [diff] [blame] | 398 | return; |
| 399 | case Xrm_Reg: |
sewardj | 35421a3 | 2004-07-05 13:12:34 +0000 | [diff] [blame] | 400 | ppHRegX86(op->Xrm.Reg.reg); |
sewardj | 66f2f79 | 2004-06-30 16:37:16 +0000 | [diff] [blame] | 401 | return; |
| 402 | default: |
sewardj | 35421a3 | 2004-07-05 13:12:34 +0000 | [diff] [blame] | 403 | vpanic("ppX86RM"); |
sewardj | c97096c | 2004-06-30 09:28:04 +0000 | [diff] [blame] | 404 | } |
| 405 | } |
| 406 | |
sewardj | 53f85a9 | 2004-07-02 13:45:17 +0000 | [diff] [blame] | 407 | /* Because an X86RM can be both a source or destination operand, we |
| 408 | have to supply a mode -- pertaining to the operand as a whole -- |
| 409 | indicating how it's being used. */ |
| 410 | static void addRegUsage_X86RM ( HRegUsage* u, X86RM* op, HRegMode mode ) { |
| 411 | switch (op->tag) { |
| 412 | case Xrm_Mem: |
| 413 | /* Memory is read, written or modified. So we just want to |
| 414 | know the regs read by the amode. */ |
| 415 | addRegUsage_X86AMode(u, op->Xrm.Mem.am); |
| 416 | return; |
| 417 | case Xrm_Reg: |
| 418 | /* reg is read, written or modified. Add it in the |
| 419 | appropriate way. */ |
| 420 | addHRegUse(u, mode, op->Xrm.Reg.reg); |
| 421 | return; |
| 422 | default: |
sewardj | 35421a3 | 2004-07-05 13:12:34 +0000 | [diff] [blame] | 423 | vpanic("addRegUsage_X86RM"); |
sewardj | 53f85a9 | 2004-07-02 13:45:17 +0000 | [diff] [blame] | 424 | } |
| 425 | } |
| 426 | |
| 427 | static void mapRegs_X86RM ( HRegRemap* m, X86RM* op ) |
| 428 | { |
| 429 | switch (op->tag) { |
| 430 | case Xrm_Mem: |
| 431 | mapRegs_X86AMode(m, op->Xrm.Mem.am); |
| 432 | return; |
| 433 | case Xrm_Reg: |
| 434 | op->Xrm.Reg.reg = lookupHRegRemap(m, op->Xrm.Reg.reg); |
| 435 | return; |
| 436 | default: |
sewardj | 35421a3 | 2004-07-05 13:12:34 +0000 | [diff] [blame] | 437 | vpanic("mapRegs_X86RM"); |
sewardj | 53f85a9 | 2004-07-02 13:45:17 +0000 | [diff] [blame] | 438 | } |
| 439 | } |
| 440 | |
sewardj | c97096c | 2004-06-30 09:28:04 +0000 | [diff] [blame] | 441 | |
| 442 | /* --------- Instructions. --------- */ |
| 443 | |
sewardj | d08f2d7 | 2004-12-01 23:19:36 +0000 | [diff] [blame] | 444 | HChar* showX86UnaryOp ( X86UnaryOp op ) { |
sewardj | 66f2f79 | 2004-06-30 16:37:16 +0000 | [diff] [blame] | 445 | switch (op) { |
sewardj | 358b7d4 | 2004-11-08 18:54:50 +0000 | [diff] [blame] | 446 | case Xun_NOT: return "not"; |
| 447 | case Xun_NEG: return "neg"; |
sewardj | cfded9a | 2004-09-09 11:44:16 +0000 | [diff] [blame] | 448 | default: vpanic("showX86UnaryOp"); |
sewardj | 60f4e3c | 2004-07-19 01:56:50 +0000 | [diff] [blame] | 449 | } |
| 450 | } |
| 451 | |
sewardj | d08f2d7 | 2004-12-01 23:19:36 +0000 | [diff] [blame] | 452 | HChar* showX86AluOp ( X86AluOp op ) { |
sewardj | 60f4e3c | 2004-07-19 01:56:50 +0000 | [diff] [blame] | 453 | switch (op) { |
| 454 | case Xalu_MOV: return "mov"; |
| 455 | case Xalu_CMP: return "cmp"; |
sewardj | 60f4e3c | 2004-07-19 01:56:50 +0000 | [diff] [blame] | 456 | case Xalu_ADD: return "add"; |
| 457 | case Xalu_SUB: return "sub"; |
| 458 | case Xalu_ADC: return "adc"; |
| 459 | case Xalu_SBB: return "sbb"; |
| 460 | case Xalu_AND: return "and"; |
| 461 | case Xalu_OR: return "or"; |
| 462 | case Xalu_XOR: return "xor"; |
| 463 | case Xalu_MUL: return "mul"; |
sewardj | cfded9a | 2004-09-09 11:44:16 +0000 | [diff] [blame] | 464 | default: vpanic("showX86AluOp"); |
sewardj | 60f4e3c | 2004-07-19 01:56:50 +0000 | [diff] [blame] | 465 | } |
| 466 | } |
| 467 | |
sewardj | d08f2d7 | 2004-12-01 23:19:36 +0000 | [diff] [blame] | 468 | HChar* showX86ShiftOp ( X86ShiftOp op ) { |
sewardj | 60f4e3c | 2004-07-19 01:56:50 +0000 | [diff] [blame] | 469 | switch (op) { |
| 470 | case Xsh_SHL: return "shl"; |
| 471 | case Xsh_SHR: return "shr"; |
| 472 | case Xsh_SAR: return "sar"; |
sewardj | cfded9a | 2004-09-09 11:44:16 +0000 | [diff] [blame] | 473 | default: vpanic("showX86ShiftOp"); |
sewardj | 66f2f79 | 2004-06-30 16:37:16 +0000 | [diff] [blame] | 474 | } |
sewardj | 66f2f79 | 2004-06-30 16:37:16 +0000 | [diff] [blame] | 475 | } |
| 476 | |
sewardj | d08f2d7 | 2004-12-01 23:19:36 +0000 | [diff] [blame] | 477 | HChar* showX86FpOp ( X86FpOp op ) { |
sewardj | d1725d1 | 2004-08-12 20:46:53 +0000 | [diff] [blame] | 478 | switch (op) { |
sewardj | bb53f8c | 2004-08-14 11:50:01 +0000 | [diff] [blame] | 479 | case Xfp_ADD: return "add"; |
| 480 | case Xfp_SUB: return "sub"; |
| 481 | case Xfp_MUL: return "mul"; |
| 482 | case Xfp_DIV: return "div"; |
sewardj | 8d38778 | 2004-11-11 02:15:15 +0000 | [diff] [blame] | 483 | case Xfp_SCALE: return "scale"; |
| 484 | case Xfp_ATAN: return "atan"; |
| 485 | case Xfp_YL2X: return "yl2x"; |
| 486 | case Xfp_YL2XP1: return "yl2xp1"; |
| 487 | case Xfp_PREM: return "prem"; |
| 488 | case Xfp_PREM1: return "prem1"; |
sewardj | bb53f8c | 2004-08-14 11:50:01 +0000 | [diff] [blame] | 489 | case Xfp_SQRT: return "sqrt"; |
sewardj | 883b00b | 2004-09-11 09:30:24 +0000 | [diff] [blame] | 490 | case Xfp_ABS: return "abs"; |
sewardj | 8d38778 | 2004-11-11 02:15:15 +0000 | [diff] [blame] | 491 | case Xfp_NEG: return "chs"; |
sewardj | bb53f8c | 2004-08-14 11:50:01 +0000 | [diff] [blame] | 492 | case Xfp_MOV: return "mov"; |
sewardj | cfded9a | 2004-09-09 11:44:16 +0000 | [diff] [blame] | 493 | case Xfp_SIN: return "sin"; |
| 494 | case Xfp_COS: return "cos"; |
sewardj | 99016a7 | 2004-10-15 22:09:17 +0000 | [diff] [blame] | 495 | case Xfp_TAN: return "tan"; |
sewardj | 8d38778 | 2004-11-11 02:15:15 +0000 | [diff] [blame] | 496 | case Xfp_ROUND: return "round"; |
sewardj | 06c32a0 | 2004-09-12 12:07:34 +0000 | [diff] [blame] | 497 | case Xfp_2XM1: return "2xm1"; |
sewardj | cfded9a | 2004-09-09 11:44:16 +0000 | [diff] [blame] | 498 | default: vpanic("showX86FpOp"); |
sewardj | d1725d1 | 2004-08-12 20:46:53 +0000 | [diff] [blame] | 499 | } |
| 500 | } |
| 501 | |
sewardj | d08f2d7 | 2004-12-01 23:19:36 +0000 | [diff] [blame] | 502 | HChar* showX86SseOp ( X86SseOp op ) { |
| 503 | switch (op) { |
sewardj | 164f927 | 2004-12-09 00:39:32 +0000 | [diff] [blame] | 504 | case Xsse_MOV: return "mov(?!)"; |
| 505 | case Xsse_ADDF: return "add"; |
| 506 | case Xsse_SUBF: return "sub"; |
| 507 | case Xsse_MULF: return "mul"; |
| 508 | case Xsse_DIVF: return "div"; |
| 509 | case Xsse_MAXF: return "max"; |
| 510 | case Xsse_MINF: return "min"; |
| 511 | case Xsse_CMPEQF: return "cmpFeq"; |
| 512 | case Xsse_CMPLTF: return "cmpFlt"; |
| 513 | case Xsse_CMPLEF: return "cmpFle"; |
| 514 | case Xsse_CMPUNF: return "cmpFun"; |
| 515 | case Xsse_RCPF: return "rcp"; |
| 516 | case Xsse_RSQRTF: return "rsqrt"; |
| 517 | case Xsse_SQRTF: return "sqrt"; |
| 518 | case Xsse_AND: return "and"; |
| 519 | case Xsse_OR: return "or"; |
| 520 | case Xsse_XOR: return "xor"; |
| 521 | case Xsse_ANDN: return "andn"; |
| 522 | case Xsse_ADD8: return "paddb"; |
| 523 | case Xsse_ADD16: return "paddw"; |
| 524 | case Xsse_ADD32: return "paddd"; |
| 525 | case Xsse_ADD64: return "paddq"; |
| 526 | case Xsse_QADD8U: return "paddusb"; |
| 527 | case Xsse_QADD16U: return "paddusw"; |
| 528 | case Xsse_QADD8S: return "paddsb"; |
| 529 | case Xsse_QADD16S: return "paddsw"; |
| 530 | case Xsse_SUB8: return "psubb"; |
| 531 | case Xsse_SUB16: return "psubw"; |
| 532 | case Xsse_SUB32: return "psubd"; |
| 533 | case Xsse_SUB64: return "psubq"; |
| 534 | case Xsse_QSUB8U: return "psubusb"; |
| 535 | case Xsse_QSUB16U: return "psubusw"; |
| 536 | case Xsse_QSUB8S: return "psubsb"; |
| 537 | case Xsse_QSUB16S: return "psubsw"; |
| 538 | case Xsse_MUL16: return "pmullw"; |
| 539 | case Xsse_MULHI16U: return "pmulhuw"; |
| 540 | case Xsse_MULHI16S: return "pmulhw"; |
| 541 | case Xsse_AVG8U: return "pavgb"; |
| 542 | case Xsse_AVG16U: return "pavgw"; |
| 543 | case Xsse_MAX16S: return "pmaxw"; |
| 544 | case Xsse_MAX8U: return "pmaxub"; |
| 545 | case Xsse_MIN16S: return "pminw"; |
| 546 | case Xsse_MIN8U: return "pminub"; |
| 547 | case Xsse_CMPEQ8: return "pcmpeqb"; |
| 548 | case Xsse_CMPEQ16: return "pcmpeqw"; |
| 549 | case Xsse_CMPEQ32: return "pcmpeqd"; |
| 550 | case Xsse_CMPGT8S: return "pcmpgtb"; |
| 551 | case Xsse_CMPGT16S: return "pcmpgtw"; |
| 552 | case Xsse_CMPGT32S: return "pcmpgtd"; |
| 553 | case Xsse_SHL16: return "psllw"; |
| 554 | case Xsse_SHL32: return "pslld"; |
| 555 | case Xsse_SHL64: return "psllq"; |
| 556 | case Xsse_SHR16: return "psrlw"; |
| 557 | case Xsse_SHR32: return "psrld"; |
| 558 | case Xsse_SHR64: return "psrlq"; |
| 559 | case Xsse_SAR16: return "psraw"; |
| 560 | case Xsse_SAR32: return "psrad"; |
| 561 | case Xsse_PACKSSD: return "packssdw"; |
| 562 | case Xsse_PACKSSW: return "packsswb"; |
| 563 | case Xsse_PACKUSW: return "packuswb"; |
sewardj | 9e20359 | 2004-12-10 01:48:18 +0000 | [diff] [blame] | 564 | case Xsse_UNPCKHB: return "punpckhb"; |
| 565 | case Xsse_UNPCKHW: return "punpckhw"; |
| 566 | case Xsse_UNPCKHD: return "punpckhd"; |
| 567 | case Xsse_UNPCKHQ: return "punpckhq"; |
| 568 | case Xsse_UNPCKLB: return "punpcklb"; |
| 569 | case Xsse_UNPCKLW: return "punpcklw"; |
| 570 | case Xsse_UNPCKLD: return "punpckld"; |
| 571 | case Xsse_UNPCKLQ: return "punpcklq"; |
sewardj | d08f2d7 | 2004-12-01 23:19:36 +0000 | [diff] [blame] | 572 | default: vpanic("showX86SseOp"); |
| 573 | } |
| 574 | } |
| 575 | |
sewardj | 66f2f79 | 2004-06-30 16:37:16 +0000 | [diff] [blame] | 576 | X86Instr* X86Instr_Alu32R ( X86AluOp op, X86RMI* src, HReg dst ) { |
sewardj | 35421a3 | 2004-07-05 13:12:34 +0000 | [diff] [blame] | 577 | X86Instr* i = LibVEX_Alloc(sizeof(X86Instr)); |
sewardj | 66f2f79 | 2004-06-30 16:37:16 +0000 | [diff] [blame] | 578 | i->tag = Xin_Alu32R; |
| 579 | i->Xin.Alu32R.op = op; |
| 580 | i->Xin.Alu32R.src = src; |
| 581 | i->Xin.Alu32R.dst = dst; |
| 582 | return i; |
| 583 | } |
sewardj | 66f2f79 | 2004-06-30 16:37:16 +0000 | [diff] [blame] | 584 | X86Instr* X86Instr_Alu32M ( X86AluOp op, X86RI* src, X86AMode* dst ) { |
sewardj | 35421a3 | 2004-07-05 13:12:34 +0000 | [diff] [blame] | 585 | X86Instr* i = LibVEX_Alloc(sizeof(X86Instr)); |
sewardj | 66f2f79 | 2004-06-30 16:37:16 +0000 | [diff] [blame] | 586 | i->tag = Xin_Alu32M; |
| 587 | i->Xin.Alu32M.op = op; |
| 588 | i->Xin.Alu32M.src = src; |
| 589 | i->Xin.Alu32M.dst = dst; |
sewardj | e8c922f | 2004-07-23 01:34:11 +0000 | [diff] [blame] | 590 | vassert(op != Xalu_MUL); |
| 591 | return i; |
| 592 | } |
sewardj | eba63f8 | 2005-02-23 13:31:25 +0000 | [diff] [blame] | 593 | X86Instr* X86Instr_Sh32 ( X86ShiftOp op, UInt src, HReg dst ) { |
sewardj | e8c922f | 2004-07-23 01:34:11 +0000 | [diff] [blame] | 594 | X86Instr* i = LibVEX_Alloc(sizeof(X86Instr)); |
| 595 | i->tag = Xin_Sh32; |
| 596 | i->Xin.Sh32.op = op; |
| 597 | i->Xin.Sh32.src = src; |
| 598 | i->Xin.Sh32.dst = dst; |
| 599 | return i; |
| 600 | } |
sewardj | eba63f8 | 2005-02-23 13:31:25 +0000 | [diff] [blame] | 601 | X86Instr* X86Instr_Test32 ( UInt imm32, HReg dst ) { |
| 602 | X86Instr* i = LibVEX_Alloc(sizeof(X86Instr)); |
| 603 | i->tag = Xin_Test32; |
| 604 | i->Xin.Test32.imm32 = imm32; |
| 605 | i->Xin.Test32.dst = dst; |
sewardj | 66f2f79 | 2004-06-30 16:37:16 +0000 | [diff] [blame] | 606 | return i; |
| 607 | } |
sewardj | eba63f8 | 2005-02-23 13:31:25 +0000 | [diff] [blame] | 608 | X86Instr* X86Instr_Unary32 ( X86UnaryOp op, HReg dst ) { |
sewardj | 60f4e3c | 2004-07-19 01:56:50 +0000 | [diff] [blame] | 609 | X86Instr* i = LibVEX_Alloc(sizeof(X86Instr)); |
| 610 | i->tag = Xin_Unary32; |
| 611 | i->Xin.Unary32.op = op; |
| 612 | i->Xin.Unary32.dst = dst; |
sewardj | 443cd9d | 2004-07-18 23:06:45 +0000 | [diff] [blame] | 613 | return i; |
| 614 | } |
sewardj | eba63f8 | 2005-02-23 13:31:25 +0000 | [diff] [blame] | 615 | X86Instr* X86Instr_MulL ( Bool syned, X86RM* src ) { |
sewardj | 597b71b | 2004-07-19 02:51:12 +0000 | [diff] [blame] | 616 | X86Instr* i = LibVEX_Alloc(sizeof(X86Instr)); |
| 617 | i->tag = Xin_MulL; |
| 618 | i->Xin.MulL.syned = syned; |
sewardj | 597b71b | 2004-07-19 02:51:12 +0000 | [diff] [blame] | 619 | i->Xin.MulL.src = src; |
| 620 | return i; |
| 621 | } |
sewardj | eba63f8 | 2005-02-23 13:31:25 +0000 | [diff] [blame] | 622 | X86Instr* X86Instr_Div ( Bool syned, X86RM* src ) { |
| 623 | X86Instr* i = LibVEX_Alloc(sizeof(X86Instr)); |
| 624 | i->tag = Xin_Div; |
| 625 | i->Xin.Div.syned = syned; |
| 626 | i->Xin.Div.src = src; |
sewardj | 5c34dc9 | 2004-07-19 12:48:11 +0000 | [diff] [blame] | 627 | return i; |
| 628 | } |
sewardj | e5f384c | 2004-07-30 16:17:28 +0000 | [diff] [blame] | 629 | X86Instr* X86Instr_Sh3232 ( X86ShiftOp op, UInt amt, HReg src, HReg dst ) { |
sewardj | 5c34dc9 | 2004-07-19 12:48:11 +0000 | [diff] [blame] | 630 | X86Instr* i = LibVEX_Alloc(sizeof(X86Instr)); |
| 631 | i->tag = Xin_Sh3232; |
| 632 | i->Xin.Sh3232.op = op; |
| 633 | i->Xin.Sh3232.amt = amt; |
sewardj | e5f384c | 2004-07-30 16:17:28 +0000 | [diff] [blame] | 634 | i->Xin.Sh3232.src = src; |
| 635 | i->Xin.Sh3232.dst = dst; |
sewardj | 5c34dc9 | 2004-07-19 12:48:11 +0000 | [diff] [blame] | 636 | vassert(op == Xsh_SHL || op == Xsh_SHR); |
| 637 | return i; |
| 638 | } |
sewardj | e8e9d73 | 2004-07-16 21:03:45 +0000 | [diff] [blame] | 639 | X86Instr* X86Instr_Push( X86RMI* src ) { |
sewardj | 35421a3 | 2004-07-05 13:12:34 +0000 | [diff] [blame] | 640 | X86Instr* i = LibVEX_Alloc(sizeof(X86Instr)); |
sewardj | e8e9d73 | 2004-07-16 21:03:45 +0000 | [diff] [blame] | 641 | i->tag = Xin_Push; |
| 642 | i->Xin.Push.src = src; |
| 643 | return i; |
| 644 | } |
sewardj | 4b861de | 2004-11-03 15:24:42 +0000 | [diff] [blame] | 645 | X86Instr* X86Instr_Call ( X86CondCode cond, Addr32 target, Int regparms ) { |
sewardj | 7735254 | 2004-10-30 20:39:01 +0000 | [diff] [blame] | 646 | X86Instr* i = LibVEX_Alloc(sizeof(X86Instr)); |
| 647 | i->tag = Xin_Call; |
sewardj | 4b861de | 2004-11-03 15:24:42 +0000 | [diff] [blame] | 648 | i->Xin.Call.cond = cond; |
sewardj | 7735254 | 2004-10-30 20:39:01 +0000 | [diff] [blame] | 649 | i->Xin.Call.target = target; |
| 650 | i->Xin.Call.regparms = regparms; |
| 651 | vassert(regparms >= 0 && regparms <= 3); |
sewardj | e8e9d73 | 2004-07-16 21:03:45 +0000 | [diff] [blame] | 652 | return i; |
| 653 | } |
sewardj | 750f407 | 2004-07-26 22:39:11 +0000 | [diff] [blame] | 654 | X86Instr* X86Instr_Goto ( IRJumpKind jk, X86CondCode cond, X86RI* dst ) { |
sewardj | 443cd9d | 2004-07-18 23:06:45 +0000 | [diff] [blame] | 655 | X86Instr* i = LibVEX_Alloc(sizeof(X86Instr)); |
| 656 | i->tag = Xin_Goto; |
| 657 | i->Xin.Goto.cond = cond; |
| 658 | i->Xin.Goto.dst = dst; |
sewardj | 750f407 | 2004-07-26 22:39:11 +0000 | [diff] [blame] | 659 | i->Xin.Goto.jk = jk; |
sewardj | c97096c | 2004-06-30 09:28:04 +0000 | [diff] [blame] | 660 | return i; |
| 661 | } |
sewardj | 5c34dc9 | 2004-07-19 12:48:11 +0000 | [diff] [blame] | 662 | X86Instr* X86Instr_CMov32 ( X86CondCode cond, X86RM* src, HReg dst ) { |
| 663 | X86Instr* i = LibVEX_Alloc(sizeof(X86Instr)); |
| 664 | i->tag = Xin_CMov32; |
| 665 | i->Xin.CMov32.cond = cond; |
| 666 | i->Xin.CMov32.src = src; |
| 667 | i->Xin.CMov32.dst = dst; |
| 668 | vassert(cond != Xcc_ALWAYS); |
sewardj | 4042c7e | 2004-07-18 01:28:30 +0000 | [diff] [blame] | 669 | return i; |
| 670 | } |
sewardj | 4042c7e | 2004-07-18 01:28:30 +0000 | [diff] [blame] | 671 | X86Instr* X86Instr_LoadEX ( UChar szSmall, Bool syned, |
| 672 | X86AMode* src, HReg dst ) { |
| 673 | X86Instr* i = LibVEX_Alloc(sizeof(X86Instr)); |
| 674 | i->tag = Xin_LoadEX; |
| 675 | i->Xin.LoadEX.szSmall = szSmall; |
| 676 | i->Xin.LoadEX.syned = syned; |
| 677 | i->Xin.LoadEX.src = src; |
| 678 | i->Xin.LoadEX.dst = dst; |
| 679 | vassert(szSmall == 1 || szSmall == 2); |
| 680 | return i; |
| 681 | } |
sewardj | d1725d1 | 2004-08-12 20:46:53 +0000 | [diff] [blame] | 682 | X86Instr* X86Instr_Store ( UChar sz, HReg src, X86AMode* dst ) { |
sewardj | 443cd9d | 2004-07-18 23:06:45 +0000 | [diff] [blame] | 683 | X86Instr* i = LibVEX_Alloc(sizeof(X86Instr)); |
| 684 | i->tag = Xin_Store; |
| 685 | i->Xin.Store.sz = sz; |
| 686 | i->Xin.Store.src = src; |
| 687 | i->Xin.Store.dst = dst; |
| 688 | vassert(sz == 1 || sz == 2); |
| 689 | return i; |
| 690 | } |
sewardj | d7cb853 | 2004-08-17 23:59:23 +0000 | [diff] [blame] | 691 | X86Instr* X86Instr_Set32 ( X86CondCode cond, HReg dst ) { |
| 692 | X86Instr* i = LibVEX_Alloc(sizeof(X86Instr)); |
| 693 | i->tag = Xin_Set32; |
| 694 | i->Xin.Set32.cond = cond; |
| 695 | i->Xin.Set32.dst = dst; |
| 696 | return i; |
| 697 | } |
sewardj | d08f2d7 | 2004-12-01 23:19:36 +0000 | [diff] [blame] | 698 | X86Instr* X86Instr_Bsfr32 ( Bool isFwds, HReg src, HReg dst ) { |
sewardj | ce646f2 | 2004-08-31 23:55:54 +0000 | [diff] [blame] | 699 | X86Instr* i = LibVEX_Alloc(sizeof(X86Instr)); |
| 700 | i->tag = Xin_Bsfr32; |
| 701 | i->Xin.Bsfr32.isFwds = isFwds; |
| 702 | i->Xin.Bsfr32.src = src; |
| 703 | i->Xin.Bsfr32.dst = dst; |
| 704 | return i; |
| 705 | } |
sewardj | 3e83893 | 2005-01-07 12:09:15 +0000 | [diff] [blame] | 706 | X86Instr* X86Instr_MFence ( VexSubArch subarch ) |
| 707 | { |
| 708 | X86Instr* i = LibVEX_Alloc(sizeof(X86Instr)); |
| 709 | i->tag = Xin_MFence; |
| 710 | i->Xin.MFence.subarch = subarch; |
| 711 | vassert(subarch == VexSubArchX86_sse0 |
| 712 | || subarch == VexSubArchX86_sse1 |
| 713 | || subarch == VexSubArchX86_sse2); |
| 714 | return i; |
| 715 | } |
| 716 | |
sewardj | d1725d1 | 2004-08-12 20:46:53 +0000 | [diff] [blame] | 717 | X86Instr* X86Instr_FpUnary ( X86FpOp op, HReg src, HReg dst ) { |
| 718 | X86Instr* i = LibVEX_Alloc(sizeof(X86Instr)); |
| 719 | i->tag = Xin_FpUnary; |
| 720 | i->Xin.FpUnary.op = op; |
| 721 | i->Xin.FpUnary.src = src; |
| 722 | i->Xin.FpUnary.dst = dst; |
| 723 | return i; |
| 724 | } |
| 725 | X86Instr* X86Instr_FpBinary ( X86FpOp op, HReg srcL, HReg srcR, HReg dst ) { |
| 726 | X86Instr* i = LibVEX_Alloc(sizeof(X86Instr)); |
| 727 | i->tag = Xin_FpBinary; |
| 728 | i->Xin.FpBinary.op = op; |
| 729 | i->Xin.FpBinary.srcL = srcL; |
| 730 | i->Xin.FpBinary.srcR = srcR; |
| 731 | i->Xin.FpBinary.dst = dst; |
| 732 | return i; |
| 733 | } |
| 734 | X86Instr* X86Instr_FpLdSt ( Bool isLoad, UChar sz, HReg reg, X86AMode* addr ) { |
| 735 | X86Instr* i = LibVEX_Alloc(sizeof(X86Instr)); |
| 736 | i->tag = Xin_FpLdSt; |
| 737 | i->Xin.FpLdSt.isLoad = isLoad; |
| 738 | i->Xin.FpLdSt.sz = sz; |
| 739 | i->Xin.FpLdSt.reg = reg; |
| 740 | i->Xin.FpLdSt.addr = addr; |
| 741 | vassert(sz == 4 || sz == 8); |
| 742 | return i; |
| 743 | } |
sewardj | d08f2d7 | 2004-12-01 23:19:36 +0000 | [diff] [blame] | 744 | X86Instr* X86Instr_FpLdStI ( Bool isLoad, UChar sz, |
| 745 | HReg reg, X86AMode* addr ) { |
sewardj | 89cd093 | 2004-09-08 18:23:25 +0000 | [diff] [blame] | 746 | X86Instr* i = LibVEX_Alloc(sizeof(X86Instr)); |
| 747 | i->tag = Xin_FpLdStI; |
| 748 | i->Xin.FpLdStI.isLoad = isLoad; |
| 749 | i->Xin.FpLdStI.sz = sz; |
| 750 | i->Xin.FpLdStI.reg = reg; |
| 751 | i->Xin.FpLdStI.addr = addr; |
| 752 | vassert(sz == 2 || sz == 4 || sz == 8); |
sewardj | d1725d1 | 2004-08-12 20:46:53 +0000 | [diff] [blame] | 753 | return i; |
| 754 | } |
sewardj | 3bca906 | 2004-12-04 14:36:09 +0000 | [diff] [blame] | 755 | X86Instr* X86Instr_Fp64to32 ( HReg src, HReg dst ) { |
| 756 | X86Instr* i = LibVEX_Alloc(sizeof(X86Instr)); |
| 757 | i->tag = Xin_Fp64to32; |
| 758 | i->Xin.Fp64to32.src = src; |
| 759 | i->Xin.Fp64to32.dst = dst; |
| 760 | return i; |
| 761 | } |
sewardj | 33124f6 | 2004-08-30 17:54:18 +0000 | [diff] [blame] | 762 | X86Instr* X86Instr_FpCMov ( X86CondCode cond, HReg src, HReg dst ) { |
| 763 | X86Instr* i = LibVEX_Alloc(sizeof(X86Instr)); |
| 764 | i->tag = Xin_FpCMov; |
| 765 | i->Xin.FpCMov.cond = cond; |
| 766 | i->Xin.FpCMov.src = src; |
| 767 | i->Xin.FpCMov.dst = dst; |
| 768 | vassert(cond != Xcc_ALWAYS); |
| 769 | return i; |
| 770 | } |
sewardj | eba63f8 | 2005-02-23 13:31:25 +0000 | [diff] [blame] | 771 | X86Instr* X86Instr_FpLdCW ( X86AMode* addr ) { |
| 772 | X86Instr* i = LibVEX_Alloc(sizeof(X86Instr)); |
| 773 | i->tag = Xin_FpLdCW; |
| 774 | i->Xin.FpLdCW.addr = addr; |
sewardj | 8f3debf | 2004-09-08 23:42:23 +0000 | [diff] [blame] | 775 | return i; |
| 776 | } |
sewardj | d08f2d7 | 2004-12-01 23:19:36 +0000 | [diff] [blame] | 777 | X86Instr* X86Instr_FpStSW_AX ( void ) { |
sewardj | 46de407 | 2004-09-11 19:23:24 +0000 | [diff] [blame] | 778 | X86Instr* i = LibVEX_Alloc(sizeof(X86Instr)); |
| 779 | i->tag = Xin_FpStSW_AX; |
| 780 | return i; |
| 781 | } |
sewardj | d08f2d7 | 2004-12-01 23:19:36 +0000 | [diff] [blame] | 782 | X86Instr* X86Instr_FpCmp ( HReg srcL, HReg srcR, HReg dst ) { |
sewardj | bdc7d21 | 2004-09-09 02:46:40 +0000 | [diff] [blame] | 783 | X86Instr* i = LibVEX_Alloc(sizeof(X86Instr)); |
| 784 | i->tag = Xin_FpCmp; |
| 785 | i->Xin.FpCmp.srcL = srcL; |
| 786 | i->Xin.FpCmp.srcR = srcR; |
| 787 | i->Xin.FpCmp.dst = dst; |
| 788 | return i; |
| 789 | } |
sewardj | 4042c7e | 2004-07-18 01:28:30 +0000 | [diff] [blame] | 790 | |
sewardj | 1e6ad74 | 2004-12-02 16:16:11 +0000 | [diff] [blame] | 791 | X86Instr* X86Instr_SseConst ( UShort con, HReg dst ) { |
| 792 | X86Instr* i = LibVEX_Alloc(sizeof(X86Instr)); |
| 793 | i->tag = Xin_SseConst; |
| 794 | i->Xin.SseConst.con = con; |
| 795 | i->Xin.SseConst.dst = dst; |
| 796 | vassert(hregClass(dst) == HRcVec128); |
| 797 | return i; |
| 798 | } |
sewardj | d08f2d7 | 2004-12-01 23:19:36 +0000 | [diff] [blame] | 799 | X86Instr* X86Instr_SseLdSt ( Bool isLoad, HReg reg, X86AMode* addr ) { |
| 800 | X86Instr* i = LibVEX_Alloc(sizeof(X86Instr)); |
| 801 | i->tag = Xin_SseLdSt; |
| 802 | i->Xin.SseLdSt.isLoad = isLoad; |
| 803 | i->Xin.SseLdSt.reg = reg; |
| 804 | i->Xin.SseLdSt.addr = addr; |
| 805 | return i; |
| 806 | } |
sewardj | 129b3d9 | 2004-12-05 15:42:05 +0000 | [diff] [blame] | 807 | X86Instr* X86Instr_SseLdzLO ( Int sz, HReg reg, X86AMode* addr ) |
| 808 | { |
| 809 | X86Instr* i = LibVEX_Alloc(sizeof(X86Instr)); |
| 810 | i->tag = Xin_SseLdzLO; |
sewardj | 8ee8c88 | 2005-02-25 17:40:26 +0000 | [diff] [blame] | 811 | i->Xin.SseLdzLO.sz = toUChar(sz); |
sewardj | 129b3d9 | 2004-12-05 15:42:05 +0000 | [diff] [blame] | 812 | i->Xin.SseLdzLO.reg = reg; |
| 813 | i->Xin.SseLdzLO.addr = addr; |
| 814 | vassert(sz == 4 || sz == 8); |
| 815 | return i; |
| 816 | } |
sewardj | 636ad76 | 2004-12-07 11:16:04 +0000 | [diff] [blame] | 817 | X86Instr* X86Instr_Sse32Fx4 ( X86SseOp op, HReg src, HReg dst ) { |
sewardj | d08f2d7 | 2004-12-01 23:19:36 +0000 | [diff] [blame] | 818 | X86Instr* i = LibVEX_Alloc(sizeof(X86Instr)); |
| 819 | i->tag = Xin_Sse32Fx4; |
| 820 | i->Xin.Sse32Fx4.op = op; |
| 821 | i->Xin.Sse32Fx4.src = src; |
| 822 | i->Xin.Sse32Fx4.dst = dst; |
sewardj | 164f927 | 2004-12-09 00:39:32 +0000 | [diff] [blame] | 823 | vassert(op != Xsse_MOV); |
sewardj | d08f2d7 | 2004-12-01 23:19:36 +0000 | [diff] [blame] | 824 | return i; |
| 825 | } |
sewardj | 636ad76 | 2004-12-07 11:16:04 +0000 | [diff] [blame] | 826 | X86Instr* X86Instr_Sse32FLo ( X86SseOp op, HReg src, HReg dst ) { |
sewardj | d08f2d7 | 2004-12-01 23:19:36 +0000 | [diff] [blame] | 827 | X86Instr* i = LibVEX_Alloc(sizeof(X86Instr)); |
| 828 | i->tag = Xin_Sse32FLo; |
| 829 | i->Xin.Sse32FLo.op = op; |
| 830 | i->Xin.Sse32FLo.src = src; |
| 831 | i->Xin.Sse32FLo.dst = dst; |
sewardj | 164f927 | 2004-12-09 00:39:32 +0000 | [diff] [blame] | 832 | vassert(op != Xsse_MOV); |
sewardj | d08f2d7 | 2004-12-01 23:19:36 +0000 | [diff] [blame] | 833 | return i; |
| 834 | } |
sewardj | 636ad76 | 2004-12-07 11:16:04 +0000 | [diff] [blame] | 835 | X86Instr* X86Instr_Sse64Fx2 ( X86SseOp op, HReg src, HReg dst ) { |
| 836 | X86Instr* i = LibVEX_Alloc(sizeof(X86Instr)); |
| 837 | i->tag = Xin_Sse64Fx2; |
| 838 | i->Xin.Sse64Fx2.op = op; |
| 839 | i->Xin.Sse64Fx2.src = src; |
| 840 | i->Xin.Sse64Fx2.dst = dst; |
sewardj | 164f927 | 2004-12-09 00:39:32 +0000 | [diff] [blame] | 841 | vassert(op != Xsse_MOV); |
sewardj | 636ad76 | 2004-12-07 11:16:04 +0000 | [diff] [blame] | 842 | return i; |
| 843 | } |
| 844 | X86Instr* X86Instr_Sse64FLo ( X86SseOp op, HReg src, HReg dst ) { |
| 845 | X86Instr* i = LibVEX_Alloc(sizeof(X86Instr)); |
| 846 | i->tag = Xin_Sse64FLo; |
| 847 | i->Xin.Sse64FLo.op = op; |
| 848 | i->Xin.Sse64FLo.src = src; |
| 849 | i->Xin.Sse64FLo.dst = dst; |
sewardj | 164f927 | 2004-12-09 00:39:32 +0000 | [diff] [blame] | 850 | vassert(op != Xsse_MOV); |
| 851 | return i; |
| 852 | } |
| 853 | X86Instr* X86Instr_SseReRg ( X86SseOp op, HReg re, HReg rg ) { |
| 854 | X86Instr* i = LibVEX_Alloc(sizeof(X86Instr)); |
| 855 | i->tag = Xin_SseReRg; |
| 856 | i->Xin.SseReRg.op = op; |
| 857 | i->Xin.SseReRg.src = re; |
| 858 | i->Xin.SseReRg.dst = rg; |
sewardj | 636ad76 | 2004-12-07 11:16:04 +0000 | [diff] [blame] | 859 | return i; |
| 860 | } |
sewardj | b9fa69b | 2004-12-09 23:25:14 +0000 | [diff] [blame] | 861 | X86Instr* X86Instr_SseCMov ( X86CondCode cond, HReg src, HReg dst ) { |
| 862 | X86Instr* i = LibVEX_Alloc(sizeof(X86Instr)); |
| 863 | i->tag = Xin_SseCMov; |
| 864 | i->Xin.SseCMov.cond = cond; |
| 865 | i->Xin.SseCMov.src = src; |
| 866 | i->Xin.SseCMov.dst = dst; |
| 867 | vassert(cond != Xcc_ALWAYS); |
| 868 | return i; |
| 869 | } |
sewardj | 109ffdb | 2004-12-10 21:45:38 +0000 | [diff] [blame] | 870 | X86Instr* X86Instr_SseShuf ( Int order, HReg src, HReg dst ) { |
| 871 | X86Instr* i = LibVEX_Alloc(sizeof(X86Instr)); |
| 872 | i->tag = Xin_SseShuf; |
| 873 | i->Xin.SseShuf.order = order; |
| 874 | i->Xin.SseShuf.src = src; |
| 875 | i->Xin.SseShuf.dst = dst; |
| 876 | vassert(order >= 0 && order <= 0xFF); |
| 877 | return i; |
| 878 | } |
sewardj | 4042c7e | 2004-07-18 01:28:30 +0000 | [diff] [blame] | 879 | |
cerion | 92b6436 | 2005-12-13 12:02:26 +0000 | [diff] [blame] | 880 | void ppX86Instr ( X86Instr* i, Bool mode64 ) { |
| 881 | vassert(mode64 == False); |
sewardj | c97096c | 2004-06-30 09:28:04 +0000 | [diff] [blame] | 882 | switch (i->tag) { |
sewardj | 66f2f79 | 2004-06-30 16:37:16 +0000 | [diff] [blame] | 883 | case Xin_Alu32R: |
sewardj | 60f4e3c | 2004-07-19 01:56:50 +0000 | [diff] [blame] | 884 | vex_printf("%sl ", showX86AluOp(i->Xin.Alu32R.op)); |
sewardj | 35421a3 | 2004-07-05 13:12:34 +0000 | [diff] [blame] | 885 | ppX86RMI(i->Xin.Alu32R.src); |
| 886 | vex_printf(","); |
| 887 | ppHRegX86(i->Xin.Alu32R.dst); |
sewardj | c97096c | 2004-06-30 09:28:04 +0000 | [diff] [blame] | 888 | return; |
sewardj | 66f2f79 | 2004-06-30 16:37:16 +0000 | [diff] [blame] | 889 | case Xin_Alu32M: |
sewardj | 60f4e3c | 2004-07-19 01:56:50 +0000 | [diff] [blame] | 890 | vex_printf("%sl ", showX86AluOp(i->Xin.Alu32M.op)); |
sewardj | 35421a3 | 2004-07-05 13:12:34 +0000 | [diff] [blame] | 891 | ppX86RI(i->Xin.Alu32M.src); |
| 892 | vex_printf(","); |
| 893 | ppX86AMode(i->Xin.Alu32M.dst); |
sewardj | c97096c | 2004-06-30 09:28:04 +0000 | [diff] [blame] | 894 | return; |
sewardj | e8c922f | 2004-07-23 01:34:11 +0000 | [diff] [blame] | 895 | case Xin_Sh32: |
| 896 | vex_printf("%sl ", showX86ShiftOp(i->Xin.Sh32.op)); |
| 897 | if (i->Xin.Sh32.src == 0) |
sewardj | bb53f8c | 2004-08-14 11:50:01 +0000 | [diff] [blame] | 898 | vex_printf("%%cl,"); |
sewardj | e8c922f | 2004-07-23 01:34:11 +0000 | [diff] [blame] | 899 | else |
sewardj | 8ee8c88 | 2005-02-25 17:40:26 +0000 | [diff] [blame] | 900 | vex_printf("$%d,", (Int)i->Xin.Sh32.src); |
sewardj | eba63f8 | 2005-02-23 13:31:25 +0000 | [diff] [blame] | 901 | ppHRegX86(i->Xin.Sh32.dst); |
sewardj | e8c922f | 2004-07-23 01:34:11 +0000 | [diff] [blame] | 902 | return; |
| 903 | case Xin_Test32: |
sewardj | 8ee8c88 | 2005-02-25 17:40:26 +0000 | [diff] [blame] | 904 | vex_printf("testl $%d,", (Int)i->Xin.Test32.imm32); |
sewardj | eba63f8 | 2005-02-23 13:31:25 +0000 | [diff] [blame] | 905 | ppHRegX86(i->Xin.Test32.dst); |
sewardj | e8c922f | 2004-07-23 01:34:11 +0000 | [diff] [blame] | 906 | return; |
sewardj | 60f4e3c | 2004-07-19 01:56:50 +0000 | [diff] [blame] | 907 | case Xin_Unary32: |
| 908 | vex_printf("%sl ", showX86UnaryOp(i->Xin.Unary32.op)); |
sewardj | eba63f8 | 2005-02-23 13:31:25 +0000 | [diff] [blame] | 909 | ppHRegX86(i->Xin.Unary32.dst); |
sewardj | 443cd9d | 2004-07-18 23:06:45 +0000 | [diff] [blame] | 910 | return; |
sewardj | 597b71b | 2004-07-19 02:51:12 +0000 | [diff] [blame] | 911 | case Xin_MulL: |
sewardj | eba63f8 | 2005-02-23 13:31:25 +0000 | [diff] [blame] | 912 | vex_printf("%cmull ", i->Xin.MulL.syned ? 's' : 'u'); |
sewardj | 597b71b | 2004-07-19 02:51:12 +0000 | [diff] [blame] | 913 | ppX86RM(i->Xin.MulL.src); |
| 914 | return; |
sewardj | 5c34dc9 | 2004-07-19 12:48:11 +0000 | [diff] [blame] | 915 | case Xin_Div: |
sewardj | eba63f8 | 2005-02-23 13:31:25 +0000 | [diff] [blame] | 916 | vex_printf("%cdivl ", i->Xin.Div.syned ? 's' : 'u'); |
sewardj | 5c34dc9 | 2004-07-19 12:48:11 +0000 | [diff] [blame] | 917 | ppX86RM(i->Xin.Div.src); |
| 918 | return; |
sewardj | 5c34dc9 | 2004-07-19 12:48:11 +0000 | [diff] [blame] | 919 | case Xin_Sh3232: |
| 920 | vex_printf("%sdl ", showX86ShiftOp(i->Xin.Sh3232.op)); |
| 921 | if (i->Xin.Sh3232.amt == 0) |
sewardj | ea64e14 | 2004-07-22 16:47:21 +0000 | [diff] [blame] | 922 | vex_printf(" %%cl,"); |
sewardj | 5c34dc9 | 2004-07-19 12:48:11 +0000 | [diff] [blame] | 923 | else |
sewardj | 8ee8c88 | 2005-02-25 17:40:26 +0000 | [diff] [blame] | 924 | vex_printf(" $%d,", (Int)i->Xin.Sh3232.amt); |
sewardj | e5f384c | 2004-07-30 16:17:28 +0000 | [diff] [blame] | 925 | ppHRegX86(i->Xin.Sh3232.src); |
sewardj | 5c34dc9 | 2004-07-19 12:48:11 +0000 | [diff] [blame] | 926 | vex_printf(","); |
sewardj | e5f384c | 2004-07-30 16:17:28 +0000 | [diff] [blame] | 927 | ppHRegX86(i->Xin.Sh3232.dst); |
sewardj | 5c34dc9 | 2004-07-19 12:48:11 +0000 | [diff] [blame] | 928 | return; |
sewardj | e8e9d73 | 2004-07-16 21:03:45 +0000 | [diff] [blame] | 929 | case Xin_Push: |
| 930 | vex_printf("pushl "); |
| 931 | ppX86RMI(i->Xin.Push.src); |
| 932 | return; |
| 933 | case Xin_Call: |
sewardj | 4b861de | 2004-11-03 15:24:42 +0000 | [diff] [blame] | 934 | vex_printf("call%s[%d] ", |
| 935 | i->Xin.Call.cond==Xcc_ALWAYS |
| 936 | ? "" : showX86CondCode(i->Xin.Call.cond), |
| 937 | i->Xin.Call.regparms); |
| 938 | vex_printf("0x%x", i->Xin.Call.target); |
sewardj | e8e9d73 | 2004-07-16 21:03:45 +0000 | [diff] [blame] | 939 | break; |
sewardj | 443cd9d | 2004-07-18 23:06:45 +0000 | [diff] [blame] | 940 | case Xin_Goto: |
sewardj | 893aada | 2004-11-29 19:57:54 +0000 | [diff] [blame] | 941 | if (i->Xin.Goto.cond != Xcc_ALWAYS) { |
| 942 | vex_printf("if (%%eflags.%s) { ", |
| 943 | showX86CondCode(i->Xin.Goto.cond)); |
| 944 | } |
sewardj | 17c7f95 | 2005-12-15 14:02:34 +0000 | [diff] [blame^] | 945 | if (i->Xin.Goto.jk != Ijk_Boring |
| 946 | && i->Xin.Goto.jk != Ijk_Call |
| 947 | && i->Xin.Goto.jk != Ijk_Ret) { |
sewardj | 750f407 | 2004-07-26 22:39:11 +0000 | [diff] [blame] | 948 | vex_printf("movl $"); |
| 949 | ppIRJumpKind(i->Xin.Goto.jk); |
sewardj | 893aada | 2004-11-29 19:57:54 +0000 | [diff] [blame] | 950 | vex_printf(",%%ebp ; "); |
sewardj | 750f407 | 2004-07-26 22:39:11 +0000 | [diff] [blame] | 951 | } |
sewardj | 893aada | 2004-11-29 19:57:54 +0000 | [diff] [blame] | 952 | vex_printf("movl "); |
| 953 | ppX86RI(i->Xin.Goto.dst); |
sewardj | 17c7f95 | 2005-12-15 14:02:34 +0000 | [diff] [blame^] | 954 | vex_printf(",%%eax ; movl $dispatcher_addr,%%edx ; jmp *%%edx"); |
sewardj | 893aada | 2004-11-29 19:57:54 +0000 | [diff] [blame] | 955 | if (i->Xin.Goto.cond != Xcc_ALWAYS) { |
| 956 | vex_printf(" }"); |
| 957 | } |
sewardj | c97096c | 2004-06-30 09:28:04 +0000 | [diff] [blame] | 958 | return; |
sewardj | 5c34dc9 | 2004-07-19 12:48:11 +0000 | [diff] [blame] | 959 | case Xin_CMov32: |
sewardj | a2dad5c | 2004-07-23 11:43:43 +0000 | [diff] [blame] | 960 | vex_printf("cmov%s ", showX86CondCode(i->Xin.CMov32.cond)); |
sewardj | 5c34dc9 | 2004-07-19 12:48:11 +0000 | [diff] [blame] | 961 | ppX86RM(i->Xin.CMov32.src); |
sewardj | 4042c7e | 2004-07-18 01:28:30 +0000 | [diff] [blame] | 962 | vex_printf(","); |
sewardj | 5c34dc9 | 2004-07-19 12:48:11 +0000 | [diff] [blame] | 963 | ppHRegX86(i->Xin.CMov32.dst); |
sewardj | 4042c7e | 2004-07-18 01:28:30 +0000 | [diff] [blame] | 964 | return; |
| 965 | case Xin_LoadEX: |
| 966 | vex_printf("mov%c%cl ", |
| 967 | i->Xin.LoadEX.syned ? 's' : 'z', |
| 968 | i->Xin.LoadEX.szSmall==1 ? 'b' : 'w'); |
| 969 | ppX86AMode(i->Xin.LoadEX.src); |
| 970 | vex_printf(","); |
| 971 | ppHRegX86(i->Xin.LoadEX.dst); |
| 972 | return; |
sewardj | 443cd9d | 2004-07-18 23:06:45 +0000 | [diff] [blame] | 973 | case Xin_Store: |
| 974 | vex_printf("mov%c ", i->Xin.Store.sz==1 ? 'b' : 'w'); |
| 975 | ppHRegX86(i->Xin.Store.src); |
| 976 | vex_printf(","); |
| 977 | ppX86AMode(i->Xin.Store.dst); |
| 978 | return; |
sewardj | d7cb853 | 2004-08-17 23:59:23 +0000 | [diff] [blame] | 979 | case Xin_Set32: |
| 980 | vex_printf("setl%s ", showX86CondCode(i->Xin.Set32.cond)); |
| 981 | ppHRegX86(i->Xin.Set32.dst); |
| 982 | return; |
sewardj | ce646f2 | 2004-08-31 23:55:54 +0000 | [diff] [blame] | 983 | case Xin_Bsfr32: |
| 984 | vex_printf("bs%cl ", i->Xin.Bsfr32.isFwds ? 'f' : 'r'); |
| 985 | ppHRegX86(i->Xin.Bsfr32.src); |
| 986 | vex_printf(","); |
| 987 | ppHRegX86(i->Xin.Bsfr32.dst); |
| 988 | return; |
sewardj | 3e83893 | 2005-01-07 12:09:15 +0000 | [diff] [blame] | 989 | case Xin_MFence: |
| 990 | vex_printf("mfence(%s)", |
| 991 | LibVEX_ppVexSubArch(i->Xin.MFence.subarch)); |
| 992 | return; |
sewardj | bb53f8c | 2004-08-14 11:50:01 +0000 | [diff] [blame] | 993 | case Xin_FpUnary: |
| 994 | vex_printf("g%sD ", showX86FpOp(i->Xin.FpUnary.op)); |
| 995 | ppHRegX86(i->Xin.FpUnary.src); |
| 996 | vex_printf(","); |
| 997 | ppHRegX86(i->Xin.FpUnary.dst); |
| 998 | break; |
| 999 | case Xin_FpBinary: |
| 1000 | vex_printf("g%sD ", showX86FpOp(i->Xin.FpBinary.op)); |
| 1001 | ppHRegX86(i->Xin.FpBinary.srcL); |
| 1002 | vex_printf(","); |
| 1003 | ppHRegX86(i->Xin.FpBinary.srcR); |
| 1004 | vex_printf(","); |
| 1005 | ppHRegX86(i->Xin.FpBinary.dst); |
| 1006 | break; |
sewardj | d1725d1 | 2004-08-12 20:46:53 +0000 | [diff] [blame] | 1007 | case Xin_FpLdSt: |
| 1008 | if (i->Xin.FpLdSt.isLoad) { |
sewardj | 3196daf | 2004-08-13 00:18:58 +0000 | [diff] [blame] | 1009 | vex_printf("gld%c " , i->Xin.FpLdSt.sz==8 ? 'D' : 'F'); |
sewardj | d1725d1 | 2004-08-12 20:46:53 +0000 | [diff] [blame] | 1010 | ppX86AMode(i->Xin.FpLdSt.addr); |
| 1011 | vex_printf(", "); |
| 1012 | ppHRegX86(i->Xin.FpLdSt.reg); |
| 1013 | } else { |
sewardj | 3196daf | 2004-08-13 00:18:58 +0000 | [diff] [blame] | 1014 | vex_printf("gst%c " , i->Xin.FpLdSt.sz==8 ? 'D' : 'F'); |
sewardj | d1725d1 | 2004-08-12 20:46:53 +0000 | [diff] [blame] | 1015 | ppHRegX86(i->Xin.FpLdSt.reg); |
| 1016 | vex_printf(", "); |
| 1017 | ppX86AMode(i->Xin.FpLdSt.addr); |
| 1018 | } |
| 1019 | return; |
sewardj | 89cd093 | 2004-09-08 18:23:25 +0000 | [diff] [blame] | 1020 | case Xin_FpLdStI: |
| 1021 | if (i->Xin.FpLdStI.isLoad) { |
| 1022 | vex_printf("gild%s ", i->Xin.FpLdStI.sz==8 ? "ll" : |
| 1023 | i->Xin.FpLdStI.sz==4 ? "l" : "w"); |
| 1024 | ppX86AMode(i->Xin.FpLdStI.addr); |
sewardj | bb53f8c | 2004-08-14 11:50:01 +0000 | [diff] [blame] | 1025 | vex_printf(", "); |
sewardj | 89cd093 | 2004-09-08 18:23:25 +0000 | [diff] [blame] | 1026 | ppHRegX86(i->Xin.FpLdStI.reg); |
| 1027 | } else { |
| 1028 | vex_printf("gist%s ", i->Xin.FpLdStI.sz==8 ? "ll" : |
| 1029 | i->Xin.FpLdStI.sz==4 ? "l" : "w"); |
| 1030 | ppHRegX86(i->Xin.FpLdStI.reg); |
| 1031 | vex_printf(", "); |
| 1032 | ppX86AMode(i->Xin.FpLdStI.addr); |
sewardj | bb53f8c | 2004-08-14 11:50:01 +0000 | [diff] [blame] | 1033 | } |
| 1034 | return; |
sewardj | 3bca906 | 2004-12-04 14:36:09 +0000 | [diff] [blame] | 1035 | case Xin_Fp64to32: |
| 1036 | vex_printf("gdtof "); |
| 1037 | ppHRegX86(i->Xin.Fp64to32.src); |
| 1038 | vex_printf(","); |
| 1039 | ppHRegX86(i->Xin.Fp64to32.dst); |
| 1040 | return; |
sewardj | 33124f6 | 2004-08-30 17:54:18 +0000 | [diff] [blame] | 1041 | case Xin_FpCMov: |
| 1042 | vex_printf("gcmov%s ", showX86CondCode(i->Xin.FpCMov.cond)); |
| 1043 | ppHRegX86(i->Xin.FpCMov.src); |
| 1044 | vex_printf(","); |
| 1045 | ppHRegX86(i->Xin.FpCMov.dst); |
| 1046 | return; |
sewardj | eba63f8 | 2005-02-23 13:31:25 +0000 | [diff] [blame] | 1047 | case Xin_FpLdCW: |
| 1048 | vex_printf("fldcw "); |
| 1049 | ppX86AMode(i->Xin.FpLdCW.addr); |
sewardj | 8f3debf | 2004-09-08 23:42:23 +0000 | [diff] [blame] | 1050 | return; |
sewardj | 46de407 | 2004-09-11 19:23:24 +0000 | [diff] [blame] | 1051 | case Xin_FpStSW_AX: |
| 1052 | vex_printf("fstsw %%ax"); |
| 1053 | return; |
sewardj | bdc7d21 | 2004-09-09 02:46:40 +0000 | [diff] [blame] | 1054 | case Xin_FpCmp: |
| 1055 | vex_printf("gcmp "); |
| 1056 | ppHRegX86(i->Xin.FpCmp.srcL); |
| 1057 | vex_printf(","); |
| 1058 | ppHRegX86(i->Xin.FpCmp.srcR); |
| 1059 | vex_printf(","); |
| 1060 | ppHRegX86(i->Xin.FpCmp.dst); |
| 1061 | break; |
sewardj | 1e6ad74 | 2004-12-02 16:16:11 +0000 | [diff] [blame] | 1062 | case Xin_SseConst: |
| 1063 | vex_printf("const $0x%04x,", (Int)i->Xin.SseConst.con); |
| 1064 | ppHRegX86(i->Xin.SseConst.dst); |
| 1065 | break; |
sewardj | d08f2d7 | 2004-12-01 23:19:36 +0000 | [diff] [blame] | 1066 | case Xin_SseLdSt: |
| 1067 | vex_printf("movups "); |
| 1068 | if (i->Xin.SseLdSt.isLoad) { |
| 1069 | ppX86AMode(i->Xin.SseLdSt.addr); |
| 1070 | vex_printf(","); |
| 1071 | ppHRegX86(i->Xin.SseLdSt.reg); |
| 1072 | } else { |
| 1073 | ppHRegX86(i->Xin.SseLdSt.reg); |
| 1074 | vex_printf(","); |
| 1075 | ppX86AMode(i->Xin.SseLdSt.addr); |
| 1076 | } |
| 1077 | return; |
sewardj | 129b3d9 | 2004-12-05 15:42:05 +0000 | [diff] [blame] | 1078 | case Xin_SseLdzLO: |
| 1079 | vex_printf("movs%s ", i->Xin.SseLdzLO.sz==4 ? "s" : "d"); |
| 1080 | ppX86AMode(i->Xin.SseLdzLO.addr); |
| 1081 | vex_printf(","); |
| 1082 | ppHRegX86(i->Xin.SseLdzLO.reg); |
| 1083 | return; |
sewardj | d08f2d7 | 2004-12-01 23:19:36 +0000 | [diff] [blame] | 1084 | case Xin_Sse32Fx4: |
| 1085 | vex_printf("%sps ", showX86SseOp(i->Xin.Sse32Fx4.op)); |
| 1086 | ppHRegX86(i->Xin.Sse32Fx4.src); |
| 1087 | vex_printf(","); |
| 1088 | ppHRegX86(i->Xin.Sse32Fx4.dst); |
| 1089 | return; |
| 1090 | case Xin_Sse32FLo: |
| 1091 | vex_printf("%sss ", showX86SseOp(i->Xin.Sse32FLo.op)); |
| 1092 | ppHRegX86(i->Xin.Sse32FLo.src); |
| 1093 | vex_printf(","); |
| 1094 | ppHRegX86(i->Xin.Sse32FLo.dst); |
| 1095 | return; |
sewardj | 636ad76 | 2004-12-07 11:16:04 +0000 | [diff] [blame] | 1096 | case Xin_Sse64Fx2: |
| 1097 | vex_printf("%spd ", showX86SseOp(i->Xin.Sse64Fx2.op)); |
| 1098 | ppHRegX86(i->Xin.Sse64Fx2.src); |
| 1099 | vex_printf(","); |
| 1100 | ppHRegX86(i->Xin.Sse64Fx2.dst); |
| 1101 | return; |
| 1102 | case Xin_Sse64FLo: |
| 1103 | vex_printf("%ssd ", showX86SseOp(i->Xin.Sse64FLo.op)); |
| 1104 | ppHRegX86(i->Xin.Sse64FLo.src); |
| 1105 | vex_printf(","); |
| 1106 | ppHRegX86(i->Xin.Sse64FLo.dst); |
| 1107 | return; |
sewardj | 164f927 | 2004-12-09 00:39:32 +0000 | [diff] [blame] | 1108 | case Xin_SseReRg: |
| 1109 | vex_printf("%s ", showX86SseOp(i->Xin.SseReRg.op)); |
| 1110 | ppHRegX86(i->Xin.SseReRg.src); |
| 1111 | vex_printf(","); |
| 1112 | ppHRegX86(i->Xin.SseReRg.dst); |
| 1113 | return; |
sewardj | b9fa69b | 2004-12-09 23:25:14 +0000 | [diff] [blame] | 1114 | case Xin_SseCMov: |
| 1115 | vex_printf("cmov%s ", showX86CondCode(i->Xin.SseCMov.cond)); |
| 1116 | ppHRegX86(i->Xin.SseCMov.src); |
| 1117 | vex_printf(","); |
| 1118 | ppHRegX86(i->Xin.SseCMov.dst); |
| 1119 | return; |
sewardj | 109ffdb | 2004-12-10 21:45:38 +0000 | [diff] [blame] | 1120 | case Xin_SseShuf: |
| 1121 | vex_printf("pshufd $0x%x,", i->Xin.SseShuf.order); |
| 1122 | ppHRegX86(i->Xin.SseShuf.src); |
| 1123 | vex_printf(","); |
| 1124 | ppHRegX86(i->Xin.SseShuf.dst); |
| 1125 | return; |
sewardj | d08f2d7 | 2004-12-01 23:19:36 +0000 | [diff] [blame] | 1126 | |
sewardj | c97096c | 2004-06-30 09:28:04 +0000 | [diff] [blame] | 1127 | default: |
sewardj | 35421a3 | 2004-07-05 13:12:34 +0000 | [diff] [blame] | 1128 | vpanic("ppX86Instr"); |
sewardj | c97096c | 2004-06-30 09:28:04 +0000 | [diff] [blame] | 1129 | } |
| 1130 | } |
sewardj | 53f85a9 | 2004-07-02 13:45:17 +0000 | [diff] [blame] | 1131 | |
sewardj | 194d54a | 2004-07-03 19:08:18 +0000 | [diff] [blame] | 1132 | /* --------- Helpers for register allocation. --------- */ |
| 1133 | |
cerion | 92b6436 | 2005-12-13 12:02:26 +0000 | [diff] [blame] | 1134 | void getRegUsage_X86Instr (HRegUsage* u, X86Instr* i, Bool mode64) |
sewardj | 53f85a9 | 2004-07-02 13:45:17 +0000 | [diff] [blame] | 1135 | { |
sewardj | 0bd7ce6 | 2004-12-05 02:47:40 +0000 | [diff] [blame] | 1136 | Bool unary; |
cerion | 92b6436 | 2005-12-13 12:02:26 +0000 | [diff] [blame] | 1137 | vassert(mode64 == False); |
sewardj | 53f85a9 | 2004-07-02 13:45:17 +0000 | [diff] [blame] | 1138 | initHRegUsage(u); |
| 1139 | switch (i->tag) { |
| 1140 | case Xin_Alu32R: |
| 1141 | addRegUsage_X86RMI(u, i->Xin.Alu32R.src); |
sewardj | 4042c7e | 2004-07-18 01:28:30 +0000 | [diff] [blame] | 1142 | if (i->Xin.Alu32R.op == Xalu_MOV) { |
sewardj | eba63f8 | 2005-02-23 13:31:25 +0000 | [diff] [blame] | 1143 | addHRegUse(u, HRmWrite, i->Xin.Alu32R.dst); |
sewardj | 4042c7e | 2004-07-18 01:28:30 +0000 | [diff] [blame] | 1144 | return; |
| 1145 | } |
sewardj | e8c922f | 2004-07-23 01:34:11 +0000 | [diff] [blame] | 1146 | if (i->Xin.Alu32R.op == Xalu_CMP) { |
sewardj | eba63f8 | 2005-02-23 13:31:25 +0000 | [diff] [blame] | 1147 | addHRegUse(u, HRmRead, i->Xin.Alu32R.dst); |
sewardj | 4042c7e | 2004-07-18 01:28:30 +0000 | [diff] [blame] | 1148 | return; |
| 1149 | } |
| 1150 | addHRegUse(u, HRmModify, i->Xin.Alu32R.dst); |
sewardj | 53f85a9 | 2004-07-02 13:45:17 +0000 | [diff] [blame] | 1151 | return; |
| 1152 | case Xin_Alu32M: |
| 1153 | addRegUsage_X86RI(u, i->Xin.Alu32M.src); |
| 1154 | addRegUsage_X86AMode(u, i->Xin.Alu32M.dst); |
| 1155 | return; |
sewardj | e8c922f | 2004-07-23 01:34:11 +0000 | [diff] [blame] | 1156 | case Xin_Sh32: |
sewardj | eba63f8 | 2005-02-23 13:31:25 +0000 | [diff] [blame] | 1157 | addHRegUse(u, HRmModify, i->Xin.Sh32.dst); |
sewardj | e8c922f | 2004-07-23 01:34:11 +0000 | [diff] [blame] | 1158 | if (i->Xin.Sh32.src == 0) |
| 1159 | addHRegUse(u, HRmRead, hregX86_ECX()); |
| 1160 | return; |
| 1161 | case Xin_Test32: |
sewardj | eba63f8 | 2005-02-23 13:31:25 +0000 | [diff] [blame] | 1162 | addHRegUse(u, HRmRead, i->Xin.Test32.dst); |
sewardj | e8c922f | 2004-07-23 01:34:11 +0000 | [diff] [blame] | 1163 | return; |
sewardj | 1f40a0a | 2004-07-21 12:28:07 +0000 | [diff] [blame] | 1164 | case Xin_Unary32: |
sewardj | eba63f8 | 2005-02-23 13:31:25 +0000 | [diff] [blame] | 1165 | addHRegUse(u, HRmModify, i->Xin.Unary32.dst); |
sewardj | 1f40a0a | 2004-07-21 12:28:07 +0000 | [diff] [blame] | 1166 | return; |
| 1167 | case Xin_MulL: |
| 1168 | addRegUsage_X86RM(u, i->Xin.MulL.src, HRmRead); |
| 1169 | addHRegUse(u, HRmModify, hregX86_EAX()); |
| 1170 | addHRegUse(u, HRmWrite, hregX86_EDX()); |
| 1171 | return; |
| 1172 | case Xin_Div: |
sewardj | ea64e14 | 2004-07-22 16:47:21 +0000 | [diff] [blame] | 1173 | addRegUsage_X86RM(u, i->Xin.Div.src, HRmRead); |
sewardj | 1f40a0a | 2004-07-21 12:28:07 +0000 | [diff] [blame] | 1174 | addHRegUse(u, HRmModify, hregX86_EAX()); |
| 1175 | addHRegUse(u, HRmModify, hregX86_EDX()); |
| 1176 | return; |
sewardj | 1f40a0a | 2004-07-21 12:28:07 +0000 | [diff] [blame] | 1177 | case Xin_Sh3232: |
sewardj | e5f384c | 2004-07-30 16:17:28 +0000 | [diff] [blame] | 1178 | addHRegUse(u, HRmRead, i->Xin.Sh3232.src); |
| 1179 | addHRegUse(u, HRmModify, i->Xin.Sh3232.dst); |
sewardj | 1f40a0a | 2004-07-21 12:28:07 +0000 | [diff] [blame] | 1180 | if (i->Xin.Sh3232.amt == 0) |
| 1181 | addHRegUse(u, HRmRead, hregX86_ECX()); |
| 1182 | return; |
sewardj | e8e9d73 | 2004-07-16 21:03:45 +0000 | [diff] [blame] | 1183 | case Xin_Push: |
| 1184 | addRegUsage_X86RMI(u, i->Xin.Push.src); |
| 1185 | addHRegUse(u, HRmModify, hregX86_ESP()); |
| 1186 | return; |
| 1187 | case Xin_Call: |
sewardj | 4b861de | 2004-11-03 15:24:42 +0000 | [diff] [blame] | 1188 | /* This is a bit subtle. */ |
sewardj | cdcf00b | 2005-02-04 01:40:03 +0000 | [diff] [blame] | 1189 | /* First off, claim it trashes all the caller-saved regs |
| 1190 | which fall within the register allocator's jurisdiction. |
| 1191 | These I believe to be %eax,%ecx,%edx. */ |
sewardj | e8e9d73 | 2004-07-16 21:03:45 +0000 | [diff] [blame] | 1192 | addHRegUse(u, HRmWrite, hregX86_EAX()); |
| 1193 | addHRegUse(u, HRmWrite, hregX86_ECX()); |
| 1194 | addHRegUse(u, HRmWrite, hregX86_EDX()); |
sewardj | 4b861de | 2004-11-03 15:24:42 +0000 | [diff] [blame] | 1195 | /* Now we have to state any parameter-carrying registers |
| 1196 | which might be read. This depends on the regparmness. */ |
sewardj | 7735254 | 2004-10-30 20:39:01 +0000 | [diff] [blame] | 1197 | switch (i->Xin.Call.regparms) { |
| 1198 | case 3: addHRegUse(u, HRmRead, hregX86_ECX()); /*fallthru*/ |
| 1199 | case 2: addHRegUse(u, HRmRead, hregX86_EDX()); /*fallthru*/ |
| 1200 | case 1: addHRegUse(u, HRmRead, hregX86_EAX()); break; |
| 1201 | case 0: break; |
| 1202 | default: vpanic("getRegUsage_X86Instr:Call:regparms"); |
| 1203 | } |
sewardj | 4b861de | 2004-11-03 15:24:42 +0000 | [diff] [blame] | 1204 | /* Finally, there is the issue that the insn trashes a |
| 1205 | register because the literal target address has to be |
| 1206 | loaded into a register. Fortunately, for the 0/1/2 |
sewardj | 45c50eb | 2004-11-04 18:25:33 +0000 | [diff] [blame] | 1207 | regparm case, we can use EAX, EDX and ECX respectively, so |
sewardj | 4b861de | 2004-11-03 15:24:42 +0000 | [diff] [blame] | 1208 | this does not cause any further damage. For the 3-regparm |
| 1209 | case, we'll have to choose another register arbitrarily -- |
sewardj | 45c50eb | 2004-11-04 18:25:33 +0000 | [diff] [blame] | 1210 | since A, D and C are used for parameters -- and so we might |
sewardj | 4b861de | 2004-11-03 15:24:42 +0000 | [diff] [blame] | 1211 | as well choose EDI. */ |
| 1212 | if (i->Xin.Call.regparms == 3) |
| 1213 | addHRegUse(u, HRmWrite, hregX86_EDI()); |
| 1214 | /* Upshot of this is that the assembler really must observe |
| 1215 | the here-stated convention of which register to use as an |
| 1216 | address temporary, depending on the regparmness: 0==EAX, |
sewardj | 45c50eb | 2004-11-04 18:25:33 +0000 | [diff] [blame] | 1217 | 1==EDX, 2==ECX, 3==EDI. */ |
sewardj | e8e9d73 | 2004-07-16 21:03:45 +0000 | [diff] [blame] | 1218 | return; |
sewardj | 443cd9d | 2004-07-18 23:06:45 +0000 | [diff] [blame] | 1219 | case Xin_Goto: |
| 1220 | addRegUsage_X86RI(u, i->Xin.Goto.dst); |
sewardj | 17c7f95 | 2005-12-15 14:02:34 +0000 | [diff] [blame^] | 1221 | addHRegUse(u, HRmWrite, hregX86_EAX()); /* used for next guest addr */ |
| 1222 | addHRegUse(u, HRmWrite, hregX86_EDX()); /* used for dispatcher addr */ |
| 1223 | if (i->Xin.Goto.jk != Ijk_Boring |
| 1224 | && i->Xin.Goto.jk != Ijk_Call |
| 1225 | && i->Xin.Goto.jk != Ijk_Ret) |
| 1226 | /* note, this is irrelevant since ebp is not actually |
| 1227 | available to the allocator. But still .. */ |
sewardj | 750f407 | 2004-07-26 22:39:11 +0000 | [diff] [blame] | 1228 | addHRegUse(u, HRmWrite, hregX86_EBP()); |
sewardj | 0ec3325 | 2004-07-03 13:30:00 +0000 | [diff] [blame] | 1229 | return; |
sewardj | 1f40a0a | 2004-07-21 12:28:07 +0000 | [diff] [blame] | 1230 | case Xin_CMov32: |
| 1231 | addRegUsage_X86RM(u, i->Xin.CMov32.src, HRmRead); |
| 1232 | addHRegUse(u, HRmModify, i->Xin.CMov32.dst); |
| 1233 | return; |
| 1234 | case Xin_LoadEX: |
| 1235 | addRegUsage_X86AMode(u, i->Xin.LoadEX.src); |
| 1236 | addHRegUse(u, HRmWrite, i->Xin.LoadEX.dst); |
| 1237 | return; |
| 1238 | case Xin_Store: |
| 1239 | addHRegUse(u, HRmRead, i->Xin.Store.src); |
| 1240 | addRegUsage_X86AMode(u, i->Xin.Store.dst); |
| 1241 | return; |
sewardj | d7cb853 | 2004-08-17 23:59:23 +0000 | [diff] [blame] | 1242 | case Xin_Set32: |
| 1243 | addHRegUse(u, HRmWrite, i->Xin.Set32.dst); |
| 1244 | return; |
sewardj | ce646f2 | 2004-08-31 23:55:54 +0000 | [diff] [blame] | 1245 | case Xin_Bsfr32: |
| 1246 | addHRegUse(u, HRmRead, i->Xin.Bsfr32.src); |
| 1247 | addHRegUse(u, HRmWrite, i->Xin.Bsfr32.dst); |
| 1248 | return; |
sewardj | 3e83893 | 2005-01-07 12:09:15 +0000 | [diff] [blame] | 1249 | case Xin_MFence: |
| 1250 | return; |
sewardj | bb53f8c | 2004-08-14 11:50:01 +0000 | [diff] [blame] | 1251 | case Xin_FpUnary: |
| 1252 | addHRegUse(u, HRmRead, i->Xin.FpUnary.src); |
| 1253 | addHRegUse(u, HRmWrite, i->Xin.FpUnary.dst); |
| 1254 | return; |
| 1255 | case Xin_FpBinary: |
| 1256 | addHRegUse(u, HRmRead, i->Xin.FpBinary.srcL); |
| 1257 | addHRegUse(u, HRmRead, i->Xin.FpBinary.srcR); |
| 1258 | addHRegUse(u, HRmWrite, i->Xin.FpBinary.dst); |
| 1259 | return; |
sewardj | 3196daf | 2004-08-13 00:18:58 +0000 | [diff] [blame] | 1260 | case Xin_FpLdSt: |
| 1261 | addRegUsage_X86AMode(u, i->Xin.FpLdSt.addr); |
| 1262 | addHRegUse(u, i->Xin.FpLdSt.isLoad ? HRmWrite : HRmRead, |
| 1263 | i->Xin.FpLdSt.reg); |
| 1264 | return; |
sewardj | 89cd093 | 2004-09-08 18:23:25 +0000 | [diff] [blame] | 1265 | case Xin_FpLdStI: |
| 1266 | addRegUsage_X86AMode(u, i->Xin.FpLdStI.addr); |
| 1267 | addHRegUse(u, i->Xin.FpLdStI.isLoad ? HRmWrite : HRmRead, |
| 1268 | i->Xin.FpLdStI.reg); |
sewardj | bb53f8c | 2004-08-14 11:50:01 +0000 | [diff] [blame] | 1269 | return; |
sewardj | 3bca906 | 2004-12-04 14:36:09 +0000 | [diff] [blame] | 1270 | case Xin_Fp64to32: |
| 1271 | addHRegUse(u, HRmRead, i->Xin.Fp64to32.src); |
| 1272 | addHRegUse(u, HRmWrite, i->Xin.Fp64to32.dst); |
| 1273 | return; |
sewardj | 3fc76d2 | 2004-08-31 11:47:54 +0000 | [diff] [blame] | 1274 | case Xin_FpCMov: |
sewardj | b9fa69b | 2004-12-09 23:25:14 +0000 | [diff] [blame] | 1275 | addHRegUse(u, HRmRead, i->Xin.FpCMov.src); |
sewardj | 3fc76d2 | 2004-08-31 11:47:54 +0000 | [diff] [blame] | 1276 | addHRegUse(u, HRmModify, i->Xin.FpCMov.dst); |
| 1277 | return; |
sewardj | eba63f8 | 2005-02-23 13:31:25 +0000 | [diff] [blame] | 1278 | case Xin_FpLdCW: |
| 1279 | addRegUsage_X86AMode(u, i->Xin.FpLdCW.addr); |
sewardj | 8f3debf | 2004-09-08 23:42:23 +0000 | [diff] [blame] | 1280 | return; |
sewardj | 46de407 | 2004-09-11 19:23:24 +0000 | [diff] [blame] | 1281 | case Xin_FpStSW_AX: |
| 1282 | addHRegUse(u, HRmWrite, hregX86_EAX()); |
| 1283 | return; |
sewardj | bdc7d21 | 2004-09-09 02:46:40 +0000 | [diff] [blame] | 1284 | case Xin_FpCmp: |
| 1285 | addHRegUse(u, HRmRead, i->Xin.FpCmp.srcL); |
| 1286 | addHRegUse(u, HRmRead, i->Xin.FpCmp.srcR); |
| 1287 | addHRegUse(u, HRmWrite, i->Xin.FpCmp.dst); |
| 1288 | addHRegUse(u, HRmWrite, hregX86_EAX()); |
| 1289 | return; |
sewardj | d08f2d7 | 2004-12-01 23:19:36 +0000 | [diff] [blame] | 1290 | case Xin_SseLdSt: |
| 1291 | addRegUsage_X86AMode(u, i->Xin.SseLdSt.addr); |
| 1292 | addHRegUse(u, i->Xin.SseLdSt.isLoad ? HRmWrite : HRmRead, |
| 1293 | i->Xin.SseLdSt.reg); |
| 1294 | return; |
sewardj | 129b3d9 | 2004-12-05 15:42:05 +0000 | [diff] [blame] | 1295 | case Xin_SseLdzLO: |
| 1296 | addRegUsage_X86AMode(u, i->Xin.SseLdzLO.addr); |
| 1297 | addHRegUse(u, HRmWrite, i->Xin.SseLdzLO.reg); |
| 1298 | return; |
sewardj | 1e6ad74 | 2004-12-02 16:16:11 +0000 | [diff] [blame] | 1299 | case Xin_SseConst: |
| 1300 | addHRegUse(u, HRmWrite, i->Xin.SseConst.dst); |
| 1301 | return; |
sewardj | d08f2d7 | 2004-12-01 23:19:36 +0000 | [diff] [blame] | 1302 | case Xin_Sse32Fx4: |
| 1303 | vassert(i->Xin.Sse32Fx4.op != Xsse_MOV); |
sewardj | 8ee8c88 | 2005-02-25 17:40:26 +0000 | [diff] [blame] | 1304 | unary = toBool( i->Xin.Sse32Fx4.op == Xsse_RCPF |
| 1305 | || i->Xin.Sse32Fx4.op == Xsse_RSQRTF |
| 1306 | || i->Xin.Sse32Fx4.op == Xsse_SQRTF ); |
sewardj | 0bd7ce6 | 2004-12-05 02:47:40 +0000 | [diff] [blame] | 1307 | addHRegUse(u, HRmRead, i->Xin.Sse32Fx4.src); |
| 1308 | addHRegUse(u, unary ? HRmWrite : HRmModify, |
| 1309 | i->Xin.Sse32Fx4.dst); |
sewardj | d08f2d7 | 2004-12-01 23:19:36 +0000 | [diff] [blame] | 1310 | return; |
sewardj | 1e6ad74 | 2004-12-02 16:16:11 +0000 | [diff] [blame] | 1311 | case Xin_Sse32FLo: |
| 1312 | vassert(i->Xin.Sse32FLo.op != Xsse_MOV); |
sewardj | 8ee8c88 | 2005-02-25 17:40:26 +0000 | [diff] [blame] | 1313 | unary = toBool( i->Xin.Sse32FLo.op == Xsse_RCPF |
| 1314 | || i->Xin.Sse32FLo.op == Xsse_RSQRTF |
| 1315 | || i->Xin.Sse32FLo.op == Xsse_SQRTF ); |
sewardj | 0bd7ce6 | 2004-12-05 02:47:40 +0000 | [diff] [blame] | 1316 | addHRegUse(u, HRmRead, i->Xin.Sse32FLo.src); |
| 1317 | addHRegUse(u, unary ? HRmWrite : HRmModify, |
| 1318 | i->Xin.Sse32FLo.dst); |
sewardj | 1e6ad74 | 2004-12-02 16:16:11 +0000 | [diff] [blame] | 1319 | return; |
sewardj | 636ad76 | 2004-12-07 11:16:04 +0000 | [diff] [blame] | 1320 | case Xin_Sse64Fx2: |
| 1321 | vassert(i->Xin.Sse64Fx2.op != Xsse_MOV); |
sewardj | 8ee8c88 | 2005-02-25 17:40:26 +0000 | [diff] [blame] | 1322 | unary = toBool( i->Xin.Sse64Fx2.op == Xsse_RCPF |
| 1323 | || i->Xin.Sse64Fx2.op == Xsse_RSQRTF |
| 1324 | || i->Xin.Sse64Fx2.op == Xsse_SQRTF ); |
sewardj | 636ad76 | 2004-12-07 11:16:04 +0000 | [diff] [blame] | 1325 | addHRegUse(u, HRmRead, i->Xin.Sse64Fx2.src); |
| 1326 | addHRegUse(u, unary ? HRmWrite : HRmModify, |
| 1327 | i->Xin.Sse64Fx2.dst); |
| 1328 | return; |
| 1329 | case Xin_Sse64FLo: |
| 1330 | vassert(i->Xin.Sse64FLo.op != Xsse_MOV); |
sewardj | 8ee8c88 | 2005-02-25 17:40:26 +0000 | [diff] [blame] | 1331 | unary = toBool( i->Xin.Sse64FLo.op == Xsse_RCPF |
| 1332 | || i->Xin.Sse64FLo.op == Xsse_RSQRTF |
| 1333 | || i->Xin.Sse64FLo.op == Xsse_SQRTF ); |
sewardj | 636ad76 | 2004-12-07 11:16:04 +0000 | [diff] [blame] | 1334 | addHRegUse(u, HRmRead, i->Xin.Sse64FLo.src); |
| 1335 | addHRegUse(u, unary ? HRmWrite : HRmModify, |
| 1336 | i->Xin.Sse64FLo.dst); |
| 1337 | return; |
sewardj | 164f927 | 2004-12-09 00:39:32 +0000 | [diff] [blame] | 1338 | case Xin_SseReRg: |
sewardj | 109ffdb | 2004-12-10 21:45:38 +0000 | [diff] [blame] | 1339 | if (i->Xin.SseReRg.op == Xsse_XOR |
| 1340 | && i->Xin.SseReRg.src == i->Xin.SseReRg.dst) { |
| 1341 | /* reg-alloc needs to understand 'xor r,r' as a write of r */ |
| 1342 | /* (as opposed to a rite of passage :-) */ |
| 1343 | addHRegUse(u, HRmWrite, i->Xin.SseReRg.dst); |
| 1344 | } else { |
| 1345 | addHRegUse(u, HRmRead, i->Xin.SseReRg.src); |
| 1346 | addHRegUse(u, i->Xin.SseReRg.op == Xsse_MOV |
| 1347 | ? HRmWrite : HRmModify, |
| 1348 | i->Xin.SseReRg.dst); |
| 1349 | } |
sewardj | 164f927 | 2004-12-09 00:39:32 +0000 | [diff] [blame] | 1350 | return; |
sewardj | b9fa69b | 2004-12-09 23:25:14 +0000 | [diff] [blame] | 1351 | case Xin_SseCMov: |
| 1352 | addHRegUse(u, HRmRead, i->Xin.SseCMov.src); |
| 1353 | addHRegUse(u, HRmModify, i->Xin.SseCMov.dst); |
| 1354 | return; |
sewardj | 109ffdb | 2004-12-10 21:45:38 +0000 | [diff] [blame] | 1355 | case Xin_SseShuf: |
| 1356 | addHRegUse(u, HRmRead, i->Xin.SseShuf.src); |
| 1357 | addHRegUse(u, HRmWrite, i->Xin.SseShuf.dst); |
| 1358 | return; |
sewardj | 53f85a9 | 2004-07-02 13:45:17 +0000 | [diff] [blame] | 1359 | default: |
cerion | 92b6436 | 2005-12-13 12:02:26 +0000 | [diff] [blame] | 1360 | ppX86Instr(i, False); |
sewardj | 35421a3 | 2004-07-05 13:12:34 +0000 | [diff] [blame] | 1361 | vpanic("getRegUsage_X86Instr"); |
sewardj | 53f85a9 | 2004-07-02 13:45:17 +0000 | [diff] [blame] | 1362 | } |
| 1363 | } |
| 1364 | |
sewardj | 1f40a0a | 2004-07-21 12:28:07 +0000 | [diff] [blame] | 1365 | /* local helper */ |
cerion | 92b6436 | 2005-12-13 12:02:26 +0000 | [diff] [blame] | 1366 | static void mapReg( HRegRemap* m, HReg* r ) |
sewardj | 1f40a0a | 2004-07-21 12:28:07 +0000 | [diff] [blame] | 1367 | { |
| 1368 | *r = lookupHRegRemap(m, *r); |
| 1369 | } |
| 1370 | |
cerion | 92b6436 | 2005-12-13 12:02:26 +0000 | [diff] [blame] | 1371 | void mapRegs_X86Instr ( HRegRemap* m, X86Instr* i, Bool mode64 ) |
sewardj | 53f85a9 | 2004-07-02 13:45:17 +0000 | [diff] [blame] | 1372 | { |
cerion | 92b6436 | 2005-12-13 12:02:26 +0000 | [diff] [blame] | 1373 | vassert(mode64 == False); |
sewardj | 53f85a9 | 2004-07-02 13:45:17 +0000 | [diff] [blame] | 1374 | switch (i->tag) { |
| 1375 | case Xin_Alu32R: |
| 1376 | mapRegs_X86RMI(m, i->Xin.Alu32R.src); |
sewardj | 1f40a0a | 2004-07-21 12:28:07 +0000 | [diff] [blame] | 1377 | mapReg(m, &i->Xin.Alu32R.dst); |
sewardj | 53f85a9 | 2004-07-02 13:45:17 +0000 | [diff] [blame] | 1378 | return; |
| 1379 | case Xin_Alu32M: |
| 1380 | mapRegs_X86RI(m, i->Xin.Alu32M.src); |
| 1381 | mapRegs_X86AMode(m, i->Xin.Alu32M.dst); |
| 1382 | return; |
sewardj | e8c922f | 2004-07-23 01:34:11 +0000 | [diff] [blame] | 1383 | case Xin_Sh32: |
sewardj | eba63f8 | 2005-02-23 13:31:25 +0000 | [diff] [blame] | 1384 | mapReg(m, &i->Xin.Sh32.dst); |
sewardj | e8c922f | 2004-07-23 01:34:11 +0000 | [diff] [blame] | 1385 | return; |
| 1386 | case Xin_Test32: |
sewardj | eba63f8 | 2005-02-23 13:31:25 +0000 | [diff] [blame] | 1387 | mapReg(m, &i->Xin.Test32.dst); |
sewardj | e8c922f | 2004-07-23 01:34:11 +0000 | [diff] [blame] | 1388 | return; |
sewardj | 1f40a0a | 2004-07-21 12:28:07 +0000 | [diff] [blame] | 1389 | case Xin_Unary32: |
sewardj | eba63f8 | 2005-02-23 13:31:25 +0000 | [diff] [blame] | 1390 | mapReg(m, &i->Xin.Unary32.dst); |
sewardj | 1f40a0a | 2004-07-21 12:28:07 +0000 | [diff] [blame] | 1391 | return; |
| 1392 | case Xin_MulL: |
| 1393 | mapRegs_X86RM(m, i->Xin.MulL.src); |
| 1394 | return; |
| 1395 | case Xin_Div: |
sewardj | ea64e14 | 2004-07-22 16:47:21 +0000 | [diff] [blame] | 1396 | mapRegs_X86RM(m, i->Xin.Div.src); |
sewardj | 1f40a0a | 2004-07-21 12:28:07 +0000 | [diff] [blame] | 1397 | return; |
sewardj | 1f40a0a | 2004-07-21 12:28:07 +0000 | [diff] [blame] | 1398 | case Xin_Sh3232: |
sewardj | e5f384c | 2004-07-30 16:17:28 +0000 | [diff] [blame] | 1399 | mapReg(m, &i->Xin.Sh3232.src); |
| 1400 | mapReg(m, &i->Xin.Sh3232.dst); |
sewardj | 1f40a0a | 2004-07-21 12:28:07 +0000 | [diff] [blame] | 1401 | return; |
| 1402 | case Xin_Push: |
| 1403 | mapRegs_X86RMI(m, i->Xin.Push.src); |
| 1404 | return; |
| 1405 | case Xin_Call: |
sewardj | 1f40a0a | 2004-07-21 12:28:07 +0000 | [diff] [blame] | 1406 | return; |
sewardj | 443cd9d | 2004-07-18 23:06:45 +0000 | [diff] [blame] | 1407 | case Xin_Goto: |
| 1408 | mapRegs_X86RI(m, i->Xin.Goto.dst); |
sewardj | 0ec3325 | 2004-07-03 13:30:00 +0000 | [diff] [blame] | 1409 | return; |
sewardj | 1f40a0a | 2004-07-21 12:28:07 +0000 | [diff] [blame] | 1410 | case Xin_CMov32: |
| 1411 | mapRegs_X86RM(m, i->Xin.CMov32.src); |
| 1412 | mapReg(m, &i->Xin.CMov32.dst); |
| 1413 | return; |
| 1414 | case Xin_LoadEX: |
| 1415 | mapRegs_X86AMode(m, i->Xin.LoadEX.src); |
| 1416 | mapReg(m, &i->Xin.LoadEX.dst); |
| 1417 | return; |
| 1418 | case Xin_Store: |
| 1419 | mapReg(m, &i->Xin.Store.src); |
| 1420 | mapRegs_X86AMode(m, i->Xin.Store.dst); |
| 1421 | return; |
sewardj | d7cb853 | 2004-08-17 23:59:23 +0000 | [diff] [blame] | 1422 | case Xin_Set32: |
| 1423 | mapReg(m, &i->Xin.Set32.dst); |
| 1424 | return; |
sewardj | ce646f2 | 2004-08-31 23:55:54 +0000 | [diff] [blame] | 1425 | case Xin_Bsfr32: |
| 1426 | mapReg(m, &i->Xin.Bsfr32.src); |
| 1427 | mapReg(m, &i->Xin.Bsfr32.dst); |
| 1428 | return; |
sewardj | 3e83893 | 2005-01-07 12:09:15 +0000 | [diff] [blame] | 1429 | case Xin_MFence: |
| 1430 | return; |
sewardj | cfded9a | 2004-09-09 11:44:16 +0000 | [diff] [blame] | 1431 | case Xin_FpUnary: |
| 1432 | mapReg(m, &i->Xin.FpUnary.src); |
| 1433 | mapReg(m, &i->Xin.FpUnary.dst); |
| 1434 | return; |
sewardj | bb53f8c | 2004-08-14 11:50:01 +0000 | [diff] [blame] | 1435 | case Xin_FpBinary: |
| 1436 | mapReg(m, &i->Xin.FpBinary.srcL); |
| 1437 | mapReg(m, &i->Xin.FpBinary.srcR); |
| 1438 | mapReg(m, &i->Xin.FpBinary.dst); |
| 1439 | return; |
sewardj | 3196daf | 2004-08-13 00:18:58 +0000 | [diff] [blame] | 1440 | case Xin_FpLdSt: |
| 1441 | mapRegs_X86AMode(m, i->Xin.FpLdSt.addr); |
| 1442 | mapReg(m, &i->Xin.FpLdSt.reg); |
| 1443 | return; |
sewardj | 89cd093 | 2004-09-08 18:23:25 +0000 | [diff] [blame] | 1444 | case Xin_FpLdStI: |
| 1445 | mapRegs_X86AMode(m, i->Xin.FpLdStI.addr); |
| 1446 | mapReg(m, &i->Xin.FpLdStI.reg); |
sewardj | bb53f8c | 2004-08-14 11:50:01 +0000 | [diff] [blame] | 1447 | return; |
sewardj | 3bca906 | 2004-12-04 14:36:09 +0000 | [diff] [blame] | 1448 | case Xin_Fp64to32: |
| 1449 | mapReg(m, &i->Xin.Fp64to32.src); |
| 1450 | mapReg(m, &i->Xin.Fp64to32.dst); |
| 1451 | return; |
sewardj | 3fc76d2 | 2004-08-31 11:47:54 +0000 | [diff] [blame] | 1452 | case Xin_FpCMov: |
| 1453 | mapReg(m, &i->Xin.FpCMov.src); |
| 1454 | mapReg(m, &i->Xin.FpCMov.dst); |
| 1455 | return; |
sewardj | eba63f8 | 2005-02-23 13:31:25 +0000 | [diff] [blame] | 1456 | case Xin_FpLdCW: |
| 1457 | mapRegs_X86AMode(m, i->Xin.FpLdCW.addr); |
sewardj | 8f3debf | 2004-09-08 23:42:23 +0000 | [diff] [blame] | 1458 | return; |
sewardj | 46de407 | 2004-09-11 19:23:24 +0000 | [diff] [blame] | 1459 | case Xin_FpStSW_AX: |
| 1460 | return; |
sewardj | bdc7d21 | 2004-09-09 02:46:40 +0000 | [diff] [blame] | 1461 | case Xin_FpCmp: |
| 1462 | mapReg(m, &i->Xin.FpCmp.srcL); |
| 1463 | mapReg(m, &i->Xin.FpCmp.srcR); |
| 1464 | mapReg(m, &i->Xin.FpCmp.dst); |
| 1465 | return; |
sewardj | 1e6ad74 | 2004-12-02 16:16:11 +0000 | [diff] [blame] | 1466 | case Xin_SseConst: |
| 1467 | mapReg(m, &i->Xin.SseConst.dst); |
| 1468 | return; |
sewardj | d08f2d7 | 2004-12-01 23:19:36 +0000 | [diff] [blame] | 1469 | case Xin_SseLdSt: |
| 1470 | mapReg(m, &i->Xin.SseLdSt.reg); |
| 1471 | mapRegs_X86AMode(m, i->Xin.SseLdSt.addr); |
| 1472 | break; |
sewardj | 129b3d9 | 2004-12-05 15:42:05 +0000 | [diff] [blame] | 1473 | case Xin_SseLdzLO: |
| 1474 | mapReg(m, &i->Xin.SseLdzLO.reg); |
| 1475 | mapRegs_X86AMode(m, i->Xin.SseLdzLO.addr); |
| 1476 | break; |
sewardj | d08f2d7 | 2004-12-01 23:19:36 +0000 | [diff] [blame] | 1477 | case Xin_Sse32Fx4: |
| 1478 | mapReg(m, &i->Xin.Sse32Fx4.src); |
| 1479 | mapReg(m, &i->Xin.Sse32Fx4.dst); |
| 1480 | return; |
sewardj | 1e6ad74 | 2004-12-02 16:16:11 +0000 | [diff] [blame] | 1481 | case Xin_Sse32FLo: |
| 1482 | mapReg(m, &i->Xin.Sse32FLo.src); |
| 1483 | mapReg(m, &i->Xin.Sse32FLo.dst); |
| 1484 | return; |
sewardj | 636ad76 | 2004-12-07 11:16:04 +0000 | [diff] [blame] | 1485 | case Xin_Sse64Fx2: |
| 1486 | mapReg(m, &i->Xin.Sse64Fx2.src); |
| 1487 | mapReg(m, &i->Xin.Sse64Fx2.dst); |
| 1488 | return; |
| 1489 | case Xin_Sse64FLo: |
| 1490 | mapReg(m, &i->Xin.Sse64FLo.src); |
| 1491 | mapReg(m, &i->Xin.Sse64FLo.dst); |
| 1492 | return; |
sewardj | 164f927 | 2004-12-09 00:39:32 +0000 | [diff] [blame] | 1493 | case Xin_SseReRg: |
| 1494 | mapReg(m, &i->Xin.SseReRg.src); |
| 1495 | mapReg(m, &i->Xin.SseReRg.dst); |
| 1496 | return; |
sewardj | b9fa69b | 2004-12-09 23:25:14 +0000 | [diff] [blame] | 1497 | case Xin_SseCMov: |
| 1498 | mapReg(m, &i->Xin.SseCMov.src); |
| 1499 | mapReg(m, &i->Xin.SseCMov.dst); |
| 1500 | return; |
sewardj | 109ffdb | 2004-12-10 21:45:38 +0000 | [diff] [blame] | 1501 | case Xin_SseShuf: |
| 1502 | mapReg(m, &i->Xin.SseShuf.src); |
| 1503 | mapReg(m, &i->Xin.SseShuf.dst); |
| 1504 | return; |
sewardj | 53f85a9 | 2004-07-02 13:45:17 +0000 | [diff] [blame] | 1505 | default: |
cerion | 92b6436 | 2005-12-13 12:02:26 +0000 | [diff] [blame] | 1506 | ppX86Instr(i, mode64); |
sewardj | 35421a3 | 2004-07-05 13:12:34 +0000 | [diff] [blame] | 1507 | vpanic("mapRegs_X86Instr"); |
sewardj | 53f85a9 | 2004-07-02 13:45:17 +0000 | [diff] [blame] | 1508 | } |
| 1509 | } |
| 1510 | |
sewardj | bb53f8c | 2004-08-14 11:50:01 +0000 | [diff] [blame] | 1511 | /* Figure out if i represents a reg-reg move, and if so assign the |
| 1512 | source and destination to *src and *dst. If in doubt say No. Used |
| 1513 | by the register allocator to do move coalescing. |
| 1514 | */ |
sewardj | a9a0cd2 | 2004-07-03 14:49:41 +0000 | [diff] [blame] | 1515 | Bool isMove_X86Instr ( X86Instr* i, HReg* src, HReg* dst ) |
| 1516 | { |
sewardj | bb53f8c | 2004-08-14 11:50:01 +0000 | [diff] [blame] | 1517 | /* Moves between integer regs */ |
| 1518 | if (i->tag == Xin_Alu32R) { |
| 1519 | if (i->Xin.Alu32R.op != Xalu_MOV) |
| 1520 | return False; |
| 1521 | if (i->Xin.Alu32R.src->tag != Xrmi_Reg) |
| 1522 | return False; |
| 1523 | *src = i->Xin.Alu32R.src->Xrmi.Reg.reg; |
| 1524 | *dst = i->Xin.Alu32R.dst; |
| 1525 | return True; |
| 1526 | } |
| 1527 | /* Moves between FP regs */ |
| 1528 | if (i->tag == Xin_FpUnary) { |
| 1529 | if (i->Xin.FpUnary.op != Xfp_MOV) |
| 1530 | return False; |
| 1531 | *src = i->Xin.FpUnary.src; |
| 1532 | *dst = i->Xin.FpUnary.dst; |
| 1533 | return True; |
| 1534 | } |
sewardj | 9e20359 | 2004-12-10 01:48:18 +0000 | [diff] [blame] | 1535 | if (i->tag == Xin_SseReRg) { |
| 1536 | if (i->Xin.SseReRg.op != Xsse_MOV) |
sewardj | d08f2d7 | 2004-12-01 23:19:36 +0000 | [diff] [blame] | 1537 | return False; |
sewardj | 9e20359 | 2004-12-10 01:48:18 +0000 | [diff] [blame] | 1538 | *src = i->Xin.SseReRg.src; |
| 1539 | *dst = i->Xin.SseReRg.dst; |
sewardj | d08f2d7 | 2004-12-01 23:19:36 +0000 | [diff] [blame] | 1540 | return True; |
| 1541 | } |
sewardj | bb53f8c | 2004-08-14 11:50:01 +0000 | [diff] [blame] | 1542 | return False; |
sewardj | a9a0cd2 | 2004-07-03 14:49:41 +0000 | [diff] [blame] | 1543 | } |
sewardj | 194d54a | 2004-07-03 19:08:18 +0000 | [diff] [blame] | 1544 | |
sewardj | bb53f8c | 2004-08-14 11:50:01 +0000 | [diff] [blame] | 1545 | |
sewardj | 81ec418 | 2004-10-25 23:15:52 +0000 | [diff] [blame] | 1546 | /* Generate x86 spill/reload instructions under the direction of the |
sewardj | 4b861de | 2004-11-03 15:24:42 +0000 | [diff] [blame] | 1547 | register allocator. Note it's critical these don't write the |
| 1548 | condition codes. */ |
sewardj | 14731f2 | 2004-07-25 01:24:28 +0000 | [diff] [blame] | 1549 | |
cerion | 92b6436 | 2005-12-13 12:02:26 +0000 | [diff] [blame] | 1550 | X86Instr* genSpill_X86 ( HReg rreg, Int offsetB, Bool mode64 ) |
sewardj | 194d54a | 2004-07-03 19:08:18 +0000 | [diff] [blame] | 1551 | { |
sewardj | 3f57c2d | 2004-10-04 09:14:05 +0000 | [diff] [blame] | 1552 | X86AMode* am; |
sewardj | 81ec418 | 2004-10-25 23:15:52 +0000 | [diff] [blame] | 1553 | vassert(offsetB >= 0); |
sewardj | 35421a3 | 2004-07-05 13:12:34 +0000 | [diff] [blame] | 1554 | vassert(!hregIsVirtual(rreg)); |
cerion | 92b6436 | 2005-12-13 12:02:26 +0000 | [diff] [blame] | 1555 | vassert(mode64 == False); |
sewardj | 81ec418 | 2004-10-25 23:15:52 +0000 | [diff] [blame] | 1556 | am = X86AMode_IR(offsetB, hregX86_EBP()); |
sewardj | 3f57c2d | 2004-10-04 09:14:05 +0000 | [diff] [blame] | 1557 | |
sewardj | 194d54a | 2004-07-03 19:08:18 +0000 | [diff] [blame] | 1558 | switch (hregClass(rreg)) { |
sewardj | 4a31b26 | 2004-12-01 02:24:44 +0000 | [diff] [blame] | 1559 | case HRcInt32: |
sewardj | 3f57c2d | 2004-10-04 09:14:05 +0000 | [diff] [blame] | 1560 | return X86Instr_Alu32M ( Xalu_MOV, X86RI_Reg(rreg), am ); |
sewardj | 4a31b26 | 2004-12-01 02:24:44 +0000 | [diff] [blame] | 1561 | case HRcFlt64: |
sewardj | 3f57c2d | 2004-10-04 09:14:05 +0000 | [diff] [blame] | 1562 | return X86Instr_FpLdSt ( False/*store*/, 8, rreg, am ); |
sewardj | 9ee8286 | 2004-12-14 01:16:59 +0000 | [diff] [blame] | 1563 | case HRcVec128: |
| 1564 | return X86Instr_SseLdSt ( False/*store*/, rreg, am ); |
sewardj | 194d54a | 2004-07-03 19:08:18 +0000 | [diff] [blame] | 1565 | default: |
sewardj | 35421a3 | 2004-07-05 13:12:34 +0000 | [diff] [blame] | 1566 | ppHRegClass(hregClass(rreg)); |
| 1567 | vpanic("genSpill_X86: unimplemented regclass"); |
sewardj | 194d54a | 2004-07-03 19:08:18 +0000 | [diff] [blame] | 1568 | } |
| 1569 | } |
| 1570 | |
cerion | 92b6436 | 2005-12-13 12:02:26 +0000 | [diff] [blame] | 1571 | X86Instr* genReload_X86 ( HReg rreg, Int offsetB, Bool mode64 ) |
sewardj | 194d54a | 2004-07-03 19:08:18 +0000 | [diff] [blame] | 1572 | { |
sewardj | 3f57c2d | 2004-10-04 09:14:05 +0000 | [diff] [blame] | 1573 | X86AMode* am; |
sewardj | 81ec418 | 2004-10-25 23:15:52 +0000 | [diff] [blame] | 1574 | vassert(offsetB >= 0); |
sewardj | 35421a3 | 2004-07-05 13:12:34 +0000 | [diff] [blame] | 1575 | vassert(!hregIsVirtual(rreg)); |
cerion | 92b6436 | 2005-12-13 12:02:26 +0000 | [diff] [blame] | 1576 | vassert(mode64 == False); |
sewardj | 81ec418 | 2004-10-25 23:15:52 +0000 | [diff] [blame] | 1577 | am = X86AMode_IR(offsetB, hregX86_EBP()); |
sewardj | 194d54a | 2004-07-03 19:08:18 +0000 | [diff] [blame] | 1578 | switch (hregClass(rreg)) { |
sewardj | 4a31b26 | 2004-12-01 02:24:44 +0000 | [diff] [blame] | 1579 | case HRcInt32: |
sewardj | 3f57c2d | 2004-10-04 09:14:05 +0000 | [diff] [blame] | 1580 | return X86Instr_Alu32R ( Xalu_MOV, X86RMI_Mem(am), rreg ); |
sewardj | 4a31b26 | 2004-12-01 02:24:44 +0000 | [diff] [blame] | 1581 | case HRcFlt64: |
sewardj | 3f57c2d | 2004-10-04 09:14:05 +0000 | [diff] [blame] | 1582 | return X86Instr_FpLdSt ( True/*load*/, 8, rreg, am ); |
sewardj | 9ee8286 | 2004-12-14 01:16:59 +0000 | [diff] [blame] | 1583 | case HRcVec128: |
| 1584 | return X86Instr_SseLdSt ( True/*load*/, rreg, am ); |
sewardj | 194d54a | 2004-07-03 19:08:18 +0000 | [diff] [blame] | 1585 | default: |
sewardj | 35421a3 | 2004-07-05 13:12:34 +0000 | [diff] [blame] | 1586 | ppHRegClass(hregClass(rreg)); |
| 1587 | vpanic("genReload_X86: unimplemented regclass"); |
sewardj | 194d54a | 2004-07-03 19:08:18 +0000 | [diff] [blame] | 1588 | } |
| 1589 | } |
sewardj | 35421a3 | 2004-07-05 13:12:34 +0000 | [diff] [blame] | 1590 | |
sewardj | 81bd550 | 2004-07-21 18:49:27 +0000 | [diff] [blame] | 1591 | |
| 1592 | /* --------- The x86 assembler (bleh.) --------- */ |
| 1593 | |
sewardj | 8ee8c88 | 2005-02-25 17:40:26 +0000 | [diff] [blame] | 1594 | static UChar iregNo ( HReg r ) |
sewardj | bad34a9 | 2004-07-22 01:14:11 +0000 | [diff] [blame] | 1595 | { |
| 1596 | UInt n; |
sewardj | 4a31b26 | 2004-12-01 02:24:44 +0000 | [diff] [blame] | 1597 | vassert(hregClass(r) == HRcInt32); |
sewardj | bad34a9 | 2004-07-22 01:14:11 +0000 | [diff] [blame] | 1598 | vassert(!hregIsVirtual(r)); |
| 1599 | n = hregNumber(r); |
| 1600 | vassert(n <= 7); |
sewardj | 8ee8c88 | 2005-02-25 17:40:26 +0000 | [diff] [blame] | 1601 | return toUChar(n); |
sewardj | bad34a9 | 2004-07-22 01:14:11 +0000 | [diff] [blame] | 1602 | } |
| 1603 | |
sewardj | 140656d | 2004-08-22 02:37:25 +0000 | [diff] [blame] | 1604 | static UInt fregNo ( HReg r ) |
| 1605 | { |
| 1606 | UInt n; |
sewardj | 4a31b26 | 2004-12-01 02:24:44 +0000 | [diff] [blame] | 1607 | vassert(hregClass(r) == HRcFlt64); |
sewardj | 140656d | 2004-08-22 02:37:25 +0000 | [diff] [blame] | 1608 | vassert(!hregIsVirtual(r)); |
| 1609 | n = hregNumber(r); |
sewardj | eafde5a | 2004-10-09 01:36:57 +0000 | [diff] [blame] | 1610 | vassert(n <= 5); |
sewardj | 140656d | 2004-08-22 02:37:25 +0000 | [diff] [blame] | 1611 | return n; |
| 1612 | } |
| 1613 | |
sewardj | d08f2d7 | 2004-12-01 23:19:36 +0000 | [diff] [blame] | 1614 | static UInt vregNo ( HReg r ) |
| 1615 | { |
| 1616 | UInt n; |
| 1617 | vassert(hregClass(r) == HRcVec128); |
| 1618 | vassert(!hregIsVirtual(r)); |
| 1619 | n = hregNumber(r); |
| 1620 | vassert(n <= 7); |
| 1621 | return n; |
| 1622 | } |
| 1623 | |
sewardj | bad34a9 | 2004-07-22 01:14:11 +0000 | [diff] [blame] | 1624 | static UChar mkModRegRM ( UChar mod, UChar reg, UChar regmem ) |
| 1625 | { |
sewardj | 8ee8c88 | 2005-02-25 17:40:26 +0000 | [diff] [blame] | 1626 | return toUChar( ((mod & 3) << 6) |
| 1627 | | ((reg & 7) << 3) |
| 1628 | | (regmem & 7) ); |
sewardj | bad34a9 | 2004-07-22 01:14:11 +0000 | [diff] [blame] | 1629 | } |
| 1630 | |
| 1631 | static UChar mkSIB ( Int shift, Int regindex, Int regbase ) |
| 1632 | { |
sewardj | 8ee8c88 | 2005-02-25 17:40:26 +0000 | [diff] [blame] | 1633 | return toUChar( ((shift & 3) << 6) |
| 1634 | | ((regindex & 7) << 3) |
| 1635 | | (regbase & 7) ); |
sewardj | bad34a9 | 2004-07-22 01:14:11 +0000 | [diff] [blame] | 1636 | } |
| 1637 | |
| 1638 | static UChar* emit32 ( UChar* p, UInt w32 ) |
| 1639 | { |
sewardj | 8ee8c88 | 2005-02-25 17:40:26 +0000 | [diff] [blame] | 1640 | *p++ = toUChar( w32 & 0x000000FF); |
| 1641 | *p++ = toUChar((w32 >> 8) & 0x000000FF); |
| 1642 | *p++ = toUChar((w32 >> 16) & 0x000000FF); |
| 1643 | *p++ = toUChar((w32 >> 24) & 0x000000FF); |
sewardj | bad34a9 | 2004-07-22 01:14:11 +0000 | [diff] [blame] | 1644 | return p; |
| 1645 | } |
| 1646 | |
sewardj | ea64e14 | 2004-07-22 16:47:21 +0000 | [diff] [blame] | 1647 | /* Does a sign-extend of the lowest 8 bits give |
| 1648 | the original number? */ |
sewardj | bad34a9 | 2004-07-22 01:14:11 +0000 | [diff] [blame] | 1649 | static Bool fits8bits ( UInt w32 ) |
| 1650 | { |
sewardj | ea64e14 | 2004-07-22 16:47:21 +0000 | [diff] [blame] | 1651 | Int i32 = (Int)w32; |
sewardj | 8ee8c88 | 2005-02-25 17:40:26 +0000 | [diff] [blame] | 1652 | return toBool(i32 == ((i32 << 24) >> 24)); |
sewardj | bad34a9 | 2004-07-22 01:14:11 +0000 | [diff] [blame] | 1653 | } |
| 1654 | |
| 1655 | |
| 1656 | /* Forming mod-reg-rm bytes and scale-index-base bytes. |
| 1657 | |
| 1658 | greg, 0(ereg) | ereg != ESP && ereg != EBP |
| 1659 | = 00 greg ereg |
| 1660 | |
| 1661 | greg, d8(ereg) | ereg != ESP |
| 1662 | = 01 greg ereg, d8 |
| 1663 | |
| 1664 | greg, d32(ereg) | ereg != ESP |
| 1665 | = 10 greg ereg, d32 |
| 1666 | |
sewardj | a58ea66 | 2004-08-15 03:12:41 +0000 | [diff] [blame] | 1667 | greg, d8(%esp) = 01 greg 100, 0x24, d8 |
| 1668 | |
sewardj | bad34a9 | 2004-07-22 01:14:11 +0000 | [diff] [blame] | 1669 | ----------------------------------------------- |
| 1670 | |
| 1671 | greg, d8(base,index,scale) |
| 1672 | | index != ESP |
| 1673 | = 01 greg 100, scale index base, d8 |
| 1674 | |
| 1675 | greg, d32(base,index,scale) |
| 1676 | | index != ESP |
| 1677 | = 10 greg 100, scale index base, d32 |
| 1678 | */ |
| 1679 | static UChar* doAMode_M ( UChar* p, HReg greg, X86AMode* am ) |
| 1680 | { |
| 1681 | if (am->tag == Xam_IR) { |
| 1682 | if (am->Xam.IR.imm == 0 |
| 1683 | && am->Xam.IR.reg != hregX86_ESP() |
| 1684 | && am->Xam.IR.reg != hregX86_EBP() ) { |
| 1685 | *p++ = mkModRegRM(0, iregNo(greg), iregNo(am->Xam.IR.reg)); |
| 1686 | return p; |
| 1687 | } |
| 1688 | if (fits8bits(am->Xam.IR.imm) |
| 1689 | && am->Xam.IR.reg != hregX86_ESP()) { |
| 1690 | *p++ = mkModRegRM(1, iregNo(greg), iregNo(am->Xam.IR.reg)); |
sewardj | 8ee8c88 | 2005-02-25 17:40:26 +0000 | [diff] [blame] | 1691 | *p++ = toUChar(am->Xam.IR.imm & 0xFF); |
sewardj | bad34a9 | 2004-07-22 01:14:11 +0000 | [diff] [blame] | 1692 | return p; |
| 1693 | } |
| 1694 | if (am->Xam.IR.reg != hregX86_ESP()) { |
| 1695 | *p++ = mkModRegRM(2, iregNo(greg), iregNo(am->Xam.IR.reg)); |
| 1696 | p = emit32(p, am->Xam.IR.imm); |
| 1697 | return p; |
| 1698 | } |
sewardj | a58ea66 | 2004-08-15 03:12:41 +0000 | [diff] [blame] | 1699 | if (am->Xam.IR.reg == hregX86_ESP() |
| 1700 | && fits8bits(am->Xam.IR.imm)) { |
| 1701 | *p++ = mkModRegRM(1, iregNo(greg), 4); |
| 1702 | *p++ = 0x24; |
sewardj | 8ee8c88 | 2005-02-25 17:40:26 +0000 | [diff] [blame] | 1703 | *p++ = toUChar(am->Xam.IR.imm & 0xFF); |
sewardj | a58ea66 | 2004-08-15 03:12:41 +0000 | [diff] [blame] | 1704 | return p; |
| 1705 | } |
sewardj | bad34a9 | 2004-07-22 01:14:11 +0000 | [diff] [blame] | 1706 | ppX86AMode(am); |
| 1707 | vpanic("doAMode_M: can't emit amode IR"); |
| 1708 | /*NOTREACHED*/ |
| 1709 | } |
| 1710 | if (am->tag == Xam_IRRS) { |
| 1711 | if (fits8bits(am->Xam.IRRS.imm) |
| 1712 | && am->Xam.IRRS.index != hregX86_ESP()) { |
| 1713 | *p++ = mkModRegRM(1, iregNo(greg), 4); |
| 1714 | *p++ = mkSIB(am->Xam.IRRS.shift, am->Xam.IRRS.index, |
| 1715 | am->Xam.IRRS.base); |
sewardj | 8ee8c88 | 2005-02-25 17:40:26 +0000 | [diff] [blame] | 1716 | *p++ = toUChar(am->Xam.IRRS.imm & 0xFF); |
sewardj | bad34a9 | 2004-07-22 01:14:11 +0000 | [diff] [blame] | 1717 | return p; |
| 1718 | } |
| 1719 | if (am->Xam.IRRS.index != hregX86_ESP()) { |
| 1720 | *p++ = mkModRegRM(2, iregNo(greg), 4); |
| 1721 | *p++ = mkSIB(am->Xam.IRRS.shift, am->Xam.IRRS.index, |
| 1722 | am->Xam.IRRS.base); |
| 1723 | p = emit32(p, am->Xam.IRRS.imm); |
| 1724 | return p; |
| 1725 | } |
| 1726 | ppX86AMode(am); |
| 1727 | vpanic("doAMode_M: can't emit amode IRRS"); |
| 1728 | /*NOTREACHED*/ |
| 1729 | } |
| 1730 | vpanic("doAMode_M: unknown amode"); |
| 1731 | /*NOTREACHED*/ |
| 1732 | } |
| 1733 | |
| 1734 | |
| 1735 | /* Emit a mod-reg-rm byte when the rm bit denotes a reg. */ |
| 1736 | static UChar* doAMode_R ( UChar* p, HReg greg, HReg ereg ) |
| 1737 | { |
| 1738 | *p++ = mkModRegRM(3, iregNo(greg), iregNo(ereg)); |
| 1739 | return p; |
| 1740 | } |
| 1741 | |
| 1742 | |
sewardj | 3196daf | 2004-08-13 00:18:58 +0000 | [diff] [blame] | 1743 | /* Emit ffree %st(7) */ |
| 1744 | static UChar* do_ffree_st7 ( UChar* p ) |
| 1745 | { |
| 1746 | *p++ = 0xDD; |
| 1747 | *p++ = 0xC7; |
| 1748 | return p; |
| 1749 | } |
| 1750 | |
sewardj | eafde5a | 2004-10-09 01:36:57 +0000 | [diff] [blame] | 1751 | /* Emit fstp %st(i), 1 <= i <= 7 */ |
sewardj | 3196daf | 2004-08-13 00:18:58 +0000 | [diff] [blame] | 1752 | static UChar* do_fstp_st ( UChar* p, Int i ) |
| 1753 | { |
sewardj | eafde5a | 2004-10-09 01:36:57 +0000 | [diff] [blame] | 1754 | vassert(1 <= i && i <= 7); |
sewardj | 3196daf | 2004-08-13 00:18:58 +0000 | [diff] [blame] | 1755 | *p++ = 0xDD; |
sewardj | 8ee8c88 | 2005-02-25 17:40:26 +0000 | [diff] [blame] | 1756 | *p++ = toUChar(0xD8+i); |
sewardj | 3196daf | 2004-08-13 00:18:58 +0000 | [diff] [blame] | 1757 | return p; |
| 1758 | } |
| 1759 | |
sewardj | b3944c2 | 2004-10-15 22:22:09 +0000 | [diff] [blame] | 1760 | /* Emit fld %st(i), 0 <= i <= 6 */ |
sewardj | 3196daf | 2004-08-13 00:18:58 +0000 | [diff] [blame] | 1761 | static UChar* do_fld_st ( UChar* p, Int i ) |
| 1762 | { |
sewardj | b3944c2 | 2004-10-15 22:22:09 +0000 | [diff] [blame] | 1763 | vassert(0 <= i && i <= 6); |
sewardj | 3196daf | 2004-08-13 00:18:58 +0000 | [diff] [blame] | 1764 | *p++ = 0xD9; |
sewardj | 8ee8c88 | 2005-02-25 17:40:26 +0000 | [diff] [blame] | 1765 | *p++ = toUChar(0xC0+i); |
sewardj | 3196daf | 2004-08-13 00:18:58 +0000 | [diff] [blame] | 1766 | return p; |
| 1767 | } |
| 1768 | |
sewardj | cfded9a | 2004-09-09 11:44:16 +0000 | [diff] [blame] | 1769 | /* Emit f<op> %st(0) */ |
| 1770 | static UChar* do_fop1_st ( UChar* p, X86FpOp op ) |
| 1771 | { |
| 1772 | switch (op) { |
sewardj | 883b00b | 2004-09-11 09:30:24 +0000 | [diff] [blame] | 1773 | case Xfp_NEG: *p++ = 0xD9; *p++ = 0xE0; break; |
| 1774 | case Xfp_ABS: *p++ = 0xD9; *p++ = 0xE1; break; |
sewardj | c4be80c | 2004-09-10 16:17:45 +0000 | [diff] [blame] | 1775 | case Xfp_SQRT: *p++ = 0xD9; *p++ = 0xFA; break; |
sewardj | e670911 | 2004-09-10 18:37:18 +0000 | [diff] [blame] | 1776 | case Xfp_ROUND: *p++ = 0xD9; *p++ = 0xFC; break; |
sewardj | cfded9a | 2004-09-09 11:44:16 +0000 | [diff] [blame] | 1777 | case Xfp_SIN: *p++ = 0xD9; *p++ = 0xFE; break; |
| 1778 | case Xfp_COS: *p++ = 0xD9; *p++ = 0xFF; break; |
sewardj | 06c32a0 | 2004-09-12 12:07:34 +0000 | [diff] [blame] | 1779 | case Xfp_2XM1: *p++ = 0xD9; *p++ = 0xF0; break; |
sewardj | bec1084 | 2004-10-12 13:44:45 +0000 | [diff] [blame] | 1780 | case Xfp_MOV: break; |
sewardj | 99016a7 | 2004-10-15 22:09:17 +0000 | [diff] [blame] | 1781 | case Xfp_TAN: p = do_ffree_st7(p); /* since fptan pushes 1.0 */ |
| 1782 | *p++ = 0xD9; *p++ = 0xF2; /* fptan */ |
| 1783 | *p++ = 0xD9; *p++ = 0xF7; /* fincstp */ |
| 1784 | break; |
sewardj | cfded9a | 2004-09-09 11:44:16 +0000 | [diff] [blame] | 1785 | default: vpanic("do_fop1_st: unknown op"); |
| 1786 | } |
| 1787 | return p; |
| 1788 | } |
| 1789 | |
sewardj | bb53f8c | 2004-08-14 11:50:01 +0000 | [diff] [blame] | 1790 | /* Emit f<op> %st(i), 1 <= i <= 5 */ |
sewardj | cfded9a | 2004-09-09 11:44:16 +0000 | [diff] [blame] | 1791 | static UChar* do_fop2_st ( UChar* p, X86FpOp op, Int i ) |
sewardj | bb53f8c | 2004-08-14 11:50:01 +0000 | [diff] [blame] | 1792 | { |
sewardj | 4a31b26 | 2004-12-01 02:24:44 +0000 | [diff] [blame] | 1793 | # define fake(_n) mkHReg((_n), HRcInt32, False) |
sewardj | bb53f8c | 2004-08-14 11:50:01 +0000 | [diff] [blame] | 1794 | Int subopc; |
| 1795 | switch (op) { |
sewardj | a58ea66 | 2004-08-15 03:12:41 +0000 | [diff] [blame] | 1796 | case Xfp_ADD: subopc = 0; break; |
sewardj | ce646f2 | 2004-08-31 23:55:54 +0000 | [diff] [blame] | 1797 | case Xfp_SUB: subopc = 4; break; |
sewardj | bb53f8c | 2004-08-14 11:50:01 +0000 | [diff] [blame] | 1798 | case Xfp_MUL: subopc = 1; break; |
sewardj | ce646f2 | 2004-08-31 23:55:54 +0000 | [diff] [blame] | 1799 | case Xfp_DIV: subopc = 6; break; |
sewardj | cfded9a | 2004-09-09 11:44:16 +0000 | [diff] [blame] | 1800 | default: vpanic("do_fop2_st: unknown op"); |
sewardj | bb53f8c | 2004-08-14 11:50:01 +0000 | [diff] [blame] | 1801 | } |
| 1802 | *p++ = 0xD8; |
| 1803 | p = doAMode_R(p, fake(subopc), fake(i)); |
| 1804 | return p; |
| 1805 | # undef fake |
| 1806 | } |
sewardj | bad34a9 | 2004-07-22 01:14:11 +0000 | [diff] [blame] | 1807 | |
sewardj | 1e6ad74 | 2004-12-02 16:16:11 +0000 | [diff] [blame] | 1808 | /* Push a 32-bit word on the stack. The word depends on tags[3:0]; |
| 1809 | each byte is either 0x00 or 0xFF depending on the corresponding bit in tags[]. |
| 1810 | */ |
| 1811 | static UChar* push_word_from_tags ( UChar* p, UShort tags ) |
| 1812 | { |
| 1813 | UInt w; |
| 1814 | vassert(0 == (tags & ~0xF)); |
| 1815 | if (tags == 0) { |
| 1816 | /* pushl $0x00000000 */ |
| 1817 | *p++ = 0x6A; |
| 1818 | *p++ = 0x00; |
| 1819 | } |
| 1820 | else |
| 1821 | /* pushl $0xFFFFFFFF */ |
| 1822 | if (tags == 0xF) { |
| 1823 | *p++ = 0x6A; |
| 1824 | *p++ = 0xFF; |
| 1825 | } else { |
| 1826 | vassert(0); /* awaiting test case */ |
| 1827 | w = 0; |
| 1828 | if (tags & 1) w |= 0x000000FF; |
| 1829 | if (tags & 2) w |= 0x0000FF00; |
| 1830 | if (tags & 4) w |= 0x00FF0000; |
| 1831 | if (tags & 8) w |= 0xFF000000; |
| 1832 | *p++ = 0x68; |
| 1833 | p = emit32(p, w); |
| 1834 | } |
| 1835 | return p; |
| 1836 | } |
| 1837 | |
sewardj | 81bd550 | 2004-07-21 18:49:27 +0000 | [diff] [blame] | 1838 | /* Emit an instruction into buf and return the number of bytes used. |
| 1839 | Note that buf is not the insn's final place, and therefore it is |
| 1840 | imperative to emit position-independent code. */ |
| 1841 | |
sewardj | 17c7f95 | 2005-12-15 14:02:34 +0000 | [diff] [blame^] | 1842 | Int emit_X86Instr ( UChar* buf, Int nbuf, X86Instr* i, |
| 1843 | Bool mode64, void* dispatch ) |
sewardj | 81bd550 | 2004-07-21 18:49:27 +0000 | [diff] [blame] | 1844 | { |
sewardj | 4b861de | 2004-11-03 15:24:42 +0000 | [diff] [blame] | 1845 | UInt irno, opc, opc_rr, subopc_imm, opc_imma, opc_cl, opc_imm, subopc; |
sewardj | ea64e14 | 2004-07-22 16:47:21 +0000 | [diff] [blame] | 1846 | |
sewardj | 1e6ad74 | 2004-12-02 16:16:11 +0000 | [diff] [blame] | 1847 | UInt xtra; |
sewardj | bad34a9 | 2004-07-22 01:14:11 +0000 | [diff] [blame] | 1848 | UChar* p = &buf[0]; |
sewardj | 750f407 | 2004-07-26 22:39:11 +0000 | [diff] [blame] | 1849 | UChar* ptmp; |
sewardj | bad34a9 | 2004-07-22 01:14:11 +0000 | [diff] [blame] | 1850 | vassert(nbuf >= 32); |
cerion | 92b6436 | 2005-12-13 12:02:26 +0000 | [diff] [blame] | 1851 | vassert(mode64 == False); |
sewardj | bad34a9 | 2004-07-22 01:14:11 +0000 | [diff] [blame] | 1852 | |
sewardj | ea64e14 | 2004-07-22 16:47:21 +0000 | [diff] [blame] | 1853 | /* Wrap an integer as a int register, for use assembling |
| 1854 | GrpN insns, in which the greg field is used as a sub-opcode |
| 1855 | and does not really contain a register. */ |
sewardj | 4a31b26 | 2004-12-01 02:24:44 +0000 | [diff] [blame] | 1856 | # define fake(_n) mkHReg((_n), HRcInt32, False) |
sewardj | ea64e14 | 2004-07-22 16:47:21 +0000 | [diff] [blame] | 1857 | |
cerion | 92b6436 | 2005-12-13 12:02:26 +0000 | [diff] [blame] | 1858 | /* vex_printf("asm ");ppX86Instr(i, mode64); vex_printf("\n"); */ |
sewardj | bec1084 | 2004-10-12 13:44:45 +0000 | [diff] [blame] | 1859 | |
sewardj | 81bd550 | 2004-07-21 18:49:27 +0000 | [diff] [blame] | 1860 | switch (i->tag) { |
sewardj | bad34a9 | 2004-07-22 01:14:11 +0000 | [diff] [blame] | 1861 | |
| 1862 | case Xin_Alu32R: |
sewardj | ea64e14 | 2004-07-22 16:47:21 +0000 | [diff] [blame] | 1863 | /* Deal specially with MOV */ |
sewardj | bad34a9 | 2004-07-22 01:14:11 +0000 | [diff] [blame] | 1864 | if (i->Xin.Alu32R.op == Xalu_MOV) { |
| 1865 | switch (i->Xin.Alu32R.src->tag) { |
sewardj | ea64e14 | 2004-07-22 16:47:21 +0000 | [diff] [blame] | 1866 | case Xrmi_Imm: |
sewardj | 8ee8c88 | 2005-02-25 17:40:26 +0000 | [diff] [blame] | 1867 | *p++ = toUChar(0xB8 + iregNo(i->Xin.Alu32R.dst)); |
sewardj | ea64e14 | 2004-07-22 16:47:21 +0000 | [diff] [blame] | 1868 | p = emit32(p, i->Xin.Alu32R.src->Xrmi.Imm.imm32); |
| 1869 | goto done; |
| 1870 | case Xrmi_Reg: |
sewardj | 750f407 | 2004-07-26 22:39:11 +0000 | [diff] [blame] | 1871 | *p++ = 0x89; |
| 1872 | p = doAMode_R(p, i->Xin.Alu32R.src->Xrmi.Reg.reg, |
| 1873 | i->Xin.Alu32R.dst); |
| 1874 | goto done; |
sewardj | ea64e14 | 2004-07-22 16:47:21 +0000 | [diff] [blame] | 1875 | case Xrmi_Mem: |
| 1876 | *p++ = 0x8B; |
| 1877 | p = doAMode_M(p, i->Xin.Alu32R.dst, |
| 1878 | i->Xin.Alu32R.src->Xrmi.Mem.am); |
| 1879 | goto done; |
| 1880 | default: |
| 1881 | goto bad; |
| 1882 | } |
| 1883 | } |
sewardj | e8c922f | 2004-07-23 01:34:11 +0000 | [diff] [blame] | 1884 | /* MUL */ |
| 1885 | if (i->Xin.Alu32R.op == Xalu_MUL) { |
sewardj | d75fe5a | 2004-07-23 12:57:47 +0000 | [diff] [blame] | 1886 | switch (i->Xin.Alu32R.src->tag) { |
| 1887 | case Xrmi_Reg: |
| 1888 | *p++ = 0x0F; |
| 1889 | *p++ = 0xAF; |
| 1890 | p = doAMode_R(p, i->Xin.Alu32R.dst, |
| 1891 | i->Xin.Alu32R.src->Xrmi.Reg.reg); |
| 1892 | goto done; |
sewardj | 140656d | 2004-08-22 02:37:25 +0000 | [diff] [blame] | 1893 | case Xrmi_Mem: |
| 1894 | *p++ = 0x0F; |
| 1895 | *p++ = 0xAF; |
| 1896 | p = doAMode_M(p, i->Xin.Alu32R.dst, |
| 1897 | i->Xin.Alu32R.src->Xrmi.Mem.am); |
| 1898 | goto done; |
sewardj | d75fe5a | 2004-07-23 12:57:47 +0000 | [diff] [blame] | 1899 | case Xrmi_Imm: |
| 1900 | if (fits8bits(i->Xin.Alu32R.src->Xrmi.Imm.imm32)) { |
| 1901 | *p++ = 0x6B; |
| 1902 | p = doAMode_R(p, i->Xin.Alu32R.dst, i->Xin.Alu32R.dst); |
sewardj | 8ee8c88 | 2005-02-25 17:40:26 +0000 | [diff] [blame] | 1903 | *p++ = toUChar(0xFF & i->Xin.Alu32R.src->Xrmi.Imm.imm32); |
sewardj | d75fe5a | 2004-07-23 12:57:47 +0000 | [diff] [blame] | 1904 | } else { |
sewardj | 278c44c | 2004-08-20 00:28:13 +0000 | [diff] [blame] | 1905 | *p++ = 0x69; |
| 1906 | p = doAMode_R(p, i->Xin.Alu32R.dst, i->Xin.Alu32R.dst); |
| 1907 | p = emit32(p, i->Xin.Alu32R.src->Xrmi.Imm.imm32); |
sewardj | d75fe5a | 2004-07-23 12:57:47 +0000 | [diff] [blame] | 1908 | } |
sewardj | 278c44c | 2004-08-20 00:28:13 +0000 | [diff] [blame] | 1909 | goto done; |
sewardj | d75fe5a | 2004-07-23 12:57:47 +0000 | [diff] [blame] | 1910 | default: |
| 1911 | goto bad; |
| 1912 | } |
sewardj | e8c922f | 2004-07-23 01:34:11 +0000 | [diff] [blame] | 1913 | } |
| 1914 | /* ADD/SUB/ADC/SBB/AND/OR/XOR/CMP */ |
sewardj | ea64e14 | 2004-07-22 16:47:21 +0000 | [diff] [blame] | 1915 | opc = opc_rr = subopc_imm = opc_imma = 0; |
| 1916 | switch (i->Xin.Alu32R.op) { |
sewardj | d3f9de7 | 2005-01-15 20:43:10 +0000 | [diff] [blame] | 1917 | case Xalu_ADC: opc = 0x13; opc_rr = 0x11; |
| 1918 | subopc_imm = 2; opc_imma = 0x15; break; |
sewardj | ea64e14 | 2004-07-22 16:47:21 +0000 | [diff] [blame] | 1919 | case Xalu_ADD: opc = 0x03; opc_rr = 0x01; |
| 1920 | subopc_imm = 0; opc_imma = 0x05; break; |
| 1921 | case Xalu_SUB: opc = 0x2B; opc_rr = 0x29; |
| 1922 | subopc_imm = 5; opc_imma = 0x2D; break; |
sewardj | 70f676d | 2004-12-10 14:59:57 +0000 | [diff] [blame] | 1923 | case Xalu_SBB: opc = 0x1B; opc_rr = 0x19; |
| 1924 | subopc_imm = 3; opc_imma = 0x1D; break; |
sewardj | 86898e8 | 2004-07-22 17:26:12 +0000 | [diff] [blame] | 1925 | case Xalu_AND: opc = 0x23; opc_rr = 0x21; |
| 1926 | subopc_imm = 4; opc_imma = 0x25; break; |
sewardj | e8c922f | 2004-07-23 01:34:11 +0000 | [diff] [blame] | 1927 | case Xalu_XOR: opc = 0x33; opc_rr = 0x31; |
| 1928 | subopc_imm = 6; opc_imma = 0x35; break; |
| 1929 | case Xalu_OR: opc = 0x0B; opc_rr = 0x09; |
| 1930 | subopc_imm = 1; opc_imma = 0x0D; break; |
| 1931 | case Xalu_CMP: opc = 0x3B; opc_rr = 0x39; |
| 1932 | subopc_imm = 7; opc_imma = 0x3D; break; |
sewardj | ea64e14 | 2004-07-22 16:47:21 +0000 | [diff] [blame] | 1933 | default: goto bad; |
| 1934 | } |
| 1935 | switch (i->Xin.Alu32R.src->tag) { |
| 1936 | case Xrmi_Imm: |
| 1937 | if (i->Xin.Alu32R.dst == hregX86_EAX() |
| 1938 | && !fits8bits(i->Xin.Alu32R.src->Xrmi.Imm.imm32)) { |
sewardj | 8ee8c88 | 2005-02-25 17:40:26 +0000 | [diff] [blame] | 1939 | *p++ = toUChar(opc_imma); |
sewardj | ea64e14 | 2004-07-22 16:47:21 +0000 | [diff] [blame] | 1940 | p = emit32(p, i->Xin.Alu32R.src->Xrmi.Imm.imm32); |
| 1941 | } else |
sewardj | d3f9de7 | 2005-01-15 20:43:10 +0000 | [diff] [blame] | 1942 | if (fits8bits(i->Xin.Alu32R.src->Xrmi.Imm.imm32)) { |
sewardj | ea64e14 | 2004-07-22 16:47:21 +0000 | [diff] [blame] | 1943 | *p++ = 0x83; |
| 1944 | p = doAMode_R(p, fake(subopc_imm), i->Xin.Alu32R.dst); |
sewardj | 8ee8c88 | 2005-02-25 17:40:26 +0000 | [diff] [blame] | 1945 | *p++ = toUChar(0xFF & i->Xin.Alu32R.src->Xrmi.Imm.imm32); |
sewardj | ea64e14 | 2004-07-22 16:47:21 +0000 | [diff] [blame] | 1946 | } else { |
| 1947 | *p++ = 0x81; |
| 1948 | p = doAMode_R(p, fake(subopc_imm), i->Xin.Alu32R.dst); |
| 1949 | p = emit32(p, i->Xin.Alu32R.src->Xrmi.Imm.imm32); |
| 1950 | } |
| 1951 | goto done; |
| 1952 | case Xrmi_Reg: |
sewardj | 8ee8c88 | 2005-02-25 17:40:26 +0000 | [diff] [blame] | 1953 | *p++ = toUChar(opc_rr); |
sewardj | ea64e14 | 2004-07-22 16:47:21 +0000 | [diff] [blame] | 1954 | p = doAMode_R(p, i->Xin.Alu32R.src->Xrmi.Reg.reg, |
| 1955 | i->Xin.Alu32R.dst); |
| 1956 | goto done; |
sewardj | bad34a9 | 2004-07-22 01:14:11 +0000 | [diff] [blame] | 1957 | case Xrmi_Mem: |
sewardj | 8ee8c88 | 2005-02-25 17:40:26 +0000 | [diff] [blame] | 1958 | *p++ = toUChar(opc); |
sewardj | ea64e14 | 2004-07-22 16:47:21 +0000 | [diff] [blame] | 1959 | p = doAMode_M(p, i->Xin.Alu32R.dst, |
sewardj | bad34a9 | 2004-07-22 01:14:11 +0000 | [diff] [blame] | 1960 | i->Xin.Alu32R.src->Xrmi.Mem.am); |
| 1961 | goto done; |
sewardj | ea64e14 | 2004-07-22 16:47:21 +0000 | [diff] [blame] | 1962 | default: |
sewardj | bad34a9 | 2004-07-22 01:14:11 +0000 | [diff] [blame] | 1963 | goto bad; |
sewardj | bad34a9 | 2004-07-22 01:14:11 +0000 | [diff] [blame] | 1964 | } |
| 1965 | break; |
| 1966 | |
| 1967 | case Xin_Alu32M: |
sewardj | ea64e14 | 2004-07-22 16:47:21 +0000 | [diff] [blame] | 1968 | /* Deal specially with MOV */ |
sewardj | bad34a9 | 2004-07-22 01:14:11 +0000 | [diff] [blame] | 1969 | if (i->Xin.Alu32M.op == Xalu_MOV) { |
sewardj | ea64e14 | 2004-07-22 16:47:21 +0000 | [diff] [blame] | 1970 | switch (i->Xin.Alu32M.src->tag) { |
| 1971 | case Xri_Reg: |
| 1972 | *p++ = 0x89; |
| 1973 | p = doAMode_M(p, i->Xin.Alu32M.src->Xri.Reg.reg, |
| 1974 | i->Xin.Alu32M.dst); |
| 1975 | goto done; |
| 1976 | case Xri_Imm: |
| 1977 | *p++ = 0xC7; |
| 1978 | p = doAMode_M(p, fake(0), i->Xin.Alu32M.dst); |
| 1979 | p = emit32(p, i->Xin.Alu32M.src->Xri.Imm.imm32); |
| 1980 | goto done; |
| 1981 | default: |
| 1982 | goto bad; |
| 1983 | } |
| 1984 | } |
sewardj | e8c922f | 2004-07-23 01:34:11 +0000 | [diff] [blame] | 1985 | /* ADD/SUB/ADC/SBB/AND/OR/XOR/CMP. MUL is not |
| 1986 | allowed here. */ |
sewardj | ea64e14 | 2004-07-22 16:47:21 +0000 | [diff] [blame] | 1987 | opc = subopc_imm = opc_imma = 0; |
| 1988 | switch (i->Xin.Alu32M.op) { |
| 1989 | case Xalu_ADD: opc = 0x01; subopc_imm = 0; break; |
sewardj | 86898e8 | 2004-07-22 17:26:12 +0000 | [diff] [blame] | 1990 | case Xalu_SUB: opc = 0x29; subopc_imm = 5; break; |
sewardj | ea64e14 | 2004-07-22 16:47:21 +0000 | [diff] [blame] | 1991 | default: goto bad; |
| 1992 | } |
| 1993 | switch (i->Xin.Alu32M.src->tag) { |
| 1994 | case Xri_Reg: |
sewardj | 8ee8c88 | 2005-02-25 17:40:26 +0000 | [diff] [blame] | 1995 | *p++ = toUChar(opc); |
sewardj | ea64e14 | 2004-07-22 16:47:21 +0000 | [diff] [blame] | 1996 | p = doAMode_M(p, i->Xin.Alu32M.src->Xri.Reg.reg, |
| 1997 | i->Xin.Alu32M.dst); |
| 1998 | goto done; |
| 1999 | case Xri_Imm: |
| 2000 | if (fits8bits(i->Xin.Alu32M.src->Xri.Imm.imm32)) { |
| 2001 | *p++ = 0x83; |
| 2002 | p = doAMode_M(p, fake(subopc_imm), i->Xin.Alu32M.dst); |
sewardj | 8ee8c88 | 2005-02-25 17:40:26 +0000 | [diff] [blame] | 2003 | *p++ = toUChar(0xFF & i->Xin.Alu32M.src->Xri.Imm.imm32); |
sewardj | ea64e14 | 2004-07-22 16:47:21 +0000 | [diff] [blame] | 2004 | goto done; |
| 2005 | } else { |
| 2006 | *p++ = 0x81; |
| 2007 | p = doAMode_M(p, fake(subopc_imm), i->Xin.Alu32M.dst); |
| 2008 | p = emit32(p, i->Xin.Alu32M.src->Xri.Imm.imm32); |
| 2009 | goto done; |
| 2010 | } |
| 2011 | default: |
| 2012 | goto bad; |
sewardj | bad34a9 | 2004-07-22 01:14:11 +0000 | [diff] [blame] | 2013 | } |
| 2014 | break; |
| 2015 | |
sewardj | e8c922f | 2004-07-23 01:34:11 +0000 | [diff] [blame] | 2016 | case Xin_Sh32: |
sewardj | d75fe5a | 2004-07-23 12:57:47 +0000 | [diff] [blame] | 2017 | opc_cl = opc_imm = subopc = 0; |
| 2018 | switch (i->Xin.Sh32.op) { |
| 2019 | case Xsh_SHR: opc_cl = 0xD3; opc_imm = 0xC1; subopc = 5; break; |
sewardj | 07134a4 | 2004-07-26 02:04:54 +0000 | [diff] [blame] | 2020 | case Xsh_SAR: opc_cl = 0xD3; opc_imm = 0xC1; subopc = 7; break; |
| 2021 | case Xsh_SHL: opc_cl = 0xD3; opc_imm = 0xC1; subopc = 4; break; |
sewardj | d75fe5a | 2004-07-23 12:57:47 +0000 | [diff] [blame] | 2022 | default: goto bad; |
| 2023 | } |
| 2024 | if (i->Xin.Sh32.src == 0) { |
sewardj | 8ee8c88 | 2005-02-25 17:40:26 +0000 | [diff] [blame] | 2025 | *p++ = toUChar(opc_cl); |
sewardj | eba63f8 | 2005-02-23 13:31:25 +0000 | [diff] [blame] | 2026 | p = doAMode_R(p, fake(subopc), i->Xin.Sh32.dst); |
sewardj | d75fe5a | 2004-07-23 12:57:47 +0000 | [diff] [blame] | 2027 | } else { |
sewardj | 8ee8c88 | 2005-02-25 17:40:26 +0000 | [diff] [blame] | 2028 | *p++ = toUChar(opc_imm); |
sewardj | eba63f8 | 2005-02-23 13:31:25 +0000 | [diff] [blame] | 2029 | p = doAMode_R(p, fake(subopc), i->Xin.Sh32.dst); |
| 2030 | *p++ = (UChar)(i->Xin.Sh32.src); |
sewardj | d75fe5a | 2004-07-23 12:57:47 +0000 | [diff] [blame] | 2031 | } |
sewardj | eba63f8 | 2005-02-23 13:31:25 +0000 | [diff] [blame] | 2032 | goto done; |
sewardj | e8c922f | 2004-07-23 01:34:11 +0000 | [diff] [blame] | 2033 | |
| 2034 | case Xin_Test32: |
sewardj | eba63f8 | 2005-02-23 13:31:25 +0000 | [diff] [blame] | 2035 | /* testl $imm32, %reg */ |
| 2036 | *p++ = 0xF7; |
| 2037 | p = doAMode_R(p, fake(0), i->Xin.Test32.dst); |
| 2038 | p = emit32(p, i->Xin.Test32.imm32); |
| 2039 | goto done; |
sewardj | e8c922f | 2004-07-23 01:34:11 +0000 | [diff] [blame] | 2040 | |
| 2041 | case Xin_Unary32: |
sewardj | 358b7d4 | 2004-11-08 18:54:50 +0000 | [diff] [blame] | 2042 | if (i->Xin.Unary32.op == Xun_NOT) { |
sewardj | d75fe5a | 2004-07-23 12:57:47 +0000 | [diff] [blame] | 2043 | *p++ = 0xF7; |
sewardj | eba63f8 | 2005-02-23 13:31:25 +0000 | [diff] [blame] | 2044 | p = doAMode_R(p, fake(2), i->Xin.Unary32.dst); |
| 2045 | goto done; |
sewardj | d75fe5a | 2004-07-23 12:57:47 +0000 | [diff] [blame] | 2046 | } |
sewardj | 358b7d4 | 2004-11-08 18:54:50 +0000 | [diff] [blame] | 2047 | if (i->Xin.Unary32.op == Xun_NEG) { |
| 2048 | *p++ = 0xF7; |
sewardj | eba63f8 | 2005-02-23 13:31:25 +0000 | [diff] [blame] | 2049 | p = doAMode_R(p, fake(3), i->Xin.Unary32.dst); |
| 2050 | goto done; |
sewardj | 358b7d4 | 2004-11-08 18:54:50 +0000 | [diff] [blame] | 2051 | } |
sewardj | d75fe5a | 2004-07-23 12:57:47 +0000 | [diff] [blame] | 2052 | break; |
sewardj | e8c922f | 2004-07-23 01:34:11 +0000 | [diff] [blame] | 2053 | |
sewardj | a2dad5c | 2004-07-23 11:43:43 +0000 | [diff] [blame] | 2054 | case Xin_MulL: |
sewardj | d75fe5a | 2004-07-23 12:57:47 +0000 | [diff] [blame] | 2055 | subopc = i->Xin.MulL.syned ? 5 : 4; |
sewardj | eba63f8 | 2005-02-23 13:31:25 +0000 | [diff] [blame] | 2056 | *p++ = 0xF7; |
| 2057 | switch (i->Xin.MulL.src->tag) { |
| 2058 | case Xrm_Mem: |
| 2059 | p = doAMode_M(p, fake(subopc), |
| 2060 | i->Xin.MulL.src->Xrm.Mem.am); |
| 2061 | goto done; |
| 2062 | case Xrm_Reg: |
| 2063 | p = doAMode_R(p, fake(subopc), |
| 2064 | i->Xin.MulL.src->Xrm.Reg.reg); |
| 2065 | goto done; |
| 2066 | default: |
| 2067 | goto bad; |
sewardj | d75fe5a | 2004-07-23 12:57:47 +0000 | [diff] [blame] | 2068 | } |
| 2069 | break; |
sewardj | a2dad5c | 2004-07-23 11:43:43 +0000 | [diff] [blame] | 2070 | |
| 2071 | case Xin_Div: |
sewardj | d75fe5a | 2004-07-23 12:57:47 +0000 | [diff] [blame] | 2072 | subopc = i->Xin.Div.syned ? 7 : 6; |
sewardj | eba63f8 | 2005-02-23 13:31:25 +0000 | [diff] [blame] | 2073 | *p++ = 0xF7; |
| 2074 | switch (i->Xin.Div.src->tag) { |
| 2075 | case Xrm_Mem: |
| 2076 | p = doAMode_M(p, fake(subopc), |
| 2077 | i->Xin.Div.src->Xrm.Mem.am); |
| 2078 | goto done; |
| 2079 | case Xrm_Reg: |
| 2080 | p = doAMode_R(p, fake(subopc), |
| 2081 | i->Xin.Div.src->Xrm.Reg.reg); |
| 2082 | goto done; |
| 2083 | default: |
| 2084 | goto bad; |
sewardj | d75fe5a | 2004-07-23 12:57:47 +0000 | [diff] [blame] | 2085 | } |
| 2086 | break; |
sewardj | a2dad5c | 2004-07-23 11:43:43 +0000 | [diff] [blame] | 2087 | |
| 2088 | case Xin_Sh3232: |
sewardj | d75fe5a | 2004-07-23 12:57:47 +0000 | [diff] [blame] | 2089 | vassert(i->Xin.Sh3232.op == Xsh_SHL || i->Xin.Sh3232.op == Xsh_SHR); |
| 2090 | if (i->Xin.Sh3232.amt == 0) { |
| 2091 | /* shldl/shrdl by %cl */ |
| 2092 | *p++ = 0x0F; |
sewardj | 6851154 | 2004-07-28 00:15:44 +0000 | [diff] [blame] | 2093 | if (i->Xin.Sh3232.op == Xsh_SHL) { |
| 2094 | *p++ = 0xA5; |
sewardj | 6851154 | 2004-07-28 00:15:44 +0000 | [diff] [blame] | 2095 | } else { |
| 2096 | *p++ = 0xAD; |
sewardj | 6851154 | 2004-07-28 00:15:44 +0000 | [diff] [blame] | 2097 | } |
sewardj | e5f384c | 2004-07-30 16:17:28 +0000 | [diff] [blame] | 2098 | p = doAMode_R(p, i->Xin.Sh3232.src, i->Xin.Sh3232.dst); |
sewardj | d75fe5a | 2004-07-23 12:57:47 +0000 | [diff] [blame] | 2099 | goto done; |
| 2100 | } |
| 2101 | break; |
sewardj | a2dad5c | 2004-07-23 11:43:43 +0000 | [diff] [blame] | 2102 | |
sewardj | e8c922f | 2004-07-23 01:34:11 +0000 | [diff] [blame] | 2103 | case Xin_Push: |
sewardj | d75fe5a | 2004-07-23 12:57:47 +0000 | [diff] [blame] | 2104 | switch (i->Xin.Push.src->tag) { |
| 2105 | case Xrmi_Mem: |
| 2106 | *p++ = 0xFF; |
| 2107 | p = doAMode_M(p, fake(6), i->Xin.Push.src->Xrmi.Mem.am); |
| 2108 | goto done; |
sewardj | a58ea66 | 2004-08-15 03:12:41 +0000 | [diff] [blame] | 2109 | case Xrmi_Imm: |
| 2110 | *p++ = 0x68; |
| 2111 | p = emit32(p, i->Xin.Push.src->Xrmi.Imm.imm32); |
| 2112 | goto done; |
sewardj | d7cb853 | 2004-08-17 23:59:23 +0000 | [diff] [blame] | 2113 | case Xrmi_Reg: |
sewardj | 8ee8c88 | 2005-02-25 17:40:26 +0000 | [diff] [blame] | 2114 | *p++ = toUChar(0x50 + iregNo(i->Xin.Push.src->Xrmi.Reg.reg)); |
sewardj | d7cb853 | 2004-08-17 23:59:23 +0000 | [diff] [blame] | 2115 | goto done; |
sewardj | a58ea66 | 2004-08-15 03:12:41 +0000 | [diff] [blame] | 2116 | default: |
sewardj | d75fe5a | 2004-07-23 12:57:47 +0000 | [diff] [blame] | 2117 | goto bad; |
| 2118 | } |
sewardj | e8c922f | 2004-07-23 01:34:11 +0000 | [diff] [blame] | 2119 | |
| 2120 | case Xin_Call: |
sewardj | 4b861de | 2004-11-03 15:24:42 +0000 | [diff] [blame] | 2121 | /* See detailed comment for Xin_Call in getRegUsage_X86Instr above |
| 2122 | for explanation of this. */ |
| 2123 | switch (i->Xin.Call.regparms) { |
| 2124 | case 0: irno = iregNo(hregX86_EAX()); break; |
sewardj | 45c50eb | 2004-11-04 18:25:33 +0000 | [diff] [blame] | 2125 | case 1: irno = iregNo(hregX86_EDX()); break; |
| 2126 | case 2: irno = iregNo(hregX86_ECX()); break; |
sewardj | 4b861de | 2004-11-03 15:24:42 +0000 | [diff] [blame] | 2127 | case 3: irno = iregNo(hregX86_EDI()); break; |
| 2128 | default: vpanic(" emit_X86Instr:call:regparms"); |
| 2129 | } |
| 2130 | /* jump over the following two insns if the condition does not |
| 2131 | hold */ |
| 2132 | if (i->Xin.Call.cond != Xcc_ALWAYS) { |
sewardj | 8ee8c88 | 2005-02-25 17:40:26 +0000 | [diff] [blame] | 2133 | *p++ = toUChar(0x70 + (0xF & (i->Xin.Call.cond ^ 1))); |
sewardj | 4b861de | 2004-11-03 15:24:42 +0000 | [diff] [blame] | 2134 | *p++ = 0x07; /* 7 bytes in the next two insns */ |
| 2135 | } |
| 2136 | /* movl $target, %tmp */ |
sewardj | 8ee8c88 | 2005-02-25 17:40:26 +0000 | [diff] [blame] | 2137 | *p++ = toUChar(0xB8 + irno); |
sewardj | 4b861de | 2004-11-03 15:24:42 +0000 | [diff] [blame] | 2138 | p = emit32(p, i->Xin.Call.target); |
| 2139 | /* call *%tmp */ |
sewardj | d75fe5a | 2004-07-23 12:57:47 +0000 | [diff] [blame] | 2140 | *p++ = 0xFF; |
sewardj | 8ee8c88 | 2005-02-25 17:40:26 +0000 | [diff] [blame] | 2141 | *p++ = toUChar(0xD0 + irno); |
sewardj | d75fe5a | 2004-07-23 12:57:47 +0000 | [diff] [blame] | 2142 | goto done; |
sewardj | e8c922f | 2004-07-23 01:34:11 +0000 | [diff] [blame] | 2143 | |
sewardj | 86898e8 | 2004-07-22 17:26:12 +0000 | [diff] [blame] | 2144 | case Xin_Goto: |
sewardj | 893aada | 2004-11-29 19:57:54 +0000 | [diff] [blame] | 2145 | /* Use ptmp for backpatching conditional jumps. */ |
| 2146 | ptmp = NULL; |
| 2147 | |
| 2148 | /* First off, if this is conditional, create a conditional |
| 2149 | jump over the rest of it. */ |
| 2150 | if (i->Xin.Goto.cond != Xcc_ALWAYS) { |
| 2151 | /* jmp fwds if !condition */ |
sewardj | 8ee8c88 | 2005-02-25 17:40:26 +0000 | [diff] [blame] | 2152 | *p++ = toUChar(0x70 + (0xF & (i->Xin.Goto.cond ^ 1))); |
sewardj | 893aada | 2004-11-29 19:57:54 +0000 | [diff] [blame] | 2153 | ptmp = p; /* fill in this bit later */ |
| 2154 | *p++ = 0; /* # of bytes to jump over; don't know how many yet. */ |
sewardj | 750f407 | 2004-07-26 22:39:11 +0000 | [diff] [blame] | 2155 | } |
sewardj | 893aada | 2004-11-29 19:57:54 +0000 | [diff] [blame] | 2156 | |
| 2157 | /* If a non-boring, set %ebp (the guest state pointer) |
| 2158 | appropriately. */ |
| 2159 | /* movl $magic_number, %ebp */ |
| 2160 | switch (i->Xin.Goto.jk) { |
| 2161 | case Ijk_ClientReq: |
| 2162 | *p++ = 0xBD; |
| 2163 | p = emit32(p, VEX_TRC_JMP_CLIENTREQ); break; |
sewardj | 4fa325a | 2005-11-03 13:27:24 +0000 | [diff] [blame] | 2164 | case Ijk_Sys_int128: |
sewardj | 893aada | 2004-11-29 19:57:54 +0000 | [diff] [blame] | 2165 | *p++ = 0xBD; |
sewardj | 4fa325a | 2005-11-03 13:27:24 +0000 | [diff] [blame] | 2166 | p = emit32(p, VEX_TRC_JMP_SYS_INT128); break; |
sewardj | 893aada | 2004-11-29 19:57:54 +0000 | [diff] [blame] | 2167 | case Ijk_Yield: |
| 2168 | *p++ = 0xBD; |
| 2169 | p = emit32(p, VEX_TRC_JMP_YIELD); break; |
| 2170 | case Ijk_EmWarn: |
| 2171 | *p++ = 0xBD; |
| 2172 | p = emit32(p, VEX_TRC_JMP_EMWARN); break; |
sewardj | 52444cb | 2004-12-13 14:09:01 +0000 | [diff] [blame] | 2173 | case Ijk_MapFail: |
| 2174 | *p++ = 0xBD; |
| 2175 | p = emit32(p, VEX_TRC_JMP_MAPFAIL); break; |
| 2176 | case Ijk_NoDecode: |
| 2177 | *p++ = 0xBD; |
| 2178 | p = emit32(p, VEX_TRC_JMP_NODECODE); break; |
sewardj | db4738a | 2005-07-07 01:32:16 +0000 | [diff] [blame] | 2179 | case Ijk_TInval: |
| 2180 | *p++ = 0xBD; |
| 2181 | p = emit32(p, VEX_TRC_JMP_TINVAL); break; |
sewardj | 4fa325a | 2005-11-03 13:27:24 +0000 | [diff] [blame] | 2182 | case Ijk_Sys_sysenter: |
sewardj | f07ed03 | 2005-08-07 14:48:03 +0000 | [diff] [blame] | 2183 | *p++ = 0xBD; |
sewardj | 4fa325a | 2005-11-03 13:27:24 +0000 | [diff] [blame] | 2184 | p = emit32(p, VEX_TRC_JMP_SYS_SYSENTER); break; |
sewardj | 893aada | 2004-11-29 19:57:54 +0000 | [diff] [blame] | 2185 | case Ijk_Ret: |
| 2186 | case Ijk_Call: |
| 2187 | case Ijk_Boring: |
| 2188 | break; |
| 2189 | default: |
| 2190 | ppIRJumpKind(i->Xin.Goto.jk); |
| 2191 | vpanic("emit_X86Instr.Xin_Goto: unknown jump kind"); |
| 2192 | } |
| 2193 | |
| 2194 | /* Get the destination address into %eax */ |
| 2195 | if (i->Xin.Goto.dst->tag == Xri_Imm) { |
sewardj | 17c7f95 | 2005-12-15 14:02:34 +0000 | [diff] [blame^] | 2196 | /* movl $immediate, %eax */ |
sewardj | 86898e8 | 2004-07-22 17:26:12 +0000 | [diff] [blame] | 2197 | *p++ = 0xB8; |
| 2198 | p = emit32(p, i->Xin.Goto.dst->Xri.Imm.imm32); |
sewardj | 893aada | 2004-11-29 19:57:54 +0000 | [diff] [blame] | 2199 | } else { |
| 2200 | vassert(i->Xin.Goto.dst->tag == Xri_Reg); |
sewardj | 17c7f95 | 2005-12-15 14:02:34 +0000 | [diff] [blame^] | 2201 | /* movl %reg, %eax */ |
sewardj | e8c922f | 2004-07-23 01:34:11 +0000 | [diff] [blame] | 2202 | if (i->Xin.Goto.dst->Xri.Reg.reg != hregX86_EAX()) { |
| 2203 | *p++ = 0x89; |
| 2204 | p = doAMode_R(p, i->Xin.Goto.dst->Xri.Reg.reg, hregX86_EAX()); |
sewardj | d75fe5a | 2004-07-23 12:57:47 +0000 | [diff] [blame] | 2205 | } |
sewardj | d75fe5a | 2004-07-23 12:57:47 +0000 | [diff] [blame] | 2206 | } |
sewardj | 893aada | 2004-11-29 19:57:54 +0000 | [diff] [blame] | 2207 | |
sewardj | 17c7f95 | 2005-12-15 14:02:34 +0000 | [diff] [blame^] | 2208 | /* Get the dispatcher address into %edx. This has to happen |
| 2209 | after the load of %eax since %edx might be carrying the value |
| 2210 | destined for %eax immediately prior to this Xin_Goto. */ |
| 2211 | vassert(sizeof(UInt) == sizeof(void*)); |
| 2212 | vassert(dispatch != NULL); |
| 2213 | /* movl $imm32, %edx */ |
| 2214 | *p++ = 0xBA; |
| 2215 | p = emit32(p, (UInt)dispatch); |
| 2216 | |
| 2217 | /* jmp *%edx */ |
| 2218 | *p++ = 0xFF; |
| 2219 | *p++ = 0xE2; |
sewardj | 893aada | 2004-11-29 19:57:54 +0000 | [diff] [blame] | 2220 | |
| 2221 | /* Fix up the conditional jump, if there was one. */ |
| 2222 | if (i->Xin.Goto.cond != Xcc_ALWAYS) { |
| 2223 | Int delta = p - ptmp; |
| 2224 | vassert(delta > 0 && delta < 20); |
sewardj | 8ee8c88 | 2005-02-25 17:40:26 +0000 | [diff] [blame] | 2225 | *ptmp = toUChar(delta-1); |
sewardj | e8c922f | 2004-07-23 01:34:11 +0000 | [diff] [blame] | 2226 | } |
sewardj | 893aada | 2004-11-29 19:57:54 +0000 | [diff] [blame] | 2227 | goto done; |
sewardj | 86898e8 | 2004-07-22 17:26:12 +0000 | [diff] [blame] | 2228 | |
sewardj | e8c922f | 2004-07-23 01:34:11 +0000 | [diff] [blame] | 2229 | case Xin_CMov32: |
sewardj | d75fe5a | 2004-07-23 12:57:47 +0000 | [diff] [blame] | 2230 | vassert(i->Xin.CMov32.cond != Xcc_ALWAYS); |
sewardj | c4904af | 2005-08-08 00:33:37 +0000 | [diff] [blame] | 2231 | |
sewardj | 893aada | 2004-11-29 19:57:54 +0000 | [diff] [blame] | 2232 | /* This generates cmov, which is illegal on P54/P55. */ |
sewardj | c4904af | 2005-08-08 00:33:37 +0000 | [diff] [blame] | 2233 | /* |
sewardj | d75fe5a | 2004-07-23 12:57:47 +0000 | [diff] [blame] | 2234 | *p++ = 0x0F; |
sewardj | 8ee8c88 | 2005-02-25 17:40:26 +0000 | [diff] [blame] | 2235 | *p++ = toUChar(0x40 + (0xF & i->Xin.CMov32.cond)); |
sewardj | d75fe5a | 2004-07-23 12:57:47 +0000 | [diff] [blame] | 2236 | if (i->Xin.CMov32.src->tag == Xrm_Reg) { |
| 2237 | p = doAMode_R(p, i->Xin.CMov32.dst, i->Xin.CMov32.src->Xrm.Reg.reg); |
| 2238 | goto done; |
| 2239 | } |
| 2240 | if (i->Xin.CMov32.src->tag == Xrm_Mem) { |
| 2241 | p = doAMode_M(p, i->Xin.CMov32.dst, i->Xin.CMov32.src->Xrm.Mem.am); |
| 2242 | goto done; |
| 2243 | } |
sewardj | c4904af | 2005-08-08 00:33:37 +0000 | [diff] [blame] | 2244 | */ |
| 2245 | |
| 2246 | /* Alternative version which works on any x86 variant. */ |
| 2247 | /* jmp fwds if !condition */ |
sewardj | c7cd214 | 2005-09-09 22:31:49 +0000 | [diff] [blame] | 2248 | *p++ = toUChar(0x70 + (i->Xin.CMov32.cond ^ 1)); |
sewardj | c4904af | 2005-08-08 00:33:37 +0000 | [diff] [blame] | 2249 | *p++ = 0; /* # of bytes in the next bit, which we don't know yet */ |
| 2250 | ptmp = p; |
| 2251 | |
| 2252 | switch (i->Xin.CMov32.src->tag) { |
| 2253 | case Xrm_Reg: |
| 2254 | /* Big sigh. This is movl E -> G ... */ |
| 2255 | *p++ = 0x89; |
| 2256 | p = doAMode_R(p, i->Xin.CMov32.src->Xrm.Reg.reg, |
| 2257 | i->Xin.CMov32.dst); |
| 2258 | |
| 2259 | break; |
| 2260 | case Xrm_Mem: |
| 2261 | /* ... whereas this is movl G -> E. That's why the args |
| 2262 | to doAMode_R appear to be the wrong way round in the |
| 2263 | Xrm_Reg case. */ |
| 2264 | *p++ = 0x8B; |
| 2265 | p = doAMode_M(p, i->Xin.CMov32.dst, |
| 2266 | i->Xin.CMov32.src->Xrm.Mem.am); |
| 2267 | break; |
| 2268 | default: |
| 2269 | goto bad; |
| 2270 | } |
| 2271 | /* Fill in the jump offset. */ |
sewardj | c7cd214 | 2005-09-09 22:31:49 +0000 | [diff] [blame] | 2272 | *(ptmp-1) = toUChar(p - ptmp); |
sewardj | c4904af | 2005-08-08 00:33:37 +0000 | [diff] [blame] | 2273 | goto done; |
| 2274 | |
sewardj | d75fe5a | 2004-07-23 12:57:47 +0000 | [diff] [blame] | 2275 | break; |
sewardj | e8c922f | 2004-07-23 01:34:11 +0000 | [diff] [blame] | 2276 | |
| 2277 | case Xin_LoadEX: |
sewardj | d75fe5a | 2004-07-23 12:57:47 +0000 | [diff] [blame] | 2278 | if (i->Xin.LoadEX.szSmall == 1 && !i->Xin.LoadEX.syned) { |
| 2279 | /* movzbl */ |
| 2280 | *p++ = 0x0F; |
| 2281 | *p++ = 0xB6; |
| 2282 | p = doAMode_M(p, i->Xin.LoadEX.dst, i->Xin.LoadEX.src); |
| 2283 | goto done; |
| 2284 | } |
| 2285 | if (i->Xin.LoadEX.szSmall == 2 && !i->Xin.LoadEX.syned) { |
| 2286 | /* movzwl */ |
| 2287 | *p++ = 0x0F; |
| 2288 | *p++ = 0xB7; |
| 2289 | p = doAMode_M(p, i->Xin.LoadEX.dst, i->Xin.LoadEX.src); |
| 2290 | goto done; |
| 2291 | } |
| 2292 | break; |
sewardj | e8c922f | 2004-07-23 01:34:11 +0000 | [diff] [blame] | 2293 | |
sewardj | d7cb853 | 2004-08-17 23:59:23 +0000 | [diff] [blame] | 2294 | case Xin_Set32: |
| 2295 | /* Make the destination register be 1 or 0, depending on whether |
| 2296 | the relevant condition holds. We have to dodge and weave |
| 2297 | when the destination is %esi or %edi as we cannot directly |
| 2298 | emit the native 'setb %reg' for those. Further complication: |
| 2299 | the top 24 bits of the destination should be forced to zero, |
| 2300 | but doing 'xor %r,%r' kills the flag(s) we are about to read. |
sewardj | 3503ad8 | 2004-08-24 00:24:56 +0000 | [diff] [blame] | 2301 | Sigh. So start off my moving $0 into the dest. */ |
sewardj | d7cb853 | 2004-08-17 23:59:23 +0000 | [diff] [blame] | 2302 | |
sewardj | 3503ad8 | 2004-08-24 00:24:56 +0000 | [diff] [blame] | 2303 | /* Do we need to swap in %eax? */ |
sewardj | d7cb853 | 2004-08-17 23:59:23 +0000 | [diff] [blame] | 2304 | if (iregNo(i->Xin.Set32.dst) >= 4) { |
| 2305 | /* xchg %eax, %dst */ |
sewardj | 8ee8c88 | 2005-02-25 17:40:26 +0000 | [diff] [blame] | 2306 | *p++ = toUChar(0x90 + iregNo(i->Xin.Set32.dst)); |
sewardj | 3503ad8 | 2004-08-24 00:24:56 +0000 | [diff] [blame] | 2307 | /* movl $0, %eax */ |
sewardj | 8ee8c88 | 2005-02-25 17:40:26 +0000 | [diff] [blame] | 2308 | *p++ =toUChar(0xB8 + iregNo(hregX86_EAX())); |
sewardj | 3503ad8 | 2004-08-24 00:24:56 +0000 | [diff] [blame] | 2309 | p = emit32(p, 0); |
| 2310 | /* setb lo8(%eax) */ |
sewardj | d7cb853 | 2004-08-17 23:59:23 +0000 | [diff] [blame] | 2311 | *p++ = 0x0F; |
sewardj | 8ee8c88 | 2005-02-25 17:40:26 +0000 | [diff] [blame] | 2312 | *p++ = toUChar(0x90 + (0xF & i->Xin.Set32.cond)); |
sewardj | d7cb853 | 2004-08-17 23:59:23 +0000 | [diff] [blame] | 2313 | p = doAMode_R(p, fake(0), hregX86_EAX()); |
| 2314 | /* xchg %eax, %dst */ |
sewardj | 8ee8c88 | 2005-02-25 17:40:26 +0000 | [diff] [blame] | 2315 | *p++ = toUChar(0x90 + iregNo(i->Xin.Set32.dst)); |
sewardj | d7cb853 | 2004-08-17 23:59:23 +0000 | [diff] [blame] | 2316 | } else { |
sewardj | 3503ad8 | 2004-08-24 00:24:56 +0000 | [diff] [blame] | 2317 | /* movl $0, %dst */ |
sewardj | 8ee8c88 | 2005-02-25 17:40:26 +0000 | [diff] [blame] | 2318 | *p++ = toUChar(0xB8 + iregNo(i->Xin.Set32.dst)); |
sewardj | 3503ad8 | 2004-08-24 00:24:56 +0000 | [diff] [blame] | 2319 | p = emit32(p, 0); |
| 2320 | /* setb lo8(%dst) */ |
sewardj | d7cb853 | 2004-08-17 23:59:23 +0000 | [diff] [blame] | 2321 | *p++ = 0x0F; |
sewardj | 8ee8c88 | 2005-02-25 17:40:26 +0000 | [diff] [blame] | 2322 | *p++ = toUChar(0x90 + (0xF & i->Xin.Set32.cond)); |
sewardj | d7cb853 | 2004-08-17 23:59:23 +0000 | [diff] [blame] | 2323 | p = doAMode_R(p, fake(0), i->Xin.Set32.dst); |
| 2324 | } |
| 2325 | goto done; |
| 2326 | |
sewardj | ce646f2 | 2004-08-31 23:55:54 +0000 | [diff] [blame] | 2327 | case Xin_Bsfr32: |
| 2328 | *p++ = 0x0F; |
| 2329 | if (i->Xin.Bsfr32.isFwds) { |
| 2330 | *p++ = 0xBC; |
| 2331 | } else { |
| 2332 | *p++ = 0xBD; |
| 2333 | } |
| 2334 | p = doAMode_R(p, i->Xin.Bsfr32.dst, i->Xin.Bsfr32.src); |
| 2335 | goto done; |
| 2336 | |
sewardj | 3e83893 | 2005-01-07 12:09:15 +0000 | [diff] [blame] | 2337 | case Xin_MFence: |
| 2338 | /* see comment in hdefs.h re this insn */ |
sewardj | bb3f52d | 2005-01-07 14:14:50 +0000 | [diff] [blame] | 2339 | if (0) vex_printf("EMIT FENCE\n"); |
sewardj | 3e83893 | 2005-01-07 12:09:15 +0000 | [diff] [blame] | 2340 | switch (i->Xin.MFence.subarch) { |
| 2341 | case VexSubArchX86_sse0: |
sewardj | 3e83893 | 2005-01-07 12:09:15 +0000 | [diff] [blame] | 2342 | /* lock addl $0,0(%esp) */ |
| 2343 | *p++ = 0xF0; *p++ = 0x83; *p++ = 0x44; |
| 2344 | *p++ = 0x24; *p++ = 0x00; *p++ = 0x00; |
| 2345 | goto done; |
| 2346 | case VexSubArchX86_sse1: |
| 2347 | /* sfence */ |
| 2348 | *p++ = 0x0F; *p++ = 0xAE; *p++ = 0xF8; |
| 2349 | /* lock addl $0,0(%esp) */ |
| 2350 | *p++ = 0xF0; *p++ = 0x83; *p++ = 0x44; |
| 2351 | *p++ = 0x24; *p++ = 0x00; *p++ = 0x00; |
| 2352 | goto done; |
| 2353 | case VexSubArchX86_sse2: |
sewardj | 3e83893 | 2005-01-07 12:09:15 +0000 | [diff] [blame] | 2354 | /* mfence */ |
| 2355 | *p++ = 0x0F; *p++ = 0xAE; *p++ = 0xF0; |
| 2356 | goto done; |
| 2357 | default: |
| 2358 | vpanic("emit_X86Instr:mfence:subarch"); |
| 2359 | } |
| 2360 | break; |
| 2361 | |
sewardj | e8c922f | 2004-07-23 01:34:11 +0000 | [diff] [blame] | 2362 | case Xin_Store: |
sewardj | d75fe5a | 2004-07-23 12:57:47 +0000 | [diff] [blame] | 2363 | if (i->Xin.Store.sz == 2) { |
| 2364 | /* This case, at least, is simple, given that we can |
| 2365 | reference the low 16 bits of any integer register. */ |
| 2366 | *p++ = 0x66; |
| 2367 | *p++ = 0x89; |
| 2368 | p = doAMode_M(p, i->Xin.Store.src, i->Xin.Store.dst); |
| 2369 | goto done; |
sewardj | e8c922f | 2004-07-23 01:34:11 +0000 | [diff] [blame] | 2370 | } |
sewardj | d75fe5a | 2004-07-23 12:57:47 +0000 | [diff] [blame] | 2371 | |
| 2372 | if (i->Xin.Store.sz == 1) { |
| 2373 | /* We have to do complex dodging and weaving if src is not |
| 2374 | the low 8 bits of %eax/%ebx/%ecx/%edx. */ |
| 2375 | if (iregNo(i->Xin.Store.src) < 4) { |
| 2376 | /* we're OK, can do it directly */ |
| 2377 | *p++ = 0x88; |
| 2378 | p = doAMode_M(p, i->Xin.Store.src, i->Xin.Store.dst); |
| 2379 | goto done; |
| 2380 | } else { |
| 2381 | /* Bleh. This means the source is %edi or %esi. Since |
| 2382 | the address mode can only mention three registers, at |
| 2383 | least one of %eax/%ebx/%ecx/%edx must be available to |
| 2384 | temporarily swap the source into, so the store can |
| 2385 | happen. So we have to look at the regs mentioned |
| 2386 | in the amode. */ |
sewardj | 2e56f9f | 2004-07-24 01:24:38 +0000 | [diff] [blame] | 2387 | HReg swap = INVALID_HREG; |
| 2388 | HReg eax = hregX86_EAX(), ebx = hregX86_EBX(), |
| 2389 | ecx = hregX86_ECX(), edx = hregX86_EDX(); |
sewardj | d75fe5a | 2004-07-23 12:57:47 +0000 | [diff] [blame] | 2390 | Bool a_ok = True, b_ok = True, c_ok = True, d_ok = True; |
| 2391 | HRegUsage u; |
| 2392 | Int j; |
| 2393 | initHRegUsage(&u); |
| 2394 | addRegUsage_X86AMode(&u, i->Xin.Store.dst); |
| 2395 | for (j = 0; j < u.n_used; j++) { |
| 2396 | HReg r = u.hreg[j]; |
| 2397 | if (r == eax) a_ok = False; |
| 2398 | if (r == ebx) b_ok = False; |
| 2399 | if (r == ecx) c_ok = False; |
| 2400 | if (r == edx) d_ok = False; |
| 2401 | } |
sewardj | d75fe5a | 2004-07-23 12:57:47 +0000 | [diff] [blame] | 2402 | if (a_ok) swap = eax; |
| 2403 | if (b_ok) swap = ebx; |
| 2404 | if (c_ok) swap = ecx; |
| 2405 | if (d_ok) swap = edx; |
| 2406 | vassert(swap != INVALID_HREG); |
| 2407 | /* xchgl %source, %swap. Could do better if swap is %eax. */ |
| 2408 | *p++ = 0x87; |
| 2409 | p = doAMode_R(p, i->Xin.Store.src, swap); |
| 2410 | /* movb lo8{%swap}, (dst) */ |
| 2411 | *p++ = 0x88; |
| 2412 | p = doAMode_M(p, swap, i->Xin.Store.dst); |
| 2413 | /* xchgl %source, %swap. Could do better if swap is %eax. */ |
| 2414 | *p++ = 0x87; |
| 2415 | p = doAMode_R(p, i->Xin.Store.src, swap); |
| 2416 | goto done; |
| 2417 | } |
| 2418 | } /* if (i->Xin.Store.sz == 1) */ |
| 2419 | break; |
sewardj | 86898e8 | 2004-07-22 17:26:12 +0000 | [diff] [blame] | 2420 | |
sewardj | cfded9a | 2004-09-09 11:44:16 +0000 | [diff] [blame] | 2421 | case Xin_FpUnary: |
| 2422 | /* gop %src, %dst |
| 2423 | --> ffree %st7 ; fld %st(src) ; fop %st(0) ; fstp %st(1+dst) |
| 2424 | */ |
| 2425 | p = do_ffree_st7(p); |
| 2426 | p = do_fld_st(p, 0+hregNumber(i->Xin.FpUnary.src)); |
| 2427 | p = do_fop1_st(p, i->Xin.FpUnary.op); |
| 2428 | p = do_fstp_st(p, 1+hregNumber(i->Xin.FpUnary.dst)); |
| 2429 | goto done; |
| 2430 | |
sewardj | bb53f8c | 2004-08-14 11:50:01 +0000 | [diff] [blame] | 2431 | case Xin_FpBinary: |
sewardj | 06c32a0 | 2004-09-12 12:07:34 +0000 | [diff] [blame] | 2432 | if (i->Xin.FpBinary.op == Xfp_YL2X |
| 2433 | || i->Xin.FpBinary.op == Xfp_YL2XP1) { |
sewardj | 8308aad | 2004-09-12 11:09:54 +0000 | [diff] [blame] | 2434 | /* Have to do this specially. */ |
| 2435 | /* ffree %st7 ; fld %st(srcL) ; |
sewardj | 06c32a0 | 2004-09-12 12:07:34 +0000 | [diff] [blame] | 2436 | ffree %st7 ; fld %st(srcR+1) ; fyl2x{p1} ; fstp(1+dst) */ |
sewardj | 8308aad | 2004-09-12 11:09:54 +0000 | [diff] [blame] | 2437 | p = do_ffree_st7(p); |
| 2438 | p = do_fld_st(p, 0+hregNumber(i->Xin.FpBinary.srcL)); |
| 2439 | p = do_ffree_st7(p); |
| 2440 | p = do_fld_st(p, 1+hregNumber(i->Xin.FpBinary.srcR)); |
sewardj | 06c32a0 | 2004-09-12 12:07:34 +0000 | [diff] [blame] | 2441 | *p++ = 0xD9; |
sewardj | 8ee8c88 | 2005-02-25 17:40:26 +0000 | [diff] [blame] | 2442 | *p++ = toUChar(i->Xin.FpBinary.op==Xfp_YL2X ? 0xF1 : 0xF9); |
sewardj | 8308aad | 2004-09-12 11:09:54 +0000 | [diff] [blame] | 2443 | p = do_fstp_st(p, 1+hregNumber(i->Xin.FpBinary.dst)); |
| 2444 | goto done; |
| 2445 | } |
sewardj | 52ace3e | 2004-09-11 17:10:08 +0000 | [diff] [blame] | 2446 | if (i->Xin.FpBinary.op == Xfp_ATAN) { |
sewardj | cfded9a | 2004-09-09 11:44:16 +0000 | [diff] [blame] | 2447 | /* Have to do this specially. */ |
sewardj | 46de407 | 2004-09-11 19:23:24 +0000 | [diff] [blame] | 2448 | /* ffree %st7 ; fld %st(srcL) ; |
| 2449 | ffree %st7 ; fld %st(srcR+1) ; fpatan ; fstp(1+dst) */ |
sewardj | cfded9a | 2004-09-09 11:44:16 +0000 | [diff] [blame] | 2450 | p = do_ffree_st7(p); |
| 2451 | p = do_fld_st(p, 0+hregNumber(i->Xin.FpBinary.srcL)); |
sewardj | 46de407 | 2004-09-11 19:23:24 +0000 | [diff] [blame] | 2452 | p = do_ffree_st7(p); |
sewardj | cfded9a | 2004-09-09 11:44:16 +0000 | [diff] [blame] | 2453 | p = do_fld_st(p, 1+hregNumber(i->Xin.FpBinary.srcR)); |
| 2454 | *p++ = 0xD9; *p++ = 0xF3; |
| 2455 | p = do_fstp_st(p, 1+hregNumber(i->Xin.FpBinary.dst)); |
| 2456 | goto done; |
| 2457 | } |
sewardj | 06c32a0 | 2004-09-12 12:07:34 +0000 | [diff] [blame] | 2458 | if (i->Xin.FpBinary.op == Xfp_PREM |
sewardj | 442d0be | 2004-10-15 22:57:13 +0000 | [diff] [blame] | 2459 | || i->Xin.FpBinary.op == Xfp_PREM1 |
sewardj | 06c32a0 | 2004-09-12 12:07:34 +0000 | [diff] [blame] | 2460 | || i->Xin.FpBinary.op == Xfp_SCALE) { |
sewardj | 46de407 | 2004-09-11 19:23:24 +0000 | [diff] [blame] | 2461 | /* Have to do this specially. */ |
| 2462 | /* ffree %st7 ; fld %st(srcR) ; |
sewardj | 442d0be | 2004-10-15 22:57:13 +0000 | [diff] [blame] | 2463 | ffree %st7 ; fld %st(srcL+1) ; fprem/fprem1/fscale ; fstp(2+dst) ; |
sewardj | 46de407 | 2004-09-11 19:23:24 +0000 | [diff] [blame] | 2464 | fincstp ; ffree %st7 */ |
| 2465 | p = do_ffree_st7(p); |
| 2466 | p = do_fld_st(p, 0+hregNumber(i->Xin.FpBinary.srcR)); |
| 2467 | p = do_ffree_st7(p); |
| 2468 | p = do_fld_st(p, 1+hregNumber(i->Xin.FpBinary.srcL)); |
sewardj | 442d0be | 2004-10-15 22:57:13 +0000 | [diff] [blame] | 2469 | *p++ = 0xD9; |
| 2470 | switch (i->Xin.FpBinary.op) { |
| 2471 | case Xfp_PREM: *p++ = 0xF8; break; |
| 2472 | case Xfp_PREM1: *p++ = 0xF5; break; |
| 2473 | case Xfp_SCALE: *p++ = 0xFD; break; |
| 2474 | default: vpanic("emitX86Instr(FpBinary,PREM/PREM1/SCALE)"); |
| 2475 | } |
sewardj | 46de407 | 2004-09-11 19:23:24 +0000 | [diff] [blame] | 2476 | p = do_fstp_st(p, 2+hregNumber(i->Xin.FpBinary.dst)); |
| 2477 | *p++ = 0xD9; *p++ = 0xF7; |
| 2478 | p = do_ffree_st7(p); |
| 2479 | goto done; |
| 2480 | } |
sewardj | cfded9a | 2004-09-09 11:44:16 +0000 | [diff] [blame] | 2481 | /* General case */ |
sewardj | bb53f8c | 2004-08-14 11:50:01 +0000 | [diff] [blame] | 2482 | /* gop %srcL, %srcR, %dst |
| 2483 | --> ffree %st7 ; fld %st(srcL) ; fop %st(1+srcR) ; fstp %st(1+dst) |
| 2484 | */ |
| 2485 | p = do_ffree_st7(p); |
| 2486 | p = do_fld_st(p, 0+hregNumber(i->Xin.FpBinary.srcL)); |
sewardj | 3bca906 | 2004-12-04 14:36:09 +0000 | [diff] [blame] | 2487 | p = do_fop2_st(p, i->Xin.FpBinary.op, |
| 2488 | 1+hregNumber(i->Xin.FpBinary.srcR)); |
sewardj | bb53f8c | 2004-08-14 11:50:01 +0000 | [diff] [blame] | 2489 | p = do_fstp_st(p, 1+hregNumber(i->Xin.FpBinary.dst)); |
| 2490 | goto done; |
| 2491 | |
sewardj | 3196daf | 2004-08-13 00:18:58 +0000 | [diff] [blame] | 2492 | case Xin_FpLdSt: |
sewardj | 3bca906 | 2004-12-04 14:36:09 +0000 | [diff] [blame] | 2493 | vassert(i->Xin.FpLdSt.sz == 4 || i->Xin.FpLdSt.sz == 8); |
sewardj | 3196daf | 2004-08-13 00:18:58 +0000 | [diff] [blame] | 2494 | if (i->Xin.FpLdSt.isLoad) { |
| 2495 | /* Load from memory into %fakeN. |
sewardj | bb53f8c | 2004-08-14 11:50:01 +0000 | [diff] [blame] | 2496 | --> ffree %st(7) ; fld{s/l} amode ; fstp st(N+1) |
sewardj | 3196daf | 2004-08-13 00:18:58 +0000 | [diff] [blame] | 2497 | */ |
| 2498 | p = do_ffree_st7(p); |
sewardj | 8ee8c88 | 2005-02-25 17:40:26 +0000 | [diff] [blame] | 2499 | *p++ = toUChar(i->Xin.FpLdSt.sz==4 ? 0xD9 : 0xDD); |
sewardj | 3196daf | 2004-08-13 00:18:58 +0000 | [diff] [blame] | 2500 | p = doAMode_M(p, fake(0)/*subopcode*/, i->Xin.FpLdSt.addr); |
| 2501 | p = do_fstp_st(p, 1+hregNumber(i->Xin.FpLdSt.reg)); |
| 2502 | goto done; |
| 2503 | } else { |
| 2504 | /* Store from %fakeN into memory. |
sewardj | bb53f8c | 2004-08-14 11:50:01 +0000 | [diff] [blame] | 2505 | --> ffree %st(7) ; fld st(N) ; fstp{l|s} amode |
sewardj | 3196daf | 2004-08-13 00:18:58 +0000 | [diff] [blame] | 2506 | */ |
| 2507 | p = do_ffree_st7(p); |
| 2508 | p = do_fld_st(p, 0+hregNumber(i->Xin.FpLdSt.reg)); |
sewardj | 8ee8c88 | 2005-02-25 17:40:26 +0000 | [diff] [blame] | 2509 | *p++ = toUChar(i->Xin.FpLdSt.sz==4 ? 0xD9 : 0xDD); |
sewardj | 3196daf | 2004-08-13 00:18:58 +0000 | [diff] [blame] | 2510 | p = doAMode_M(p, fake(3)/*subopcode*/, i->Xin.FpLdSt.addr); |
| 2511 | goto done; |
| 2512 | } |
| 2513 | break; |
| 2514 | |
sewardj | 89cd093 | 2004-09-08 18:23:25 +0000 | [diff] [blame] | 2515 | case Xin_FpLdStI: |
| 2516 | if (i->Xin.FpLdStI.isLoad) { |
| 2517 | /* Load from memory into %fakeN, converting from an int. |
| 2518 | --> ffree %st(7) ; fild{w/l/ll} amode ; fstp st(N+1) |
| 2519 | */ |
| 2520 | switch (i->Xin.FpLdStI.sz) { |
sewardj | bdc7d21 | 2004-09-09 02:46:40 +0000 | [diff] [blame] | 2521 | case 8: opc = 0xDF; subopc_imm = 5; break; |
sewardj | 89cd093 | 2004-09-08 18:23:25 +0000 | [diff] [blame] | 2522 | case 4: opc = 0xDB; subopc_imm = 0; break; |
| 2523 | case 2: vassert(0); opc = 0xDF; subopc_imm = 0; break; |
| 2524 | default: vpanic("emitX86Instr(Xin_FpLdStI-load)"); |
| 2525 | } |
| 2526 | p = do_ffree_st7(p); |
sewardj | 8ee8c88 | 2005-02-25 17:40:26 +0000 | [diff] [blame] | 2527 | *p++ = toUChar(opc); |
sewardj | 89cd093 | 2004-09-08 18:23:25 +0000 | [diff] [blame] | 2528 | p = doAMode_M(p, fake(subopc_imm)/*subopcode*/, i->Xin.FpLdStI.addr); |
| 2529 | p = do_fstp_st(p, 1+hregNumber(i->Xin.FpLdStI.reg)); |
| 2530 | goto done; |
| 2531 | } else { |
| 2532 | /* Store from %fakeN into memory, converting to an int. |
| 2533 | --> ffree %st(7) ; fld st(N) ; fistp{w/l/ll} amode |
| 2534 | */ |
| 2535 | switch (i->Xin.FpLdStI.sz) { |
sewardj | cfded9a | 2004-09-09 11:44:16 +0000 | [diff] [blame] | 2536 | case 8: opc = 0xDF; subopc_imm = 7; break; |
sewardj | 89cd093 | 2004-09-08 18:23:25 +0000 | [diff] [blame] | 2537 | case 4: opc = 0xDB; subopc_imm = 3; break; |
| 2538 | case 2: opc = 0xDF; subopc_imm = 3; break; |
| 2539 | default: vpanic("emitX86Instr(Xin_FpLdStI-store)"); |
| 2540 | } |
| 2541 | p = do_ffree_st7(p); |
| 2542 | p = do_fld_st(p, 0+hregNumber(i->Xin.FpLdStI.reg)); |
sewardj | 8ee8c88 | 2005-02-25 17:40:26 +0000 | [diff] [blame] | 2543 | *p++ = toUChar(opc); |
sewardj | 89cd093 | 2004-09-08 18:23:25 +0000 | [diff] [blame] | 2544 | p = doAMode_M(p, fake(subopc_imm)/*subopcode*/, i->Xin.FpLdStI.addr); |
| 2545 | goto done; |
| 2546 | } |
| 2547 | break; |
| 2548 | |
sewardj | 3bca906 | 2004-12-04 14:36:09 +0000 | [diff] [blame] | 2549 | case Xin_Fp64to32: |
| 2550 | /* ffree %st7 ; fld %st(src) */ |
| 2551 | p = do_ffree_st7(p); |
| 2552 | p = do_fld_st(p, 0+fregNo(i->Xin.Fp64to32.src)); |
| 2553 | /* subl $4, %esp */ |
| 2554 | *p++ = 0x83; *p++ = 0xEC; *p++ = 0x04; |
| 2555 | /* fstps (%esp) */ |
| 2556 | *p++ = 0xD9; *p++ = 0x1C; *p++ = 0x24; |
| 2557 | /* flds (%esp) */ |
| 2558 | *p++ = 0xD9; *p++ = 0x04; *p++ = 0x24; |
| 2559 | /* addl $4, %esp */ |
| 2560 | *p++ = 0x83; *p++ = 0xC4; *p++ = 0x04; |
| 2561 | /* fstp %st(1+dst) */ |
| 2562 | p = do_fstp_st(p, 1+fregNo(i->Xin.Fp64to32.dst)); |
| 2563 | goto done; |
| 2564 | |
sewardj | 3fc76d2 | 2004-08-31 11:47:54 +0000 | [diff] [blame] | 2565 | case Xin_FpCMov: |
| 2566 | /* jmp fwds if !condition */ |
sewardj | 8ee8c88 | 2005-02-25 17:40:26 +0000 | [diff] [blame] | 2567 | *p++ = toUChar(0x70 + (i->Xin.FpCMov.cond ^ 1)); |
sewardj | 3fc76d2 | 2004-08-31 11:47:54 +0000 | [diff] [blame] | 2568 | *p++ = 0; /* # of bytes in the next bit, which we don't know yet */ |
| 2569 | ptmp = p; |
| 2570 | |
| 2571 | /* ffree %st7 ; fld %st(src) ; fstp %st(1+dst) */ |
| 2572 | p = do_ffree_st7(p); |
sewardj | bdc7d21 | 2004-09-09 02:46:40 +0000 | [diff] [blame] | 2573 | p = do_fld_st(p, 0+fregNo(i->Xin.FpCMov.src)); |
| 2574 | p = do_fstp_st(p, 1+fregNo(i->Xin.FpCMov.dst)); |
sewardj | 3fc76d2 | 2004-08-31 11:47:54 +0000 | [diff] [blame] | 2575 | |
| 2576 | /* Fill in the jump offset. */ |
sewardj | 8ee8c88 | 2005-02-25 17:40:26 +0000 | [diff] [blame] | 2577 | *(ptmp-1) = toUChar(p - ptmp); |
sewardj | 3fc76d2 | 2004-08-31 11:47:54 +0000 | [diff] [blame] | 2578 | goto done; |
| 2579 | |
sewardj | eba63f8 | 2005-02-23 13:31:25 +0000 | [diff] [blame] | 2580 | case Xin_FpLdCW: |
| 2581 | *p++ = 0xD9; |
| 2582 | p = doAMode_M(p, fake(5)/*subopcode*/, i->Xin.FpLdCW.addr); |
sewardj | 8f3debf | 2004-09-08 23:42:23 +0000 | [diff] [blame] | 2583 | goto done; |
| 2584 | |
sewardj | 46de407 | 2004-09-11 19:23:24 +0000 | [diff] [blame] | 2585 | case Xin_FpStSW_AX: |
| 2586 | /* note, this emits fnstsw %ax, not fstsw %ax */ |
| 2587 | *p++ = 0xDF; |
| 2588 | *p++ = 0xE0; |
| 2589 | goto done; |
sewardj | bdc7d21 | 2004-09-09 02:46:40 +0000 | [diff] [blame] | 2590 | |
| 2591 | case Xin_FpCmp: |
| 2592 | /* gcmp %fL, %fR, %dst |
| 2593 | -> ffree %st7; fpush %fL ; fucomp %(fR+1) ; |
| 2594 | fnstsw %ax ; movl %eax, %dst |
| 2595 | */ |
| 2596 | /* ffree %st7 */ |
| 2597 | p = do_ffree_st7(p); |
| 2598 | /* fpush %fL */ |
| 2599 | p = do_fld_st(p, 0+fregNo(i->Xin.FpCmp.srcL)); |
| 2600 | /* fucomp %(fR+1) */ |
| 2601 | *p++ = 0xDD; |
sewardj | 8ee8c88 | 2005-02-25 17:40:26 +0000 | [diff] [blame] | 2602 | *p++ = toUChar(0xE8 + (7 & (1+fregNo(i->Xin.FpCmp.srcR)))); |
sewardj | bdc7d21 | 2004-09-09 02:46:40 +0000 | [diff] [blame] | 2603 | /* fnstsw %ax */ |
| 2604 | *p++ = 0xDF; |
| 2605 | *p++ = 0xE0; |
| 2606 | /* movl %eax, %dst */ |
| 2607 | *p++ = 0x89; |
| 2608 | p = doAMode_R(p, hregX86_EAX(), i->Xin.FpCmp.dst); |
| 2609 | goto done; |
| 2610 | |
sewardj | 1e6ad74 | 2004-12-02 16:16:11 +0000 | [diff] [blame] | 2611 | case Xin_SseConst: { |
| 2612 | UShort con = i->Xin.SseConst.con; |
sewardj | 8ee8c88 | 2005-02-25 17:40:26 +0000 | [diff] [blame] | 2613 | p = push_word_from_tags(p, toUShort((con >> 12) & 0xF)); |
| 2614 | p = push_word_from_tags(p, toUShort((con >> 8) & 0xF)); |
| 2615 | p = push_word_from_tags(p, toUShort((con >> 4) & 0xF)); |
| 2616 | p = push_word_from_tags(p, toUShort(con & 0xF)); |
sewardj | 1e6ad74 | 2004-12-02 16:16:11 +0000 | [diff] [blame] | 2617 | /* movl (%esp), %xmm-dst */ |
| 2618 | *p++ = 0x0F; |
| 2619 | *p++ = 0x10; |
sewardj | 8ee8c88 | 2005-02-25 17:40:26 +0000 | [diff] [blame] | 2620 | *p++ = toUChar(0x04 + 8 * (7 & vregNo(i->Xin.SseConst.dst))); |
sewardj | 1e6ad74 | 2004-12-02 16:16:11 +0000 | [diff] [blame] | 2621 | *p++ = 0x24; |
| 2622 | /* addl $16, %esp */ |
| 2623 | *p++ = 0x83; |
| 2624 | *p++ = 0xC4; |
| 2625 | *p++ = 0x10; |
| 2626 | goto done; |
| 2627 | } |
sewardj | 129b3d9 | 2004-12-05 15:42:05 +0000 | [diff] [blame] | 2628 | |
sewardj | d08f2d7 | 2004-12-01 23:19:36 +0000 | [diff] [blame] | 2629 | case Xin_SseLdSt: |
| 2630 | *p++ = 0x0F; |
sewardj | 8ee8c88 | 2005-02-25 17:40:26 +0000 | [diff] [blame] | 2631 | *p++ = toUChar(i->Xin.SseLdSt.isLoad ? 0x10 : 0x11); |
sewardj | d08f2d7 | 2004-12-01 23:19:36 +0000 | [diff] [blame] | 2632 | p = doAMode_M(p, fake(vregNo(i->Xin.SseLdSt.reg)), i->Xin.SseLdSt.addr); |
| 2633 | goto done; |
| 2634 | |
sewardj | 129b3d9 | 2004-12-05 15:42:05 +0000 | [diff] [blame] | 2635 | case Xin_SseLdzLO: |
sewardj | 636ad76 | 2004-12-07 11:16:04 +0000 | [diff] [blame] | 2636 | vassert(i->Xin.SseLdzLO.sz == 4 || i->Xin.SseLdzLO.sz == 8); |
| 2637 | /* movs[sd] amode, %xmm-dst */ |
sewardj | 8ee8c88 | 2005-02-25 17:40:26 +0000 | [diff] [blame] | 2638 | *p++ = toUChar(i->Xin.SseLdzLO.sz==4 ? 0xF3 : 0xF2); |
sewardj | 636ad76 | 2004-12-07 11:16:04 +0000 | [diff] [blame] | 2639 | *p++ = 0x0F; |
| 2640 | *p++ = 0x10; |
| 2641 | p = doAMode_M(p, fake(vregNo(i->Xin.SseLdzLO.reg)), |
| 2642 | i->Xin.SseLdzLO.addr); |
| 2643 | goto done; |
sewardj | 129b3d9 | 2004-12-05 15:42:05 +0000 | [diff] [blame] | 2644 | |
sewardj | 1e6ad74 | 2004-12-02 16:16:11 +0000 | [diff] [blame] | 2645 | case Xin_Sse32Fx4: |
| 2646 | xtra = 0; |
| 2647 | *p++ = 0x0F; |
| 2648 | switch (i->Xin.Sse32Fx4.op) { |
| 2649 | case Xsse_ADDF: *p++ = 0x58; break; |
sewardj | 176a59c | 2004-12-03 20:08:31 +0000 | [diff] [blame] | 2650 | case Xsse_DIVF: *p++ = 0x5E; break; |
| 2651 | case Xsse_MAXF: *p++ = 0x5F; break; |
| 2652 | case Xsse_MINF: *p++ = 0x5D; break; |
sewardj | 9636b44 | 2004-12-04 01:38:37 +0000 | [diff] [blame] | 2653 | case Xsse_MULF: *p++ = 0x59; break; |
sewardj | 0bd7ce6 | 2004-12-05 02:47:40 +0000 | [diff] [blame] | 2654 | case Xsse_RCPF: *p++ = 0x53; break; |
sewardj | c1e7dfc | 2004-12-05 19:29:45 +0000 | [diff] [blame] | 2655 | case Xsse_RSQRTF: *p++ = 0x52; break; |
| 2656 | case Xsse_SQRTF: *p++ = 0x51; break; |
| 2657 | case Xsse_SUBF: *p++ = 0x5C; break; |
sewardj | 1e6ad74 | 2004-12-02 16:16:11 +0000 | [diff] [blame] | 2658 | case Xsse_CMPEQF: *p++ = 0xC2; xtra = 0x100; break; |
| 2659 | case Xsse_CMPLTF: *p++ = 0xC2; xtra = 0x101; break; |
| 2660 | case Xsse_CMPLEF: *p++ = 0xC2; xtra = 0x102; break; |
sewardj | a26f661 | 2005-11-05 01:54:07 +0000 | [diff] [blame] | 2661 | case Xsse_CMPUNF: *p++ = 0xC2; xtra = 0x103; break; |
sewardj | 1e6ad74 | 2004-12-02 16:16:11 +0000 | [diff] [blame] | 2662 | default: goto bad; |
| 2663 | } |
sewardj | d08f2d7 | 2004-12-01 23:19:36 +0000 | [diff] [blame] | 2664 | p = doAMode_R(p, fake(vregNo(i->Xin.Sse32Fx4.dst)), |
| 2665 | fake(vregNo(i->Xin.Sse32Fx4.src)) ); |
sewardj | 1e6ad74 | 2004-12-02 16:16:11 +0000 | [diff] [blame] | 2666 | if (xtra & 0x100) |
sewardj | 8ee8c88 | 2005-02-25 17:40:26 +0000 | [diff] [blame] | 2667 | *p++ = toUChar(xtra & 0xFF); |
sewardj | 1e6ad74 | 2004-12-02 16:16:11 +0000 | [diff] [blame] | 2668 | goto done; |
| 2669 | |
sewardj | 636ad76 | 2004-12-07 11:16:04 +0000 | [diff] [blame] | 2670 | case Xin_Sse64Fx2: |
| 2671 | xtra = 0; |
| 2672 | *p++ = 0x66; |
| 2673 | *p++ = 0x0F; |
| 2674 | switch (i->Xin.Sse64Fx2.op) { |
| 2675 | case Xsse_ADDF: *p++ = 0x58; break; |
| 2676 | case Xsse_DIVF: *p++ = 0x5E; break; |
| 2677 | case Xsse_MAXF: *p++ = 0x5F; break; |
| 2678 | case Xsse_MINF: *p++ = 0x5D; break; |
| 2679 | case Xsse_MULF: *p++ = 0x59; break; |
| 2680 | case Xsse_RCPF: *p++ = 0x53; break; |
| 2681 | case Xsse_RSQRTF: *p++ = 0x52; break; |
| 2682 | case Xsse_SQRTF: *p++ = 0x51; break; |
| 2683 | case Xsse_SUBF: *p++ = 0x5C; break; |
| 2684 | case Xsse_CMPEQF: *p++ = 0xC2; xtra = 0x100; break; |
| 2685 | case Xsse_CMPLTF: *p++ = 0xC2; xtra = 0x101; break; |
| 2686 | case Xsse_CMPLEF: *p++ = 0xC2; xtra = 0x102; break; |
sewardj | a26f661 | 2005-11-05 01:54:07 +0000 | [diff] [blame] | 2687 | case Xsse_CMPUNF: *p++ = 0xC2; xtra = 0x103; break; |
sewardj | 636ad76 | 2004-12-07 11:16:04 +0000 | [diff] [blame] | 2688 | default: goto bad; |
| 2689 | } |
| 2690 | p = doAMode_R(p, fake(vregNo(i->Xin.Sse64Fx2.dst)), |
| 2691 | fake(vregNo(i->Xin.Sse64Fx2.src)) ); |
| 2692 | if (xtra & 0x100) |
sewardj | 8ee8c88 | 2005-02-25 17:40:26 +0000 | [diff] [blame] | 2693 | *p++ = toUChar(xtra & 0xFF); |
sewardj | 636ad76 | 2004-12-07 11:16:04 +0000 | [diff] [blame] | 2694 | goto done; |
| 2695 | |
sewardj | 1e6ad74 | 2004-12-02 16:16:11 +0000 | [diff] [blame] | 2696 | case Xin_Sse32FLo: |
| 2697 | xtra = 0; |
| 2698 | *p++ = 0xF3; |
| 2699 | *p++ = 0x0F; |
| 2700 | switch (i->Xin.Sse32FLo.op) { |
| 2701 | case Xsse_ADDF: *p++ = 0x58; break; |
sewardj | 176a59c | 2004-12-03 20:08:31 +0000 | [diff] [blame] | 2702 | case Xsse_DIVF: *p++ = 0x5E; break; |
| 2703 | case Xsse_MAXF: *p++ = 0x5F; break; |
| 2704 | case Xsse_MINF: *p++ = 0x5D; break; |
sewardj | 9636b44 | 2004-12-04 01:38:37 +0000 | [diff] [blame] | 2705 | case Xsse_MULF: *p++ = 0x59; break; |
sewardj | 0bd7ce6 | 2004-12-05 02:47:40 +0000 | [diff] [blame] | 2706 | case Xsse_RCPF: *p++ = 0x53; break; |
sewardj | c1e7dfc | 2004-12-05 19:29:45 +0000 | [diff] [blame] | 2707 | case Xsse_RSQRTF: *p++ = 0x52; break; |
| 2708 | case Xsse_SQRTF: *p++ = 0x51; break; |
| 2709 | case Xsse_SUBF: *p++ = 0x5C; break; |
sewardj | 1e6ad74 | 2004-12-02 16:16:11 +0000 | [diff] [blame] | 2710 | case Xsse_CMPEQF: *p++ = 0xC2; xtra = 0x100; break; |
| 2711 | case Xsse_CMPLTF: *p++ = 0xC2; xtra = 0x101; break; |
| 2712 | case Xsse_CMPLEF: *p++ = 0xC2; xtra = 0x102; break; |
sewardj | a26f661 | 2005-11-05 01:54:07 +0000 | [diff] [blame] | 2713 | case Xsse_CMPUNF: *p++ = 0xC2; xtra = 0x103; break; |
sewardj | 1e6ad74 | 2004-12-02 16:16:11 +0000 | [diff] [blame] | 2714 | default: goto bad; |
| 2715 | } |
| 2716 | p = doAMode_R(p, fake(vregNo(i->Xin.Sse32FLo.dst)), |
| 2717 | fake(vregNo(i->Xin.Sse32FLo.src)) ); |
| 2718 | if (xtra & 0x100) |
sewardj | 8ee8c88 | 2005-02-25 17:40:26 +0000 | [diff] [blame] | 2719 | *p++ = toUChar(xtra & 0xFF); |
sewardj | d08f2d7 | 2004-12-01 23:19:36 +0000 | [diff] [blame] | 2720 | goto done; |
| 2721 | |
sewardj | 636ad76 | 2004-12-07 11:16:04 +0000 | [diff] [blame] | 2722 | case Xin_Sse64FLo: |
| 2723 | xtra = 0; |
| 2724 | *p++ = 0xF2; |
| 2725 | *p++ = 0x0F; |
| 2726 | switch (i->Xin.Sse64FLo.op) { |
| 2727 | case Xsse_ADDF: *p++ = 0x58; break; |
| 2728 | case Xsse_DIVF: *p++ = 0x5E; break; |
| 2729 | case Xsse_MAXF: *p++ = 0x5F; break; |
| 2730 | case Xsse_MINF: *p++ = 0x5D; break; |
| 2731 | case Xsse_MULF: *p++ = 0x59; break; |
| 2732 | case Xsse_RCPF: *p++ = 0x53; break; |
| 2733 | case Xsse_RSQRTF: *p++ = 0x52; break; |
| 2734 | case Xsse_SQRTF: *p++ = 0x51; break; |
| 2735 | case Xsse_SUBF: *p++ = 0x5C; break; |
| 2736 | case Xsse_CMPEQF: *p++ = 0xC2; xtra = 0x100; break; |
| 2737 | case Xsse_CMPLTF: *p++ = 0xC2; xtra = 0x101; break; |
| 2738 | case Xsse_CMPLEF: *p++ = 0xC2; xtra = 0x102; break; |
sewardj | a26f661 | 2005-11-05 01:54:07 +0000 | [diff] [blame] | 2739 | case Xsse_CMPUNF: *p++ = 0xC2; xtra = 0x103; break; |
sewardj | 636ad76 | 2004-12-07 11:16:04 +0000 | [diff] [blame] | 2740 | default: goto bad; |
| 2741 | } |
| 2742 | p = doAMode_R(p, fake(vregNo(i->Xin.Sse64FLo.dst)), |
| 2743 | fake(vregNo(i->Xin.Sse64FLo.src)) ); |
| 2744 | if (xtra & 0x100) |
sewardj | 8ee8c88 | 2005-02-25 17:40:26 +0000 | [diff] [blame] | 2745 | *p++ = toUChar(xtra & 0xFF); |
sewardj | 636ad76 | 2004-12-07 11:16:04 +0000 | [diff] [blame] | 2746 | goto done; |
| 2747 | |
sewardj | 164f927 | 2004-12-09 00:39:32 +0000 | [diff] [blame] | 2748 | case Xin_SseReRg: |
| 2749 | # define XX(_n) *p++ = (_n) |
| 2750 | switch (i->Xin.SseReRg.op) { |
sewardj | 9e20359 | 2004-12-10 01:48:18 +0000 | [diff] [blame] | 2751 | case Xsse_MOV: /*movups*/ XX(0x0F); XX(0x10); break; |
| 2752 | case Xsse_OR: XX(0x0F); XX(0x56); break; |
| 2753 | case Xsse_XOR: XX(0x0F); XX(0x57); break; |
| 2754 | case Xsse_AND: XX(0x0F); XX(0x54); break; |
sewardj | e5854d6 | 2004-12-09 03:44:34 +0000 | [diff] [blame] | 2755 | case Xsse_PACKSSD: XX(0x66); XX(0x0F); XX(0x6B); break; |
| 2756 | case Xsse_PACKSSW: XX(0x66); XX(0x0F); XX(0x63); break; |
| 2757 | case Xsse_PACKUSW: XX(0x66); XX(0x0F); XX(0x67); break; |
| 2758 | case Xsse_ADD8: XX(0x66); XX(0x0F); XX(0xFC); break; |
| 2759 | case Xsse_ADD16: XX(0x66); XX(0x0F); XX(0xFD); break; |
| 2760 | case Xsse_ADD32: XX(0x66); XX(0x0F); XX(0xFE); break; |
| 2761 | case Xsse_ADD64: XX(0x66); XX(0x0F); XX(0xD4); break; |
| 2762 | case Xsse_QADD8S: XX(0x66); XX(0x0F); XX(0xEC); break; |
| 2763 | case Xsse_QADD16S: XX(0x66); XX(0x0F); XX(0xED); break; |
| 2764 | case Xsse_QADD8U: XX(0x66); XX(0x0F); XX(0xDC); break; |
| 2765 | case Xsse_QADD16U: XX(0x66); XX(0x0F); XX(0xDD); break; |
| 2766 | case Xsse_AVG8U: XX(0x66); XX(0x0F); XX(0xE0); break; |
| 2767 | case Xsse_AVG16U: XX(0x66); XX(0x0F); XX(0xE3); break; |
| 2768 | case Xsse_CMPEQ8: XX(0x66); XX(0x0F); XX(0x74); break; |
| 2769 | case Xsse_CMPEQ16: XX(0x66); XX(0x0F); XX(0x75); break; |
| 2770 | case Xsse_CMPEQ32: XX(0x66); XX(0x0F); XX(0x76); break; |
| 2771 | case Xsse_CMPGT8S: XX(0x66); XX(0x0F); XX(0x64); break; |
| 2772 | case Xsse_CMPGT16S: XX(0x66); XX(0x0F); XX(0x65); break; |
| 2773 | case Xsse_CMPGT32S: XX(0x66); XX(0x0F); XX(0x66); break; |
| 2774 | case Xsse_MAX16S: XX(0x66); XX(0x0F); XX(0xEE); break; |
| 2775 | case Xsse_MAX8U: XX(0x66); XX(0x0F); XX(0xDE); break; |
| 2776 | case Xsse_MIN16S: XX(0x66); XX(0x0F); XX(0xEA); break; |
| 2777 | case Xsse_MIN8U: XX(0x66); XX(0x0F); XX(0xDA); break; |
| 2778 | case Xsse_MULHI16U: XX(0x66); XX(0x0F); XX(0xE4); break; |
| 2779 | case Xsse_MULHI16S: XX(0x66); XX(0x0F); XX(0xE5); break; |
| 2780 | case Xsse_MUL16: XX(0x66); XX(0x0F); XX(0xD5); break; |
sewardj | b9fa69b | 2004-12-09 23:25:14 +0000 | [diff] [blame] | 2781 | case Xsse_SHL16: XX(0x66); XX(0x0F); XX(0xF1); break; |
| 2782 | case Xsse_SHL32: XX(0x66); XX(0x0F); XX(0xF2); break; |
| 2783 | case Xsse_SHL64: XX(0x66); XX(0x0F); XX(0xF3); break; |
| 2784 | case Xsse_SAR16: XX(0x66); XX(0x0F); XX(0xE1); break; |
| 2785 | case Xsse_SAR32: XX(0x66); XX(0x0F); XX(0xE2); break; |
| 2786 | case Xsse_SHR16: XX(0x66); XX(0x0F); XX(0xD1); break; |
| 2787 | case Xsse_SHR32: XX(0x66); XX(0x0F); XX(0xD2); break; |
| 2788 | case Xsse_SHR64: XX(0x66); XX(0x0F); XX(0xD3); break; |
| 2789 | case Xsse_SUB8: XX(0x66); XX(0x0F); XX(0xF8); break; |
| 2790 | case Xsse_SUB16: XX(0x66); XX(0x0F); XX(0xF9); break; |
| 2791 | case Xsse_SUB32: XX(0x66); XX(0x0F); XX(0xFA); break; |
| 2792 | case Xsse_SUB64: XX(0x66); XX(0x0F); XX(0xFB); break; |
| 2793 | case Xsse_QSUB8S: XX(0x66); XX(0x0F); XX(0xE8); break; |
| 2794 | case Xsse_QSUB16S: XX(0x66); XX(0x0F); XX(0xE9); break; |
| 2795 | case Xsse_QSUB8U: XX(0x66); XX(0x0F); XX(0xD8); break; |
| 2796 | case Xsse_QSUB16U: XX(0x66); XX(0x0F); XX(0xD9); break; |
sewardj | 9e20359 | 2004-12-10 01:48:18 +0000 | [diff] [blame] | 2797 | case Xsse_UNPCKHB: XX(0x66); XX(0x0F); XX(0x68); break; |
| 2798 | case Xsse_UNPCKHW: XX(0x66); XX(0x0F); XX(0x69); break; |
| 2799 | case Xsse_UNPCKHD: XX(0x66); XX(0x0F); XX(0x6A); break; |
| 2800 | case Xsse_UNPCKHQ: XX(0x66); XX(0x0F); XX(0x6D); break; |
| 2801 | case Xsse_UNPCKLB: XX(0x66); XX(0x0F); XX(0x60); break; |
| 2802 | case Xsse_UNPCKLW: XX(0x66); XX(0x0F); XX(0x61); break; |
| 2803 | case Xsse_UNPCKLD: XX(0x66); XX(0x0F); XX(0x62); break; |
| 2804 | case Xsse_UNPCKLQ: XX(0x66); XX(0x0F); XX(0x6C); break; |
sewardj | 164f927 | 2004-12-09 00:39:32 +0000 | [diff] [blame] | 2805 | default: goto bad; |
| 2806 | } |
| 2807 | p = doAMode_R(p, fake(vregNo(i->Xin.SseReRg.dst)), |
| 2808 | fake(vregNo(i->Xin.SseReRg.src)) ); |
| 2809 | # undef XX |
| 2810 | goto done; |
| 2811 | |
sewardj | b9fa69b | 2004-12-09 23:25:14 +0000 | [diff] [blame] | 2812 | case Xin_SseCMov: |
| 2813 | /* jmp fwds if !condition */ |
sewardj | 8ee8c88 | 2005-02-25 17:40:26 +0000 | [diff] [blame] | 2814 | *p++ = toUChar(0x70 + (i->Xin.SseCMov.cond ^ 1)); |
sewardj | b9fa69b | 2004-12-09 23:25:14 +0000 | [diff] [blame] | 2815 | *p++ = 0; /* # of bytes in the next bit, which we don't know yet */ |
| 2816 | ptmp = p; |
| 2817 | |
| 2818 | /* movaps %src, %dst */ |
| 2819 | *p++ = 0x0F; |
| 2820 | *p++ = 0x28; |
| 2821 | p = doAMode_R(p, fake(vregNo(i->Xin.SseCMov.dst)), |
| 2822 | fake(vregNo(i->Xin.SseCMov.src)) ); |
| 2823 | |
| 2824 | /* Fill in the jump offset. */ |
sewardj | 8ee8c88 | 2005-02-25 17:40:26 +0000 | [diff] [blame] | 2825 | *(ptmp-1) = toUChar(p - ptmp); |
sewardj | b9fa69b | 2004-12-09 23:25:14 +0000 | [diff] [blame] | 2826 | goto done; |
| 2827 | |
sewardj | 109ffdb | 2004-12-10 21:45:38 +0000 | [diff] [blame] | 2828 | case Xin_SseShuf: |
| 2829 | *p++ = 0x66; |
| 2830 | *p++ = 0x0F; |
| 2831 | *p++ = 0x70; |
| 2832 | p = doAMode_R(p, fake(vregNo(i->Xin.SseShuf.dst)), |
| 2833 | fake(vregNo(i->Xin.SseShuf.src)) ); |
| 2834 | *p++ = (UChar)(i->Xin.SseShuf.order); |
| 2835 | goto done; |
| 2836 | |
sewardj | ea64e14 | 2004-07-22 16:47:21 +0000 | [diff] [blame] | 2837 | default: |
| 2838 | goto bad; |
sewardj | 81bd550 | 2004-07-21 18:49:27 +0000 | [diff] [blame] | 2839 | } |
sewardj | ea64e14 | 2004-07-22 16:47:21 +0000 | [diff] [blame] | 2840 | |
| 2841 | bad: |
cerion | 92b6436 | 2005-12-13 12:02:26 +0000 | [diff] [blame] | 2842 | ppX86Instr(i, mode64); |
sewardj | ea64e14 | 2004-07-22 16:47:21 +0000 | [diff] [blame] | 2843 | vpanic("emit_X86Instr"); |
| 2844 | /*NOTREACHED*/ |
| 2845 | |
sewardj | bad34a9 | 2004-07-22 01:14:11 +0000 | [diff] [blame] | 2846 | done: |
| 2847 | vassert(p - &buf[0] <= 32); |
| 2848 | return p - &buf[0]; |
sewardj | ea64e14 | 2004-07-22 16:47:21 +0000 | [diff] [blame] | 2849 | |
sewardj | d75fe5a | 2004-07-23 12:57:47 +0000 | [diff] [blame] | 2850 | # undef fake |
sewardj | 81bd550 | 2004-07-21 18:49:27 +0000 | [diff] [blame] | 2851 | } |
| 2852 | |
sewardj | 35421a3 | 2004-07-05 13:12:34 +0000 | [diff] [blame] | 2853 | /*---------------------------------------------------------------*/ |
sewardj | c0ee2ed | 2004-07-27 10:29:41 +0000 | [diff] [blame] | 2854 | /*--- end host-x86/hdefs.c ---*/ |
sewardj | 35421a3 | 2004-07-05 13:12:34 +0000 | [diff] [blame] | 2855 | /*---------------------------------------------------------------*/ |