bart | 09dc13f | 2009-02-14 15:13:31 +0000 | [diff] [blame] | 1 | /* |
bart | 86562bd | 2009-02-16 19:43:56 +0000 | [diff] [blame] | 2 | This file is part of drd, a thread error detector. |
bart | 09dc13f | 2009-02-14 15:13:31 +0000 | [diff] [blame] | 3 | |
bart | 922304f | 2011-03-13 12:02:44 +0000 | [diff] [blame] | 4 | Copyright (C) 2006-2011 Bart Van Assche <bvanassche@acm.org>. |
bart | 09dc13f | 2009-02-14 15:13:31 +0000 | [diff] [blame] | 5 | |
| 6 | This program is free software; you can redistribute it and/or |
| 7 | modify it under the terms of the GNU General Public License as |
| 8 | published by the Free Software Foundation; either version 2 of the |
| 9 | License, or (at your option) any later version. |
| 10 | |
| 11 | This program is distributed in the hope that it will be useful, but |
| 12 | WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
| 14 | General Public License for more details. |
| 15 | |
| 16 | You should have received a copy of the GNU General Public License |
| 17 | along with this program; if not, write to the Free Software |
| 18 | Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA |
| 19 | 02111-1307, USA. |
| 20 | |
| 21 | The GNU General Public License is contained in the file COPYING. |
| 22 | */ |
| 23 | |
| 24 | |
| 25 | #include "drd_bitmap.h" |
| 26 | #include "drd_thread_bitmap.h" |
bart | 41b226c | 2009-02-14 16:55:19 +0000 | [diff] [blame] | 27 | #include "drd_vc.h" /* DRD_(vc_snprint)() */ |
bart | 09dc13f | 2009-02-14 15:13:31 +0000 | [diff] [blame] | 28 | |
| 29 | /* Include several source files here in order to allow the compiler to */ |
| 30 | /* do more inlining. */ |
| 31 | #include "drd_bitmap.c" |
| 32 | #include "drd_load_store.h" |
| 33 | #include "drd_segment.c" |
| 34 | #include "drd_thread.c" |
| 35 | #include "drd_vc.c" |
| 36 | #include "libvex_guest_offsets.h" |
| 37 | |
| 38 | |
| 39 | /* STACK_POINTER_OFFSET: VEX register offset for the stack pointer register. */ |
| 40 | #if defined(VGA_x86) |
| 41 | #define STACK_POINTER_OFFSET OFFSET_x86_ESP |
| 42 | #elif defined(VGA_amd64) |
| 43 | #define STACK_POINTER_OFFSET OFFSET_amd64_RSP |
| 44 | #elif defined(VGA_ppc32) |
sewardj | 4cb6bf7 | 2010-01-01 18:31:41 +0000 | [diff] [blame] | 45 | #define STACK_POINTER_OFFSET OFFSET_ppc32_GPR1 |
bart | 09dc13f | 2009-02-14 15:13:31 +0000 | [diff] [blame] | 46 | #elif defined(VGA_ppc64) |
sewardj | 4cb6bf7 | 2010-01-01 18:31:41 +0000 | [diff] [blame] | 47 | #define STACK_POINTER_OFFSET OFFSET_ppc64_GPR1 |
| 48 | #elif defined(VGA_arm) |
| 49 | #define STACK_POINTER_OFFSET OFFSET_arm_R13 |
sewardj | b5b8740 | 2011-03-07 16:05:35 +0000 | [diff] [blame] | 50 | #elif defined(VGA_s390x) |
| 51 | #define STACK_POINTER_OFFSET OFFSET_s390x_r15 |
bart | 09dc13f | 2009-02-14 15:13:31 +0000 | [diff] [blame] | 52 | #else |
| 53 | #error Unknown architecture. |
| 54 | #endif |
| 55 | |
| 56 | |
| 57 | /* Local variables. */ |
| 58 | |
bart | f98a569 | 2009-05-03 17:17:37 +0000 | [diff] [blame] | 59 | static Bool s_check_stack_accesses = False; |
| 60 | static Bool s_first_race_only = False; |
bart | 09dc13f | 2009-02-14 15:13:31 +0000 | [diff] [blame] | 61 | |
| 62 | |
| 63 | /* Function definitions. */ |
| 64 | |
| 65 | Bool DRD_(get_check_stack_accesses)() |
| 66 | { |
bart | f98a569 | 2009-05-03 17:17:37 +0000 | [diff] [blame] | 67 | return s_check_stack_accesses; |
bart | 09dc13f | 2009-02-14 15:13:31 +0000 | [diff] [blame] | 68 | } |
| 69 | |
| 70 | void DRD_(set_check_stack_accesses)(const Bool c) |
| 71 | { |
bart | bedfd23 | 2009-03-26 19:07:15 +0000 | [diff] [blame] | 72 | tl_assert(c == False || c == True); |
bart | f98a569 | 2009-05-03 17:17:37 +0000 | [diff] [blame] | 73 | s_check_stack_accesses = c; |
| 74 | } |
| 75 | |
| 76 | Bool DRD_(get_first_race_only)() |
| 77 | { |
| 78 | return s_first_race_only; |
| 79 | } |
| 80 | |
| 81 | void DRD_(set_first_race_only)(const Bool fro) |
| 82 | { |
| 83 | tl_assert(fro == False || fro == True); |
| 84 | s_first_race_only = fro; |
bart | 09dc13f | 2009-02-14 15:13:31 +0000 | [diff] [blame] | 85 | } |
| 86 | |
bart | 1335ecc | 2009-02-14 16:10:53 +0000 | [diff] [blame] | 87 | void DRD_(trace_mem_access)(const Addr addr, const SizeT size, |
bart | 7826acb | 2011-12-11 18:49:39 +0000 | [diff] [blame] | 88 | const BmAccessTypeT access_type, |
bart | 42f3263 | 2011-12-13 11:12:05 +0000 | [diff] [blame] | 89 | const HWord stored_value_hi, |
| 90 | const HWord stored_value_lo) |
bart | 09dc13f | 2009-02-14 15:13:31 +0000 | [diff] [blame] | 91 | { |
bart | bedfd23 | 2009-03-26 19:07:15 +0000 | [diff] [blame] | 92 | if (DRD_(is_any_traced)(addr, addr + size)) |
| 93 | { |
bart | 8f822af | 2009-06-08 18:20:42 +0000 | [diff] [blame] | 94 | char* vc; |
| 95 | |
| 96 | vc = DRD_(vc_aprint)(DRD_(thread_get_vc)(DRD_(thread_get_running_tid)())); |
bart | 7826acb | 2011-12-11 18:49:39 +0000 | [diff] [blame] | 97 | if (access_type == eStore && size <= sizeof(HWord)) { |
bart | 5cda1b5 | 2011-12-12 19:37:10 +0000 | [diff] [blame] | 98 | DRD_(trace_msg_w_bt)("store 0x%lx size %ld val %ld/0x%lx (thread %d /" |
bart | 42f3263 | 2011-12-13 11:12:05 +0000 | [diff] [blame] | 99 | " vc %s)", addr, size, stored_value_lo, |
| 100 | stored_value_lo, DRD_(thread_get_running_tid)(), |
| 101 | vc); |
| 102 | } else if (access_type == eStore && size > sizeof(HWord)) { |
| 103 | ULong sv; |
| 104 | |
| 105 | tl_assert(sizeof(HWord) == 4); |
| 106 | sv = ((ULong)stored_value_hi << 32) | stored_value_lo; |
| 107 | DRD_(trace_msg_w_bt)("store 0x%lx size %ld val %lld/0x%llx (thread %d" |
| 108 | " / vc %s)", addr, size, sv, sv, |
bart | 7826acb | 2011-12-11 18:49:39 +0000 | [diff] [blame] | 109 | DRD_(thread_get_running_tid)(), vc); |
| 110 | } else { |
| 111 | DRD_(trace_msg_w_bt)("%s 0x%lx size %ld (thread %d / vc %s)", |
| 112 | access_type == eLoad ? "load " |
| 113 | : access_type == eStore ? "store" |
| 114 | : access_type == eStart ? "start" |
| 115 | : access_type == eEnd ? "end " : "????", |
| 116 | addr, size, DRD_(thread_get_running_tid)(), vc); |
| 117 | } |
bart | 8f822af | 2009-06-08 18:20:42 +0000 | [diff] [blame] | 118 | VG_(free)(vc); |
bart | bedfd23 | 2009-03-26 19:07:15 +0000 | [diff] [blame] | 119 | tl_assert(DRD_(DrdThreadIdToVgThreadId)(DRD_(thread_get_running_tid)()) |
| 120 | == VG_(get_running_tid)()); |
| 121 | } |
bart | 09dc13f | 2009-02-14 15:13:31 +0000 | [diff] [blame] | 122 | } |
| 123 | |
bart | 0759503 | 2010-08-29 09:51:06 +0000 | [diff] [blame] | 124 | static VG_REGPARM(2) void drd_trace_mem_load(const Addr addr, const SizeT size) |
bart | 09dc13f | 2009-02-14 15:13:31 +0000 | [diff] [blame] | 125 | { |
bart | 42f3263 | 2011-12-13 11:12:05 +0000 | [diff] [blame] | 126 | return DRD_(trace_mem_access)(addr, size, eLoad, 0, 0); |
bart | 09dc13f | 2009-02-14 15:13:31 +0000 | [diff] [blame] | 127 | } |
| 128 | |
bart | 7826acb | 2011-12-11 18:49:39 +0000 | [diff] [blame] | 129 | static VG_REGPARM(3) void drd_trace_mem_store(const Addr addr,const SizeT size, |
bart | 42f3263 | 2011-12-13 11:12:05 +0000 | [diff] [blame] | 130 | const HWord stored_value_hi, |
| 131 | const HWord stored_value_lo) |
bart | 09dc13f | 2009-02-14 15:13:31 +0000 | [diff] [blame] | 132 | { |
bart | 42f3263 | 2011-12-13 11:12:05 +0000 | [diff] [blame] | 133 | return DRD_(trace_mem_access)(addr, size, eStore, stored_value_hi, |
| 134 | stored_value_lo); |
bart | 09dc13f | 2009-02-14 15:13:31 +0000 | [diff] [blame] | 135 | } |
| 136 | |
| 137 | static void drd_report_race(const Addr addr, const SizeT size, |
| 138 | const BmAccessTypeT access_type) |
| 139 | { |
bart | bedfd23 | 2009-03-26 19:07:15 +0000 | [diff] [blame] | 140 | DataRaceErrInfo drei; |
bart | 09dc13f | 2009-02-14 15:13:31 +0000 | [diff] [blame] | 141 | |
bart | bedfd23 | 2009-03-26 19:07:15 +0000 | [diff] [blame] | 142 | drei.tid = DRD_(thread_get_running_tid)(); |
| 143 | drei.addr = addr; |
| 144 | drei.size = size; |
| 145 | drei.access_type = access_type; |
| 146 | VG_(maybe_record_error)(VG_(get_running_tid)(), |
| 147 | DataRaceErr, |
| 148 | VG_(get_IP)(VG_(get_running_tid)()), |
bart | 74b2d97 | 2011-10-08 08:54:57 +0000 | [diff] [blame] | 149 | "Conflicting access", |
bart | bedfd23 | 2009-03-26 19:07:15 +0000 | [diff] [blame] | 150 | &drei); |
bart | f98a569 | 2009-05-03 17:17:37 +0000 | [diff] [blame] | 151 | |
| 152 | if (s_first_race_only) |
| 153 | { |
| 154 | DRD_(start_suppression)(addr, addr + size, "first race only"); |
| 155 | } |
bart | 09dc13f | 2009-02-14 15:13:31 +0000 | [diff] [blame] | 156 | } |
| 157 | |
bart | 99edb29 | 2009-02-15 15:59:20 +0000 | [diff] [blame] | 158 | VG_REGPARM(2) void DRD_(trace_load)(Addr addr, SizeT size) |
bart | 09dc13f | 2009-02-14 15:13:31 +0000 | [diff] [blame] | 159 | { |
| 160 | #ifdef ENABLE_DRD_CONSISTENCY_CHECKS |
bart | bedfd23 | 2009-03-26 19:07:15 +0000 | [diff] [blame] | 161 | /* The assert below has been commented out because of performance reasons.*/ |
bart | d5bbc61 | 2010-09-02 14:44:17 +0000 | [diff] [blame] | 162 | tl_assert(DRD_(thread_get_running_tid)() |
| 163 | == DRD_(VgThreadIdToDrdThreadId)(VG_(get_running_tid()))); |
bart | 09dc13f | 2009-02-14 15:13:31 +0000 | [diff] [blame] | 164 | #endif |
| 165 | |
bart | d45d995 | 2009-05-31 18:53:54 +0000 | [diff] [blame] | 166 | if (DRD_(running_thread_is_recording_loads)() |
bart | f98a569 | 2009-05-03 17:17:37 +0000 | [diff] [blame] | 167 | && (s_check_stack_accesses |
bart | bedfd23 | 2009-03-26 19:07:15 +0000 | [diff] [blame] | 168 | || ! DRD_(thread_address_on_stack)(addr)) |
| 169 | && bm_access_load_triggers_conflict(addr, addr + size) |
| 170 | && ! DRD_(is_suppressed)(addr, addr + size)) |
| 171 | { |
| 172 | drd_report_race(addr, size, eLoad); |
| 173 | } |
bart | 09dc13f | 2009-02-14 15:13:31 +0000 | [diff] [blame] | 174 | } |
| 175 | |
| 176 | static VG_REGPARM(1) void drd_trace_load_1(Addr addr) |
| 177 | { |
bart | d45d995 | 2009-05-31 18:53:54 +0000 | [diff] [blame] | 178 | if (DRD_(running_thread_is_recording_loads)() |
bart | f98a569 | 2009-05-03 17:17:37 +0000 | [diff] [blame] | 179 | && (s_check_stack_accesses |
bart | bedfd23 | 2009-03-26 19:07:15 +0000 | [diff] [blame] | 180 | || ! DRD_(thread_address_on_stack)(addr)) |
| 181 | && bm_access_load_1_triggers_conflict(addr) |
| 182 | && ! DRD_(is_suppressed)(addr, addr + 1)) |
| 183 | { |
| 184 | drd_report_race(addr, 1, eLoad); |
| 185 | } |
bart | 09dc13f | 2009-02-14 15:13:31 +0000 | [diff] [blame] | 186 | } |
| 187 | |
| 188 | static VG_REGPARM(1) void drd_trace_load_2(Addr addr) |
| 189 | { |
bart | d45d995 | 2009-05-31 18:53:54 +0000 | [diff] [blame] | 190 | if (DRD_(running_thread_is_recording_loads)() |
bart | f98a569 | 2009-05-03 17:17:37 +0000 | [diff] [blame] | 191 | && (s_check_stack_accesses |
bart | bedfd23 | 2009-03-26 19:07:15 +0000 | [diff] [blame] | 192 | || ! DRD_(thread_address_on_stack)(addr)) |
| 193 | && bm_access_load_2_triggers_conflict(addr) |
| 194 | && ! DRD_(is_suppressed)(addr, addr + 2)) |
| 195 | { |
| 196 | drd_report_race(addr, 2, eLoad); |
| 197 | } |
bart | 09dc13f | 2009-02-14 15:13:31 +0000 | [diff] [blame] | 198 | } |
| 199 | |
| 200 | static VG_REGPARM(1) void drd_trace_load_4(Addr addr) |
| 201 | { |
bart | d45d995 | 2009-05-31 18:53:54 +0000 | [diff] [blame] | 202 | if (DRD_(running_thread_is_recording_loads)() |
bart | f98a569 | 2009-05-03 17:17:37 +0000 | [diff] [blame] | 203 | && (s_check_stack_accesses |
bart | bedfd23 | 2009-03-26 19:07:15 +0000 | [diff] [blame] | 204 | || ! DRD_(thread_address_on_stack)(addr)) |
| 205 | && bm_access_load_4_triggers_conflict(addr) |
| 206 | && ! DRD_(is_suppressed)(addr, addr + 4)) |
| 207 | { |
| 208 | drd_report_race(addr, 4, eLoad); |
| 209 | } |
bart | 09dc13f | 2009-02-14 15:13:31 +0000 | [diff] [blame] | 210 | } |
| 211 | |
| 212 | static VG_REGPARM(1) void drd_trace_load_8(Addr addr) |
| 213 | { |
bart | d45d995 | 2009-05-31 18:53:54 +0000 | [diff] [blame] | 214 | if (DRD_(running_thread_is_recording_loads)() |
bart | f98a569 | 2009-05-03 17:17:37 +0000 | [diff] [blame] | 215 | && (s_check_stack_accesses |
bart | bedfd23 | 2009-03-26 19:07:15 +0000 | [diff] [blame] | 216 | || ! DRD_(thread_address_on_stack)(addr)) |
| 217 | && bm_access_load_8_triggers_conflict(addr) |
| 218 | && ! DRD_(is_suppressed)(addr, addr + 8)) |
| 219 | { |
| 220 | drd_report_race(addr, 8, eLoad); |
| 221 | } |
bart | 09dc13f | 2009-02-14 15:13:31 +0000 | [diff] [blame] | 222 | } |
| 223 | |
bart | 99edb29 | 2009-02-15 15:59:20 +0000 | [diff] [blame] | 224 | VG_REGPARM(2) void DRD_(trace_store)(Addr addr, SizeT size) |
bart | 09dc13f | 2009-02-14 15:13:31 +0000 | [diff] [blame] | 225 | { |
| 226 | #ifdef ENABLE_DRD_CONSISTENCY_CHECKS |
bart | bedfd23 | 2009-03-26 19:07:15 +0000 | [diff] [blame] | 227 | /* The assert below has been commented out because of performance reasons.*/ |
bart | d5bbc61 | 2010-09-02 14:44:17 +0000 | [diff] [blame] | 228 | tl_assert(DRD_(thread_get_running_tid)() |
| 229 | == DRD_(VgThreadIdToDrdThreadId)(VG_(get_running_tid()))); |
bart | 09dc13f | 2009-02-14 15:13:31 +0000 | [diff] [blame] | 230 | #endif |
| 231 | |
bart | d45d995 | 2009-05-31 18:53:54 +0000 | [diff] [blame] | 232 | if (DRD_(running_thread_is_recording_stores)() |
bart | f98a569 | 2009-05-03 17:17:37 +0000 | [diff] [blame] | 233 | && (s_check_stack_accesses |
bart | bedfd23 | 2009-03-26 19:07:15 +0000 | [diff] [blame] | 234 | || ! DRD_(thread_address_on_stack)(addr)) |
| 235 | && bm_access_store_triggers_conflict(addr, addr + size) |
| 236 | && ! DRD_(is_suppressed)(addr, addr + size)) |
| 237 | { |
| 238 | drd_report_race(addr, size, eStore); |
| 239 | } |
bart | 09dc13f | 2009-02-14 15:13:31 +0000 | [diff] [blame] | 240 | } |
| 241 | |
| 242 | static VG_REGPARM(1) void drd_trace_store_1(Addr addr) |
| 243 | { |
bart | d45d995 | 2009-05-31 18:53:54 +0000 | [diff] [blame] | 244 | if (DRD_(running_thread_is_recording_stores)() |
bart | f98a569 | 2009-05-03 17:17:37 +0000 | [diff] [blame] | 245 | && (s_check_stack_accesses |
bart | bedfd23 | 2009-03-26 19:07:15 +0000 | [diff] [blame] | 246 | || ! DRD_(thread_address_on_stack)(addr)) |
| 247 | && bm_access_store_1_triggers_conflict(addr) |
| 248 | && ! DRD_(is_suppressed)(addr, addr + 1)) |
| 249 | { |
| 250 | drd_report_race(addr, 1, eStore); |
| 251 | } |
bart | 09dc13f | 2009-02-14 15:13:31 +0000 | [diff] [blame] | 252 | } |
| 253 | |
| 254 | static VG_REGPARM(1) void drd_trace_store_2(Addr addr) |
| 255 | { |
bart | d45d995 | 2009-05-31 18:53:54 +0000 | [diff] [blame] | 256 | if (DRD_(running_thread_is_recording_stores)() |
bart | f98a569 | 2009-05-03 17:17:37 +0000 | [diff] [blame] | 257 | && (s_check_stack_accesses |
bart | bedfd23 | 2009-03-26 19:07:15 +0000 | [diff] [blame] | 258 | || ! DRD_(thread_address_on_stack)(addr)) |
| 259 | && bm_access_store_2_triggers_conflict(addr) |
| 260 | && ! DRD_(is_suppressed)(addr, addr + 2)) |
| 261 | { |
| 262 | drd_report_race(addr, 2, eStore); |
| 263 | } |
bart | 09dc13f | 2009-02-14 15:13:31 +0000 | [diff] [blame] | 264 | } |
| 265 | |
| 266 | static VG_REGPARM(1) void drd_trace_store_4(Addr addr) |
| 267 | { |
bart | d45d995 | 2009-05-31 18:53:54 +0000 | [diff] [blame] | 268 | if (DRD_(running_thread_is_recording_stores)() |
bart | f98a569 | 2009-05-03 17:17:37 +0000 | [diff] [blame] | 269 | && (s_check_stack_accesses |
bart | 71ce132 | 2011-12-11 17:54:17 +0000 | [diff] [blame] | 270 | || !DRD_(thread_address_on_stack)(addr)) |
bart | bedfd23 | 2009-03-26 19:07:15 +0000 | [diff] [blame] | 271 | && bm_access_store_4_triggers_conflict(addr) |
bart | 71ce132 | 2011-12-11 17:54:17 +0000 | [diff] [blame] | 272 | && !DRD_(is_suppressed)(addr, addr + 4)) |
bart | bedfd23 | 2009-03-26 19:07:15 +0000 | [diff] [blame] | 273 | { |
| 274 | drd_report_race(addr, 4, eStore); |
| 275 | } |
bart | 09dc13f | 2009-02-14 15:13:31 +0000 | [diff] [blame] | 276 | } |
| 277 | |
| 278 | static VG_REGPARM(1) void drd_trace_store_8(Addr addr) |
| 279 | { |
bart | d45d995 | 2009-05-31 18:53:54 +0000 | [diff] [blame] | 280 | if (DRD_(running_thread_is_recording_stores)() |
bart | f98a569 | 2009-05-03 17:17:37 +0000 | [diff] [blame] | 281 | && (s_check_stack_accesses |
bart | bedfd23 | 2009-03-26 19:07:15 +0000 | [diff] [blame] | 282 | || ! DRD_(thread_address_on_stack)(addr)) |
| 283 | && bm_access_store_8_triggers_conflict(addr) |
| 284 | && ! DRD_(is_suppressed)(addr, addr + 8)) |
| 285 | { |
| 286 | drd_report_race(addr, 8, eStore); |
| 287 | } |
bart | 09dc13f | 2009-02-14 15:13:31 +0000 | [diff] [blame] | 288 | } |
| 289 | |
| 290 | /** |
| 291 | * Return true if and only if addr_expr matches the pattern (SP) or |
| 292 | * <offset>(SP). |
| 293 | */ |
| 294 | static Bool is_stack_access(IRSB* const bb, IRExpr* const addr_expr) |
| 295 | { |
bart | bedfd23 | 2009-03-26 19:07:15 +0000 | [diff] [blame] | 296 | Bool result = False; |
bart | 09dc13f | 2009-02-14 15:13:31 +0000 | [diff] [blame] | 297 | |
bart | bedfd23 | 2009-03-26 19:07:15 +0000 | [diff] [blame] | 298 | if (addr_expr->tag == Iex_RdTmp) |
| 299 | { |
| 300 | int i; |
| 301 | for (i = 0; i < bb->stmts_size; i++) |
bart | 09dc13f | 2009-02-14 15:13:31 +0000 | [diff] [blame] | 302 | { |
bart | bedfd23 | 2009-03-26 19:07:15 +0000 | [diff] [blame] | 303 | if (bb->stmts[i] |
| 304 | && bb->stmts[i]->tag == Ist_WrTmp |
| 305 | && bb->stmts[i]->Ist.WrTmp.tmp == addr_expr->Iex.RdTmp.tmp) |
| 306 | { |
| 307 | IRExpr* e = bb->stmts[i]->Ist.WrTmp.data; |
| 308 | if (e->tag == Iex_Get && e->Iex.Get.offset == STACK_POINTER_OFFSET) |
| 309 | { |
| 310 | result = True; |
| 311 | } |
bart | 09dc13f | 2009-02-14 15:13:31 +0000 | [diff] [blame] | 312 | |
bart | bedfd23 | 2009-03-26 19:07:15 +0000 | [diff] [blame] | 313 | //ppIRExpr(e); |
| 314 | //VG_(printf)(" (%s)\n", result ? "True" : "False"); |
| 315 | break; |
| 316 | } |
bart | 09dc13f | 2009-02-14 15:13:31 +0000 | [diff] [blame] | 317 | } |
bart | bedfd23 | 2009-03-26 19:07:15 +0000 | [diff] [blame] | 318 | } |
| 319 | return result; |
bart | 09dc13f | 2009-02-14 15:13:31 +0000 | [diff] [blame] | 320 | } |
| 321 | |
bart | ea69215 | 2011-12-11 20:17:57 +0000 | [diff] [blame] | 322 | static const IROp u_widen_irop[5][9] = { |
bart | 9ad8d80 | 2011-12-12 19:54:32 +0000 | [diff] [blame] | 323 | [Ity_I1 - Ity_I1] = { [4] = Iop_1Uto32, [8] = Iop_1Uto64 }, |
| 324 | [Ity_I8 - Ity_I1] = { [4] = Iop_8Uto32, [8] = Iop_8Uto64 }, |
| 325 | [Ity_I16 - Ity_I1] = { [4] = Iop_16Uto32, [8] = Iop_16Uto64 }, |
| 326 | [Ity_I32 - Ity_I1] = { [8] = Iop_32Uto64 }, |
bart | ea69215 | 2011-12-11 20:17:57 +0000 | [diff] [blame] | 327 | }; |
| 328 | |
bart | b63dc78 | 2011-12-12 19:18:26 +0000 | [diff] [blame] | 329 | /** |
| 330 | * Instrument the client code to trace a memory load (--trace-addr). |
| 331 | */ |
bart | 25026ef | 2011-12-17 12:59:45 +0000 | [diff] [blame^] | 332 | static IRExpr* instr_trace_mem_load(IRSB* const bb, IRExpr* addr_expr, |
| 333 | const HWord size) |
bart | ea69215 | 2011-12-11 20:17:57 +0000 | [diff] [blame] | 334 | { |
bart | 25026ef | 2011-12-17 12:59:45 +0000 | [diff] [blame^] | 335 | IRTemp tmp; |
| 336 | |
| 337 | tmp = newIRTemp(bb->tyenv, typeOfIRExpr(bb->tyenv, addr_expr)); |
| 338 | addStmtToIRSB(bb, IRStmt_WrTmp(tmp, addr_expr)); |
| 339 | addr_expr = IRExpr_RdTmp(tmp); |
| 340 | |
bart | b63dc78 | 2011-12-12 19:18:26 +0000 | [diff] [blame] | 341 | addStmtToIRSB(bb, |
| 342 | IRStmt_Dirty( |
| 343 | unsafeIRDirty_0_N(/*regparms*/2, |
| 344 | "drd_trace_mem_load", |
| 345 | VG_(fnptr_to_fnentry) |
| 346 | (drd_trace_mem_load), |
| 347 | mkIRExprVec_2(addr_expr, mkIRExpr_HWord(size))))); |
bart | 25026ef | 2011-12-17 12:59:45 +0000 | [diff] [blame^] | 348 | |
| 349 | return addr_expr; |
bart | b63dc78 | 2011-12-12 19:18:26 +0000 | [diff] [blame] | 350 | } |
| 351 | |
| 352 | /** |
| 353 | * Instrument the client code to trace a memory store (--trace-addr). |
| 354 | */ |
| 355 | static void instr_trace_mem_store(IRSB* const bb, IRExpr* const addr_expr, |
bart | 42f3263 | 2011-12-13 11:12:05 +0000 | [diff] [blame] | 356 | IRExpr* data_expr_hi, IRExpr* data_expr_lo) |
bart | b63dc78 | 2011-12-12 19:18:26 +0000 | [diff] [blame] | 357 | { |
| 358 | IRType ty_data_expr; |
bart | ea69215 | 2011-12-11 20:17:57 +0000 | [diff] [blame] | 359 | HWord size; |
| 360 | |
bart | b63dc78 | 2011-12-12 19:18:26 +0000 | [diff] [blame] | 361 | tl_assert(sizeof(HWord) == 4 || sizeof(HWord) == 8); |
bart | 42f3263 | 2011-12-13 11:12:05 +0000 | [diff] [blame] | 362 | tl_assert(!data_expr_hi || typeOfIRExpr(bb->tyenv, data_expr_hi) == Ity_I32); |
bart | ea69215 | 2011-12-11 20:17:57 +0000 | [diff] [blame] | 363 | |
bart | 42f3263 | 2011-12-13 11:12:05 +0000 | [diff] [blame] | 364 | ty_data_expr = typeOfIRExpr(bb->tyenv, data_expr_lo); |
bart | b63dc78 | 2011-12-12 19:18:26 +0000 | [diff] [blame] | 365 | size = sizeofIRType(ty_data_expr); |
| 366 | |
bart | 7ca75ed | 2011-12-13 08:53:23 +0000 | [diff] [blame] | 367 | #if 0 |
| 368 | // Test code |
| 369 | if (ty_data_expr == Ity_I32) { |
| 370 | IRTemp tmp = newIRTemp(bb->tyenv, Ity_F32); |
bart | 42f3263 | 2011-12-13 11:12:05 +0000 | [diff] [blame] | 371 | data_expr_lo = IRExpr_Unop(Iop_ReinterpI32asF32, data_expr_lo); |
| 372 | addStmtToIRSB(bb, IRStmt_WrTmp(tmp, data_expr_lo)); |
| 373 | data_expr_lo = IRExpr_RdTmp(tmp); |
bart | 7ca75ed | 2011-12-13 08:53:23 +0000 | [diff] [blame] | 374 | ty_data_expr = Ity_F32; |
| 375 | } else if (ty_data_expr == Ity_I64) { |
| 376 | IRTemp tmp = newIRTemp(bb->tyenv, Ity_F64); |
bart | 42f3263 | 2011-12-13 11:12:05 +0000 | [diff] [blame] | 377 | data_expr_lo = IRExpr_Unop(Iop_ReinterpI64asF64, data_expr_lo); |
| 378 | addStmtToIRSB(bb, IRStmt_WrTmp(tmp, data_expr_lo)); |
| 379 | data_expr_lo = IRExpr_RdTmp(tmp); |
bart | 7ca75ed | 2011-12-13 08:53:23 +0000 | [diff] [blame] | 380 | ty_data_expr = Ity_F64; |
| 381 | } |
| 382 | #endif |
| 383 | |
| 384 | if (ty_data_expr == Ity_F32) { |
| 385 | IRTemp tmp = newIRTemp(bb->tyenv, Ity_I32); |
| 386 | addStmtToIRSB(bb, IRStmt_WrTmp(tmp, IRExpr_Unop(Iop_ReinterpF32asI32, |
bart | 42f3263 | 2011-12-13 11:12:05 +0000 | [diff] [blame] | 387 | data_expr_lo))); |
| 388 | data_expr_lo = IRExpr_RdTmp(tmp); |
bart | 7ca75ed | 2011-12-13 08:53:23 +0000 | [diff] [blame] | 389 | ty_data_expr = Ity_I32; |
| 390 | } else if (ty_data_expr == Ity_F64) { |
| 391 | IRTemp tmp = newIRTemp(bb->tyenv, Ity_I64); |
| 392 | addStmtToIRSB(bb, IRStmt_WrTmp(tmp, IRExpr_Unop(Iop_ReinterpF64asI64, |
bart | 42f3263 | 2011-12-13 11:12:05 +0000 | [diff] [blame] | 393 | data_expr_lo))); |
| 394 | data_expr_lo = IRExpr_RdTmp(tmp); |
bart | 7ca75ed | 2011-12-13 08:53:23 +0000 | [diff] [blame] | 395 | ty_data_expr = Ity_I64; |
| 396 | } |
| 397 | |
bart | b63dc78 | 2011-12-12 19:18:26 +0000 | [diff] [blame] | 398 | if (size == sizeof(HWord) |
| 399 | && (ty_data_expr == Ity_I32 || ty_data_expr == Ity_I64)) |
| 400 | { |
| 401 | /* No conversion necessary */ |
bart | ea69215 | 2011-12-11 20:17:57 +0000 | [diff] [blame] | 402 | } else { |
| 403 | IROp widen_op; |
| 404 | |
bart | b63dc78 | 2011-12-12 19:18:26 +0000 | [diff] [blame] | 405 | if (Ity_I1 <= ty_data_expr |
| 406 | && ty_data_expr |
| 407 | < Ity_I1 + sizeof(u_widen_irop)/sizeof(u_widen_irop[0])) |
| 408 | { |
| 409 | widen_op = u_widen_irop[ty_data_expr - Ity_I1][sizeof(HWord)]; |
bart | ea69215 | 2011-12-11 20:17:57 +0000 | [diff] [blame] | 410 | if (!widen_op) |
| 411 | widen_op = Iop_INVALID; |
| 412 | } else { |
| 413 | widen_op = Iop_INVALID; |
| 414 | } |
| 415 | if (widen_op != Iop_INVALID) { |
| 416 | IRTemp tmp; |
| 417 | |
bart | b63dc78 | 2011-12-12 19:18:26 +0000 | [diff] [blame] | 418 | /* Widen the integer expression to a HWord */ |
bart | ea69215 | 2011-12-11 20:17:57 +0000 | [diff] [blame] | 419 | tmp = newIRTemp(bb->tyenv, sizeof(HWord) == 4 ? Ity_I32 : Ity_I64); |
| 420 | addStmtToIRSB(bb, |
bart | 42f3263 | 2011-12-13 11:12:05 +0000 | [diff] [blame] | 421 | IRStmt_WrTmp(tmp, IRExpr_Unop(widen_op, data_expr_lo))); |
| 422 | data_expr_lo = IRExpr_RdTmp(tmp); |
| 423 | } else if (size > sizeof(HWord) && !data_expr_hi |
| 424 | && ty_data_expr == Ity_I64) { |
| 425 | IRTemp tmp; |
| 426 | |
| 427 | tl_assert(sizeof(HWord) == 4); |
| 428 | tl_assert(size == 8); |
| 429 | tmp = newIRTemp(bb->tyenv, Ity_I32); |
| 430 | addStmtToIRSB(bb, |
| 431 | IRStmt_WrTmp(tmp, |
| 432 | IRExpr_Unop(Iop_64HIto32, data_expr_lo))); |
| 433 | data_expr_hi = IRExpr_RdTmp(tmp); |
| 434 | tmp = newIRTemp(bb->tyenv, Ity_I32); |
| 435 | addStmtToIRSB(bb, IRStmt_WrTmp(tmp, |
| 436 | IRExpr_Unop(Iop_64to32, data_expr_lo))); |
| 437 | data_expr_lo = IRExpr_RdTmp(tmp); |
bart | ea69215 | 2011-12-11 20:17:57 +0000 | [diff] [blame] | 438 | } else { |
bart | 42f3263 | 2011-12-13 11:12:05 +0000 | [diff] [blame] | 439 | data_expr_lo = mkIRExpr_HWord(0); |
bart | ea69215 | 2011-12-11 20:17:57 +0000 | [diff] [blame] | 440 | } |
| 441 | } |
| 442 | addStmtToIRSB(bb, |
| 443 | IRStmt_Dirty( |
| 444 | unsafeIRDirty_0_N(/*regparms*/3, |
| 445 | "drd_trace_mem_store", |
bart | 42f3263 | 2011-12-13 11:12:05 +0000 | [diff] [blame] | 446 | VG_(fnptr_to_fnentry)(drd_trace_mem_store), |
| 447 | mkIRExprVec_4(addr_expr, mkIRExpr_HWord(size), |
| 448 | data_expr_hi ? data_expr_hi |
| 449 | : mkIRExpr_HWord(0), data_expr_lo)))); |
bart | ea69215 | 2011-12-11 20:17:57 +0000 | [diff] [blame] | 450 | } |
| 451 | |
| 452 | static void instrument_load(IRSB* const bb, IRExpr* const addr_expr, |
bart | b63dc78 | 2011-12-12 19:18:26 +0000 | [diff] [blame] | 453 | const HWord size) |
bart | 09dc13f | 2009-02-14 15:13:31 +0000 | [diff] [blame] | 454 | { |
bart | bedfd23 | 2009-03-26 19:07:15 +0000 | [diff] [blame] | 455 | IRExpr* size_expr; |
| 456 | IRExpr** argv; |
| 457 | IRDirty* di; |
bart | 09dc13f | 2009-02-14 15:13:31 +0000 | [diff] [blame] | 458 | |
bart | ea69215 | 2011-12-11 20:17:57 +0000 | [diff] [blame] | 459 | if (!s_check_stack_accesses && is_stack_access(bb, addr_expr)) |
bart | bedfd23 | 2009-03-26 19:07:15 +0000 | [diff] [blame] | 460 | return; |
bart | 09dc13f | 2009-02-14 15:13:31 +0000 | [diff] [blame] | 461 | |
bart | bedfd23 | 2009-03-26 19:07:15 +0000 | [diff] [blame] | 462 | switch (size) |
| 463 | { |
| 464 | case 1: |
| 465 | argv = mkIRExprVec_1(addr_expr); |
| 466 | di = unsafeIRDirty_0_N(/*regparms*/1, |
| 467 | "drd_trace_load_1", |
| 468 | VG_(fnptr_to_fnentry)(drd_trace_load_1), |
| 469 | argv); |
| 470 | break; |
| 471 | case 2: |
| 472 | argv = mkIRExprVec_1(addr_expr); |
| 473 | di = unsafeIRDirty_0_N(/*regparms*/1, |
| 474 | "drd_trace_load_2", |
| 475 | VG_(fnptr_to_fnentry)(drd_trace_load_2), |
| 476 | argv); |
| 477 | break; |
| 478 | case 4: |
| 479 | argv = mkIRExprVec_1(addr_expr); |
| 480 | di = unsafeIRDirty_0_N(/*regparms*/1, |
| 481 | "drd_trace_load_4", |
| 482 | VG_(fnptr_to_fnentry)(drd_trace_load_4), |
| 483 | argv); |
| 484 | break; |
| 485 | case 8: |
| 486 | argv = mkIRExprVec_1(addr_expr); |
| 487 | di = unsafeIRDirty_0_N(/*regparms*/1, |
| 488 | "drd_trace_load_8", |
| 489 | VG_(fnptr_to_fnentry)(drd_trace_load_8), |
| 490 | argv); |
| 491 | break; |
| 492 | default: |
| 493 | size_expr = mkIRExpr_HWord(size); |
| 494 | argv = mkIRExprVec_2(addr_expr, size_expr); |
| 495 | di = unsafeIRDirty_0_N(/*regparms*/2, |
| 496 | "drd_trace_load", |
| 497 | VG_(fnptr_to_fnentry)(DRD_(trace_load)), |
| 498 | argv); |
| 499 | break; |
| 500 | } |
| 501 | addStmtToIRSB(bb, IRStmt_Dirty(di)); |
bart | 09dc13f | 2009-02-14 15:13:31 +0000 | [diff] [blame] | 502 | } |
| 503 | |
bart | 25026ef | 2011-12-17 12:59:45 +0000 | [diff] [blame^] | 504 | static void instrument_store(IRSB* const bb, IRExpr* addr_expr, |
bart | 7826acb | 2011-12-11 18:49:39 +0000 | [diff] [blame] | 505 | IRExpr* const data_expr) |
bart | 09dc13f | 2009-02-14 15:13:31 +0000 | [diff] [blame] | 506 | { |
bart | bedfd23 | 2009-03-26 19:07:15 +0000 | [diff] [blame] | 507 | IRExpr* size_expr; |
| 508 | IRExpr** argv; |
| 509 | IRDirty* di; |
bart | 7826acb | 2011-12-11 18:49:39 +0000 | [diff] [blame] | 510 | HWord size; |
| 511 | |
| 512 | size = sizeofIRType(typeOfIRExpr(bb->tyenv, data_expr)); |
bart | 09dc13f | 2009-02-14 15:13:31 +0000 | [diff] [blame] | 513 | |
bart | 25026ef | 2011-12-17 12:59:45 +0000 | [diff] [blame^] | 514 | if (UNLIKELY(DRD_(any_address_is_traced)())) { |
| 515 | IRTemp tmp = newIRTemp(bb->tyenv, typeOfIRExpr(bb->tyenv, addr_expr)); |
| 516 | addStmtToIRSB(bb, IRStmt_WrTmp(tmp, addr_expr)); |
| 517 | addr_expr = IRExpr_RdTmp(tmp); |
bart | 42f3263 | 2011-12-13 11:12:05 +0000 | [diff] [blame] | 518 | instr_trace_mem_store(bb, addr_expr, NULL, data_expr); |
bart | 25026ef | 2011-12-17 12:59:45 +0000 | [diff] [blame^] | 519 | } |
bart | 09dc13f | 2009-02-14 15:13:31 +0000 | [diff] [blame] | 520 | |
bart | 71ce132 | 2011-12-11 17:54:17 +0000 | [diff] [blame] | 521 | if (!s_check_stack_accesses && is_stack_access(bb, addr_expr)) |
bart | bedfd23 | 2009-03-26 19:07:15 +0000 | [diff] [blame] | 522 | return; |
bart | 09dc13f | 2009-02-14 15:13:31 +0000 | [diff] [blame] | 523 | |
bart | bedfd23 | 2009-03-26 19:07:15 +0000 | [diff] [blame] | 524 | switch (size) |
| 525 | { |
| 526 | case 1: |
| 527 | argv = mkIRExprVec_1(addr_expr); |
| 528 | di = unsafeIRDirty_0_N(/*regparms*/1, |
| 529 | "drd_trace_store_1", |
| 530 | VG_(fnptr_to_fnentry)(drd_trace_store_1), |
| 531 | argv); |
| 532 | break; |
| 533 | case 2: |
| 534 | argv = mkIRExprVec_1(addr_expr); |
| 535 | di = unsafeIRDirty_0_N(/*regparms*/1, |
| 536 | "drd_trace_store_2", |
| 537 | VG_(fnptr_to_fnentry)(drd_trace_store_2), |
| 538 | argv); |
| 539 | break; |
| 540 | case 4: |
| 541 | argv = mkIRExprVec_1(addr_expr); |
| 542 | di = unsafeIRDirty_0_N(/*regparms*/1, |
| 543 | "drd_trace_store_4", |
| 544 | VG_(fnptr_to_fnentry)(drd_trace_store_4), |
| 545 | argv); |
| 546 | break; |
| 547 | case 8: |
| 548 | argv = mkIRExprVec_1(addr_expr); |
| 549 | di = unsafeIRDirty_0_N(/*regparms*/1, |
| 550 | "drd_trace_store_8", |
| 551 | VG_(fnptr_to_fnentry)(drd_trace_store_8), |
| 552 | argv); |
| 553 | break; |
| 554 | default: |
| 555 | size_expr = mkIRExpr_HWord(size); |
| 556 | argv = mkIRExprVec_2(addr_expr, size_expr); |
| 557 | di = unsafeIRDirty_0_N(/*regparms*/2, |
| 558 | "drd_trace_store", |
| 559 | VG_(fnptr_to_fnentry)(DRD_(trace_store)), |
| 560 | argv); |
| 561 | break; |
| 562 | } |
| 563 | addStmtToIRSB(bb, IRStmt_Dirty(di)); |
bart | 09dc13f | 2009-02-14 15:13:31 +0000 | [diff] [blame] | 564 | } |
| 565 | |
bart | 1335ecc | 2009-02-14 16:10:53 +0000 | [diff] [blame] | 566 | IRSB* DRD_(instrument)(VgCallbackClosure* const closure, |
bart | bedfd23 | 2009-03-26 19:07:15 +0000 | [diff] [blame] | 567 | IRSB* const bb_in, |
| 568 | VexGuestLayout* const layout, |
bart | 31b983d | 2010-02-21 14:52:59 +0000 | [diff] [blame] | 569 | VexGuestExtents* const vge, |
bart | bedfd23 | 2009-03-26 19:07:15 +0000 | [diff] [blame] | 570 | IRType const gWordTy, |
| 571 | IRType const hWordTy) |
bart | 09dc13f | 2009-02-14 15:13:31 +0000 | [diff] [blame] | 572 | { |
bart | bedfd23 | 2009-03-26 19:07:15 +0000 | [diff] [blame] | 573 | IRDirty* di; |
| 574 | Int i; |
| 575 | IRSB* bb; |
| 576 | IRExpr** argv; |
| 577 | Bool instrument = True; |
bart | 09dc13f | 2009-02-14 15:13:31 +0000 | [diff] [blame] | 578 | |
bart | bedfd23 | 2009-03-26 19:07:15 +0000 | [diff] [blame] | 579 | /* Set up BB */ |
| 580 | bb = emptyIRSB(); |
| 581 | bb->tyenv = deepCopyIRTypeEnv(bb_in->tyenv); |
| 582 | bb->next = deepCopyIRExpr(bb_in->next); |
| 583 | bb->jumpkind = bb_in->jumpkind; |
bart | 09dc13f | 2009-02-14 15:13:31 +0000 | [diff] [blame] | 584 | |
bart | bedfd23 | 2009-03-26 19:07:15 +0000 | [diff] [blame] | 585 | for (i = 0; i < bb_in->stmts_used; i++) |
| 586 | { |
| 587 | IRStmt* const st = bb_in->stmts[i]; |
| 588 | tl_assert(st); |
sewardj | db5907d | 2009-11-26 17:20:21 +0000 | [diff] [blame] | 589 | tl_assert(isFlatIRStmt(st)); |
bart | 09dc13f | 2009-02-14 15:13:31 +0000 | [diff] [blame] | 590 | |
bart | bedfd23 | 2009-03-26 19:07:15 +0000 | [diff] [blame] | 591 | switch (st->tag) |
bart | 09dc13f | 2009-02-14 15:13:31 +0000 | [diff] [blame] | 592 | { |
bart | bedfd23 | 2009-03-26 19:07:15 +0000 | [diff] [blame] | 593 | /* Note: the code for not instrumenting the code in .plt */ |
| 594 | /* sections is only necessary on CentOS 3.0 x86 (kernel 2.4.21 */ |
| 595 | /* + glibc 2.3.2 + NPTL 0.60 + binutils 2.14.90.0.4). */ |
| 596 | /* This is because on this platform dynamic library symbols are */ |
| 597 | /* relocated in another way than by later binutils versions. The */ |
| 598 | /* linker e.g. does not generate .got.plt sections on CentOS 3.0. */ |
| 599 | case Ist_IMark: |
sewardj | e3f1e59 | 2009-07-31 09:41:29 +0000 | [diff] [blame] | 600 | instrument = VG_(DebugInfo_sect_kind)(NULL, 0, st->Ist.IMark.addr) |
bart | bedfd23 | 2009-03-26 19:07:15 +0000 | [diff] [blame] | 601 | != Vg_SectPLT; |
| 602 | addStmtToIRSB(bb, st); |
| 603 | break; |
| 604 | |
| 605 | case Ist_MBE: |
| 606 | switch (st->Ist.MBE.event) |
| 607 | { |
| 608 | case Imbe_Fence: |
| 609 | break; /* not interesting */ |
bart | bedfd23 | 2009-03-26 19:07:15 +0000 | [diff] [blame] | 610 | default: |
| 611 | tl_assert(0); |
| 612 | } |
| 613 | addStmtToIRSB(bb, st); |
| 614 | break; |
| 615 | |
| 616 | case Ist_Store: |
sewardj | db5907d | 2009-11-26 17:20:21 +0000 | [diff] [blame] | 617 | if (instrument) |
bart | 7826acb | 2011-12-11 18:49:39 +0000 | [diff] [blame] | 618 | instrument_store(bb, st->Ist.Store.addr, st->Ist.Store.data); |
bart | bedfd23 | 2009-03-26 19:07:15 +0000 | [diff] [blame] | 619 | addStmtToIRSB(bb, st); |
| 620 | break; |
| 621 | |
| 622 | case Ist_WrTmp: |
bart | ea69215 | 2011-12-11 20:17:57 +0000 | [diff] [blame] | 623 | if (instrument) { |
bart | bedfd23 | 2009-03-26 19:07:15 +0000 | [diff] [blame] | 624 | const IRExpr* const data = st->Ist.WrTmp.data; |
bart | 25026ef | 2011-12-17 12:59:45 +0000 | [diff] [blame^] | 625 | IRExpr* addr_expr = data->Iex.Load.addr; |
bart | b63dc78 | 2011-12-12 19:18:26 +0000 | [diff] [blame] | 626 | if (data->tag == Iex_Load) { |
bart | 25026ef | 2011-12-17 12:59:45 +0000 | [diff] [blame^] | 627 | if (UNLIKELY(DRD_(any_address_is_traced)())) { |
| 628 | addr_expr = instr_trace_mem_load(bb, addr_expr, |
bart | b63dc78 | 2011-12-12 19:18:26 +0000 | [diff] [blame] | 629 | sizeofIRType(data->Iex.Load.ty)); |
bart | 25026ef | 2011-12-17 12:59:45 +0000 | [diff] [blame^] | 630 | } |
bart | ea69215 | 2011-12-11 20:17:57 +0000 | [diff] [blame] | 631 | instrument_load(bb, data->Iex.Load.addr, |
bart | b63dc78 | 2011-12-12 19:18:26 +0000 | [diff] [blame] | 632 | sizeofIRType(data->Iex.Load.ty)); |
| 633 | } |
bart | bedfd23 | 2009-03-26 19:07:15 +0000 | [diff] [blame] | 634 | } |
| 635 | addStmtToIRSB(bb, st); |
| 636 | break; |
| 637 | |
| 638 | case Ist_Dirty: |
bart | b63dc78 | 2011-12-12 19:18:26 +0000 | [diff] [blame] | 639 | if (instrument) { |
bart | bedfd23 | 2009-03-26 19:07:15 +0000 | [diff] [blame] | 640 | IRDirty* d = st->Ist.Dirty.details; |
| 641 | IREffect const mFx = d->mFx; |
| 642 | switch (mFx) { |
| 643 | case Ifx_None: |
| 644 | break; |
| 645 | case Ifx_Read: |
| 646 | case Ifx_Write: |
| 647 | case Ifx_Modify: |
| 648 | tl_assert(d->mAddr); |
| 649 | tl_assert(d->mSize > 0); |
| 650 | argv = mkIRExprVec_2(d->mAddr, mkIRExpr_HWord(d->mSize)); |
| 651 | if (mFx == Ifx_Read || mFx == Ifx_Modify) { |
| 652 | di = unsafeIRDirty_0_N( |
| 653 | /*regparms*/2, |
| 654 | "drd_trace_load", |
| 655 | VG_(fnptr_to_fnentry)(DRD_(trace_load)), |
| 656 | argv); |
| 657 | addStmtToIRSB(bb, IRStmt_Dirty(di)); |
| 658 | } |
sewardj | 1c0ce7a | 2009-07-01 08:10:49 +0000 | [diff] [blame] | 659 | if (mFx == Ifx_Write || mFx == Ifx_Modify) |
bart | bedfd23 | 2009-03-26 19:07:15 +0000 | [diff] [blame] | 660 | { |
| 661 | di = unsafeIRDirty_0_N( |
| 662 | /*regparms*/2, |
| 663 | "drd_trace_store", |
| 664 | VG_(fnptr_to_fnentry)(DRD_(trace_store)), |
| 665 | argv); |
| 666 | addStmtToIRSB(bb, IRStmt_Dirty(di)); |
| 667 | } |
| 668 | break; |
| 669 | default: |
| 670 | tl_assert(0); |
| 671 | } |
| 672 | } |
| 673 | addStmtToIRSB(bb, st); |
| 674 | break; |
| 675 | |
sewardj | 1c0ce7a | 2009-07-01 08:10:49 +0000 | [diff] [blame] | 676 | case Ist_CAS: |
bart | b63dc78 | 2011-12-12 19:18:26 +0000 | [diff] [blame] | 677 | if (instrument) { |
bart | a14e328 | 2009-07-11 14:35:59 +0000 | [diff] [blame] | 678 | /* |
| 679 | * Treat compare-and-swap as a read. By handling atomic |
| 680 | * instructions as read instructions no data races are reported |
| 681 | * between conflicting atomic operations nor between atomic |
| 682 | * operations and non-atomic reads. Conflicts between atomic |
| 683 | * operations and non-atomic write operations are still reported |
| 684 | * however. |
| 685 | */ |
sewardj | 1c0ce7a | 2009-07-01 08:10:49 +0000 | [diff] [blame] | 686 | Int dataSize; |
| 687 | IRCAS* cas = st->Ist.CAS.details; |
bart | b63dc78 | 2011-12-12 19:18:26 +0000 | [diff] [blame] | 688 | |
sewardj | 1c0ce7a | 2009-07-01 08:10:49 +0000 | [diff] [blame] | 689 | tl_assert(cas->addr != NULL); |
| 690 | tl_assert(cas->dataLo != NULL); |
| 691 | dataSize = sizeofIRType(typeOfIRExpr(bb->tyenv, cas->dataLo)); |
| 692 | if (cas->dataHi != NULL) |
| 693 | dataSize *= 2; /* since it's a doubleword-CAS */ |
bart | b63dc78 | 2011-12-12 19:18:26 +0000 | [diff] [blame] | 694 | |
bart | 42f3263 | 2011-12-13 11:12:05 +0000 | [diff] [blame] | 695 | if (UNLIKELY(DRD_(any_address_is_traced)())) |
| 696 | instr_trace_mem_store(bb, cas->addr, cas->dataHi, cas->dataLo); |
bart | b63dc78 | 2011-12-12 19:18:26 +0000 | [diff] [blame] | 697 | |
| 698 | instrument_load(bb, cas->addr, dataSize); |
sewardj | 1c0ce7a | 2009-07-01 08:10:49 +0000 | [diff] [blame] | 699 | } |
| 700 | addStmtToIRSB(bb, st); |
| 701 | break; |
| 702 | |
sewardj | db5907d | 2009-11-26 17:20:21 +0000 | [diff] [blame] | 703 | case Ist_LLSC: { |
bart | ea69215 | 2011-12-11 20:17:57 +0000 | [diff] [blame] | 704 | /* |
| 705 | * Ignore store-conditionals (except for tracing), and handle |
| 706 | * load-linked's exactly like normal loads. |
| 707 | */ |
sewardj | db5907d | 2009-11-26 17:20:21 +0000 | [diff] [blame] | 708 | IRType dataTy; |
bart | b63dc78 | 2011-12-12 19:18:26 +0000 | [diff] [blame] | 709 | |
bart | ea69215 | 2011-12-11 20:17:57 +0000 | [diff] [blame] | 710 | if (st->Ist.LLSC.storedata == NULL) { |
sewardj | db5907d | 2009-11-26 17:20:21 +0000 | [diff] [blame] | 711 | /* LL */ |
| 712 | dataTy = typeOfIRTemp(bb_in->tyenv, st->Ist.LLSC.result); |
bart | b63dc78 | 2011-12-12 19:18:26 +0000 | [diff] [blame] | 713 | if (instrument) { |
bart | 25026ef | 2011-12-17 12:59:45 +0000 | [diff] [blame^] | 714 | IRExpr* addr_expr = st->Ist.LLSC.addr; |
bart | b63dc78 | 2011-12-12 19:18:26 +0000 | [diff] [blame] | 715 | if (UNLIKELY(DRD_(any_address_is_traced)())) |
bart | 25026ef | 2011-12-17 12:59:45 +0000 | [diff] [blame^] | 716 | addr_expr = instr_trace_mem_load(bb, addr_expr, |
| 717 | sizeofIRType(dataTy)); |
bart | b63dc78 | 2011-12-12 19:18:26 +0000 | [diff] [blame] | 718 | |
bart | 25026ef | 2011-12-17 12:59:45 +0000 | [diff] [blame^] | 719 | instrument_load(bb, addr_expr, sizeofIRType(dataTy)); |
bart | b63dc78 | 2011-12-12 19:18:26 +0000 | [diff] [blame] | 720 | } |
bart | ea69215 | 2011-12-11 20:17:57 +0000 | [diff] [blame] | 721 | } else { |
sewardj | db5907d | 2009-11-26 17:20:21 +0000 | [diff] [blame] | 722 | /* SC */ |
bart | 42f3263 | 2011-12-13 11:12:05 +0000 | [diff] [blame] | 723 | instr_trace_mem_store(bb, st->Ist.LLSC.addr, NULL, |
bart | b63dc78 | 2011-12-12 19:18:26 +0000 | [diff] [blame] | 724 | st->Ist.LLSC.storedata); |
sewardj | db5907d | 2009-11-26 17:20:21 +0000 | [diff] [blame] | 725 | } |
bart | bedfd23 | 2009-03-26 19:07:15 +0000 | [diff] [blame] | 726 | addStmtToIRSB(bb, st); |
| 727 | break; |
bart | 09dc13f | 2009-02-14 15:13:31 +0000 | [diff] [blame] | 728 | } |
sewardj | db5907d | 2009-11-26 17:20:21 +0000 | [diff] [blame] | 729 | |
| 730 | case Ist_NoOp: |
| 731 | case Ist_AbiHint: |
| 732 | case Ist_Put: |
| 733 | case Ist_PutI: |
| 734 | case Ist_Exit: |
| 735 | /* None of these can contain any memory references. */ |
| 736 | addStmtToIRSB(bb, st); |
| 737 | break; |
| 738 | |
| 739 | default: |
| 740 | ppIRStmt(st); |
| 741 | tl_assert(0); |
| 742 | } |
bart | bedfd23 | 2009-03-26 19:07:15 +0000 | [diff] [blame] | 743 | } |
bart | 09dc13f | 2009-02-14 15:13:31 +0000 | [diff] [blame] | 744 | |
bart | bedfd23 | 2009-03-26 19:07:15 +0000 | [diff] [blame] | 745 | return bb; |
bart | 09dc13f | 2009-02-14 15:13:31 +0000 | [diff] [blame] | 746 | } |
| 747 | |