cerion | 896a137 | 2005-01-25 12:24:25 +0000 | [diff] [blame] | 1 | |
| 2 | /*--------------------------------------------------------------------*/ |
| 3 | /*--- ---*/ |
cerion | d0eae2d | 2005-12-23 11:43:01 +0000 | [diff] [blame] | 4 | /*--- This file (guest-ppc/toIR.c) is ---*/ |
sewardj | dbcfae7 | 2005-08-02 11:14:04 +0000 | [diff] [blame] | 5 | /*--- Copyright (C) OpenWorks LLP. All rights reserved. ---*/ |
cerion | 896a137 | 2005-01-25 12:24:25 +0000 | [diff] [blame] | 6 | /*--- ---*/ |
| 7 | /*--------------------------------------------------------------------*/ |
| 8 | |
| 9 | /* |
| 10 | This file is part of LibVEX, a library for dynamic binary |
| 11 | instrumentation and translation. |
| 12 | |
sewardj | a33e9a4 | 2006-06-05 23:13:19 +0000 | [diff] [blame] | 13 | Copyright (C) 2004-2006 OpenWorks LLP. All rights reserved. |
cerion | 896a137 | 2005-01-25 12:24:25 +0000 | [diff] [blame] | 14 | |
sewardj | 7bd6ffe | 2005-08-03 16:07:36 +0000 | [diff] [blame] | 15 | This library is made available under a dual licensing scheme. |
cerion | 896a137 | 2005-01-25 12:24:25 +0000 | [diff] [blame] | 16 | |
sewardj | 7bd6ffe | 2005-08-03 16:07:36 +0000 | [diff] [blame] | 17 | If you link LibVEX against other code all of which is itself |
| 18 | licensed under the GNU General Public License, version 2 dated June |
| 19 | 1991 ("GPL v2"), then you may use LibVEX under the terms of the GPL |
| 20 | v2, as appearing in the file LICENSE.GPL. If the file LICENSE.GPL |
| 21 | is missing, you can obtain a copy of the GPL v2 from the Free |
| 22 | Software Foundation Inc., 51 Franklin St, Fifth Floor, Boston, MA |
| 23 | 02110-1301, USA. |
| 24 | |
| 25 | For any other uses of LibVEX, you must first obtain a commercial |
| 26 | license from OpenWorks LLP. Please contact info@open-works.co.uk |
| 27 | for information about commercial licensing. |
| 28 | |
| 29 | This software is provided by OpenWorks LLP "as is" and any express |
| 30 | or implied warranties, including, but not limited to, the implied |
| 31 | warranties of merchantability and fitness for a particular purpose |
| 32 | are disclaimed. In no event shall OpenWorks LLP be liable for any |
| 33 | direct, indirect, incidental, special, exemplary, or consequential |
| 34 | damages (including, but not limited to, procurement of substitute |
| 35 | goods or services; loss of use, data, or profits; or business |
| 36 | interruption) however caused and on any theory of liability, |
| 37 | whether in contract, strict liability, or tort (including |
| 38 | negligence or otherwise) arising in any way out of the use of this |
| 39 | software, even if advised of the possibility of such damage. |
cerion | 896a137 | 2005-01-25 12:24:25 +0000 | [diff] [blame] | 40 | |
| 41 | Neither the names of the U.S. Department of Energy nor the |
| 42 | University of California nor the names of its contributors may be |
| 43 | used to endorse or promote products derived from this software |
| 44 | without prior written permission. |
cerion | 896a137 | 2005-01-25 12:24:25 +0000 | [diff] [blame] | 45 | */ |
| 46 | |
cerion | edf7fc5 | 2005-11-18 20:57:41 +0000 | [diff] [blame] | 47 | /* TODO 18/Nov/05: |
sewardj | b51f0f4 | 2005-07-18 11:38:02 +0000 | [diff] [blame] | 48 | |
sewardj | cf8986c | 2006-01-18 04:14:52 +0000 | [diff] [blame] | 49 | Spot rld... cases which are simply left/right shifts and emit |
| 50 | Shl64/Shr64 accordingly. |
sewardj | e14bb9f | 2005-07-22 09:39:02 +0000 | [diff] [blame] | 51 | |
cerion | edf7fc5 | 2005-11-18 20:57:41 +0000 | [diff] [blame] | 52 | Altivec |
| 53 | - datastream insns |
| 54 | - lvxl,stvxl: load/store with 'least recently used' hint |
| 55 | - vexptefp, vlogefp |
sewardj | 87e651f | 2005-09-09 08:31:18 +0000 | [diff] [blame] | 56 | |
| 57 | LIMITATIONS: |
| 58 | |
| 59 | Various, including: |
| 60 | |
| 61 | - Some invalid forms of lswi and lswx are accepted when they should |
| 62 | not be. |
| 63 | |
cerion | edf7fc5 | 2005-11-18 20:57:41 +0000 | [diff] [blame] | 64 | - Floating Point: |
| 65 | - All exceptions disabled in FPSCR |
| 66 | - condition codes not set in FPSCR |
cerion | 76de5cf | 2005-11-18 18:25:12 +0000 | [diff] [blame] | 67 | |
cerion | edf7fc5 | 2005-11-18 20:57:41 +0000 | [diff] [blame] | 68 | - Altivec floating point: |
| 69 | - vmaddfp, vnmsubfp |
| 70 | Because we're using Java/IEEE mode (FPSCR[NJ]), rather than the |
| 71 | system default of Non-Java mode, we get some small errors |
| 72 | (lowest bit only). |
| 73 | This is because Non-Java mode brutally hacks denormalised results |
| 74 | to zero, whereas we keep maximum accuracy. However, using |
| 75 | Non-Java mode would give us more inaccuracy, as our intermediate |
| 76 | results would then be zeroed, too. |
sewardj | cf8986c | 2006-01-18 04:14:52 +0000 | [diff] [blame] | 77 | |
| 78 | - 64-bit mode: AbiHints for the stack red zone are only emitted for |
| 79 | unconditional calls and returns (bl, blr). They should also be |
| 80 | emitted for conditional calls and returns, but we don't have a |
| 81 | way to express that right now. Ah well. |
sewardj | b51f0f4 | 2005-07-18 11:38:02 +0000 | [diff] [blame] | 82 | */ |
| 83 | |
sewardj | ce02aa7 | 2006-01-12 12:27:58 +0000 | [diff] [blame] | 84 | /* "Special" instructions. |
| 85 | |
sewardj | 09e88d1 | 2006-01-27 16:05:49 +0000 | [diff] [blame] | 86 | This instruction decoder can decode four special instructions |
sewardj | ce02aa7 | 2006-01-12 12:27:58 +0000 | [diff] [blame] | 87 | which mean nothing natively (are no-ops as far as regs/mem are |
| 88 | concerned) but have meaning for supporting Valgrind. A special |
sewardj | 1eb7e6b | 2006-01-12 21:13:14 +0000 | [diff] [blame] | 89 | instruction is flagged by a 16-byte preamble: |
| 90 | |
| 91 | 32-bit mode: 54001800 54006800 5400E800 54009800 |
| 92 | (rlwinm 0,0,3,0,0; rlwinm 0,0,13,0,0; |
| 93 | rlwinm 0,0,29,0,0; rlwinm 0,0,19,0,0) |
| 94 | |
| 95 | 64-bit mode: 78001800 78006800 7800E802 78009802 |
| 96 | (rotldi 0,0,3; rotldi 0,0,13; |
| 97 | rotldi 0,0,61; rotldi 0,0,51) |
| 98 | |
| 99 | Following that, one of the following 3 are allowed |
sewardj | ce02aa7 | 2006-01-12 12:27:58 +0000 | [diff] [blame] | 100 | (standard interpretation in parentheses): |
| 101 | |
| 102 | 7C210B78 (or 1,1,1) %R3 = client_request ( %R4 ) |
| 103 | 7C421378 (or 2,2,2) %R3 = guest_NRADDR |
| 104 | 7C631B78 (or 3,3,3) branch-and-link-to-noredir %R11 |
sewardj | 5ff11dd | 2006-01-20 14:19:25 +0000 | [diff] [blame] | 105 | 7C842378 (or 4,4,4) %R3 = guest_NRADDR_GPR2 (64-bit mode only) |
sewardj | ce02aa7 | 2006-01-12 12:27:58 +0000 | [diff] [blame] | 106 | |
| 107 | Any other bytes following the 16-byte preamble are illegal and |
| 108 | constitute a failure in instruction decoding. This all assumes |
| 109 | that the preamble will never occur except in specific code |
| 110 | fragments designed for Valgrind to catch. |
| 111 | */ |
| 112 | |
sewardj | b51f0f4 | 2005-07-18 11:38:02 +0000 | [diff] [blame] | 113 | |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 114 | /* Translates PPC32/64 code to IR. */ |
cerion | 896a137 | 2005-01-25 12:24:25 +0000 | [diff] [blame] | 115 | |
cerion | 645c930 | 2005-01-31 10:09:59 +0000 | [diff] [blame] | 116 | /* References |
cerion | a982c05 | 2005-06-28 17:23:09 +0000 | [diff] [blame] | 117 | |
| 118 | #define PPC32 |
cerion | 645c930 | 2005-01-31 10:09:59 +0000 | [diff] [blame] | 119 | "PowerPC Microprocessor Family: |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 120 | The Programming Environments Manual for 32-Bit Microprocessors" |
cerion | e9d361a | 2005-03-04 17:35:29 +0000 | [diff] [blame] | 121 | 02/21/2000 |
| 122 | http://www-3.ibm.com/chips/techlib/techlib.nsf/techdocs/852569B20050FF778525699600719DF2 |
| 123 | |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 124 | #define PPC64 |
| 125 | "PowerPC Microprocessor Family: |
| 126 | Programming Environments Manual for 64-Bit Microprocessors" |
| 127 | 06/10/2003 |
| 128 | http://www-3.ibm.com/chips/techlib/techlib.nsf/techdocs/F7E732FF811F783187256FDD004D3797 |
| 129 | |
cerion | a982c05 | 2005-06-28 17:23:09 +0000 | [diff] [blame] | 130 | #define AV |
| 131 | "PowerPC Microprocessor Family: |
| 132 | AltiVec(TM) Technology Programming Environments Manual" |
| 133 | 07/10/2003 |
| 134 | http://www-3.ibm.com/chips/techlib/techlib.nsf/techdocs/FBFA164F824370F987256D6A006F424D |
cerion | 645c930 | 2005-01-31 10:09:59 +0000 | [diff] [blame] | 135 | */ |
| 136 | |
cerion | 896a137 | 2005-01-25 12:24:25 +0000 | [diff] [blame] | 137 | #include "libvex_basictypes.h" |
| 138 | #include "libvex_ir.h" |
| 139 | #include "libvex.h" |
cerion | 1515db9 | 2005-01-25 17:21:23 +0000 | [diff] [blame] | 140 | #include "libvex_guest_ppc32.h" |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 141 | #include "libvex_guest_ppc64.h" |
cerion | 896a137 | 2005-01-25 12:24:25 +0000 | [diff] [blame] | 142 | |
| 143 | #include "main/vex_util.h" |
| 144 | #include "main/vex_globals.h" |
sewardj | 9e6491a | 2005-07-02 19:24:10 +0000 | [diff] [blame] | 145 | #include "guest-generic/bb_to_IR.h" |
cerion | d0eae2d | 2005-12-23 11:43:01 +0000 | [diff] [blame] | 146 | #include "guest-ppc/gdefs.h" |
cerion | 896a137 | 2005-01-25 12:24:25 +0000 | [diff] [blame] | 147 | |
| 148 | |
| 149 | /*------------------------------------------------------------*/ |
| 150 | /*--- Globals ---*/ |
| 151 | /*------------------------------------------------------------*/ |
| 152 | |
sewardj | 9e6491a | 2005-07-02 19:24:10 +0000 | [diff] [blame] | 153 | /* These are set at the start of the translation of an insn, right |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 154 | down in disInstr_PPC, so that we don't have to pass them around |
sewardj | 9e6491a | 2005-07-02 19:24:10 +0000 | [diff] [blame] | 155 | endlessly. They are all constant during the translation of any |
| 156 | given insn. */ |
cerion | 896a137 | 2005-01-25 12:24:25 +0000 | [diff] [blame] | 157 | |
cerion | ed623db | 2005-06-20 12:42:04 +0000 | [diff] [blame] | 158 | /* We need to know this to do sub-register accesses correctly. */ |
cerion | ed623db | 2005-06-20 12:42:04 +0000 | [diff] [blame] | 159 | static Bool host_is_bigendian; |
| 160 | |
cerion | 896a137 | 2005-01-25 12:24:25 +0000 | [diff] [blame] | 161 | /* Pointer to the guest code area. */ |
cerion | 896a137 | 2005-01-25 12:24:25 +0000 | [diff] [blame] | 162 | static UChar* guest_code; |
| 163 | |
| 164 | /* The guest address corresponding to guest_code[0]. */ |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 165 | static Addr64 guest_CIA_bbstart; |
cerion | 896a137 | 2005-01-25 12:24:25 +0000 | [diff] [blame] | 166 | |
sewardj | 01a9e80 | 2005-02-01 20:46:00 +0000 | [diff] [blame] | 167 | /* The guest address for the instruction currently being |
| 168 | translated. */ |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 169 | static Addr64 guest_CIA_curr_instr; |
sewardj | 01a9e80 | 2005-02-01 20:46:00 +0000 | [diff] [blame] | 170 | |
cerion | 896a137 | 2005-01-25 12:24:25 +0000 | [diff] [blame] | 171 | /* The IRBB* into which we're generating code. */ |
| 172 | static IRBB* irbb; |
| 173 | |
sewardj | 5df65bb | 2005-11-29 14:47:04 +0000 | [diff] [blame] | 174 | /* Is our guest binary 32 or 64bit? Set at each call to |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 175 | disInstr_PPC below. */ |
sewardj | 5df65bb | 2005-11-29 14:47:04 +0000 | [diff] [blame] | 176 | static Bool mode64 = False; |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 177 | |
cerion | 4c4f5ef | 2006-01-02 14:41:50 +0000 | [diff] [blame] | 178 | // Given a pointer to a function as obtained by "& functionname" in C, |
| 179 | // produce a pointer to the actual entry point for the function. For |
| 180 | // most platforms it's the identity function. Unfortunately, on |
| 181 | // ppc64-linux it isn't (sigh). |
| 182 | static void* fnptr_to_fnentry( void* f ) |
| 183 | { |
| 184 | #if defined(__powerpc64__) |
| 185 | /* f is a pointer to a 3-word function descriptor, of which |
| 186 | the first word is the entry address. */ |
| 187 | ULong* fdescr = (ULong*)f; |
| 188 | return (void*)(fdescr[0]); |
| 189 | #else |
| 190 | return f; |
| 191 | #endif |
| 192 | } |
| 193 | |
cerion | 896a137 | 2005-01-25 12:24:25 +0000 | [diff] [blame] | 194 | |
| 195 | /*------------------------------------------------------------*/ |
| 196 | /*--- Debugging output ---*/ |
| 197 | /*------------------------------------------------------------*/ |
| 198 | |
| 199 | #define DIP(format, args...) \ |
| 200 | if (vex_traceflags & VEX_TRACE_FE) \ |
| 201 | vex_printf(format, ## args) |
| 202 | |
| 203 | #define DIS(buf, format, args...) \ |
| 204 | if (vex_traceflags & VEX_TRACE_FE) \ |
| 205 | vex_sprintf(buf, format, ## args) |
| 206 | |
| 207 | |
cerion | 896a137 | 2005-01-25 12:24:25 +0000 | [diff] [blame] | 208 | /*------------------------------------------------------------*/ |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 209 | /*--- Offsets of various parts of the ppc32/64 guest state ---*/ |
cerion | 896a137 | 2005-01-25 12:24:25 +0000 | [diff] [blame] | 210 | /*------------------------------------------------------------*/ |
| 211 | |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 212 | #define offsetofPPCGuestState(_x) \ |
| 213 | (mode64 ? offsetof(VexGuestPPC64State, _x) : \ |
| 214 | offsetof(VexGuestPPC32State, _x)) |
cerion | 91ad536 | 2005-01-27 23:02:41 +0000 | [diff] [blame] | 215 | |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 216 | #define OFFB_CIA offsetofPPCGuestState(guest_CIA) |
| 217 | #define OFFB_LR offsetofPPCGuestState(guest_LR) |
| 218 | #define OFFB_CTR offsetofPPCGuestState(guest_CTR) |
| 219 | #define OFFB_XER_SO offsetofPPCGuestState(guest_XER_SO) |
| 220 | #define OFFB_XER_OV offsetofPPCGuestState(guest_XER_OV) |
| 221 | #define OFFB_XER_CA offsetofPPCGuestState(guest_XER_CA) |
| 222 | #define OFFB_XER_BC offsetofPPCGuestState(guest_XER_BC) |
| 223 | #define OFFB_FPROUND offsetofPPCGuestState(guest_FPROUND) |
| 224 | #define OFFB_VRSAVE offsetofPPCGuestState(guest_VRSAVE) |
| 225 | #define OFFB_VSCR offsetofPPCGuestState(guest_VSCR) |
| 226 | #define OFFB_EMWARN offsetofPPCGuestState(guest_EMWARN) |
| 227 | #define OFFB_TISTART offsetofPPCGuestState(guest_TISTART) |
| 228 | #define OFFB_TILEN offsetofPPCGuestState(guest_TILEN) |
| 229 | #define OFFB_RESVN offsetofPPCGuestState(guest_RESVN) |
sewardj | ce02aa7 | 2006-01-12 12:27:58 +0000 | [diff] [blame] | 230 | #define OFFB_NRADDR offsetofPPCGuestState(guest_NRADDR) |
sewardj | 7787af4 | 2005-08-04 18:32:19 +0000 | [diff] [blame] | 231 | |
sewardj | 5ff11dd | 2006-01-20 14:19:25 +0000 | [diff] [blame] | 232 | /* This only exists in the 64-bit guest state */ |
| 233 | #define OFFB64_NRADDR_GPR2 \ |
| 234 | offsetof(VexGuestPPC64State,guest_NRADDR_GPR2) |
| 235 | |
cerion | 91ad536 | 2005-01-27 23:02:41 +0000 | [diff] [blame] | 236 | |
cerion | 3867460 | 2005-02-08 02:19:25 +0000 | [diff] [blame] | 237 | /*------------------------------------------------------------*/ |
sewardj | b51f0f4 | 2005-07-18 11:38:02 +0000 | [diff] [blame] | 238 | /*--- Extract instruction fields --- */ |
cerion | 3867460 | 2005-02-08 02:19:25 +0000 | [diff] [blame] | 239 | /*------------------------------------------------------------*/ |
cerion | e9d361a | 2005-03-04 17:35:29 +0000 | [diff] [blame] | 240 | |
cerion | 76de5cf | 2005-11-18 18:25:12 +0000 | [diff] [blame] | 241 | /* Extract field from insn, given idx (zero = lsb) and field length */ |
| 242 | #define IFIELD( insn, idx, len ) ((insn >> idx) & ((1<<len)-1)) |
| 243 | |
sewardj | b51f0f4 | 2005-07-18 11:38:02 +0000 | [diff] [blame] | 244 | /* Extract primary opcode, instr[31:26] */ |
cerion | 76de5cf | 2005-11-18 18:25:12 +0000 | [diff] [blame] | 245 | static UChar ifieldOPC( UInt instr ) { |
| 246 | return toUChar( IFIELD( instr, 26, 6 ) ); |
sewardj | b51f0f4 | 2005-07-18 11:38:02 +0000 | [diff] [blame] | 247 | } |
cerion | e9d361a | 2005-03-04 17:35:29 +0000 | [diff] [blame] | 248 | |
cerion | 76de5cf | 2005-11-18 18:25:12 +0000 | [diff] [blame] | 249 | /* Extract 10-bit secondary opcode, instr[10:1] */ |
sewardj | b51f0f4 | 2005-07-18 11:38:02 +0000 | [diff] [blame] | 250 | static UInt ifieldOPClo10 ( UInt instr) { |
cerion | 76de5cf | 2005-11-18 18:25:12 +0000 | [diff] [blame] | 251 | return IFIELD( instr, 1, 10 ); |
| 252 | } |
| 253 | |
| 254 | /* Extract 9-bit secondary opcode, instr[9:1] */ |
| 255 | static UInt ifieldOPClo9 ( UInt instr) { |
| 256 | return IFIELD( instr, 1, 9 ); |
| 257 | } |
| 258 | |
| 259 | /* Extract 5-bit secondary opcode, instr[5:1] */ |
| 260 | static UInt ifieldOPClo5 ( UInt instr) { |
| 261 | return IFIELD( instr, 1, 5 ); |
sewardj | b51f0f4 | 2005-07-18 11:38:02 +0000 | [diff] [blame] | 262 | } |
cerion | e9d361a | 2005-03-04 17:35:29 +0000 | [diff] [blame] | 263 | |
sewardj | b51f0f4 | 2005-07-18 11:38:02 +0000 | [diff] [blame] | 264 | /* Extract RD (destination register) field, instr[25:21] */ |
cerion | 76de5cf | 2005-11-18 18:25:12 +0000 | [diff] [blame] | 265 | static UChar ifieldRegDS( UInt instr ) { |
| 266 | return toUChar( IFIELD( instr, 21, 5 ) ); |
sewardj | b51f0f4 | 2005-07-18 11:38:02 +0000 | [diff] [blame] | 267 | } |
cerion | 094d139 | 2005-06-20 13:45:57 +0000 | [diff] [blame] | 268 | |
cerion | 76de5cf | 2005-11-18 18:25:12 +0000 | [diff] [blame] | 269 | /* Extract RA (1st source register) field, instr[20:16] */ |
| 270 | static UChar ifieldRegA ( UInt instr ) { |
| 271 | return toUChar( IFIELD( instr, 16, 5 ) ); |
sewardj | b51f0f4 | 2005-07-18 11:38:02 +0000 | [diff] [blame] | 272 | } |
| 273 | |
cerion | 76de5cf | 2005-11-18 18:25:12 +0000 | [diff] [blame] | 274 | /* Extract RB (2nd source register) field, instr[15:11] */ |
| 275 | static UChar ifieldRegB ( UInt instr ) { |
| 276 | return toUChar( IFIELD( instr, 11, 5 ) ); |
sewardj | b51f0f4 | 2005-07-18 11:38:02 +0000 | [diff] [blame] | 277 | } |
| 278 | |
cerion | 76de5cf | 2005-11-18 18:25:12 +0000 | [diff] [blame] | 279 | /* Extract RC (3rd source register) field, instr[10:6] */ |
| 280 | static UChar ifieldRegC ( UInt instr ) { |
| 281 | return toUChar( IFIELD( instr, 6, 5 ) ); |
sewardj | b51f0f4 | 2005-07-18 11:38:02 +0000 | [diff] [blame] | 282 | } |
| 283 | |
cerion | 76de5cf | 2005-11-18 18:25:12 +0000 | [diff] [blame] | 284 | /* Extract 2nd lowest bit, instr[1] */ |
| 285 | static UChar ifieldBIT10 ( UInt instr ) { |
| 286 | return toUChar( IFIELD( instr, 10, 1 ) ); |
| 287 | } |
| 288 | |
| 289 | /* Extract 2nd lowest bit, instr[1] */ |
| 290 | static UChar ifieldBIT1 ( UInt instr ) { |
| 291 | return toUChar( IFIELD( instr, 1, 1 ) ); |
| 292 | } |
| 293 | |
| 294 | /* Extract lowest bit, instr[0] */ |
| 295 | static UChar ifieldBIT0 ( UInt instr ) { |
| 296 | return toUChar( instr & 0x1 ); |
| 297 | } |
| 298 | |
| 299 | /* Extract unsigned bottom half, instr[15:0] */ |
| 300 | static UInt ifieldUIMM16 ( UInt instr ) { |
| 301 | return instr & 0xFFFF; |
| 302 | } |
| 303 | |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 304 | /* Extract unsigned bottom 26 bits, instr[25:0] */ |
| 305 | static UInt ifieldUIMM26 ( UInt instr ) { |
| 306 | return instr & 0x3FFFFFF; |
cerion | 76de5cf | 2005-11-18 18:25:12 +0000 | [diff] [blame] | 307 | } |
| 308 | |
sewardj | b51f0f4 | 2005-07-18 11:38:02 +0000 | [diff] [blame] | 309 | |
cerion | edf7fc5 | 2005-11-18 20:57:41 +0000 | [diff] [blame] | 310 | /*------------------------------------------------------------*/ |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 311 | /*--- Guest-state identifiers ---*/ |
cerion | edf7fc5 | 2005-11-18 20:57:41 +0000 | [diff] [blame] | 312 | /*------------------------------------------------------------*/ |
sewardj | e14bb9f | 2005-07-22 09:39:02 +0000 | [diff] [blame] | 313 | |
cerion | e9d361a | 2005-03-04 17:35:29 +0000 | [diff] [blame] | 314 | typedef enum { |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 315 | PPC_GST_CIA, // Current Instruction Address |
| 316 | PPC_GST_LR, // Link Register |
| 317 | PPC_GST_CTR, // Count Register |
| 318 | PPC_GST_XER, // Overflow, carry flags, byte count |
| 319 | PPC_GST_CR, // Condition Register |
| 320 | PPC_GST_FPSCR, // Floating Point Status/Control Register |
| 321 | PPC_GST_VRSAVE, // Vector Save/Restore Register |
| 322 | PPC_GST_VSCR, // Vector Status and Control Register |
| 323 | PPC_GST_EMWARN, // Emulation warnings |
| 324 | PPC_GST_TISTART,// For icbi: start of area to invalidate |
| 325 | PPC_GST_TILEN, // For icbi: length of area to invalidate |
| 326 | PPC_GST_RESVN, // For lwarx/stwcx. |
| 327 | PPC_GST_MAX |
| 328 | } PPC_GST; |
cerion | e9d361a | 2005-03-04 17:35:29 +0000 | [diff] [blame] | 329 | |
cerion | edf7fc5 | 2005-11-18 20:57:41 +0000 | [diff] [blame] | 330 | #define MASK_FPSCR_RN 0x3 |
| 331 | #define MASK_VSCR_VALID 0x00010001 |
sewardj | e14bb9f | 2005-07-22 09:39:02 +0000 | [diff] [blame] | 332 | |
cerion | edf7fc5 | 2005-11-18 20:57:41 +0000 | [diff] [blame] | 333 | |
| 334 | /*------------------------------------------------------------*/ |
| 335 | /*--- FP Helpers ---*/ |
| 336 | /*------------------------------------------------------------*/ |
| 337 | |
sewardj | 2ead522 | 2005-11-23 03:53:45 +0000 | [diff] [blame] | 338 | /* Produce the 32-bit pattern corresponding to the supplied |
| 339 | float. */ |
| 340 | static UInt float_to_bits ( Float f ) |
| 341 | { |
| 342 | union { UInt i; Float f; } u; |
| 343 | vassert(4 == sizeof(UInt)); |
| 344 | vassert(4 == sizeof(Float)); |
| 345 | vassert(4 == sizeof(u)); |
| 346 | u.f = f; |
| 347 | return u.i; |
| 348 | } |
| 349 | |
cerion | 3867460 | 2005-02-08 02:19:25 +0000 | [diff] [blame] | 350 | |
cerion | 3867460 | 2005-02-08 02:19:25 +0000 | [diff] [blame] | 351 | /*------------------------------------------------------------*/ |
| 352 | /*--- Misc Helpers ---*/ |
| 353 | /*------------------------------------------------------------*/ |
| 354 | |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 355 | /* Generate mask with 1's from 'begin' through 'end', |
| 356 | wrapping if begin > end. |
| 357 | begin->end works from right to left, 0=lsb |
| 358 | */ |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 359 | static UInt MASK32( UInt begin, UInt end ) |
cerion | 3867460 | 2005-02-08 02:19:25 +0000 | [diff] [blame] | 360 | { |
sewardj | 6332740 | 2006-01-25 03:26:27 +0000 | [diff] [blame] | 361 | UInt m1, m2, mask; |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 362 | vassert(begin < 32); |
| 363 | vassert(end < 32); |
sewardj | 6332740 | 2006-01-25 03:26:27 +0000 | [diff] [blame] | 364 | m1 = ((UInt)(-1)) << begin; |
| 365 | m2 = ((UInt)(-1)) << end << 1; |
| 366 | mask = m1 ^ m2; |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 367 | if (begin > end) mask = ~mask; // wrap mask |
| 368 | return mask; |
cerion | 3867460 | 2005-02-08 02:19:25 +0000 | [diff] [blame] | 369 | } |
| 370 | |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 371 | /* ditto for 64bit mask */ |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 372 | static ULong MASK64( UInt begin, UInt end ) |
| 373 | { |
sewardj | 6332740 | 2006-01-25 03:26:27 +0000 | [diff] [blame] | 374 | ULong m1, m2, mask; |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 375 | vassert(begin < 64); |
| 376 | vassert(end < 64); |
sewardj | 6332740 | 2006-01-25 03:26:27 +0000 | [diff] [blame] | 377 | m1 = ((ULong)(-1)) << begin; |
| 378 | m2 = ((ULong)(-1)) << end << 1; |
| 379 | mask = m1 ^ m2; |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 380 | if (begin > end) mask = ~mask; // wrap mask |
| 381 | return mask; |
| 382 | } |
| 383 | |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 384 | static Addr64 nextInsnAddr( void ) |
| 385 | { |
| 386 | return guest_CIA_curr_instr + 4; |
| 387 | } |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 388 | |
cerion | 896a137 | 2005-01-25 12:24:25 +0000 | [diff] [blame] | 389 | |
cerion | 896a137 | 2005-01-25 12:24:25 +0000 | [diff] [blame] | 390 | /*------------------------------------------------------------*/ |
| 391 | /*--- Helper bits and pieces for deconstructing the ---*/ |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 392 | /*--- ppc32/64 insn stream. ---*/ |
cerion | 896a137 | 2005-01-25 12:24:25 +0000 | [diff] [blame] | 393 | /*------------------------------------------------------------*/ |
| 394 | |
| 395 | /* Add a statement to the list held by "irbb". */ |
| 396 | static void stmt ( IRStmt* st ) |
| 397 | { |
| 398 | addStmtToIRBB( irbb, st ); |
| 399 | } |
| 400 | |
cerion | 896a137 | 2005-01-25 12:24:25 +0000 | [diff] [blame] | 401 | /* Generate a new temporary of the given type. */ |
| 402 | static IRTemp newTemp ( IRType ty ) |
| 403 | { |
sewardj | 496a58d | 2005-03-20 18:44:44 +0000 | [diff] [blame] | 404 | vassert(isPlausibleIRType(ty)); |
cerion | 896a137 | 2005-01-25 12:24:25 +0000 | [diff] [blame] | 405 | return newIRTemp( irbb->tyenv, ty ); |
| 406 | } |
cerion | 896a137 | 2005-01-25 12:24:25 +0000 | [diff] [blame] | 407 | |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 408 | /* Various simple conversions */ |
| 409 | |
| 410 | static UChar extend_s_5to8 ( UChar x ) |
| 411 | { |
| 412 | return toUChar((((Int)x) << 27) >> 27); |
| 413 | } |
| 414 | |
cerion | 92d9d87 | 2005-09-15 21:58:50 +0000 | [diff] [blame] | 415 | static UInt extend_s_8to32( UChar x ) |
| 416 | { |
| 417 | return (UInt)((((Int)x) << 24) >> 24); |
| 418 | } |
cerion | 91ad536 | 2005-01-27 23:02:41 +0000 | [diff] [blame] | 419 | |
cerion | 896a137 | 2005-01-25 12:24:25 +0000 | [diff] [blame] | 420 | static UInt extend_s_16to32 ( UInt x ) |
| 421 | { |
| 422 | return (UInt)((((Int)x) << 16) >> 16); |
| 423 | } |
cerion | 896a137 | 2005-01-25 12:24:25 +0000 | [diff] [blame] | 424 | |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 425 | static ULong extend_s_16to64 ( UInt x ) |
| 426 | { |
| 427 | return (ULong)((((Long)x) << 48) >> 48); |
| 428 | } |
| 429 | |
| 430 | static ULong extend_s_26to64 ( UInt x ) |
| 431 | { |
| 432 | return (ULong)((((Long)x) << 38) >> 38); |
| 433 | } |
| 434 | |
| 435 | static ULong extend_s_32to64 ( UInt x ) |
| 436 | { |
| 437 | return (ULong)((((Long)x) << 32) >> 32); |
| 438 | } |
| 439 | |
sewardj | 684aa95 | 2005-01-30 12:52:14 +0000 | [diff] [blame] | 440 | /* Do a big-endian load of a 32-bit word, regardless of the endianness |
| 441 | of the underlying host. */ |
cerion | cf00446 | 2005-01-31 15:24:55 +0000 | [diff] [blame] | 442 | static UInt getUIntBigendianly ( UChar* p ) |
sewardj | 684aa95 | 2005-01-30 12:52:14 +0000 | [diff] [blame] | 443 | { |
cerion | cf00446 | 2005-01-31 15:24:55 +0000 | [diff] [blame] | 444 | UInt w = 0; |
sewardj | 684aa95 | 2005-01-30 12:52:14 +0000 | [diff] [blame] | 445 | w = (w << 8) | p[0]; |
| 446 | w = (w << 8) | p[1]; |
| 447 | w = (w << 8) | p[2]; |
| 448 | w = (w << 8) | p[3]; |
| 449 | return w; |
| 450 | } |
| 451 | |
cerion | 896a137 | 2005-01-25 12:24:25 +0000 | [diff] [blame] | 452 | |
| 453 | /*------------------------------------------------------------*/ |
| 454 | /*--- Helpers for constructing IR. ---*/ |
| 455 | /*------------------------------------------------------------*/ |
| 456 | |
cerion | 896a137 | 2005-01-25 12:24:25 +0000 | [diff] [blame] | 457 | static void assign ( IRTemp dst, IRExpr* e ) |
| 458 | { |
| 459 | stmt( IRStmt_Tmp(dst, e) ); |
| 460 | } |
| 461 | |
cerion | ae69462 | 2005-01-28 17:52:47 +0000 | [diff] [blame] | 462 | static void storeBE ( IRExpr* addr, IRExpr* data ) |
cerion | 896a137 | 2005-01-25 12:24:25 +0000 | [diff] [blame] | 463 | { |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 464 | vassert(typeOfIRExpr(irbb->tyenv, addr) == Ity_I32 || |
| 465 | typeOfIRExpr(irbb->tyenv, addr) == Ity_I64); |
sewardj | af1ceca | 2005-06-30 23:31:27 +0000 | [diff] [blame] | 466 | stmt( IRStmt_Store(Iend_BE,addr,data) ); |
cerion | 896a137 | 2005-01-25 12:24:25 +0000 | [diff] [blame] | 467 | } |
| 468 | |
| 469 | static IRExpr* unop ( IROp op, IRExpr* a ) |
| 470 | { |
| 471 | return IRExpr_Unop(op, a); |
| 472 | } |
| 473 | |
| 474 | static IRExpr* binop ( IROp op, IRExpr* a1, IRExpr* a2 ) |
| 475 | { |
| 476 | return IRExpr_Binop(op, a1, a2); |
| 477 | } |
| 478 | |
sewardj | b183b85 | 2006-02-03 16:08:03 +0000 | [diff] [blame] | 479 | static IRExpr* triop ( IROp op, IRExpr* a1, IRExpr* a2, IRExpr* a3 ) |
| 480 | { |
| 481 | return IRExpr_Triop(op, a1, a2, a3); |
| 482 | } |
| 483 | |
sewardj | 40c8026 | 2006-02-08 19:30:46 +0000 | [diff] [blame] | 484 | static IRExpr* qop ( IROp op, IRExpr* a1, IRExpr* a2, |
| 485 | IRExpr* a3, IRExpr* a4 ) |
| 486 | { |
| 487 | return IRExpr_Qop(op, a1, a2, a3, a4); |
| 488 | } |
| 489 | |
cerion | 896a137 | 2005-01-25 12:24:25 +0000 | [diff] [blame] | 490 | static IRExpr* mkexpr ( IRTemp tmp ) |
| 491 | { |
| 492 | return IRExpr_Tmp(tmp); |
| 493 | } |
| 494 | |
sewardj | 684c037 | 2005-02-07 02:33:58 +0000 | [diff] [blame] | 495 | static IRExpr* mkU8 ( UChar i ) |
cerion | 896a137 | 2005-01-25 12:24:25 +0000 | [diff] [blame] | 496 | { |
cerion | 896a137 | 2005-01-25 12:24:25 +0000 | [diff] [blame] | 497 | return IRExpr_Const(IRConst_U8(i)); |
| 498 | } |
cerion | 896a137 | 2005-01-25 12:24:25 +0000 | [diff] [blame] | 499 | |
cerion | 92d9d87 | 2005-09-15 21:58:50 +0000 | [diff] [blame] | 500 | static IRExpr* mkU16 ( UInt i ) |
| 501 | { |
| 502 | return IRExpr_Const(IRConst_U16(i)); |
| 503 | } |
| 504 | |
cerion | 896a137 | 2005-01-25 12:24:25 +0000 | [diff] [blame] | 505 | static IRExpr* mkU32 ( UInt i ) |
| 506 | { |
| 507 | return IRExpr_Const(IRConst_U32(i)); |
| 508 | } |
| 509 | |
cerion | 4a49b03 | 2005-11-08 16:23:07 +0000 | [diff] [blame] | 510 | static IRExpr* mkU64 ( ULong i ) |
| 511 | { |
| 512 | return IRExpr_Const(IRConst_U64(i)); |
| 513 | } |
| 514 | |
cerion | ae69462 | 2005-01-28 17:52:47 +0000 | [diff] [blame] | 515 | static IRExpr* loadBE ( IRType ty, IRExpr* data ) |
cerion | 896a137 | 2005-01-25 12:24:25 +0000 | [diff] [blame] | 516 | { |
sewardj | af1ceca | 2005-06-30 23:31:27 +0000 | [diff] [blame] | 517 | return IRExpr_Load(Iend_BE,ty,data); |
cerion | 896a137 | 2005-01-25 12:24:25 +0000 | [diff] [blame] | 518 | } |
cerion | 896a137 | 2005-01-25 12:24:25 +0000 | [diff] [blame] | 519 | |
sewardj | 20ef547 | 2005-07-21 14:48:31 +0000 | [diff] [blame] | 520 | static IRExpr* mkOR1 ( IRExpr* arg1, IRExpr* arg2 ) |
| 521 | { |
| 522 | vassert(typeOfIRExpr(irbb->tyenv, arg1) == Ity_I1); |
| 523 | vassert(typeOfIRExpr(irbb->tyenv, arg2) == Ity_I1); |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 524 | return unop(Iop_32to1, binop(Iop_Or32, unop(Iop_1Uto32, arg1), |
| 525 | unop(Iop_1Uto32, arg2))); |
sewardj | 20ef547 | 2005-07-21 14:48:31 +0000 | [diff] [blame] | 526 | } |
| 527 | |
| 528 | static IRExpr* mkAND1 ( IRExpr* arg1, IRExpr* arg2 ) |
| 529 | { |
| 530 | vassert(typeOfIRExpr(irbb->tyenv, arg1) == Ity_I1); |
| 531 | vassert(typeOfIRExpr(irbb->tyenv, arg2) == Ity_I1); |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 532 | return unop(Iop_32to1, binop(Iop_And32, unop(Iop_1Uto32, arg1), |
| 533 | unop(Iop_1Uto32, arg2))); |
sewardj | 20ef547 | 2005-07-21 14:48:31 +0000 | [diff] [blame] | 534 | } |
sewardj | b51f0f4 | 2005-07-18 11:38:02 +0000 | [diff] [blame] | 535 | |
cerion | 4a49b03 | 2005-11-08 16:23:07 +0000 | [diff] [blame] | 536 | /* expand V128_8Ux16 to 2x V128_16Ux8's */ |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 537 | static void expand8Ux16( IRExpr* vIn, |
| 538 | /*OUTs*/ IRTemp* vEvn, IRTemp* vOdd ) |
cerion | 4a49b03 | 2005-11-08 16:23:07 +0000 | [diff] [blame] | 539 | { |
| 540 | IRTemp ones8x16 = newTemp(Ity_V128); |
| 541 | |
| 542 | vassert(typeOfIRExpr(irbb->tyenv, vIn) == Ity_V128); |
| 543 | vassert(vEvn && *vEvn == IRTemp_INVALID); |
| 544 | vassert(vOdd && *vOdd == IRTemp_INVALID); |
| 545 | *vEvn = newTemp(Ity_V128); |
| 546 | *vOdd = newTemp(Ity_V128); |
| 547 | |
| 548 | assign( ones8x16, unop(Iop_Dup8x16, mkU8(0x1)) ); |
cerion | 24d06f1 | 2005-11-09 21:34:20 +0000 | [diff] [blame] | 549 | assign( *vOdd, binop(Iop_MullEven8Ux16, mkexpr(ones8x16), vIn) ); |
| 550 | assign( *vEvn, binop(Iop_MullEven8Ux16, mkexpr(ones8x16), |
| 551 | binop(Iop_ShrV128, vIn, mkU8(8))) ); |
cerion | 4a49b03 | 2005-11-08 16:23:07 +0000 | [diff] [blame] | 552 | } |
| 553 | |
| 554 | /* expand V128_8Sx16 to 2x V128_16Sx8's */ |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 555 | static void expand8Sx16( IRExpr* vIn, |
| 556 | /*OUTs*/ IRTemp* vEvn, IRTemp* vOdd ) |
cerion | 4a49b03 | 2005-11-08 16:23:07 +0000 | [diff] [blame] | 557 | { |
| 558 | IRTemp ones8x16 = newTemp(Ity_V128); |
| 559 | |
| 560 | vassert(typeOfIRExpr(irbb->tyenv, vIn) == Ity_V128); |
| 561 | vassert(vEvn && *vEvn == IRTemp_INVALID); |
| 562 | vassert(vOdd && *vOdd == IRTemp_INVALID); |
| 563 | *vEvn = newTemp(Ity_V128); |
| 564 | *vOdd = newTemp(Ity_V128); |
| 565 | |
| 566 | assign( ones8x16, unop(Iop_Dup8x16, mkU8(0x1)) ); |
cerion | 24d06f1 | 2005-11-09 21:34:20 +0000 | [diff] [blame] | 567 | assign( *vOdd, binop(Iop_MullEven8Sx16, mkexpr(ones8x16), vIn) ); |
| 568 | assign( *vEvn, binop(Iop_MullEven8Sx16, mkexpr(ones8x16), |
| 569 | binop(Iop_ShrV128, vIn, mkU8(8))) ); |
cerion | 4a49b03 | 2005-11-08 16:23:07 +0000 | [diff] [blame] | 570 | } |
| 571 | |
| 572 | /* expand V128_16Uto8 to 2x V128_32Ux4's */ |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 573 | static void expand16Ux8( IRExpr* vIn, |
| 574 | /*OUTs*/ IRTemp* vEvn, IRTemp* vOdd ) |
cerion | 4a49b03 | 2005-11-08 16:23:07 +0000 | [diff] [blame] | 575 | { |
| 576 | IRTemp ones16x8 = newTemp(Ity_V128); |
| 577 | |
| 578 | vassert(typeOfIRExpr(irbb->tyenv, vIn) == Ity_V128); |
| 579 | vassert(vEvn && *vEvn == IRTemp_INVALID); |
| 580 | vassert(vOdd && *vOdd == IRTemp_INVALID); |
| 581 | *vEvn = newTemp(Ity_V128); |
| 582 | *vOdd = newTemp(Ity_V128); |
| 583 | |
| 584 | assign( ones16x8, unop(Iop_Dup16x8, mkU16(0x1)) ); |
cerion | 24d06f1 | 2005-11-09 21:34:20 +0000 | [diff] [blame] | 585 | assign( *vOdd, binop(Iop_MullEven16Ux8, mkexpr(ones16x8), vIn) ); |
| 586 | assign( *vEvn, binop(Iop_MullEven16Ux8, mkexpr(ones16x8), |
| 587 | binop(Iop_ShrV128, vIn, mkU8(16))) ); |
cerion | 4a49b03 | 2005-11-08 16:23:07 +0000 | [diff] [blame] | 588 | } |
| 589 | |
| 590 | /* expand V128_16Sto8 to 2x V128_32Sx4's */ |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 591 | static void expand16Sx8( IRExpr* vIn, |
| 592 | /*OUTs*/ IRTemp* vEvn, IRTemp* vOdd ) |
cerion | 4a49b03 | 2005-11-08 16:23:07 +0000 | [diff] [blame] | 593 | { |
| 594 | IRTemp ones16x8 = newTemp(Ity_V128); |
| 595 | |
| 596 | vassert(typeOfIRExpr(irbb->tyenv, vIn) == Ity_V128); |
| 597 | vassert(vEvn && *vEvn == IRTemp_INVALID); |
| 598 | vassert(vOdd && *vOdd == IRTemp_INVALID); |
| 599 | *vEvn = newTemp(Ity_V128); |
| 600 | *vOdd = newTemp(Ity_V128); |
| 601 | |
| 602 | assign( ones16x8, unop(Iop_Dup16x8, mkU16(0x1)) ); |
cerion | 24d06f1 | 2005-11-09 21:34:20 +0000 | [diff] [blame] | 603 | assign( *vOdd, binop(Iop_MullEven16Sx8, mkexpr(ones16x8), vIn) ); |
| 604 | assign( *vEvn, binop(Iop_MullEven16Sx8, mkexpr(ones16x8), |
| 605 | binop(Iop_ShrV128, vIn, mkU8(16))) ); |
cerion | 4a49b03 | 2005-11-08 16:23:07 +0000 | [diff] [blame] | 606 | } |
| 607 | |
| 608 | /* break V128 to 4xI32's, then sign-extend to I64's */ |
| 609 | static void breakV128to4x64S( IRExpr* t128, |
| 610 | /*OUTs*/ |
| 611 | IRTemp* t3, IRTemp* t2, |
| 612 | IRTemp* t1, IRTemp* t0 ) |
| 613 | { |
| 614 | IRTemp hi64 = newTemp(Ity_I64); |
| 615 | IRTemp lo64 = newTemp(Ity_I64); |
| 616 | |
| 617 | vassert(typeOfIRExpr(irbb->tyenv, t128) == Ity_V128); |
| 618 | vassert(t0 && *t0 == IRTemp_INVALID); |
| 619 | vassert(t1 && *t1 == IRTemp_INVALID); |
| 620 | vassert(t2 && *t2 == IRTemp_INVALID); |
| 621 | vassert(t3 && *t3 == IRTemp_INVALID); |
| 622 | *t0 = newTemp(Ity_I64); |
| 623 | *t1 = newTemp(Ity_I64); |
| 624 | *t2 = newTemp(Ity_I64); |
| 625 | *t3 = newTemp(Ity_I64); |
| 626 | |
| 627 | assign( hi64, unop(Iop_V128HIto64, t128) ); |
| 628 | assign( lo64, unop(Iop_V128to64, t128) ); |
| 629 | assign( *t3, unop(Iop_32Sto64, unop(Iop_64HIto32, mkexpr(hi64))) ); |
| 630 | assign( *t2, unop(Iop_32Sto64, unop(Iop_64to32, mkexpr(hi64))) ); |
| 631 | assign( *t1, unop(Iop_32Sto64, unop(Iop_64HIto32, mkexpr(lo64))) ); |
| 632 | assign( *t0, unop(Iop_32Sto64, unop(Iop_64to32, mkexpr(lo64))) ); |
| 633 | } |
| 634 | |
| 635 | /* break V128 to 4xI32's, then zero-extend to I64's */ |
| 636 | static void breakV128to4x64U ( IRExpr* t128, |
| 637 | /*OUTs*/ |
| 638 | IRTemp* t3, IRTemp* t2, |
| 639 | IRTemp* t1, IRTemp* t0 ) |
| 640 | { |
| 641 | IRTemp hi64 = newTemp(Ity_I64); |
| 642 | IRTemp lo64 = newTemp(Ity_I64); |
| 643 | |
| 644 | vassert(typeOfIRExpr(irbb->tyenv, t128) == Ity_V128); |
| 645 | vassert(t0 && *t0 == IRTemp_INVALID); |
| 646 | vassert(t1 && *t1 == IRTemp_INVALID); |
| 647 | vassert(t2 && *t2 == IRTemp_INVALID); |
| 648 | vassert(t3 && *t3 == IRTemp_INVALID); |
| 649 | *t0 = newTemp(Ity_I64); |
| 650 | *t1 = newTemp(Ity_I64); |
| 651 | *t2 = newTemp(Ity_I64); |
| 652 | *t3 = newTemp(Ity_I64); |
| 653 | |
| 654 | assign( hi64, unop(Iop_V128HIto64, t128) ); |
| 655 | assign( lo64, unop(Iop_V128to64, t128) ); |
| 656 | assign( *t3, unop(Iop_32Uto64, unop(Iop_64HIto32, mkexpr(hi64))) ); |
| 657 | assign( *t2, unop(Iop_32Uto64, unop(Iop_64to32, mkexpr(hi64))) ); |
| 658 | assign( *t1, unop(Iop_32Uto64, unop(Iop_64HIto32, mkexpr(lo64))) ); |
| 659 | assign( *t0, unop(Iop_32Uto64, unop(Iop_64to32, mkexpr(lo64))) ); |
| 660 | } |
| 661 | |
| 662 | /* Signed saturating narrow 64S to 32 */ |
| 663 | static IRExpr* mkQNarrow64Sto32 ( IRExpr* t64 ) |
| 664 | { |
| 665 | IRTemp hi32 = newTemp(Ity_I32); |
| 666 | IRTemp lo32 = newTemp(Ity_I32); |
| 667 | |
| 668 | vassert(typeOfIRExpr(irbb->tyenv, t64) == Ity_I64); |
| 669 | |
| 670 | assign( hi32, unop(Iop_64HIto32, t64)); |
| 671 | assign( lo32, unop(Iop_64to32, t64)); |
| 672 | |
| 673 | return IRExpr_Mux0X( |
| 674 | /* if (hi32 == (lo32 >>s 31)) */ |
| 675 | unop(Iop_1Uto8, |
| 676 | binop(Iop_CmpEQ32, mkexpr(hi32), |
| 677 | binop( Iop_Sar32, mkexpr(lo32), mkU8(31)))), |
| 678 | /* else: sign dep saturate: 1->0x80000000, 0->0x7FFFFFFF */ |
| 679 | binop(Iop_Add32, mkU32(0x7FFFFFFF), |
| 680 | binop(Iop_Shr32, mkexpr(hi32), mkU8(31))), |
| 681 | /* then: within signed-32 range: lo half good enough */ |
| 682 | mkexpr(lo32) ); |
| 683 | } |
| 684 | |
| 685 | /* Unsigned saturating narrow 64S to 32 */ |
| 686 | static IRExpr* mkQNarrow64Uto32 ( IRExpr* t64 ) |
| 687 | { |
| 688 | IRTemp hi32 = newTemp(Ity_I32); |
| 689 | IRTemp lo32 = newTemp(Ity_I32); |
| 690 | |
| 691 | vassert(typeOfIRExpr(irbb->tyenv, t64) == Ity_I64); |
| 692 | |
| 693 | assign( hi32, unop(Iop_64HIto32, t64)); |
| 694 | assign( lo32, unop(Iop_64to32, t64)); |
| 695 | |
| 696 | return IRExpr_Mux0X( |
| 697 | /* if (top 32 bits of t64 are 0) */ |
| 698 | unop(Iop_1Uto8, binop(Iop_CmpEQ32, mkexpr(hi32), mkU32(0))), |
| 699 | /* else: positive saturate -> 0xFFFFFFFF */ |
| 700 | mkU32(0xFFFFFFFF), |
| 701 | /* then: within unsigned-32 range: lo half good enough */ |
| 702 | mkexpr(lo32) ); |
| 703 | } |
| 704 | |
| 705 | /* Signed saturate narrow 64->32, combining to V128 */ |
| 706 | static IRExpr* mkV128from4x64S ( IRExpr* t3, IRExpr* t2, |
| 707 | IRExpr* t1, IRExpr* t0 ) |
| 708 | { |
| 709 | vassert(typeOfIRExpr(irbb->tyenv, t3) == Ity_I64); |
| 710 | vassert(typeOfIRExpr(irbb->tyenv, t2) == Ity_I64); |
| 711 | vassert(typeOfIRExpr(irbb->tyenv, t1) == Ity_I64); |
| 712 | vassert(typeOfIRExpr(irbb->tyenv, t0) == Ity_I64); |
| 713 | return binop(Iop_64HLtoV128, |
| 714 | binop(Iop_32HLto64, |
| 715 | mkQNarrow64Sto32( t3 ), |
| 716 | mkQNarrow64Sto32( t2 )), |
| 717 | binop(Iop_32HLto64, |
| 718 | mkQNarrow64Sto32( t1 ), |
| 719 | mkQNarrow64Sto32( t0 ))); |
| 720 | } |
| 721 | |
| 722 | /* Unsigned saturate narrow 64->32, combining to V128 */ |
| 723 | static IRExpr* mkV128from4x64U ( IRExpr* t3, IRExpr* t2, |
| 724 | IRExpr* t1, IRExpr* t0 ) |
| 725 | { |
| 726 | vassert(typeOfIRExpr(irbb->tyenv, t3) == Ity_I64); |
| 727 | vassert(typeOfIRExpr(irbb->tyenv, t2) == Ity_I64); |
| 728 | vassert(typeOfIRExpr(irbb->tyenv, t1) == Ity_I64); |
| 729 | vassert(typeOfIRExpr(irbb->tyenv, t0) == Ity_I64); |
| 730 | return binop(Iop_64HLtoV128, |
| 731 | binop(Iop_32HLto64, |
| 732 | mkQNarrow64Uto32( t3 ), |
| 733 | mkQNarrow64Uto32( t2 )), |
| 734 | binop(Iop_32HLto64, |
| 735 | mkQNarrow64Uto32( t1 ), |
| 736 | mkQNarrow64Uto32( t0 ))); |
| 737 | } |
| 738 | |
cerion | 24d06f1 | 2005-11-09 21:34:20 +0000 | [diff] [blame] | 739 | /* Simulate irops Iop_MullOdd*, since we don't have them */ |
| 740 | #define MK_Iop_MullOdd8Ux16( expr_vA, expr_vB ) \ |
| 741 | binop(Iop_MullEven8Ux16, \ |
| 742 | binop(Iop_ShrV128, expr_vA, mkU8(8)), \ |
| 743 | binop(Iop_ShrV128, expr_vB, mkU8(8))) |
| 744 | |
| 745 | #define MK_Iop_MullOdd8Sx16( expr_vA, expr_vB ) \ |
| 746 | binop(Iop_MullEven8Sx16, \ |
| 747 | binop(Iop_ShrV128, expr_vA, mkU8(8)), \ |
| 748 | binop(Iop_ShrV128, expr_vB, mkU8(8))) |
| 749 | |
| 750 | #define MK_Iop_MullOdd16Ux8( expr_vA, expr_vB ) \ |
| 751 | binop(Iop_MullEven16Ux8, \ |
| 752 | binop(Iop_ShrV128, expr_vA, mkU8(16)), \ |
| 753 | binop(Iop_ShrV128, expr_vB, mkU8(16))) |
| 754 | |
| 755 | #define MK_Iop_MullOdd16Sx8( expr_vA, expr_vB ) \ |
| 756 | binop(Iop_MullEven16Sx8, \ |
| 757 | binop(Iop_ShrV128, expr_vA, mkU8(16)), \ |
| 758 | binop(Iop_ShrV128, expr_vB, mkU8(16))) |
| 759 | |
cerion | 59b2c31 | 2005-12-17 11:28:53 +0000 | [diff] [blame] | 760 | static IRExpr* /* :: Ity_I64 */ mk64lo32Sto64 ( IRExpr* src ) |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 761 | { |
| 762 | vassert(typeOfIRExpr(irbb->tyenv, src) == Ity_I64); |
| 763 | return unop(Iop_32Sto64, unop(Iop_64to32, src)); |
| 764 | } |
| 765 | |
cerion | 59b2c31 | 2005-12-17 11:28:53 +0000 | [diff] [blame] | 766 | static IRExpr* /* :: Ity_I64 */ mk64lo32Uto64 ( IRExpr* src ) |
cerion | bb01b7c | 2005-12-16 13:40:18 +0000 | [diff] [blame] | 767 | { |
| 768 | vassert(typeOfIRExpr(irbb->tyenv, src) == Ity_I64); |
| 769 | return unop(Iop_32Uto64, unop(Iop_64to32, src)); |
| 770 | } |
| 771 | |
cerion | 2831b00 | 2005-11-30 19:55:22 +0000 | [diff] [blame] | 772 | static IROp mkSzOp ( IRType ty, IROp op8 ) |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 773 | { |
| 774 | Int adj; |
| 775 | vassert(ty == Ity_I8 || ty == Ity_I16 || |
| 776 | ty == Ity_I32 || ty == Ity_I64); |
| 777 | vassert(op8 == Iop_Add8 || op8 == Iop_Sub8 || op8 == Iop_Mul8 || |
| 778 | op8 == Iop_Or8 || op8 == Iop_And8 || op8 == Iop_Xor8 || |
| 779 | op8 == Iop_Shl8 || op8 == Iop_Shr8 || op8 == Iop_Sar8 || |
| 780 | op8 == Iop_CmpEQ8 || op8 == Iop_CmpNE8 || |
| 781 | op8 == Iop_Not8 || op8 == Iop_Neg8 ); |
| 782 | adj = ty==Ity_I8 ? 0 : (ty==Ity_I16 ? 1 : (ty==Ity_I32 ? 2 : 3)); |
| 783 | return adj + op8; |
| 784 | } |
| 785 | |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 786 | /* Make sure we get valid 32 and 64bit addresses */ |
cerion | 2831b00 | 2005-11-30 19:55:22 +0000 | [diff] [blame] | 787 | static Addr64 mkSzAddr ( IRType ty, Addr64 addr ) |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 788 | { |
| 789 | vassert(ty == Ity_I32 || ty == Ity_I64); |
| 790 | return ( ty == Ity_I64 ? |
| 791 | (Addr64)addr : |
| 792 | (Addr64)extend_s_32to64( toUInt(addr) ) ); |
| 793 | } |
| 794 | |
| 795 | /* sz, ULong -> IRExpr */ |
cerion | 2831b00 | 2005-11-30 19:55:22 +0000 | [diff] [blame] | 796 | static IRExpr* mkSzImm ( IRType ty, ULong imm64 ) |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 797 | { |
| 798 | vassert(ty == Ity_I32 || ty == Ity_I64); |
| 799 | return ty == Ity_I64 ? mkU64(imm64) : mkU32((UInt)imm64); |
| 800 | } |
| 801 | |
| 802 | /* sz, ULong -> IRConst */ |
cerion | 2831b00 | 2005-11-30 19:55:22 +0000 | [diff] [blame] | 803 | static IRConst* mkSzConst ( IRType ty, ULong imm64 ) |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 804 | { |
| 805 | vassert(ty == Ity_I32 || ty == Ity_I64); |
| 806 | return ( ty == Ity_I64 ? |
| 807 | IRConst_U64(imm64) : |
| 808 | IRConst_U32((UInt)imm64) ); |
| 809 | } |
| 810 | |
| 811 | /* Sign extend imm16 -> IRExpr* */ |
cerion | 2831b00 | 2005-11-30 19:55:22 +0000 | [diff] [blame] | 812 | static IRExpr* mkSzExtendS16 ( IRType ty, UInt imm16 ) |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 813 | { |
| 814 | vassert(ty == Ity_I32 || ty == Ity_I64); |
| 815 | return ( ty == Ity_I64 ? |
| 816 | mkU64(extend_s_16to64(imm16)) : |
| 817 | mkU32(extend_s_16to32(imm16)) ); |
| 818 | } |
| 819 | |
| 820 | /* Sign extend imm32 -> IRExpr* */ |
cerion | 2831b00 | 2005-11-30 19:55:22 +0000 | [diff] [blame] | 821 | static IRExpr* mkSzExtendS32 ( IRType ty, UInt imm32 ) |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 822 | { |
| 823 | vassert(ty == Ity_I32 || ty == Ity_I64); |
| 824 | return ( ty == Ity_I64 ? |
| 825 | mkU64(extend_s_32to64(imm32)) : |
| 826 | mkU32(imm32) ); |
| 827 | } |
| 828 | |
| 829 | /* IR narrows I32/I64 -> I8/I16/I32 */ |
cerion | 2831b00 | 2005-11-30 19:55:22 +0000 | [diff] [blame] | 830 | static IRExpr* mkSzNarrow8 ( IRType ty, IRExpr* src ) |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 831 | { |
| 832 | vassert(ty == Ity_I32 || ty == Ity_I64); |
| 833 | return ty == Ity_I64 ? unop(Iop_64to8, src) : unop(Iop_32to8, src); |
| 834 | } |
| 835 | |
cerion | 2831b00 | 2005-11-30 19:55:22 +0000 | [diff] [blame] | 836 | static IRExpr* mkSzNarrow16 ( IRType ty, IRExpr* src ) |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 837 | { |
| 838 | vassert(ty == Ity_I32 || ty == Ity_I64); |
| 839 | return ty == Ity_I64 ? unop(Iop_64to16, src) : unop(Iop_32to16, src); |
| 840 | } |
| 841 | |
cerion | 2831b00 | 2005-11-30 19:55:22 +0000 | [diff] [blame] | 842 | static IRExpr* mkSzNarrow32 ( IRType ty, IRExpr* src ) |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 843 | { |
| 844 | vassert(ty == Ity_I32 || ty == Ity_I64); |
| 845 | return ty == Ity_I64 ? unop(Iop_64to32, src) : src; |
| 846 | } |
| 847 | |
| 848 | /* Signed/Unsigned IR widens I8/I16/I32 -> I32/I64 */ |
cerion | 2831b00 | 2005-11-30 19:55:22 +0000 | [diff] [blame] | 849 | static IRExpr* mkSzWiden8 ( IRType ty, IRExpr* src, Bool sined ) |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 850 | { |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 851 | IROp op; |
sewardj | 6332740 | 2006-01-25 03:26:27 +0000 | [diff] [blame] | 852 | vassert(ty == Ity_I32 || ty == Ity_I64); |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 853 | if (sined) op = (ty==Ity_I32) ? Iop_8Sto32 : Iop_8Sto64; |
| 854 | else op = (ty==Ity_I32) ? Iop_8Uto32 : Iop_8Uto64; |
| 855 | return unop(op, src); |
| 856 | } |
| 857 | |
cerion | 2831b00 | 2005-11-30 19:55:22 +0000 | [diff] [blame] | 858 | static IRExpr* mkSzWiden16 ( IRType ty, IRExpr* src, Bool sined ) |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 859 | { |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 860 | IROp op; |
sewardj | 6332740 | 2006-01-25 03:26:27 +0000 | [diff] [blame] | 861 | vassert(ty == Ity_I32 || ty == Ity_I64); |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 862 | if (sined) op = (ty==Ity_I32) ? Iop_16Sto32 : Iop_16Sto64; |
| 863 | else op = (ty==Ity_I32) ? Iop_16Uto32 : Iop_16Uto64; |
| 864 | return unop(op, src); |
| 865 | } |
| 866 | |
cerion | 2831b00 | 2005-11-30 19:55:22 +0000 | [diff] [blame] | 867 | static IRExpr* mkSzWiden32 ( IRType ty, IRExpr* src, Bool sined ) |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 868 | { |
| 869 | vassert(ty == Ity_I32 || ty == Ity_I64); |
| 870 | if (ty == Ity_I32) |
| 871 | return src; |
| 872 | return (sined) ? unop(Iop_32Sto64, src) : unop(Iop_32Uto64, src); |
| 873 | } |
cerion | 24d06f1 | 2005-11-09 21:34:20 +0000 | [diff] [blame] | 874 | |
cerion | 4a49b03 | 2005-11-08 16:23:07 +0000 | [diff] [blame] | 875 | |
sewardj | b51f0f4 | 2005-07-18 11:38:02 +0000 | [diff] [blame] | 876 | static Int integerGuestRegOffset ( UInt archreg ) |
cerion | 45b70ff | 2005-01-31 17:03:25 +0000 | [diff] [blame] | 877 | { |
sewardj | b51f0f4 | 2005-07-18 11:38:02 +0000 | [diff] [blame] | 878 | vassert(archreg < 32); |
| 879 | |
| 880 | // jrs: probably not necessary; only matters if we reference sub-parts |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 881 | // of the ppc registers, but that isn't the case |
sewardj | b51f0f4 | 2005-07-18 11:38:02 +0000 | [diff] [blame] | 882 | // later: this might affect Altivec though? |
| 883 | vassert(host_is_bigendian); |
| 884 | |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 885 | switch (archreg) { |
| 886 | case 0: return offsetofPPCGuestState(guest_GPR0); |
| 887 | case 1: return offsetofPPCGuestState(guest_GPR1); |
| 888 | case 2: return offsetofPPCGuestState(guest_GPR2); |
| 889 | case 3: return offsetofPPCGuestState(guest_GPR3); |
| 890 | case 4: return offsetofPPCGuestState(guest_GPR4); |
| 891 | case 5: return offsetofPPCGuestState(guest_GPR5); |
| 892 | case 6: return offsetofPPCGuestState(guest_GPR6); |
| 893 | case 7: return offsetofPPCGuestState(guest_GPR7); |
| 894 | case 8: return offsetofPPCGuestState(guest_GPR8); |
| 895 | case 9: return offsetofPPCGuestState(guest_GPR9); |
| 896 | case 10: return offsetofPPCGuestState(guest_GPR10); |
| 897 | case 11: return offsetofPPCGuestState(guest_GPR11); |
| 898 | case 12: return offsetofPPCGuestState(guest_GPR12); |
| 899 | case 13: return offsetofPPCGuestState(guest_GPR13); |
| 900 | case 14: return offsetofPPCGuestState(guest_GPR14); |
| 901 | case 15: return offsetofPPCGuestState(guest_GPR15); |
| 902 | case 16: return offsetofPPCGuestState(guest_GPR16); |
| 903 | case 17: return offsetofPPCGuestState(guest_GPR17); |
| 904 | case 18: return offsetofPPCGuestState(guest_GPR18); |
| 905 | case 19: return offsetofPPCGuestState(guest_GPR19); |
| 906 | case 20: return offsetofPPCGuestState(guest_GPR20); |
| 907 | case 21: return offsetofPPCGuestState(guest_GPR21); |
| 908 | case 22: return offsetofPPCGuestState(guest_GPR22); |
| 909 | case 23: return offsetofPPCGuestState(guest_GPR23); |
| 910 | case 24: return offsetofPPCGuestState(guest_GPR24); |
| 911 | case 25: return offsetofPPCGuestState(guest_GPR25); |
| 912 | case 26: return offsetofPPCGuestState(guest_GPR26); |
| 913 | case 27: return offsetofPPCGuestState(guest_GPR27); |
| 914 | case 28: return offsetofPPCGuestState(guest_GPR28); |
| 915 | case 29: return offsetofPPCGuestState(guest_GPR29); |
| 916 | case 30: return offsetofPPCGuestState(guest_GPR30); |
| 917 | case 31: return offsetofPPCGuestState(guest_GPR31); |
| 918 | default: break; |
sewardj | b51f0f4 | 2005-07-18 11:38:02 +0000 | [diff] [blame] | 919 | } |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 920 | vpanic("integerGuestRegOffset(ppc,be)"); /*notreached*/ |
sewardj | b51f0f4 | 2005-07-18 11:38:02 +0000 | [diff] [blame] | 921 | } |
| 922 | |
| 923 | static IRExpr* getIReg ( UInt archreg ) |
| 924 | { |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 925 | IRType ty = mode64 ? Ity_I64 : Ity_I32; |
sewardj | b51f0f4 | 2005-07-18 11:38:02 +0000 | [diff] [blame] | 926 | vassert(archreg < 32); |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 927 | return IRExpr_Get( integerGuestRegOffset(archreg), ty ); |
sewardj | b51f0f4 | 2005-07-18 11:38:02 +0000 | [diff] [blame] | 928 | } |
| 929 | |
| 930 | /* Ditto, but write to a reg instead. */ |
| 931 | static void putIReg ( UInt archreg, IRExpr* e ) |
| 932 | { |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 933 | IRType ty = mode64 ? Ity_I64 : Ity_I32; |
sewardj | b51f0f4 | 2005-07-18 11:38:02 +0000 | [diff] [blame] | 934 | vassert(archreg < 32); |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 935 | vassert(typeOfIRExpr(irbb->tyenv, e) == ty ); |
sewardj | b51f0f4 | 2005-07-18 11:38:02 +0000 | [diff] [blame] | 936 | stmt( IRStmt_Put(integerGuestRegOffset(archreg), e) ); |
| 937 | } |
| 938 | |
| 939 | |
| 940 | static Int floatGuestRegOffset ( UInt archreg ) |
| 941 | { |
| 942 | vassert(archreg < 32); |
| 943 | |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 944 | switch (archreg) { |
| 945 | case 0: return offsetofPPCGuestState(guest_FPR0); |
| 946 | case 1: return offsetofPPCGuestState(guest_FPR1); |
| 947 | case 2: return offsetofPPCGuestState(guest_FPR2); |
| 948 | case 3: return offsetofPPCGuestState(guest_FPR3); |
| 949 | case 4: return offsetofPPCGuestState(guest_FPR4); |
| 950 | case 5: return offsetofPPCGuestState(guest_FPR5); |
| 951 | case 6: return offsetofPPCGuestState(guest_FPR6); |
| 952 | case 7: return offsetofPPCGuestState(guest_FPR7); |
| 953 | case 8: return offsetofPPCGuestState(guest_FPR8); |
| 954 | case 9: return offsetofPPCGuestState(guest_FPR9); |
| 955 | case 10: return offsetofPPCGuestState(guest_FPR10); |
| 956 | case 11: return offsetofPPCGuestState(guest_FPR11); |
| 957 | case 12: return offsetofPPCGuestState(guest_FPR12); |
| 958 | case 13: return offsetofPPCGuestState(guest_FPR13); |
| 959 | case 14: return offsetofPPCGuestState(guest_FPR14); |
| 960 | case 15: return offsetofPPCGuestState(guest_FPR15); |
| 961 | case 16: return offsetofPPCGuestState(guest_FPR16); |
| 962 | case 17: return offsetofPPCGuestState(guest_FPR17); |
| 963 | case 18: return offsetofPPCGuestState(guest_FPR18); |
| 964 | case 19: return offsetofPPCGuestState(guest_FPR19); |
| 965 | case 20: return offsetofPPCGuestState(guest_FPR20); |
| 966 | case 21: return offsetofPPCGuestState(guest_FPR21); |
| 967 | case 22: return offsetofPPCGuestState(guest_FPR22); |
| 968 | case 23: return offsetofPPCGuestState(guest_FPR23); |
| 969 | case 24: return offsetofPPCGuestState(guest_FPR24); |
| 970 | case 25: return offsetofPPCGuestState(guest_FPR25); |
| 971 | case 26: return offsetofPPCGuestState(guest_FPR26); |
| 972 | case 27: return offsetofPPCGuestState(guest_FPR27); |
| 973 | case 28: return offsetofPPCGuestState(guest_FPR28); |
| 974 | case 29: return offsetofPPCGuestState(guest_FPR29); |
| 975 | case 30: return offsetofPPCGuestState(guest_FPR30); |
| 976 | case 31: return offsetofPPCGuestState(guest_FPR31); |
| 977 | default: break; |
sewardj | b51f0f4 | 2005-07-18 11:38:02 +0000 | [diff] [blame] | 978 | } |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 979 | vpanic("floatGuestRegOffset(ppc)"); /*notreached*/ |
sewardj | b51f0f4 | 2005-07-18 11:38:02 +0000 | [diff] [blame] | 980 | } |
| 981 | |
| 982 | static IRExpr* getFReg ( UInt archreg ) |
| 983 | { |
| 984 | vassert(archreg < 32); |
| 985 | return IRExpr_Get( floatGuestRegOffset(archreg), Ity_F64 ); |
| 986 | } |
| 987 | |
| 988 | /* Ditto, but write to a reg instead. */ |
| 989 | static void putFReg ( UInt archreg, IRExpr* e ) |
| 990 | { |
| 991 | vassert(archreg < 32); |
| 992 | vassert(typeOfIRExpr(irbb->tyenv, e) == Ity_F64); |
| 993 | stmt( IRStmt_Put(floatGuestRegOffset(archreg), e) ); |
| 994 | } |
| 995 | |
| 996 | |
| 997 | static Int vectorGuestRegOffset ( UInt archreg ) |
| 998 | { |
| 999 | vassert(archreg < 32); |
| 1000 | |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 1001 | switch (archreg) { |
| 1002 | case 0: return offsetofPPCGuestState(guest_VR0); |
| 1003 | case 1: return offsetofPPCGuestState(guest_VR1); |
| 1004 | case 2: return offsetofPPCGuestState(guest_VR2); |
| 1005 | case 3: return offsetofPPCGuestState(guest_VR3); |
| 1006 | case 4: return offsetofPPCGuestState(guest_VR4); |
| 1007 | case 5: return offsetofPPCGuestState(guest_VR5); |
| 1008 | case 6: return offsetofPPCGuestState(guest_VR6); |
| 1009 | case 7: return offsetofPPCGuestState(guest_VR7); |
| 1010 | case 8: return offsetofPPCGuestState(guest_VR8); |
| 1011 | case 9: return offsetofPPCGuestState(guest_VR9); |
| 1012 | case 10: return offsetofPPCGuestState(guest_VR10); |
| 1013 | case 11: return offsetofPPCGuestState(guest_VR11); |
| 1014 | case 12: return offsetofPPCGuestState(guest_VR12); |
| 1015 | case 13: return offsetofPPCGuestState(guest_VR13); |
| 1016 | case 14: return offsetofPPCGuestState(guest_VR14); |
| 1017 | case 15: return offsetofPPCGuestState(guest_VR15); |
| 1018 | case 16: return offsetofPPCGuestState(guest_VR16); |
| 1019 | case 17: return offsetofPPCGuestState(guest_VR17); |
| 1020 | case 18: return offsetofPPCGuestState(guest_VR18); |
| 1021 | case 19: return offsetofPPCGuestState(guest_VR19); |
| 1022 | case 20: return offsetofPPCGuestState(guest_VR20); |
| 1023 | case 21: return offsetofPPCGuestState(guest_VR21); |
| 1024 | case 22: return offsetofPPCGuestState(guest_VR22); |
| 1025 | case 23: return offsetofPPCGuestState(guest_VR23); |
| 1026 | case 24: return offsetofPPCGuestState(guest_VR24); |
| 1027 | case 25: return offsetofPPCGuestState(guest_VR25); |
| 1028 | case 26: return offsetofPPCGuestState(guest_VR26); |
| 1029 | case 27: return offsetofPPCGuestState(guest_VR27); |
| 1030 | case 28: return offsetofPPCGuestState(guest_VR28); |
| 1031 | case 29: return offsetofPPCGuestState(guest_VR29); |
| 1032 | case 30: return offsetofPPCGuestState(guest_VR30); |
| 1033 | case 31: return offsetofPPCGuestState(guest_VR31); |
| 1034 | default: break; |
sewardj | b51f0f4 | 2005-07-18 11:38:02 +0000 | [diff] [blame] | 1035 | } |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 1036 | vpanic("vextorGuestRegOffset(ppc)"); /*notreached*/ |
sewardj | b51f0f4 | 2005-07-18 11:38:02 +0000 | [diff] [blame] | 1037 | } |
| 1038 | |
| 1039 | static IRExpr* getVReg ( UInt archreg ) |
| 1040 | { |
| 1041 | vassert(archreg < 32); |
| 1042 | return IRExpr_Get( vectorGuestRegOffset(archreg), Ity_V128 ); |
| 1043 | } |
| 1044 | |
| 1045 | /* Ditto, but write to a reg instead. */ |
| 1046 | static void putVReg ( UInt archreg, IRExpr* e ) |
| 1047 | { |
| 1048 | vassert(archreg < 32); |
| 1049 | vassert(typeOfIRExpr(irbb->tyenv, e) == Ity_V128); |
| 1050 | stmt( IRStmt_Put(vectorGuestRegOffset(archreg), e) ); |
| 1051 | } |
| 1052 | |
| 1053 | static Int guestCR321offset ( UInt cr ) |
| 1054 | { |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 1055 | switch (cr) { |
| 1056 | case 0: return offsetofPPCGuestState(guest_CR0_321 ); |
| 1057 | case 1: return offsetofPPCGuestState(guest_CR1_321 ); |
| 1058 | case 2: return offsetofPPCGuestState(guest_CR2_321 ); |
| 1059 | case 3: return offsetofPPCGuestState(guest_CR3_321 ); |
| 1060 | case 4: return offsetofPPCGuestState(guest_CR4_321 ); |
| 1061 | case 5: return offsetofPPCGuestState(guest_CR5_321 ); |
| 1062 | case 6: return offsetofPPCGuestState(guest_CR6_321 ); |
| 1063 | case 7: return offsetofPPCGuestState(guest_CR7_321 ); |
| 1064 | default: vpanic("guestCR321offset(ppc)"); |
sewardj | b51f0f4 | 2005-07-18 11:38:02 +0000 | [diff] [blame] | 1065 | } |
| 1066 | } |
| 1067 | |
| 1068 | static Int guestCR0offset ( UInt cr ) |
| 1069 | { |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 1070 | switch (cr) { |
| 1071 | case 0: return offsetofPPCGuestState(guest_CR0_0 ); |
| 1072 | case 1: return offsetofPPCGuestState(guest_CR1_0 ); |
| 1073 | case 2: return offsetofPPCGuestState(guest_CR2_0 ); |
| 1074 | case 3: return offsetofPPCGuestState(guest_CR3_0 ); |
| 1075 | case 4: return offsetofPPCGuestState(guest_CR4_0 ); |
| 1076 | case 5: return offsetofPPCGuestState(guest_CR5_0 ); |
| 1077 | case 6: return offsetofPPCGuestState(guest_CR6_0 ); |
| 1078 | case 7: return offsetofPPCGuestState(guest_CR7_0 ); |
| 1079 | default: vpanic("guestCR3offset(ppc)"); |
sewardj | b51f0f4 | 2005-07-18 11:38:02 +0000 | [diff] [blame] | 1080 | } |
sewardj | b51f0f4 | 2005-07-18 11:38:02 +0000 | [diff] [blame] | 1081 | } |
| 1082 | |
cerion | 07b07a9 | 2005-12-22 14:32:35 +0000 | [diff] [blame] | 1083 | // ROTL(src32/64, rot_amt5/6) |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 1084 | static IRExpr* /* :: Ity_I32/64 */ ROTL ( IRExpr* src, |
| 1085 | IRExpr* rot_amt ) |
sewardj | b51f0f4 | 2005-07-18 11:38:02 +0000 | [diff] [blame] | 1086 | { |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 1087 | IRExpr *mask, *rot; |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 1088 | vassert(typeOfIRExpr(irbb->tyenv,rot_amt) == Ity_I8); |
sewardj | b51f0f4 | 2005-07-18 11:38:02 +0000 | [diff] [blame] | 1089 | |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 1090 | if (typeOfIRExpr(irbb->tyenv,src) == Ity_I64) { |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 1091 | // rot = (src << rot_amt) | (src >> (64-rot_amt)) |
| 1092 | mask = binop(Iop_And8, rot_amt, mkU8(63)); |
| 1093 | rot = binop(Iop_Or64, |
| 1094 | binop(Iop_Shl64, src, mask), |
| 1095 | binop(Iop_Shr64, src, binop(Iop_Sub8, mkU8(64), mask))); |
| 1096 | } else { |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 1097 | // rot = (src << rot_amt) | (src >> (32-rot_amt)) |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 1098 | mask = binop(Iop_And8, rot_amt, mkU8(31)); |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 1099 | rot = binop(Iop_Or32, |
| 1100 | binop(Iop_Shl32, src, mask), |
| 1101 | binop(Iop_Shr32, src, binop(Iop_Sub8, mkU8(32), mask))); |
cerion | 2831b00 | 2005-11-30 19:55:22 +0000 | [diff] [blame] | 1102 | } |
sewardj | c965953 | 2005-07-21 21:33:57 +0000 | [diff] [blame] | 1103 | /* Note: the MuxOX is not merely an optimisation; it's needed |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 1104 | because otherwise the Shr is a shift by the word size when |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 1105 | mask denotes zero. For rotates by immediates, a lot of |
sewardj | c965953 | 2005-07-21 21:33:57 +0000 | [diff] [blame] | 1106 | this junk gets folded out. */ |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 1107 | return IRExpr_Mux0X( mask, /* zero rotate */ src, |
| 1108 | /* non-zero rotate */ rot ); |
cerion | 45b70ff | 2005-01-31 17:03:25 +0000 | [diff] [blame] | 1109 | } |
cerion | 896a137 | 2005-01-25 12:24:25 +0000 | [diff] [blame] | 1110 | |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 1111 | #if 0 |
| 1112 | /* ROTL32_64(src64, rot_amt5) |
| 1113 | Weirdo 32bit rotl on ppc64: |
| 1114 | rot32 = ROTL(src_lo32,y); |
| 1115 | return (rot32|rot32); |
| 1116 | */ |
| 1117 | static IRExpr* /* :: Ity_I64 */ ROTL32_64 ( IRExpr* src64, |
| 1118 | IRExpr* rot_amt ) |
sewardj | 87e651f | 2005-09-09 08:31:18 +0000 | [diff] [blame] | 1119 | { |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 1120 | IRExpr *mask, *rot32; |
| 1121 | vassert(mode64); // used only in 64bit mode |
| 1122 | vassert(typeOfIRExpr(irbb->tyenv,src64) == Ity_I64); |
| 1123 | vassert(typeOfIRExpr(irbb->tyenv,rot_amt) == Ity_I8); |
| 1124 | |
| 1125 | mask = binop(Iop_And8, rot_amt, mkU8(31)); |
| 1126 | rot32 = ROTL( unop(Iop_64to32, src64), rot_amt ); |
| 1127 | |
| 1128 | return binop(Iop_Or64, |
| 1129 | binop(Iop_Shl64, unop(Iop_32Uto64, rot32), mkU8(32)), |
cerion | 2831b00 | 2005-11-30 19:55:22 +0000 | [diff] [blame] | 1130 | unop(Iop_32Uto64, rot32)); |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 1131 | } |
| 1132 | #endif |
| 1133 | |
| 1134 | |
| 1135 | /* Standard effective address calc: (rA + rB) */ |
| 1136 | static IRExpr* ea_rA_idxd ( UInt rA, UInt rB ) |
| 1137 | { |
| 1138 | IRType ty = mode64 ? Ity_I64 : Ity_I32; |
| 1139 | vassert(rA < 32); |
| 1140 | vassert(rB < 32); |
cerion | 2831b00 | 2005-11-30 19:55:22 +0000 | [diff] [blame] | 1141 | return binop(mkSzOp(ty, Iop_Add8), getIReg(rA), getIReg(rB)); |
sewardj | 87e651f | 2005-09-09 08:31:18 +0000 | [diff] [blame] | 1142 | } |
| 1143 | |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 1144 | /* Standard effective address calc: (rA + simm) */ |
| 1145 | static IRExpr* ea_rA_simm ( UInt rA, UInt simm16 ) |
sewardj | 87e651f | 2005-09-09 08:31:18 +0000 | [diff] [blame] | 1146 | { |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 1147 | IRType ty = mode64 ? Ity_I64 : Ity_I32; |
| 1148 | vassert(rA < 32); |
cerion | 2831b00 | 2005-11-30 19:55:22 +0000 | [diff] [blame] | 1149 | return binop(mkSzOp(ty, Iop_Add8), getIReg(rA), |
| 1150 | mkSzExtendS16(ty, simm16)); |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 1151 | } |
| 1152 | |
| 1153 | /* Standard effective address calc: (rA|0) */ |
| 1154 | static IRExpr* ea_rAor0 ( UInt rA ) |
| 1155 | { |
| 1156 | IRType ty = mode64 ? Ity_I64 : Ity_I32; |
| 1157 | vassert(rA < 32); |
sewardj | 87e651f | 2005-09-09 08:31:18 +0000 | [diff] [blame] | 1158 | if (rA == 0) { |
cerion | 2831b00 | 2005-11-30 19:55:22 +0000 | [diff] [blame] | 1159 | return mkSzImm(ty, 0); |
sewardj | 87e651f | 2005-09-09 08:31:18 +0000 | [diff] [blame] | 1160 | } else { |
| 1161 | return getIReg(rA); |
| 1162 | } |
| 1163 | } |
| 1164 | |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 1165 | /* Standard effective address calc: (rA|0) + rB */ |
| 1166 | static IRExpr* ea_rAor0_idxd ( UInt rA, UInt rB ) |
| 1167 | { |
| 1168 | vassert(rA < 32); |
| 1169 | vassert(rB < 32); |
| 1170 | return (rA == 0) ? getIReg(rB) : ea_rA_idxd( rA, rB ); |
| 1171 | } |
| 1172 | |
| 1173 | /* Standard effective address calc: (rA|0) + simm16 */ |
| 1174 | static IRExpr* ea_rAor0_simm ( UInt rA, UInt simm16 ) |
| 1175 | { |
| 1176 | IRType ty = mode64 ? Ity_I64 : Ity_I32; |
| 1177 | vassert(rA < 32); |
| 1178 | if (rA == 0) { |
cerion | 2831b00 | 2005-11-30 19:55:22 +0000 | [diff] [blame] | 1179 | return mkSzExtendS16(ty, simm16); |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 1180 | } else { |
| 1181 | return ea_rA_simm( rA, simm16 ); |
| 1182 | } |
| 1183 | } |
| 1184 | |
| 1185 | |
| 1186 | /* Align effective address */ |
| 1187 | static IRExpr* addr_align( IRExpr* addr, UChar align ) |
| 1188 | { |
| 1189 | IRType ty = mode64 ? Ity_I64 : Ity_I32; |
| 1190 | Long mask; |
| 1191 | switch (align) { |
cerion | 2831b00 | 2005-11-30 19:55:22 +0000 | [diff] [blame] | 1192 | case 1: return addr; // byte aligned |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 1193 | case 2: mask = ((Long)-1) << 1; break; // half-word aligned |
| 1194 | case 4: mask = ((Long)-1) << 2; break; // word aligned |
| 1195 | case 16: mask = ((Long)-1) << 4; break; // quad-word aligned |
| 1196 | default: |
| 1197 | vex_printf("addr_align: align = %u\n", align); |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 1198 | vpanic("addr_align(ppc)"); |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 1199 | } |
| 1200 | |
| 1201 | vassert(typeOfIRExpr(irbb->tyenv,addr) == ty); |
cerion | fb197c4 | 2005-12-24 12:32:10 +0000 | [diff] [blame] | 1202 | return binop( mkSzOp(ty, Iop_And8), addr, mkSzImm(ty, mask) ); |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 1203 | } |
| 1204 | |
cerion | 896a137 | 2005-01-25 12:24:25 +0000 | [diff] [blame] | 1205 | |
sewardj | cf8986c | 2006-01-18 04:14:52 +0000 | [diff] [blame] | 1206 | /* Generate AbiHints which mark points at which the ELF ppc64 ABI says |
| 1207 | that the stack red zone (viz, -288(r1) .. -1(r1)) becomes |
| 1208 | undefined. That is at function calls and returns. Only in 64-bit |
| 1209 | mode - ELF ppc32 doesn't have this "feature". |
| 1210 | */ |
| 1211 | static void make_redzone_AbiHint ( HChar* who ) |
| 1212 | { |
| 1213 | if (0) vex_printf("AbiHint: %s\n", who); |
| 1214 | vassert(mode64); |
| 1215 | stmt( IRStmt_AbiHint( |
| 1216 | binop(Iop_Sub64, getIReg(1), mkU64(288)), |
| 1217 | 288 |
| 1218 | )); |
| 1219 | } |
| 1220 | |
| 1221 | |
cerion | 896a137 | 2005-01-25 12:24:25 +0000 | [diff] [blame] | 1222 | /*------------------------------------------------------------*/ |
sewardj | b51f0f4 | 2005-07-18 11:38:02 +0000 | [diff] [blame] | 1223 | /*--- Helpers for condition codes. ---*/ |
cerion | 896a137 | 2005-01-25 12:24:25 +0000 | [diff] [blame] | 1224 | /*------------------------------------------------------------*/ |
| 1225 | |
sewardj | b51f0f4 | 2005-07-18 11:38:02 +0000 | [diff] [blame] | 1226 | /* Condition register layout. |
cerion | 896a137 | 2005-01-25 12:24:25 +0000 | [diff] [blame] | 1227 | |
sewardj | b51f0f4 | 2005-07-18 11:38:02 +0000 | [diff] [blame] | 1228 | In the hardware, CR is laid out like this. The leftmost end is the |
| 1229 | most significant bit in the register; however the IBM documentation |
| 1230 | numbers the bits backwards for some reason. |
| 1231 | |
| 1232 | CR0 CR1 .......... CR6 CR7 |
| 1233 | 0 .. 3 ....................... 28 .. 31 (IBM bit numbering) |
| 1234 | 31 28 3 0 (normal bit numbering) |
| 1235 | |
cerion | edf7fc5 | 2005-11-18 20:57:41 +0000 | [diff] [blame] | 1236 | Each CR field is 4 bits: [<,>,==,SO] |
sewardj | b51f0f4 | 2005-07-18 11:38:02 +0000 | [diff] [blame] | 1237 | |
cerion | edf7fc5 | 2005-11-18 20:57:41 +0000 | [diff] [blame] | 1238 | Hence in IBM's notation, BI=0 is CR7[SO], BI=1 is CR7[==], etc. |
sewardj | b51f0f4 | 2005-07-18 11:38:02 +0000 | [diff] [blame] | 1239 | |
| 1240 | Indexing from BI to guest state: |
| 1241 | |
| 1242 | let n = BI / 4 |
| 1243 | off = BI % 4 |
| 1244 | this references CR n: |
| 1245 | |
cerion | edf7fc5 | 2005-11-18 20:57:41 +0000 | [diff] [blame] | 1246 | off==0 -> guest_CRn_321 >> 3 |
| 1247 | off==1 -> guest_CRn_321 >> 2 |
| 1248 | off==2 -> guest_CRn_321 >> 1 |
sewardj | b51f0f4 | 2005-07-18 11:38:02 +0000 | [diff] [blame] | 1249 | off==3 -> guest_CRn_SO |
sewardj | b51f0f4 | 2005-07-18 11:38:02 +0000 | [diff] [blame] | 1250 | |
| 1251 | Bear in mind the only significant bit in guest_CRn_SO is bit 0 |
cerion | edf7fc5 | 2005-11-18 20:57:41 +0000 | [diff] [blame] | 1252 | (normal notation) and in guest_CRn_321 the significant bits are |
sewardj | b51f0f4 | 2005-07-18 11:38:02 +0000 | [diff] [blame] | 1253 | 3, 2 and 1 (normal notation). |
| 1254 | */ |
cerion | edf7fc5 | 2005-11-18 20:57:41 +0000 | [diff] [blame] | 1255 | |
| 1256 | static void putCR321 ( UInt cr, IRExpr* e ) |
| 1257 | { |
| 1258 | vassert(cr < 8); |
| 1259 | vassert(typeOfIRExpr(irbb->tyenv, e) == Ity_I8); |
| 1260 | stmt( IRStmt_Put(guestCR321offset(cr), e) ); |
| 1261 | } |
| 1262 | |
| 1263 | static void putCR0 ( UInt cr, IRExpr* e ) |
| 1264 | { |
| 1265 | vassert(cr < 8); |
| 1266 | vassert(typeOfIRExpr(irbb->tyenv, e) == Ity_I8); |
| 1267 | stmt( IRStmt_Put(guestCR0offset(cr), e) ); |
| 1268 | } |
| 1269 | |
| 1270 | static IRExpr* /* :: Ity_I8 */ getCR0 ( UInt cr ) |
| 1271 | { |
| 1272 | vassert(cr < 8); |
| 1273 | return IRExpr_Get(guestCR0offset(cr), Ity_I8); |
| 1274 | } |
| 1275 | |
| 1276 | static IRExpr* /* :: Ity_I8 */ getCR321 ( UInt cr ) |
| 1277 | { |
| 1278 | vassert(cr < 8); |
| 1279 | return IRExpr_Get(guestCR321offset(cr), Ity_I8); |
| 1280 | } |
| 1281 | |
sewardj | b51f0f4 | 2005-07-18 11:38:02 +0000 | [diff] [blame] | 1282 | /* Fetch the specified CR bit (as per IBM/hardware notation) and |
| 1283 | return it at the bottom of an I32; the top 31 bits are guaranteed |
| 1284 | to be zero. */ |
| 1285 | static IRExpr* /* :: Ity_I32 */ getCRbit ( UInt bi ) |
cerion | 896a137 | 2005-01-25 12:24:25 +0000 | [diff] [blame] | 1286 | { |
sewardj | b51f0f4 | 2005-07-18 11:38:02 +0000 | [diff] [blame] | 1287 | UInt n = bi / 4; |
| 1288 | UInt off = bi % 4; |
| 1289 | vassert(bi < 32); |
| 1290 | if (off == 3) { |
| 1291 | /* Fetch the SO bit for this CR field */ |
| 1292 | /* Note: And32 is redundant paranoia iff guest state only has 0 |
| 1293 | or 1 in that slot. */ |
| 1294 | return binop(Iop_And32, unop(Iop_8Uto32, getCR0(n)), mkU32(1)); |
| 1295 | } else { |
| 1296 | /* Fetch the <, > or == bit for this CR field */ |
| 1297 | return binop( Iop_And32, |
| 1298 | binop( Iop_Shr32, |
| 1299 | unop(Iop_8Uto32, getCR321(n)), |
sewardj | c7cd214 | 2005-09-09 22:31:49 +0000 | [diff] [blame] | 1300 | mkU8(toUChar(3-off)) ), |
sewardj | b51f0f4 | 2005-07-18 11:38:02 +0000 | [diff] [blame] | 1301 | mkU32(1) ); |
| 1302 | } |
cerion | 91ad536 | 2005-01-27 23:02:41 +0000 | [diff] [blame] | 1303 | } |
| 1304 | |
sewardj | b51f0f4 | 2005-07-18 11:38:02 +0000 | [diff] [blame] | 1305 | /* Dually, write the least significant bit of BIT to the specified CR |
| 1306 | bit. Indexing as per getCRbit. */ |
| 1307 | static void putCRbit ( UInt bi, IRExpr* bit ) |
| 1308 | { |
sewardj | 197bd17 | 2005-10-12 11:34:33 +0000 | [diff] [blame] | 1309 | UInt n, off; |
sewardj | b51f0f4 | 2005-07-18 11:38:02 +0000 | [diff] [blame] | 1310 | IRExpr* safe; |
| 1311 | vassert(typeOfIRExpr(irbb->tyenv,bit) == Ity_I32); |
| 1312 | safe = binop(Iop_And32, bit, mkU32(1)); |
sewardj | 197bd17 | 2005-10-12 11:34:33 +0000 | [diff] [blame] | 1313 | n = bi / 4; |
| 1314 | off = bi % 4; |
sewardj | b51f0f4 | 2005-07-18 11:38:02 +0000 | [diff] [blame] | 1315 | vassert(bi < 32); |
| 1316 | if (off == 3) { |
| 1317 | /* This is the SO bit for this CR field */ |
| 1318 | putCR0(n, unop(Iop_32to8, safe)); |
| 1319 | } else { |
| 1320 | off = 3 - off; |
| 1321 | vassert(off == 1 || off == 2 || off == 3); |
| 1322 | putCR321( |
| 1323 | n, |
| 1324 | unop( Iop_32to8, |
| 1325 | binop( Iop_Or32, |
| 1326 | /* old value with field masked out */ |
| 1327 | binop(Iop_And32, unop(Iop_8Uto32, getCR321(n)), |
| 1328 | mkU32(~(1 << off))), |
| 1329 | /* new value in the right place */ |
sewardj | c7cd214 | 2005-09-09 22:31:49 +0000 | [diff] [blame] | 1330 | binop(Iop_Shl32, safe, mkU8(toUChar(off))) |
sewardj | b51f0f4 | 2005-07-18 11:38:02 +0000 | [diff] [blame] | 1331 | ) |
| 1332 | ) |
| 1333 | ); |
| 1334 | } |
| 1335 | } |
| 1336 | |
sewardj | b51f0f4 | 2005-07-18 11:38:02 +0000 | [diff] [blame] | 1337 | /* Fetch the specified CR bit (as per IBM/hardware notation) and |
| 1338 | return it somewhere in an I32; it does not matter where, but |
| 1339 | whichever bit it is, all other bits are guaranteed to be zero. In |
| 1340 | other words, the I32-typed expression will be zero if the bit is |
| 1341 | zero and nonzero if the bit is 1. Write into *where the index |
| 1342 | of where the bit will be. */ |
| 1343 | |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 1344 | static |
| 1345 | IRExpr* /* :: Ity_I32 */ getCRbit_anywhere ( UInt bi, Int* where ) |
sewardj | b51f0f4 | 2005-07-18 11:38:02 +0000 | [diff] [blame] | 1346 | { |
| 1347 | UInt n = bi / 4; |
| 1348 | UInt off = bi % 4; |
| 1349 | vassert(bi < 32); |
| 1350 | if (off == 3) { |
| 1351 | /* Fetch the SO bit for this CR field */ |
| 1352 | /* Note: And32 is redundant paranoia iff guest state only has 0 |
| 1353 | or 1 in that slot. */ |
| 1354 | *where = 0; |
| 1355 | return binop(Iop_And32, unop(Iop_8Uto32, getCR0(n)), mkU32(1)); |
| 1356 | } else { |
| 1357 | /* Fetch the <, > or == bit for this CR field */ |
| 1358 | *where = 3-off; |
| 1359 | return binop( Iop_And32, |
| 1360 | unop(Iop_8Uto32, getCR321(n)), |
| 1361 | mkU32(1 << (3-off)) ); |
| 1362 | } |
| 1363 | } |
| 1364 | |
sewardj | b51f0f4 | 2005-07-18 11:38:02 +0000 | [diff] [blame] | 1365 | /* Set the CR0 flags following an arithmetic operation. |
| 1366 | (Condition Register CR0 Field Definition, PPC32 p60) |
cerion | 896a137 | 2005-01-25 12:24:25 +0000 | [diff] [blame] | 1367 | */ |
cerion | edf7fc5 | 2005-11-18 20:57:41 +0000 | [diff] [blame] | 1368 | static IRExpr* getXER_SO ( void ); |
sewardj | 20ef547 | 2005-07-21 14:48:31 +0000 | [diff] [blame] | 1369 | static void set_CR0 ( IRExpr* result ) |
cerion | 896a137 | 2005-01-25 12:24:25 +0000 | [diff] [blame] | 1370 | { |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 1371 | vassert(typeOfIRExpr(irbb->tyenv,result) == Ity_I32 || |
| 1372 | typeOfIRExpr(irbb->tyenv,result) == Ity_I64); |
| 1373 | if (mode64) { |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 1374 | putCR321( 0, unop(Iop_64to8, |
cerion | 2831b00 | 2005-11-30 19:55:22 +0000 | [diff] [blame] | 1375 | binop(Iop_CmpORD64S, result, mkU64(0))) ); |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 1376 | } else { |
| 1377 | putCR321( 0, unop(Iop_32to8, |
| 1378 | binop(Iop_CmpORD32S, result, mkU32(0))) ); |
| 1379 | } |
sewardj | b51f0f4 | 2005-07-18 11:38:02 +0000 | [diff] [blame] | 1380 | putCR0( 0, getXER_SO() ); |
cerion | 896a137 | 2005-01-25 12:24:25 +0000 | [diff] [blame] | 1381 | } |
cerion | 896a137 | 2005-01-25 12:24:25 +0000 | [diff] [blame] | 1382 | |
sewardj | 20ef547 | 2005-07-21 14:48:31 +0000 | [diff] [blame] | 1383 | |
cerion | edf7fc5 | 2005-11-18 20:57:41 +0000 | [diff] [blame] | 1384 | /* Set the CR6 flags following an AltiVec compare operation. */ |
| 1385 | static void set_AV_CR6 ( IRExpr* result, Bool test_all_ones ) |
| 1386 | { |
| 1387 | /* CR6[0:3] = {all_ones, 0, all_zeros, 0} |
| 1388 | all_ones = (v[0] && v[1] && v[2] && v[3]) |
| 1389 | all_zeros = ~(v[0] || v[1] || v[2] || v[3]) |
| 1390 | */ |
| 1391 | IRTemp v0 = newTemp(Ity_V128); |
| 1392 | IRTemp v1 = newTemp(Ity_V128); |
| 1393 | IRTemp v2 = newTemp(Ity_V128); |
| 1394 | IRTemp v3 = newTemp(Ity_V128); |
| 1395 | IRTemp rOnes = newTemp(Ity_I8); |
| 1396 | IRTemp rZeros = newTemp(Ity_I8); |
| 1397 | |
| 1398 | vassert(typeOfIRExpr(irbb->tyenv,result) == Ity_V128); |
| 1399 | |
| 1400 | assign( v0, result ); |
| 1401 | assign( v1, binop(Iop_ShrV128, result, mkU8(32)) ); |
| 1402 | assign( v2, binop(Iop_ShrV128, result, mkU8(64)) ); |
| 1403 | assign( v3, binop(Iop_ShrV128, result, mkU8(96)) ); |
| 1404 | |
| 1405 | assign( rZeros, unop(Iop_1Uto8, |
| 1406 | binop(Iop_CmpEQ32, mkU32(0xFFFFFFFF), |
| 1407 | unop(Iop_Not32, |
| 1408 | unop(Iop_V128to32, |
| 1409 | binop(Iop_OrV128, |
| 1410 | binop(Iop_OrV128, mkexpr(v0), mkexpr(v1)), |
| 1411 | binop(Iop_OrV128, mkexpr(v2), mkexpr(v3)))) |
| 1412 | ))) ); |
| 1413 | |
| 1414 | if (test_all_ones) { |
| 1415 | assign( rOnes, unop(Iop_1Uto8, |
| 1416 | binop(Iop_CmpEQ32, mkU32(0xFFFFFFFF), |
| 1417 | unop(Iop_V128to32, |
| 1418 | binop(Iop_AndV128, |
| 1419 | binop(Iop_AndV128, mkexpr(v0), mkexpr(v1)), |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 1420 | binop(Iop_AndV128, mkexpr(v2), mkexpr(v3))) |
| 1421 | ))) ); |
cerion | edf7fc5 | 2005-11-18 20:57:41 +0000 | [diff] [blame] | 1422 | putCR321( 6, binop(Iop_Or8, |
| 1423 | binop(Iop_Shl8, mkexpr(rOnes), mkU8(3)), |
| 1424 | binop(Iop_Shl8, mkexpr(rZeros), mkU8(1))) ); |
| 1425 | } else { |
| 1426 | putCR321( 6, binop(Iop_Shl8, mkexpr(rZeros), mkU8(1)) ); |
| 1427 | } |
| 1428 | putCR0( 6, mkU8(0) ); |
| 1429 | } |
| 1430 | |
| 1431 | |
| 1432 | |
| 1433 | /*------------------------------------------------------------*/ |
| 1434 | /*--- Helpers for XER flags. ---*/ |
| 1435 | /*------------------------------------------------------------*/ |
| 1436 | |
| 1437 | static void putXER_SO ( IRExpr* e ) |
| 1438 | { |
sewardj | 6332740 | 2006-01-25 03:26:27 +0000 | [diff] [blame] | 1439 | IRExpr* so; |
cerion | edf7fc5 | 2005-11-18 20:57:41 +0000 | [diff] [blame] | 1440 | vassert(typeOfIRExpr(irbb->tyenv, e) == Ity_I8); |
sewardj | 6332740 | 2006-01-25 03:26:27 +0000 | [diff] [blame] | 1441 | so = binop(Iop_And8, e, mkU8(1)); |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 1442 | stmt( IRStmt_Put( OFFB_XER_SO, so ) ); |
cerion | edf7fc5 | 2005-11-18 20:57:41 +0000 | [diff] [blame] | 1443 | } |
| 1444 | |
| 1445 | static void putXER_OV ( IRExpr* e ) |
| 1446 | { |
sewardj | 6332740 | 2006-01-25 03:26:27 +0000 | [diff] [blame] | 1447 | IRExpr* ov; |
cerion | edf7fc5 | 2005-11-18 20:57:41 +0000 | [diff] [blame] | 1448 | vassert(typeOfIRExpr(irbb->tyenv, e) == Ity_I8); |
sewardj | 6332740 | 2006-01-25 03:26:27 +0000 | [diff] [blame] | 1449 | ov = binop(Iop_And8, e, mkU8(1)); |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 1450 | stmt( IRStmt_Put( OFFB_XER_OV, ov ) ); |
cerion | edf7fc5 | 2005-11-18 20:57:41 +0000 | [diff] [blame] | 1451 | } |
| 1452 | |
| 1453 | static void putXER_CA ( IRExpr* e ) |
| 1454 | { |
sewardj | 6332740 | 2006-01-25 03:26:27 +0000 | [diff] [blame] | 1455 | IRExpr* ca; |
cerion | edf7fc5 | 2005-11-18 20:57:41 +0000 | [diff] [blame] | 1456 | vassert(typeOfIRExpr(irbb->tyenv, e) == Ity_I8); |
sewardj | 6332740 | 2006-01-25 03:26:27 +0000 | [diff] [blame] | 1457 | ca = binop(Iop_And8, e, mkU8(1)); |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 1458 | stmt( IRStmt_Put( OFFB_XER_CA, ca ) ); |
cerion | edf7fc5 | 2005-11-18 20:57:41 +0000 | [diff] [blame] | 1459 | } |
| 1460 | |
| 1461 | static void putXER_BC ( IRExpr* e ) |
| 1462 | { |
sewardj | 6332740 | 2006-01-25 03:26:27 +0000 | [diff] [blame] | 1463 | IRExpr* bc; |
cerion | edf7fc5 | 2005-11-18 20:57:41 +0000 | [diff] [blame] | 1464 | vassert(typeOfIRExpr(irbb->tyenv, e) == Ity_I8); |
sewardj | 6332740 | 2006-01-25 03:26:27 +0000 | [diff] [blame] | 1465 | bc = binop(Iop_And8, e, mkU8(0x7F)); |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 1466 | stmt( IRStmt_Put( OFFB_XER_BC, bc ) ); |
cerion | edf7fc5 | 2005-11-18 20:57:41 +0000 | [diff] [blame] | 1467 | } |
| 1468 | |
| 1469 | static IRExpr* /* :: Ity_I8 */ getXER_SO ( void ) |
| 1470 | { |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 1471 | return IRExpr_Get( OFFB_XER_SO, Ity_I8 ); |
cerion | edf7fc5 | 2005-11-18 20:57:41 +0000 | [diff] [blame] | 1472 | } |
| 1473 | |
| 1474 | static IRExpr* /* :: Ity_I32 */ getXER_SO32 ( void ) |
| 1475 | { |
| 1476 | return binop( Iop_And32, unop(Iop_8Uto32, getXER_SO()), mkU32(1) ); |
| 1477 | } |
| 1478 | |
| 1479 | static IRExpr* /* :: Ity_I8 */ getXER_OV ( void ) |
| 1480 | { |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 1481 | return IRExpr_Get( OFFB_XER_OV, Ity_I8 ); |
cerion | edf7fc5 | 2005-11-18 20:57:41 +0000 | [diff] [blame] | 1482 | } |
| 1483 | |
| 1484 | static IRExpr* /* :: Ity_I32 */ getXER_OV32 ( void ) |
| 1485 | { |
| 1486 | return binop( Iop_And32, unop(Iop_8Uto32, getXER_OV()), mkU32(1) ); |
| 1487 | } |
| 1488 | |
| 1489 | static IRExpr* /* :: Ity_I32 */ getXER_CA32 ( void ) |
| 1490 | { |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 1491 | IRExpr* ca = IRExpr_Get( OFFB_XER_CA, Ity_I8 ); |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 1492 | return binop( Iop_And32, unop(Iop_8Uto32, ca ), mkU32(1) ); |
cerion | edf7fc5 | 2005-11-18 20:57:41 +0000 | [diff] [blame] | 1493 | } |
| 1494 | |
| 1495 | static IRExpr* /* :: Ity_I8 */ getXER_BC ( void ) |
| 1496 | { |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 1497 | return IRExpr_Get( OFFB_XER_BC, Ity_I8 ); |
cerion | edf7fc5 | 2005-11-18 20:57:41 +0000 | [diff] [blame] | 1498 | } |
| 1499 | |
| 1500 | static IRExpr* /* :: Ity_I32 */ getXER_BC32 ( void ) |
| 1501 | { |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 1502 | IRExpr* bc = IRExpr_Get( OFFB_XER_BC, Ity_I8 ); |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 1503 | return binop( Iop_And32, unop(Iop_8Uto32, bc), mkU32(0x7F) ); |
cerion | edf7fc5 | 2005-11-18 20:57:41 +0000 | [diff] [blame] | 1504 | } |
| 1505 | |
| 1506 | |
sewardj | 20ef547 | 2005-07-21 14:48:31 +0000 | [diff] [blame] | 1507 | /* RES is the result of doing OP on ARGL and ARGR. Set %XER.OV and |
| 1508 | %XER.SO accordingly. */ |
| 1509 | |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 1510 | static void set_XER_OV_32( UInt op, IRExpr* res, |
| 1511 | IRExpr* argL, IRExpr* argR ) |
sewardj | 20ef547 | 2005-07-21 14:48:31 +0000 | [diff] [blame] | 1512 | { |
| 1513 | IRTemp t64; |
| 1514 | IRExpr* xer_ov; |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 1515 | vassert(op < PPCG_FLAG_OP_NUMBER); |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 1516 | vassert(typeOfIRExpr(irbb->tyenv,res) == Ity_I32); |
sewardj | 20ef547 | 2005-07-21 14:48:31 +0000 | [diff] [blame] | 1517 | vassert(typeOfIRExpr(irbb->tyenv,argL) == Ity_I32); |
| 1518 | vassert(typeOfIRExpr(irbb->tyenv,argR) == Ity_I32); |
| 1519 | |
| 1520 | # define INT32_MIN 0x80000000 |
| 1521 | |
| 1522 | # define XOR2(_aa,_bb) \ |
| 1523 | binop(Iop_Xor32,(_aa),(_bb)) |
| 1524 | |
| 1525 | # define XOR3(_cc,_dd,_ee) \ |
| 1526 | binop(Iop_Xor32,binop(Iop_Xor32,(_cc),(_dd)),(_ee)) |
| 1527 | |
| 1528 | # define AND3(_ff,_gg,_hh) \ |
| 1529 | binop(Iop_And32,binop(Iop_And32,(_ff),(_gg)),(_hh)) |
| 1530 | |
| 1531 | #define NOT(_jj) \ |
| 1532 | unop(Iop_Not32, (_jj)) |
| 1533 | |
| 1534 | switch (op) { |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 1535 | case /* 0 */ PPCG_FLAG_OP_ADD: |
| 1536 | case /* 1 */ PPCG_FLAG_OP_ADDE: |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 1537 | /* (argL^argR^-1) & (argL^res) & (1<<31) ?1:0 */ |
| 1538 | // i.e. ((both_same_sign) & (sign_changed) & (sign_mask)) |
| 1539 | xer_ov |
| 1540 | = AND3( XOR3(argL,argR,mkU32(-1)), |
| 1541 | XOR2(argL,res), |
| 1542 | mkU32(INT32_MIN) ); |
| 1543 | /* xer_ov can only be 0 or 1<<31 */ |
| 1544 | xer_ov |
| 1545 | = binop(Iop_Shr32, xer_ov, mkU8(31) ); |
| 1546 | break; |
| 1547 | |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 1548 | case /* 2 */ PPCG_FLAG_OP_DIVW: |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 1549 | /* (argL == INT32_MIN && argR == -1) || argR == 0 */ |
| 1550 | xer_ov |
| 1551 | = mkOR1( |
| 1552 | mkAND1( |
| 1553 | binop(Iop_CmpEQ32, argL, mkU32(INT32_MIN)), |
| 1554 | binop(Iop_CmpEQ32, argR, mkU32(-1)) |
| 1555 | ), |
| 1556 | binop(Iop_CmpEQ32, argR, mkU32(0) ) |
| 1557 | ); |
| 1558 | xer_ov |
| 1559 | = unop(Iop_1Uto32, xer_ov); |
| 1560 | break; |
| 1561 | |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 1562 | case /* 3 */ PPCG_FLAG_OP_DIVWU: |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 1563 | /* argR == 0 */ |
| 1564 | xer_ov |
| 1565 | = unop(Iop_1Uto32, binop(Iop_CmpEQ32, argR, mkU32(0))); |
| 1566 | break; |
| 1567 | |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 1568 | case /* 4 */ PPCG_FLAG_OP_MULLW: |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 1569 | /* OV true if result can't be represented in 32 bits |
| 1570 | i.e sHi != sign extension of sLo */ |
| 1571 | t64 = newTemp(Ity_I64); |
| 1572 | assign( t64, binop(Iop_MullS32, argL, argR) ); |
| 1573 | xer_ov |
| 1574 | = binop( Iop_CmpNE32, |
| 1575 | unop(Iop_64HIto32, mkexpr(t64)), |
| 1576 | binop( Iop_Sar32, |
| 1577 | unop(Iop_64to32, mkexpr(t64)), |
| 1578 | mkU8(31)) |
| 1579 | ); |
| 1580 | xer_ov |
| 1581 | = unop(Iop_1Uto32, xer_ov); |
| 1582 | break; |
| 1583 | |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 1584 | case /* 5 */ PPCG_FLAG_OP_NEG: |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 1585 | /* argL == INT32_MIN */ |
| 1586 | xer_ov |
| 1587 | = unop( Iop_1Uto32, |
| 1588 | binop(Iop_CmpEQ32, argL, mkU32(INT32_MIN)) ); |
| 1589 | break; |
| 1590 | |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 1591 | case /* 6 */ PPCG_FLAG_OP_SUBF: |
| 1592 | case /* 7 */ PPCG_FLAG_OP_SUBFC: |
| 1593 | case /* 8 */ PPCG_FLAG_OP_SUBFE: |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 1594 | /* ((~argL)^argR^-1) & ((~argL)^res) & (1<<31) ?1:0; */ |
| 1595 | xer_ov |
| 1596 | = AND3( XOR3(NOT(argL),argR,mkU32(-1)), |
| 1597 | XOR2(NOT(argL),res), |
| 1598 | mkU32(INT32_MIN) ); |
| 1599 | /* xer_ov can only be 0 or 1<<31 */ |
| 1600 | xer_ov |
| 1601 | = binop(Iop_Shr32, xer_ov, mkU8(31) ); |
| 1602 | break; |
| 1603 | |
| 1604 | default: |
| 1605 | vex_printf("set_XER_OV: op = %u\n", op); |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 1606 | vpanic("set_XER_OV(ppc)"); |
sewardj | 20ef547 | 2005-07-21 14:48:31 +0000 | [diff] [blame] | 1607 | } |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 1608 | |
sewardj | 20ef547 | 2005-07-21 14:48:31 +0000 | [diff] [blame] | 1609 | /* xer_ov MUST denote either 0 or 1, no other value allowed */ |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 1610 | putXER_OV( unop(Iop_32to8, xer_ov) ); |
sewardj | 20ef547 | 2005-07-21 14:48:31 +0000 | [diff] [blame] | 1611 | |
| 1612 | /* Update the summary overflow */ |
cerion | edf7fc5 | 2005-11-18 20:57:41 +0000 | [diff] [blame] | 1613 | putXER_SO( binop(Iop_Or8, getXER_SO(), getXER_OV()) ); |
sewardj | 20ef547 | 2005-07-21 14:48:31 +0000 | [diff] [blame] | 1614 | |
| 1615 | # undef INT32_MIN |
| 1616 | # undef AND3 |
| 1617 | # undef XOR3 |
| 1618 | # undef XOR2 |
| 1619 | # undef NOT |
| 1620 | } |
| 1621 | |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 1622 | static void set_XER_OV_64( UInt op, IRExpr* res, |
| 1623 | IRExpr* argL, IRExpr* argR ) |
| 1624 | { |
| 1625 | IRExpr* xer_ov; |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 1626 | vassert(op < PPCG_FLAG_OP_NUMBER); |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 1627 | vassert(typeOfIRExpr(irbb->tyenv,res) == Ity_I64); |
| 1628 | vassert(typeOfIRExpr(irbb->tyenv,argL) == Ity_I64); |
| 1629 | vassert(typeOfIRExpr(irbb->tyenv,argR) == Ity_I64); |
| 1630 | |
cerion | 2831b00 | 2005-11-30 19:55:22 +0000 | [diff] [blame] | 1631 | # define INT64_MIN 0x8000000000000000ULL |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 1632 | |
| 1633 | # define XOR2(_aa,_bb) \ |
| 1634 | binop(Iop_Xor64,(_aa),(_bb)) |
| 1635 | |
| 1636 | # define XOR3(_cc,_dd,_ee) \ |
| 1637 | binop(Iop_Xor64,binop(Iop_Xor64,(_cc),(_dd)),(_ee)) |
| 1638 | |
| 1639 | # define AND3(_ff,_gg,_hh) \ |
| 1640 | binop(Iop_And64,binop(Iop_And64,(_ff),(_gg)),(_hh)) |
| 1641 | |
| 1642 | #define NOT(_jj) \ |
| 1643 | unop(Iop_Not64, (_jj)) |
| 1644 | |
| 1645 | switch (op) { |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 1646 | case /* 0 */ PPCG_FLAG_OP_ADD: |
| 1647 | case /* 1 */ PPCG_FLAG_OP_ADDE: |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 1648 | /* (argL^argR^-1) & (argL^res) & (1<<63) ? 1:0 */ |
| 1649 | // i.e. ((both_same_sign) & (sign_changed) & (sign_mask)) |
| 1650 | xer_ov |
| 1651 | = AND3( XOR3(argL,argR,mkU64(-1)), |
| 1652 | XOR2(argL,res), |
| 1653 | mkU64(INT64_MIN) ); |
| 1654 | /* xer_ov can only be 0 or 1<<63 */ |
| 1655 | xer_ov |
| 1656 | = unop(Iop_64to1, binop(Iop_Shr64, xer_ov, mkU8(63))); |
| 1657 | break; |
| 1658 | |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 1659 | case /* 2 */ PPCG_FLAG_OP_DIVW: |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 1660 | /* (argL == INT64_MIN && argR == -1) || argR == 0 */ |
| 1661 | xer_ov |
| 1662 | = mkOR1( |
| 1663 | mkAND1( |
| 1664 | binop(Iop_CmpEQ64, argL, mkU64(INT64_MIN)), |
| 1665 | binop(Iop_CmpEQ64, argR, mkU64(-1)) |
| 1666 | ), |
| 1667 | binop(Iop_CmpEQ64, argR, mkU64(0) ) |
| 1668 | ); |
| 1669 | break; |
| 1670 | |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 1671 | case /* 3 */ PPCG_FLAG_OP_DIVWU: |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 1672 | /* argR == 0 */ |
| 1673 | xer_ov |
| 1674 | = binop(Iop_CmpEQ64, argR, mkU64(0)); |
| 1675 | break; |
| 1676 | |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 1677 | case /* 4 */ PPCG_FLAG_OP_MULLW: { |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 1678 | /* OV true if result can't be represented in 64 bits |
| 1679 | i.e sHi != sign extension of sLo */ |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 1680 | xer_ov |
cerion | bb01b7c | 2005-12-16 13:40:18 +0000 | [diff] [blame] | 1681 | = binop( Iop_CmpNE32, |
| 1682 | unop(Iop_64HIto32, res), |
| 1683 | binop( Iop_Sar32, |
| 1684 | unop(Iop_64to32, res), |
| 1685 | mkU8(31)) |
| 1686 | ); |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 1687 | break; |
| 1688 | } |
| 1689 | |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 1690 | case /* 5 */ PPCG_FLAG_OP_NEG: |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 1691 | /* argL == INT64_MIN */ |
| 1692 | xer_ov |
| 1693 | = binop(Iop_CmpEQ64, argL, mkU64(INT64_MIN)); |
| 1694 | break; |
| 1695 | |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 1696 | case /* 6 */ PPCG_FLAG_OP_SUBF: |
| 1697 | case /* 7 */ PPCG_FLAG_OP_SUBFC: |
| 1698 | case /* 8 */ PPCG_FLAG_OP_SUBFE: |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 1699 | /* ((~argL)^argR^-1) & ((~argL)^res) & (1<<63) ?1:0; */ |
| 1700 | xer_ov |
| 1701 | = AND3( XOR3(NOT(argL),argR,mkU64(-1)), |
| 1702 | XOR2(NOT(argL),res), |
| 1703 | mkU64(INT64_MIN) ); |
| 1704 | /* xer_ov can only be 0 or 1<<63 */ |
| 1705 | xer_ov |
| 1706 | = unop(Iop_64to1, binop(Iop_Shr64, xer_ov, mkU8(63))); |
| 1707 | break; |
| 1708 | |
| 1709 | default: |
| 1710 | vex_printf("set_XER_OV: op = %u\n", op); |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 1711 | vpanic("set_XER_OV(ppc64)"); |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 1712 | } |
| 1713 | |
| 1714 | /* xer_ov MUST denote either 0 or 1, no other value allowed */ |
| 1715 | putXER_OV( unop(Iop_1Uto8, xer_ov) ); |
| 1716 | |
| 1717 | /* Update the summary overflow */ |
| 1718 | putXER_SO( binop(Iop_Or8, getXER_SO(), getXER_OV()) ); |
| 1719 | |
| 1720 | # undef INT64_MIN |
| 1721 | # undef AND3 |
| 1722 | # undef XOR3 |
| 1723 | # undef XOR2 |
| 1724 | # undef NOT |
| 1725 | } |
| 1726 | |
| 1727 | static void set_XER_OV ( IRType ty, UInt op, IRExpr* res, |
| 1728 | IRExpr* argL, IRExpr* argR ) |
| 1729 | { |
| 1730 | if (ty == Ity_I32) |
| 1731 | set_XER_OV_32( op, res, argL, argR ); |
| 1732 | else |
| 1733 | set_XER_OV_64( op, res, argL, argR ); |
| 1734 | } |
| 1735 | |
| 1736 | |
| 1737 | |
sewardj | b51f0f4 | 2005-07-18 11:38:02 +0000 | [diff] [blame] | 1738 | /* RES is the result of doing OP on ARGL and ARGR with the old %XER.CA |
| 1739 | value being OLDCA. Set %XER.CA accordingly. */ |
cerion | e9d361a | 2005-03-04 17:35:29 +0000 | [diff] [blame] | 1740 | |
cerion | 2831b00 | 2005-11-30 19:55:22 +0000 | [diff] [blame] | 1741 | static void set_XER_CA_32 ( UInt op, IRExpr* res, |
| 1742 | IRExpr* argL, IRExpr* argR, IRExpr* oldca ) |
cerion | 3867460 | 2005-02-08 02:19:25 +0000 | [diff] [blame] | 1743 | { |
sewardj | 9a036bf | 2005-03-14 18:19:08 +0000 | [diff] [blame] | 1744 | IRExpr* xer_ca; |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 1745 | vassert(op < PPCG_FLAG_OP_NUMBER); |
sewardj | b51f0f4 | 2005-07-18 11:38:02 +0000 | [diff] [blame] | 1746 | vassert(typeOfIRExpr(irbb->tyenv,res) == Ity_I32); |
| 1747 | vassert(typeOfIRExpr(irbb->tyenv,argL) == Ity_I32); |
| 1748 | vassert(typeOfIRExpr(irbb->tyenv,argR) == Ity_I32); |
| 1749 | vassert(typeOfIRExpr(irbb->tyenv,oldca) == Ity_I32); |
cerion | 70e2412 | 2005-03-16 00:27:37 +0000 | [diff] [blame] | 1750 | |
sewardj | 20ef547 | 2005-07-21 14:48:31 +0000 | [diff] [blame] | 1751 | /* Incoming oldca is assumed to hold the values 0 or 1 only. This |
| 1752 | seems reasonable given that it's always generated by |
cerion | edf7fc5 | 2005-11-18 20:57:41 +0000 | [diff] [blame] | 1753 | getXER_CA32(), which masks it accordingly. In any case it being |
cerion | 7594920 | 2005-12-24 13:14:11 +0000 | [diff] [blame] | 1754 | 0 or 1 is an invariant of the ppc guest state representation; |
sewardj | 20ef547 | 2005-07-21 14:48:31 +0000 | [diff] [blame] | 1755 | if it has any other value, that invariant has been violated. */ |
cerion | e9d361a | 2005-03-04 17:35:29 +0000 | [diff] [blame] | 1756 | |
sewardj | 20ef547 | 2005-07-21 14:48:31 +0000 | [diff] [blame] | 1757 | switch (op) { |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 1758 | case /* 0 */ PPCG_FLAG_OP_ADD: |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 1759 | /* res <u argL */ |
| 1760 | xer_ca |
| 1761 | = unop(Iop_1Uto32, binop(Iop_CmpLT32U, res, argL)); |
| 1762 | break; |
| 1763 | |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 1764 | case /* 1 */ PPCG_FLAG_OP_ADDE: |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 1765 | /* res <u argL || (old_ca==1 && res==argL) */ |
| 1766 | xer_ca |
| 1767 | = mkOR1( |
| 1768 | binop(Iop_CmpLT32U, res, argL), |
| 1769 | mkAND1( |
| 1770 | binop(Iop_CmpEQ32, oldca, mkU32(1)), |
| 1771 | binop(Iop_CmpEQ32, res, argL) |
| 1772 | ) |
| 1773 | ); |
| 1774 | xer_ca |
| 1775 | = unop(Iop_1Uto32, xer_ca); |
| 1776 | break; |
| 1777 | |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 1778 | case /* 8 */ PPCG_FLAG_OP_SUBFE: |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 1779 | /* res <u argR || (old_ca==1 && res==argR) */ |
| 1780 | xer_ca |
| 1781 | = mkOR1( |
| 1782 | binop(Iop_CmpLT32U, res, argR), |
| 1783 | mkAND1( |
| 1784 | binop(Iop_CmpEQ32, oldca, mkU32(1)), |
| 1785 | binop(Iop_CmpEQ32, res, argR) |
| 1786 | ) |
| 1787 | ); |
| 1788 | xer_ca |
| 1789 | = unop(Iop_1Uto32, xer_ca); |
| 1790 | break; |
| 1791 | |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 1792 | case /* 7 */ PPCG_FLAG_OP_SUBFC: |
| 1793 | case /* 9 */ PPCG_FLAG_OP_SUBFI: |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 1794 | /* res <=u argR */ |
| 1795 | xer_ca |
| 1796 | = unop(Iop_1Uto32, binop(Iop_CmpLE32U, res, argR)); |
| 1797 | break; |
| 1798 | |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 1799 | case /* 10 */ PPCG_FLAG_OP_SRAW: |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 1800 | /* The shift amount is guaranteed to be in 0 .. 63 inclusive. |
| 1801 | If it is <= 31, behave like SRAWI; else XER.CA is the sign |
| 1802 | bit of argL. */ |
| 1803 | /* This term valid for shift amount < 32 only */ |
| 1804 | xer_ca |
| 1805 | = binop( |
| 1806 | Iop_And32, |
| 1807 | binop(Iop_Sar32, argL, mkU8(31)), |
| 1808 | binop( Iop_And32, |
| 1809 | argL, |
| 1810 | binop( Iop_Sub32, |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 1811 | binop(Iop_Shl32, mkU32(1), |
| 1812 | unop(Iop_32to8,argR)), |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 1813 | mkU32(1) ) |
| 1814 | ) |
sewardj | 20ef547 | 2005-07-21 14:48:31 +0000 | [diff] [blame] | 1815 | ); |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 1816 | xer_ca |
| 1817 | = IRExpr_Mux0X( |
| 1818 | /* shift amt > 31 ? */ |
| 1819 | unop(Iop_1Uto8, binop(Iop_CmpLT32U, mkU32(31), argR)), |
| 1820 | /* no -- be like srawi */ |
| 1821 | unop(Iop_1Uto32, binop(Iop_CmpNE32, xer_ca, mkU32(0))), |
| 1822 | /* yes -- get sign bit of argL */ |
| 1823 | binop(Iop_Shr32, argL, mkU8(31)) |
| 1824 | ); |
| 1825 | break; |
sewardj | 20ef547 | 2005-07-21 14:48:31 +0000 | [diff] [blame] | 1826 | |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 1827 | case /* 11 */ PPCG_FLAG_OP_SRAWI: |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 1828 | /* xer_ca is 1 iff src was negative and bits_shifted_out != |
| 1829 | 0. Since the shift amount is known to be in the range |
| 1830 | 0 .. 31 inclusive the following seems viable: |
| 1831 | xer.ca == 1 iff the following is nonzero: |
| 1832 | (argL >>s 31) -- either all 0s or all 1s |
| 1833 | & (argL & (1<<argR)-1) -- the stuff shifted out */ |
| 1834 | xer_ca |
| 1835 | = binop( |
| 1836 | Iop_And32, |
| 1837 | binop(Iop_Sar32, argL, mkU8(31)), |
| 1838 | binop( Iop_And32, |
| 1839 | argL, |
| 1840 | binop( Iop_Sub32, |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 1841 | binop(Iop_Shl32, mkU32(1), |
| 1842 | unop(Iop_32to8,argR)), |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 1843 | mkU32(1) ) |
| 1844 | ) |
sewardj | 20ef547 | 2005-07-21 14:48:31 +0000 | [diff] [blame] | 1845 | ); |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 1846 | xer_ca |
| 1847 | = unop(Iop_1Uto32, binop(Iop_CmpNE32, xer_ca, mkU32(0))); |
| 1848 | break; |
| 1849 | |
| 1850 | default: |
| 1851 | vex_printf("set_XER_CA: op = %u\n", op); |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 1852 | vpanic("set_XER_CA(ppc)"); |
sewardj | 20ef547 | 2005-07-21 14:48:31 +0000 | [diff] [blame] | 1853 | } |
| 1854 | |
| 1855 | /* xer_ca MUST denote either 0 or 1, no other value allowed */ |
cerion | edf7fc5 | 2005-11-18 20:57:41 +0000 | [diff] [blame] | 1856 | putXER_CA( unop(Iop_32to8, xer_ca) ); |
sewardj | b51f0f4 | 2005-07-18 11:38:02 +0000 | [diff] [blame] | 1857 | } |
| 1858 | |
cerion | 2831b00 | 2005-11-30 19:55:22 +0000 | [diff] [blame] | 1859 | static void set_XER_CA_64 ( UInt op, IRExpr* res, |
| 1860 | IRExpr* argL, IRExpr* argR, IRExpr* oldca ) |
sewardj | e14bb9f | 2005-07-22 09:39:02 +0000 | [diff] [blame] | 1861 | { |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 1862 | IRExpr* xer_ca; |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 1863 | vassert(op < PPCG_FLAG_OP_NUMBER); |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 1864 | vassert(typeOfIRExpr(irbb->tyenv,res) == Ity_I64); |
| 1865 | vassert(typeOfIRExpr(irbb->tyenv,argL) == Ity_I64); |
| 1866 | vassert(typeOfIRExpr(irbb->tyenv,argR) == Ity_I64); |
| 1867 | vassert(typeOfIRExpr(irbb->tyenv,oldca) == Ity_I64); |
sewardj | e14bb9f | 2005-07-22 09:39:02 +0000 | [diff] [blame] | 1868 | |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 1869 | /* Incoming oldca is assumed to hold the values 0 or 1 only. This |
| 1870 | seems reasonable given that it's always generated by |
| 1871 | getXER_CA32(), which masks it accordingly. In any case it being |
cerion | 7594920 | 2005-12-24 13:14:11 +0000 | [diff] [blame] | 1872 | 0 or 1 is an invariant of the ppc guest state representation; |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 1873 | if it has any other value, that invariant has been violated. */ |
| 1874 | |
| 1875 | switch (op) { |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 1876 | case /* 0 */ PPCG_FLAG_OP_ADD: |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 1877 | /* res <u argL */ |
| 1878 | xer_ca |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 1879 | = unop(Iop_1Uto32, binop(Iop_CmpLT64U, res, argL)); |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 1880 | break; |
sewardj | e14bb9f | 2005-07-22 09:39:02 +0000 | [diff] [blame] | 1881 | |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 1882 | case /* 1 */ PPCG_FLAG_OP_ADDE: |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 1883 | /* res <u argL || (old_ca==1 && res==argL) */ |
| 1884 | xer_ca |
| 1885 | = mkOR1( |
| 1886 | binop(Iop_CmpLT64U, res, argL), |
| 1887 | mkAND1( |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 1888 | binop(Iop_CmpEQ64, oldca, mkU64(1)), |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 1889 | binop(Iop_CmpEQ64, res, argL) |
| 1890 | ) |
| 1891 | ); |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 1892 | xer_ca |
| 1893 | = unop(Iop_1Uto32, xer_ca); |
cerion | edf7fc5 | 2005-11-18 20:57:41 +0000 | [diff] [blame] | 1894 | break; |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 1895 | |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 1896 | case /* 8 */ PPCG_FLAG_OP_SUBFE: |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 1897 | /* res <u argR || (old_ca==1 && res==argR) */ |
| 1898 | xer_ca |
| 1899 | = mkOR1( |
| 1900 | binop(Iop_CmpLT64U, res, argR), |
| 1901 | mkAND1( |
| 1902 | binop(Iop_CmpEQ64, oldca, mkU64(1)), |
| 1903 | binop(Iop_CmpEQ64, res, argR) |
| 1904 | ) |
| 1905 | ); |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 1906 | xer_ca |
| 1907 | = unop(Iop_1Uto32, xer_ca); |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 1908 | break; |
| 1909 | |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 1910 | case /* 7 */ PPCG_FLAG_OP_SUBFC: |
| 1911 | case /* 9 */ PPCG_FLAG_OP_SUBFI: |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 1912 | /* res <=u argR */ |
| 1913 | xer_ca |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 1914 | = unop(Iop_1Uto32, binop(Iop_CmpLE64U, res, argR)); |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 1915 | break; |
| 1916 | |
| 1917 | |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 1918 | case /* 10 */ PPCG_FLAG_OP_SRAW: |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 1919 | /* The shift amount is guaranteed to be in 0 .. 31 inclusive. |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 1920 | If it is <= 31, behave like SRAWI; else XER.CA is the sign |
| 1921 | bit of argL. */ |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 1922 | /* This term valid for shift amount < 31 only */ |
| 1923 | |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 1924 | xer_ca |
| 1925 | = binop( |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 1926 | Iop_And64, |
| 1927 | binop(Iop_Sar64, argL, mkU8(31)), |
| 1928 | binop( Iop_And64, |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 1929 | argL, |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 1930 | binop( Iop_Sub64, |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 1931 | binop(Iop_Shl64, mkU64(1), |
| 1932 | unop(Iop_64to8,argR)), |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 1933 | mkU64(1) ) |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 1934 | ) |
| 1935 | ); |
| 1936 | xer_ca |
| 1937 | = IRExpr_Mux0X( |
| 1938 | /* shift amt > 31 ? */ |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 1939 | unop(Iop_1Uto8, binop(Iop_CmpLT64U, mkU64(31), argR)), |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 1940 | /* no -- be like srawi */ |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 1941 | unop(Iop_1Uto32, binop(Iop_CmpNE64, xer_ca, mkU64(0))), |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 1942 | /* yes -- get sign bit of argL */ |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 1943 | unop(Iop_64to32, binop(Iop_Shr64, argL, mkU8(63))) |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 1944 | ); |
| 1945 | break; |
| 1946 | |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 1947 | case /* 11 */ PPCG_FLAG_OP_SRAWI: |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 1948 | /* xer_ca is 1 iff src was negative and bits_shifted_out != 0. |
| 1949 | Since the shift amount is known to be in the range 0 .. 31 |
| 1950 | inclusive the following seems viable: |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 1951 | xer.ca == 1 iff the following is nonzero: |
| 1952 | (argL >>s 31) -- either all 0s or all 1s |
| 1953 | & (argL & (1<<argR)-1) -- the stuff shifted out */ |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 1954 | |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 1955 | xer_ca |
| 1956 | = binop( |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 1957 | Iop_And64, |
| 1958 | binop(Iop_Sar64, argL, mkU8(31)), |
| 1959 | binop( Iop_And64, |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 1960 | argL, |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 1961 | binop( Iop_Sub64, |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 1962 | binop(Iop_Shl64, mkU64(1), |
| 1963 | unop(Iop_64to8,argR)), |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 1964 | mkU64(1) ) |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 1965 | ) |
| 1966 | ); |
| 1967 | xer_ca |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 1968 | = unop(Iop_1Uto32, binop(Iop_CmpNE64, xer_ca, mkU64(0))); |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 1969 | break; |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 1970 | |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 1971 | |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 1972 | case /* 12 */ PPCG_FLAG_OP_SRAD: |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 1973 | /* The shift amount is guaranteed to be in 0 .. 63 inclusive. |
| 1974 | If it is <= 63, behave like SRADI; else XER.CA is the sign |
| 1975 | bit of argL. */ |
| 1976 | /* This term valid for shift amount < 63 only */ |
| 1977 | |
| 1978 | xer_ca |
| 1979 | = binop( |
| 1980 | Iop_And64, |
| 1981 | binop(Iop_Sar64, argL, mkU8(63)), |
| 1982 | binop( Iop_And64, |
| 1983 | argL, |
| 1984 | binop( Iop_Sub64, |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 1985 | binop(Iop_Shl64, mkU64(1), |
| 1986 | unop(Iop_64to8,argR)), |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 1987 | mkU64(1) ) |
| 1988 | ) |
| 1989 | ); |
| 1990 | xer_ca |
| 1991 | = IRExpr_Mux0X( |
| 1992 | /* shift amt > 63 ? */ |
| 1993 | unop(Iop_1Uto8, binop(Iop_CmpLT64U, mkU64(63), argR)), |
cerion | 07b07a9 | 2005-12-22 14:32:35 +0000 | [diff] [blame] | 1994 | /* no -- be like sradi */ |
| 1995 | unop(Iop_1Uto32, binop(Iop_CmpNE64, xer_ca, mkU64(0))), |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 1996 | /* yes -- get sign bit of argL */ |
| 1997 | unop(Iop_64to32, binop(Iop_Shr64, argL, mkU8(63))) |
| 1998 | ); |
| 1999 | break; |
| 2000 | |
| 2001 | |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 2002 | case /* 13 */ PPCG_FLAG_OP_SRADI: |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 2003 | /* xer_ca is 1 iff src was negative and bits_shifted_out != 0. |
| 2004 | Since the shift amount is known to be in the range 0 .. 63 |
| 2005 | inclusive, the following seems viable: |
| 2006 | xer.ca == 1 iff the following is nonzero: |
| 2007 | (argL >>s 63) -- either all 0s or all 1s |
| 2008 | & (argL & (1<<argR)-1) -- the stuff shifted out */ |
| 2009 | |
| 2010 | xer_ca |
| 2011 | = binop( |
| 2012 | Iop_And64, |
| 2013 | binop(Iop_Sar64, argL, mkU8(63)), |
| 2014 | binop( Iop_And64, |
| 2015 | argL, |
| 2016 | binop( Iop_Sub64, |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 2017 | binop(Iop_Shl64, mkU64(1), |
| 2018 | unop(Iop_64to8,argR)), |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 2019 | mkU64(1) ) |
| 2020 | ) |
| 2021 | ); |
| 2022 | xer_ca |
| 2023 | = unop(Iop_1Uto32, binop(Iop_CmpNE64, xer_ca, mkU64(0))); |
| 2024 | break; |
| 2025 | |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 2026 | default: |
| 2027 | vex_printf("set_XER_CA: op = %u\n", op); |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 2028 | vpanic("set_XER_CA(ppc64)"); |
sewardj | e14bb9f | 2005-07-22 09:39:02 +0000 | [diff] [blame] | 2029 | } |
| 2030 | |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 2031 | /* xer_ca MUST denote either 0 or 1, no other value allowed */ |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 2032 | putXER_CA( unop(Iop_32to8, xer_ca) ); |
sewardj | e14bb9f | 2005-07-22 09:39:02 +0000 | [diff] [blame] | 2033 | } |
| 2034 | |
cerion | 2831b00 | 2005-11-30 19:55:22 +0000 | [diff] [blame] | 2035 | static void set_XER_CA ( IRType ty, UInt op, IRExpr* res, |
| 2036 | IRExpr* argL, IRExpr* argR, IRExpr* oldca ) |
cerion | edf7fc5 | 2005-11-18 20:57:41 +0000 | [diff] [blame] | 2037 | { |
cerion | 2831b00 | 2005-11-30 19:55:22 +0000 | [diff] [blame] | 2038 | if (ty == Ity_I32) |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 2039 | set_XER_CA_32( op, res, argL, argR, oldca ); |
| 2040 | else |
| 2041 | set_XER_CA_64( op, res, argL, argR, oldca ); |
cerion | edf7fc5 | 2005-11-18 20:57:41 +0000 | [diff] [blame] | 2042 | } |
| 2043 | |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 2044 | |
| 2045 | |
| 2046 | /*------------------------------------------------------------*/ |
| 2047 | /*--- Read/write to guest-state --- */ |
| 2048 | /*------------------------------------------------------------*/ |
| 2049 | |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 2050 | static IRExpr* /* :: Ity_I32/64 */ getGST ( PPC_GST reg ) |
cerion | edf7fc5 | 2005-11-18 20:57:41 +0000 | [diff] [blame] | 2051 | { |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 2052 | IRType ty = mode64 ? Ity_I64 : Ity_I32; |
cerion | edf7fc5 | 2005-11-18 20:57:41 +0000 | [diff] [blame] | 2053 | switch (reg) { |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 2054 | case PPC_GST_LR: |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 2055 | return IRExpr_Get( OFFB_LR, ty ); |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 2056 | |
| 2057 | case PPC_GST_CTR: |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 2058 | return IRExpr_Get( OFFB_CTR, ty ); |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 2059 | |
| 2060 | case PPC_GST_VRSAVE: |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 2061 | return IRExpr_Get( OFFB_VRSAVE, Ity_I32 ); |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 2062 | |
| 2063 | case PPC_GST_VSCR: |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 2064 | return binop(Iop_And32, IRExpr_Get( OFFB_VSCR,Ity_I32 ), |
| 2065 | mkU32(MASK_VSCR_VALID)); |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 2066 | |
| 2067 | case PPC_GST_CR: { |
cerion | edf7fc5 | 2005-11-18 20:57:41 +0000 | [diff] [blame] | 2068 | /* Synthesise the entire CR into a single word. Expensive. */ |
| 2069 | # define FIELD(_n) \ |
| 2070 | binop(Iop_Shl32, \ |
| 2071 | unop(Iop_8Uto32, \ |
| 2072 | binop(Iop_Or8, \ |
| 2073 | binop(Iop_And8, getCR321(_n), mkU8(7<<1)), \ |
| 2074 | binop(Iop_And8, getCR0(_n), mkU8(1)) \ |
| 2075 | ) \ |
| 2076 | ), \ |
| 2077 | mkU8(4 * (7-(_n))) \ |
| 2078 | ) |
| 2079 | return binop(Iop_Or32, |
| 2080 | binop(Iop_Or32, |
| 2081 | binop(Iop_Or32, FIELD(0), FIELD(1)), |
| 2082 | binop(Iop_Or32, FIELD(2), FIELD(3)) |
| 2083 | ), |
| 2084 | binop(Iop_Or32, |
| 2085 | binop(Iop_Or32, FIELD(4), FIELD(5)), |
| 2086 | binop(Iop_Or32, FIELD(6), FIELD(7)) |
| 2087 | ) |
| 2088 | ); |
| 2089 | # undef FIELD |
| 2090 | } |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 2091 | |
| 2092 | case PPC_GST_XER: |
cerion | edf7fc5 | 2005-11-18 20:57:41 +0000 | [diff] [blame] | 2093 | return binop(Iop_Or32, |
| 2094 | binop(Iop_Or32, |
| 2095 | binop( Iop_Shl32, getXER_SO32(), mkU8(31)), |
| 2096 | binop( Iop_Shl32, getXER_OV32(), mkU8(30))), |
| 2097 | binop(Iop_Or32, |
| 2098 | binop( Iop_Shl32, getXER_CA32(), mkU8(29)), |
| 2099 | getXER_BC32())); |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 2100 | |
| 2101 | case PPC_GST_RESVN: |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 2102 | return IRExpr_Get( OFFB_RESVN, ty); |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 2103 | |
cerion | edf7fc5 | 2005-11-18 20:57:41 +0000 | [diff] [blame] | 2104 | default: |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 2105 | vex_printf("getGST(ppc): reg = %u", reg); |
| 2106 | vpanic("getGST(ppc)"); |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 2107 | } |
| 2108 | } |
| 2109 | |
| 2110 | /* Get a masked word from the given reg */ |
| 2111 | static IRExpr* /* ::Ity_I32 */ getGST_masked ( PPC_GST reg, UInt mask ) |
| 2112 | { |
| 2113 | IRTemp val = newTemp(Ity_I32); |
| 2114 | vassert( reg < PPC_GST_MAX ); |
| 2115 | |
| 2116 | switch (reg) { |
| 2117 | |
| 2118 | case PPC_GST_FPSCR: { |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 2119 | /* Vex-generated code expects the FPSCR to be set as follows: |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 2120 | all exceptions masked, round-to-nearest. |
| 2121 | This corresponds to a FPSCR value of 0x0. */ |
| 2122 | |
| 2123 | /* We're only keeping track of the rounding mode, |
| 2124 | so if the mask isn't asking for this, just return 0x0 */ |
| 2125 | if (mask & 0x3) { |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 2126 | assign( val, IRExpr_Get( OFFB_FPROUND, Ity_I32 ) ); |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 2127 | } else { |
| 2128 | assign( val, mkU32(0x0) ); |
| 2129 | } |
| 2130 | break; |
| 2131 | } |
| 2132 | |
| 2133 | default: |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 2134 | vex_printf("getGST_masked(ppc): reg = %u", reg); |
| 2135 | vpanic("getGST_masked(ppc)"); |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 2136 | } |
| 2137 | |
| 2138 | if (mask != 0xFFFFFFFF) { |
| 2139 | return binop(Iop_And32, mkexpr(val), mkU32(mask)); |
| 2140 | } else { |
| 2141 | return mkexpr(val); |
| 2142 | } |
| 2143 | } |
| 2144 | |
| 2145 | /* Fetch the specified REG[FLD] nibble (as per IBM/hardware notation) |
| 2146 | and return it at the bottom of an I32; the top 27 bits are |
| 2147 | guaranteed to be zero. */ |
| 2148 | static IRExpr* /* ::Ity_I32 */ getGST_field ( PPC_GST reg, UInt fld ) |
| 2149 | { |
| 2150 | UInt shft, mask; |
| 2151 | |
| 2152 | vassert( fld < 8 ); |
| 2153 | vassert( reg < PPC_GST_MAX ); |
| 2154 | |
| 2155 | shft = 4*(7-fld); |
| 2156 | mask = 0xF<<shft; |
| 2157 | |
| 2158 | switch (reg) { |
| 2159 | case PPC_GST_XER: |
| 2160 | vassert(fld ==7); |
| 2161 | return binop(Iop_Or32, |
| 2162 | binop(Iop_Or32, |
| 2163 | binop(Iop_Shl32, getXER_SO32(), mkU8(3)), |
| 2164 | binop(Iop_Shl32, getXER_OV32(), mkU8(2))), |
| 2165 | binop( Iop_Shl32, getXER_CA32(), mkU8(1))); |
| 2166 | break; |
| 2167 | |
| 2168 | default: |
| 2169 | if (shft == 0) |
| 2170 | return getGST_masked( reg, mask ); |
| 2171 | else |
| 2172 | return binop(Iop_Shr32, |
| 2173 | getGST_masked( reg, mask ), |
| 2174 | mkU8(toUChar( shft ))); |
| 2175 | } |
| 2176 | } |
| 2177 | |
| 2178 | static void putGST ( PPC_GST reg, IRExpr* src ) |
| 2179 | { |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 2180 | IRType ty = mode64 ? Ity_I64 : Ity_I32; |
| 2181 | IRType ty_src = typeOfIRExpr(irbb->tyenv,src ); |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 2182 | vassert( reg < PPC_GST_MAX ); |
| 2183 | switch (reg) { |
| 2184 | case PPC_GST_CIA: |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 2185 | vassert( ty_src == ty ); |
| 2186 | stmt( IRStmt_Put( OFFB_CIA, src ) ); |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 2187 | break; |
| 2188 | case PPC_GST_LR: |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 2189 | vassert( ty_src == ty ); |
| 2190 | stmt( IRStmt_Put( OFFB_LR, src ) ); |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 2191 | break; |
| 2192 | case PPC_GST_CTR: |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 2193 | vassert( ty_src == ty ); |
| 2194 | stmt( IRStmt_Put( OFFB_CTR, src ) ); |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 2195 | break; |
| 2196 | case PPC_GST_VRSAVE: |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 2197 | vassert( ty_src == Ity_I32 ); |
| 2198 | stmt( IRStmt_Put( OFFB_VRSAVE,src)); |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 2199 | break; |
| 2200 | case PPC_GST_VSCR: |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 2201 | vassert( ty_src == Ity_I32 ); |
| 2202 | stmt( IRStmt_Put( OFFB_VSCR, |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 2203 | binop(Iop_And32, src, |
| 2204 | mkU32(MASK_VSCR_VALID)) ) ); |
| 2205 | break; |
| 2206 | case PPC_GST_XER: |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 2207 | vassert( ty_src == Ity_I32 ); |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 2208 | putXER_SO( unop(Iop_32to8, binop(Iop_Shr32, src, mkU8(31))) ); |
| 2209 | putXER_OV( unop(Iop_32to8, binop(Iop_Shr32, src, mkU8(30))) ); |
| 2210 | putXER_CA( unop(Iop_32to8, binop(Iop_Shr32, src, mkU8(29))) ); |
| 2211 | putXER_BC( unop(Iop_32to8, src) ); |
| 2212 | break; |
| 2213 | |
| 2214 | case PPC_GST_EMWARN: |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 2215 | vassert( ty_src == Ity_I32 ); |
| 2216 | stmt( IRStmt_Put( OFFB_EMWARN,src) ); |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 2217 | break; |
| 2218 | |
| 2219 | case PPC_GST_TISTART: |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 2220 | vassert( ty_src == ty ); |
| 2221 | stmt( IRStmt_Put( OFFB_TISTART, src) ); |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 2222 | break; |
| 2223 | |
| 2224 | case PPC_GST_TILEN: |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 2225 | vassert( ty_src == ty ); |
| 2226 | stmt( IRStmt_Put( OFFB_TILEN, src) ); |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 2227 | break; |
| 2228 | |
| 2229 | case PPC_GST_RESVN: |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 2230 | vassert( ty_src == ty ); |
| 2231 | stmt( IRStmt_Put( OFFB_RESVN, src) ); |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 2232 | break; |
| 2233 | |
| 2234 | default: |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 2235 | vex_printf("putGST(ppc): reg = %u", reg); |
| 2236 | vpanic("putGST(ppc)"); |
cerion | edf7fc5 | 2005-11-18 20:57:41 +0000 | [diff] [blame] | 2237 | } |
| 2238 | } |
sewardj | e14bb9f | 2005-07-22 09:39:02 +0000 | [diff] [blame] | 2239 | |
| 2240 | /* Write masked src to the given reg */ |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 2241 | static void putGST_masked ( PPC_GST reg, IRExpr* src, UInt mask ) |
sewardj | e14bb9f | 2005-07-22 09:39:02 +0000 | [diff] [blame] | 2242 | { |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 2243 | IRType ty = mode64 ? Ity_I64 : Ity_I32; |
| 2244 | vassert( reg < PPC_GST_MAX ); |
sewardj | e14bb9f | 2005-07-22 09:39:02 +0000 | [diff] [blame] | 2245 | vassert( typeOfIRExpr(irbb->tyenv,src ) == Ity_I32 ); |
| 2246 | |
| 2247 | switch (reg) { |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 2248 | case PPC_GST_FPSCR: { |
sewardj | e14bb9f | 2005-07-22 09:39:02 +0000 | [diff] [blame] | 2249 | /* Allow writes to Rounding Mode */ |
| 2250 | if (mask & 0x3) { |
sewardj | b183b85 | 2006-02-03 16:08:03 +0000 | [diff] [blame] | 2251 | /* construct new fpround from new and old values as per mask: |
| 2252 | new fpround = (src & (3 & mask)) | (fpround & (3 & ~mask)) */ |
| 2253 | stmt( |
| 2254 | IRStmt_Put( |
| 2255 | OFFB_FPROUND, |
| 2256 | binop( |
| 2257 | Iop_Or32, |
| 2258 | binop(Iop_And32, src, mkU32(3 & mask)), |
| 2259 | binop( |
| 2260 | Iop_And32, |
| 2261 | IRExpr_Get(OFFB_FPROUND,Ity_I32), |
| 2262 | mkU32(3 & ~mask) |
| 2263 | ) |
| 2264 | ) |
| 2265 | ) |
| 2266 | ); |
sewardj | e14bb9f | 2005-07-22 09:39:02 +0000 | [diff] [blame] | 2267 | } |
| 2268 | |
cerion | edf7fc5 | 2005-11-18 20:57:41 +0000 | [diff] [blame] | 2269 | /* Give EmWarn for attempted writes to: |
sewardj | e14bb9f | 2005-07-22 09:39:02 +0000 | [diff] [blame] | 2270 | - Exception Controls |
| 2271 | - Non-IEEE Mode |
| 2272 | */ |
| 2273 | if (mask & 0xFC) { // Exception Control, Non-IEE mode |
sewardj | 5ff11dd | 2006-01-20 14:19:25 +0000 | [diff] [blame] | 2274 | VexEmWarn ew = EmWarn_PPCexns; |
sewardj | e14bb9f | 2005-07-22 09:39:02 +0000 | [diff] [blame] | 2275 | |
| 2276 | /* If any of the src::exception_control bits are actually set, |
| 2277 | side-exit to the next insn, reporting the warning, |
| 2278 | so that Valgrind's dispatcher sees the warning. */ |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 2279 | putGST( PPC_GST_EMWARN, mkU32(ew) ); |
sewardj | e14bb9f | 2005-07-22 09:39:02 +0000 | [diff] [blame] | 2280 | stmt( |
| 2281 | IRStmt_Exit( |
| 2282 | binop(Iop_CmpNE32, mkU32(ew), mkU32(EmWarn_NONE)), |
| 2283 | Ijk_EmWarn, |
cerion | 2831b00 | 2005-11-30 19:55:22 +0000 | [diff] [blame] | 2284 | mkSzConst( ty, nextInsnAddr()) )); |
sewardj | e14bb9f | 2005-07-22 09:39:02 +0000 | [diff] [blame] | 2285 | } |
| 2286 | |
cerion | edf7fc5 | 2005-11-18 20:57:41 +0000 | [diff] [blame] | 2287 | /* Ignore all other writes */ |
sewardj | e14bb9f | 2005-07-22 09:39:02 +0000 | [diff] [blame] | 2288 | break; |
cerion | edf7fc5 | 2005-11-18 20:57:41 +0000 | [diff] [blame] | 2289 | } |
sewardj | e14bb9f | 2005-07-22 09:39:02 +0000 | [diff] [blame] | 2290 | |
| 2291 | default: |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 2292 | vex_printf("putGST_masked(ppc): reg = %u", reg); |
| 2293 | vpanic("putGST_masked(ppc)"); |
sewardj | e14bb9f | 2005-07-22 09:39:02 +0000 | [diff] [blame] | 2294 | } |
| 2295 | } |
| 2296 | |
cerion | edf7fc5 | 2005-11-18 20:57:41 +0000 | [diff] [blame] | 2297 | /* Write the least significant nibble of src to the specified |
| 2298 | REG[FLD] (as per IBM/hardware notation). */ |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 2299 | static void putGST_field ( PPC_GST reg, IRExpr* src, UInt fld ) |
cerion | edf7fc5 | 2005-11-18 20:57:41 +0000 | [diff] [blame] | 2300 | { |
sewardj | 41a7b70 | 2005-11-18 22:18:23 +0000 | [diff] [blame] | 2301 | UInt shft, mask; |
| 2302 | |
cerion | edf7fc5 | 2005-11-18 20:57:41 +0000 | [diff] [blame] | 2303 | vassert( typeOfIRExpr(irbb->tyenv,src ) == Ity_I32 ); |
| 2304 | vassert( fld < 8 ); |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 2305 | vassert( reg < PPC_GST_MAX ); |
cerion | edf7fc5 | 2005-11-18 20:57:41 +0000 | [diff] [blame] | 2306 | |
sewardj | 41a7b70 | 2005-11-18 22:18:23 +0000 | [diff] [blame] | 2307 | shft = 4*(7-fld); |
| 2308 | mask = 0xF<<shft; |
cerion | edf7fc5 | 2005-11-18 20:57:41 +0000 | [diff] [blame] | 2309 | |
| 2310 | switch (reg) { |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 2311 | case PPC_GST_CR: |
cerion | edf7fc5 | 2005-11-18 20:57:41 +0000 | [diff] [blame] | 2312 | putCR0 (fld, binop(Iop_And8, mkU8(1 ), unop(Iop_32to8, src))); |
| 2313 | putCR321(fld, binop(Iop_And8, mkU8(7<<1), unop(Iop_32to8, src))); |
| 2314 | break; |
| 2315 | |
| 2316 | default: |
| 2317 | if (shft == 0) { |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 2318 | putGST_masked( reg, src, mask ); |
cerion | edf7fc5 | 2005-11-18 20:57:41 +0000 | [diff] [blame] | 2319 | } else { |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 2320 | putGST_masked( reg, |
cerion | edf7fc5 | 2005-11-18 20:57:41 +0000 | [diff] [blame] | 2321 | binop(Iop_Shl32, src, mkU8(toUChar(shft))), |
| 2322 | mask ); |
| 2323 | } |
| 2324 | } |
| 2325 | } |
cerion | 62bec57 | 2005-02-01 21:29:39 +0000 | [diff] [blame] | 2326 | |
cerion | 7622226 | 2005-02-05 13:45:57 +0000 | [diff] [blame] | 2327 | |
| 2328 | |
cerion | e9d361a | 2005-03-04 17:35:29 +0000 | [diff] [blame] | 2329 | /*------------------------------------------------------------*/ |
cerion | 3d870a3 | 2005-03-18 12:23:33 +0000 | [diff] [blame] | 2330 | /*--- Integer Instruction Translation --- */ |
cerion | e9d361a | 2005-03-04 17:35:29 +0000 | [diff] [blame] | 2331 | /*------------------------------------------------------------*/ |
cerion | 896a137 | 2005-01-25 12:24:25 +0000 | [diff] [blame] | 2332 | |
cerion | 91ad536 | 2005-01-27 23:02:41 +0000 | [diff] [blame] | 2333 | /* |
| 2334 | Integer Arithmetic Instructions |
| 2335 | */ |
cerion | 645c930 | 2005-01-31 10:09:59 +0000 | [diff] [blame] | 2336 | static Bool dis_int_arith ( UInt theInstr ) |
cerion | 91ad536 | 2005-01-27 23:02:41 +0000 | [diff] [blame] | 2337 | { |
cerion | 76de5cf | 2005-11-18 18:25:12 +0000 | [diff] [blame] | 2338 | /* D-Form, XO-Form */ |
| 2339 | UChar opc1 = ifieldOPC(theInstr); |
| 2340 | UChar rD_addr = ifieldRegDS(theInstr); |
| 2341 | UChar rA_addr = ifieldRegA(theInstr); |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 2342 | UInt uimm16 = ifieldUIMM16(theInstr); |
cerion | 76de5cf | 2005-11-18 18:25:12 +0000 | [diff] [blame] | 2343 | UChar rB_addr = ifieldRegB(theInstr); |
| 2344 | UChar flag_OE = ifieldBIT10(theInstr); |
| 2345 | UInt opc2 = ifieldOPClo9(theInstr); |
| 2346 | UChar flag_rC = ifieldBIT0(theInstr); |
| 2347 | |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 2348 | Long simm16 = extend_s_16to64(uimm16); |
| 2349 | IRType ty = mode64 ? Ity_I64 : Ity_I32; |
| 2350 | IRTemp rA = newTemp(ty); |
| 2351 | IRTemp rB = newTemp(ty); |
| 2352 | IRTemp rD = newTemp(ty); |
cerion | 70e2412 | 2005-03-16 00:27:37 +0000 | [diff] [blame] | 2353 | |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 2354 | Bool do_rc = False; |
cerion | 91ad536 | 2005-01-27 23:02:41 +0000 | [diff] [blame] | 2355 | |
cerion | 76de5cf | 2005-11-18 18:25:12 +0000 | [diff] [blame] | 2356 | assign( rA, getIReg(rA_addr) ); |
| 2357 | assign( rB, getIReg(rB_addr) ); // XO-Form: rD, rA, rB |
sewardj | b51f0f4 | 2005-07-18 11:38:02 +0000 | [diff] [blame] | 2358 | |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 2359 | switch (opc1) { |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 2360 | /* D-Form */ |
cerion | e9d361a | 2005-03-04 17:35:29 +0000 | [diff] [blame] | 2361 | case 0x0C: // addic (Add Immediate Carrying, PPC32 p351 |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 2362 | DIP("addic r%u,r%u,%d\n", rD_addr, rA_addr, (Int)simm16); |
cerion | 2831b00 | 2005-11-30 19:55:22 +0000 | [diff] [blame] | 2363 | assign( rD, binop( mkSzOp(ty, Iop_Add8), mkexpr(rA), |
| 2364 | mkSzExtendS16(ty, uimm16) ) ); |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 2365 | set_XER_CA( ty, PPCG_FLAG_OP_ADD, |
cerion | 2831b00 | 2005-11-30 19:55:22 +0000 | [diff] [blame] | 2366 | mkexpr(rD), mkexpr(rA), mkSzExtendS16(ty, uimm16), |
| 2367 | mkSzImm(ty, 0)/*old xer.ca, which is ignored*/ ); |
cerion | 4561acb | 2005-02-21 14:07:48 +0000 | [diff] [blame] | 2368 | break; |
sewardj | b51f0f4 | 2005-07-18 11:38:02 +0000 | [diff] [blame] | 2369 | |
cerion | e9d361a | 2005-03-04 17:35:29 +0000 | [diff] [blame] | 2370 | case 0x0D: // addic. (Add Immediate Carrying and Record, PPC32 p352) |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 2371 | DIP("addic. r%u,r%u,%d\n", rD_addr, rA_addr, (Int)simm16); |
cerion | 2831b00 | 2005-11-30 19:55:22 +0000 | [diff] [blame] | 2372 | assign( rD, binop( mkSzOp(ty, Iop_Add8), mkexpr(rA), |
| 2373 | mkSzExtendS16(ty, uimm16) ) ); |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 2374 | set_XER_CA( ty, PPCG_FLAG_OP_ADD, |
cerion | 2831b00 | 2005-11-30 19:55:22 +0000 | [diff] [blame] | 2375 | mkexpr(rD), mkexpr(rA), mkSzExtendS16(ty, uimm16), |
| 2376 | mkSzImm(ty, 0)/*old xer.ca, which is ignored*/ ); |
cerion | 70e2412 | 2005-03-16 00:27:37 +0000 | [diff] [blame] | 2377 | do_rc = True; // Always record to CR |
cerion | 76de5cf | 2005-11-18 18:25:12 +0000 | [diff] [blame] | 2378 | flag_rC = 1; |
cerion | 4561acb | 2005-02-21 14:07:48 +0000 | [diff] [blame] | 2379 | break; |
| 2380 | |
cerion | e9d361a | 2005-03-04 17:35:29 +0000 | [diff] [blame] | 2381 | case 0x0E: // addi (Add Immediate, PPC32 p350) |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 2382 | // li rD,val == addi rD,0,val |
| 2383 | // la disp(rA) == addi rD,rA,disp |
cerion | 76de5cf | 2005-11-18 18:25:12 +0000 | [diff] [blame] | 2384 | if ( rA_addr == 0 ) { |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 2385 | DIP("li r%u,%d\n", rD_addr, (Int)simm16); |
cerion | 2831b00 | 2005-11-30 19:55:22 +0000 | [diff] [blame] | 2386 | assign( rD, mkSzExtendS16(ty, uimm16) ); |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 2387 | } else { |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 2388 | DIP("addi r%u,r%u,%d\n", rD_addr, rA_addr, (Int)simm16); |
cerion | 2831b00 | 2005-11-30 19:55:22 +0000 | [diff] [blame] | 2389 | assign( rD, binop( mkSzOp(ty, Iop_Add8), mkexpr(rA), |
| 2390 | mkSzExtendS16(ty, uimm16) ) ); |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 2391 | } |
| 2392 | break; |
cerion | 91ad536 | 2005-01-27 23:02:41 +0000 | [diff] [blame] | 2393 | |
cerion | e9d361a | 2005-03-04 17:35:29 +0000 | [diff] [blame] | 2394 | case 0x0F: // addis (Add Immediate Shifted, PPC32 p353) |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 2395 | // lis rD,val == addis rD,0,val |
cerion | 76de5cf | 2005-11-18 18:25:12 +0000 | [diff] [blame] | 2396 | if ( rA_addr == 0 ) { |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 2397 | DIP("lis r%u,%d\n", rD_addr, (Int)simm16); |
cerion | 2831b00 | 2005-11-30 19:55:22 +0000 | [diff] [blame] | 2398 | assign( rD, mkSzExtendS32(ty, uimm16 << 16) ); |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 2399 | } else { |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 2400 | DIP("addis r%u,r%u,0x%x\n", rD_addr, rA_addr, (Int)simm16); |
cerion | 2831b00 | 2005-11-30 19:55:22 +0000 | [diff] [blame] | 2401 | assign( rD, binop( mkSzOp(ty, Iop_Add8), mkexpr(rA), |
| 2402 | mkSzExtendS32(ty, uimm16 << 16) ) ); |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 2403 | } |
| 2404 | break; |
cerion | 91ad536 | 2005-01-27 23:02:41 +0000 | [diff] [blame] | 2405 | |
cerion | e9d361a | 2005-03-04 17:35:29 +0000 | [diff] [blame] | 2406 | case 0x07: // mulli (Multiply Low Immediate, PPC32 p490) |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 2407 | DIP("mulli r%u,r%u,%d\n", rD_addr, rA_addr, (Int)simm16); |
| 2408 | if (mode64) |
| 2409 | assign( rD, unop(Iop_128to64, |
| 2410 | binop(Iop_MullS64, mkexpr(rA), |
cerion | 2831b00 | 2005-11-30 19:55:22 +0000 | [diff] [blame] | 2411 | mkSzExtendS16(ty, uimm16))) ); |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 2412 | else |
| 2413 | assign( rD, unop(Iop_64to32, |
| 2414 | binop(Iop_MullS32, mkexpr(rA), |
cerion | 2831b00 | 2005-11-30 19:55:22 +0000 | [diff] [blame] | 2415 | mkSzExtendS16(ty, uimm16))) ); |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 2416 | break; |
cerion | 3867460 | 2005-02-08 02:19:25 +0000 | [diff] [blame] | 2417 | |
cerion | e9d361a | 2005-03-04 17:35:29 +0000 | [diff] [blame] | 2418 | case 0x08: // subfic (Subtract from Immediate Carrying, PPC32 p540) |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 2419 | DIP("subfic r%u,r%u,%d\n", rD_addr, rA_addr, (Int)simm16); |
cerion | 76de5cf | 2005-11-18 18:25:12 +0000 | [diff] [blame] | 2420 | // rD = simm16 - rA |
cerion | 2831b00 | 2005-11-30 19:55:22 +0000 | [diff] [blame] | 2421 | assign( rD, binop( mkSzOp(ty, Iop_Sub8), |
| 2422 | mkSzExtendS16(ty, uimm16), |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 2423 | mkexpr(rA)) ); |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 2424 | set_XER_CA( ty, PPCG_FLAG_OP_SUBFI, |
cerion | 2831b00 | 2005-11-30 19:55:22 +0000 | [diff] [blame] | 2425 | mkexpr(rD), mkexpr(rA), mkSzExtendS16(ty, uimm16), |
| 2426 | mkSzImm(ty, 0)/*old xer.ca, which is ignored*/ ); |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 2427 | break; |
cerion | 3867460 | 2005-02-08 02:19:25 +0000 | [diff] [blame] | 2428 | |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 2429 | /* XO-Form */ |
| 2430 | case 0x1F: |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 2431 | do_rc = True; // All below record to CR |
| 2432 | |
| 2433 | switch (opc2) { |
cerion | e9d361a | 2005-03-04 17:35:29 +0000 | [diff] [blame] | 2434 | case 0x10A: // add (Add, PPC32 p347) |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 2435 | DIP("add%s%s r%u,r%u,r%u\n", |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 2436 | flag_OE ? "o" : "", flag_rC ? ".":"", |
cerion | 76de5cf | 2005-11-18 18:25:12 +0000 | [diff] [blame] | 2437 | rD_addr, rA_addr, rB_addr); |
cerion | 2831b00 | 2005-11-30 19:55:22 +0000 | [diff] [blame] | 2438 | assign( rD, binop( mkSzOp(ty, Iop_Add8), |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 2439 | mkexpr(rA), mkexpr(rB) ) ); |
cerion | 70e2412 | 2005-03-16 00:27:37 +0000 | [diff] [blame] | 2440 | if (flag_OE) { |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 2441 | set_XER_OV( ty, PPCG_FLAG_OP_ADD, |
cerion | 76de5cf | 2005-11-18 18:25:12 +0000 | [diff] [blame] | 2442 | mkexpr(rD), mkexpr(rA), mkexpr(rB) ); |
cerion | 70e2412 | 2005-03-16 00:27:37 +0000 | [diff] [blame] | 2443 | } |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 2444 | break; |
cerion | 91ad536 | 2005-01-27 23:02:41 +0000 | [diff] [blame] | 2445 | |
cerion | e9d361a | 2005-03-04 17:35:29 +0000 | [diff] [blame] | 2446 | case 0x00A: // addc (Add Carrying, PPC32 p348) |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 2447 | DIP("addc%s%s r%u,r%u,r%u\n", |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 2448 | flag_OE ? "o" : "", flag_rC ? ".":"", |
cerion | 76de5cf | 2005-11-18 18:25:12 +0000 | [diff] [blame] | 2449 | rD_addr, rA_addr, rB_addr); |
cerion | 2831b00 | 2005-11-30 19:55:22 +0000 | [diff] [blame] | 2450 | assign( rD, binop( mkSzOp(ty, Iop_Add8), |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 2451 | mkexpr(rA), mkexpr(rB)) ); |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 2452 | set_XER_CA( ty, PPCG_FLAG_OP_ADD, |
cerion | 76de5cf | 2005-11-18 18:25:12 +0000 | [diff] [blame] | 2453 | mkexpr(rD), mkexpr(rA), mkexpr(rB), |
cerion | 2831b00 | 2005-11-30 19:55:22 +0000 | [diff] [blame] | 2454 | mkSzImm(ty, 0)/*old xer.ca, which is ignored*/ ); |
cerion | 70e2412 | 2005-03-16 00:27:37 +0000 | [diff] [blame] | 2455 | if (flag_OE) { |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 2456 | set_XER_OV( ty, PPCG_FLAG_OP_ADD, |
cerion | 76de5cf | 2005-11-18 18:25:12 +0000 | [diff] [blame] | 2457 | mkexpr(rD), mkexpr(rA), mkexpr(rB) ); |
cerion | 70e2412 | 2005-03-16 00:27:37 +0000 | [diff] [blame] | 2458 | } |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 2459 | break; |
| 2460 | |
sewardj | b51f0f4 | 2005-07-18 11:38:02 +0000 | [diff] [blame] | 2461 | case 0x08A: { // adde (Add Extended, PPC32 p349) |
cerion | 2831b00 | 2005-11-30 19:55:22 +0000 | [diff] [blame] | 2462 | IRTemp old_xer_ca = newTemp(ty); |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 2463 | DIP("adde%s%s r%u,r%u,r%u\n", |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 2464 | flag_OE ? "o" : "", flag_rC ? ".":"", |
cerion | 76de5cf | 2005-11-18 18:25:12 +0000 | [diff] [blame] | 2465 | rD_addr, rA_addr, rB_addr); |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 2466 | // rD = rA + rB + XER[CA] |
cerion | 2831b00 | 2005-11-30 19:55:22 +0000 | [diff] [blame] | 2467 | assign( old_xer_ca, mkSzWiden32(ty, getXER_CA32(), False) ); |
| 2468 | assign( rD, binop( mkSzOp(ty, Iop_Add8), mkexpr(rA), |
| 2469 | binop( mkSzOp(ty, Iop_Add8), |
| 2470 | mkexpr(rB), mkexpr(old_xer_ca))) ); |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 2471 | set_XER_CA( ty, PPCG_FLAG_OP_ADDE, |
cerion | 76de5cf | 2005-11-18 18:25:12 +0000 | [diff] [blame] | 2472 | mkexpr(rD), mkexpr(rA), mkexpr(rB), |
cerion | 2831b00 | 2005-11-30 19:55:22 +0000 | [diff] [blame] | 2473 | mkexpr(old_xer_ca) ); |
cerion | 70e2412 | 2005-03-16 00:27:37 +0000 | [diff] [blame] | 2474 | if (flag_OE) { |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 2475 | set_XER_OV( ty, PPCG_FLAG_OP_ADDE, |
cerion | 76de5cf | 2005-11-18 18:25:12 +0000 | [diff] [blame] | 2476 | mkexpr(rD), mkexpr(rA), mkexpr(rB) ); |
cerion | 70e2412 | 2005-03-16 00:27:37 +0000 | [diff] [blame] | 2477 | } |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 2478 | break; |
sewardj | b51f0f4 | 2005-07-18 11:38:02 +0000 | [diff] [blame] | 2479 | } |
| 2480 | |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 2481 | case 0x0EA: { // addme (Add to Minus One Extended, PPC32 p354) |
cerion | 2831b00 | 2005-11-30 19:55:22 +0000 | [diff] [blame] | 2482 | IRTemp old_xer_ca = newTemp(ty); |
| 2483 | IRExpr *min_one; |
cerion | 76de5cf | 2005-11-18 18:25:12 +0000 | [diff] [blame] | 2484 | if (rB_addr != 0) { |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 2485 | vex_printf("dis_int_arith(ppc)(addme,rB_addr)\n"); |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 2486 | return False; |
| 2487 | } |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 2488 | DIP("addme%s%s r%u,r%u,r%u\n", |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 2489 | flag_OE ? "o" : "", flag_rC ? ".":"", |
cerion | 76de5cf | 2005-11-18 18:25:12 +0000 | [diff] [blame] | 2490 | rD_addr, rA_addr, rB_addr); |
cerion | 70e2412 | 2005-03-16 00:27:37 +0000 | [diff] [blame] | 2491 | // rD = rA + (-1) + XER[CA] |
| 2492 | // => Just another form of adde |
cerion | 2831b00 | 2005-11-30 19:55:22 +0000 | [diff] [blame] | 2493 | assign( old_xer_ca, mkSzWiden32(ty, getXER_CA32(), False) ); |
| 2494 | min_one = mkSzImm(ty, (Long)-1); |
| 2495 | assign( rD, binop( mkSzOp(ty, Iop_Add8), mkexpr(rA), |
| 2496 | binop( mkSzOp(ty, Iop_Add8), |
| 2497 | min_one, mkexpr(old_xer_ca)) )); |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 2498 | set_XER_CA( ty, PPCG_FLAG_OP_ADDE, |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 2499 | mkexpr(rD), mkexpr(rA), min_one, |
cerion | 2831b00 | 2005-11-30 19:55:22 +0000 | [diff] [blame] | 2500 | mkexpr(old_xer_ca) ); |
cerion | 70e2412 | 2005-03-16 00:27:37 +0000 | [diff] [blame] | 2501 | if (flag_OE) { |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 2502 | set_XER_OV( ty, PPCG_FLAG_OP_ADDE, |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 2503 | mkexpr(rD), mkexpr(rA), min_one ); |
cerion | 70e2412 | 2005-03-16 00:27:37 +0000 | [diff] [blame] | 2504 | } |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 2505 | break; |
sewardj | b51f0f4 | 2005-07-18 11:38:02 +0000 | [diff] [blame] | 2506 | } |
| 2507 | |
| 2508 | case 0x0CA: { // addze (Add to Zero Extended, PPC32 p355) |
cerion | 2831b00 | 2005-11-30 19:55:22 +0000 | [diff] [blame] | 2509 | IRTemp old_xer_ca = newTemp(ty); |
cerion | 76de5cf | 2005-11-18 18:25:12 +0000 | [diff] [blame] | 2510 | if (rB_addr != 0) { |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 2511 | vex_printf("dis_int_arith(ppc)(addze,rB_addr)\n"); |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 2512 | return False; |
| 2513 | } |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 2514 | DIP("addze%s%s r%u,r%u,r%u\n", |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 2515 | flag_OE ? "o" : "", flag_rC ? ".":"", |
cerion | 76de5cf | 2005-11-18 18:25:12 +0000 | [diff] [blame] | 2516 | rD_addr, rA_addr, rB_addr); |
cerion | 70e2412 | 2005-03-16 00:27:37 +0000 | [diff] [blame] | 2517 | // rD = rA + (0) + XER[CA] |
| 2518 | // => Just another form of adde |
cerion | 2831b00 | 2005-11-30 19:55:22 +0000 | [diff] [blame] | 2519 | assign( old_xer_ca, mkSzWiden32(ty, getXER_CA32(), False) ); |
| 2520 | assign( rD, binop( mkSzOp(ty, Iop_Add8), |
| 2521 | mkexpr(rA), mkexpr(old_xer_ca)) ); |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 2522 | set_XER_CA( ty, PPCG_FLAG_OP_ADDE, |
cerion | 2831b00 | 2005-11-30 19:55:22 +0000 | [diff] [blame] | 2523 | mkexpr(rD), mkexpr(rA), mkSzImm(ty, 0), |
| 2524 | mkexpr(old_xer_ca) ); |
cerion | 70e2412 | 2005-03-16 00:27:37 +0000 | [diff] [blame] | 2525 | if (flag_OE) { |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 2526 | set_XER_OV( ty, PPCG_FLAG_OP_ADDE, |
cerion | 2831b00 | 2005-11-30 19:55:22 +0000 | [diff] [blame] | 2527 | mkexpr(rD), mkexpr(rA), mkSzImm(ty, 0) ); |
cerion | 70e2412 | 2005-03-16 00:27:37 +0000 | [diff] [blame] | 2528 | } |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 2529 | break; |
sewardj | b51f0f4 | 2005-07-18 11:38:02 +0000 | [diff] [blame] | 2530 | } |
cerion | 91ad536 | 2005-01-27 23:02:41 +0000 | [diff] [blame] | 2531 | |
cerion | e9d361a | 2005-03-04 17:35:29 +0000 | [diff] [blame] | 2532 | case 0x1EB: // divw (Divide Word, PPC32 p388) |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 2533 | DIP("divw%s%s r%u,r%u,r%u\n", |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 2534 | flag_OE ? "o" : "", flag_rC ? ".":"", |
cerion | 76de5cf | 2005-11-18 18:25:12 +0000 | [diff] [blame] | 2535 | rD_addr, rA_addr, rB_addr); |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 2536 | if (mode64) { |
cerion | 2831b00 | 2005-11-30 19:55:22 +0000 | [diff] [blame] | 2537 | /* Note: |
| 2538 | XER settings are mode independent, and reflect the |
| 2539 | overflow of the low-order 32bit result |
| 2540 | CR0[LT|GT|EQ] are undefined if flag_rC && mode64 |
| 2541 | */ |
cerion | bb01b7c | 2005-12-16 13:40:18 +0000 | [diff] [blame] | 2542 | /* rD[hi32] are undefined: setting them to sign of lo32 |
| 2543 | - makes set_CR0 happy */ |
| 2544 | IRExpr* dividend = mk64lo32Sto64( mkexpr(rA) ); |
| 2545 | IRExpr* divisor = mk64lo32Sto64( mkexpr(rB) ); |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 2546 | assign( rD, mk64lo32Uto64( binop(Iop_DivS64, dividend, |
| 2547 | divisor) ) ); |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 2548 | if (flag_OE) { |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 2549 | set_XER_OV( ty, PPCG_FLAG_OP_DIVW, |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 2550 | mkexpr(rD), dividend, divisor ); |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 2551 | } |
| 2552 | } else { |
| 2553 | assign( rD, binop(Iop_DivS32, mkexpr(rA), mkexpr(rB)) ); |
| 2554 | if (flag_OE) { |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 2555 | set_XER_OV( ty, PPCG_FLAG_OP_DIVW, |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 2556 | mkexpr(rD), mkexpr(rA), mkexpr(rB) ); |
| 2557 | } |
cerion | 70e2412 | 2005-03-16 00:27:37 +0000 | [diff] [blame] | 2558 | } |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 2559 | /* Note: |
| 2560 | if (0x8000_0000 / -1) or (x / 0) |
cerion | 76de5cf | 2005-11-18 18:25:12 +0000 | [diff] [blame] | 2561 | => rD=undef, if(flag_rC) CR7=undef, if(flag_OE) XER_OV=1 |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 2562 | => But _no_ exception raised. */ |
| 2563 | break; |
cerion | 91ad536 | 2005-01-27 23:02:41 +0000 | [diff] [blame] | 2564 | |
cerion | e9d361a | 2005-03-04 17:35:29 +0000 | [diff] [blame] | 2565 | case 0x1CB: // divwu (Divide Word Unsigned, PPC32 p389) |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 2566 | DIP("divwu%s%s r%u,r%u,r%u\n", |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 2567 | flag_OE ? "o" : "", flag_rC ? ".":"", |
cerion | 76de5cf | 2005-11-18 18:25:12 +0000 | [diff] [blame] | 2568 | rD_addr, rA_addr, rB_addr); |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 2569 | if (mode64) { |
cerion | 2831b00 | 2005-11-30 19:55:22 +0000 | [diff] [blame] | 2570 | /* Note: |
| 2571 | XER settings are mode independent, and reflect the |
| 2572 | overflow of the low-order 32bit result |
| 2573 | CR0[LT|GT|EQ] are undefined if flag_rC && mode64 |
| 2574 | */ |
cerion | bb01b7c | 2005-12-16 13:40:18 +0000 | [diff] [blame] | 2575 | IRExpr* dividend = mk64lo32Uto64( mkexpr(rA) ); |
| 2576 | IRExpr* divisor = mk64lo32Uto64( mkexpr(rB) ); |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 2577 | assign( rD, mk64lo32Uto64( binop(Iop_DivU64, dividend, |
| 2578 | divisor) ) ); |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 2579 | if (flag_OE) { |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 2580 | set_XER_OV( ty, PPCG_FLAG_OP_DIVWU, |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 2581 | mkexpr(rD), dividend, divisor ); |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 2582 | } |
cerion | 2831b00 | 2005-11-30 19:55:22 +0000 | [diff] [blame] | 2583 | } else { |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 2584 | assign( rD, binop(Iop_DivU32, mkexpr(rA), mkexpr(rB)) ); |
| 2585 | if (flag_OE) { |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 2586 | set_XER_OV( ty, PPCG_FLAG_OP_DIVWU, |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 2587 | mkexpr(rD), mkexpr(rA), mkexpr(rB) ); |
| 2588 | } |
cerion | 70e2412 | 2005-03-16 00:27:37 +0000 | [diff] [blame] | 2589 | } |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 2590 | /* Note: ditto comment divw, for (x / 0) */ |
| 2591 | break; |
cerion | 91ad536 | 2005-01-27 23:02:41 +0000 | [diff] [blame] | 2592 | |
cerion | e9d361a | 2005-03-04 17:35:29 +0000 | [diff] [blame] | 2593 | case 0x04B: // mulhw (Multiply High Word, PPC32 p488) |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 2594 | if (flag_OE != 0) { |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 2595 | vex_printf("dis_int_arith(ppc)(mulhw,flag_OE)\n"); |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 2596 | return False; |
| 2597 | } |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 2598 | DIP("mulhw%s r%u,r%u,r%u\n", flag_rC ? ".":"", |
cerion | 76de5cf | 2005-11-18 18:25:12 +0000 | [diff] [blame] | 2599 | rD_addr, rA_addr, rB_addr); |
cerion | 2831b00 | 2005-11-30 19:55:22 +0000 | [diff] [blame] | 2600 | if (mode64) { |
cerion | bb01b7c | 2005-12-16 13:40:18 +0000 | [diff] [blame] | 2601 | /* rD[hi32] are undefined: setting them to sign of lo32 |
| 2602 | - makes set_CR0 happy */ |
| 2603 | assign( rD, binop(Iop_Sar64, |
| 2604 | binop(Iop_Mul64, |
| 2605 | mk64lo32Sto64( mkexpr(rA) ), |
| 2606 | mk64lo32Sto64( mkexpr(rB) )), |
| 2607 | mkU8(32)) ); |
cerion | 2831b00 | 2005-11-30 19:55:22 +0000 | [diff] [blame] | 2608 | } else { |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 2609 | assign( rD, unop(Iop_64HIto32, |
| 2610 | binop(Iop_MullS32, |
| 2611 | mkexpr(rA), mkexpr(rB))) ); |
cerion | 2831b00 | 2005-11-30 19:55:22 +0000 | [diff] [blame] | 2612 | } |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 2613 | break; |
cerion | c19d5e1 | 2005-02-01 15:56:25 +0000 | [diff] [blame] | 2614 | |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 2615 | case 0x00B: // mulhwu (Multiply High Word Unsigned, PPC32 p489) |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 2616 | if (flag_OE != 0) { |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 2617 | vex_printf("dis_int_arith(ppc)(mulhwu,flag_OE)\n"); |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 2618 | return False; |
| 2619 | } |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 2620 | DIP("mulhwu%s r%u,r%u,r%u\n", flag_rC ? ".":"", |
cerion | 76de5cf | 2005-11-18 18:25:12 +0000 | [diff] [blame] | 2621 | rD_addr, rA_addr, rB_addr); |
cerion | 2831b00 | 2005-11-30 19:55:22 +0000 | [diff] [blame] | 2622 | if (mode64) { |
cerion | bb01b7c | 2005-12-16 13:40:18 +0000 | [diff] [blame] | 2623 | /* rD[hi32] are undefined: setting them to sign of lo32 |
| 2624 | - makes set_CR0 happy */ |
| 2625 | assign( rD, binop(Iop_Sar64, |
| 2626 | binop(Iop_Mul64, |
| 2627 | mk64lo32Uto64( mkexpr(rA) ), |
| 2628 | mk64lo32Uto64( mkexpr(rB) ) ), |
| 2629 | mkU8(32)) ); |
cerion | 2831b00 | 2005-11-30 19:55:22 +0000 | [diff] [blame] | 2630 | } else { |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 2631 | assign( rD, unop(Iop_64HIto32, |
| 2632 | binop(Iop_MullU32, |
| 2633 | mkexpr(rA), mkexpr(rB))) ); |
cerion | 2831b00 | 2005-11-30 19:55:22 +0000 | [diff] [blame] | 2634 | } |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 2635 | break; |
| 2636 | |
cerion | e9d361a | 2005-03-04 17:35:29 +0000 | [diff] [blame] | 2637 | case 0x0EB: // mullw (Multiply Low Word, PPC32 p491) |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 2638 | DIP("mullw%s%s r%u,r%u,r%u\n", |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 2639 | flag_OE ? "o" : "", flag_rC ? ".":"", |
cerion | 76de5cf | 2005-11-18 18:25:12 +0000 | [diff] [blame] | 2640 | rD_addr, rA_addr, rB_addr); |
cerion | 2831b00 | 2005-11-30 19:55:22 +0000 | [diff] [blame] | 2641 | if (mode64) { |
cerion | bb01b7c | 2005-12-16 13:40:18 +0000 | [diff] [blame] | 2642 | /* rD[hi32] are undefined: setting them to sign of lo32 |
| 2643 | - set_XER_OV() and set_CR0() depend on this */ |
| 2644 | IRExpr *a = unop(Iop_64to32, mkexpr(rA) ); |
| 2645 | IRExpr *b = unop(Iop_64to32, mkexpr(rB) ); |
| 2646 | assign( rD, binop(Iop_MullS32, a, b) ); |
| 2647 | if (flag_OE) { |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 2648 | set_XER_OV( ty, PPCG_FLAG_OP_MULLW, |
cerion | bb01b7c | 2005-12-16 13:40:18 +0000 | [diff] [blame] | 2649 | mkexpr(rD), |
| 2650 | unop(Iop_32Uto64, a), unop(Iop_32Uto64, b) ); |
| 2651 | } |
cerion | 2831b00 | 2005-11-30 19:55:22 +0000 | [diff] [blame] | 2652 | } else { |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 2653 | assign( rD, unop(Iop_64to32, |
| 2654 | binop(Iop_MullU32, |
| 2655 | mkexpr(rA), mkexpr(rB))) ); |
cerion | bb01b7c | 2005-12-16 13:40:18 +0000 | [diff] [blame] | 2656 | if (flag_OE) { |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 2657 | set_XER_OV( ty, PPCG_FLAG_OP_MULLW, |
cerion | bb01b7c | 2005-12-16 13:40:18 +0000 | [diff] [blame] | 2658 | mkexpr(rD), mkexpr(rA), mkexpr(rB) ); |
| 2659 | } |
cerion | 70e2412 | 2005-03-16 00:27:37 +0000 | [diff] [blame] | 2660 | } |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 2661 | break; |
cerion | c19d5e1 | 2005-02-01 15:56:25 +0000 | [diff] [blame] | 2662 | |
cerion | e9d361a | 2005-03-04 17:35:29 +0000 | [diff] [blame] | 2663 | case 0x068: // neg (Negate, PPC32 p493) |
cerion | 76de5cf | 2005-11-18 18:25:12 +0000 | [diff] [blame] | 2664 | if (rB_addr != 0) { |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 2665 | vex_printf("dis_int_arith(ppc)(neg,rB_addr)\n"); |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 2666 | return False; |
| 2667 | } |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 2668 | DIP("neg%s%s r%u,r%u\n", |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 2669 | flag_OE ? "o" : "", flag_rC ? ".":"", |
cerion | 76de5cf | 2005-11-18 18:25:12 +0000 | [diff] [blame] | 2670 | rD_addr, rA_addr); |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 2671 | // rD = (~rA) + 1 |
cerion | 2831b00 | 2005-11-30 19:55:22 +0000 | [diff] [blame] | 2672 | assign( rD, binop( mkSzOp(ty, Iop_Add8), |
| 2673 | unop( mkSzOp(ty, Iop_Not8), mkexpr(rA) ), |
| 2674 | mkSzImm(ty, 1)) ); |
cerion | 70e2412 | 2005-03-16 00:27:37 +0000 | [diff] [blame] | 2675 | if (flag_OE) { |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 2676 | set_XER_OV( ty, PPCG_FLAG_OP_NEG, |
cerion | 76de5cf | 2005-11-18 18:25:12 +0000 | [diff] [blame] | 2677 | mkexpr(rD), mkexpr(rA), mkexpr(rB) ); |
cerion | 70e2412 | 2005-03-16 00:27:37 +0000 | [diff] [blame] | 2678 | } |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 2679 | break; |
cerion | 91ad536 | 2005-01-27 23:02:41 +0000 | [diff] [blame] | 2680 | |
cerion | e9d361a | 2005-03-04 17:35:29 +0000 | [diff] [blame] | 2681 | case 0x028: // subf (Subtract From, PPC32 p537) |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 2682 | DIP("subf%s%s r%u,r%u,r%u\n", |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 2683 | flag_OE ? "o" : "", flag_rC ? ".":"", |
cerion | 76de5cf | 2005-11-18 18:25:12 +0000 | [diff] [blame] | 2684 | rD_addr, rA_addr, rB_addr); |
cerion | 0190847 | 2005-02-25 16:43:08 +0000 | [diff] [blame] | 2685 | // rD = rB - rA |
cerion | 2831b00 | 2005-11-30 19:55:22 +0000 | [diff] [blame] | 2686 | assign( rD, binop( mkSzOp(ty, Iop_Sub8), |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 2687 | mkexpr(rB), mkexpr(rA)) ); |
cerion | 70e2412 | 2005-03-16 00:27:37 +0000 | [diff] [blame] | 2688 | if (flag_OE) { |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 2689 | set_XER_OV( ty, PPCG_FLAG_OP_SUBF, |
cerion | 76de5cf | 2005-11-18 18:25:12 +0000 | [diff] [blame] | 2690 | mkexpr(rD), mkexpr(rA), mkexpr(rB) ); |
cerion | 70e2412 | 2005-03-16 00:27:37 +0000 | [diff] [blame] | 2691 | } |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 2692 | break; |
cerion | 3867460 | 2005-02-08 02:19:25 +0000 | [diff] [blame] | 2693 | |
cerion | e9d361a | 2005-03-04 17:35:29 +0000 | [diff] [blame] | 2694 | case 0x008: // subfc (Subtract from Carrying, PPC32 p538) |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 2695 | DIP("subfc%s%s r%u,r%u,r%u\n", |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 2696 | flag_OE ? "o" : "", flag_rC ? ".":"", |
cerion | 76de5cf | 2005-11-18 18:25:12 +0000 | [diff] [blame] | 2697 | rD_addr, rA_addr, rB_addr); |
cerion | 0190847 | 2005-02-25 16:43:08 +0000 | [diff] [blame] | 2698 | // rD = rB - rA |
cerion | 2831b00 | 2005-11-30 19:55:22 +0000 | [diff] [blame] | 2699 | assign( rD, binop( mkSzOp(ty, Iop_Sub8), |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 2700 | mkexpr(rB), mkexpr(rA)) ); |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 2701 | set_XER_CA( ty, PPCG_FLAG_OP_SUBFC, |
cerion | 76de5cf | 2005-11-18 18:25:12 +0000 | [diff] [blame] | 2702 | mkexpr(rD), mkexpr(rA), mkexpr(rB), |
cerion | 2831b00 | 2005-11-30 19:55:22 +0000 | [diff] [blame] | 2703 | mkSzImm(ty, 0)/*old xer.ca, which is ignored*/ ); |
cerion | 70e2412 | 2005-03-16 00:27:37 +0000 | [diff] [blame] | 2704 | if (flag_OE) { |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 2705 | set_XER_OV( ty, PPCG_FLAG_OP_SUBFC, |
cerion | 76de5cf | 2005-11-18 18:25:12 +0000 | [diff] [blame] | 2706 | mkexpr(rD), mkexpr(rA), mkexpr(rB) ); |
cerion | 70e2412 | 2005-03-16 00:27:37 +0000 | [diff] [blame] | 2707 | } |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 2708 | break; |
| 2709 | |
sewardj | b51f0f4 | 2005-07-18 11:38:02 +0000 | [diff] [blame] | 2710 | case 0x088: {// subfe (Subtract from Extended, PPC32 p539) |
cerion | 2831b00 | 2005-11-30 19:55:22 +0000 | [diff] [blame] | 2711 | IRTemp old_xer_ca = newTemp(ty); |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 2712 | DIP("subfe%s%s r%u,r%u,r%u\n", |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 2713 | flag_OE ? "o" : "", flag_rC ? ".":"", |
cerion | 76de5cf | 2005-11-18 18:25:12 +0000 | [diff] [blame] | 2714 | rD_addr, rA_addr, rB_addr); |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 2715 | // rD = (log not)rA + rB + XER[CA] |
cerion | 2831b00 | 2005-11-30 19:55:22 +0000 | [diff] [blame] | 2716 | assign( old_xer_ca, mkSzWiden32(ty, getXER_CA32(), False) ); |
| 2717 | assign( rD, binop( mkSzOp(ty, Iop_Add8), |
| 2718 | unop( mkSzOp(ty, Iop_Not8), mkexpr(rA)), |
| 2719 | binop( mkSzOp(ty, Iop_Add8), |
| 2720 | mkexpr(rB), mkexpr(old_xer_ca))) ); |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 2721 | set_XER_CA( ty, PPCG_FLAG_OP_SUBFE, |
cerion | 76de5cf | 2005-11-18 18:25:12 +0000 | [diff] [blame] | 2722 | mkexpr(rD), mkexpr(rA), mkexpr(rB), |
cerion | 2831b00 | 2005-11-30 19:55:22 +0000 | [diff] [blame] | 2723 | mkexpr(old_xer_ca) ); |
cerion | 70e2412 | 2005-03-16 00:27:37 +0000 | [diff] [blame] | 2724 | if (flag_OE) { |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 2725 | set_XER_OV( ty, PPCG_FLAG_OP_SUBFE, |
cerion | 76de5cf | 2005-11-18 18:25:12 +0000 | [diff] [blame] | 2726 | mkexpr(rD), mkexpr(rA), mkexpr(rB) ); |
cerion | 70e2412 | 2005-03-16 00:27:37 +0000 | [diff] [blame] | 2727 | } |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 2728 | break; |
sewardj | b51f0f4 | 2005-07-18 11:38:02 +0000 | [diff] [blame] | 2729 | } |
| 2730 | |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 2731 | case 0x0E8: { // subfme (Subtract from -1 Extended, PPC32 p541) |
cerion | 2831b00 | 2005-11-30 19:55:22 +0000 | [diff] [blame] | 2732 | IRTemp old_xer_ca = newTemp(ty); |
| 2733 | IRExpr *min_one; |
cerion | 76de5cf | 2005-11-18 18:25:12 +0000 | [diff] [blame] | 2734 | if (rB_addr != 0) { |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 2735 | vex_printf("dis_int_arith(ppc)(subfme,rB_addr)\n"); |
sewardj | 20ef547 | 2005-07-21 14:48:31 +0000 | [diff] [blame] | 2736 | return False; |
| 2737 | } |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 2738 | DIP("subfme%s%s r%u,r%u\n", |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 2739 | flag_OE ? "o" : "", flag_rC ? ".":"", |
cerion | 76de5cf | 2005-11-18 18:25:12 +0000 | [diff] [blame] | 2740 | rD_addr, rA_addr); |
sewardj | 20ef547 | 2005-07-21 14:48:31 +0000 | [diff] [blame] | 2741 | // rD = (log not)rA + (-1) + XER[CA] |
| 2742 | // => Just another form of subfe |
cerion | 2831b00 | 2005-11-30 19:55:22 +0000 | [diff] [blame] | 2743 | assign( old_xer_ca, mkSzWiden32(ty, getXER_CA32(), False) ); |
| 2744 | min_one = mkSzImm(ty, (Long)-1); |
| 2745 | assign( rD, binop( mkSzOp(ty, Iop_Add8), |
| 2746 | unop( mkSzOp(ty, Iop_Not8), mkexpr(rA)), |
| 2747 | binop( mkSzOp(ty, Iop_Add8), |
| 2748 | min_one, mkexpr(old_xer_ca))) ); |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 2749 | set_XER_CA( ty, PPCG_FLAG_OP_SUBFE, |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 2750 | mkexpr(rD), mkexpr(rA), min_one, |
cerion | 2831b00 | 2005-11-30 19:55:22 +0000 | [diff] [blame] | 2751 | mkexpr(old_xer_ca) ); |
sewardj | 20ef547 | 2005-07-21 14:48:31 +0000 | [diff] [blame] | 2752 | if (flag_OE) { |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 2753 | set_XER_OV( ty, PPCG_FLAG_OP_SUBFE, |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 2754 | mkexpr(rD), mkexpr(rA), min_one ); |
sewardj | 20ef547 | 2005-07-21 14:48:31 +0000 | [diff] [blame] | 2755 | } |
| 2756 | break; |
| 2757 | } |
| 2758 | |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 2759 | case 0x0C8: { // subfze (Subtract from Zero Extended, PPC32 p542) |
cerion | 2831b00 | 2005-11-30 19:55:22 +0000 | [diff] [blame] | 2760 | IRTemp old_xer_ca = newTemp(ty); |
cerion | 76de5cf | 2005-11-18 18:25:12 +0000 | [diff] [blame] | 2761 | if (rB_addr != 0) { |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 2762 | vex_printf("dis_int_arith(ppc)(subfze,rB_addr)\n"); |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 2763 | return False; |
| 2764 | } |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 2765 | DIP("subfze%s%s r%u,r%u\n", |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 2766 | flag_OE ? "o" : "", flag_rC ? ".":"", |
cerion | 76de5cf | 2005-11-18 18:25:12 +0000 | [diff] [blame] | 2767 | rD_addr, rA_addr); |
cerion | 70e2412 | 2005-03-16 00:27:37 +0000 | [diff] [blame] | 2768 | // rD = (log not)rA + (0) + XER[CA] |
| 2769 | // => Just another form of subfe |
cerion | 2831b00 | 2005-11-30 19:55:22 +0000 | [diff] [blame] | 2770 | assign( old_xer_ca, mkSzWiden32(ty, getXER_CA32(), False) ); |
| 2771 | assign( rD, binop( mkSzOp(ty, Iop_Add8), |
| 2772 | unop( mkSzOp(ty, Iop_Not8), |
| 2773 | mkexpr(rA)), mkexpr(old_xer_ca)) ); |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 2774 | set_XER_CA( ty, PPCG_FLAG_OP_SUBFE, |
cerion | 2831b00 | 2005-11-30 19:55:22 +0000 | [diff] [blame] | 2775 | mkexpr(rD), mkexpr(rA), mkSzImm(ty, 0), |
| 2776 | mkexpr(old_xer_ca) ); |
cerion | 70e2412 | 2005-03-16 00:27:37 +0000 | [diff] [blame] | 2777 | if (flag_OE) { |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 2778 | set_XER_OV( ty, PPCG_FLAG_OP_SUBFE, |
cerion | 2831b00 | 2005-11-30 19:55:22 +0000 | [diff] [blame] | 2779 | mkexpr(rD), mkexpr(rA), mkSzImm(ty, 0) ); |
cerion | 70e2412 | 2005-03-16 00:27:37 +0000 | [diff] [blame] | 2780 | } |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 2781 | break; |
sewardj | b51f0f4 | 2005-07-18 11:38:02 +0000 | [diff] [blame] | 2782 | } |
cerion | ae69462 | 2005-01-28 17:52:47 +0000 | [diff] [blame] | 2783 | |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 2784 | |
| 2785 | /* 64bit Arithmetic */ |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 2786 | case 0x49: // mulhd (Multiply High DWord, PPC64 p539) |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 2787 | if (flag_OE != 0) { |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 2788 | vex_printf("dis_int_arith(ppc)(mulhd,flagOE)\n"); |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 2789 | return False; |
| 2790 | } |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 2791 | DIP("mulhd%s r%u,r%u,r%u\n", flag_rC ? ".":"", |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 2792 | rD_addr, rA_addr, rB_addr); |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 2793 | assign( rD, unop(Iop_128HIto64, |
cerion | 07b07a9 | 2005-12-22 14:32:35 +0000 | [diff] [blame] | 2794 | binop(Iop_MullS64, |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 2795 | mkexpr(rA), mkexpr(rB))) ); |
cerion | 07b07a9 | 2005-12-22 14:32:35 +0000 | [diff] [blame] | 2796 | |
| 2797 | break; |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 2798 | |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 2799 | case 0x9: // mulhdu (Multiply High DWord Unsigned, PPC64 p540) |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 2800 | if (flag_OE != 0) { |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 2801 | vex_printf("dis_int_arith(ppc)(mulhdu,flagOE)\n"); |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 2802 | return False; |
| 2803 | } |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 2804 | DIP("mulhdu%s r%u,r%u,r%u\n", flag_rC ? ".":"", |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 2805 | rD_addr, rA_addr, rB_addr); |
cerion | 07b07a9 | 2005-12-22 14:32:35 +0000 | [diff] [blame] | 2806 | assign( rD, unop(Iop_128HIto64, |
| 2807 | binop(Iop_MullU64, |
| 2808 | mkexpr(rA), mkexpr(rB))) ); |
| 2809 | break; |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 2810 | |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 2811 | case 0xE9: // mulld (Multiply Low DWord, PPC64 p543) |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 2812 | DIP("mulld%s%s r%u,r%u,r%u\n", |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 2813 | flag_OE ? "o" : "", flag_rC ? ".":"", |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 2814 | rD_addr, rA_addr, rB_addr); |
| 2815 | assign( rD, binop(Iop_Mul64, mkexpr(rA), mkexpr(rB)) ); |
| 2816 | if (flag_OE) { |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 2817 | set_XER_OV( ty, PPCG_FLAG_OP_MULLW, |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 2818 | mkexpr(rD), mkexpr(rA), mkexpr(rB) ); |
| 2819 | } |
| 2820 | break; |
| 2821 | |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 2822 | case 0x1E9: // divd (Divide DWord, PPC64 p419) |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 2823 | DIP("divd%s%s r%u,r%u,r%u\n", |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 2824 | flag_OE ? "o" : "", flag_rC ? ".":"", |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 2825 | rD_addr, rA_addr, rB_addr); |
cerion | 07b07a9 | 2005-12-22 14:32:35 +0000 | [diff] [blame] | 2826 | assign( rD, binop(Iop_DivS64, mkexpr(rA), mkexpr(rB)) ); |
| 2827 | if (flag_OE) { |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 2828 | set_XER_OV( ty, PPCG_FLAG_OP_DIVW, |
cerion | 07b07a9 | 2005-12-22 14:32:35 +0000 | [diff] [blame] | 2829 | mkexpr(rD), mkexpr(rA), mkexpr(rB) ); |
| 2830 | } |
| 2831 | break; |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 2832 | /* Note: |
cerion | 07b07a9 | 2005-12-22 14:32:35 +0000 | [diff] [blame] | 2833 | if (0x8000_0000_0000_0000 / -1) or (x / 0) |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 2834 | => rD=undef, if(flag_rC) CR7=undef, if(flag_OE) XER_OV=1 |
| 2835 | => But _no_ exception raised. */ |
| 2836 | |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 2837 | case 0x1C9: // divdu (Divide DWord Unsigned, PPC64 p420) |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 2838 | DIP("divdu%s%s r%u,r%u,r%u\n", |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 2839 | flag_OE ? "o" : "", flag_rC ? ".":"", |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 2840 | rD_addr, rA_addr, rB_addr); |
cerion | 07b07a9 | 2005-12-22 14:32:35 +0000 | [diff] [blame] | 2841 | assign( rD, binop(Iop_DivU64, mkexpr(rA), mkexpr(rB)) ); |
| 2842 | if (flag_OE) { |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 2843 | set_XER_OV( ty, PPCG_FLAG_OP_DIVWU, |
cerion | 07b07a9 | 2005-12-22 14:32:35 +0000 | [diff] [blame] | 2844 | mkexpr(rD), mkexpr(rA), mkexpr(rB) ); |
| 2845 | } |
| 2846 | break; |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 2847 | /* Note: ditto comment divd, for (x / 0) */ |
| 2848 | |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 2849 | default: |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 2850 | vex_printf("dis_int_arith(ppc)(opc2)\n"); |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 2851 | return False; |
| 2852 | } |
| 2853 | break; |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 2854 | |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 2855 | default: |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 2856 | vex_printf("dis_int_arith(ppc)(opc1)\n"); |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 2857 | return False; |
| 2858 | } |
cerion | 91ad536 | 2005-01-27 23:02:41 +0000 | [diff] [blame] | 2859 | |
cerion | 76de5cf | 2005-11-18 18:25:12 +0000 | [diff] [blame] | 2860 | putIReg( rD_addr, mkexpr(rD) ); |
| 2861 | |
| 2862 | if (do_rc && flag_rC) { |
| 2863 | set_CR0( mkexpr(rD) ); |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 2864 | } |
| 2865 | return True; |
cerion | 91ad536 | 2005-01-27 23:02:41 +0000 | [diff] [blame] | 2866 | } |
| 2867 | |
| 2868 | |
| 2869 | |
cerion | 3d870a3 | 2005-03-18 12:23:33 +0000 | [diff] [blame] | 2870 | /* |
| 2871 | Integer Compare Instructions |
| 2872 | */ |
cerion | 7aa4bbc | 2005-01-29 09:32:07 +0000 | [diff] [blame] | 2873 | static Bool dis_int_cmp ( UInt theInstr ) |
| 2874 | { |
cerion | 76de5cf | 2005-11-18 18:25:12 +0000 | [diff] [blame] | 2875 | /* D-Form, X-Form */ |
| 2876 | UChar opc1 = ifieldOPC(theInstr); |
| 2877 | UChar crfD = toUChar( IFIELD( theInstr, 23, 3 ) ); |
| 2878 | UChar b22 = toUChar( IFIELD( theInstr, 22, 1 ) ); |
| 2879 | UChar flag_L = toUChar( IFIELD( theInstr, 21, 1 ) ); |
| 2880 | UChar rA_addr = ifieldRegA(theInstr); |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 2881 | UInt uimm16 = ifieldUIMM16(theInstr); |
cerion | 76de5cf | 2005-11-18 18:25:12 +0000 | [diff] [blame] | 2882 | UChar rB_addr = ifieldRegB(theInstr); |
| 2883 | UInt opc2 = ifieldOPClo10(theInstr); |
| 2884 | UChar b0 = ifieldBIT0(theInstr); |
cerion | 7aa4bbc | 2005-01-29 09:32:07 +0000 | [diff] [blame] | 2885 | |
cerion | bb01b7c | 2005-12-16 13:40:18 +0000 | [diff] [blame] | 2886 | IRType ty = mode64 ? Ity_I64 : Ity_I32; |
| 2887 | IRExpr *a = getIReg(rA_addr); |
| 2888 | IRExpr *b; |
cerion | 76de5cf | 2005-11-18 18:25:12 +0000 | [diff] [blame] | 2889 | |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 2890 | if (!mode64 && flag_L==1) { // L==1 invalid for 32 bit. |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 2891 | vex_printf("dis_int_cmp(ppc)(flag_L)\n"); |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 2892 | return False; |
| 2893 | } |
| 2894 | |
cerion | 76de5cf | 2005-11-18 18:25:12 +0000 | [diff] [blame] | 2895 | if (b22 != 0) { |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 2896 | vex_printf("dis_int_cmp(ppc)(b22)\n"); |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 2897 | return False; |
| 2898 | } |
| 2899 | |
| 2900 | switch (opc1) { |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 2901 | case 0x0B: // cmpi (Compare Immediate, PPC32 p368) |
| 2902 | DIP("cmpi cr%u,%u,r%u,%d\n", crfD, flag_L, rA_addr, |
| 2903 | (Int)extend_s_16to32(uimm16)); |
cerion | 2831b00 | 2005-11-30 19:55:22 +0000 | [diff] [blame] | 2904 | b = mkSzExtendS16( ty, uimm16 ); |
cerion | bb01b7c | 2005-12-16 13:40:18 +0000 | [diff] [blame] | 2905 | if (flag_L == 1) { |
cerion | 2831b00 | 2005-11-30 19:55:22 +0000 | [diff] [blame] | 2906 | putCR321(crfD, unop(Iop_64to8, binop(Iop_CmpORD64S, a, b))); |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 2907 | } else { |
cerion | bb01b7c | 2005-12-16 13:40:18 +0000 | [diff] [blame] | 2908 | a = mkSzNarrow32( ty, a ); |
| 2909 | b = mkSzNarrow32( ty, b ); |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 2910 | putCR321(crfD, unop(Iop_32to8, binop(Iop_CmpORD32S, a, b))); |
| 2911 | } |
| 2912 | putCR0( crfD, getXER_SO() ); |
| 2913 | break; |
| 2914 | |
| 2915 | case 0x0A: // cmpli (Compare Logical Immediate, PPC32 p370) |
| 2916 | DIP("cmpli cr%u,%u,r%u,0x%x\n", crfD, flag_L, rA_addr, uimm16); |
cerion | 2831b00 | 2005-11-30 19:55:22 +0000 | [diff] [blame] | 2917 | b = mkSzImm( ty, uimm16 ); |
cerion | bb01b7c | 2005-12-16 13:40:18 +0000 | [diff] [blame] | 2918 | if (flag_L == 1) { |
cerion | 2831b00 | 2005-11-30 19:55:22 +0000 | [diff] [blame] | 2919 | putCR321(crfD, unop(Iop_64to8, binop(Iop_CmpORD64U, a, b))); |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 2920 | } else { |
cerion | bb01b7c | 2005-12-16 13:40:18 +0000 | [diff] [blame] | 2921 | a = mkSzNarrow32( ty, a ); |
| 2922 | b = mkSzNarrow32( ty, b ); |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 2923 | putCR321(crfD, unop(Iop_32to8, binop(Iop_CmpORD32U, a, b))); |
| 2924 | } |
| 2925 | putCR0( crfD, getXER_SO() ); |
| 2926 | break; |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 2927 | |
| 2928 | /* X Form */ |
| 2929 | case 0x1F: |
| 2930 | if (b0 != 0) { |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 2931 | vex_printf("dis_int_cmp(ppc)(0x1F,b0)\n"); |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 2932 | return False; |
| 2933 | } |
cerion | bb01b7c | 2005-12-16 13:40:18 +0000 | [diff] [blame] | 2934 | b = getIReg(rB_addr); |
cerion | 7aa4bbc | 2005-01-29 09:32:07 +0000 | [diff] [blame] | 2935 | |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 2936 | switch (opc2) { |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 2937 | case 0x000: // cmp (Compare, PPC32 p367) |
| 2938 | DIP("cmp cr%u,%u,r%u,r%u\n", crfD, flag_L, rA_addr, rB_addr); |
sewardj | a9cb67b | 2006-08-19 18:31:53 +0000 | [diff] [blame] | 2939 | /* Comparing a reg with itself produces a result which |
| 2940 | doesn't depend on the contents of the reg. Therefore |
| 2941 | remove the false dependency, which has been known to cause |
| 2942 | memcheck to produce false errors. */ |
sewardj | 9195aa1 | 2006-08-19 22:18:53 +0000 | [diff] [blame] | 2943 | if (rA_addr == rB_addr) |
| 2944 | a = b = typeOfIRExpr(irbb->tyenv,a) == Ity_I64 |
| 2945 | ? mkU64(0) : mkU32(0); |
cerion | bb01b7c | 2005-12-16 13:40:18 +0000 | [diff] [blame] | 2946 | if (flag_L == 1) { |
| 2947 | putCR321(crfD, unop(Iop_64to8, binop(Iop_CmpORD64S, a, b))); |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 2948 | } else { |
cerion | bb01b7c | 2005-12-16 13:40:18 +0000 | [diff] [blame] | 2949 | a = mkSzNarrow32( ty, a ); |
| 2950 | b = mkSzNarrow32( ty, b ); |
| 2951 | putCR321(crfD, unop(Iop_32to8,binop(Iop_CmpORD32S, a, b))); |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 2952 | } |
| 2953 | putCR0( crfD, getXER_SO() ); |
| 2954 | break; |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 2955 | |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 2956 | case 0x020: // cmpl (Compare Logical, PPC32 p369) |
| 2957 | DIP("cmpl cr%u,%u,r%u,r%u\n", crfD, flag_L, rA_addr, rB_addr); |
sewardj | a9cb67b | 2006-08-19 18:31:53 +0000 | [diff] [blame] | 2958 | /* Comparing a reg with itself produces a result which |
| 2959 | doesn't depend on the contents of the reg. Therefore |
| 2960 | remove the false dependency, which has been known to cause |
| 2961 | memcheck to produce false errors. */ |
sewardj | 9195aa1 | 2006-08-19 22:18:53 +0000 | [diff] [blame] | 2962 | if (rA_addr == rB_addr) |
| 2963 | a = b = typeOfIRExpr(irbb->tyenv,a) == Ity_I64 |
| 2964 | ? mkU64(0) : mkU32(0); |
cerion | bb01b7c | 2005-12-16 13:40:18 +0000 | [diff] [blame] | 2965 | if (flag_L == 1) { |
| 2966 | putCR321(crfD, unop(Iop_64to8, binop(Iop_CmpORD64U, a, b))); |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 2967 | } else { |
cerion | bb01b7c | 2005-12-16 13:40:18 +0000 | [diff] [blame] | 2968 | a = mkSzNarrow32( ty, a ); |
| 2969 | b = mkSzNarrow32( ty, b ); |
| 2970 | putCR321(crfD, unop(Iop_32to8, binop(Iop_CmpORD32U, a, b))); |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 2971 | } |
| 2972 | putCR0( crfD, getXER_SO() ); |
| 2973 | break; |
cerion | 7aa4bbc | 2005-01-29 09:32:07 +0000 | [diff] [blame] | 2974 | |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 2975 | default: |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 2976 | vex_printf("dis_int_cmp(ppc)(opc2)\n"); |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 2977 | return False; |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 2978 | } |
| 2979 | break; |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 2980 | |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 2981 | default: |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 2982 | vex_printf("dis_int_cmp(ppc)(opc1)\n"); |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 2983 | return False; |
| 2984 | } |
| 2985 | |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 2986 | return True; |
cerion | 7aa4bbc | 2005-01-29 09:32:07 +0000 | [diff] [blame] | 2987 | } |
| 2988 | |
| 2989 | |
cerion | 3d870a3 | 2005-03-18 12:23:33 +0000 | [diff] [blame] | 2990 | /* |
| 2991 | Integer Logical Instructions |
| 2992 | */ |
cerion | 7aa4bbc | 2005-01-29 09:32:07 +0000 | [diff] [blame] | 2993 | static Bool dis_int_logic ( UInt theInstr ) |
| 2994 | { |
cerion | 76de5cf | 2005-11-18 18:25:12 +0000 | [diff] [blame] | 2995 | /* D-Form, X-Form */ |
| 2996 | UChar opc1 = ifieldOPC(theInstr); |
| 2997 | UChar rS_addr = ifieldRegDS(theInstr); |
| 2998 | UChar rA_addr = ifieldRegA(theInstr); |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 2999 | UInt uimm16 = ifieldUIMM16(theInstr); |
cerion | 76de5cf | 2005-11-18 18:25:12 +0000 | [diff] [blame] | 3000 | UChar rB_addr = ifieldRegB(theInstr); |
| 3001 | UInt opc2 = ifieldOPClo10(theInstr); |
| 3002 | UChar flag_rC = ifieldBIT0(theInstr); |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 3003 | |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 3004 | IRType ty = mode64 ? Ity_I64 : Ity_I32; |
| 3005 | IRTemp rS = newTemp(ty); |
| 3006 | IRTemp rA = newTemp(ty); |
| 3007 | IRTemp rB = newTemp(ty); |
cerion | e9d361a | 2005-03-04 17:35:29 +0000 | [diff] [blame] | 3008 | IRExpr* irx; |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 3009 | Bool do_rc = False; |
| 3010 | |
cerion | 76de5cf | 2005-11-18 18:25:12 +0000 | [diff] [blame] | 3011 | assign( rS, getIReg(rS_addr) ); |
| 3012 | assign( rB, getIReg(rB_addr) ); |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 3013 | |
| 3014 | switch (opc1) { |
cerion | e9d361a | 2005-03-04 17:35:29 +0000 | [diff] [blame] | 3015 | case 0x1C: // andi. (AND Immediate, PPC32 p358) |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 3016 | DIP("andi. r%u,r%u,0x%x\n", rA_addr, rS_addr, uimm16); |
cerion | 2831b00 | 2005-11-30 19:55:22 +0000 | [diff] [blame] | 3017 | assign( rA, binop( mkSzOp(ty, Iop_And8), mkexpr(rS), |
| 3018 | mkSzImm(ty, uimm16)) ); |
cerion | 70e2412 | 2005-03-16 00:27:37 +0000 | [diff] [blame] | 3019 | do_rc = True; // Always record to CR |
cerion | 76de5cf | 2005-11-18 18:25:12 +0000 | [diff] [blame] | 3020 | flag_rC = 1; |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 3021 | break; |
| 3022 | |
cerion | e9d361a | 2005-03-04 17:35:29 +0000 | [diff] [blame] | 3023 | case 0x1D: // andis. (AND Immediate Shifted, PPC32 p359) |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 3024 | DIP("andis r%u,r%u,0x%x\n", rA_addr, rS_addr, uimm16); |
cerion | 2831b00 | 2005-11-30 19:55:22 +0000 | [diff] [blame] | 3025 | assign( rA, binop( mkSzOp(ty, Iop_And8), mkexpr(rS), |
| 3026 | mkSzImm(ty, uimm16 << 16)) ); |
cerion | 70e2412 | 2005-03-16 00:27:37 +0000 | [diff] [blame] | 3027 | do_rc = True; // Always record to CR |
cerion | 76de5cf | 2005-11-18 18:25:12 +0000 | [diff] [blame] | 3028 | flag_rC = 1; |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 3029 | break; |
cerion | 7aa4bbc | 2005-01-29 09:32:07 +0000 | [diff] [blame] | 3030 | |
cerion | e9d361a | 2005-03-04 17:35:29 +0000 | [diff] [blame] | 3031 | case 0x18: // ori (OR Immediate, PPC32 p497) |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 3032 | DIP("ori r%u,r%u,0x%x\n", rA_addr, rS_addr, uimm16); |
cerion | 2831b00 | 2005-11-30 19:55:22 +0000 | [diff] [blame] | 3033 | assign( rA, binop( mkSzOp(ty, Iop_Or8), mkexpr(rS), |
| 3034 | mkSzImm(ty, uimm16)) ); |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 3035 | break; |
cerion | 7aa4bbc | 2005-01-29 09:32:07 +0000 | [diff] [blame] | 3036 | |
cerion | e9d361a | 2005-03-04 17:35:29 +0000 | [diff] [blame] | 3037 | case 0x19: // oris (OR Immediate Shifted, PPC32 p498) |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 3038 | DIP("oris r%u,r%u,0x%x\n", rA_addr, rS_addr, uimm16); |
cerion | 2831b00 | 2005-11-30 19:55:22 +0000 | [diff] [blame] | 3039 | assign( rA, binop( mkSzOp(ty, Iop_Or8), mkexpr(rS), |
| 3040 | mkSzImm(ty, uimm16 << 16)) ); |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 3041 | break; |
cerion | aabdfbf | 2005-01-29 12:56:15 +0000 | [diff] [blame] | 3042 | |
cerion | e9d361a | 2005-03-04 17:35:29 +0000 | [diff] [blame] | 3043 | case 0x1A: // xori (XOR Immediate, PPC32 p550) |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 3044 | DIP("xori r%u,r%u,0x%x\n", rA_addr, rS_addr, uimm16); |
cerion | 2831b00 | 2005-11-30 19:55:22 +0000 | [diff] [blame] | 3045 | assign( rA, binop( mkSzOp(ty, Iop_Xor8), mkexpr(rS), |
| 3046 | mkSzImm(ty, uimm16)) ); |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 3047 | break; |
cerion | 3867460 | 2005-02-08 02:19:25 +0000 | [diff] [blame] | 3048 | |
cerion | e9d361a | 2005-03-04 17:35:29 +0000 | [diff] [blame] | 3049 | case 0x1B: // xoris (XOR Immediate Shifted, PPC32 p551) |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 3050 | DIP("xoris r%u,r%u,0x%x\n", rA_addr, rS_addr, uimm16); |
cerion | 2831b00 | 2005-11-30 19:55:22 +0000 | [diff] [blame] | 3051 | assign( rA, binop( mkSzOp(ty, Iop_Xor8), mkexpr(rS), |
| 3052 | mkSzImm(ty, uimm16 << 16)) ); |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 3053 | break; |
cerion | aabdfbf | 2005-01-29 12:56:15 +0000 | [diff] [blame] | 3054 | |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 3055 | /* X Form */ |
| 3056 | case 0x1F: |
cerion | 70e2412 | 2005-03-16 00:27:37 +0000 | [diff] [blame] | 3057 | do_rc = True; // All below record to CR |
| 3058 | |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 3059 | switch (opc2) { |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 3060 | case 0x01C: // and (AND, PPC32 p356) |
| 3061 | DIP("and%s r%u,r%u,r%u\n", |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 3062 | flag_rC ? ".":"", rA_addr, rS_addr, rB_addr); |
cerion | 2831b00 | 2005-11-30 19:55:22 +0000 | [diff] [blame] | 3063 | assign(rA, binop( mkSzOp(ty, Iop_And8), |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 3064 | mkexpr(rS), mkexpr(rB))); |
| 3065 | break; |
| 3066 | |
| 3067 | case 0x03C: // andc (AND with Complement, PPC32 p357) |
| 3068 | DIP("andc%s r%u,r%u,r%u\n", |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 3069 | flag_rC ? ".":"", rA_addr, rS_addr, rB_addr); |
cerion | 2831b00 | 2005-11-30 19:55:22 +0000 | [diff] [blame] | 3070 | assign(rA, binop( mkSzOp(ty, Iop_And8), mkexpr(rS), |
| 3071 | unop( mkSzOp(ty, Iop_Not8), |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 3072 | mkexpr(rB)))); |
| 3073 | break; |
| 3074 | |
| 3075 | case 0x01A: { // cntlzw (Count Leading Zeros Word, PPC32 p371) |
| 3076 | IRExpr* lo32; |
| 3077 | if (rB_addr!=0) { |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 3078 | vex_printf("dis_int_logic(ppc)(cntlzw,rB_addr)\n"); |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 3079 | return False; |
| 3080 | } |
| 3081 | DIP("cntlzw%s r%u,r%u\n", |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 3082 | flag_rC ? ".":"", rA_addr, rS_addr); |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 3083 | |
| 3084 | // mode64: count in low word only |
| 3085 | lo32 = mode64 ? unop(Iop_64to32, mkexpr(rS)) : mkexpr(rS); |
| 3086 | |
| 3087 | // Iop_Clz32 undefined for arg==0, so deal with that case: |
| 3088 | irx = binop(Iop_CmpNE32, lo32, mkU32(0)); |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 3089 | assign(rA, mkSzWiden32(ty, |
| 3090 | IRExpr_Mux0X( unop(Iop_1Uto8, irx), |
| 3091 | mkU32(32), |
| 3092 | unop(Iop_Clz32, lo32)), |
| 3093 | False)); |
| 3094 | |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 3095 | // TODO: alternatively: assign(rA, verbose_Clz32(rS)); |
| 3096 | break; |
| 3097 | } |
| 3098 | |
| 3099 | case 0x11C: // eqv (Equivalent, PPC32 p396) |
| 3100 | DIP("eqv%s r%u,r%u,r%u\n", |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 3101 | flag_rC ? ".":"", rA_addr, rS_addr, rB_addr); |
cerion | 2831b00 | 2005-11-30 19:55:22 +0000 | [diff] [blame] | 3102 | assign( rA, unop( mkSzOp(ty, Iop_Not8), |
| 3103 | binop( mkSzOp(ty, Iop_Xor8), |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 3104 | mkexpr(rS), mkexpr(rB))) ); |
sewardj | 20ef547 | 2005-07-21 14:48:31 +0000 | [diff] [blame] | 3105 | break; |
cerion | 7aa4bbc | 2005-01-29 09:32:07 +0000 | [diff] [blame] | 3106 | |
cerion | e9d361a | 2005-03-04 17:35:29 +0000 | [diff] [blame] | 3107 | case 0x3BA: // extsb (Extend Sign Byte, PPC32 p397 |
cerion | 76de5cf | 2005-11-18 18:25:12 +0000 | [diff] [blame] | 3108 | if (rB_addr!=0) { |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 3109 | vex_printf("dis_int_logic(ppc)(extsb,rB_addr)\n"); |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 3110 | return False; |
| 3111 | } |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 3112 | DIP("extsb%s r%u,r%u\n", |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 3113 | flag_rC ? ".":"", rA_addr, rS_addr); |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 3114 | if (mode64) |
| 3115 | assign( rA, unop(Iop_8Sto64, unop(Iop_64to8, mkexpr(rS))) ); |
| 3116 | else |
| 3117 | assign( rA, unop(Iop_8Sto32, unop(Iop_32to8, mkexpr(rS))) ); |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 3118 | break; |
cerion | 7aa4bbc | 2005-01-29 09:32:07 +0000 | [diff] [blame] | 3119 | |
cerion | e9d361a | 2005-03-04 17:35:29 +0000 | [diff] [blame] | 3120 | case 0x39A: // extsh (Extend Sign Half Word, PPC32 p398) |
cerion | 76de5cf | 2005-11-18 18:25:12 +0000 | [diff] [blame] | 3121 | if (rB_addr!=0) { |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 3122 | vex_printf("dis_int_logic(ppc)(extsh,rB_addr)\n"); |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 3123 | return False; |
| 3124 | } |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 3125 | DIP("extsh%s r%u,r%u\n", |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 3126 | flag_rC ? ".":"", rA_addr, rS_addr); |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 3127 | if (mode64) |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 3128 | assign( rA, unop(Iop_16Sto64, |
| 3129 | unop(Iop_64to16, mkexpr(rS))) ); |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 3130 | else |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 3131 | assign( rA, unop(Iop_16Sto32, |
| 3132 | unop(Iop_32to16, mkexpr(rS))) ); |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 3133 | break; |
cerion | 7aa4bbc | 2005-01-29 09:32:07 +0000 | [diff] [blame] | 3134 | |
cerion | e9d361a | 2005-03-04 17:35:29 +0000 | [diff] [blame] | 3135 | case 0x1DC: // nand (NAND, PPC32 p492) |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 3136 | DIP("nand%s r%u,r%u,r%u\n", |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 3137 | flag_rC ? ".":"", rA_addr, rS_addr, rB_addr); |
cerion | 2831b00 | 2005-11-30 19:55:22 +0000 | [diff] [blame] | 3138 | assign( rA, unop( mkSzOp(ty, Iop_Not8), |
| 3139 | binop( mkSzOp(ty, Iop_And8), |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 3140 | mkexpr(rS), mkexpr(rB))) ); |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 3141 | break; |
| 3142 | |
cerion | e9d361a | 2005-03-04 17:35:29 +0000 | [diff] [blame] | 3143 | case 0x07C: // nor (NOR, PPC32 p494) |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 3144 | DIP("nor%s r%u,r%u,r%u\n", |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 3145 | flag_rC ? ".":"", rA_addr, rS_addr, rB_addr); |
cerion | 2831b00 | 2005-11-30 19:55:22 +0000 | [diff] [blame] | 3146 | assign( rA, unop( mkSzOp(ty, Iop_Not8), |
| 3147 | binop( mkSzOp(ty, Iop_Or8), |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 3148 | mkexpr(rS), mkexpr(rB))) ); |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 3149 | break; |
cerion | 7aa4bbc | 2005-01-29 09:32:07 +0000 | [diff] [blame] | 3150 | |
cerion | e9d361a | 2005-03-04 17:35:29 +0000 | [diff] [blame] | 3151 | case 0x1BC: // or (OR, PPC32 p495) |
cerion | 76de5cf | 2005-11-18 18:25:12 +0000 | [diff] [blame] | 3152 | if ((!flag_rC) && rS_addr == rB_addr) { |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 3153 | DIP("mr r%u,r%u\n", rA_addr, rS_addr); |
cerion | 76de5cf | 2005-11-18 18:25:12 +0000 | [diff] [blame] | 3154 | assign( rA, mkexpr(rS) ); |
sewardj | b51f0f4 | 2005-07-18 11:38:02 +0000 | [diff] [blame] | 3155 | } else { |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 3156 | DIP("or%s r%u,r%u,r%u\n", |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 3157 | flag_rC ? ".":"", rA_addr, rS_addr, rB_addr); |
cerion | 2831b00 | 2005-11-30 19:55:22 +0000 | [diff] [blame] | 3158 | assign( rA, binop( mkSzOp(ty, Iop_Or8), |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 3159 | mkexpr(rS), mkexpr(rB)) ); |
sewardj | b51f0f4 | 2005-07-18 11:38:02 +0000 | [diff] [blame] | 3160 | } |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 3161 | break; |
cerion | 7aa4bbc | 2005-01-29 09:32:07 +0000 | [diff] [blame] | 3162 | |
cerion | e9d361a | 2005-03-04 17:35:29 +0000 | [diff] [blame] | 3163 | case 0x19C: // orc (OR with Complement, PPC32 p496) |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 3164 | DIP("orc%s r%u,r%u,r%u\n", |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 3165 | flag_rC ? ".":"", rA_addr, rS_addr, rB_addr); |
cerion | 2831b00 | 2005-11-30 19:55:22 +0000 | [diff] [blame] | 3166 | assign( rA, binop( mkSzOp(ty, Iop_Or8), mkexpr(rS), |
| 3167 | unop(mkSzOp(ty, Iop_Not8), mkexpr(rB)))); |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 3168 | break; |
| 3169 | |
cerion | e9d361a | 2005-03-04 17:35:29 +0000 | [diff] [blame] | 3170 | case 0x13C: // xor (XOR, PPC32 p549) |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 3171 | DIP("xor%s r%u,r%u,r%u\n", |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 3172 | flag_rC ? ".":"", rA_addr, rS_addr, rB_addr); |
cerion | 2831b00 | 2005-11-30 19:55:22 +0000 | [diff] [blame] | 3173 | assign( rA, binop( mkSzOp(ty, Iop_Xor8), |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 3174 | mkexpr(rS), mkexpr(rB)) ); |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 3175 | break; |
cerion | 7aa4bbc | 2005-01-29 09:32:07 +0000 | [diff] [blame] | 3176 | |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 3177 | |
| 3178 | /* 64bit Integer Logical Instructions */ |
| 3179 | case 0x3DA: // extsw (Extend Sign Word, PPC64 p430) |
| 3180 | if (rB_addr!=0) { |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 3181 | vex_printf("dis_int_logic(ppc)(extsw,rB_addr)\n"); |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 3182 | return False; |
| 3183 | } |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 3184 | DIP("extsw%s r%u,r%u\n", flag_rC ? ".":"", rA_addr, rS_addr); |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 3185 | assign(rA, unop(Iop_32Sto64, unop(Iop_64to32, mkexpr(rS)))); |
| 3186 | break; |
| 3187 | |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 3188 | case 0x03A: // cntlzd (Count Leading Zeros DWord, PPC64 p401) |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 3189 | if (rB_addr!=0) { |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 3190 | vex_printf("dis_int_logic(ppc)(cntlzd,rB_addr)\n"); |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 3191 | return False; |
| 3192 | } |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 3193 | DIP("cntlzd%s r%u,r%u\n", |
| 3194 | flag_rC ? ".":"", rA_addr, rS_addr); |
cerion | 07b07a9 | 2005-12-22 14:32:35 +0000 | [diff] [blame] | 3195 | // Iop_Clz64 undefined for arg==0, so deal with that case: |
| 3196 | irx = binop(Iop_CmpNE64, mkexpr(rS), mkU64(0)); |
| 3197 | assign(rA, IRExpr_Mux0X( unop(Iop_1Uto8, irx), |
| 3198 | mkU64(64), |
| 3199 | unop(Iop_Clz64, mkexpr(rS)) )); |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 3200 | // TODO: alternatively: assign(rA, verbose_Clz64(rS)); |
cerion | 07b07a9 | 2005-12-22 14:32:35 +0000 | [diff] [blame] | 3201 | break; |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 3202 | |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 3203 | default: |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 3204 | vex_printf("dis_int_logic(ppc)(opc2)\n"); |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 3205 | return False; |
| 3206 | } |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 3207 | break; |
| 3208 | |
| 3209 | default: |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 3210 | vex_printf("dis_int_logic(ppc)(opc1)\n"); |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 3211 | return False; |
| 3212 | } |
cerion | 70e2412 | 2005-03-16 00:27:37 +0000 | [diff] [blame] | 3213 | |
cerion | 76de5cf | 2005-11-18 18:25:12 +0000 | [diff] [blame] | 3214 | putIReg( rA_addr, mkexpr(rA) ); |
| 3215 | |
| 3216 | if (do_rc && flag_rC) { |
| 3217 | set_CR0( mkexpr(rA) ); |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 3218 | } |
| 3219 | return True; |
cerion | 645c930 | 2005-01-31 10:09:59 +0000 | [diff] [blame] | 3220 | } |
| 3221 | |
| 3222 | |
| 3223 | |
cerion | 3d870a3 | 2005-03-18 12:23:33 +0000 | [diff] [blame] | 3224 | /* |
| 3225 | Integer Rotate Instructions |
| 3226 | */ |
cerion | 645c930 | 2005-01-31 10:09:59 +0000 | [diff] [blame] | 3227 | static Bool dis_int_rot ( UInt theInstr ) |
| 3228 | { |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 3229 | /* M-Form, MDS-Form */ |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 3230 | UChar opc1 = ifieldOPC(theInstr); |
| 3231 | UChar rS_addr = ifieldRegDS(theInstr); |
| 3232 | UChar rA_addr = ifieldRegA(theInstr); |
| 3233 | UChar rB_addr = ifieldRegB(theInstr); |
| 3234 | UChar sh_imm = rB_addr; |
| 3235 | UChar MaskBeg = toUChar( IFIELD( theInstr, 6, 5 ) ); |
| 3236 | UChar MaskEnd = toUChar( IFIELD( theInstr, 1, 5 ) ); |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 3237 | UChar msk_imm = toUChar( IFIELD( theInstr, 5, 6 ) ); |
| 3238 | UChar opc2 = toUChar( IFIELD( theInstr, 2, 3 ) ); |
| 3239 | UChar b1 = ifieldBIT1(theInstr); |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 3240 | UChar flag_rC = ifieldBIT0(theInstr); |
cerion | 76de5cf | 2005-11-18 18:25:12 +0000 | [diff] [blame] | 3241 | |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 3242 | IRType ty = mode64 ? Ity_I64 : Ity_I32; |
| 3243 | IRTemp rS = newTemp(ty); |
| 3244 | IRTemp rA = newTemp(ty); |
| 3245 | IRTemp rB = newTemp(ty); |
cerion | bb01b7c | 2005-12-16 13:40:18 +0000 | [diff] [blame] | 3246 | IRTemp rot = newTemp(ty); |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 3247 | IRExpr *r; |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 3248 | UInt mask32; |
| 3249 | ULong mask64; |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 3250 | |
cerion | 76de5cf | 2005-11-18 18:25:12 +0000 | [diff] [blame] | 3251 | assign( rS, getIReg(rS_addr) ); |
| 3252 | assign( rB, getIReg(rB_addr) ); |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 3253 | |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 3254 | switch (opc1) { |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 3255 | case 0x14: { |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 3256 | // rlwimi (Rotate Left Word Imm then Mask Insert, PPC32 p500) |
| 3257 | DIP("rlwimi%s r%u,r%u,%d,%d,%d\n", flag_rC ? ".":"", |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 3258 | rA_addr, rS_addr, sh_imm, MaskBeg, MaskEnd); |
| 3259 | if (mode64) { |
| 3260 | // tmp32 = (ROTL(rS_Lo32, Imm) |
| 3261 | // rA = ((tmp32 || tmp32) & mask64) | (rA & ~mask64) |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 3262 | mask64 = MASK64(31-MaskEnd, 31-MaskBeg); |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 3263 | r = ROTL( unop(Iop_64to32, mkexpr(rS) ), mkU8(sh_imm) ); |
| 3264 | r = unop(Iop_32Uto64, r); |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 3265 | assign( rot, binop(Iop_Or64, r, |
| 3266 | binop(Iop_Shl64, r, mkU8(32))) ); |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 3267 | assign( rA, |
| 3268 | binop(Iop_Or64, |
cerion | bb01b7c | 2005-12-16 13:40:18 +0000 | [diff] [blame] | 3269 | binop(Iop_And64, mkexpr(rot), mkU64(mask64)), |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 3270 | binop(Iop_And64, getIReg(rA_addr), mkU64(~mask64))) ); |
sewardj | 26b3320 | 2005-10-07 09:45:16 +0000 | [diff] [blame] | 3271 | } |
| 3272 | else { |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 3273 | // rA = (ROTL(rS, Imm) & mask) | (rA & ~mask); |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 3274 | mask32 = MASK32(31-MaskEnd, 31-MaskBeg); |
| 3275 | r = ROTL(mkexpr(rS), mkU8(sh_imm)); |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 3276 | assign( rA, |
| 3277 | binop(Iop_Or32, |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 3278 | binop(Iop_And32, mkU32(mask32), r), |
| 3279 | binop(Iop_And32, getIReg(rA_addr), mkU32(~mask32))) ); |
sewardj | 26b3320 | 2005-10-07 09:45:16 +0000 | [diff] [blame] | 3280 | } |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 3281 | break; |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 3282 | } |
cerion | 45b70ff | 2005-01-31 17:03:25 +0000 | [diff] [blame] | 3283 | |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 3284 | case 0x15: { |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 3285 | // rlwinm (Rotate Left Word Imm then AND with Mask, PPC32 p501) |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 3286 | vassert(MaskBeg < 32); |
| 3287 | vassert(MaskEnd < 32); |
| 3288 | vassert(sh_imm < 32); |
| 3289 | |
| 3290 | if (mode64) { |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 3291 | mask64 = MASK64(31-MaskEnd, 31-MaskBeg); |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 3292 | DIP("rlwinm%s r%u,r%u,%d,%d,%d\n", flag_rC ? ".":"", |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 3293 | rA_addr, rS_addr, sh_imm, MaskBeg, MaskEnd); |
| 3294 | // tmp32 = (ROTL(rS_Lo32, Imm) |
| 3295 | // rA = ((tmp32 || tmp32) & mask64) |
| 3296 | r = ROTL( unop(Iop_64to32, mkexpr(rS) ), mkU8(sh_imm) ); |
| 3297 | r = unop(Iop_32Uto64, r); |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 3298 | assign( rot, binop(Iop_Or64, r, |
| 3299 | binop(Iop_Shl64, r, mkU8(32))) ); |
cerion | bb01b7c | 2005-12-16 13:40:18 +0000 | [diff] [blame] | 3300 | assign( rA, binop(Iop_And64, mkexpr(rot), mkU64(mask64)) ); |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 3301 | } |
| 3302 | else { |
| 3303 | if (MaskBeg == 0 && sh_imm+MaskEnd == 31) { |
| 3304 | /* Special-case the ,n,0,31-n form as that is just n-bit |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 3305 | shift left, PPC32 p501 */ |
| 3306 | DIP("slwi%s r%u,r%u,%d\n", flag_rC ? ".":"", |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 3307 | rA_addr, rS_addr, sh_imm); |
| 3308 | assign( rA, binop(Iop_Shl32, mkexpr(rS), mkU8(sh_imm)) ); |
| 3309 | } |
cerion | 2831b00 | 2005-11-30 19:55:22 +0000 | [diff] [blame] | 3310 | else if (MaskEnd == 31 && sh_imm+MaskBeg == 32) { |
| 3311 | /* Special-case the ,32-n,n,31 form as that is just n-bit |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 3312 | unsigned shift right, PPC32 p501 */ |
| 3313 | DIP("srwi%s r%u,r%u,%d\n", flag_rC ? ".":"", |
cerion | 2831b00 | 2005-11-30 19:55:22 +0000 | [diff] [blame] | 3314 | rA_addr, rS_addr, sh_imm); |
| 3315 | assign( rA, binop(Iop_Shr32, mkexpr(rS), mkU8(MaskBeg)) ); |
| 3316 | } |
| 3317 | else { |
| 3318 | /* General case. */ |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 3319 | mask32 = MASK32(31-MaskEnd, 31-MaskBeg); |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 3320 | DIP("rlwinm%s r%u,r%u,%d,%d,%d\n", flag_rC ? ".":"", |
cerion | 2831b00 | 2005-11-30 19:55:22 +0000 | [diff] [blame] | 3321 | rA_addr, rS_addr, sh_imm, MaskBeg, MaskEnd); |
| 3322 | // rA = ROTL(rS, Imm) & mask |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 3323 | assign( rA, binop(Iop_And32, |
| 3324 | ROTL(mkexpr(rS), mkU8(sh_imm)), |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 3325 | mkU32(mask32)) ); |
cerion | 2831b00 | 2005-11-30 19:55:22 +0000 | [diff] [blame] | 3326 | } |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 3327 | } |
sewardj | c965953 | 2005-07-21 21:33:57 +0000 | [diff] [blame] | 3328 | break; |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 3329 | } |
| 3330 | |
| 3331 | case 0x17: { |
| 3332 | // rlwnm (Rotate Left Word then AND with Mask, PPC32 p503 |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 3333 | DIP("rlwnm%s r%u,r%u,r%u,%d,%d\n", flag_rC ? ".":"", |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 3334 | rA_addr, rS_addr, rB_addr, MaskBeg, MaskEnd); |
| 3335 | if (mode64) { |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 3336 | mask64 = MASK64(31-MaskEnd, 31-MaskBeg); |
cerion | bb01b7c | 2005-12-16 13:40:18 +0000 | [diff] [blame] | 3337 | /* weird insn alert! |
| 3338 | tmp32 = (ROTL(rS_Lo32, rB[0-4]) |
| 3339 | rA = ((tmp32 || tmp32) & mask64) |
| 3340 | */ |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 3341 | // note, ROTL does the masking, so we don't do it here |
| 3342 | r = ROTL( unop(Iop_64to32, mkexpr(rS)), |
cerion | bb01b7c | 2005-12-16 13:40:18 +0000 | [diff] [blame] | 3343 | unop(Iop_64to8, mkexpr(rB)) ); |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 3344 | r = unop(Iop_32Uto64, r); |
cerion | bb01b7c | 2005-12-16 13:40:18 +0000 | [diff] [blame] | 3345 | assign(rot, binop(Iop_Or64, r, binop(Iop_Shl64, r, mkU8(32)))); |
| 3346 | assign( rA, binop(Iop_And64, mkexpr(rot), mkU64(mask64)) ); |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 3347 | } else { |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 3348 | mask32 = MASK32(31-MaskEnd, 31-MaskBeg); |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 3349 | // rA = ROTL(rS, rB[0-4]) & mask |
| 3350 | // note, ROTL does the masking, so we don't do it here |
| 3351 | assign( rA, binop(Iop_And32, |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 3352 | ROTL(mkexpr(rS), |
| 3353 | unop(Iop_32to8, mkexpr(rB))), |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 3354 | mkU32(mask32)) ); |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 3355 | } |
| 3356 | break; |
| 3357 | } |
cerion | 45b70ff | 2005-01-31 17:03:25 +0000 | [diff] [blame] | 3358 | |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 3359 | |
| 3360 | /* 64bit Integer Rotates */ |
| 3361 | case 0x1E: { |
| 3362 | msk_imm = ((msk_imm & 1) << 5) | (msk_imm >> 1); |
| 3363 | sh_imm |= b1 << 5; |
| 3364 | |
| 3365 | vassert( msk_imm < 64 ); |
| 3366 | vassert( sh_imm < 64 ); |
| 3367 | |
| 3368 | switch (opc2) { |
cerion | 07b07a9 | 2005-12-22 14:32:35 +0000 | [diff] [blame] | 3369 | case 0x4: { |
| 3370 | /* r = ROTL64( rS, rB_lo6) */ |
| 3371 | r = ROTL( mkexpr(rS), unop(Iop_64to8, mkexpr(rB)) ); |
| 3372 | |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 3373 | if (b1 == 0) { // rldcl (Rotl DWord, Clear Left, PPC64 p555) |
| 3374 | DIP("rldcl%s r%u,r%u,r%u,%u\n", flag_rC ? ".":"", |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 3375 | rA_addr, rS_addr, rB_addr, msk_imm); |
cerion | 07b07a9 | 2005-12-22 14:32:35 +0000 | [diff] [blame] | 3376 | // note, ROTL does the masking, so we don't do it here |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 3377 | mask64 = MASK64(0, 63-msk_imm); |
| 3378 | assign( rA, binop(Iop_And64, r, mkU64(mask64)) ); |
| 3379 | break; |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 3380 | } else { // rldcr (Rotl DWord, Clear Right, PPC64 p556) |
| 3381 | DIP("rldcr%s r%u,r%u,r%u,%u\n", flag_rC ? ".":"", |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 3382 | rA_addr, rS_addr, rB_addr, msk_imm); |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 3383 | mask64 = MASK64(63-msk_imm, 63); |
| 3384 | assign( rA, binop(Iop_And64, r, mkU64(mask64)) ); |
| 3385 | break; |
| 3386 | } |
| 3387 | break; |
cerion | 07b07a9 | 2005-12-22 14:32:35 +0000 | [diff] [blame] | 3388 | } |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 3389 | case 0x2: // rldic (Rotl DWord Imm, Clear, PPC64 p557) |
| 3390 | DIP("rldic%s r%u,r%u,%u,%u\n", flag_rC ? ".":"", |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 3391 | rA_addr, rS_addr, sh_imm, msk_imm); |
| 3392 | r = ROTL(mkexpr(rS), mkU8(sh_imm)); |
| 3393 | mask64 = MASK64(sh_imm, 63-msk_imm); |
| 3394 | assign( rA, binop(Iop_And64, r, mkU64(mask64)) ); |
| 3395 | break; |
| 3396 | // later: deal with special case: (msk_imm==0) => SHL(sh_imm) |
| 3397 | /* |
| 3398 | Hmm... looks like this'll do the job more simply: |
| 3399 | r = SHL(rS, sh_imm) |
| 3400 | m = ~(1 << (63-msk_imm)) |
| 3401 | assign(rA, r & m); |
| 3402 | */ |
| 3403 | |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 3404 | case 0x0: // rldicl (Rotl DWord Imm, Clear Left, PPC64 p558) |
| 3405 | DIP("rldicl%s r%u,r%u,%u,%u\n", flag_rC ? ".":"", |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 3406 | rA_addr, rS_addr, sh_imm, msk_imm); |
| 3407 | r = ROTL(mkexpr(rS), mkU8(sh_imm)); |
| 3408 | mask64 = MASK64(0, 63-msk_imm); |
| 3409 | assign( rA, binop(Iop_And64, r, mkU64(mask64)) ); |
| 3410 | break; |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 3411 | /* later: deal with special case: |
| 3412 | (msk_imm + sh_imm == 63) => SHR(63 - sh_imm) */ |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 3413 | |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 3414 | case 0x1: // rldicr (Rotl DWord Imm, Clear Right, PPC64 p559) |
| 3415 | DIP("rldicr%s r%u,r%u,%u,%u\n", flag_rC ? ".":"", |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 3416 | rA_addr, rS_addr, sh_imm, msk_imm); |
| 3417 | r = ROTL(mkexpr(rS), mkU8(sh_imm)); |
| 3418 | mask64 = MASK64(63-msk_imm, 63); |
| 3419 | assign( rA, binop(Iop_And64, r, mkU64(mask64)) ); |
| 3420 | break; |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 3421 | /* later: deal with special case: |
| 3422 | (msk_imm == sh_imm) => SHL(sh_imm) */ |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 3423 | |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 3424 | case 0x3: { // rldimi (Rotl DWord Imm, Mask Insert, PPC64 p560) |
cerion | 07b07a9 | 2005-12-22 14:32:35 +0000 | [diff] [blame] | 3425 | IRTemp rA_orig = newTemp(ty); |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 3426 | DIP("rldimi%s r%u,r%u,%u,%u\n", flag_rC ? ".":"", |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 3427 | rA_addr, rS_addr, sh_imm, msk_imm); |
| 3428 | r = ROTL(mkexpr(rS), mkU8(sh_imm)); |
| 3429 | mask64 = MASK64(sh_imm, 63-msk_imm); |
cerion | 07b07a9 | 2005-12-22 14:32:35 +0000 | [diff] [blame] | 3430 | assign( rA_orig, getIReg(rA_addr) ); |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 3431 | assign( rA, binop(Iop_Or64, |
| 3432 | binop(Iop_And64, mkU64(mask64), r), |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 3433 | binop(Iop_And64, mkU64(~mask64), |
| 3434 | mkexpr(rA_orig))) ); |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 3435 | break; |
cerion | 07b07a9 | 2005-12-22 14:32:35 +0000 | [diff] [blame] | 3436 | } |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 3437 | default: |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 3438 | vex_printf("dis_int_rot(ppc)(opc2)\n"); |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 3439 | return False; |
| 3440 | } |
| 3441 | break; |
| 3442 | } |
| 3443 | |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 3444 | default: |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 3445 | vex_printf("dis_int_rot(ppc)(opc1)\n"); |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 3446 | return False; |
| 3447 | } |
cerion | 645c930 | 2005-01-31 10:09:59 +0000 | [diff] [blame] | 3448 | |
cerion | 76de5cf | 2005-11-18 18:25:12 +0000 | [diff] [blame] | 3449 | putIReg( rA_addr, mkexpr(rA) ); |
| 3450 | |
| 3451 | if (flag_rC) { |
| 3452 | set_CR0( mkexpr(rA) ); |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 3453 | } |
| 3454 | return True; |
cerion | 645c930 | 2005-01-31 10:09:59 +0000 | [diff] [blame] | 3455 | } |
| 3456 | |
| 3457 | |
cerion | 3d870a3 | 2005-03-18 12:23:33 +0000 | [diff] [blame] | 3458 | /* |
| 3459 | Integer Load Instructions |
| 3460 | */ |
cerion | 645c930 | 2005-01-31 10:09:59 +0000 | [diff] [blame] | 3461 | static Bool dis_int_load ( UInt theInstr ) |
| 3462 | { |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 3463 | /* D-Form, X-Form, DS-Form */ |
cerion | 76de5cf | 2005-11-18 18:25:12 +0000 | [diff] [blame] | 3464 | UChar opc1 = ifieldOPC(theInstr); |
| 3465 | UChar rD_addr = ifieldRegDS(theInstr); |
| 3466 | UChar rA_addr = ifieldRegA(theInstr); |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 3467 | UInt uimm16 = ifieldUIMM16(theInstr); |
cerion | 76de5cf | 2005-11-18 18:25:12 +0000 | [diff] [blame] | 3468 | UChar rB_addr = ifieldRegB(theInstr); |
| 3469 | UInt opc2 = ifieldOPClo10(theInstr); |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 3470 | UChar b1 = ifieldBIT1(theInstr); |
cerion | 76de5cf | 2005-11-18 18:25:12 +0000 | [diff] [blame] | 3471 | UChar b0 = ifieldBIT0(theInstr); |
| 3472 | |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 3473 | Int simm16 = extend_s_16to32(uimm16); |
| 3474 | IRType ty = mode64 ? Ity_I64 : Ity_I32; |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 3475 | IRTemp EA = newTemp(ty); |
| 3476 | IRExpr* val; |
cerion | edf7fc5 | 2005-11-18 20:57:41 +0000 | [diff] [blame] | 3477 | |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 3478 | switch (opc1) { |
| 3479 | case 0x1F: // register offset |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 3480 | assign( EA, ea_rAor0_idxd( rA_addr, rB_addr ) ); |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 3481 | break; |
| 3482 | case 0x3A: // immediate offset: 64bit |
| 3483 | simm16 = simm16 & 0xFFFFFFFC; |
| 3484 | default: // immediate offset |
| 3485 | assign( EA, ea_rAor0_simm( rA_addr, simm16 ) ); |
| 3486 | break; |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 3487 | } |
cerion | e9d361a | 2005-03-04 17:35:29 +0000 | [diff] [blame] | 3488 | |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 3489 | switch (opc1) { |
cerion | e9d361a | 2005-03-04 17:35:29 +0000 | [diff] [blame] | 3490 | case 0x22: // lbz (Load B & Zero, PPC32 p433) |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 3491 | DIP("lbz r%u,%d(r%u)\n", rD_addr, (Int)simm16, rA_addr); |
| 3492 | val = loadBE(Ity_I8, mkexpr(EA)); |
cerion | 2831b00 | 2005-11-30 19:55:22 +0000 | [diff] [blame] | 3493 | putIReg( rD_addr, mkSzWiden8(ty, val, False) ); |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 3494 | break; |
| 3495 | |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 3496 | case 0x23: // lbzu (Load B & Zero, Update, PPC32 p434) |
cerion | 76de5cf | 2005-11-18 18:25:12 +0000 | [diff] [blame] | 3497 | if (rA_addr == 0 || rA_addr == rD_addr) { |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 3498 | vex_printf("dis_int_load(ppc)(lbzu,rA_addr|rD_addr)\n"); |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 3499 | return False; |
| 3500 | } |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 3501 | DIP("lbzu r%u,%d(r%u)\n", rD_addr, (Int)simm16, rA_addr); |
| 3502 | val = loadBE(Ity_I8, mkexpr(EA)); |
cerion | 2831b00 | 2005-11-30 19:55:22 +0000 | [diff] [blame] | 3503 | putIReg( rD_addr, mkSzWiden8(ty, val, False) ); |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 3504 | putIReg( rA_addr, mkexpr(EA) ); |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 3505 | break; |
| 3506 | |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 3507 | case 0x2A: // lha (Load HW Alg, PPC32 p445) |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 3508 | DIP("lha r%u,%d(r%u)\n", rD_addr, (Int)simm16, rA_addr); |
| 3509 | val = loadBE(Ity_I16, mkexpr(EA)); |
cerion | 2831b00 | 2005-11-30 19:55:22 +0000 | [diff] [blame] | 3510 | putIReg( rD_addr, mkSzWiden16(ty, val, True) ); |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 3511 | break; |
cerion | 645c930 | 2005-01-31 10:09:59 +0000 | [diff] [blame] | 3512 | |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 3513 | case 0x2B: // lhau (Load HW Alg, Update, PPC32 p446) |
cerion | 76de5cf | 2005-11-18 18:25:12 +0000 | [diff] [blame] | 3514 | if (rA_addr == 0 || rA_addr == rD_addr) { |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 3515 | vex_printf("dis_int_load(ppc)(lhau,rA_addr|rD_addr)\n"); |
cerion | cb14e73 | 2005-09-09 16:38:19 +0000 | [diff] [blame] | 3516 | return False; |
| 3517 | } |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 3518 | DIP("lhau r%u,%d(r%u)\n", rD_addr, (Int)simm16, rA_addr); |
| 3519 | val = loadBE(Ity_I16, mkexpr(EA)); |
cerion | 2831b00 | 2005-11-30 19:55:22 +0000 | [diff] [blame] | 3520 | putIReg( rD_addr, mkSzWiden16(ty, val, True) ); |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 3521 | putIReg( rA_addr, mkexpr(EA) ); |
cerion | cb14e73 | 2005-09-09 16:38:19 +0000 | [diff] [blame] | 3522 | break; |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 3523 | |
cerion | e9d361a | 2005-03-04 17:35:29 +0000 | [diff] [blame] | 3524 | case 0x28: // lhz (Load HW & Zero, PPC32 p450) |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 3525 | DIP("lhz r%u,%d(r%u)\n", rD_addr, (Int)simm16, rA_addr); |
| 3526 | val = loadBE(Ity_I16, mkexpr(EA)); |
cerion | 2831b00 | 2005-11-30 19:55:22 +0000 | [diff] [blame] | 3527 | putIReg( rD_addr, mkSzWiden16(ty, val, False) ); |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 3528 | break; |
| 3529 | |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 3530 | case 0x29: // lhzu (Load HW & and Zero, Update, PPC32 p451) |
cerion | 76de5cf | 2005-11-18 18:25:12 +0000 | [diff] [blame] | 3531 | if (rA_addr == 0 || rA_addr == rD_addr) { |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 3532 | vex_printf("dis_int_load(ppc)(lhzu,rA_addr|rD_addr)\n"); |
sewardj | 0e2cc67 | 2005-07-29 21:58:51 +0000 | [diff] [blame] | 3533 | return False; |
| 3534 | } |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 3535 | DIP("lhzu r%u,%d(r%u)\n", rD_addr, (Int)simm16, rA_addr); |
| 3536 | val = loadBE(Ity_I16, mkexpr(EA)); |
cerion | 2831b00 | 2005-11-30 19:55:22 +0000 | [diff] [blame] | 3537 | putIReg( rD_addr, mkSzWiden16(ty, val, False) ); |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 3538 | putIReg( rA_addr, mkexpr(EA) ); |
sewardj | 0e2cc67 | 2005-07-29 21:58:51 +0000 | [diff] [blame] | 3539 | break; |
cerion | 645c930 | 2005-01-31 10:09:59 +0000 | [diff] [blame] | 3540 | |
cerion | e9d361a | 2005-03-04 17:35:29 +0000 | [diff] [blame] | 3541 | case 0x20: // lwz (Load W & Zero, PPC32 p460) |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 3542 | DIP("lwz r%u,%d(r%u)\n", rD_addr, (Int)simm16, rA_addr); |
| 3543 | val = loadBE(Ity_I32, mkexpr(EA)); |
cerion | 2831b00 | 2005-11-30 19:55:22 +0000 | [diff] [blame] | 3544 | putIReg( rD_addr, mkSzWiden32(ty, val, False) ); |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 3545 | break; |
| 3546 | |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 3547 | case 0x21: // lwzu (Load W & Zero, Update, PPC32 p461)) |
cerion | 76de5cf | 2005-11-18 18:25:12 +0000 | [diff] [blame] | 3548 | if (rA_addr == 0 || rA_addr == rD_addr) { |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 3549 | vex_printf("dis_int_load(ppc)(lwzu,rA_addr|rD_addr)\n"); |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 3550 | return False; |
| 3551 | } |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 3552 | DIP("lwzu r%u,%d(r%u)\n", rD_addr, (Int)simm16, rA_addr); |
| 3553 | val = loadBE(Ity_I32, mkexpr(EA)); |
cerion | 2831b00 | 2005-11-30 19:55:22 +0000 | [diff] [blame] | 3554 | putIReg( rD_addr, mkSzWiden32(ty, val, False) ); |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 3555 | putIReg( rA_addr, mkexpr(EA) ); |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 3556 | break; |
| 3557 | |
| 3558 | /* X Form */ |
| 3559 | case 0x1F: |
| 3560 | if (b0 != 0) { |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 3561 | vex_printf("dis_int_load(ppc)(Ox1F,b0)\n"); |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 3562 | return False; |
| 3563 | } |
cerion | 645c930 | 2005-01-31 10:09:59 +0000 | [diff] [blame] | 3564 | |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 3565 | switch (opc2) { |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 3566 | case 0x077: // lbzux (Load B & Zero, Update Indexed, PPC32 p435) |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 3567 | DIP("lbzux r%u,r%u,r%u\n", rD_addr, rA_addr, rB_addr); |
cerion | 76de5cf | 2005-11-18 18:25:12 +0000 | [diff] [blame] | 3568 | if (rA_addr == 0 || rA_addr == rD_addr) { |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 3569 | vex_printf("dis_int_load(ppc)(lwzux,rA_addr|rD_addr)\n"); |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 3570 | return False; |
| 3571 | } |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 3572 | val = loadBE(Ity_I8, mkexpr(EA)); |
cerion | 2831b00 | 2005-11-30 19:55:22 +0000 | [diff] [blame] | 3573 | putIReg( rD_addr, mkSzWiden8(ty, val, False) ); |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 3574 | putIReg( rA_addr, mkexpr(EA) ); |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 3575 | break; |
| 3576 | |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 3577 | case 0x057: // lbzx (Load B & Zero, Indexed, PPC32 p436) |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 3578 | DIP("lbzx r%u,r%u,r%u\n", rD_addr, rA_addr, rB_addr); |
| 3579 | val = loadBE(Ity_I8, mkexpr(EA)); |
cerion | 2831b00 | 2005-11-30 19:55:22 +0000 | [diff] [blame] | 3580 | putIReg( rD_addr, mkSzWiden8(ty, val, False) ); |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 3581 | break; |
| 3582 | |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 3583 | case 0x177: // lhaux (Load HW Alg, Update Indexed, PPC32 p447) |
cerion | 76de5cf | 2005-11-18 18:25:12 +0000 | [diff] [blame] | 3584 | if (rA_addr == 0 || rA_addr == rD_addr) { |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 3585 | vex_printf("dis_int_load(ppc)(lhaux,rA_addr|rD_addr)\n"); |
cerion | cb14e73 | 2005-09-09 16:38:19 +0000 | [diff] [blame] | 3586 | return False; |
| 3587 | } |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 3588 | DIP("lhaux r%u,r%u,r%u\n", rD_addr, rA_addr, rB_addr); |
| 3589 | val = loadBE(Ity_I16, mkexpr(EA)); |
cerion | 2831b00 | 2005-11-30 19:55:22 +0000 | [diff] [blame] | 3590 | putIReg( rD_addr, mkSzWiden16(ty, val, True) ); |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 3591 | putIReg( rA_addr, mkexpr(EA) ); |
cerion | cb14e73 | 2005-09-09 16:38:19 +0000 | [diff] [blame] | 3592 | break; |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 3593 | |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 3594 | case 0x157: // lhax (Load HW Alg, Indexed, PPC32 p448) |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 3595 | DIP("lhax r%u,r%u,r%u\n", rD_addr, rA_addr, rB_addr); |
| 3596 | val = loadBE(Ity_I16, mkexpr(EA)); |
cerion | 2831b00 | 2005-11-30 19:55:22 +0000 | [diff] [blame] | 3597 | putIReg( rD_addr, mkSzWiden16(ty, val, True) ); |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 3598 | break; |
| 3599 | |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 3600 | case 0x137: // lhzux (Load HW & Zero, Update Indexed, PPC32 p452) |
cerion | 76de5cf | 2005-11-18 18:25:12 +0000 | [diff] [blame] | 3601 | if (rA_addr == 0 || rA_addr == rD_addr) { |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 3602 | vex_printf("dis_int_load(ppc)(lhzux,rA_addr|rD_addr)\n"); |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 3603 | return False; |
| 3604 | } |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 3605 | DIP("lhzux r%u,r%u,r%u\n", rD_addr, rA_addr, rB_addr); |
| 3606 | val = loadBE(Ity_I16, mkexpr(EA)); |
cerion | 2831b00 | 2005-11-30 19:55:22 +0000 | [diff] [blame] | 3607 | putIReg( rD_addr, mkSzWiden16(ty, val, False) ); |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 3608 | putIReg( rA_addr, mkexpr(EA) ); |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 3609 | break; |
| 3610 | |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 3611 | case 0x117: // lhzx (Load HW & Zero, Indexed, PPC32 p453) |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 3612 | DIP("lhzx r%u,r%u,r%u\n", rD_addr, rA_addr, rB_addr); |
| 3613 | val = loadBE(Ity_I16, mkexpr(EA)); |
cerion | 2831b00 | 2005-11-30 19:55:22 +0000 | [diff] [blame] | 3614 | putIReg( rD_addr, mkSzWiden16(ty, val, False) ); |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 3615 | break; |
cerion | 44997f2 | 2005-01-31 18:45:59 +0000 | [diff] [blame] | 3616 | |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 3617 | case 0x037: // lwzux (Load W & Zero, Update Indexed, PPC32 p462) |
cerion | 76de5cf | 2005-11-18 18:25:12 +0000 | [diff] [blame] | 3618 | if (rA_addr == 0 || rA_addr == rD_addr) { |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 3619 | vex_printf("dis_int_load(ppc)(lwzux,rA_addr|rD_addr)\n"); |
sewardj | 7787af4 | 2005-08-04 18:32:19 +0000 | [diff] [blame] | 3620 | return False; |
| 3621 | } |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 3622 | DIP("lwzux r%u,r%u,r%u\n", rD_addr, rA_addr, rB_addr); |
| 3623 | val = loadBE(Ity_I32, mkexpr(EA)); |
cerion | 2831b00 | 2005-11-30 19:55:22 +0000 | [diff] [blame] | 3624 | putIReg( rD_addr, mkSzWiden32(ty, val, False) ); |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 3625 | putIReg( rA_addr, mkexpr(EA) ); |
sewardj | 7787af4 | 2005-08-04 18:32:19 +0000 | [diff] [blame] | 3626 | break; |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 3627 | |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 3628 | case 0x017: // lwzx (Load W & Zero, Indexed, PPC32 p463) |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 3629 | DIP("lwzx r%u,r%u,r%u\n", rD_addr, rA_addr, rB_addr); |
| 3630 | val = loadBE(Ity_I32, mkexpr(EA)); |
cerion | 2831b00 | 2005-11-30 19:55:22 +0000 | [diff] [blame] | 3631 | putIReg( rD_addr, mkSzWiden32(ty, val, False) ); |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 3632 | break; |
cerion | 44997f2 | 2005-01-31 18:45:59 +0000 | [diff] [blame] | 3633 | |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 3634 | |
| 3635 | /* 64bit Loads */ |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 3636 | case 0x035: // ldux (Load DWord, Update Indexed, PPC64 p475) |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 3637 | if (rA_addr == 0 || rA_addr == rD_addr) { |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 3638 | vex_printf("dis_int_load(ppc)(ldux,rA_addr|rD_addr)\n"); |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 3639 | return False; |
| 3640 | } |
| 3641 | DIP("ldux r%u,r%u,r%u\n", rD_addr, rA_addr, rB_addr); |
| 3642 | putIReg( rD_addr, loadBE(Ity_I64, mkexpr(EA)) ); |
| 3643 | putIReg( rA_addr, mkexpr(EA) ); |
| 3644 | break; |
| 3645 | |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 3646 | case 0x015: // ldx (Load DWord, Indexed, PPC64 p476) |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 3647 | DIP("ldx r%u,r%u,r%u\n", rD_addr, rA_addr, rB_addr); |
| 3648 | putIReg( rD_addr, loadBE(Ity_I64, mkexpr(EA)) ); |
| 3649 | break; |
| 3650 | |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 3651 | case 0x175: // lwaux (Load W Alg, Update Indexed, PPC64 p501) |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 3652 | if (rA_addr == 0 || rA_addr == rD_addr) { |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 3653 | vex_printf("dis_int_load(ppc)(lwaux,rA_addr|rD_addr)\n"); |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 3654 | return False; |
| 3655 | } |
| 3656 | DIP("lwaux r%u,r%u,r%u\n", rD_addr, rA_addr, rB_addr); |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 3657 | putIReg( rD_addr, |
| 3658 | unop(Iop_32Sto64, loadBE(Ity_I32, mkexpr(EA))) ); |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 3659 | putIReg( rA_addr, mkexpr(EA) ); |
| 3660 | break; |
| 3661 | |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 3662 | case 0x155: // lwax (Load W Alg, Indexed, PPC64 p502) |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 3663 | DIP("lwax r%u,r%u,r%u\n", rD_addr, rA_addr, rB_addr); |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 3664 | putIReg( rD_addr, |
| 3665 | unop(Iop_32Sto64, loadBE(Ity_I32, mkexpr(EA))) ); |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 3666 | break; |
| 3667 | |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 3668 | default: |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 3669 | vex_printf("dis_int_load(ppc)(opc2)\n"); |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 3670 | return False; |
| 3671 | } |
| 3672 | break; |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 3673 | |
| 3674 | /* DS Form - 64bit Loads */ |
| 3675 | case 0x3A: |
| 3676 | switch (b1<<1 | b0) { |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 3677 | case 0x0: // ld (Load DWord, PPC64 p472) |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 3678 | DIP("ld r%u,%d(r%u)\n", rD_addr, simm16, rA_addr); |
| 3679 | putIReg( rD_addr, loadBE(Ity_I64, mkexpr(EA)) ); |
| 3680 | break; |
| 3681 | |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 3682 | case 0x1: // ldu (Load DWord, Update, PPC64 p474) |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 3683 | if (rA_addr == 0 || rA_addr == rD_addr) { |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 3684 | vex_printf("dis_int_load(ppc)(ldu,rA_addr|rD_addr)\n"); |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 3685 | return False; |
| 3686 | } |
| 3687 | DIP("ldu r%u,%d(r%u)\n", rD_addr, simm16, rA_addr); |
| 3688 | simm16 = simm16 & ~0x3; |
| 3689 | putIReg( rD_addr, loadBE(Ity_I64, mkexpr(EA)) ); |
| 3690 | putIReg( rA_addr, mkexpr(EA) ); |
| 3691 | break; |
| 3692 | |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 3693 | case 0x2: // lwa (Load Word Alg, PPC64 p499) |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 3694 | DIP("lwa r%u,%d(r%u)\n", rD_addr, simm16, rA_addr); |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 3695 | putIReg( rD_addr, |
| 3696 | unop(Iop_32Sto64, loadBE(Ity_I32, mkexpr(EA))) ); |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 3697 | break; |
| 3698 | |
| 3699 | default: |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 3700 | vex_printf("dis_int_load(ppc)(0x3A, opc2)\n"); |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 3701 | return False; |
| 3702 | } |
| 3703 | break; |
| 3704 | |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 3705 | default: |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 3706 | vex_printf("dis_int_load(ppc)(opc1)\n"); |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 3707 | return False; |
| 3708 | } |
| 3709 | return True; |
cerion | 7aa4bbc | 2005-01-29 09:32:07 +0000 | [diff] [blame] | 3710 | } |
| 3711 | |
| 3712 | |
| 3713 | |
cerion | 3d870a3 | 2005-03-18 12:23:33 +0000 | [diff] [blame] | 3714 | /* |
| 3715 | Integer Store Instructions |
| 3716 | */ |
cerion | d23be4e | 2005-01-31 07:23:07 +0000 | [diff] [blame] | 3717 | static Bool dis_int_store ( UInt theInstr ) |
| 3718 | { |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 3719 | /* D-Form, X-Form, DS-Form */ |
cerion | edf7fc5 | 2005-11-18 20:57:41 +0000 | [diff] [blame] | 3720 | UChar opc1 = ifieldOPC(theInstr); |
cerion | 76de5cf | 2005-11-18 18:25:12 +0000 | [diff] [blame] | 3721 | UInt rS_addr = ifieldRegDS(theInstr); |
| 3722 | UInt rA_addr = ifieldRegA(theInstr); |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 3723 | UInt uimm16 = ifieldUIMM16(theInstr); |
cerion | 76de5cf | 2005-11-18 18:25:12 +0000 | [diff] [blame] | 3724 | UInt rB_addr = ifieldRegB(theInstr); |
| 3725 | UInt opc2 = ifieldOPClo10(theInstr); |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 3726 | UChar b1 = ifieldBIT1(theInstr); |
cerion | 76de5cf | 2005-11-18 18:25:12 +0000 | [diff] [blame] | 3727 | UChar b0 = ifieldBIT0(theInstr); |
| 3728 | |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 3729 | Int simm16 = extend_s_16to32(uimm16); |
| 3730 | IRType ty = mode64 ? Ity_I64 : Ity_I32; |
| 3731 | IRTemp rS = newTemp(ty); |
| 3732 | IRTemp rB = newTemp(ty); |
| 3733 | IRTemp EA = newTemp(ty); |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 3734 | |
cerion | 76de5cf | 2005-11-18 18:25:12 +0000 | [diff] [blame] | 3735 | assign( rB, getIReg(rB_addr) ); |
| 3736 | assign( rS, getIReg(rS_addr) ); |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 3737 | |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 3738 | switch (opc1) { |
| 3739 | case 0x1F: // register offset |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 3740 | assign( EA, ea_rAor0_idxd( rA_addr, rB_addr ) ); |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 3741 | break; |
| 3742 | case 0x3E: // immediate offset: 64bit |
| 3743 | simm16 = simm16 & 0xFFFFFFFC; |
| 3744 | default: // immediate offset |
| 3745 | assign( EA, ea_rAor0_simm( rA_addr, simm16 ) ); |
| 3746 | break; |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 3747 | } |
| 3748 | |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 3749 | switch (opc1) { |
sewardj | afe8583 | 2005-09-09 10:25:39 +0000 | [diff] [blame] | 3750 | case 0x26: // stb (Store B, PPC32 p509) |
cerion | 76de5cf | 2005-11-18 18:25:12 +0000 | [diff] [blame] | 3751 | DIP("stb r%u,%d(r%u)\n", rS_addr, simm16, rA_addr); |
cerion | 2831b00 | 2005-11-30 19:55:22 +0000 | [diff] [blame] | 3752 | storeBE( mkexpr(EA), mkSzNarrow8(ty, mkexpr(rS)) ); |
sewardj | afe8583 | 2005-09-09 10:25:39 +0000 | [diff] [blame] | 3753 | break; |
sewardj | b51f0f4 | 2005-07-18 11:38:02 +0000 | [diff] [blame] | 3754 | |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 3755 | case 0x27: // stbu (Store B, Update, PPC32 p510) |
cerion | 76de5cf | 2005-11-18 18:25:12 +0000 | [diff] [blame] | 3756 | if (rA_addr == 0 ) { |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 3757 | vex_printf("dis_int_store(ppc)(stbu,rA_addr)\n"); |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 3758 | return False; |
| 3759 | } |
cerion | 76de5cf | 2005-11-18 18:25:12 +0000 | [diff] [blame] | 3760 | DIP("stbu r%u,%d(r%u)\n", rS_addr, simm16, rA_addr); |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 3761 | putIReg( rA_addr, mkexpr(EA) ); |
cerion | 2831b00 | 2005-11-30 19:55:22 +0000 | [diff] [blame] | 3762 | storeBE( mkexpr(EA), mkSzNarrow8(ty, mkexpr(rS)) ); |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 3763 | break; |
cerion | d23be4e | 2005-01-31 07:23:07 +0000 | [diff] [blame] | 3764 | |
cerion | e9d361a | 2005-03-04 17:35:29 +0000 | [diff] [blame] | 3765 | case 0x2C: // sth (Store HW, PPC32 p522) |
cerion | 76de5cf | 2005-11-18 18:25:12 +0000 | [diff] [blame] | 3766 | DIP("sth r%u,%d(r%u)\n", rS_addr, simm16, rA_addr); |
cerion | 2831b00 | 2005-11-30 19:55:22 +0000 | [diff] [blame] | 3767 | storeBE( mkexpr(EA), mkSzNarrow16(ty, mkexpr(rS)) ); |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 3768 | break; |
| 3769 | |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 3770 | case 0x2D: // sthu (Store HW, Update, PPC32 p524) |
cerion | 76de5cf | 2005-11-18 18:25:12 +0000 | [diff] [blame] | 3771 | if (rA_addr == 0) { |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 3772 | vex_printf("dis_int_store(ppc)(sthu,rA_addr)\n"); |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 3773 | return False; |
| 3774 | } |
cerion | 76de5cf | 2005-11-18 18:25:12 +0000 | [diff] [blame] | 3775 | DIP("sthu r%u,%d(r%u)\n", rS_addr, simm16, rA_addr); |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 3776 | putIReg( rA_addr, mkexpr(EA) ); |
cerion | 2831b00 | 2005-11-30 19:55:22 +0000 | [diff] [blame] | 3777 | storeBE( mkexpr(EA), mkSzNarrow16(ty, mkexpr(rS)) ); |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 3778 | break; |
cerion | d23be4e | 2005-01-31 07:23:07 +0000 | [diff] [blame] | 3779 | |
cerion | e9d361a | 2005-03-04 17:35:29 +0000 | [diff] [blame] | 3780 | case 0x24: // stw (Store W, PPC32 p530) |
cerion | 76de5cf | 2005-11-18 18:25:12 +0000 | [diff] [blame] | 3781 | DIP("stw r%u,%d(r%u)\n", rS_addr, simm16, rA_addr); |
cerion | 2831b00 | 2005-11-30 19:55:22 +0000 | [diff] [blame] | 3782 | storeBE( mkexpr(EA), mkSzNarrow32(ty, mkexpr(rS)) ); |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 3783 | break; |
cerion | d23be4e | 2005-01-31 07:23:07 +0000 | [diff] [blame] | 3784 | |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 3785 | case 0x25: // stwu (Store W, Update, PPC32 p534) |
cerion | 76de5cf | 2005-11-18 18:25:12 +0000 | [diff] [blame] | 3786 | if (rA_addr == 0) { |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 3787 | vex_printf("dis_int_store(ppc)(stwu,rA_addr)\n"); |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 3788 | return False; |
| 3789 | } |
cerion | 76de5cf | 2005-11-18 18:25:12 +0000 | [diff] [blame] | 3790 | DIP("stwu r%u,%d(r%u)\n", rS_addr, simm16, rA_addr); |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 3791 | putIReg( rA_addr, mkexpr(EA) ); |
cerion | 2831b00 | 2005-11-30 19:55:22 +0000 | [diff] [blame] | 3792 | storeBE( mkexpr(EA), mkSzNarrow32(ty, mkexpr(rS)) ); |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 3793 | break; |
| 3794 | |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 3795 | /* X Form : all these use EA_indexed */ |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 3796 | case 0x1F: |
| 3797 | if (b0 != 0) { |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 3798 | vex_printf("dis_int_store(ppc)(0x1F,b0)\n"); |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 3799 | return False; |
| 3800 | } |
cerion | 44997f2 | 2005-01-31 18:45:59 +0000 | [diff] [blame] | 3801 | |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 3802 | switch (opc2) { |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 3803 | case 0x0F7: // stbux (Store B, Update Indexed, PPC32 p511) |
cerion | 76de5cf | 2005-11-18 18:25:12 +0000 | [diff] [blame] | 3804 | if (rA_addr == 0) { |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 3805 | vex_printf("dis_int_store(ppc)(stbux,rA_addr)\n"); |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 3806 | return False; |
| 3807 | } |
cerion | 76de5cf | 2005-11-18 18:25:12 +0000 | [diff] [blame] | 3808 | DIP("stbux r%u,r%u,r%u\n", rS_addr, rA_addr, rB_addr); |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 3809 | putIReg( rA_addr, mkexpr(EA) ); |
cerion | 2831b00 | 2005-11-30 19:55:22 +0000 | [diff] [blame] | 3810 | storeBE( mkexpr(EA), mkSzNarrow8(ty, mkexpr(rS)) ); |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 3811 | break; |
| 3812 | |
cerion | e9d361a | 2005-03-04 17:35:29 +0000 | [diff] [blame] | 3813 | case 0x0D7: // stbx (Store B Indexed, PPC32 p512) |
cerion | 76de5cf | 2005-11-18 18:25:12 +0000 | [diff] [blame] | 3814 | DIP("stbx r%u,r%u,r%u\n", rS_addr, rA_addr, rB_addr); |
cerion | 2831b00 | 2005-11-30 19:55:22 +0000 | [diff] [blame] | 3815 | storeBE( mkexpr(EA), mkSzNarrow8(ty, mkexpr(rS)) ); |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 3816 | break; |
| 3817 | |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 3818 | case 0x1B7: // sthux (Store HW, Update Indexed, PPC32 p525) |
cerion | 76de5cf | 2005-11-18 18:25:12 +0000 | [diff] [blame] | 3819 | if (rA_addr == 0) { |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 3820 | vex_printf("dis_int_store(ppc)(sthux,rA_addr)\n"); |
cerion | cb14e73 | 2005-09-09 16:38:19 +0000 | [diff] [blame] | 3821 | return False; |
| 3822 | } |
cerion | 76de5cf | 2005-11-18 18:25:12 +0000 | [diff] [blame] | 3823 | DIP("sthux r%u,r%u,r%u\n", rS_addr, rA_addr, rB_addr); |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 3824 | putIReg( rA_addr, mkexpr(EA) ); |
cerion | 2831b00 | 2005-11-30 19:55:22 +0000 | [diff] [blame] | 3825 | storeBE( mkexpr(EA), mkSzNarrow16(ty, mkexpr(rS)) ); |
cerion | cb14e73 | 2005-09-09 16:38:19 +0000 | [diff] [blame] | 3826 | break; |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 3827 | |
cerion | e9d361a | 2005-03-04 17:35:29 +0000 | [diff] [blame] | 3828 | case 0x197: // sthx (Store HW Indexed, PPC32 p526) |
cerion | 76de5cf | 2005-11-18 18:25:12 +0000 | [diff] [blame] | 3829 | DIP("sthx r%u,r%u,r%u\n", rS_addr, rA_addr, rB_addr); |
cerion | 2831b00 | 2005-11-30 19:55:22 +0000 | [diff] [blame] | 3830 | storeBE( mkexpr(EA), mkSzNarrow16(ty, mkexpr(rS)) ); |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 3831 | break; |
| 3832 | |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 3833 | case 0x0B7: // stwux (Store W, Update Indexed, PPC32 p535) |
cerion | 76de5cf | 2005-11-18 18:25:12 +0000 | [diff] [blame] | 3834 | if (rA_addr == 0) { |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 3835 | vex_printf("dis_int_store(ppc)(stwux,rA_addr)\n"); |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 3836 | return False; |
| 3837 | } |
cerion | 76de5cf | 2005-11-18 18:25:12 +0000 | [diff] [blame] | 3838 | DIP("stwux r%u,r%u,r%u\n", rS_addr, rA_addr, rB_addr); |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 3839 | putIReg( rA_addr, mkexpr(EA) ); |
cerion | 2831b00 | 2005-11-30 19:55:22 +0000 | [diff] [blame] | 3840 | storeBE( mkexpr(EA), mkSzNarrow32(ty, mkexpr(rS)) ); |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 3841 | break; |
cerion | 44997f2 | 2005-01-31 18:45:59 +0000 | [diff] [blame] | 3842 | |
cerion | e9d361a | 2005-03-04 17:35:29 +0000 | [diff] [blame] | 3843 | case 0x097: // stwx (Store W Indexed, PPC32 p536) |
cerion | 76de5cf | 2005-11-18 18:25:12 +0000 | [diff] [blame] | 3844 | DIP("stwx r%u,r%u,r%u\n", rS_addr, rA_addr, rB_addr); |
cerion | 2831b00 | 2005-11-30 19:55:22 +0000 | [diff] [blame] | 3845 | storeBE( mkexpr(EA), mkSzNarrow32(ty, mkexpr(rS)) ); |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 3846 | break; |
| 3847 | |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 3848 | |
| 3849 | /* 64bit Stores */ |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 3850 | case 0x0B5: // stdux (Store DWord, Update Indexed, PPC64 p584) |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 3851 | if (rA_addr == 0) { |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 3852 | vex_printf("dis_int_store(ppc)(stdux,rA_addr)\n"); |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 3853 | return False; |
| 3854 | } |
| 3855 | DIP("stdux r%u,r%u,r%u\n", rS_addr, rA_addr, rB_addr); |
| 3856 | putIReg( rA_addr, mkexpr(EA) ); |
| 3857 | storeBE( mkexpr(EA), mkexpr(rS) ); |
| 3858 | break; |
| 3859 | |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 3860 | case 0x095: // stdx (Store DWord Indexed, PPC64 p585) |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 3861 | DIP("stdx r%u,r%u,r%u\n", rS_addr, rA_addr, rB_addr); |
| 3862 | storeBE( mkexpr(EA), mkexpr(rS) ); |
| 3863 | break; |
| 3864 | |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 3865 | default: |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 3866 | vex_printf("dis_int_store(ppc)(opc2)\n"); |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 3867 | return False; |
| 3868 | } |
| 3869 | break; |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 3870 | |
| 3871 | /* DS Form - 64bit Stores */ |
| 3872 | case 0x3E: |
| 3873 | switch (b1<<1 | b0) { |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 3874 | case 0x0: // std (Store DWord, PPC64 p580) |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 3875 | DIP("std r%u,%d(r%u)\n", rS_addr, simm16, rA_addr); |
| 3876 | storeBE( mkexpr(EA), mkexpr(rS) ); |
| 3877 | break; |
| 3878 | |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 3879 | case 0x1: // stdu (Store DWord, Update, PPC64 p583) |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 3880 | DIP("stdu r%u,%d(r%u)\n", rS_addr, simm16, rA_addr); |
| 3881 | putIReg( rA_addr, mkexpr(EA) ); |
| 3882 | storeBE( mkexpr(EA), mkexpr(rS) ); |
| 3883 | break; |
| 3884 | |
| 3885 | default: |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 3886 | vex_printf("dis_int_load(ppc)(0x3A, opc2)\n"); |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 3887 | return False; |
| 3888 | } |
| 3889 | break; |
| 3890 | |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 3891 | default: |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 3892 | vex_printf("dis_int_store(ppc)(opc1)\n"); |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 3893 | return False; |
| 3894 | } |
| 3895 | return True; |
cerion | d23be4e | 2005-01-31 07:23:07 +0000 | [diff] [blame] | 3896 | } |
| 3897 | |
| 3898 | |
| 3899 | |
sewardj | 7787af4 | 2005-08-04 18:32:19 +0000 | [diff] [blame] | 3900 | /* |
| 3901 | Integer Load/Store Multiple Instructions |
| 3902 | */ |
| 3903 | static Bool dis_int_ldst_mult ( UInt theInstr ) |
| 3904 | { |
| 3905 | /* D-Form */ |
cerion | 76de5cf | 2005-11-18 18:25:12 +0000 | [diff] [blame] | 3906 | UChar opc1 = ifieldOPC(theInstr); |
| 3907 | UChar rD_addr = ifieldRegDS(theInstr); |
| 3908 | UChar rS_addr = rD_addr; |
| 3909 | UChar rA_addr = ifieldRegA(theInstr); |
cerion | 2831b00 | 2005-11-30 19:55:22 +0000 | [diff] [blame] | 3910 | UInt uimm16 = ifieldUIMM16(theInstr); |
cerion | edf7fc5 | 2005-11-18 20:57:41 +0000 | [diff] [blame] | 3911 | |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 3912 | Int simm16 = extend_s_16to32(uimm16); |
| 3913 | IRType ty = mode64 ? Ity_I64 : Ity_I32; |
| 3914 | IRTemp EA = newTemp(ty); |
| 3915 | UInt r = 0; |
| 3916 | UInt ea_off = 0; |
sewardj | 7787af4 | 2005-08-04 18:32:19 +0000 | [diff] [blame] | 3917 | IRExpr* irx_addr; |
cerion | edf7fc5 | 2005-11-18 20:57:41 +0000 | [diff] [blame] | 3918 | |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 3919 | assign( EA, ea_rAor0_simm( rA_addr, simm16 ) ); |
| 3920 | |
sewardj | 7787af4 | 2005-08-04 18:32:19 +0000 | [diff] [blame] | 3921 | switch (opc1) { |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 3922 | case 0x2E: // lmw (Load Multiple Word, PPC32 p454) |
| 3923 | if (rA_addr >= rD_addr) { |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 3924 | vex_printf("dis_int_ldst_mult(ppc)(lmw,rA_addr)\n"); |
sewardj | 7787af4 | 2005-08-04 18:32:19 +0000 | [diff] [blame] | 3925 | return False; |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 3926 | } |
| 3927 | DIP("lmw r%u,%d(r%u)\n", rD_addr, simm16, rA_addr); |
| 3928 | for (r = rD_addr; r <= 31; r++) { |
| 3929 | irx_addr = binop(Iop_Add32, mkexpr(EA), mkU32(ea_off)); |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 3930 | putIReg( r, mkSzWiden32(ty, loadBE(Ity_I32, irx_addr ), |
| 3931 | False) ); |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 3932 | ea_off += 4; |
| 3933 | } |
| 3934 | break; |
| 3935 | |
| 3936 | case 0x2F: // stmw (Store Multiple Word, PPC32 p527) |
| 3937 | DIP("stmw r%u,%d(r%u)\n", rS_addr, simm16, rA_addr); |
| 3938 | for (r = rS_addr; r <= 31; r++) { |
| 3939 | irx_addr = binop(Iop_Add32, mkexpr(EA), mkU32(ea_off)); |
cerion | 2831b00 | 2005-11-30 19:55:22 +0000 | [diff] [blame] | 3940 | storeBE( irx_addr, mkSzNarrow32(ty, getIReg(r)) ); |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 3941 | ea_off += 4; |
| 3942 | } |
| 3943 | break; |
| 3944 | |
| 3945 | default: |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 3946 | vex_printf("dis_int_ldst_mult(ppc)(opc1)\n"); |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 3947 | return False; |
sewardj | 7787af4 | 2005-08-04 18:32:19 +0000 | [diff] [blame] | 3948 | } |
| 3949 | return True; |
| 3950 | } |
| 3951 | |
| 3952 | |
| 3953 | |
sewardj | 87e651f | 2005-09-09 08:31:18 +0000 | [diff] [blame] | 3954 | /* |
| 3955 | Integer Load/Store String Instructions |
| 3956 | */ |
| 3957 | static |
| 3958 | void generate_lsw_sequence ( IRTemp tNBytes, // # bytes, :: Ity_I32 |
| 3959 | IRTemp EA, // EA |
| 3960 | Int rD, // first dst register |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 3961 | Int maxBytes ) // 32 or 128 |
sewardj | 87e651f | 2005-09-09 08:31:18 +0000 | [diff] [blame] | 3962 | { |
| 3963 | Int i, shift = 24; |
| 3964 | IRExpr* e_nbytes = mkexpr(tNBytes); |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 3965 | IRExpr* e_EA = mkexpr(EA); |
| 3966 | IRType ty = mode64 ? Ity_I64 : Ity_I32; |
sewardj | 87e651f | 2005-09-09 08:31:18 +0000 | [diff] [blame] | 3967 | |
sewardj | 5876fa1 | 2005-09-09 09:35:29 +0000 | [diff] [blame] | 3968 | vassert(rD >= 0 && rD < 32); |
sewardj | 87e651f | 2005-09-09 08:31:18 +0000 | [diff] [blame] | 3969 | rD--; if (rD < 0) rD = 31; |
| 3970 | |
| 3971 | for (i = 0; i < maxBytes; i++) { |
sewardj | 87e651f | 2005-09-09 08:31:18 +0000 | [diff] [blame] | 3972 | /* if (nBytes < (i+1)) goto NIA; */ |
| 3973 | stmt( IRStmt_Exit( binop(Iop_CmpLT32U, e_nbytes, mkU32(i+1)), |
| 3974 | Ijk_Boring, |
cerion | 2831b00 | 2005-11-30 19:55:22 +0000 | [diff] [blame] | 3975 | mkSzConst( ty, nextInsnAddr()) )); |
sewardj | 87e651f | 2005-09-09 08:31:18 +0000 | [diff] [blame] | 3976 | /* when crossing into a new dest register, set it to zero. */ |
| 3977 | if ((i % 4) == 0) { |
| 3978 | rD++; if (rD == 32) rD = 0; |
cerion | 2831b00 | 2005-11-30 19:55:22 +0000 | [diff] [blame] | 3979 | putIReg(rD, mkSzImm(ty, 0)); |
sewardj | 87e651f | 2005-09-09 08:31:18 +0000 | [diff] [blame] | 3980 | shift = 24; |
| 3981 | } |
| 3982 | /* rD |= (8Uto32(*(EA+i))) << shift */ |
| 3983 | vassert(shift == 0 || shift == 8 || shift == 16 || shift == 24); |
sewardj | 2ef8a37 | 2006-01-28 17:07:19 +0000 | [diff] [blame] | 3984 | putIReg( |
| 3985 | rD, |
| 3986 | mkSzWiden32( |
| 3987 | ty, |
| 3988 | binop( |
| 3989 | Iop_Or32, |
| 3990 | mkSzNarrow32(ty, getIReg(rD)), |
| 3991 | binop( |
| 3992 | Iop_Shl32, |
| 3993 | unop( |
| 3994 | Iop_8Uto32, |
| 3995 | loadBE(Ity_I8, |
| 3996 | binop(mkSzOp(ty,Iop_Add8), e_EA, mkSzImm(ty,i))) |
| 3997 | ), |
| 3998 | mkU8(toUChar(shift)) |
| 3999 | ) |
| 4000 | ), |
| 4001 | /*Signed*/False |
| 4002 | ) |
| 4003 | ); |
sewardj | 87e651f | 2005-09-09 08:31:18 +0000 | [diff] [blame] | 4004 | shift -= 8; |
| 4005 | } |
| 4006 | } |
| 4007 | |
sewardj | 5876fa1 | 2005-09-09 09:35:29 +0000 | [diff] [blame] | 4008 | static |
| 4009 | void generate_stsw_sequence ( IRTemp tNBytes, // # bytes, :: Ity_I32 |
| 4010 | IRTemp EA, // EA |
| 4011 | Int rS, // first src register |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 4012 | Int maxBytes ) // 32 or 128 |
sewardj | 5876fa1 | 2005-09-09 09:35:29 +0000 | [diff] [blame] | 4013 | { |
| 4014 | Int i, shift = 24; |
| 4015 | IRExpr* e_nbytes = mkexpr(tNBytes); |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 4016 | IRExpr* e_EA = mkexpr(EA); |
| 4017 | IRType ty = mode64 ? Ity_I64 : Ity_I32; |
sewardj | 5876fa1 | 2005-09-09 09:35:29 +0000 | [diff] [blame] | 4018 | |
| 4019 | vassert(rS >= 0 && rS < 32); |
| 4020 | rS--; if (rS < 0) rS = 31; |
| 4021 | |
| 4022 | for (i = 0; i < maxBytes; i++) { |
| 4023 | /* if (nBytes < (i+1)) goto NIA; */ |
| 4024 | stmt( IRStmt_Exit( binop(Iop_CmpLT32U, e_nbytes, mkU32(i+1)), |
| 4025 | Ijk_Boring, |
cerion | 2831b00 | 2005-11-30 19:55:22 +0000 | [diff] [blame] | 4026 | mkSzConst( ty, nextInsnAddr() ) )); |
sewardj | 5876fa1 | 2005-09-09 09:35:29 +0000 | [diff] [blame] | 4027 | /* check for crossing into a new src register. */ |
| 4028 | if ((i % 4) == 0) { |
| 4029 | rS++; if (rS == 32) rS = 0; |
| 4030 | shift = 24; |
| 4031 | } |
| 4032 | /* *(EA+i) = 32to8(rS >> shift) */ |
| 4033 | vassert(shift == 0 || shift == 8 || shift == 16 || shift == 24); |
| 4034 | storeBE( |
cerion | 2831b00 | 2005-11-30 19:55:22 +0000 | [diff] [blame] | 4035 | binop(mkSzOp(ty,Iop_Add8), e_EA, mkSzImm(ty,i)), |
sewardj | 5876fa1 | 2005-09-09 09:35:29 +0000 | [diff] [blame] | 4036 | unop(Iop_32to8, |
cerion | 2831b00 | 2005-11-30 19:55:22 +0000 | [diff] [blame] | 4037 | binop(Iop_Shr32, |
| 4038 | mkSzNarrow32(ty, getIReg(rS)), |
| 4039 | mkU8(toUChar(shift)))) |
sewardj | 5876fa1 | 2005-09-09 09:35:29 +0000 | [diff] [blame] | 4040 | ); |
| 4041 | shift -= 8; |
| 4042 | } |
| 4043 | } |
| 4044 | |
sewardj | 87e651f | 2005-09-09 08:31:18 +0000 | [diff] [blame] | 4045 | static Bool dis_int_ldst_str ( UInt theInstr, /*OUT*/Bool* stopHere ) |
| 4046 | { |
| 4047 | /* X-Form */ |
cerion | 76de5cf | 2005-11-18 18:25:12 +0000 | [diff] [blame] | 4048 | UChar opc1 = ifieldOPC(theInstr); |
| 4049 | UChar rD_addr = ifieldRegDS(theInstr); |
| 4050 | UChar rS_addr = rD_addr; |
| 4051 | UChar rA_addr = ifieldRegA(theInstr); |
| 4052 | UChar rB_addr = ifieldRegB(theInstr); |
| 4053 | UChar NumBytes = rB_addr; |
| 4054 | UInt opc2 = ifieldOPClo10(theInstr); |
| 4055 | UChar b0 = ifieldBIT0(theInstr); |
cerion | edf7fc5 | 2005-11-18 20:57:41 +0000 | [diff] [blame] | 4056 | |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 4057 | IRType ty = mode64 ? Ity_I64 : Ity_I32; |
| 4058 | IRTemp t_EA = newTemp(ty); |
sewardj | 87e651f | 2005-09-09 08:31:18 +0000 | [diff] [blame] | 4059 | IRTemp t_nbytes = IRTemp_INVALID; |
cerion | edf7fc5 | 2005-11-18 20:57:41 +0000 | [diff] [blame] | 4060 | |
sewardj | 87e651f | 2005-09-09 08:31:18 +0000 | [diff] [blame] | 4061 | *stopHere = False; |
cerion | edf7fc5 | 2005-11-18 20:57:41 +0000 | [diff] [blame] | 4062 | |
sewardj | 87e651f | 2005-09-09 08:31:18 +0000 | [diff] [blame] | 4063 | if (opc1 != 0x1F || b0 != 0) { |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 4064 | vex_printf("dis_int_ldst_str(ppc)(opc1)\n"); |
sewardj | 87e651f | 2005-09-09 08:31:18 +0000 | [diff] [blame] | 4065 | return False; |
| 4066 | } |
| 4067 | |
| 4068 | switch (opc2) { |
| 4069 | case 0x255: // lswi (Load String Word Immediate, PPC32 p455) |
| 4070 | /* NB: does not reject the case where RA is in the range of |
| 4071 | registers to be loaded. It should. */ |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 4072 | DIP("lswi r%u,r%u,%d\n", rD_addr, rA_addr, NumBytes); |
| 4073 | assign( t_EA, ea_rAor0(rA_addr) ); |
sewardj | 2ef8a37 | 2006-01-28 17:07:19 +0000 | [diff] [blame] | 4074 | if (NumBytes == 8 && !mode64) { |
sewardj | 87e651f | 2005-09-09 08:31:18 +0000 | [diff] [blame] | 4075 | /* Special case hack */ |
cerion | 76de5cf | 2005-11-18 18:25:12 +0000 | [diff] [blame] | 4076 | /* rD = Mem[EA]; (rD+1)%32 = Mem[EA+4] */ |
| 4077 | putIReg( rD_addr, |
sewardj | 87e651f | 2005-09-09 08:31:18 +0000 | [diff] [blame] | 4078 | loadBE(Ity_I32, mkexpr(t_EA)) ); |
cerion | 76de5cf | 2005-11-18 18:25:12 +0000 | [diff] [blame] | 4079 | putIReg( (rD_addr+1) % 32, |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 4080 | loadBE(Ity_I32, |
| 4081 | binop(Iop_Add32, mkexpr(t_EA), mkU32(4))) ); |
sewardj | 87e651f | 2005-09-09 08:31:18 +0000 | [diff] [blame] | 4082 | } else { |
| 4083 | t_nbytes = newTemp(Ity_I32); |
cerion | 76de5cf | 2005-11-18 18:25:12 +0000 | [diff] [blame] | 4084 | assign( t_nbytes, mkU32(NumBytes==0 ? 32 : NumBytes) ); |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 4085 | generate_lsw_sequence( t_nbytes, t_EA, rD_addr, 32 ); |
sewardj | 87e651f | 2005-09-09 08:31:18 +0000 | [diff] [blame] | 4086 | *stopHere = True; |
| 4087 | } |
| 4088 | return True; |
| 4089 | |
| 4090 | case 0x215: // lswx (Load String Word Indexed, PPC32 p456) |
| 4091 | /* NB: does not reject the case where RA is in the range of |
| 4092 | registers to be loaded. It should. Although considering |
| 4093 | that that can only be detected at run time, it's not easy to |
| 4094 | do so. */ |
cerion | 76de5cf | 2005-11-18 18:25:12 +0000 | [diff] [blame] | 4095 | if (rD_addr == rA_addr || rD_addr == rB_addr) |
sewardj | 87e651f | 2005-09-09 08:31:18 +0000 | [diff] [blame] | 4096 | return False; |
cerion | 76de5cf | 2005-11-18 18:25:12 +0000 | [diff] [blame] | 4097 | if (rD_addr == 0 && rA_addr == 0) |
sewardj | 87e651f | 2005-09-09 08:31:18 +0000 | [diff] [blame] | 4098 | return False; |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 4099 | DIP("lswx r%u,r%u,r%u\n", rD_addr, rA_addr, rB_addr); |
sewardj | 87e651f | 2005-09-09 08:31:18 +0000 | [diff] [blame] | 4100 | t_nbytes = newTemp(Ity_I32); |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 4101 | assign( t_EA, ea_rAor0_idxd(rA_addr,rB_addr) ); |
cerion | edf7fc5 | 2005-11-18 20:57:41 +0000 | [diff] [blame] | 4102 | assign( t_nbytes, unop( Iop_8Uto32, getXER_BC() ) ); |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 4103 | generate_lsw_sequence( t_nbytes, t_EA, rD_addr, 128 ); |
sewardj | 87e651f | 2005-09-09 08:31:18 +0000 | [diff] [blame] | 4104 | *stopHere = True; |
| 4105 | return True; |
| 4106 | |
sewardj | 5876fa1 | 2005-09-09 09:35:29 +0000 | [diff] [blame] | 4107 | case 0x2D5: // stswi (Store String Word Immediate, PPC32 p528) |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 4108 | DIP("stswi r%u,r%u,%d\n", rS_addr, rA_addr, NumBytes); |
| 4109 | assign( t_EA, ea_rAor0(rA_addr) ); |
sewardj | 2ef8a37 | 2006-01-28 17:07:19 +0000 | [diff] [blame] | 4110 | if (NumBytes == 8 && !mode64) { |
sewardj | 5876fa1 | 2005-09-09 09:35:29 +0000 | [diff] [blame] | 4111 | /* Special case hack */ |
cerion | 76de5cf | 2005-11-18 18:25:12 +0000 | [diff] [blame] | 4112 | /* Mem[EA] = rD; Mem[EA+4] = (rD+1)%32 */ |
| 4113 | storeBE( mkexpr(t_EA), |
| 4114 | getIReg(rD_addr) ); |
| 4115 | storeBE( binop(Iop_Add32, mkexpr(t_EA), mkU32(4)), |
| 4116 | getIReg((rD_addr+1) % 32) ); |
sewardj | 5876fa1 | 2005-09-09 09:35:29 +0000 | [diff] [blame] | 4117 | } else { |
| 4118 | t_nbytes = newTemp(Ity_I32); |
cerion | 76de5cf | 2005-11-18 18:25:12 +0000 | [diff] [blame] | 4119 | assign( t_nbytes, mkU32(NumBytes==0 ? 32 : NumBytes) ); |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 4120 | generate_stsw_sequence( t_nbytes, t_EA, rD_addr, 32 ); |
sewardj | 5876fa1 | 2005-09-09 09:35:29 +0000 | [diff] [blame] | 4121 | *stopHere = True; |
| 4122 | } |
| 4123 | return True; |
| 4124 | |
sewardj | 5876fa1 | 2005-09-09 09:35:29 +0000 | [diff] [blame] | 4125 | case 0x295: // stswx (Store String Word Indexed, PPC32 p529) |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 4126 | DIP("stswx r%u,r%u,r%u\n", rS_addr, rA_addr, rB_addr); |
sewardj | 5876fa1 | 2005-09-09 09:35:29 +0000 | [diff] [blame] | 4127 | t_nbytes = newTemp(Ity_I32); |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 4128 | assign( t_EA, ea_rAor0_idxd(rA_addr,rB_addr) ); |
cerion | edf7fc5 | 2005-11-18 20:57:41 +0000 | [diff] [blame] | 4129 | assign( t_nbytes, unop( Iop_8Uto32, getXER_BC() ) ); |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 4130 | generate_stsw_sequence( t_nbytes, t_EA, rS_addr, 128 ); |
sewardj | 5876fa1 | 2005-09-09 09:35:29 +0000 | [diff] [blame] | 4131 | *stopHere = True; |
| 4132 | return True; |
sewardj | 87e651f | 2005-09-09 08:31:18 +0000 | [diff] [blame] | 4133 | |
| 4134 | default: |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 4135 | vex_printf("dis_int_ldst_str(ppc)(opc2)\n"); |
sewardj | 87e651f | 2005-09-09 08:31:18 +0000 | [diff] [blame] | 4136 | return False; |
| 4137 | } |
| 4138 | return True; |
| 4139 | } |
| 4140 | |
cerion | 094d139 | 2005-06-20 13:45:57 +0000 | [diff] [blame] | 4141 | |
sewardj | b51f0f4 | 2005-07-18 11:38:02 +0000 | [diff] [blame] | 4142 | /* ------------------------------------------------------------------ |
| 4143 | Integer Branch Instructions |
| 4144 | ------------------------------------------------------------------ */ |
cerion | 645c930 | 2005-01-31 10:09:59 +0000 | [diff] [blame] | 4145 | |
cerion | 45552a9 | 2005-02-03 18:20:22 +0000 | [diff] [blame] | 4146 | /* |
| 4147 | Branch helper function |
| 4148 | ok = BO[2] | ((CTR[0] != 0) ^ BO[1]) |
sewardj | b51f0f4 | 2005-07-18 11:38:02 +0000 | [diff] [blame] | 4149 | Returns an I32 which is 0x00000000 if the ctr condition failed |
| 4150 | and 0xFFFFFFFF otherwise. |
cerion | 45552a9 | 2005-02-03 18:20:22 +0000 | [diff] [blame] | 4151 | */ |
sewardj | b51f0f4 | 2005-07-18 11:38:02 +0000 | [diff] [blame] | 4152 | static IRExpr* /* :: Ity_I32 */ branch_ctr_ok( UInt BO ) |
cerion | 45552a9 | 2005-02-03 18:20:22 +0000 | [diff] [blame] | 4153 | { |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 4154 | IRType ty = mode64 ? Ity_I64 : Ity_I32; |
sewardj | b51f0f4 | 2005-07-18 11:38:02 +0000 | [diff] [blame] | 4155 | IRTemp ok = newTemp(Ity_I32); |
cerion | ed623db | 2005-06-20 12:42:04 +0000 | [diff] [blame] | 4156 | |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 4157 | if ((BO >> 2) & 1) { // independent of ctr |
sewardj | b51f0f4 | 2005-07-18 11:38:02 +0000 | [diff] [blame] | 4158 | assign( ok, mkU32(0xFFFFFFFF) ); |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 4159 | } else { |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 4160 | if ((BO >> 1) & 1) { // ctr == 0 ? |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 4161 | assign( ok, unop( Iop_1Sto32, |
cerion | 4e2c2b3 | 2006-01-02 13:35:51 +0000 | [diff] [blame] | 4162 | binop( mkSzOp(ty, Iop_CmpEQ8), |
| 4163 | getGST( PPC_GST_CTR ), |
| 4164 | mkSzImm(ty,0))) ); |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 4165 | } else { // ctr != 0 ? |
sewardj | b51f0f4 | 2005-07-18 11:38:02 +0000 | [diff] [blame] | 4166 | assign( ok, unop( Iop_1Sto32, |
cerion | 4e2c2b3 | 2006-01-02 13:35:51 +0000 | [diff] [blame] | 4167 | binop( mkSzOp(ty, Iop_CmpNE8), |
| 4168 | getGST( PPC_GST_CTR ), |
| 4169 | mkSzImm(ty,0))) ); |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 4170 | } |
| 4171 | } |
| 4172 | return mkexpr(ok); |
cerion | 45552a9 | 2005-02-03 18:20:22 +0000 | [diff] [blame] | 4173 | } |
| 4174 | |
sewardj | b51f0f4 | 2005-07-18 11:38:02 +0000 | [diff] [blame] | 4175 | |
cerion | 45552a9 | 2005-02-03 18:20:22 +0000 | [diff] [blame] | 4176 | /* |
sewardj | b51f0f4 | 2005-07-18 11:38:02 +0000 | [diff] [blame] | 4177 | Branch helper function cond_ok = BO[4] | (CR[BI] == BO[3]) |
| 4178 | Returns an I32 which is either 0 if the condition failed or |
| 4179 | some arbitrary nonzero value otherwise. */ |
| 4180 | |
| 4181 | static IRExpr* /* :: Ity_I32 */ branch_cond_ok( UInt BO, UInt BI ) |
cerion | 45552a9 | 2005-02-03 18:20:22 +0000 | [diff] [blame] | 4182 | { |
sewardj | b51f0f4 | 2005-07-18 11:38:02 +0000 | [diff] [blame] | 4183 | Int where; |
| 4184 | IRTemp res = newTemp(Ity_I32); |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 4185 | IRTemp cr_bi = newTemp(Ity_I32); |
| 4186 | |
sewardj | b51f0f4 | 2005-07-18 11:38:02 +0000 | [diff] [blame] | 4187 | if ((BO >> 4) & 1) { |
| 4188 | assign( res, mkU32(1) ); |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 4189 | } else { |
sewardj | b51f0f4 | 2005-07-18 11:38:02 +0000 | [diff] [blame] | 4190 | // ok = (CR[BI] == BO[3]) Note, the following relies on |
| 4191 | // getCRbit_anywhere returning a value which |
| 4192 | // is either zero or has exactly 1 bit set. |
| 4193 | assign( cr_bi, getCRbit_anywhere( BI, &where ) ); |
cerion | e9d361a | 2005-03-04 17:35:29 +0000 | [diff] [blame] | 4194 | |
| 4195 | if ((BO >> 3) & 1) { |
sewardj | b51f0f4 | 2005-07-18 11:38:02 +0000 | [diff] [blame] | 4196 | /* We can use cr_bi as-is. */ |
| 4197 | assign( res, mkexpr(cr_bi) ); |
cerion | e9d361a | 2005-03-04 17:35:29 +0000 | [diff] [blame] | 4198 | } else { |
sewardj | b51f0f4 | 2005-07-18 11:38:02 +0000 | [diff] [blame] | 4199 | /* We have to invert the sense of the information held in |
| 4200 | cr_bi. For that we need to know which bit |
cerion | 76de5cf | 2005-11-18 18:25:12 +0000 | [diff] [blame] | 4201 | getCRbit_anywhere regards as significant. */ |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 4202 | assign( res, binop(Iop_Xor32, mkexpr(cr_bi), |
| 4203 | mkU32(1<<where)) ); |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 4204 | } |
| 4205 | } |
sewardj | b51f0f4 | 2005-07-18 11:38:02 +0000 | [diff] [blame] | 4206 | return mkexpr(res); |
cerion | 45552a9 | 2005-02-03 18:20:22 +0000 | [diff] [blame] | 4207 | } |
| 4208 | |
| 4209 | |
cerion | 3d870a3 | 2005-03-18 12:23:33 +0000 | [diff] [blame] | 4210 | /* |
| 4211 | Integer Branch Instructions |
| 4212 | */ |
sewardj | 9d540e5 | 2005-10-08 11:28:16 +0000 | [diff] [blame] | 4213 | static Bool dis_branch ( UInt theInstr, |
| 4214 | /*OUT*/DisResult* dres, |
sewardj | c716aea | 2006-01-17 01:48:46 +0000 | [diff] [blame] | 4215 | Bool (*resteerOkFn)(void*,Addr64), |
| 4216 | void* callback_opaque ) |
cerion | 91ad536 | 2005-01-27 23:02:41 +0000 | [diff] [blame] | 4217 | { |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 4218 | UChar opc1 = ifieldOPC(theInstr); |
| 4219 | UChar BO = ifieldRegDS(theInstr); |
| 4220 | UChar BI = ifieldRegA(theInstr); |
| 4221 | UInt BD_u16 = ifieldUIMM16(theInstr) & 0xFFFFFFFC; /* mask off */ |
| 4222 | UChar b11to15 = ifieldRegB(theInstr); |
| 4223 | UInt opc2 = ifieldOPClo10(theInstr); |
| 4224 | UInt LI_u26 = ifieldUIMM26(theInstr) & 0xFFFFFFFC; /* mask off */ |
| 4225 | UChar flag_AA = ifieldBIT1(theInstr); |
| 4226 | UChar flag_LK = ifieldBIT0(theInstr); |
| 4227 | |
cerion | 2831b00 | 2005-11-30 19:55:22 +0000 | [diff] [blame] | 4228 | IRType ty = mode64 ? Ity_I64 : Ity_I32; |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 4229 | Addr64 tgt = 0; |
| 4230 | Int BD = extend_s_16to32(BD_u16); |
cerion | 2831b00 | 2005-11-30 19:55:22 +0000 | [diff] [blame] | 4231 | IRTemp do_branch = newTemp(Ity_I32); |
| 4232 | IRTemp ctr_ok = newTemp(Ity_I32); |
| 4233 | IRTemp cond_ok = newTemp(Ity_I32); |
| 4234 | IRExpr* e_nia = mkSzImm(ty, nextInsnAddr()); |
| 4235 | IRConst* c_nia = mkSzConst(ty, nextInsnAddr()); |
sewardj | df07b88 | 2005-11-29 18:19:11 +0000 | [diff] [blame] | 4236 | IRTemp lr_old = newTemp(ty); |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 4237 | |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 4238 | /* Hack to pass through code that just wants to read the PC */ |
| 4239 | if (theInstr == 0x429F0005) { |
sewardj | b51f0f4 | 2005-07-18 11:38:02 +0000 | [diff] [blame] | 4240 | DIP("bcl 0x%x, 0x%x (a.k.a mr lr,cia+4)\n", BO, BI); |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 4241 | putGST( PPC_GST_LR, e_nia ); |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 4242 | return True; |
sewardj | b51f0f4 | 2005-07-18 11:38:02 +0000 | [diff] [blame] | 4243 | } |
sewardj | 9d540e5 | 2005-10-08 11:28:16 +0000 | [diff] [blame] | 4244 | |
| 4245 | /* The default what-next. Individual cases can override it. */ |
| 4246 | dres->whatNext = Dis_StopHere; |
| 4247 | |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 4248 | switch (opc1) { |
cerion | e9d361a | 2005-03-04 17:35:29 +0000 | [diff] [blame] | 4249 | case 0x12: // b (Branch, PPC32 p360) |
cerion | 4561acb | 2005-02-21 14:07:48 +0000 | [diff] [blame] | 4250 | if (flag_AA) { |
cerion | 2831b00 | 2005-11-30 19:55:22 +0000 | [diff] [blame] | 4251 | tgt = mkSzAddr( ty, extend_s_26to64(LI_u26) ); |
cerion | 4561acb | 2005-02-21 14:07:48 +0000 | [diff] [blame] | 4252 | } else { |
cerion | 2831b00 | 2005-11-30 19:55:22 +0000 | [diff] [blame] | 4253 | tgt = mkSzAddr( ty, guest_CIA_curr_instr + |
| 4254 | (Long)extend_s_26to64(LI_u26) ); |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 4255 | } |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 4256 | if (mode64) { |
| 4257 | DIP("b%s%s 0x%llx\n", |
| 4258 | flag_LK ? "l" : "", flag_AA ? "a" : "", tgt); |
| 4259 | } else { |
| 4260 | DIP("b%s%s 0x%x\n", |
| 4261 | flag_LK ? "l" : "", flag_AA ? "a" : "", (Addr32)tgt); |
sewardj | 9d540e5 | 2005-10-08 11:28:16 +0000 | [diff] [blame] | 4262 | } |
| 4263 | |
sewardj | cf8986c | 2006-01-18 04:14:52 +0000 | [diff] [blame] | 4264 | if (flag_LK) { |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 4265 | putGST( PPC_GST_LR, e_nia ); |
sewardj | cf8986c | 2006-01-18 04:14:52 +0000 | [diff] [blame] | 4266 | if (mode64) |
| 4267 | make_redzone_AbiHint( "branch-and-link (unconditional call)" ); |
| 4268 | } |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 4269 | |
sewardj | c716aea | 2006-01-17 01:48:46 +0000 | [diff] [blame] | 4270 | if (resteerOkFn( callback_opaque, tgt )) { |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 4271 | dres->whatNext = Dis_Resteer; |
| 4272 | dres->continueAt = tgt; |
sewardj | 9d540e5 | 2005-10-08 11:28:16 +0000 | [diff] [blame] | 4273 | } else { |
| 4274 | irbb->jumpkind = flag_LK ? Ijk_Call : Ijk_Boring; |
cerion | 2831b00 | 2005-11-30 19:55:22 +0000 | [diff] [blame] | 4275 | irbb->next = mkSzImm(ty, tgt); |
sewardj | 9d540e5 | 2005-10-08 11:28:16 +0000 | [diff] [blame] | 4276 | } |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 4277 | break; |
| 4278 | |
cerion | e9d361a | 2005-03-04 17:35:29 +0000 | [diff] [blame] | 4279 | case 0x10: // bc (Branch Conditional, PPC32 p361) |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 4280 | DIP("bc%s%s 0x%x, 0x%x, 0x%x\n", |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 4281 | flag_LK ? "l" : "", flag_AA ? "a" : "", BO, BI, BD); |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 4282 | |
| 4283 | if (!(BO & 0x4)) { |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 4284 | putGST( PPC_GST_CTR, |
cerion | 2831b00 | 2005-11-30 19:55:22 +0000 | [diff] [blame] | 4285 | binop(mkSzOp(ty, Iop_Sub8), |
| 4286 | getGST( PPC_GST_CTR ), mkSzImm(ty, 1)) ); |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 4287 | } |
sewardj | b51f0f4 | 2005-07-18 11:38:02 +0000 | [diff] [blame] | 4288 | |
| 4289 | /* This is a bit subtle. ctr_ok is either all 0s or all 1s. |
cerion | 76de5cf | 2005-11-18 18:25:12 +0000 | [diff] [blame] | 4290 | cond_ok is either zero or nonzero, since that's the cheapest |
| 4291 | way to compute it. Anding them together gives a value which |
| 4292 | is either zero or non zero and so that's what we must test |
| 4293 | for in the IRStmt_Exit. */ |
sewardj | b51f0f4 | 2005-07-18 11:38:02 +0000 | [diff] [blame] | 4294 | assign( ctr_ok, branch_ctr_ok( BO ) ); |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 4295 | assign( cond_ok, branch_cond_ok( BO, BI ) ); |
sewardj | b51f0f4 | 2005-07-18 11:38:02 +0000 | [diff] [blame] | 4296 | assign( do_branch, |
| 4297 | binop(Iop_And32, mkexpr(cond_ok), mkexpr(ctr_ok)) ); |
| 4298 | |
cerion | 4561acb | 2005-02-21 14:07:48 +0000 | [diff] [blame] | 4299 | if (flag_AA) { |
cerion | 2831b00 | 2005-11-30 19:55:22 +0000 | [diff] [blame] | 4300 | tgt = mkSzAddr(ty, extend_s_16to64(BD_u16)); |
cerion | 4561acb | 2005-02-21 14:07:48 +0000 | [diff] [blame] | 4301 | } else { |
cerion | 2831b00 | 2005-11-30 19:55:22 +0000 | [diff] [blame] | 4302 | tgt = mkSzAddr(ty, guest_CIA_curr_instr + |
| 4303 | (Long)extend_s_16to64(BD_u16)); |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 4304 | } |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 4305 | if (flag_LK) |
| 4306 | putGST( PPC_GST_LR, e_nia ); |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 4307 | |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 4308 | stmt( IRStmt_Exit( |
| 4309 | binop(Iop_CmpNE32, mkexpr(do_branch), mkU32(0)), |
| 4310 | flag_LK ? Ijk_Call : Ijk_Boring, |
cerion | 2831b00 | 2005-11-30 19:55:22 +0000 | [diff] [blame] | 4311 | mkSzConst(ty, tgt) ) ); |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 4312 | |
| 4313 | irbb->jumpkind = Ijk_Boring; |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 4314 | irbb->next = e_nia; |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 4315 | break; |
| 4316 | |
| 4317 | case 0x13: |
sewardj | 6be6723 | 2006-01-24 19:00:05 +0000 | [diff] [blame] | 4318 | /* For bclr and bcctr, it appears that the lowest two bits of |
| 4319 | b11to15 are a branch hint, and so we only need to ensure it's |
| 4320 | of the form 000XX. */ |
| 4321 | if ((b11to15 & ~3) != 0) { |
| 4322 | vex_printf("dis_int_branch(ppc)(0x13,b11to15)(%d)\n", (Int)b11to15); |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 4323 | return False; |
| 4324 | } |
cerion | 91ad536 | 2005-01-27 23:02:41 +0000 | [diff] [blame] | 4325 | |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 4326 | switch (opc2) { |
cerion | e9d361a | 2005-03-04 17:35:29 +0000 | [diff] [blame] | 4327 | case 0x210: // bcctr (Branch Cond. to Count Register, PPC32 p363) |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 4328 | if ((BO & 0x4) == 0) { // "decr and test CTR" option invalid |
| 4329 | vex_printf("dis_int_branch(ppc)(bcctr,BO)\n"); |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 4330 | return False; |
| 4331 | } |
cerion | a31e8b5 | 2005-02-21 16:30:45 +0000 | [diff] [blame] | 4332 | DIP("bcctr%s 0x%x, 0x%x\n", flag_LK ? "l" : "", BO, BI); |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 4333 | |
| 4334 | assign( cond_ok, branch_cond_ok( BO, BI ) ); |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 4335 | |
cerion | 2831b00 | 2005-11-30 19:55:22 +0000 | [diff] [blame] | 4336 | assign( lr_old, addr_align( getGST( PPC_GST_CTR ), 4 )); |
sewardj | df07b88 | 2005-11-29 18:19:11 +0000 | [diff] [blame] | 4337 | |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 4338 | if (flag_LK) |
| 4339 | putGST( PPC_GST_LR, e_nia ); |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 4340 | |
sewardj | b51f0f4 | 2005-07-18 11:38:02 +0000 | [diff] [blame] | 4341 | stmt( IRStmt_Exit( |
| 4342 | binop(Iop_CmpEQ32, mkexpr(cond_ok), mkU32(0)), |
| 4343 | Ijk_Boring, |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 4344 | c_nia )); |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 4345 | |
| 4346 | irbb->jumpkind = flag_LK ? Ijk_Call : Ijk_Boring; |
sewardj | df07b88 | 2005-11-29 18:19:11 +0000 | [diff] [blame] | 4347 | irbb->next = mkexpr(lr_old); |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 4348 | break; |
| 4349 | |
sewardj | cf8986c | 2006-01-18 04:14:52 +0000 | [diff] [blame] | 4350 | case 0x010: { // bclr (Branch Cond. to Link Register, PPC32 p365) |
| 4351 | Bool vanilla_return = False; |
sewardj | b51f0f4 | 2005-07-18 11:38:02 +0000 | [diff] [blame] | 4352 | if ((BO & 0x14 /* 1z1zz */) == 0x14 && flag_LK == 0) { |
cerion | 225a034 | 2005-09-12 20:49:09 +0000 | [diff] [blame] | 4353 | DIP("blr\n"); |
sewardj | cf8986c | 2006-01-18 04:14:52 +0000 | [diff] [blame] | 4354 | vanilla_return = True; |
sewardj | b51f0f4 | 2005-07-18 11:38:02 +0000 | [diff] [blame] | 4355 | } else { |
| 4356 | DIP("bclr%s 0x%x, 0x%x\n", flag_LK ? "l" : "", BO, BI); |
| 4357 | } |
cerion | 91ad536 | 2005-01-27 23:02:41 +0000 | [diff] [blame] | 4358 | |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 4359 | if (!(BO & 0x4)) { |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 4360 | putGST( PPC_GST_CTR, |
cerion | 2831b00 | 2005-11-30 19:55:22 +0000 | [diff] [blame] | 4361 | binop(mkSzOp(ty, Iop_Sub8), |
| 4362 | getGST( PPC_GST_CTR ), mkSzImm(ty, 1)) ); |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 4363 | } |
| 4364 | |
sewardj | b51f0f4 | 2005-07-18 11:38:02 +0000 | [diff] [blame] | 4365 | /* See comments above for 'bc' about this */ |
| 4366 | assign( ctr_ok, branch_ctr_ok( BO ) ); |
| 4367 | assign( cond_ok, branch_cond_ok( BO, BI ) ); |
| 4368 | assign( do_branch, |
| 4369 | binop(Iop_And32, mkexpr(cond_ok), mkexpr(ctr_ok)) ); |
cerion | 2831b00 | 2005-11-30 19:55:22 +0000 | [diff] [blame] | 4370 | |
sewardj | df07b88 | 2005-11-29 18:19:11 +0000 | [diff] [blame] | 4371 | assign( lr_old, addr_align( getGST( PPC_GST_LR ), 4 )); |
| 4372 | |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 4373 | if (flag_LK) |
| 4374 | putGST( PPC_GST_LR, e_nia ); |
sewardj | b51f0f4 | 2005-07-18 11:38:02 +0000 | [diff] [blame] | 4375 | |
| 4376 | stmt( IRStmt_Exit( |
| 4377 | binop(Iop_CmpEQ32, mkexpr(do_branch), mkU32(0)), |
| 4378 | Ijk_Boring, |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 4379 | c_nia )); |
sewardj | b51f0f4 | 2005-07-18 11:38:02 +0000 | [diff] [blame] | 4380 | |
sewardj | cf8986c | 2006-01-18 04:14:52 +0000 | [diff] [blame] | 4381 | if (vanilla_return && mode64) |
| 4382 | make_redzone_AbiHint( "branch-to-lr (unconditional return)" ); |
| 4383 | |
sewardj | d37be03 | 2005-11-12 12:56:31 +0000 | [diff] [blame] | 4384 | /* blrl is pretty strange; it's like a return that sets the |
| 4385 | return address of its caller to the insn following this |
| 4386 | one. Mark it as a return. */ |
| 4387 | irbb->jumpkind = Ijk_Ret; /* was flag_LK ? Ijk_Call : Ijk_Ret; */ |
sewardj | df07b88 | 2005-11-29 18:19:11 +0000 | [diff] [blame] | 4388 | irbb->next = mkexpr(lr_old); |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 4389 | break; |
sewardj | cf8986c | 2006-01-18 04:14:52 +0000 | [diff] [blame] | 4390 | } |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 4391 | default: |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 4392 | vex_printf("dis_int_branch(ppc)(opc2)\n"); |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 4393 | return False; |
| 4394 | } |
| 4395 | break; |
cerion | 2831b00 | 2005-11-30 19:55:22 +0000 | [diff] [blame] | 4396 | |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 4397 | default: |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 4398 | vex_printf("dis_int_branch(ppc)(opc1)\n"); |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 4399 | return False; |
| 4400 | } |
cerion | 2831b00 | 2005-11-30 19:55:22 +0000 | [diff] [blame] | 4401 | |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 4402 | return True; |
cerion | 91ad536 | 2005-01-27 23:02:41 +0000 | [diff] [blame] | 4403 | } |
| 4404 | |
| 4405 | |
| 4406 | |
cerion | 3d870a3 | 2005-03-18 12:23:33 +0000 | [diff] [blame] | 4407 | /* |
| 4408 | Condition Register Logical Instructions |
| 4409 | */ |
cerion | 3007c7f | 2005-02-23 23:13:29 +0000 | [diff] [blame] | 4410 | static Bool dis_cond_logic ( UInt theInstr ) |
| 4411 | { |
| 4412 | /* XL-Form */ |
cerion | 76de5cf | 2005-11-18 18:25:12 +0000 | [diff] [blame] | 4413 | UChar opc1 = ifieldOPC(theInstr); |
| 4414 | UChar crbD_addr = ifieldRegDS(theInstr); |
| 4415 | UChar crfD_addr = toUChar( IFIELD(theInstr, 23, 3) ); |
| 4416 | UChar crbA_addr = ifieldRegA(theInstr); |
| 4417 | UChar crfS_addr = toUChar( IFIELD(theInstr, 18, 3) ); |
| 4418 | UChar crbB_addr = ifieldRegB(theInstr); |
| 4419 | UInt opc2 = ifieldOPClo10(theInstr); |
| 4420 | UChar b0 = ifieldBIT0(theInstr); |
cerion | 3007c7f | 2005-02-23 23:13:29 +0000 | [diff] [blame] | 4421 | |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 4422 | IRTemp crbD = newTemp(Ity_I32); |
| 4423 | IRTemp crbA = newTemp(Ity_I32); |
| 4424 | IRTemp crbB = newTemp(Ity_I32); |
cerion | 3007c7f | 2005-02-23 23:13:29 +0000 | [diff] [blame] | 4425 | |
| 4426 | if (opc1 != 19 || b0 != 0) { |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 4427 | vex_printf("dis_cond_logic(ppc)(opc1)\n"); |
cerion | 3007c7f | 2005-02-23 23:13:29 +0000 | [diff] [blame] | 4428 | return False; |
| 4429 | } |
| 4430 | |
cerion | e9d361a | 2005-03-04 17:35:29 +0000 | [diff] [blame] | 4431 | if (opc2 == 0) { // mcrf (Move Cond Reg Field, PPC32 p464) |
cerion | 3007c7f | 2005-02-23 23:13:29 +0000 | [diff] [blame] | 4432 | if (((crbD_addr & 0x3) != 0) || |
cerion | 76de5cf | 2005-11-18 18:25:12 +0000 | [diff] [blame] | 4433 | ((crbA_addr & 0x3) != 0) || (crbB_addr != 0)) { |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 4434 | vex_printf("dis_cond_logic(ppc)(crbD|crbA|crbB != 0)\n"); |
cerion | 3007c7f | 2005-02-23 23:13:29 +0000 | [diff] [blame] | 4435 | return False; |
cerion | 76de5cf | 2005-11-18 18:25:12 +0000 | [diff] [blame] | 4436 | } |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 4437 | DIP("mcrf cr%u,cr%u\n", crfD_addr, crfS_addr); |
sewardj | b51f0f4 | 2005-07-18 11:38:02 +0000 | [diff] [blame] | 4438 | putCR0( crfD_addr, getCR0( crfS_addr) ); |
| 4439 | putCR321( crfD_addr, getCR321(crfS_addr) ); |
cerion | 3007c7f | 2005-02-23 23:13:29 +0000 | [diff] [blame] | 4440 | } else { |
sewardj | b51f0f4 | 2005-07-18 11:38:02 +0000 | [diff] [blame] | 4441 | assign( crbA, getCRbit(crbA_addr) ); |
cerion | a50fde5 | 2005-07-01 21:16:10 +0000 | [diff] [blame] | 4442 | if (crbA_addr == crbB_addr) |
sewardj | b51f0f4 | 2005-07-18 11:38:02 +0000 | [diff] [blame] | 4443 | crbB = crbA; |
cerion | a50fde5 | 2005-07-01 21:16:10 +0000 | [diff] [blame] | 4444 | else |
sewardj | b51f0f4 | 2005-07-18 11:38:02 +0000 | [diff] [blame] | 4445 | assign( crbB, getCRbit(crbB_addr) ); |
cerion | 3007c7f | 2005-02-23 23:13:29 +0000 | [diff] [blame] | 4446 | |
| 4447 | switch (opc2) { |
sewardj | 7c2dc71 | 2005-09-08 17:33:27 +0000 | [diff] [blame] | 4448 | case 0x101: // crand (Cond Reg AND, PPC32 p372) |
| 4449 | DIP("crand crb%d,crb%d,crb%d\n", crbD_addr, crbA_addr, crbB_addr); |
| 4450 | assign( crbD, binop(Iop_And32, mkexpr(crbA), mkexpr(crbB)) ); |
| 4451 | break; |
sewardj | 7787af4 | 2005-08-04 18:32:19 +0000 | [diff] [blame] | 4452 | case 0x081: // crandc (Cond Reg AND w. Complement, PPC32 p373) |
| 4453 | DIP("crandc crb%d,crb%d,crb%d\n", crbD_addr, crbA_addr, crbB_addr); |
| 4454 | assign( crbD, binop(Iop_And32, |
| 4455 | mkexpr(crbA), |
| 4456 | unop(Iop_Not32, mkexpr(crbB))) ); |
| 4457 | break; |
sewardj | e14bb9f | 2005-07-22 09:39:02 +0000 | [diff] [blame] | 4458 | case 0x121: // creqv (Cond Reg Equivalent, PPC32 p374) |
| 4459 | DIP("creqv crb%d,crb%d,crb%d\n", crbD_addr, crbA_addr, crbB_addr); |
| 4460 | assign( crbD, unop(Iop_Not32, |
| 4461 | binop(Iop_Xor32, mkexpr(crbA), mkexpr(crbB))) ); |
| 4462 | break; |
sewardj | 7c2dc71 | 2005-09-08 17:33:27 +0000 | [diff] [blame] | 4463 | case 0x0E1: // crnand (Cond Reg NAND, PPC32 p375) |
| 4464 | DIP("crnand crb%d,crb%d,crb%d\n", crbD_addr, crbA_addr, crbB_addr); |
| 4465 | assign( crbD, unop(Iop_Not32, |
| 4466 | binop(Iop_And32, mkexpr(crbA), mkexpr(crbB))) ); |
| 4467 | break; |
cerion | e9d361a | 2005-03-04 17:35:29 +0000 | [diff] [blame] | 4468 | case 0x021: // crnor (Cond Reg NOR, PPC32 p376) |
cerion | 3007c7f | 2005-02-23 23:13:29 +0000 | [diff] [blame] | 4469 | DIP("crnor crb%d,crb%d,crb%d\n", crbD_addr, crbA_addr, crbB_addr); |
| 4470 | assign( crbD, unop(Iop_Not32, |
| 4471 | binop(Iop_Or32, mkexpr(crbA), mkexpr(crbB))) ); |
| 4472 | break; |
cerion | e9d361a | 2005-03-04 17:35:29 +0000 | [diff] [blame] | 4473 | case 0x1C1: // cror (Cond Reg OR, PPC32 p377) |
cerion | 3007c7f | 2005-02-23 23:13:29 +0000 | [diff] [blame] | 4474 | DIP("cror crb%d,crb%d,crb%d\n", crbD_addr, crbA_addr, crbB_addr); |
| 4475 | assign( crbD, binop(Iop_Or32, mkexpr(crbA), mkexpr(crbB)) ); |
| 4476 | break; |
sewardj | 7c2dc71 | 2005-09-08 17:33:27 +0000 | [diff] [blame] | 4477 | case 0x1A1: // crorc (Cond Reg OR w. Complement, PPC32 p378) |
| 4478 | DIP("crorc crb%d,crb%d,crb%d\n", crbD_addr, crbA_addr, crbB_addr); |
| 4479 | assign( crbD, binop(Iop_Or32, |
| 4480 | mkexpr(crbA), |
| 4481 | unop(Iop_Not32, mkexpr(crbB))) ); |
| 4482 | break; |
cerion | e9d361a | 2005-03-04 17:35:29 +0000 | [diff] [blame] | 4483 | case 0x0C1: // crxor (Cond Reg XOR, PPC32 p379) |
cerion | 3007c7f | 2005-02-23 23:13:29 +0000 | [diff] [blame] | 4484 | DIP("crxor crb%d,crb%d,crb%d\n", crbD_addr, crbA_addr, crbB_addr); |
| 4485 | assign( crbD, binop(Iop_Xor32, mkexpr(crbA), mkexpr(crbB)) ); |
| 4486 | break; |
cerion | 3007c7f | 2005-02-23 23:13:29 +0000 | [diff] [blame] | 4487 | default: |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 4488 | vex_printf("dis_cond_logic(ppc)(opc2)\n"); |
cerion | 3007c7f | 2005-02-23 23:13:29 +0000 | [diff] [blame] | 4489 | return False; |
| 4490 | } |
| 4491 | |
sewardj | b51f0f4 | 2005-07-18 11:38:02 +0000 | [diff] [blame] | 4492 | putCRbit( crbD_addr, mkexpr(crbD) ); |
cerion | 3007c7f | 2005-02-23 23:13:29 +0000 | [diff] [blame] | 4493 | } |
| 4494 | return True; |
| 4495 | } |
| 4496 | |
| 4497 | |
sewardj | 334870d | 2006-02-07 16:42:39 +0000 | [diff] [blame] | 4498 | /* |
| 4499 | Trap instructions |
| 4500 | */ |
| 4501 | |
| 4502 | /* Do the code generation for a trap. Returned Bool is true iff |
| 4503 | this is an unconditional trap. */ |
sewardj | 2d19fe3 | 2006-02-07 20:55:08 +0000 | [diff] [blame] | 4504 | static Bool do_trap ( Bool is_twi, UChar TO, |
sewardj | 334870d | 2006-02-07 16:42:39 +0000 | [diff] [blame] | 4505 | IRExpr* argL0, ULong argR0, Addr64 cia ) |
| 4506 | { |
| 4507 | IRTemp argL, argR; |
| 4508 | IRExpr *argLe, *argRe, *cond, *tmp; |
| 4509 | |
sewardj | 2d19fe3 | 2006-02-07 20:55:08 +0000 | [diff] [blame] | 4510 | IROp opAND = is_twi ? Iop_And32 : Iop_And64; |
| 4511 | IROp opOR = is_twi ? Iop_Or32 : Iop_Or64; |
| 4512 | IROp opCMPORDS = is_twi ? Iop_CmpORD32S : Iop_CmpORD64S; |
| 4513 | IROp opCMPORDU = is_twi ? Iop_CmpORD32U : Iop_CmpORD64U; |
| 4514 | IROp opCMPNE = is_twi ? Iop_CmpNE32 : Iop_CmpNE64; |
| 4515 | IROp opCMPEQ = is_twi ? Iop_CmpEQ32 : Iop_CmpEQ64; |
| 4516 | IRExpr* const0 = is_twi ? mkU32(0) : mkU64(0); |
| 4517 | IRExpr* const2 = is_twi ? mkU32(2) : mkU64(2); |
| 4518 | IRExpr* const4 = is_twi ? mkU32(4) : mkU64(4); |
| 4519 | IRExpr* const8 = is_twi ? mkU32(8) : mkU64(8); |
sewardj | 334870d | 2006-02-07 16:42:39 +0000 | [diff] [blame] | 4520 | |
| 4521 | const UChar b11100 = 0x1C; |
| 4522 | const UChar b00111 = 0x07; |
| 4523 | |
| 4524 | if ((TO & b11100) == b11100 || (TO & b00111) == b00111) { |
| 4525 | /* Unconditional trap. Just do the exit without |
| 4526 | testing the arguments. */ |
| 4527 | stmt( IRStmt_Exit( |
| 4528 | binop(opCMPEQ, const0, const0), |
| 4529 | Ijk_Trap, |
| 4530 | mode64 ? IRConst_U64(cia) : IRConst_U32((UInt)cia) |
| 4531 | )); |
| 4532 | return True; /* unconditional trap */ |
| 4533 | } |
| 4534 | |
sewardj | 2d19fe3 | 2006-02-07 20:55:08 +0000 | [diff] [blame] | 4535 | if (is_twi) { |
| 4536 | argL = newTemp(Ity_I32); |
| 4537 | argR = newTemp(Ity_I32); |
| 4538 | assign( argL, mode64 ? mkSzNarrow32(Ity_I64,argL0) |
| 4539 | : argL0 ); |
sewardj | 334870d | 2006-02-07 16:42:39 +0000 | [diff] [blame] | 4540 | assign( argR, mkU32( (UInt)argR0 )); |
| 4541 | } else { |
| 4542 | vassert(mode64); |
sewardj | 2d19fe3 | 2006-02-07 20:55:08 +0000 | [diff] [blame] | 4543 | argL = newTemp(Ity_I64); |
| 4544 | argR = newTemp(Ity_I64); |
sewardj | 334870d | 2006-02-07 16:42:39 +0000 | [diff] [blame] | 4545 | assign( argL, argL0 ); |
| 4546 | assign( argR, mkU64( argR0 )); |
| 4547 | } |
| 4548 | argLe = mkexpr(argL); |
| 4549 | argRe = mkexpr(argR); |
| 4550 | cond = const0; |
| 4551 | if (TO & 16) { // L <s R |
| 4552 | tmp = binop(opAND, binop(opCMPORDS, argLe, argRe), const8); |
| 4553 | cond = binop(opOR, tmp, cond); |
| 4554 | } |
| 4555 | if (TO & 8) { // L >s R |
| 4556 | tmp = binop(opAND, binop(opCMPORDS, argLe, argRe), const4); |
| 4557 | cond = binop(opOR, tmp, cond); |
| 4558 | } |
| 4559 | if (TO & 4) { // L == R |
| 4560 | tmp = binop(opAND, binop(opCMPORDS, argLe, argRe), const2); |
| 4561 | cond = binop(opOR, tmp, cond); |
| 4562 | } |
| 4563 | if (TO & 2) { // L <u R |
| 4564 | tmp = binop(opAND, binop(opCMPORDU, argLe, argRe), const8); |
| 4565 | cond = binop(opOR, tmp, cond); |
| 4566 | } |
| 4567 | if (TO & 1) { // L >u R |
| 4568 | tmp = binop(opAND, binop(opCMPORDU, argLe, argRe), const4); |
| 4569 | cond = binop(opOR, tmp, cond); |
| 4570 | } |
| 4571 | stmt( IRStmt_Exit( |
| 4572 | binop(opCMPNE, cond, const0), |
| 4573 | Ijk_Trap, |
| 4574 | mode64 ? IRConst_U64(cia) : IRConst_U32((UInt)cia) |
| 4575 | )); |
| 4576 | return False; /* not an unconditional trap */ |
| 4577 | } |
| 4578 | |
| 4579 | static Bool dis_trapi ( UInt theInstr, |
| 4580 | /*OUT*/DisResult* dres ) |
| 4581 | { |
| 4582 | /* D-Form */ |
| 4583 | UChar opc1 = ifieldOPC(theInstr); |
| 4584 | UChar TO = ifieldRegDS(theInstr); |
| 4585 | UChar rA_addr = ifieldRegA(theInstr); |
| 4586 | UInt uimm16 = ifieldUIMM16(theInstr); |
| 4587 | ULong simm16 = extend_s_16to64(uimm16); |
| 4588 | Addr64 cia = guest_CIA_curr_instr; |
| 4589 | IRType ty = mode64 ? Ity_I64 : Ity_I32; |
| 4590 | Bool uncond = False; |
| 4591 | |
| 4592 | switch (opc1) { |
| 4593 | case 0x03: // twi (Trap Word Immediate, PPC32 p548) |
sewardj | 2d19fe3 | 2006-02-07 20:55:08 +0000 | [diff] [blame] | 4594 | uncond = do_trap( True/*is_twi*/, TO, getIReg(rA_addr), simm16, cia ); |
sewardj | 334870d | 2006-02-07 16:42:39 +0000 | [diff] [blame] | 4595 | if (TO == 4) { |
| 4596 | DIP("tweqi r%u,%d\n", (UInt)rA_addr, (Int)simm16); |
| 4597 | } else { |
| 4598 | DIP("tw%di r%u,%d\n", (Int)TO, (UInt)rA_addr, (Int)simm16); |
| 4599 | } |
| 4600 | break; |
| 4601 | case 0x02: // tdi |
| 4602 | if (!mode64) |
| 4603 | return False; |
sewardj | 2d19fe3 | 2006-02-07 20:55:08 +0000 | [diff] [blame] | 4604 | uncond = do_trap( False/*!is_twi*/, TO, getIReg(rA_addr), simm16, cia ); |
| 4605 | if (TO == 4) { |
| 4606 | DIP("tdeqi r%u,%d\n", (UInt)rA_addr, (Int)simm16); |
| 4607 | } else { |
| 4608 | DIP("td%di r%u,%d\n", (Int)TO, (UInt)rA_addr, (Int)simm16); |
| 4609 | } |
sewardj | 334870d | 2006-02-07 16:42:39 +0000 | [diff] [blame] | 4610 | break; |
| 4611 | default: |
| 4612 | return False; |
| 4613 | } |
| 4614 | |
| 4615 | if (uncond) { |
| 4616 | /* If the trap shows signs of being unconditional, don't |
| 4617 | continue decoding past it. */ |
| 4618 | irbb->next = mkSzImm( ty, nextInsnAddr() ); |
| 4619 | irbb->jumpkind = Ijk_Boring; |
| 4620 | dres->whatNext = Dis_StopHere; |
| 4621 | } |
| 4622 | |
| 4623 | return True; |
| 4624 | } |
| 4625 | |
| 4626 | |
cerion | 3d870a3 | 2005-03-18 12:23:33 +0000 | [diff] [blame] | 4627 | /* |
| 4628 | System Linkage Instructions |
| 4629 | */ |
sewardj | 9e6491a | 2005-07-02 19:24:10 +0000 | [diff] [blame] | 4630 | static Bool dis_syslink ( UInt theInstr, DisResult* dres ) |
cerion | 8c3adda | 2005-01-31 11:54:05 +0000 | [diff] [blame] | 4631 | { |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 4632 | IRType ty = mode64 ? Ity_I64 : Ity_I32; |
| 4633 | |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 4634 | if (theInstr != 0x44000002) { |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 4635 | vex_printf("dis_syslink(ppc)(theInstr)\n"); |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 4636 | return False; |
| 4637 | } |
cerion | e1d857b | 2005-02-04 18:29:05 +0000 | [diff] [blame] | 4638 | |
cerion | e9d361a | 2005-03-04 17:35:29 +0000 | [diff] [blame] | 4639 | // sc (System Call, PPC32 p504) |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 4640 | DIP("sc\n"); |
| 4641 | |
| 4642 | /* It's important that all ArchRegs carry their up-to-date value |
| 4643 | at this point. So we declare an end-of-block here, which |
| 4644 | forces any TempRegs caching ArchRegs to be flushed. */ |
cerion | 2831b00 | 2005-11-30 19:55:22 +0000 | [diff] [blame] | 4645 | irbb->next = mkSzImm( ty, nextInsnAddr() ); |
sewardj | 4fa325a | 2005-11-03 13:27:24 +0000 | [diff] [blame] | 4646 | irbb->jumpkind = Ijk_Sys_syscall; |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 4647 | |
sewardj | 9e6491a | 2005-07-02 19:24:10 +0000 | [diff] [blame] | 4648 | dres->whatNext = Dis_StopHere; |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 4649 | return True; |
cerion | 8c3adda | 2005-01-31 11:54:05 +0000 | [diff] [blame] | 4650 | } |
| 4651 | |
cerion | 3d870a3 | 2005-03-18 12:23:33 +0000 | [diff] [blame] | 4652 | |
| 4653 | /* |
| 4654 | Memory Synchronization Instructions |
cerion | 07b07a9 | 2005-12-22 14:32:35 +0000 | [diff] [blame] | 4655 | |
| 4656 | Note on Reservations: |
| 4657 | We rely on the assumption that V will in fact only allow one thread at |
| 4658 | once to run. In effect, a thread can make a reservation, but we don't |
| 4659 | check any stores it does. Instead, the reservation is cancelled when |
| 4660 | the scheduler switches to another thread (run_thread_for_a_while()). |
cerion | 3d870a3 | 2005-03-18 12:23:33 +0000 | [diff] [blame] | 4661 | */ |
cerion | 8c3adda | 2005-01-31 11:54:05 +0000 | [diff] [blame] | 4662 | static Bool dis_memsync ( UInt theInstr ) |
| 4663 | { |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 4664 | /* X-Form, XL-Form */ |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 4665 | UChar opc1 = ifieldOPC(theInstr); |
| 4666 | UInt b11to25 = IFIELD(theInstr, 11, 15); |
cerion | e43bc88 | 2006-01-05 13:11:59 +0000 | [diff] [blame] | 4667 | UChar flag_L = ifieldRegDS(theInstr); |
| 4668 | UInt b11to20 = IFIELD(theInstr, 11, 10); |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 4669 | UChar rD_addr = ifieldRegDS(theInstr); |
| 4670 | UChar rS_addr = rD_addr; |
| 4671 | UChar rA_addr = ifieldRegA(theInstr); |
| 4672 | UChar rB_addr = ifieldRegB(theInstr); |
| 4673 | UInt opc2 = ifieldOPClo10(theInstr); |
| 4674 | UChar b0 = ifieldBIT0(theInstr); |
cerion | edf7fc5 | 2005-11-18 20:57:41 +0000 | [diff] [blame] | 4675 | |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 4676 | IRType ty = mode64 ? Ity_I64 : Ity_I32; |
| 4677 | IRTemp EA = newTemp(ty); |
| 4678 | IRTemp rS = newTemp(ty); |
| 4679 | |
| 4680 | assign( EA, ea_rAor0_idxd( rA_addr, rB_addr ) ); |
| 4681 | |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 4682 | switch (opc1) { |
sewardj | afe8583 | 2005-09-09 10:25:39 +0000 | [diff] [blame] | 4683 | /* XL-Form */ |
cerion | e9d361a | 2005-03-04 17:35:29 +0000 | [diff] [blame] | 4684 | case 0x13: // isync (Instruction Synchronize, PPC32 p432) |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 4685 | if (opc2 != 0x096) { |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 4686 | vex_printf("dis_memsync(ppc)(0x13,opc2)\n"); |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 4687 | return False; |
| 4688 | } |
| 4689 | if (b11to25 != 0 || b0 != 0) { |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 4690 | vex_printf("dis_memsync(ppc)(0x13,b11to25|b0)\n"); |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 4691 | return False; |
| 4692 | } |
| 4693 | DIP("isync\n"); |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 4694 | stmt( IRStmt_MFence() ); |
| 4695 | break; |
cerion | 8c3adda | 2005-01-31 11:54:05 +0000 | [diff] [blame] | 4696 | |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 4697 | /* X-Form */ |
| 4698 | case 0x1F: |
| 4699 | switch (opc2) { |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 4700 | case 0x356: // eieio (Enforce In-Order Exec of I/O, PPC32 p394) |
sewardj | 7787af4 | 2005-08-04 18:32:19 +0000 | [diff] [blame] | 4701 | if (b11to25 != 0 || b0 != 0) { |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 4702 | vex_printf("dis_memsync(ppc)(eiei0,b11to25|b0)\n"); |
sewardj | 7787af4 | 2005-08-04 18:32:19 +0000 | [diff] [blame] | 4703 | return False; |
| 4704 | } |
| 4705 | DIP("eieio\n"); |
| 4706 | /* Insert a memory fence, just to be on the safe side. */ |
| 4707 | stmt( IRStmt_MFence() ); |
| 4708 | break; |
cerion | 8c3adda | 2005-01-31 11:54:05 +0000 | [diff] [blame] | 4709 | |
cerion | e9d361a | 2005-03-04 17:35:29 +0000 | [diff] [blame] | 4710 | case 0x014: // lwarx (Load Word and Reserve Indexed, PPC32 p458) |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 4711 | if (b0 != 0) { |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 4712 | vex_printf("dis_memsync(ppc)(lwarx,b0)\n"); |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 4713 | return False; |
| 4714 | } |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 4715 | DIP("lwarx r%u,r%u,r%u\n", rD_addr, rA_addr, rB_addr); |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 4716 | putIReg( rD_addr, mkSzWiden32(ty, loadBE(Ity_I32, mkexpr(EA)), |
| 4717 | False) ); |
cerion | 76de5cf | 2005-11-18 18:25:12 +0000 | [diff] [blame] | 4718 | /* Take a reservation */ |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 4719 | putGST( PPC_GST_RESVN, mkexpr(EA) ); |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 4720 | break; |
| 4721 | |
sewardj | 7787af4 | 2005-08-04 18:32:19 +0000 | [diff] [blame] | 4722 | case 0x096: { |
| 4723 | // stwcx. (Store Word Conditional Indexed, PPC32 p532) |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 4724 | IRTemp resaddr = newTemp(ty); |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 4725 | if (b0 != 1) { |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 4726 | vex_printf("dis_memsync(ppc)(stwcx.,b0)\n"); |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 4727 | return False; |
| 4728 | } |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 4729 | DIP("stwcx. r%u,r%u,r%u\n", rS_addr, rA_addr, rB_addr); |
cerion | 76de5cf | 2005-11-18 18:25:12 +0000 | [diff] [blame] | 4730 | assign( rS, getIReg(rS_addr) ); |
sewardj | afe8583 | 2005-09-09 10:25:39 +0000 | [diff] [blame] | 4731 | |
cerion | 76de5cf | 2005-11-18 18:25:12 +0000 | [diff] [blame] | 4732 | /* First set up as if the reservation failed */ |
sewardj | 7787af4 | 2005-08-04 18:32:19 +0000 | [diff] [blame] | 4733 | // Set CR0[LT GT EQ S0] = 0b000 || XER[SO] |
| 4734 | putCR321(0, mkU8(0<<1)); |
| 4735 | putCR0(0, getXER_SO()); |
| 4736 | |
cerion | 76de5cf | 2005-11-18 18:25:12 +0000 | [diff] [blame] | 4737 | /* Get the reservation address into a temporary, then |
| 4738 | clear it. */ |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 4739 | assign( resaddr, getGST(PPC_GST_RESVN) ); |
cerion | 2831b00 | 2005-11-30 19:55:22 +0000 | [diff] [blame] | 4740 | putGST( PPC_GST_RESVN, mkSzImm(ty, 0) ); |
sewardj | 7787af4 | 2005-08-04 18:32:19 +0000 | [diff] [blame] | 4741 | |
cerion | 76de5cf | 2005-11-18 18:25:12 +0000 | [diff] [blame] | 4742 | /* Skip the rest if the reservation really did fail. */ |
sewardj | 7787af4 | 2005-08-04 18:32:19 +0000 | [diff] [blame] | 4743 | stmt( IRStmt_Exit( |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 4744 | ( mode64 ? |
| 4745 | binop(Iop_CmpNE64, mkexpr(resaddr), mkexpr(EA)) : |
| 4746 | binop(Iop_CmpNE32, mkexpr(resaddr), mkexpr(EA)) ), |
sewardj | 7787af4 | 2005-08-04 18:32:19 +0000 | [diff] [blame] | 4747 | Ijk_Boring, |
cerion | 2831b00 | 2005-11-30 19:55:22 +0000 | [diff] [blame] | 4748 | mkSzConst( ty, nextInsnAddr()) )); |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 4749 | |
| 4750 | /* Note for mode64: |
| 4751 | If resaddr != lwarx_resaddr, CR0[EQ] is undefined, and |
| 4752 | whether rS is stored is dependent on that value. */ |
sewardj | 7787af4 | 2005-08-04 18:32:19 +0000 | [diff] [blame] | 4753 | |
cerion | 4e2c2b3 | 2006-01-02 13:35:51 +0000 | [diff] [blame] | 4754 | /* Success? Do the (32bit) store */ |
| 4755 | storeBE( mkexpr(EA), mkSzNarrow32(ty, mkexpr(rS)) ); |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 4756 | |
sewardj | b51f0f4 | 2005-07-18 11:38:02 +0000 | [diff] [blame] | 4757 | // Set CR0[LT GT EQ S0] = 0b001 || XER[SO] |
| 4758 | putCR321(0, mkU8(1<<1)); |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 4759 | break; |
sewardj | 7787af4 | 2005-08-04 18:32:19 +0000 | [diff] [blame] | 4760 | } |
| 4761 | |
sewardj | b029a61 | 2005-12-30 15:04:29 +0000 | [diff] [blame] | 4762 | case 0x256: // sync (Synchronize, PPC32 p543), |
cerion | e43bc88 | 2006-01-05 13:11:59 +0000 | [diff] [blame] | 4763 | // also lwsync (L==1), ptesync (L==2) |
sewardj | b029a61 | 2005-12-30 15:04:29 +0000 | [diff] [blame] | 4764 | /* http://sources.redhat.com/ml/binutils/2000-12/msg00311.html |
| 4765 | |
| 4766 | The PowerPC architecture used in IBM chips has expanded |
| 4767 | the sync instruction into two variants: lightweight sync |
| 4768 | and heavyweight sync. The original sync instruction is |
| 4769 | the new heavyweight sync and lightweight sync is a strict |
| 4770 | subset of the heavyweight sync functionality. This allows |
| 4771 | the programmer to specify a less expensive operation on |
| 4772 | high-end systems when the full sync functionality is not |
| 4773 | necessary. |
| 4774 | |
| 4775 | The basic "sync" mnemonic now utilizes an operand. "sync" |
| 4776 | without an operand now becomes a extended mnemonic for |
| 4777 | heavyweight sync. Processors without the lwsync |
| 4778 | instruction will not decode the L field and will perform a |
| 4779 | heavyweight sync. Everything is backward compatible. |
| 4780 | |
| 4781 | sync = sync 0 |
| 4782 | lwsync = sync 1 |
cerion | e43bc88 | 2006-01-05 13:11:59 +0000 | [diff] [blame] | 4783 | ptesync = sync 2 *** TODO - not implemented *** |
cerion | 4e2c2b3 | 2006-01-02 13:35:51 +0000 | [diff] [blame] | 4784 | */ |
cerion | e43bc88 | 2006-01-05 13:11:59 +0000 | [diff] [blame] | 4785 | if (b11to20 != 0 || b0 != 0) { |
| 4786 | vex_printf("dis_memsync(ppc)(sync/lwsync,b11to20|b0)\n"); |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 4787 | return False; |
| 4788 | } |
cerion | e43bc88 | 2006-01-05 13:11:59 +0000 | [diff] [blame] | 4789 | if (flag_L != 0/*sync*/ && flag_L != 1/*lwsync*/) { |
| 4790 | vex_printf("dis_memsync(ppc)(sync/lwsync,flag_L)\n"); |
| 4791 | return False; |
| 4792 | } |
| 4793 | DIP("%ssync\n", flag_L == 1 ? "lw" : ""); |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 4794 | /* Insert a memory fence. It's sometimes important that these |
| 4795 | are carried through to the generated code. */ |
| 4796 | stmt( IRStmt_MFence() ); |
| 4797 | break; |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 4798 | |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 4799 | /* 64bit Memsync */ |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 4800 | case 0x054: // ldarx (Load DWord and Reserve Indexed, PPC64 p473) |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 4801 | if (b0 != 0) { |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 4802 | vex_printf("dis_memsync(ppc)(ldarx,b0)\n"); |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 4803 | return False; |
| 4804 | } |
| 4805 | DIP("ldarx r%u,r%u,r%u\n", rD_addr, rA_addr, rB_addr); |
cerion | 07b07a9 | 2005-12-22 14:32:35 +0000 | [diff] [blame] | 4806 | putIReg( rD_addr, loadBE(Ity_I64, mkexpr(EA)) ); |
| 4807 | // Take a reservation |
| 4808 | putGST( PPC_GST_RESVN, mkexpr(EA) ); |
| 4809 | break; |
| 4810 | |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 4811 | case 0x0D6: { // stdcx. (Store DWord Condition Indexd, PPC64 p581) |
cerion | 07b07a9 | 2005-12-22 14:32:35 +0000 | [diff] [blame] | 4812 | IRTemp resaddr = newTemp(ty); |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 4813 | if (b0 != 1) { |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 4814 | vex_printf("dis_memsync(ppc)(stdcx.,b0)\n"); |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 4815 | return False; |
| 4816 | } |
| 4817 | DIP("stdcx. r%u,r%u,r%u\n", rS_addr, rA_addr, rB_addr); |
cerion | 07b07a9 | 2005-12-22 14:32:35 +0000 | [diff] [blame] | 4818 | assign( rS, getIReg(rS_addr) ); |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 4819 | |
cerion | 07b07a9 | 2005-12-22 14:32:35 +0000 | [diff] [blame] | 4820 | // First set up as if the reservation failed |
| 4821 | // Set CR0[LT GT EQ S0] = 0b000 || XER[SO] |
| 4822 | putCR321(0, mkU8(0<<1)); |
| 4823 | putCR0(0, getXER_SO()); |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 4824 | |
cerion | 07b07a9 | 2005-12-22 14:32:35 +0000 | [diff] [blame] | 4825 | // Get the reservation address into a temporary, then clear it. |
| 4826 | assign( resaddr, getGST(PPC_GST_RESVN) ); |
| 4827 | putGST( PPC_GST_RESVN, mkSzImm(ty, 0) ); |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 4828 | |
cerion | 07b07a9 | 2005-12-22 14:32:35 +0000 | [diff] [blame] | 4829 | // Skip the rest if the reservation really did fail. |
| 4830 | stmt( IRStmt_Exit( binop(Iop_CmpNE64, mkexpr(resaddr), |
| 4831 | mkexpr(EA)), |
| 4832 | Ijk_Boring, |
| 4833 | IRConst_U64(nextInsnAddr())) ); |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 4834 | |
cerion | 07b07a9 | 2005-12-22 14:32:35 +0000 | [diff] [blame] | 4835 | // Success? Do the store |
| 4836 | storeBE( mkexpr(EA), mkexpr(rS) ); |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 4837 | |
cerion | 07b07a9 | 2005-12-22 14:32:35 +0000 | [diff] [blame] | 4838 | // Set CR0[LT GT EQ S0] = 0b001 || XER[SO] |
| 4839 | putCR321(0, mkU8(1<<1)); |
| 4840 | break; |
| 4841 | } |
| 4842 | |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 4843 | default: |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 4844 | vex_printf("dis_memsync(ppc)(opc2)\n"); |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 4845 | return False; |
| 4846 | } |
| 4847 | break; |
cerion | 8c3adda | 2005-01-31 11:54:05 +0000 | [diff] [blame] | 4848 | |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 4849 | default: |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 4850 | vex_printf("dis_memsync(ppc)(opc1)\n"); |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 4851 | return False; |
| 4852 | } |
| 4853 | return True; |
cerion | 8c3adda | 2005-01-31 11:54:05 +0000 | [diff] [blame] | 4854 | } |
| 4855 | |
| 4856 | |
| 4857 | |
cerion | 3d870a3 | 2005-03-18 12:23:33 +0000 | [diff] [blame] | 4858 | /* |
| 4859 | Integer Shift Instructions |
| 4860 | */ |
cerion | 645c930 | 2005-01-31 10:09:59 +0000 | [diff] [blame] | 4861 | static Bool dis_int_shift ( UInt theInstr ) |
| 4862 | { |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 4863 | /* X-Form, XS-Form */ |
cerion | 76de5cf | 2005-11-18 18:25:12 +0000 | [diff] [blame] | 4864 | UChar opc1 = ifieldOPC(theInstr); |
| 4865 | UChar rS_addr = ifieldRegDS(theInstr); |
| 4866 | UChar rA_addr = ifieldRegA(theInstr); |
| 4867 | UChar rB_addr = ifieldRegB(theInstr); |
| 4868 | UChar sh_imm = rB_addr; |
| 4869 | UInt opc2 = ifieldOPClo10(theInstr); |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 4870 | UChar b1 = ifieldBIT1(theInstr); |
cerion | 76de5cf | 2005-11-18 18:25:12 +0000 | [diff] [blame] | 4871 | UChar flag_rC = ifieldBIT0(theInstr); |
| 4872 | |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 4873 | IRType ty = mode64 ? Ity_I64 : Ity_I32; |
| 4874 | IRTemp rA = newTemp(ty); |
cerion | 07b07a9 | 2005-12-22 14:32:35 +0000 | [diff] [blame] | 4875 | IRTemp rS = newTemp(ty); |
| 4876 | IRTemp rB = newTemp(ty); |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 4877 | IRTemp outofrange = newTemp(Ity_I8); |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 4878 | IRTemp rS_lo32 = newTemp(Ity_I32); |
| 4879 | IRTemp rB_lo32 = newTemp(Ity_I32); |
| 4880 | IRExpr* e_tmp; |
| 4881 | |
cerion | 07b07a9 | 2005-12-22 14:32:35 +0000 | [diff] [blame] | 4882 | assign( rS, getIReg(rS_addr) ); |
| 4883 | assign( rB, getIReg(rB_addr) ); |
| 4884 | assign( rS_lo32, mkSzNarrow32(ty, mkexpr(rS)) ); |
| 4885 | assign( rB_lo32, mkSzNarrow32(ty, mkexpr(rB)) ); |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 4886 | |
| 4887 | if (opc1 == 0x1F) { |
| 4888 | switch (opc2) { |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 4889 | case 0x018: { // slw (Shift Left Word, PPC32 p505) |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 4890 | DIP("slw%s r%u,r%u,r%u\n", flag_rC ? ".":"", |
cerion | 76de5cf | 2005-11-18 18:25:12 +0000 | [diff] [blame] | 4891 | rA_addr, rS_addr, rB_addr); |
| 4892 | /* rA = rS << rB */ |
| 4893 | /* ppc32 semantics are: |
sewardj | dfb1144 | 2005-10-08 19:58:48 +0000 | [diff] [blame] | 4894 | slw(x,y) = (x << (y & 31)) -- primary result |
| 4895 | & ~((y << 26) >>s 31) -- make result 0 |
| 4896 | for y in 32 .. 63 |
| 4897 | */ |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 4898 | e_tmp = |
| 4899 | binop( Iop_And32, |
| 4900 | binop( Iop_Shl32, |
| 4901 | mkexpr(rS_lo32), |
| 4902 | unop( Iop_32to8, |
| 4903 | binop(Iop_And32, |
| 4904 | mkexpr(rB_lo32), mkU32(31)))), |
| 4905 | unop( Iop_Not32, |
| 4906 | binop( Iop_Sar32, |
| 4907 | binop(Iop_Shl32, mkexpr(rB_lo32), mkU8(26)), |
| 4908 | mkU8(31))) ); |
cerion | 2831b00 | 2005-11-30 19:55:22 +0000 | [diff] [blame] | 4909 | assign( rA, mkSzWiden32(ty, e_tmp, /* Signed */False) ); |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 4910 | break; |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 4911 | } |
| 4912 | |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 4913 | case 0x318: { // sraw (Shift Right Alg Word, PPC32 p506) |
cerion | 07b07a9 | 2005-12-22 14:32:35 +0000 | [diff] [blame] | 4914 | IRTemp sh_amt = newTemp(Ity_I32); |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 4915 | DIP("sraw%s r%u,r%u,r%u\n", flag_rC ? ".":"", |
cerion | 76de5cf | 2005-11-18 18:25:12 +0000 | [diff] [blame] | 4916 | rA_addr, rS_addr, rB_addr); |
cerion | 76de5cf | 2005-11-18 18:25:12 +0000 | [diff] [blame] | 4917 | /* JRS: my reading of the (poorly worded) PPC32 doc p506 is: |
| 4918 | amt = rB & 63 |
| 4919 | rA = Sar32( rS, amt > 31 ? 31 : amt ) |
| 4920 | XER.CA = amt > 31 ? sign-of-rS : (computation as per srawi) |
| 4921 | */ |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 4922 | assign( sh_amt, binop(Iop_And32, mkU32(0x3F), |
| 4923 | mkexpr(rB_lo32)) ); |
cerion | 76de5cf | 2005-11-18 18:25:12 +0000 | [diff] [blame] | 4924 | assign( outofrange, |
sewardj | 20ef547 | 2005-07-21 14:48:31 +0000 | [diff] [blame] | 4925 | unop( Iop_1Uto8, |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 4926 | binop(Iop_CmpLT32U, mkU32(31), |
| 4927 | mkexpr(sh_amt)) )); |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 4928 | e_tmp = binop( Iop_Sar32, |
| 4929 | mkexpr(rS_lo32), |
sewardj | 20ef547 | 2005-07-21 14:48:31 +0000 | [diff] [blame] | 4930 | unop( Iop_32to8, |
| 4931 | IRExpr_Mux0X( mkexpr(outofrange), |
cerion | 07b07a9 | 2005-12-22 14:32:35 +0000 | [diff] [blame] | 4932 | mkexpr(sh_amt), |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 4933 | mkU32(31)) ) ); |
cerion | 2831b00 | 2005-11-30 19:55:22 +0000 | [diff] [blame] | 4934 | assign( rA, mkSzWiden32(ty, e_tmp, /* Signed */True) ); |
| 4935 | |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 4936 | set_XER_CA( ty, PPCG_FLAG_OP_SRAW, |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 4937 | mkexpr(rA), |
| 4938 | mkSzWiden32(ty, mkexpr(rS_lo32), True), |
cerion | 07b07a9 | 2005-12-22 14:32:35 +0000 | [diff] [blame] | 4939 | mkSzWiden32(ty, mkexpr(sh_amt), True ), |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 4940 | mkSzWiden32(ty, getXER_CA32(), True) ); |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 4941 | break; |
cerion | 07b07a9 | 2005-12-22 14:32:35 +0000 | [diff] [blame] | 4942 | } |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 4943 | |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 4944 | case 0x338: // srawi (Shift Right Alg Word Immediate, PPC32 p507) |
| 4945 | DIP("srawi%s r%u,r%u,%d\n", flag_rC ? ".":"", |
cerion | 76de5cf | 2005-11-18 18:25:12 +0000 | [diff] [blame] | 4946 | rA_addr, rS_addr, sh_imm); |
| 4947 | vassert(sh_imm < 32); |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 4948 | if (mode64) { |
| 4949 | assign( rA, binop(Iop_Sar64, |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 4950 | binop(Iop_Shl64, getIReg(rS_addr), |
| 4951 | mkU8(32)), |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 4952 | mkU8(32 + sh_imm)) ); |
| 4953 | } else { |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 4954 | assign( rA, binop(Iop_Sar32, mkexpr(rS_lo32), |
| 4955 | mkU8(sh_imm)) ); |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 4956 | } |
cerion | 2831b00 | 2005-11-30 19:55:22 +0000 | [diff] [blame] | 4957 | |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 4958 | set_XER_CA( ty, PPCG_FLAG_OP_SRAWI, |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 4959 | mkexpr(rA), |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 4960 | mkSzWiden32(ty, mkexpr(rS_lo32), /* Syned */True), |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 4961 | mkSzImm(ty, sh_imm), |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 4962 | mkSzWiden32(ty, getXER_CA32(), /* Syned */False) ); |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 4963 | break; |
| 4964 | |
cerion | e9d361a | 2005-03-04 17:35:29 +0000 | [diff] [blame] | 4965 | case 0x218: // srw (Shift Right Word, PPC32 p508) |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 4966 | DIP("srw%s r%u,r%u,r%u\n", flag_rC ? ".":"", |
cerion | 76de5cf | 2005-11-18 18:25:12 +0000 | [diff] [blame] | 4967 | rA_addr, rS_addr, rB_addr); |
| 4968 | /* rA = rS >>u rB */ |
| 4969 | /* ppc32 semantics are: |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 4970 | srw(x,y) = (x >>u (y & 31)) -- primary result |
sewardj | dfb1144 | 2005-10-08 19:58:48 +0000 | [diff] [blame] | 4971 | & ~((y << 26) >>s 31) -- make result 0 |
| 4972 | for y in 32 .. 63 |
| 4973 | */ |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 4974 | e_tmp = |
sewardj | dfb1144 | 2005-10-08 19:58:48 +0000 | [diff] [blame] | 4975 | binop( |
| 4976 | Iop_And32, |
| 4977 | binop( Iop_Shr32, |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 4978 | mkexpr(rS_lo32), |
sewardj | dfb1144 | 2005-10-08 19:58:48 +0000 | [diff] [blame] | 4979 | unop( Iop_32to8, |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 4980 | binop(Iop_And32, mkexpr(rB_lo32), |
| 4981 | mkU32(31)))), |
sewardj | dfb1144 | 2005-10-08 19:58:48 +0000 | [diff] [blame] | 4982 | unop( Iop_Not32, |
| 4983 | binop( Iop_Sar32, |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 4984 | binop(Iop_Shl32, mkexpr(rB_lo32), |
| 4985 | mkU8(26)), |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 4986 | mkU8(31)))); |
cerion | 2831b00 | 2005-11-30 19:55:22 +0000 | [diff] [blame] | 4987 | assign( rA, mkSzWiden32(ty, e_tmp, /* Signed */False) ); |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 4988 | break; |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 4989 | |
| 4990 | |
| 4991 | /* 64bit Shifts */ |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 4992 | case 0x01B: // sld (Shift Left DWord, PPC64 p568) |
| 4993 | DIP("sld%s r%u,r%u,r%u\n", |
| 4994 | flag_rC ? ".":"", rA_addr, rS_addr, rB_addr); |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 4995 | /* rA = rS << rB */ |
cerion | 07b07a9 | 2005-12-22 14:32:35 +0000 | [diff] [blame] | 4996 | /* ppc64 semantics are: |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 4997 | slw(x,y) = (x << (y & 63)) -- primary result |
| 4998 | & ~((y << 57) >>s 63) -- make result 0 |
| 4999 | for y in 64 .. |
| 5000 | */ |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 5001 | assign( rA, |
| 5002 | binop( |
| 5003 | Iop_And64, |
| 5004 | binop( Iop_Shl64, |
| 5005 | mkexpr(rS), |
| 5006 | unop( Iop_64to8, |
| 5007 | binop(Iop_And64, mkexpr(rB), mkU64(63)))), |
| 5008 | unop( Iop_Not64, |
| 5009 | binop( Iop_Sar64, |
| 5010 | binop(Iop_Shl64, mkexpr(rB), mkU8(57)), |
| 5011 | mkU8(63)))) ); |
cerion | 07b07a9 | 2005-12-22 14:32:35 +0000 | [diff] [blame] | 5012 | break; |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 5013 | |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 5014 | case 0x31A: { // srad (Shift Right Alg DWord, PPC64 p570) |
cerion | 07b07a9 | 2005-12-22 14:32:35 +0000 | [diff] [blame] | 5015 | IRTemp sh_amt = newTemp(Ity_I64); |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 5016 | DIP("srad%s r%u,r%u,r%u\n", |
| 5017 | flag_rC ? ".":"", rA_addr, rS_addr, rB_addr); |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 5018 | /* amt = rB & 127 |
| 5019 | rA = Sar64( rS, amt > 63 ? 63 : amt ) |
| 5020 | XER.CA = amt > 63 ? sign-of-rS : (computation as per srawi) |
| 5021 | */ |
cerion | 07b07a9 | 2005-12-22 14:32:35 +0000 | [diff] [blame] | 5022 | assign( sh_amt, binop(Iop_And64, mkU64(0x7F), mkexpr(rB)) ); |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 5023 | assign( outofrange, |
| 5024 | unop( Iop_1Uto8, |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 5025 | binop(Iop_CmpLT64U, mkU64(63), |
| 5026 | mkexpr(sh_amt)) )); |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 5027 | assign( rA, |
| 5028 | binop( Iop_Sar64, |
| 5029 | mkexpr(rS), |
| 5030 | unop( Iop_64to8, |
| 5031 | IRExpr_Mux0X( mkexpr(outofrange), |
cerion | 07b07a9 | 2005-12-22 14:32:35 +0000 | [diff] [blame] | 5032 | mkexpr(sh_amt), |
| 5033 | mkU64(63)) )) |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 5034 | ); |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 5035 | set_XER_CA( ty, PPCG_FLAG_OP_SRAD, |
cerion | 07b07a9 | 2005-12-22 14:32:35 +0000 | [diff] [blame] | 5036 | mkexpr(rA), mkexpr(rS), mkexpr(sh_amt), |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 5037 | mkSzWiden32(ty, getXER_CA32(), /* Syned */False) ); |
cerion | 07b07a9 | 2005-12-22 14:32:35 +0000 | [diff] [blame] | 5038 | break; |
| 5039 | } |
| 5040 | |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 5041 | case 0x33A: case 0x33B: // sradi (Shr Alg DWord Imm, PPC64 p571) |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 5042 | sh_imm |= b1<<5; |
| 5043 | vassert(sh_imm < 64); |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 5044 | DIP("sradi%s r%u,r%u,%u\n", |
| 5045 | flag_rC ? ".":"", rA_addr, rS_addr, sh_imm); |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 5046 | assign( rA, binop(Iop_Sar64, getIReg(rS_addr), mkU8(sh_imm)) ); |
| 5047 | |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 5048 | set_XER_CA( ty, PPCG_FLAG_OP_SRADI, |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 5049 | mkexpr(rA), |
| 5050 | getIReg(rS_addr), |
| 5051 | mkU64(sh_imm), |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 5052 | mkSzWiden32(ty, getXER_CA32(), /* Syned */False) ); |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 5053 | break; |
| 5054 | |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 5055 | case 0x21B: // srd (Shift Right DWord, PPC64 p574) |
| 5056 | DIP("srd%s r%u,r%u,r%u\n", |
| 5057 | flag_rC ? ".":"", rA_addr, rS_addr, rB_addr); |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 5058 | /* rA = rS >>u rB */ |
cerion | 07b07a9 | 2005-12-22 14:32:35 +0000 | [diff] [blame] | 5059 | /* ppc semantics are: |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 5060 | srw(x,y) = (x >>u (y & 63)) -- primary result |
| 5061 | & ~((y << 57) >>s 63) -- make result 0 |
| 5062 | for y in 64 .. 127 |
| 5063 | */ |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 5064 | assign( rA, |
| 5065 | binop( |
| 5066 | Iop_And64, |
| 5067 | binop( Iop_Shr64, |
| 5068 | mkexpr(rS), |
| 5069 | unop( Iop_64to8, |
| 5070 | binop(Iop_And64, mkexpr(rB), mkU64(63)))), |
| 5071 | unop( Iop_Not64, |
| 5072 | binop( Iop_Sar64, |
| 5073 | binop(Iop_Shl64, mkexpr(rB), mkU8(57)), |
| 5074 | mkU8(63)))) ); |
cerion | 07b07a9 | 2005-12-22 14:32:35 +0000 | [diff] [blame] | 5075 | break; |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 5076 | |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 5077 | default: |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 5078 | vex_printf("dis_int_shift(ppc)(opc2)\n"); |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 5079 | return False; |
| 5080 | } |
| 5081 | } else { |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 5082 | vex_printf("dis_int_shift(ppc)(opc1)\n"); |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 5083 | return False; |
| 5084 | } |
cerion | 0d330c5 | 2005-02-28 16:43:16 +0000 | [diff] [blame] | 5085 | |
cerion | 76de5cf | 2005-11-18 18:25:12 +0000 | [diff] [blame] | 5086 | putIReg( rA_addr, mkexpr(rA) ); |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 5087 | |
cerion | 76de5cf | 2005-11-18 18:25:12 +0000 | [diff] [blame] | 5088 | if (flag_rC) { |
| 5089 | set_CR0( mkexpr(rA) ); |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 5090 | } |
| 5091 | return True; |
cerion | 645c930 | 2005-01-31 10:09:59 +0000 | [diff] [blame] | 5092 | } |
| 5093 | |
| 5094 | |
| 5095 | |
sewardj | 602857d | 2005-09-06 09:10:09 +0000 | [diff] [blame] | 5096 | /* |
| 5097 | Integer Load/Store Reverse Instructions |
| 5098 | */ |
sewardj | 40d8c09 | 2006-05-05 13:26:14 +0000 | [diff] [blame] | 5099 | /* Generates code to swap the byte order in an Ity_I32. */ |
sewardj | fb95797 | 2005-09-08 17:53:03 +0000 | [diff] [blame] | 5100 | static IRExpr* /* :: Ity_I32 */ gen_byterev32 ( IRTemp t ) |
| 5101 | { |
| 5102 | vassert(typeOfIRTemp(irbb->tyenv, t) == Ity_I32); |
| 5103 | return |
| 5104 | binop(Iop_Or32, |
| 5105 | binop(Iop_Shl32, mkexpr(t), mkU8(24)), |
| 5106 | binop(Iop_Or32, |
| 5107 | binop(Iop_And32, binop(Iop_Shl32, mkexpr(t), mkU8(8)), |
| 5108 | mkU32(0x00FF0000)), |
| 5109 | binop(Iop_Or32, |
| 5110 | binop(Iop_And32, binop(Iop_Shr32, mkexpr(t), mkU8(8)), |
| 5111 | mkU32(0x0000FF00)), |
| 5112 | binop(Iop_And32, binop(Iop_Shr32, mkexpr(t), mkU8(24)), |
| 5113 | mkU32(0x000000FF) ) |
| 5114 | ))); |
| 5115 | } |
| 5116 | |
sewardj | 40d8c09 | 2006-05-05 13:26:14 +0000 | [diff] [blame] | 5117 | /* Generates code to swap the byte order in the lower half of an Ity_I32, |
| 5118 | and zeroes the upper half. */ |
| 5119 | static IRExpr* /* :: Ity_I32 */ gen_byterev16 ( IRTemp t ) |
| 5120 | { |
| 5121 | vassert(typeOfIRTemp(irbb->tyenv, t) == Ity_I32); |
| 5122 | return |
| 5123 | binop(Iop_Or32, |
| 5124 | binop(Iop_And32, binop(Iop_Shl32, mkexpr(t), mkU8(8)), |
| 5125 | mkU32(0x0000FF00)), |
| 5126 | binop(Iop_And32, binop(Iop_Shr32, mkexpr(t), mkU8(8)), |
| 5127 | mkU32(0x000000FF)) |
| 5128 | ); |
| 5129 | } |
| 5130 | |
sewardj | 602857d | 2005-09-06 09:10:09 +0000 | [diff] [blame] | 5131 | static Bool dis_int_ldst_rev ( UInt theInstr ) |
| 5132 | { |
| 5133 | /* X-Form */ |
cerion | 76de5cf | 2005-11-18 18:25:12 +0000 | [diff] [blame] | 5134 | UChar opc1 = ifieldOPC(theInstr); |
| 5135 | UChar rD_addr = ifieldRegDS(theInstr); |
| 5136 | UChar rS_addr = rD_addr; |
| 5137 | UChar rA_addr = ifieldRegA(theInstr); |
| 5138 | UChar rB_addr = ifieldRegB(theInstr); |
| 5139 | UInt opc2 = ifieldOPClo10(theInstr); |
| 5140 | UChar b0 = ifieldBIT0(theInstr); |
cerion | edf7fc5 | 2005-11-18 20:57:41 +0000 | [diff] [blame] | 5141 | |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 5142 | IRType ty = mode64 ? Ity_I64 : Ity_I32; |
| 5143 | IRTemp EA = newTemp(ty); |
cerion | edf7fc5 | 2005-11-18 20:57:41 +0000 | [diff] [blame] | 5144 | IRTemp w1 = newTemp(Ity_I32); |
| 5145 | IRTemp w2 = newTemp(Ity_I32); |
sewardj | 602857d | 2005-09-06 09:10:09 +0000 | [diff] [blame] | 5146 | |
| 5147 | if (opc1 != 0x1F || b0 != 0) { |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 5148 | vex_printf("dis_int_ldst_rev(ppc)(opc1|b0)\n"); |
sewardj | 602857d | 2005-09-06 09:10:09 +0000 | [diff] [blame] | 5149 | return False; |
| 5150 | } |
sewardj | afe8583 | 2005-09-09 10:25:39 +0000 | [diff] [blame] | 5151 | |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 5152 | assign( EA, ea_rAor0_idxd( rA_addr, rB_addr ) ); |
sewardj | 602857d | 2005-09-06 09:10:09 +0000 | [diff] [blame] | 5153 | |
| 5154 | switch (opc2) { |
sewardj | 40d8c09 | 2006-05-05 13:26:14 +0000 | [diff] [blame] | 5155 | |
| 5156 | case 0x316: // lhbrx (Load Halfword Byte-Reverse Indexed, PPC32 p449) |
| 5157 | DIP("lhbrx r%u,r%u,r%u\n", rD_addr, rA_addr, rB_addr); |
| 5158 | assign( w1, unop(Iop_16Uto32, loadBE(Ity_I16, mkexpr(EA))) ); |
| 5159 | assign( w2, gen_byterev16(w1) ); |
| 5160 | putIReg( rD_addr, mkSzWiden32(ty, mkexpr(w2), |
| 5161 | /* Signed */False) ); |
| 5162 | break; |
| 5163 | |
sewardj | fb95797 | 2005-09-08 17:53:03 +0000 | [diff] [blame] | 5164 | case 0x216: // lwbrx (Load Word Byte-Reverse Indexed, PPC32 p459) |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 5165 | DIP("lwbrx r%u,r%u,r%u\n", rD_addr, rA_addr, rB_addr); |
sewardj | fb95797 | 2005-09-08 17:53:03 +0000 | [diff] [blame] | 5166 | assign( w1, loadBE(Ity_I32, mkexpr(EA)) ); |
| 5167 | assign( w2, gen_byterev32(w1) ); |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 5168 | putIReg( rD_addr, mkSzWiden32(ty, mkexpr(w2), |
| 5169 | /* Signed */False) ); |
sewardj | fb95797 | 2005-09-08 17:53:03 +0000 | [diff] [blame] | 5170 | break; |
sewardj | 602857d | 2005-09-06 09:10:09 +0000 | [diff] [blame] | 5171 | |
sewardj | 413a468 | 2006-05-05 13:44:17 +0000 | [diff] [blame] | 5172 | case 0x396: // sthbrx (Store Half Word Byte-Reverse Indexed, PPC32 p523) |
| 5173 | DIP("sthbrx r%u,r%u,r%u\n", rS_addr, rA_addr, rB_addr); |
| 5174 | assign( w1, mkSzNarrow32(ty, getIReg(rS_addr)) ); |
| 5175 | storeBE( mkexpr(EA), unop(Iop_32to16, gen_byterev16(w1)) ); |
| 5176 | break; |
sewardj | 602857d | 2005-09-06 09:10:09 +0000 | [diff] [blame] | 5177 | |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 5178 | case 0x296: // stwbrx (Store Word Byte-Reverse Indxd, PPC32 p531) |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 5179 | DIP("stwbrx r%u,r%u,r%u\n", rS_addr, rA_addr, rB_addr); |
cerion | 2831b00 | 2005-11-30 19:55:22 +0000 | [diff] [blame] | 5180 | assign( w1, mkSzNarrow32(ty, getIReg(rS_addr)) ); |
sewardj | fb95797 | 2005-09-08 17:53:03 +0000 | [diff] [blame] | 5181 | storeBE( mkexpr(EA), gen_byterev32(w1) ); |
| 5182 | break; |
| 5183 | |
| 5184 | default: |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 5185 | vex_printf("dis_int_ldst_rev(ppc)(opc2)\n"); |
sewardj | fb95797 | 2005-09-08 17:53:03 +0000 | [diff] [blame] | 5186 | return False; |
sewardj | 602857d | 2005-09-06 09:10:09 +0000 | [diff] [blame] | 5187 | } |
| 5188 | return True; |
| 5189 | } |
cerion | 645c930 | 2005-01-31 10:09:59 +0000 | [diff] [blame] | 5190 | |
| 5191 | |
| 5192 | |
cerion | 3d870a3 | 2005-03-18 12:23:33 +0000 | [diff] [blame] | 5193 | /* |
| 5194 | Processor Control Instructions |
| 5195 | */ |
cerion | 8c3adda | 2005-01-31 11:54:05 +0000 | [diff] [blame] | 5196 | static Bool dis_proc_ctl ( UInt theInstr ) |
| 5197 | { |
cerion | 76de5cf | 2005-11-18 18:25:12 +0000 | [diff] [blame] | 5198 | UChar opc1 = ifieldOPC(theInstr); |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 5199 | |
| 5200 | /* X-Form */ |
cerion | 76de5cf | 2005-11-18 18:25:12 +0000 | [diff] [blame] | 5201 | UChar crfD = toUChar( IFIELD( theInstr, 23, 3 ) ); |
| 5202 | UChar b21to22 = toUChar( IFIELD( theInstr, 21, 2 ) ); |
| 5203 | UChar rD_addr = ifieldRegDS(theInstr); |
| 5204 | UInt b11to20 = IFIELD( theInstr, 11, 10 ); |
cerion | e9d361a | 2005-03-04 17:35:29 +0000 | [diff] [blame] | 5205 | |
cerion | 76de5cf | 2005-11-18 18:25:12 +0000 | [diff] [blame] | 5206 | /* XFX-Form */ |
| 5207 | UChar rS_addr = rD_addr; |
| 5208 | UInt SPR = b11to20; |
cerion | edf7fc5 | 2005-11-18 20:57:41 +0000 | [diff] [blame] | 5209 | UInt TBR = b11to20; |
cerion | 76de5cf | 2005-11-18 18:25:12 +0000 | [diff] [blame] | 5210 | UChar b20 = toUChar( IFIELD( theInstr, 20, 1 ) ); |
| 5211 | UInt CRM = IFIELD( theInstr, 12, 8 ); |
| 5212 | UChar b11 = toUChar( IFIELD( theInstr, 11, 1 ) ); |
| 5213 | |
| 5214 | UInt opc2 = ifieldOPClo10(theInstr); |
| 5215 | UChar b0 = ifieldBIT0(theInstr); |
| 5216 | |
cerion | 2831b00 | 2005-11-30 19:55:22 +0000 | [diff] [blame] | 5217 | IRType ty = mode64 ? Ity_I64 : Ity_I32; |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 5218 | IRTemp rS = newTemp(ty); |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 5219 | assign( rS, getIReg(rS_addr) ); |
sewardj | 41a7b70 | 2005-11-18 22:18:23 +0000 | [diff] [blame] | 5220 | |
cerion | 76de5cf | 2005-11-18 18:25:12 +0000 | [diff] [blame] | 5221 | /* Reorder SPR field as per PPC32 p470 */ |
| 5222 | SPR = ((SPR & 0x1F) << 5) | ((SPR >> 5) & 0x1F); |
sewardj | 73a9197 | 2005-09-06 10:25:46 +0000 | [diff] [blame] | 5223 | /* Reorder TBR field as per PPC32 p475 */ |
| 5224 | TBR = ((TBR & 31) << 5) | ((TBR >> 5) & 31); |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 5225 | |
| 5226 | if (opc1 != 0x1F || b0 != 0) { |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 5227 | vex_printf("dis_proc_ctl(ppc)(opc1|b0)\n"); |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 5228 | return False; |
| 5229 | } |
| 5230 | |
| 5231 | switch (opc2) { |
cerion | cb14e73 | 2005-09-09 16:38:19 +0000 | [diff] [blame] | 5232 | /* X-Form */ |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 5233 | case 0x200: { // mcrxr (Move to Cond Register from XER, PPC32 p466) |
cerion | cb14e73 | 2005-09-09 16:38:19 +0000 | [diff] [blame] | 5234 | if (b21to22 != 0 || b11to20 != 0) { |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 5235 | vex_printf("dis_proc_ctl(ppc)(mcrxr,b21to22|b11to20)\n"); |
cerion | cb14e73 | 2005-09-09 16:38:19 +0000 | [diff] [blame] | 5236 | return False; |
| 5237 | } |
| 5238 | DIP("mcrxr crf%d\n", crfD); |
cerion | edf7fc5 | 2005-11-18 20:57:41 +0000 | [diff] [blame] | 5239 | /* Move XER[0-3] (the top 4 bits of XER) to CR[crfD] */ |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 5240 | putGST_field( PPC_GST_CR, |
| 5241 | getGST_field( PPC_GST_XER, 7 ), |
cerion | edf7fc5 | 2005-11-18 20:57:41 +0000 | [diff] [blame] | 5242 | crfD ); |
sewardj | 55ccc3e | 2005-09-09 19:45:02 +0000 | [diff] [blame] | 5243 | |
| 5244 | // Clear XER[0-3] |
cerion | edf7fc5 | 2005-11-18 20:57:41 +0000 | [diff] [blame] | 5245 | putXER_SO( mkU8(0) ); |
| 5246 | putXER_OV( mkU8(0) ); |
| 5247 | putXER_CA( mkU8(0) ); |
cerion | cb14e73 | 2005-09-09 16:38:19 +0000 | [diff] [blame] | 5248 | break; |
sewardj | 55ccc3e | 2005-09-09 19:45:02 +0000 | [diff] [blame] | 5249 | } |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 5250 | |
sewardj | 72aefb2 | 2006-03-01 18:58:39 +0000 | [diff] [blame] | 5251 | case 0x013: |
| 5252 | // b11to20==0: mfcr (Move from Cond Register, PPC32 p467) |
| 5253 | // b20==1 & b11==0: mfocrf (Move from One CR Field) |
| 5254 | // However it seems that the 'mfcr' behaviour is an acceptable |
| 5255 | // implementation of mfocr (from the 2.02 arch spec) |
| 5256 | if (b11to20 == 0) { |
| 5257 | DIP("mfcr r%u\n", rD_addr); |
| 5258 | putIReg( rD_addr, mkSzWiden32(ty, getGST( PPC_GST_CR ), |
| 5259 | /* Signed */False) ); |
| 5260 | break; |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 5261 | } |
sewardj | 72aefb2 | 2006-03-01 18:58:39 +0000 | [diff] [blame] | 5262 | if (b20 == 1 && b11 == 0) { |
| 5263 | DIP("mfocrf r%u,%u\n", rD_addr, CRM); |
| 5264 | putIReg( rD_addr, mkSzWiden32(ty, getGST( PPC_GST_CR ), |
| 5265 | /* Signed */False) ); |
| 5266 | break; |
| 5267 | } |
| 5268 | /* not decodable */ |
| 5269 | return False; |
| 5270 | |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 5271 | /* XFX-Form */ |
cerion | e9d361a | 2005-03-04 17:35:29 +0000 | [diff] [blame] | 5272 | case 0x153: // mfspr (Move from Special-Purpose Register, PPC32 p470) |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 5273 | |
cerion | 76de5cf | 2005-11-18 18:25:12 +0000 | [diff] [blame] | 5274 | switch (SPR) { // Choose a register... |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 5275 | case 0x1: |
| 5276 | DIP("mfxer r%u\n", rD_addr); |
cerion | 2831b00 | 2005-11-30 19:55:22 +0000 | [diff] [blame] | 5277 | putIReg( rD_addr, mkSzWiden32(ty, getGST( PPC_GST_XER ), |
| 5278 | /* Signed */False) ); |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 5279 | break; |
| 5280 | case 0x8: |
| 5281 | DIP("mflr r%u\n", rD_addr); |
| 5282 | putIReg( rD_addr, getGST( PPC_GST_LR ) ); |
| 5283 | break; |
| 5284 | case 0x9: |
| 5285 | DIP("mfctr r%u\n", rD_addr); |
| 5286 | putIReg( rD_addr, getGST( PPC_GST_CTR ) ); |
| 5287 | break; |
| 5288 | case 0x100: |
| 5289 | DIP("mfvrsave r%u\n", rD_addr); |
cerion | 2831b00 | 2005-11-30 19:55:22 +0000 | [diff] [blame] | 5290 | putIReg( rD_addr, mkSzWiden32(ty, getGST( PPC_GST_VRSAVE ), |
| 5291 | /* Signed */False) ); |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 5292 | break; |
| 5293 | |
| 5294 | default: |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 5295 | vex_printf("dis_proc_ctl(ppc)(mfspr,SPR)(0x%x)\n", SPR); |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 5296 | return False; |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 5297 | } |
| 5298 | break; |
| 5299 | |
sewardj | 73a9197 | 2005-09-06 10:25:46 +0000 | [diff] [blame] | 5300 | case 0x173: { // mftb (Move from Time Base, PPC32 p475) |
| 5301 | IRTemp val = newTemp(Ity_I64); |
| 5302 | IRExpr** args = mkIRExprVec_0(); |
cerion | 4c4f5ef | 2006-01-02 14:41:50 +0000 | [diff] [blame] | 5303 | IRDirty* d = unsafeIRDirty_1_N( |
| 5304 | val, |
| 5305 | 0/*regparms*/, |
| 5306 | "ppcg_dirtyhelper_MFTB", |
| 5307 | fnptr_to_fnentry(&ppcg_dirtyhelper_MFTB), |
| 5308 | args ); |
sewardj | 73a9197 | 2005-09-06 10:25:46 +0000 | [diff] [blame] | 5309 | /* execute the dirty call, dumping the result in val. */ |
| 5310 | stmt( IRStmt_Dirty(d) ); |
| 5311 | |
| 5312 | switch (TBR) { |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 5313 | case 269: |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 5314 | DIP("mftbu r%u", rD_addr); |
cerion | 2831b00 | 2005-11-30 19:55:22 +0000 | [diff] [blame] | 5315 | putIReg( rD_addr, |
| 5316 | mkSzWiden32(ty, unop(Iop_64HIto32, mkexpr(val)), |
| 5317 | /* Signed */False) ); |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 5318 | break; |
| 5319 | case 268: |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 5320 | DIP("mftb r%u", rD_addr); |
cerion | 2831b00 | 2005-11-30 19:55:22 +0000 | [diff] [blame] | 5321 | putIReg( rD_addr, (mode64) ? mkexpr(val) : |
| 5322 | unop(Iop_64to32, mkexpr(val)) ); |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 5323 | break; |
| 5324 | default: |
| 5325 | return False; /* illegal instruction */ |
sewardj | 73a9197 | 2005-09-06 10:25:46 +0000 | [diff] [blame] | 5326 | } |
| 5327 | break; |
| 5328 | } |
| 5329 | |
sewardj | 72aefb2 | 2006-03-01 18:58:39 +0000 | [diff] [blame] | 5330 | case 0x090: { |
| 5331 | // b20==0: mtcrf (Move to Cond Register Fields, PPC32 p477) |
| 5332 | // b20==1: mtocrf (Move to One Cond Reg Field) |
cerion | edf7fc5 | 2005-11-18 20:57:41 +0000 | [diff] [blame] | 5333 | Int cr; |
| 5334 | UChar shft; |
sewardj | 72aefb2 | 2006-03-01 18:58:39 +0000 | [diff] [blame] | 5335 | if (b11 != 0) |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 5336 | return False; |
sewardj | 72aefb2 | 2006-03-01 18:58:39 +0000 | [diff] [blame] | 5337 | if (b20 == 1) { |
| 5338 | /* ppc64 v2.02 spec says mtocrf gives undefined outcome if > |
| 5339 | 1 field is written. It seems more robust to decline to |
| 5340 | decode the insn if so. */ |
| 5341 | switch (CRM) { |
| 5342 | case 0x01: case 0x02: case 0x04: case 0x08: |
| 5343 | case 0x10: case 0x20: case 0x40: case 0x80: |
| 5344 | break; |
| 5345 | default: |
| 5346 | return False; |
| 5347 | } |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 5348 | } |
sewardj | 72aefb2 | 2006-03-01 18:58:39 +0000 | [diff] [blame] | 5349 | DIP("%s 0x%x,r%u\n", b20==1 ? "mtocrf" : "mtcrf", |
| 5350 | CRM, rS_addr); |
cerion | edf7fc5 | 2005-11-18 20:57:41 +0000 | [diff] [blame] | 5351 | /* Write to each field specified by CRM */ |
| 5352 | for (cr = 0; cr < 8; cr++) { |
| 5353 | if ((CRM & (1 << (7-cr))) == 0) |
| 5354 | continue; |
| 5355 | shft = 4*(7-cr); |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 5356 | putGST_field( PPC_GST_CR, |
cerion | 2831b00 | 2005-11-30 19:55:22 +0000 | [diff] [blame] | 5357 | binop(Iop_Shr32, |
| 5358 | mkSzNarrow32(ty, mkexpr(rS)), |
| 5359 | mkU8(shft)), cr ); |
cerion | edf7fc5 | 2005-11-18 20:57:41 +0000 | [diff] [blame] | 5360 | } |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 5361 | break; |
cerion | edf7fc5 | 2005-11-18 20:57:41 +0000 | [diff] [blame] | 5362 | } |
cerion | e9d361a | 2005-03-04 17:35:29 +0000 | [diff] [blame] | 5363 | |
| 5364 | case 0x1D3: // mtspr (Move to Special-Purpose Register, PPC32 p483) |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 5365 | |
cerion | 76de5cf | 2005-11-18 18:25:12 +0000 | [diff] [blame] | 5366 | switch (SPR) { // Choose a register... |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 5367 | case 0x1: |
| 5368 | DIP("mtxer r%u\n", rS_addr); |
cerion | 2831b00 | 2005-11-30 19:55:22 +0000 | [diff] [blame] | 5369 | putGST( PPC_GST_XER, mkSzNarrow32(ty, mkexpr(rS)) ); |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 5370 | break; |
| 5371 | case 0x8: |
| 5372 | DIP("mtlr r%u\n", rS_addr); |
| 5373 | putGST( PPC_GST_LR, mkexpr(rS) ); |
| 5374 | break; |
| 5375 | case 0x9: |
| 5376 | DIP("mtctr r%u\n", rS_addr); |
| 5377 | putGST( PPC_GST_CTR, mkexpr(rS) ); |
| 5378 | break; |
| 5379 | case 0x100: |
| 5380 | DIP("mtvrsave r%u\n", rS_addr); |
cerion | 2831b00 | 2005-11-30 19:55:22 +0000 | [diff] [blame] | 5381 | putGST( PPC_GST_VRSAVE, mkSzNarrow32(ty, mkexpr(rS)) ); |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 5382 | break; |
| 5383 | |
| 5384 | default: |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 5385 | vex_printf("dis_proc_ctl(ppc)(mtspr,SPR)(%u)\n", SPR); |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 5386 | return False; |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 5387 | } |
| 5388 | break; |
| 5389 | |
| 5390 | default: |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 5391 | vex_printf("dis_proc_ctl(ppc)(opc2)\n"); |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 5392 | return False; |
| 5393 | } |
| 5394 | return True; |
cerion | 8c3adda | 2005-01-31 11:54:05 +0000 | [diff] [blame] | 5395 | } |
| 5396 | |
| 5397 | |
cerion | 3d870a3 | 2005-03-18 12:23:33 +0000 | [diff] [blame] | 5398 | /* |
| 5399 | Cache Management Instructions |
| 5400 | */ |
sewardj | d94b73a | 2005-06-30 12:08:48 +0000 | [diff] [blame] | 5401 | static Bool dis_cache_manage ( UInt theInstr, |
sewardj | 9e6491a | 2005-07-02 19:24:10 +0000 | [diff] [blame] | 5402 | DisResult* dres, |
sewardj | d94b73a | 2005-06-30 12:08:48 +0000 | [diff] [blame] | 5403 | VexArchInfo* guest_archinfo ) |
cerion | 8c3adda | 2005-01-31 11:54:05 +0000 | [diff] [blame] | 5404 | { |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 5405 | /* X-Form */ |
cerion | 76de5cf | 2005-11-18 18:25:12 +0000 | [diff] [blame] | 5406 | UChar opc1 = ifieldOPC(theInstr); |
| 5407 | UChar b21to25 = ifieldRegDS(theInstr); |
| 5408 | UChar rA_addr = ifieldRegA(theInstr); |
| 5409 | UChar rB_addr = ifieldRegB(theInstr); |
| 5410 | UInt opc2 = ifieldOPClo10(theInstr); |
| 5411 | UChar b0 = ifieldBIT0(theInstr); |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 5412 | UInt lineszB = guest_archinfo->ppc_cache_line_szB; |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 5413 | |
| 5414 | IRType ty = mode64 ? Ity_I64 : Ity_I32; |
cerion | 094d139 | 2005-06-20 13:45:57 +0000 | [diff] [blame] | 5415 | |
sewardj | 6be6723 | 2006-01-24 19:00:05 +0000 | [diff] [blame] | 5416 | /* For dcbt, the lowest two bits of b21to25 encode an |
| 5417 | access-direction hint (TH field) which we ignore. Well, that's |
| 5418 | what the PowerPC documentation says. In fact xlc -O4 on POWER5 |
| 5419 | seems to generate values of 8 and 10 for b21to25. */ |
| 5420 | if (opc1 == 0x1F && opc2 == 0x116) { |
| 5421 | /* b21to25 &= ~3; */ /* if the docs were true */ |
| 5422 | b21to25 = 0; /* blunt instrument */ |
| 5423 | } |
| 5424 | |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 5425 | if (opc1 != 0x1F || b21to25 != 0 || b0 != 0) { |
sewardj | 6be6723 | 2006-01-24 19:00:05 +0000 | [diff] [blame] | 5426 | if (0) vex_printf("dis_cache_manage %d %d %d\n", |
| 5427 | (Int)opc1, (Int)b21to25, (Int)b0); |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 5428 | vex_printf("dis_cache_manage(ppc)(opc1|b21to25|b0)\n"); |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 5429 | return False; |
| 5430 | } |
sewardj | d94b73a | 2005-06-30 12:08:48 +0000 | [diff] [blame] | 5431 | |
| 5432 | /* stay sane .. */ |
| 5433 | vassert(lineszB == 32 || lineszB == 128); |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 5434 | |
| 5435 | switch (opc2) { |
sewardj | b51f0f4 | 2005-07-18 11:38:02 +0000 | [diff] [blame] | 5436 | //zz case 0x2F6: // dcba (Data Cache Block Allocate, PPC32 p380) |
| 5437 | //zz vassert(0); /* AWAITING TEST CASE */ |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 5438 | //zz DIP("dcba r%u,r%u\n", rA_addr, rB_addr); |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 5439 | //zz if (0) vex_printf("vex ppc->IR: kludged dcba\n"); |
sewardj | b51f0f4 | 2005-07-18 11:38:02 +0000 | [diff] [blame] | 5440 | //zz break; |
sewardj | 20ef547 | 2005-07-21 14:48:31 +0000 | [diff] [blame] | 5441 | |
| 5442 | case 0x056: // dcbf (Data Cache Block Flush, PPC32 p382) |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 5443 | DIP("dcbf r%u,r%u\n", rA_addr, rB_addr); |
sewardj | 20ef547 | 2005-07-21 14:48:31 +0000 | [diff] [blame] | 5444 | /* nop as far as vex is concerned */ |
sewardj | 20ef547 | 2005-07-21 14:48:31 +0000 | [diff] [blame] | 5445 | break; |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 5446 | |
cerion | e9d361a | 2005-03-04 17:35:29 +0000 | [diff] [blame] | 5447 | case 0x036: // dcbst (Data Cache Block Store, PPC32 p384) |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 5448 | DIP("dcbst r%u,r%u\n", rA_addr, rB_addr); |
sewardj | b51f0f4 | 2005-07-18 11:38:02 +0000 | [diff] [blame] | 5449 | /* nop as far as vex is concerned */ |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 5450 | break; |
cerion | 8c3adda | 2005-01-31 11:54:05 +0000 | [diff] [blame] | 5451 | |
cerion | e9d361a | 2005-03-04 17:35:29 +0000 | [diff] [blame] | 5452 | case 0x116: // dcbt (Data Cache Block Touch, PPC32 p385) |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 5453 | DIP("dcbt r%u,r%u\n", rA_addr, rB_addr); |
sewardj | b51f0f4 | 2005-07-18 11:38:02 +0000 | [diff] [blame] | 5454 | /* nop as far as vex is concerned */ |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 5455 | break; |
| 5456 | |
cerion | e9d361a | 2005-03-04 17:35:29 +0000 | [diff] [blame] | 5457 | case 0x0F6: // dcbtst (Data Cache Block Touch for Store, PPC32 p386) |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 5458 | DIP("dcbtst r%u,r%u\n", rA_addr, rB_addr); |
sewardj | b51f0f4 | 2005-07-18 11:38:02 +0000 | [diff] [blame] | 5459 | /* nop as far as vex is concerned */ |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 5460 | break; |
| 5461 | |
cerion | 094d139 | 2005-06-20 13:45:57 +0000 | [diff] [blame] | 5462 | case 0x3F6: { // dcbz (Data Cache Block Clear to Zero, PPC32 p387) |
sewardj | d94b73a | 2005-06-30 12:08:48 +0000 | [diff] [blame] | 5463 | /* Clear all bytes in cache block at (rA|0) + rB. */ |
cerion | 2831b00 | 2005-11-30 19:55:22 +0000 | [diff] [blame] | 5464 | IRTemp EA = newTemp(ty); |
| 5465 | IRTemp addr = newTemp(ty); |
cerion | 094d139 | 2005-06-20 13:45:57 +0000 | [diff] [blame] | 5466 | IRExpr* irx_addr; |
cerion | 094d139 | 2005-06-20 13:45:57 +0000 | [diff] [blame] | 5467 | UInt i; |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 5468 | DIP("dcbz r%u,r%u\n", rA_addr, rB_addr); |
sewardj | cb1f68e | 2005-12-30 03:39:14 +0000 | [diff] [blame] | 5469 | |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 5470 | assign( EA, ea_rAor0_idxd(rA_addr, rB_addr) ); |
cerion | 094d139 | 2005-06-20 13:45:57 +0000 | [diff] [blame] | 5471 | |
cerion | 2831b00 | 2005-11-30 19:55:22 +0000 | [diff] [blame] | 5472 | if (mode64) { |
| 5473 | /* Round EA down to the start of the containing block. */ |
| 5474 | assign( addr, binop( Iop_And64, |
| 5475 | mkexpr(EA), |
| 5476 | mkU64( ~((ULong)lineszB-1) )) ); |
| 5477 | |
| 5478 | for (i = 0; i < lineszB / 8; i++) { |
| 5479 | irx_addr = binop( Iop_Add64, mkexpr(addr), mkU64(i*8) ); |
| 5480 | storeBE( irx_addr, mkU64(0) ); |
| 5481 | } |
| 5482 | } else { |
| 5483 | /* Round EA down to the start of the containing block. */ |
| 5484 | assign( addr, binop( Iop_And32, |
| 5485 | mkexpr(EA), |
| 5486 | mkU32( ~(lineszB-1) )) ); |
| 5487 | |
| 5488 | for (i = 0; i < lineszB / 4; i++) { |
| 5489 | irx_addr = binop( Iop_Add32, mkexpr(addr), mkU32(i*4) ); |
| 5490 | storeBE( irx_addr, mkU32(0) ); |
| 5491 | } |
cerion | 094d139 | 2005-06-20 13:45:57 +0000 | [diff] [blame] | 5492 | } |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 5493 | break; |
cerion | 094d139 | 2005-06-20 13:45:57 +0000 | [diff] [blame] | 5494 | } |
cerion | 8c3adda | 2005-01-31 11:54:05 +0000 | [diff] [blame] | 5495 | |
sewardj | 7ce9d15 | 2005-03-15 16:54:13 +0000 | [diff] [blame] | 5496 | case 0x3D6: { |
| 5497 | // icbi (Instruction Cache Block Invalidate, PPC32 p431) |
| 5498 | /* Invalidate all translations containing code from the cache |
sewardj | d94b73a | 2005-06-30 12:08:48 +0000 | [diff] [blame] | 5499 | block at (rA|0) + rB. */ |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 5500 | IRTemp EA = newTemp(ty); |
| 5501 | IRTemp addr = newTemp(ty); |
| 5502 | DIP("icbi r%u,r%u\n", rA_addr, rB_addr); |
| 5503 | assign( EA, ea_rAor0_idxd(rA_addr, rB_addr) ); |
sewardj | 7ce9d15 | 2005-03-15 16:54:13 +0000 | [diff] [blame] | 5504 | |
cerion | 2831b00 | 2005-11-30 19:55:22 +0000 | [diff] [blame] | 5505 | /* Round EA down to the start of the containing block. */ |
| 5506 | assign( addr, binop( mkSzOp(ty, Iop_And8), |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 5507 | mkexpr(EA), |
cerion | 2831b00 | 2005-11-30 19:55:22 +0000 | [diff] [blame] | 5508 | mkSzImm(ty, ~(((ULong)lineszB)-1) )) ); |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 5509 | putGST( PPC_GST_TISTART, mkexpr(addr) ); |
cerion | 2831b00 | 2005-11-30 19:55:22 +0000 | [diff] [blame] | 5510 | putGST( PPC_GST_TILEN, mkSzImm(ty, lineszB) ); |
sewardj | 7ce9d15 | 2005-03-15 16:54:13 +0000 | [diff] [blame] | 5511 | |
sewardj | a8078f6 | 2005-03-15 18:27:40 +0000 | [diff] [blame] | 5512 | /* be paranoid ... */ |
| 5513 | stmt( IRStmt_MFence() ); |
| 5514 | |
sewardj | 7ce9d15 | 2005-03-15 16:54:13 +0000 | [diff] [blame] | 5515 | irbb->jumpkind = Ijk_TInval; |
cerion | 2831b00 | 2005-11-30 19:55:22 +0000 | [diff] [blame] | 5516 | irbb->next = mkSzImm(ty, nextInsnAddr()); |
sewardj | 9e6491a | 2005-07-02 19:24:10 +0000 | [diff] [blame] | 5517 | dres->whatNext = Dis_StopHere; |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 5518 | break; |
sewardj | 7ce9d15 | 2005-03-15 16:54:13 +0000 | [diff] [blame] | 5519 | } |
cerion | 8c3adda | 2005-01-31 11:54:05 +0000 | [diff] [blame] | 5520 | |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 5521 | default: |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 5522 | vex_printf("dis_cache_manage(ppc)(opc2)\n"); |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 5523 | return False; |
| 5524 | } |
| 5525 | return True; |
cerion | 8c3adda | 2005-01-31 11:54:05 +0000 | [diff] [blame] | 5526 | } |
| 5527 | |
| 5528 | |
sewardj | e14bb9f | 2005-07-22 09:39:02 +0000 | [diff] [blame] | 5529 | /*------------------------------------------------------------*/ |
| 5530 | /*--- Floating Point Helpers ---*/ |
| 5531 | /*------------------------------------------------------------*/ |
| 5532 | |
sewardj | e14bb9f | 2005-07-22 09:39:02 +0000 | [diff] [blame] | 5533 | /* --------- Synthesise a 2-bit FPU rounding mode. --------- */ |
| 5534 | /* Produces a value in 0 .. 3, which is encoded as per the type |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 5535 | IRRoundingMode. PPCRoundingMode encoding is different to |
sewardj | e14bb9f | 2005-07-22 09:39:02 +0000 | [diff] [blame] | 5536 | IRRoundingMode, so need to map it. |
| 5537 | */ |
sewardj | b183b85 | 2006-02-03 16:08:03 +0000 | [diff] [blame] | 5538 | static IRExpr* /* :: Ity_I32 */ get_IR_roundingmode ( void ) |
sewardj | e14bb9f | 2005-07-22 09:39:02 +0000 | [diff] [blame] | 5539 | { |
| 5540 | /* |
| 5541 | rounding mode | PPC | IR |
| 5542 | ------------------------ |
| 5543 | to nearest | 00 | 00 |
| 5544 | to zero | 01 | 11 |
| 5545 | to +infinity | 10 | 10 |
| 5546 | to -infinity | 11 | 01 |
| 5547 | */ |
| 5548 | IRTemp rm_PPC32 = newTemp(Ity_I32); |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 5549 | assign( rm_PPC32, getGST_masked( PPC_GST_FPSCR, MASK_FPSCR_RN ) ); |
sewardj | e14bb9f | 2005-07-22 09:39:02 +0000 | [diff] [blame] | 5550 | |
| 5551 | // rm_IR = XOR( rm_PPC32, (rm_PPC32 << 1) & 2) |
sewardj | b183b85 | 2006-02-03 16:08:03 +0000 | [diff] [blame] | 5552 | return binop( Iop_Xor32, |
| 5553 | mkexpr(rm_PPC32), |
| 5554 | binop( Iop_And32, |
| 5555 | binop(Iop_Shl32, mkexpr(rm_PPC32), mkU8(1)), |
| 5556 | mkU32(2) )); |
sewardj | e14bb9f | 2005-07-22 09:39:02 +0000 | [diff] [blame] | 5557 | } |
cerion | 094d139 | 2005-06-20 13:45:57 +0000 | [diff] [blame] | 5558 | |
| 5559 | |
cerion | 3d870a3 | 2005-03-18 12:23:33 +0000 | [diff] [blame] | 5560 | /*------------------------------------------------------------*/ |
| 5561 | /*--- Floating Point Instruction Translation ---*/ |
| 5562 | /*------------------------------------------------------------*/ |
| 5563 | |
| 5564 | /* |
| 5565 | Floating Point Load Instructions |
| 5566 | */ |
| 5567 | static Bool dis_fp_load ( UInt theInstr ) |
| 5568 | { |
cerion | 76de5cf | 2005-11-18 18:25:12 +0000 | [diff] [blame] | 5569 | /* X-Form, D-Form */ |
| 5570 | UChar opc1 = ifieldOPC(theInstr); |
| 5571 | UChar frD_addr = ifieldRegDS(theInstr); |
| 5572 | UChar rA_addr = ifieldRegA(theInstr); |
| 5573 | UChar rB_addr = ifieldRegB(theInstr); |
| 5574 | UInt opc2 = ifieldOPClo10(theInstr); |
| 5575 | UChar b0 = ifieldBIT0(theInstr); |
cerion | 2831b00 | 2005-11-30 19:55:22 +0000 | [diff] [blame] | 5576 | UInt uimm16 = ifieldUIMM16(theInstr); |
cerion | 094d139 | 2005-06-20 13:45:57 +0000 | [diff] [blame] | 5577 | |
cerion | 2831b00 | 2005-11-30 19:55:22 +0000 | [diff] [blame] | 5578 | Int simm16 = extend_s_16to32(uimm16); |
| 5579 | IRType ty = mode64 ? Ity_I64 : Ity_I32; |
| 5580 | IRTemp EA = newTemp(ty); |
| 5581 | IRTemp rA = newTemp(ty); |
| 5582 | IRTemp rB = newTemp(ty); |
cerion | 094d139 | 2005-06-20 13:45:57 +0000 | [diff] [blame] | 5583 | |
| 5584 | assign( rA, getIReg(rA_addr) ); |
| 5585 | assign( rB, getIReg(rB_addr) ); |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 5586 | |
sewardj | b183b85 | 2006-02-03 16:08:03 +0000 | [diff] [blame] | 5587 | /* These are completely straightforward from a rounding and status |
| 5588 | bits perspective: no rounding involved and no funny status or CR |
| 5589 | bits affected. */ |
cerion | 3d870a3 | 2005-03-18 12:23:33 +0000 | [diff] [blame] | 5590 | |
sewardj | b183b85 | 2006-02-03 16:08:03 +0000 | [diff] [blame] | 5591 | switch (opc1) { |
sewardj | e14bb9f | 2005-07-22 09:39:02 +0000 | [diff] [blame] | 5592 | case 0x30: // lfs (Load Float Single, PPC32 p441) |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 5593 | DIP("lfs fr%u,%d(r%u)\n", frD_addr, simm16, rA_addr); |
| 5594 | assign( EA, ea_rAor0_simm(rA_addr, simm16) ); |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 5595 | putFReg( frD_addr, |
| 5596 | unop(Iop_F32toF64, loadBE(Ity_F32, mkexpr(EA))) ); |
sewardj | e14bb9f | 2005-07-22 09:39:02 +0000 | [diff] [blame] | 5597 | break; |
| 5598 | |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 5599 | case 0x31: // lfsu (Load Float Single, Update, PPC32 p442) |
sewardj | b183b85 | 2006-02-03 16:08:03 +0000 | [diff] [blame] | 5600 | if (rA_addr == 0) |
cerion | 729edb7 | 2005-12-02 16:03:46 +0000 | [diff] [blame] | 5601 | return False; |
cerion | 729edb7 | 2005-12-02 16:03:46 +0000 | [diff] [blame] | 5602 | DIP("lfsu fr%u,%d(r%u)\n", frD_addr, simm16, rA_addr); |
| 5603 | assign( EA, ea_rA_simm(rA_addr, simm16) ); |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 5604 | putFReg( frD_addr, |
| 5605 | unop(Iop_F32toF64, loadBE(Ity_F32, mkexpr(EA))) ); |
cerion | 729edb7 | 2005-12-02 16:03:46 +0000 | [diff] [blame] | 5606 | putIReg( rA_addr, mkexpr(EA) ); |
| 5607 | break; |
cerion | 094d139 | 2005-06-20 13:45:57 +0000 | [diff] [blame] | 5608 | |
| 5609 | case 0x32: // lfd (Load Float Double, PPC32 p437) |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 5610 | DIP("lfd fr%u,%d(r%u)\n", frD_addr, simm16, rA_addr); |
| 5611 | assign( EA, ea_rAor0_simm(rA_addr, simm16) ); |
cerion | 094d139 | 2005-06-20 13:45:57 +0000 | [diff] [blame] | 5612 | putFReg( frD_addr, loadBE(Ity_F64, mkexpr(EA)) ); |
| 5613 | break; |
cerion | 3d870a3 | 2005-03-18 12:23:33 +0000 | [diff] [blame] | 5614 | |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 5615 | case 0x33: // lfdu (Load Float Double, Update, PPC32 p438) |
sewardj | b183b85 | 2006-02-03 16:08:03 +0000 | [diff] [blame] | 5616 | if (rA_addr == 0) |
sewardj | 0e2cc67 | 2005-07-29 21:58:51 +0000 | [diff] [blame] | 5617 | return False; |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 5618 | DIP("lfdu fr%u,%d(r%u)\n", frD_addr, simm16, rA_addr); |
| 5619 | assign( EA, ea_rA_simm(rA_addr, simm16) ); |
sewardj | 0e2cc67 | 2005-07-29 21:58:51 +0000 | [diff] [blame] | 5620 | putFReg( frD_addr, loadBE(Ity_F64, mkexpr(EA)) ); |
| 5621 | putIReg( rA_addr, mkexpr(EA) ); |
| 5622 | break; |
sewardj | e14bb9f | 2005-07-22 09:39:02 +0000 | [diff] [blame] | 5623 | |
| 5624 | case 0x1F: |
| 5625 | if (b0 != 0) { |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 5626 | vex_printf("dis_fp_load(ppc)(instr,b0)\n"); |
sewardj | e14bb9f | 2005-07-22 09:39:02 +0000 | [diff] [blame] | 5627 | return False; |
| 5628 | } |
| 5629 | |
| 5630 | switch(opc2) { |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 5631 | case 0x217: // lfsx (Load Float Single Indexed, PPC32 p444) |
| 5632 | DIP("lfsx fr%u,r%u,r%u\n", frD_addr, rA_addr, rB_addr); |
| 5633 | assign( EA, ea_rAor0_idxd(rA_addr, rB_addr) ); |
| 5634 | putFReg( frD_addr, unop( Iop_F32toF64, |
| 5635 | loadBE(Ity_F32, mkexpr(EA))) ); |
| 5636 | break; |
| 5637 | |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 5638 | case 0x237: // lfsux (Load Float Single, Update Indxd, PPC32 p443) |
sewardj | b183b85 | 2006-02-03 16:08:03 +0000 | [diff] [blame] | 5639 | if (rA_addr == 0) |
sewardj | e14bb9f | 2005-07-22 09:39:02 +0000 | [diff] [blame] | 5640 | return False; |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 5641 | DIP("lfsux fr%u,r%u,r%u\n", frD_addr, rA_addr, rB_addr); |
| 5642 | assign( EA, ea_rA_idxd(rA_addr, rB_addr) ); |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 5643 | putFReg( frD_addr, |
| 5644 | unop(Iop_F32toF64, loadBE(Ity_F32, mkexpr(EA))) ); |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 5645 | putIReg( rA_addr, mkexpr(EA) ); |
| 5646 | break; |
| 5647 | |
| 5648 | case 0x257: // lfdx (Load Float Double Indexed, PPC32 p440) |
| 5649 | DIP("lfdx fr%u,r%u,r%u\n", frD_addr, rA_addr, rB_addr); |
| 5650 | assign( EA, ea_rAor0_idxd(rA_addr, rB_addr) ); |
| 5651 | putFReg( frD_addr, loadBE(Ity_F64, mkexpr(EA)) ); |
| 5652 | break; |
| 5653 | |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 5654 | case 0x277: // lfdux (Load Float Double, Update Indxd, PPC32 p439) |
sewardj | b183b85 | 2006-02-03 16:08:03 +0000 | [diff] [blame] | 5655 | if (rA_addr == 0) |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 5656 | return False; |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 5657 | DIP("lfdux fr%u,r%u,r%u\n", frD_addr, rA_addr, rB_addr); |
| 5658 | assign( EA, ea_rA_idxd(rA_addr, rB_addr) ); |
| 5659 | putFReg( frD_addr, loadBE(Ity_F64, mkexpr(EA)) ); |
| 5660 | putIReg( rA_addr, mkexpr(EA) ); |
| 5661 | break; |
| 5662 | |
| 5663 | default: |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 5664 | vex_printf("dis_fp_load(ppc)(opc2)\n"); |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 5665 | return False; |
sewardj | e14bb9f | 2005-07-22 09:39:02 +0000 | [diff] [blame] | 5666 | } |
| 5667 | break; |
cerion | 3d870a3 | 2005-03-18 12:23:33 +0000 | [diff] [blame] | 5668 | |
| 5669 | default: |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 5670 | vex_printf("dis_fp_load(ppc)(opc1)\n"); |
cerion | 3d870a3 | 2005-03-18 12:23:33 +0000 | [diff] [blame] | 5671 | return False; |
| 5672 | } |
| 5673 | return True; |
| 5674 | } |
| 5675 | |
| 5676 | |
| 5677 | |
| 5678 | /* |
| 5679 | Floating Point Store Instructions |
| 5680 | */ |
| 5681 | static Bool dis_fp_store ( UInt theInstr ) |
| 5682 | { |
cerion | 76de5cf | 2005-11-18 18:25:12 +0000 | [diff] [blame] | 5683 | /* X-Form, D-Form */ |
| 5684 | UChar opc1 = ifieldOPC(theInstr); |
| 5685 | UChar frS_addr = ifieldRegDS(theInstr); |
| 5686 | UChar rA_addr = ifieldRegA(theInstr); |
| 5687 | UChar rB_addr = ifieldRegB(theInstr); |
| 5688 | UInt opc2 = ifieldOPClo10(theInstr); |
| 5689 | UChar b0 = ifieldBIT0(theInstr); |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 5690 | Int uimm16 = ifieldUIMM16(theInstr); |
cerion | 094d139 | 2005-06-20 13:45:57 +0000 | [diff] [blame] | 5691 | |
cerion | 2831b00 | 2005-11-30 19:55:22 +0000 | [diff] [blame] | 5692 | Int simm16 = extend_s_16to32(uimm16); |
| 5693 | IRTemp frS = newTemp(Ity_F64); |
| 5694 | IRType ty = mode64 ? Ity_I64 : Ity_I32; |
| 5695 | IRTemp EA = newTemp(ty); |
| 5696 | IRTemp rA = newTemp(ty); |
| 5697 | IRTemp rB = newTemp(ty); |
cerion | 094d139 | 2005-06-20 13:45:57 +0000 | [diff] [blame] | 5698 | |
| 5699 | assign( frS, getFReg(frS_addr) ); |
cerion | edf7fc5 | 2005-11-18 20:57:41 +0000 | [diff] [blame] | 5700 | assign( rA, getIReg(rA_addr) ); |
| 5701 | assign( rB, getIReg(rB_addr) ); |
cerion | 3d870a3 | 2005-03-18 12:23:33 +0000 | [diff] [blame] | 5702 | |
sewardj | b183b85 | 2006-02-03 16:08:03 +0000 | [diff] [blame] | 5703 | /* These are straightforward from a status bits perspective: no |
| 5704 | funny status or CR bits affected. For single precision stores, |
| 5705 | the values are truncated and denormalised (not rounded) to turn |
| 5706 | them into single precision values. */ |
| 5707 | |
| 5708 | switch (opc1) { |
sewardj | e14bb9f | 2005-07-22 09:39:02 +0000 | [diff] [blame] | 5709 | |
| 5710 | case 0x34: // stfs (Store Float Single, PPC32 p518) |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 5711 | DIP("stfs fr%u,%d(r%u)\n", frS_addr, simm16, rA_addr); |
| 5712 | assign( EA, ea_rAor0_simm(rA_addr, simm16) ); |
sewardj | b183b85 | 2006-02-03 16:08:03 +0000 | [diff] [blame] | 5713 | /* Use Iop_TruncF64asF32 to truncate and possible denormalise |
| 5714 | the value to be stored in the correct way, without any |
| 5715 | rounding. */ |
sewardj | e14bb9f | 2005-07-22 09:39:02 +0000 | [diff] [blame] | 5716 | storeBE( mkexpr(EA), |
sewardj | b183b85 | 2006-02-03 16:08:03 +0000 | [diff] [blame] | 5717 | unop(Iop_TruncF64asF32, mkexpr(frS)) ); |
sewardj | e14bb9f | 2005-07-22 09:39:02 +0000 | [diff] [blame] | 5718 | break; |
| 5719 | |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 5720 | case 0x35: // stfsu (Store Float Single, Update, PPC32 p519) |
sewardj | b183b85 | 2006-02-03 16:08:03 +0000 | [diff] [blame] | 5721 | if (rA_addr == 0) |
cerion | 729edb7 | 2005-12-02 16:03:46 +0000 | [diff] [blame] | 5722 | return False; |
cerion | 729edb7 | 2005-12-02 16:03:46 +0000 | [diff] [blame] | 5723 | DIP("stfsu fr%u,%d(r%u)\n", frS_addr, simm16, rA_addr); |
| 5724 | assign( EA, ea_rA_simm(rA_addr, simm16) ); |
sewardj | b183b85 | 2006-02-03 16:08:03 +0000 | [diff] [blame] | 5725 | /* See comment for stfs */ |
cerion | 729edb7 | 2005-12-02 16:03:46 +0000 | [diff] [blame] | 5726 | storeBE( mkexpr(EA), |
sewardj | b183b85 | 2006-02-03 16:08:03 +0000 | [diff] [blame] | 5727 | unop(Iop_TruncF64asF32, mkexpr(frS)) ); |
cerion | 729edb7 | 2005-12-02 16:03:46 +0000 | [diff] [blame] | 5728 | putIReg( rA_addr, mkexpr(EA) ); |
| 5729 | break; |
cerion | 3d870a3 | 2005-03-18 12:23:33 +0000 | [diff] [blame] | 5730 | |
cerion | 094d139 | 2005-06-20 13:45:57 +0000 | [diff] [blame] | 5731 | case 0x36: // stfd (Store Float Double, PPC32 p513) |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 5732 | DIP("stfd fr%u,%d(r%u)\n", frS_addr, simm16, rA_addr); |
| 5733 | assign( EA, ea_rAor0_simm(rA_addr, simm16) ); |
cerion | 094d139 | 2005-06-20 13:45:57 +0000 | [diff] [blame] | 5734 | storeBE( mkexpr(EA), mkexpr(frS) ); |
| 5735 | break; |
cerion | 3d870a3 | 2005-03-18 12:23:33 +0000 | [diff] [blame] | 5736 | |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 5737 | case 0x37: // stfdu (Store Float Double, Update, PPC32 p514) |
sewardj | b183b85 | 2006-02-03 16:08:03 +0000 | [diff] [blame] | 5738 | if (rA_addr == 0) |
sewardj | e14bb9f | 2005-07-22 09:39:02 +0000 | [diff] [blame] | 5739 | return False; |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 5740 | DIP("stfdu fr%u,%d(r%u)\n", frS_addr, simm16, rA_addr); |
| 5741 | assign( EA, ea_rA_simm(rA_addr, simm16) ); |
sewardj | e14bb9f | 2005-07-22 09:39:02 +0000 | [diff] [blame] | 5742 | storeBE( mkexpr(EA), mkexpr(frS) ); |
| 5743 | putIReg( rA_addr, mkexpr(EA) ); |
| 5744 | break; |
| 5745 | |
| 5746 | case 0x1F: |
| 5747 | if (b0 != 0) { |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 5748 | vex_printf("dis_fp_store(ppc)(instr,b0)\n"); |
sewardj | e14bb9f | 2005-07-22 09:39:02 +0000 | [diff] [blame] | 5749 | return False; |
| 5750 | } |
sewardj | e14bb9f | 2005-07-22 09:39:02 +0000 | [diff] [blame] | 5751 | switch(opc2) { |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 5752 | case 0x297: // stfsx (Store Float Single Indexed, PPC32 p521) |
| 5753 | DIP("stfsx fr%u,r%u,r%u\n", frS_addr, rA_addr, rB_addr); |
| 5754 | assign( EA, ea_rAor0_idxd(rA_addr, rB_addr) ); |
sewardj | b183b85 | 2006-02-03 16:08:03 +0000 | [diff] [blame] | 5755 | /* See note for stfs */ |
| 5756 | storeBE( mkexpr(EA), |
| 5757 | unop(Iop_TruncF64asF32, mkexpr(frS)) ); |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 5758 | break; |
| 5759 | |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 5760 | case 0x2B7: // stfsux (Store Float Sgl, Update Indxd, PPC32 p520) |
sewardj | b183b85 | 2006-02-03 16:08:03 +0000 | [diff] [blame] | 5761 | if (rA_addr == 0) |
cerion | 729edb7 | 2005-12-02 16:03:46 +0000 | [diff] [blame] | 5762 | return False; |
cerion | 729edb7 | 2005-12-02 16:03:46 +0000 | [diff] [blame] | 5763 | DIP("stfsux fr%u,r%u,r%u\n", frS_addr, rA_addr, rB_addr); |
| 5764 | assign( EA, ea_rA_idxd(rA_addr, rB_addr) ); |
sewardj | b183b85 | 2006-02-03 16:08:03 +0000 | [diff] [blame] | 5765 | /* See note for stfs */ |
| 5766 | storeBE( mkexpr(EA), |
| 5767 | unop(Iop_TruncF64asF32, mkexpr(frS)) ); |
cerion | 729edb7 | 2005-12-02 16:03:46 +0000 | [diff] [blame] | 5768 | putIReg( rA_addr, mkexpr(EA) ); |
| 5769 | break; |
sewardj | e14bb9f | 2005-07-22 09:39:02 +0000 | [diff] [blame] | 5770 | |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 5771 | case 0x2D7: // stfdx (Store Float Double Indexed, PPC32 p516) |
| 5772 | DIP("stfdx fr%u,r%u,r%u\n", frS_addr, rA_addr, rB_addr); |
| 5773 | assign( EA, ea_rAor0_idxd(rA_addr, rB_addr) ); |
| 5774 | storeBE( mkexpr(EA), mkexpr(frS) ); |
| 5775 | break; |
sewardj | e14bb9f | 2005-07-22 09:39:02 +0000 | [diff] [blame] | 5776 | |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 5777 | case 0x2F7: // stfdux (Store Float Dbl, Update Indxd, PPC32 p515) |
sewardj | b183b85 | 2006-02-03 16:08:03 +0000 | [diff] [blame] | 5778 | if (rA_addr == 0) |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 5779 | return False; |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 5780 | DIP("stfdux fr%u,r%u,r%u\n", frS_addr, rA_addr, rB_addr); |
| 5781 | assign( EA, ea_rA_idxd(rA_addr, rB_addr) ); |
| 5782 | storeBE( mkexpr(EA), mkexpr(frS) ); |
| 5783 | putIReg( rA_addr, mkexpr(EA) ); |
| 5784 | break; |
sewardj | 5f63c0c | 2005-09-09 10:36:55 +0000 | [diff] [blame] | 5785 | |
sewardj | 09e88d1 | 2006-01-27 16:05:49 +0000 | [diff] [blame] | 5786 | case 0x3D7: // stfiwx (Store Float as Int, Indexed, PPC32 p517) |
sewardj | 5117ce1 | 2006-01-27 21:20:15 +0000 | [diff] [blame] | 5787 | // NOTE: POWERPC OPTIONAL, "Graphics Group" (PPC32_GX) |
sewardj | 09e88d1 | 2006-01-27 16:05:49 +0000 | [diff] [blame] | 5788 | DIP("stfiwx fr%u,r%u,r%u\n", frS_addr, rA_addr, rB_addr); |
| 5789 | assign( EA, ea_rAor0_idxd(rA_addr, rB_addr) ); |
| 5790 | storeBE( mkexpr(EA), |
| 5791 | unop(Iop_64to32, unop(Iop_ReinterpF64asI64, mkexpr(frS))) ); |
| 5792 | break; |
sewardj | e14bb9f | 2005-07-22 09:39:02 +0000 | [diff] [blame] | 5793 | |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 5794 | default: |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 5795 | vex_printf("dis_fp_store(ppc)(opc2)\n"); |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 5796 | return False; |
sewardj | e14bb9f | 2005-07-22 09:39:02 +0000 | [diff] [blame] | 5797 | } |
| 5798 | break; |
cerion | 3d870a3 | 2005-03-18 12:23:33 +0000 | [diff] [blame] | 5799 | |
| 5800 | default: |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 5801 | vex_printf("dis_fp_store(ppc)(opc1)\n"); |
cerion | 3d870a3 | 2005-03-18 12:23:33 +0000 | [diff] [blame] | 5802 | return False; |
| 5803 | } |
| 5804 | return True; |
| 5805 | } |
| 5806 | |
| 5807 | |
| 5808 | |
| 5809 | /* |
| 5810 | Floating Point Arith Instructions |
| 5811 | */ |
| 5812 | static Bool dis_fp_arith ( UInt theInstr ) |
| 5813 | { |
| 5814 | /* A-Form */ |
cerion | 76de5cf | 2005-11-18 18:25:12 +0000 | [diff] [blame] | 5815 | UChar opc1 = ifieldOPC(theInstr); |
| 5816 | UChar frD_addr = ifieldRegDS(theInstr); |
| 5817 | UChar frA_addr = ifieldRegA(theInstr); |
| 5818 | UChar frB_addr = ifieldRegB(theInstr); |
| 5819 | UChar frC_addr = ifieldRegC(theInstr); |
| 5820 | UChar opc2 = ifieldOPClo5(theInstr); |
| 5821 | UChar flag_rC = ifieldBIT0(theInstr); |
cerion | 094d139 | 2005-06-20 13:45:57 +0000 | [diff] [blame] | 5822 | |
sewardj | b183b85 | 2006-02-03 16:08:03 +0000 | [diff] [blame] | 5823 | IRTemp frD = newTemp(Ity_F64); |
| 5824 | IRTemp frA = newTemp(Ity_F64); |
| 5825 | IRTemp frB = newTemp(Ity_F64); |
| 5826 | IRTemp frC = newTemp(Ity_F64); |
| 5827 | IRExpr* rm = get_IR_roundingmode(); |
| 5828 | |
| 5829 | /* By default, we will examine the results of the operation and set |
| 5830 | fpscr[FPRF] accordingly. */ |
| 5831 | Bool set_FPRF = True; |
| 5832 | |
| 5833 | /* By default, if flag_RC is set, we will clear cr1 after the |
| 5834 | operation. In reality we should set cr1 to indicate the |
| 5835 | exception status of the operation, but since we're not |
| 5836 | simulating exceptions, the exception status will appear to be |
| 5837 | zero. Hence cr1 should be cleared if this is a . form insn. */ |
| 5838 | Bool clear_CR1 = True; |
cerion | 094d139 | 2005-06-20 13:45:57 +0000 | [diff] [blame] | 5839 | |
| 5840 | assign( frA, getFReg(frA_addr)); |
| 5841 | assign( frB, getFReg(frB_addr)); |
| 5842 | assign( frC, getFReg(frC_addr)); |
cerion | 3d870a3 | 2005-03-18 12:23:33 +0000 | [diff] [blame] | 5843 | |
| 5844 | switch (opc1) { |
sewardj | e14bb9f | 2005-07-22 09:39:02 +0000 | [diff] [blame] | 5845 | case 0x3B: |
| 5846 | switch (opc2) { |
| 5847 | case 0x12: // fdivs (Floating Divide Single, PPC32 p407) |
sewardj | b183b85 | 2006-02-03 16:08:03 +0000 | [diff] [blame] | 5848 | if (frC_addr != 0) |
sewardj | e14bb9f | 2005-07-22 09:39:02 +0000 | [diff] [blame] | 5849 | return False; |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 5850 | DIP("fdivs%s fr%u,fr%u,fr%u\n", flag_rC ? ".":"", |
sewardj | e14bb9f | 2005-07-22 09:39:02 +0000 | [diff] [blame] | 5851 | frD_addr, frA_addr, frB_addr); |
sewardj | b183b85 | 2006-02-03 16:08:03 +0000 | [diff] [blame] | 5852 | assign( frD, triop( Iop_DivF64r32, |
| 5853 | rm, mkexpr(frA), mkexpr(frB) )); |
sewardj | e14bb9f | 2005-07-22 09:39:02 +0000 | [diff] [blame] | 5854 | break; |
| 5855 | |
| 5856 | case 0x14: // fsubs (Floating Subtract Single, PPC32 p430) |
sewardj | b183b85 | 2006-02-03 16:08:03 +0000 | [diff] [blame] | 5857 | if (frC_addr != 0) |
sewardj | e14bb9f | 2005-07-22 09:39:02 +0000 | [diff] [blame] | 5858 | return False; |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 5859 | DIP("fsubs%s fr%u,fr%u,fr%u\n", flag_rC ? ".":"", |
sewardj | e14bb9f | 2005-07-22 09:39:02 +0000 | [diff] [blame] | 5860 | frD_addr, frA_addr, frB_addr); |
sewardj | b183b85 | 2006-02-03 16:08:03 +0000 | [diff] [blame] | 5861 | assign( frD, triop( Iop_SubF64r32, |
| 5862 | rm, mkexpr(frA), mkexpr(frB) )); |
sewardj | e14bb9f | 2005-07-22 09:39:02 +0000 | [diff] [blame] | 5863 | break; |
| 5864 | |
| 5865 | case 0x15: // fadds (Floating Add Single, PPC32 p401) |
sewardj | b183b85 | 2006-02-03 16:08:03 +0000 | [diff] [blame] | 5866 | if (frC_addr != 0) |
sewardj | e14bb9f | 2005-07-22 09:39:02 +0000 | [diff] [blame] | 5867 | return False; |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 5868 | DIP("fadds%s fr%u,fr%u,fr%u\n", flag_rC ? ".":"", |
sewardj | e14bb9f | 2005-07-22 09:39:02 +0000 | [diff] [blame] | 5869 | frD_addr, frA_addr, frB_addr); |
sewardj | b183b85 | 2006-02-03 16:08:03 +0000 | [diff] [blame] | 5870 | assign( frD, triop( Iop_AddF64r32, |
| 5871 | rm, mkexpr(frA), mkexpr(frB) )); |
sewardj | e14bb9f | 2005-07-22 09:39:02 +0000 | [diff] [blame] | 5872 | break; |
| 5873 | |
sewardj | 870c84b | 2006-01-24 03:33:43 +0000 | [diff] [blame] | 5874 | case 0x16: // fsqrts (Floating SqRt (Single-Precision), PPC32 p428) |
sewardj | 5117ce1 | 2006-01-27 21:20:15 +0000 | [diff] [blame] | 5875 | // NOTE: POWERPC OPTIONAL, "General-Purpose Group" (PPC32_FX) |
sewardj | b183b85 | 2006-02-03 16:08:03 +0000 | [diff] [blame] | 5876 | if (frA_addr != 0 || frC_addr != 0) |
sewardj | 870c84b | 2006-01-24 03:33:43 +0000 | [diff] [blame] | 5877 | return False; |
sewardj | 870c84b | 2006-01-24 03:33:43 +0000 | [diff] [blame] | 5878 | DIP("fsqrts%s fr%u,fr%u\n", flag_rC ? ".":"", |
| 5879 | frD_addr, frB_addr); |
sewardj | 79fd33f | 2006-01-29 17:07:57 +0000 | [diff] [blame] | 5880 | // however illogically, on ppc970 this insn behaves identically |
sewardj | b183b85 | 2006-02-03 16:08:03 +0000 | [diff] [blame] | 5881 | // to fsqrt (double-precision). So use SqrtF64, not SqrtF64r32. |
| 5882 | assign( frD, binop( Iop_SqrtF64, rm, mkexpr(frB) )); |
sewardj | 870c84b | 2006-01-24 03:33:43 +0000 | [diff] [blame] | 5883 | break; |
sewardj | e14bb9f | 2005-07-22 09:39:02 +0000 | [diff] [blame] | 5884 | |
sewardj | baf971a | 2006-01-27 15:09:35 +0000 | [diff] [blame] | 5885 | case 0x18: // fres (Floating Reciprocal Estimate Single, PPC32 p421) |
sewardj | 5117ce1 | 2006-01-27 21:20:15 +0000 | [diff] [blame] | 5886 | // NOTE: POWERPC OPTIONAL, "Graphics Group" (PPC32_GX) |
sewardj | b183b85 | 2006-02-03 16:08:03 +0000 | [diff] [blame] | 5887 | if (frA_addr != 0 || frC_addr != 0) |
sewardj | baf971a | 2006-01-27 15:09:35 +0000 | [diff] [blame] | 5888 | return False; |
sewardj | baf971a | 2006-01-27 15:09:35 +0000 | [diff] [blame] | 5889 | DIP("fres%s fr%u,fr%u\n", flag_rC ? ".":"", |
| 5890 | frD_addr, frB_addr); |
sewardj | 157b19b | 2006-01-31 16:32:25 +0000 | [diff] [blame] | 5891 | { IRExpr* ieee_one |
| 5892 | = IRExpr_Const(IRConst_F64i(0x3ff0000000000000ULL)); |
sewardj | b183b85 | 2006-02-03 16:08:03 +0000 | [diff] [blame] | 5893 | assign( frD, triop( Iop_DivF64r32, |
| 5894 | rm, |
| 5895 | ieee_one, mkexpr(frB) )); |
sewardj | 157b19b | 2006-01-31 16:32:25 +0000 | [diff] [blame] | 5896 | } |
sewardj | baf971a | 2006-01-27 15:09:35 +0000 | [diff] [blame] | 5897 | break; |
sewardj | e14bb9f | 2005-07-22 09:39:02 +0000 | [diff] [blame] | 5898 | |
| 5899 | case 0x19: // fmuls (Floating Multiply Single, PPC32 p414) |
sewardj | b183b85 | 2006-02-03 16:08:03 +0000 | [diff] [blame] | 5900 | if (frB_addr != 0) |
sewardj | e14bb9f | 2005-07-22 09:39:02 +0000 | [diff] [blame] | 5901 | return False; |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 5902 | DIP("fmuls%s fr%u,fr%u,fr%u\n", flag_rC ? ".":"", |
sewardj | e14bb9f | 2005-07-22 09:39:02 +0000 | [diff] [blame] | 5903 | frD_addr, frA_addr, frC_addr); |
sewardj | b183b85 | 2006-02-03 16:08:03 +0000 | [diff] [blame] | 5904 | assign( frD, triop( Iop_MulF64r32, |
| 5905 | rm, mkexpr(frA), mkexpr(frC) )); |
sewardj | e14bb9f | 2005-07-22 09:39:02 +0000 | [diff] [blame] | 5906 | break; |
| 5907 | |
sewardj | 79fd33f | 2006-01-29 17:07:57 +0000 | [diff] [blame] | 5908 | case 0x1A: // frsqrtes (Floating Recip SqRt Est Single) |
| 5909 | // NOTE: POWERPC OPTIONAL, "Graphics Group" (PPC32_GX) |
| 5910 | // Undocumented instruction? |
sewardj | b183b85 | 2006-02-03 16:08:03 +0000 | [diff] [blame] | 5911 | if (frA_addr != 0 || frC_addr != 0) |
sewardj | 79fd33f | 2006-01-29 17:07:57 +0000 | [diff] [blame] | 5912 | return False; |
sewardj | 79fd33f | 2006-01-29 17:07:57 +0000 | [diff] [blame] | 5913 | DIP("frsqrtes%s fr%u,fr%u\n", flag_rC ? ".":"", |
| 5914 | frD_addr, frB_addr); |
| 5915 | assign( frD, unop(Iop_Est5FRSqrt, mkexpr(frB)) ); |
| 5916 | break; |
| 5917 | |
sewardj | e14bb9f | 2005-07-22 09:39:02 +0000 | [diff] [blame] | 5918 | default: |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 5919 | vex_printf("dis_fp_arith(ppc)(3B: opc2)\n"); |
sewardj | e14bb9f | 2005-07-22 09:39:02 +0000 | [diff] [blame] | 5920 | return False; |
| 5921 | } |
| 5922 | break; |
cerion | 094d139 | 2005-06-20 13:45:57 +0000 | [diff] [blame] | 5923 | |
cerion | 3d870a3 | 2005-03-18 12:23:33 +0000 | [diff] [blame] | 5924 | case 0x3F: |
| 5925 | switch (opc2) { |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 5926 | case 0x12: // fdiv (Floating Div (Double-Precision), PPC32 p406) |
sewardj | b183b85 | 2006-02-03 16:08:03 +0000 | [diff] [blame] | 5927 | if (frC_addr != 0) |
sewardj | e14bb9f | 2005-07-22 09:39:02 +0000 | [diff] [blame] | 5928 | return False; |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 5929 | DIP("fdiv%s fr%u,fr%u,fr%u\n", flag_rC ? ".":"", |
sewardj | e14bb9f | 2005-07-22 09:39:02 +0000 | [diff] [blame] | 5930 | frD_addr, frA_addr, frB_addr); |
sewardj | b183b85 | 2006-02-03 16:08:03 +0000 | [diff] [blame] | 5931 | assign( frD, triop(Iop_DivF64, rm, mkexpr(frA), mkexpr(frB)) ); |
sewardj | e14bb9f | 2005-07-22 09:39:02 +0000 | [diff] [blame] | 5932 | break; |
| 5933 | |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 5934 | case 0x14: // fsub (Floating Sub (Double-Precision), PPC32 p429) |
sewardj | b183b85 | 2006-02-03 16:08:03 +0000 | [diff] [blame] | 5935 | if (frC_addr != 0) |
sewardj | e14bb9f | 2005-07-22 09:39:02 +0000 | [diff] [blame] | 5936 | return False; |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 5937 | DIP("fsub%s fr%u,fr%u,fr%u\n", flag_rC ? ".":"", |
sewardj | e14bb9f | 2005-07-22 09:39:02 +0000 | [diff] [blame] | 5938 | frD_addr, frA_addr, frB_addr); |
sewardj | b183b85 | 2006-02-03 16:08:03 +0000 | [diff] [blame] | 5939 | assign( frD, triop(Iop_SubF64, rm, mkexpr(frA), mkexpr(frB)) ); |
sewardj | e14bb9f | 2005-07-22 09:39:02 +0000 | [diff] [blame] | 5940 | break; |
cerion | 3d870a3 | 2005-03-18 12:23:33 +0000 | [diff] [blame] | 5941 | |
| 5942 | case 0x15: // fadd (Floating Add (Double-Precision), PPC32 p400) |
sewardj | b183b85 | 2006-02-03 16:08:03 +0000 | [diff] [blame] | 5943 | if (frC_addr != 0) |
cerion | 3d870a3 | 2005-03-18 12:23:33 +0000 | [diff] [blame] | 5944 | return False; |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 5945 | DIP("fadd%s fr%u,fr%u,fr%u\n", flag_rC ? ".":"", |
cerion | 3d870a3 | 2005-03-18 12:23:33 +0000 | [diff] [blame] | 5946 | frD_addr, frA_addr, frB_addr); |
sewardj | b183b85 | 2006-02-03 16:08:03 +0000 | [diff] [blame] | 5947 | assign( frD, triop(Iop_AddF64, rm, mkexpr(frA), mkexpr(frB)) ); |
cerion | 094d139 | 2005-06-20 13:45:57 +0000 | [diff] [blame] | 5948 | break; |
cerion | 3d870a3 | 2005-03-18 12:23:33 +0000 | [diff] [blame] | 5949 | |
cerion | 876ef41 | 2005-12-14 22:00:53 +0000 | [diff] [blame] | 5950 | case 0x16: // fsqrt (Floating SqRt (Double-Precision), PPC32 p427) |
sewardj | 5117ce1 | 2006-01-27 21:20:15 +0000 | [diff] [blame] | 5951 | // NOTE: POWERPC OPTIONAL, "General-Purpose Group" (PPC32_FX) |
sewardj | b183b85 | 2006-02-03 16:08:03 +0000 | [diff] [blame] | 5952 | if (frA_addr != 0 || frC_addr != 0) |
cerion | 876ef41 | 2005-12-14 22:00:53 +0000 | [diff] [blame] | 5953 | return False; |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 5954 | DIP("fsqrt%s fr%u,fr%u\n", flag_rC ? ".":"", |
cerion | 876ef41 | 2005-12-14 22:00:53 +0000 | [diff] [blame] | 5955 | frD_addr, frB_addr); |
sewardj | b183b85 | 2006-02-03 16:08:03 +0000 | [diff] [blame] | 5956 | assign( frD, binop(Iop_SqrtF64, rm, mkexpr(frB)) ); |
cerion | 876ef41 | 2005-12-14 22:00:53 +0000 | [diff] [blame] | 5957 | break; |
sewardj | e14bb9f | 2005-07-22 09:39:02 +0000 | [diff] [blame] | 5958 | |
| 5959 | case 0x17: { // fsel (Floating Select, PPC32 p426) |
sewardj | 5117ce1 | 2006-01-27 21:20:15 +0000 | [diff] [blame] | 5960 | // NOTE: POWERPC OPTIONAL, "Graphics Group" (PPC32_GX) |
sewardj | e14bb9f | 2005-07-22 09:39:02 +0000 | [diff] [blame] | 5961 | IRTemp cc = newTemp(Ity_I32); |
| 5962 | IRTemp cc_b0 = newTemp(Ity_I32); |
| 5963 | |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 5964 | DIP("fsel%s fr%u,fr%u,fr%u,fr%u\n", flag_rC ? ".":"", |
sewardj | e14bb9f | 2005-07-22 09:39:02 +0000 | [diff] [blame] | 5965 | frD_addr, frA_addr, frC_addr, frB_addr); |
| 5966 | |
| 5967 | // cc: UN == 0x41, LT == 0x01, GT == 0x00, EQ == 0x40 |
| 5968 | // => GT|EQ == (cc & 0x1 == 0) |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 5969 | assign( cc, binop(Iop_CmpF64, mkexpr(frA), |
| 5970 | IRExpr_Const(IRConst_F64(0))) ); |
sewardj | e14bb9f | 2005-07-22 09:39:02 +0000 | [diff] [blame] | 5971 | assign( cc_b0, binop(Iop_And32, mkexpr(cc), mkU32(1)) ); |
| 5972 | |
| 5973 | // frD = (frA >= 0.0) ? frC : frB |
| 5974 | // = (cc_b0 == 0) ? frC : frB |
| 5975 | assign( frD, |
| 5976 | IRExpr_Mux0X( |
| 5977 | unop(Iop_1Uto8, |
| 5978 | binop(Iop_CmpEQ32, mkexpr(cc_b0), mkU32(0))), |
| 5979 | mkexpr(frB), |
| 5980 | mkexpr(frC) )); |
sewardj | b183b85 | 2006-02-03 16:08:03 +0000 | [diff] [blame] | 5981 | |
| 5982 | /* One of the rare ones which don't mess with FPRF */ |
| 5983 | set_FPRF = False; |
sewardj | e14bb9f | 2005-07-22 09:39:02 +0000 | [diff] [blame] | 5984 | break; |
| 5985 | } |
| 5986 | |
sewardj | 79fd33f | 2006-01-29 17:07:57 +0000 | [diff] [blame] | 5987 | case 0x18: // fre (Floating Reciprocal Estimate) |
| 5988 | // NOTE: POWERPC OPTIONAL, "Graphics Group" (PPC32_GX) |
| 5989 | // Note: unclear whether this insn really exists or not |
| 5990 | // ppc970 doesn't have it, but POWER5 does |
sewardj | b183b85 | 2006-02-03 16:08:03 +0000 | [diff] [blame] | 5991 | if (frA_addr != 0 || frC_addr != 0) |
sewardj | 79fd33f | 2006-01-29 17:07:57 +0000 | [diff] [blame] | 5992 | return False; |
sewardj | 79fd33f | 2006-01-29 17:07:57 +0000 | [diff] [blame] | 5993 | DIP("fre%s fr%u,fr%u\n", flag_rC ? ".":"", |
| 5994 | frD_addr, frB_addr); |
sewardj | 157b19b | 2006-01-31 16:32:25 +0000 | [diff] [blame] | 5995 | { IRExpr* ieee_one |
| 5996 | = IRExpr_Const(IRConst_F64i(0x3ff0000000000000ULL)); |
sewardj | b183b85 | 2006-02-03 16:08:03 +0000 | [diff] [blame] | 5997 | assign( frD, triop( Iop_DivF64, |
sewardj | 56de421 | 2006-02-06 22:19:17 +0000 | [diff] [blame] | 5998 | rm, |
sewardj | b183b85 | 2006-02-03 16:08:03 +0000 | [diff] [blame] | 5999 | ieee_one, mkexpr(frB) )); |
sewardj | 157b19b | 2006-01-31 16:32:25 +0000 | [diff] [blame] | 6000 | } |
sewardj | 79fd33f | 2006-01-29 17:07:57 +0000 | [diff] [blame] | 6001 | break; |
| 6002 | |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 6003 | case 0x19: // fmul (Floating Mult (Double Precision), PPC32 p413) |
sewardj | b183b85 | 2006-02-03 16:08:03 +0000 | [diff] [blame] | 6004 | if (frB_addr != 0) |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 6005 | vex_printf("dis_fp_arith(ppc)(instr,fmul)\n"); |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 6006 | DIP("fmul%s fr%u,fr%u,fr%u\n", flag_rC ? ".":"", |
sewardj | e14bb9f | 2005-07-22 09:39:02 +0000 | [diff] [blame] | 6007 | frD_addr, frA_addr, frC_addr); |
sewardj | b183b85 | 2006-02-03 16:08:03 +0000 | [diff] [blame] | 6008 | assign( frD, triop(Iop_MulF64, rm, mkexpr(frA), mkexpr(frC)) ); |
sewardj | e14bb9f | 2005-07-22 09:39:02 +0000 | [diff] [blame] | 6009 | break; |
| 6010 | |
sewardj | baf971a | 2006-01-27 15:09:35 +0000 | [diff] [blame] | 6011 | case 0x1A: // frsqrte (Floating Recip SqRt Est., PPC32 p424) |
sewardj | 5117ce1 | 2006-01-27 21:20:15 +0000 | [diff] [blame] | 6012 | // NOTE: POWERPC OPTIONAL, "Graphics Group" (PPC32_GX) |
sewardj | b183b85 | 2006-02-03 16:08:03 +0000 | [diff] [blame] | 6013 | if (frA_addr != 0 || frC_addr != 0) |
sewardj | baf971a | 2006-01-27 15:09:35 +0000 | [diff] [blame] | 6014 | return False; |
sewardj | baf971a | 2006-01-27 15:09:35 +0000 | [diff] [blame] | 6015 | DIP("frsqrte%s fr%u,fr%u\n", flag_rC ? ".":"", |
| 6016 | frD_addr, frB_addr); |
| 6017 | assign( frD, unop(Iop_Est5FRSqrt, mkexpr(frB)) ); |
| 6018 | break; |
cerion | 3d870a3 | 2005-03-18 12:23:33 +0000 | [diff] [blame] | 6019 | |
| 6020 | default: |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 6021 | vex_printf("dis_fp_arith(ppc)(3F: opc2)\n"); |
cerion | 3d870a3 | 2005-03-18 12:23:33 +0000 | [diff] [blame] | 6022 | return False; |
| 6023 | } |
cerion | 094d139 | 2005-06-20 13:45:57 +0000 | [diff] [blame] | 6024 | break; |
| 6025 | |
cerion | 3d870a3 | 2005-03-18 12:23:33 +0000 | [diff] [blame] | 6026 | default: |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 6027 | vex_printf("dis_fp_arith(ppc)(opc1)\n"); |
cerion | 3d870a3 | 2005-03-18 12:23:33 +0000 | [diff] [blame] | 6028 | return False; |
| 6029 | } |
cerion | 094d139 | 2005-06-20 13:45:57 +0000 | [diff] [blame] | 6030 | |
| 6031 | putFReg( frD_addr, mkexpr(frD) ); |
sewardj | b183b85 | 2006-02-03 16:08:03 +0000 | [diff] [blame] | 6032 | |
| 6033 | if (set_FPRF) { |
| 6034 | // XXX XXX XXX FIXME |
| 6035 | // set FPRF from frD |
| 6036 | } |
| 6037 | |
| 6038 | if (flag_rC && clear_CR1) { |
| 6039 | putCR321( 1, mkU8(0) ); |
| 6040 | putCR0( 1, mkU8(0) ); |
| 6041 | } |
| 6042 | |
cerion | 3d870a3 | 2005-03-18 12:23:33 +0000 | [diff] [blame] | 6043 | return True; |
| 6044 | } |
| 6045 | |
| 6046 | |
| 6047 | |
sewardj | e14bb9f | 2005-07-22 09:39:02 +0000 | [diff] [blame] | 6048 | /* |
| 6049 | Floating Point Mult-Add Instructions |
| 6050 | */ |
| 6051 | static Bool dis_fp_multadd ( UInt theInstr ) |
| 6052 | { |
| 6053 | /* A-Form */ |
cerion | 76de5cf | 2005-11-18 18:25:12 +0000 | [diff] [blame] | 6054 | UChar opc1 = ifieldOPC(theInstr); |
| 6055 | UChar frD_addr = ifieldRegDS(theInstr); |
| 6056 | UChar frA_addr = ifieldRegA(theInstr); |
| 6057 | UChar frB_addr = ifieldRegB(theInstr); |
| 6058 | UChar frC_addr = ifieldRegC(theInstr); |
| 6059 | UChar opc2 = ifieldOPClo5(theInstr); |
| 6060 | UChar flag_rC = ifieldBIT0(theInstr); |
sewardj | e14bb9f | 2005-07-22 09:39:02 +0000 | [diff] [blame] | 6061 | |
sewardj | b183b85 | 2006-02-03 16:08:03 +0000 | [diff] [blame] | 6062 | IRTemp frD = newTemp(Ity_F64); |
| 6063 | IRTemp frA = newTemp(Ity_F64); |
| 6064 | IRTemp frB = newTemp(Ity_F64); |
| 6065 | IRTemp frC = newTemp(Ity_F64); |
| 6066 | IRTemp rmt = newTemp(Ity_I32); |
| 6067 | IRExpr* rm; |
| 6068 | |
| 6069 | /* By default, we will examine the results of the operation and set |
| 6070 | fpscr[FPRF] accordingly. */ |
| 6071 | Bool set_FPRF = True; |
| 6072 | |
| 6073 | /* By default, if flag_RC is set, we will clear cr1 after the |
| 6074 | operation. In reality we should set cr1 to indicate the |
| 6075 | exception status of the operation, but since we're not |
| 6076 | simulating exceptions, the exception status will appear to be |
| 6077 | zero. Hence cr1 should be cleared if this is a . form insn. */ |
| 6078 | Bool clear_CR1 = True; |
| 6079 | |
| 6080 | /* Bind the rounding mode expression to a temp; there's no |
| 6081 | point in creating gratuitous CSEs, as we know we'll need |
| 6082 | to use it twice. */ |
| 6083 | assign( rmt, get_IR_roundingmode() ); |
| 6084 | rm = mkexpr(rmt); |
sewardj | e14bb9f | 2005-07-22 09:39:02 +0000 | [diff] [blame] | 6085 | |
| 6086 | assign( frA, getFReg(frA_addr)); |
| 6087 | assign( frB, getFReg(frB_addr)); |
| 6088 | assign( frC, getFReg(frC_addr)); |
| 6089 | |
sewardj | b183b85 | 2006-02-03 16:08:03 +0000 | [diff] [blame] | 6090 | /* The rounding in this is all a bit dodgy. The idea is to only do |
| 6091 | one rounding. That clearly isn't achieveable without dedicated |
| 6092 | four-input IR primops, although in the single precision case we |
| 6093 | can sort-of simulate it by doing the inner multiply in double |
| 6094 | precision. |
| 6095 | |
| 6096 | In the negated cases, the negation happens after rounding. */ |
| 6097 | |
sewardj | e14bb9f | 2005-07-22 09:39:02 +0000 | [diff] [blame] | 6098 | switch (opc1) { |
| 6099 | case 0x3B: |
| 6100 | switch (opc2) { |
| 6101 | case 0x1C: // fmsubs (Floating Mult-Subtr Single, PPC32 p412) |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 6102 | DIP("fmsubs%s fr%u,fr%u,fr%u,fr%u\n", flag_rC ? ".":"", |
sewardj | e14bb9f | 2005-07-22 09:39:02 +0000 | [diff] [blame] | 6103 | frD_addr, frA_addr, frC_addr, frB_addr); |
sewardj | 40c8026 | 2006-02-08 19:30:46 +0000 | [diff] [blame] | 6104 | assign( frD, qop( Iop_MSubF64r32, rm, |
| 6105 | mkexpr(frA), mkexpr(frC), mkexpr(frB) )); |
sewardj | b183b85 | 2006-02-03 16:08:03 +0000 | [diff] [blame] | 6106 | break; |
sewardj | e14bb9f | 2005-07-22 09:39:02 +0000 | [diff] [blame] | 6107 | |
| 6108 | case 0x1D: // fmadds (Floating Mult-Add Single, PPC32 p409) |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 6109 | DIP("fmadds%s fr%u,fr%u,fr%u,fr%u\n", flag_rC ? ".":"", |
sewardj | e14bb9f | 2005-07-22 09:39:02 +0000 | [diff] [blame] | 6110 | frD_addr, frA_addr, frC_addr, frB_addr); |
sewardj | 40c8026 | 2006-02-08 19:30:46 +0000 | [diff] [blame] | 6111 | assign( frD, qop( Iop_MAddF64r32, rm, |
| 6112 | mkexpr(frA), mkexpr(frC), mkexpr(frB) )); |
sewardj | e14bb9f | 2005-07-22 09:39:02 +0000 | [diff] [blame] | 6113 | break; |
| 6114 | |
| 6115 | case 0x1E: // fnmsubs (Float Neg Mult-Subtr Single, PPC32 p420) |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 6116 | DIP("fnmsubs%s fr%u,fr%u,fr%u,fr%u\n", flag_rC ? ".":"", |
sewardj | e14bb9f | 2005-07-22 09:39:02 +0000 | [diff] [blame] | 6117 | frD_addr, frA_addr, frC_addr, frB_addr); |
sewardj | b183b85 | 2006-02-03 16:08:03 +0000 | [diff] [blame] | 6118 | assign( frD, unop( Iop_NegF64, |
sewardj | 40c8026 | 2006-02-08 19:30:46 +0000 | [diff] [blame] | 6119 | qop( Iop_MSubF64r32, rm, |
| 6120 | mkexpr(frA), mkexpr(frC), mkexpr(frB) ))); |
sewardj | e14bb9f | 2005-07-22 09:39:02 +0000 | [diff] [blame] | 6121 | break; |
| 6122 | |
| 6123 | case 0x1F: // fnmadds (Floating Negative Multiply-Add Single, PPC32 p418) |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 6124 | DIP("fnmadds%s fr%u,fr%u,fr%u,fr%u\n", flag_rC ? ".":"", |
sewardj | e14bb9f | 2005-07-22 09:39:02 +0000 | [diff] [blame] | 6125 | frD_addr, frA_addr, frC_addr, frB_addr); |
sewardj | b183b85 | 2006-02-03 16:08:03 +0000 | [diff] [blame] | 6126 | assign( frD, unop( Iop_NegF64, |
sewardj | 40c8026 | 2006-02-08 19:30:46 +0000 | [diff] [blame] | 6127 | qop( Iop_MAddF64r32, rm, |
| 6128 | mkexpr(frA), mkexpr(frC), mkexpr(frB) ))); |
sewardj | e14bb9f | 2005-07-22 09:39:02 +0000 | [diff] [blame] | 6129 | break; |
| 6130 | |
| 6131 | default: |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 6132 | vex_printf("dis_fp_multadd(ppc)(3B: opc2)\n"); |
sewardj | e14bb9f | 2005-07-22 09:39:02 +0000 | [diff] [blame] | 6133 | return False; |
| 6134 | } |
| 6135 | break; |
| 6136 | |
| 6137 | case 0x3F: |
| 6138 | switch (opc2) { |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 6139 | case 0x1C: // fmsub (Float Mult-Sub (Dbl Precision), PPC32 p411) |
| 6140 | DIP("fmsub%s fr%u,fr%u,fr%u,fr%u\n", flag_rC ? ".":"", |
sewardj | e14bb9f | 2005-07-22 09:39:02 +0000 | [diff] [blame] | 6141 | frD_addr, frA_addr, frC_addr, frB_addr); |
sewardj | 40c8026 | 2006-02-08 19:30:46 +0000 | [diff] [blame] | 6142 | assign( frD, qop( Iop_MSubF64, rm, |
| 6143 | mkexpr(frA), mkexpr(frC), mkexpr(frB) )); |
sewardj | e14bb9f | 2005-07-22 09:39:02 +0000 | [diff] [blame] | 6144 | break; |
| 6145 | |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 6146 | case 0x1D: // fmadd (Float Mult-Add (Dbl Precision), PPC32 p408) |
| 6147 | DIP("fmadd%s fr%u,fr%u,fr%u,fr%u\n", flag_rC ? ".":"", |
sewardj | e14bb9f | 2005-07-22 09:39:02 +0000 | [diff] [blame] | 6148 | frD_addr, frA_addr, frC_addr, frB_addr); |
sewardj | 40c8026 | 2006-02-08 19:30:46 +0000 | [diff] [blame] | 6149 | assign( frD, qop( Iop_MAddF64, rm, |
| 6150 | mkexpr(frA), mkexpr(frC), mkexpr(frB) )); |
sewardj | e14bb9f | 2005-07-22 09:39:02 +0000 | [diff] [blame] | 6151 | break; |
| 6152 | |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 6153 | case 0x1E: // fnmsub (Float Neg Mult-Subtr (Dbl Precision), PPC32 p419) |
| 6154 | DIP("fnmsub%s fr%u,fr%u,fr%u,fr%u\n", flag_rC ? ".":"", |
sewardj | 0e2cc67 | 2005-07-29 21:58:51 +0000 | [diff] [blame] | 6155 | frD_addr, frA_addr, frC_addr, frB_addr); |
| 6156 | assign( frD, unop( Iop_NegF64, |
sewardj | 40c8026 | 2006-02-08 19:30:46 +0000 | [diff] [blame] | 6157 | qop( Iop_MSubF64, rm, |
| 6158 | mkexpr(frA), mkexpr(frC), mkexpr(frB) ))); |
sewardj | 0e2cc67 | 2005-07-29 21:58:51 +0000 | [diff] [blame] | 6159 | break; |
| 6160 | |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 6161 | case 0x1F: // fnmadd (Float Neg Mult-Add (Dbl Precision), PPC32 p417) |
| 6162 | DIP("fnmadd%s fr%u,fr%u,fr%u,fr%u\n", flag_rC ? ".":"", |
sewardj | 0e2cc67 | 2005-07-29 21:58:51 +0000 | [diff] [blame] | 6163 | frD_addr, frA_addr, frC_addr, frB_addr); |
| 6164 | assign( frD, unop( Iop_NegF64, |
sewardj | 40c8026 | 2006-02-08 19:30:46 +0000 | [diff] [blame] | 6165 | qop( Iop_MAddF64, rm, |
| 6166 | mkexpr(frA), mkexpr(frC), mkexpr(frB) ))); |
sewardj | 0e2cc67 | 2005-07-29 21:58:51 +0000 | [diff] [blame] | 6167 | break; |
sewardj | e14bb9f | 2005-07-22 09:39:02 +0000 | [diff] [blame] | 6168 | |
| 6169 | default: |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 6170 | vex_printf("dis_fp_multadd(ppc)(3F: opc2)\n"); |
sewardj | e14bb9f | 2005-07-22 09:39:02 +0000 | [diff] [blame] | 6171 | return False; |
| 6172 | } |
| 6173 | break; |
| 6174 | |
| 6175 | default: |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 6176 | vex_printf("dis_fp_multadd(ppc)(opc1)\n"); |
sewardj | e14bb9f | 2005-07-22 09:39:02 +0000 | [diff] [blame] | 6177 | return False; |
| 6178 | } |
| 6179 | |
| 6180 | putFReg( frD_addr, mkexpr(frD) ); |
sewardj | b183b85 | 2006-02-03 16:08:03 +0000 | [diff] [blame] | 6181 | |
| 6182 | if (set_FPRF) { |
| 6183 | // XXX XXX XXX FIXME |
| 6184 | // set FPRF from frD |
| 6185 | } |
| 6186 | |
| 6187 | if (flag_rC && clear_CR1) { |
| 6188 | putCR321( 1, mkU8(0) ); |
| 6189 | putCR0( 1, mkU8(0) ); |
| 6190 | } |
| 6191 | |
sewardj | e14bb9f | 2005-07-22 09:39:02 +0000 | [diff] [blame] | 6192 | return True; |
| 6193 | } |
| 6194 | |
| 6195 | |
| 6196 | |
| 6197 | /* |
| 6198 | Floating Point Compare Instructions |
| 6199 | */ |
| 6200 | static Bool dis_fp_cmp ( UInt theInstr ) |
| 6201 | { |
| 6202 | /* X-Form */ |
cerion | 76de5cf | 2005-11-18 18:25:12 +0000 | [diff] [blame] | 6203 | UChar opc1 = ifieldOPC(theInstr); |
| 6204 | UChar crfD = toUChar( IFIELD( theInstr, 23, 3 ) ); |
| 6205 | UChar b21to22 = toUChar( IFIELD( theInstr, 21, 2 ) ); |
| 6206 | UChar frA_addr = ifieldRegA(theInstr); |
| 6207 | UChar frB_addr = ifieldRegB(theInstr); |
| 6208 | UInt opc2 = ifieldOPClo10(theInstr); |
| 6209 | UChar b0 = ifieldBIT0(theInstr); |
sewardj | e14bb9f | 2005-07-22 09:39:02 +0000 | [diff] [blame] | 6210 | |
| 6211 | IRTemp ccIR = newTemp(Ity_I32); |
| 6212 | IRTemp ccPPC32 = newTemp(Ity_I32); |
| 6213 | |
sewardj | e14bb9f | 2005-07-22 09:39:02 +0000 | [diff] [blame] | 6214 | IRTemp frA = newTemp(Ity_F64); |
| 6215 | IRTemp frB = newTemp(Ity_F64); |
sewardj | e14bb9f | 2005-07-22 09:39:02 +0000 | [diff] [blame] | 6216 | |
| 6217 | if (opc1 != 0x3F || b21to22 != 0 || b0 != 0) { |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 6218 | vex_printf("dis_fp_cmp(ppc)(instr)\n"); |
sewardj | e14bb9f | 2005-07-22 09:39:02 +0000 | [diff] [blame] | 6219 | return False; |
| 6220 | } |
| 6221 | |
| 6222 | assign( frA, getFReg(frA_addr)); |
| 6223 | assign( frB, getFReg(frB_addr)); |
| 6224 | |
| 6225 | assign( ccIR, binop(Iop_CmpF64, mkexpr(frA), mkexpr(frB)) ); |
| 6226 | |
| 6227 | /* Map compare result from IR to PPC32 */ |
| 6228 | /* |
| 6229 | FP cmp result | PPC | IR |
| 6230 | -------------------------- |
| 6231 | UN | 0x1 | 0x45 |
| 6232 | EQ | 0x2 | 0x40 |
| 6233 | GT | 0x4 | 0x00 |
| 6234 | LT | 0x8 | 0x01 |
| 6235 | */ |
| 6236 | |
sewardj | b183b85 | 2006-02-03 16:08:03 +0000 | [diff] [blame] | 6237 | // ccPPC32 = Shl(1, (~(ccIR>>5) & 2) |
| 6238 | // | ((ccIR ^ (ccIR>>6)) & 1) |
sewardj | e14bb9f | 2005-07-22 09:39:02 +0000 | [diff] [blame] | 6239 | assign( |
| 6240 | ccPPC32, |
sewardj | b183b85 | 2006-02-03 16:08:03 +0000 | [diff] [blame] | 6241 | binop( |
| 6242 | Iop_Shl32, |
| 6243 | mkU32(1), |
| 6244 | unop( |
| 6245 | Iop_32to8, |
| 6246 | binop( |
| 6247 | Iop_Or32, |
| 6248 | binop( |
| 6249 | Iop_And32, |
| 6250 | unop( |
| 6251 | Iop_Not32, |
| 6252 | binop(Iop_Shr32, mkexpr(ccIR), mkU8(5)) |
| 6253 | ), |
| 6254 | mkU32(2) |
| 6255 | ), |
| 6256 | binop( |
| 6257 | Iop_And32, |
| 6258 | binop( |
| 6259 | Iop_Xor32, |
| 6260 | mkexpr(ccIR), |
| 6261 | binop(Iop_Shr32, mkexpr(ccIR), mkU8(6)) |
| 6262 | ), |
| 6263 | mkU32(1) |
| 6264 | ) |
| 6265 | ) |
| 6266 | ) |
| 6267 | ) |
sewardj | e14bb9f | 2005-07-22 09:39:02 +0000 | [diff] [blame] | 6268 | ); |
| 6269 | |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 6270 | putGST_field( PPC_GST_CR, mkexpr(ccPPC32), crfD ); |
sewardj | e14bb9f | 2005-07-22 09:39:02 +0000 | [diff] [blame] | 6271 | |
cerion | edf7fc5 | 2005-11-18 20:57:41 +0000 | [diff] [blame] | 6272 | /* CAB: TODO?: Support writing cc to FPSCR->FPCC ? |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 6273 | putGST_field( PPC_GST_FPSCR, mkexpr(ccPPC32), 4 ); |
cerion | edf7fc5 | 2005-11-18 20:57:41 +0000 | [diff] [blame] | 6274 | */ |
sewardj | b183b85 | 2006-02-03 16:08:03 +0000 | [diff] [blame] | 6275 | // XXX XXX XXX FIXME |
| 6276 | // Also write the result into FPRF (it's not entirely clear how) |
sewardj | e14bb9f | 2005-07-22 09:39:02 +0000 | [diff] [blame] | 6277 | |
cerion | edf7fc5 | 2005-11-18 20:57:41 +0000 | [diff] [blame] | 6278 | /* Note: Differences between fcmpu and fcmpo are only in exception |
| 6279 | flag settings, which aren't supported anyway. */ |
sewardj | e14bb9f | 2005-07-22 09:39:02 +0000 | [diff] [blame] | 6280 | switch (opc2) { |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 6281 | case 0x000: // fcmpu (Floating Compare Unordered, PPC32 p403) |
| 6282 | DIP("fcmpu crf%d,fr%u,fr%u\n", crfD, frA_addr, frB_addr); |
| 6283 | break; |
| 6284 | case 0x020: // fcmpo (Floating Compare Ordered, PPC32 p402) |
| 6285 | DIP("fcmpo crf%d,fr%u,fr%u\n", crfD, frA_addr, frB_addr); |
| 6286 | break; |
| 6287 | default: |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 6288 | vex_printf("dis_fp_cmp(ppc)(opc2)\n"); |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 6289 | return False; |
sewardj | e14bb9f | 2005-07-22 09:39:02 +0000 | [diff] [blame] | 6290 | } |
| 6291 | return True; |
| 6292 | } |
| 6293 | |
| 6294 | |
| 6295 | |
| 6296 | /* |
| 6297 | Floating Point Rounding/Conversion Instructions |
| 6298 | */ |
| 6299 | static Bool dis_fp_round ( UInt theInstr ) |
| 6300 | { |
| 6301 | /* X-Form */ |
cerion | 76de5cf | 2005-11-18 18:25:12 +0000 | [diff] [blame] | 6302 | UChar opc1 = ifieldOPC(theInstr); |
| 6303 | UChar frD_addr = ifieldRegDS(theInstr); |
| 6304 | UChar b16to20 = ifieldRegA(theInstr); |
| 6305 | UChar frB_addr = ifieldRegB(theInstr); |
| 6306 | UInt opc2 = ifieldOPClo10(theInstr); |
| 6307 | UChar flag_rC = ifieldBIT0(theInstr); |
sewardj | e14bb9f | 2005-07-22 09:39:02 +0000 | [diff] [blame] | 6308 | |
sewardj | b183b85 | 2006-02-03 16:08:03 +0000 | [diff] [blame] | 6309 | IRTemp frD = newTemp(Ity_F64); |
| 6310 | IRTemp frB = newTemp(Ity_F64); |
| 6311 | IRTemp r_tmp32 = newTemp(Ity_I32); |
| 6312 | IRTemp r_tmp64 = newTemp(Ity_I64); |
| 6313 | IRExpr* rm = get_IR_roundingmode(); |
sewardj | e14bb9f | 2005-07-22 09:39:02 +0000 | [diff] [blame] | 6314 | |
sewardj | b183b85 | 2006-02-03 16:08:03 +0000 | [diff] [blame] | 6315 | /* By default, we will examine the results of the operation and set |
| 6316 | fpscr[FPRF] accordingly. */ |
| 6317 | Bool set_FPRF = True; |
| 6318 | |
| 6319 | /* By default, if flag_RC is set, we will clear cr1 after the |
| 6320 | operation. In reality we should set cr1 to indicate the |
| 6321 | exception status of the operation, but since we're not |
| 6322 | simulating exceptions, the exception status will appear to be |
| 6323 | zero. Hence cr1 should be cleared if this is a . form insn. */ |
| 6324 | Bool clear_CR1 = True; |
| 6325 | |
sewardj | e14bb9f | 2005-07-22 09:39:02 +0000 | [diff] [blame] | 6326 | if (opc1 != 0x3F || b16to20 != 0) { |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 6327 | vex_printf("dis_fp_round(ppc)(instr)\n"); |
sewardj | e14bb9f | 2005-07-22 09:39:02 +0000 | [diff] [blame] | 6328 | return False; |
| 6329 | } |
| 6330 | |
| 6331 | assign( frB, getFReg(frB_addr)); |
| 6332 | |
sewardj | e14bb9f | 2005-07-22 09:39:02 +0000 | [diff] [blame] | 6333 | switch (opc2) { |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 6334 | case 0x00C: // frsp (Float Round to Single, PPC32 p423) |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 6335 | DIP("frsp%s fr%u,fr%u\n", flag_rC ? ".":"", frD_addr, frB_addr); |
sewardj | b183b85 | 2006-02-03 16:08:03 +0000 | [diff] [blame] | 6336 | assign( frD, binop( Iop_RoundF64toF32, rm, mkexpr(frB) )); |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 6337 | break; |
| 6338 | |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 6339 | case 0x00E: // fctiw (Float Conv to Int, PPC32 p404) |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 6340 | DIP("fctiw%s fr%u,fr%u\n", flag_rC ? ".":"", frD_addr, frB_addr); |
| 6341 | assign( r_tmp32, |
sewardj | b183b85 | 2006-02-03 16:08:03 +0000 | [diff] [blame] | 6342 | binop(Iop_F64toI32, rm, mkexpr(frB)) ); |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 6343 | assign( frD, unop( Iop_ReinterpI64asF64, |
cerion | 07b07a9 | 2005-12-22 14:32:35 +0000 | [diff] [blame] | 6344 | unop( Iop_32Uto64, mkexpr(r_tmp32)))); |
sewardj | b183b85 | 2006-02-03 16:08:03 +0000 | [diff] [blame] | 6345 | /* FPRF is undefined after fctiw. Leave unchanged. */ |
| 6346 | set_FPRF = False; |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 6347 | break; |
| 6348 | |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 6349 | case 0x00F: // fctiwz (Float Conv to Int, Round to Zero, PPC32 p405) |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 6350 | DIP("fctiwz%s fr%u,fr%u\n", flag_rC ? ".":"", frD_addr, frB_addr); |
sewardj | b183b85 | 2006-02-03 16:08:03 +0000 | [diff] [blame] | 6351 | assign( r_tmp32, |
| 6352 | binop(Iop_F64toI32, mkU32(Irrm_ZERO), mkexpr(frB) )); |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 6353 | assign( frD, unop( Iop_ReinterpI64asF64, |
cerion | 07b07a9 | 2005-12-22 14:32:35 +0000 | [diff] [blame] | 6354 | unop( Iop_32Uto64, mkexpr(r_tmp32)))); |
sewardj | b183b85 | 2006-02-03 16:08:03 +0000 | [diff] [blame] | 6355 | /* FPRF is undefined after fctiwz. Leave unchanged. */ |
| 6356 | set_FPRF = False; |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 6357 | break; |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 6358 | |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 6359 | case 0x32E: // fctid (Float Conv to Int DWord, PPC64 p437) |
| 6360 | DIP("fctid%s fr%u,fr%u\n", flag_rC ? ".":"", frD_addr, frB_addr); |
| 6361 | assign( r_tmp64, |
sewardj | b183b85 | 2006-02-03 16:08:03 +0000 | [diff] [blame] | 6362 | binop(Iop_F64toI64, rm, mkexpr(frB)) ); |
cerion | 07b07a9 | 2005-12-22 14:32:35 +0000 | [diff] [blame] | 6363 | assign( frD, unop( Iop_ReinterpI64asF64, mkexpr(r_tmp64)) ); |
sewardj | b183b85 | 2006-02-03 16:08:03 +0000 | [diff] [blame] | 6364 | /* FPRF is undefined after fctid. Leave unchanged. */ |
| 6365 | set_FPRF = False; |
cerion | 07b07a9 | 2005-12-22 14:32:35 +0000 | [diff] [blame] | 6366 | break; |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 6367 | |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 6368 | case 0x32F: // fctidz (Float Conv to Int DWord, Round to Zero, PPC64 p437) |
| 6369 | DIP("fctidz%s fr%u,fr%u\n", flag_rC ? ".":"", frD_addr, frB_addr); |
sewardj | b183b85 | 2006-02-03 16:08:03 +0000 | [diff] [blame] | 6370 | assign( r_tmp64, |
| 6371 | binop(Iop_F64toI64, mkU32(Irrm_ZERO), mkexpr(frB)) ); |
cerion | 07b07a9 | 2005-12-22 14:32:35 +0000 | [diff] [blame] | 6372 | assign( frD, unop( Iop_ReinterpI64asF64, mkexpr(r_tmp64)) ); |
sewardj | b183b85 | 2006-02-03 16:08:03 +0000 | [diff] [blame] | 6373 | /* FPRF is undefined after fctidz. Leave unchanged. */ |
| 6374 | set_FPRF = False; |
cerion | 07b07a9 | 2005-12-22 14:32:35 +0000 | [diff] [blame] | 6375 | break; |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 6376 | |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 6377 | case 0x34E: // fcfid (Float Conv from Int DWord, PPC64 p434) |
| 6378 | DIP("fcfid%s fr%u,fr%u\n", flag_rC ? ".":"", frD_addr, frB_addr); |
cerion | 07b07a9 | 2005-12-22 14:32:35 +0000 | [diff] [blame] | 6379 | assign( r_tmp64, unop( Iop_ReinterpF64asI64, mkexpr(frB)) ); |
sewardj | b183b85 | 2006-02-03 16:08:03 +0000 | [diff] [blame] | 6380 | assign( frD, |
| 6381 | binop(Iop_I64toF64, rm, mkexpr(r_tmp64)) ); |
cerion | 07b07a9 | 2005-12-22 14:32:35 +0000 | [diff] [blame] | 6382 | break; |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 6383 | |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 6384 | default: |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 6385 | vex_printf("dis_fp_round(ppc)(opc2)\n"); |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 6386 | return False; |
sewardj | e14bb9f | 2005-07-22 09:39:02 +0000 | [diff] [blame] | 6387 | } |
| 6388 | |
| 6389 | putFReg( frD_addr, mkexpr(frD) ); |
sewardj | b183b85 | 2006-02-03 16:08:03 +0000 | [diff] [blame] | 6390 | |
| 6391 | if (set_FPRF) { |
| 6392 | // XXX XXX XXX FIXME |
| 6393 | // set FPRF from frD |
| 6394 | } |
| 6395 | |
| 6396 | if (flag_rC && clear_CR1) { |
| 6397 | putCR321( 1, mkU8(0) ); |
| 6398 | putCR0( 1, mkU8(0) ); |
| 6399 | } |
| 6400 | |
sewardj | e14bb9f | 2005-07-22 09:39:02 +0000 | [diff] [blame] | 6401 | return True; |
| 6402 | } |
| 6403 | |
| 6404 | |
| 6405 | |
| 6406 | /* |
| 6407 | Floating Point Move Instructions |
| 6408 | */ |
| 6409 | static Bool dis_fp_move ( UInt theInstr ) |
| 6410 | { |
| 6411 | /* X-Form */ |
cerion | 76de5cf | 2005-11-18 18:25:12 +0000 | [diff] [blame] | 6412 | UChar opc1 = ifieldOPC(theInstr); |
| 6413 | UChar frD_addr = ifieldRegDS(theInstr); |
| 6414 | UChar b16to20 = ifieldRegA(theInstr); |
| 6415 | UChar frB_addr = ifieldRegB(theInstr); |
| 6416 | UInt opc2 = ifieldOPClo10(theInstr); |
| 6417 | UChar flag_rC = ifieldBIT0(theInstr); |
sewardj | e14bb9f | 2005-07-22 09:39:02 +0000 | [diff] [blame] | 6418 | |
| 6419 | IRTemp frD = newTemp(Ity_F64); |
| 6420 | IRTemp frB = newTemp(Ity_F64); |
| 6421 | |
| 6422 | if (opc1 != 0x3F || b16to20 != 0) { |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 6423 | vex_printf("dis_fp_move(ppc)(instr)\n"); |
sewardj | e14bb9f | 2005-07-22 09:39:02 +0000 | [diff] [blame] | 6424 | return False; |
| 6425 | } |
| 6426 | |
| 6427 | assign( frB, getFReg(frB_addr)); |
| 6428 | |
sewardj | e14bb9f | 2005-07-22 09:39:02 +0000 | [diff] [blame] | 6429 | switch (opc2) { |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 6430 | case 0x028: // fneg (Floating Negate, PPC32 p416) |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 6431 | DIP("fneg%s fr%u,fr%u\n", flag_rC ? ".":"", frD_addr, frB_addr); |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 6432 | assign( frD, unop( Iop_NegF64, mkexpr(frB) )); |
| 6433 | break; |
| 6434 | |
| 6435 | case 0x048: // fmr (Floating Move Register, PPC32 p410) |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 6436 | DIP("fmr%s fr%u,fr%u\n", flag_rC ? ".":"", frD_addr, frB_addr); |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 6437 | assign( frD, mkexpr(frB) ); |
| 6438 | break; |
| 6439 | |
| 6440 | case 0x088: // fnabs (Floating Negative Absolute Value, PPC32 p415) |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 6441 | DIP("fnabs%s fr%u,fr%u\n", flag_rC ? ".":"", frD_addr, frB_addr); |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 6442 | assign( frD, unop( Iop_NegF64, unop( Iop_AbsF64, mkexpr(frB) ))); |
| 6443 | break; |
| 6444 | |
| 6445 | case 0x108: // fabs (Floating Absolute Value, PPC32 p399) |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 6446 | DIP("fabs%s fr%u,fr%u\n", flag_rC ? ".":"", frD_addr, frB_addr); |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 6447 | assign( frD, unop( Iop_AbsF64, mkexpr(frB) )); |
| 6448 | break; |
| 6449 | |
| 6450 | default: |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 6451 | vex_printf("dis_fp_move(ppc)(opc2)\n"); |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 6452 | return False; |
sewardj | e14bb9f | 2005-07-22 09:39:02 +0000 | [diff] [blame] | 6453 | } |
| 6454 | |
| 6455 | putFReg( frD_addr, mkexpr(frD) ); |
sewardj | b183b85 | 2006-02-03 16:08:03 +0000 | [diff] [blame] | 6456 | |
| 6457 | /* None of these change FPRF. cr1 is set in the usual way though, |
| 6458 | if flag_rC is set. */ |
| 6459 | |
| 6460 | if (flag_rC) { |
| 6461 | putCR321( 1, mkU8(0) ); |
| 6462 | putCR0( 1, mkU8(0) ); |
| 6463 | } |
| 6464 | |
sewardj | e14bb9f | 2005-07-22 09:39:02 +0000 | [diff] [blame] | 6465 | return True; |
| 6466 | } |
| 6467 | |
| 6468 | |
| 6469 | |
| 6470 | /* |
| 6471 | Floating Point Status/Control Register Instructions |
| 6472 | */ |
| 6473 | static Bool dis_fp_scr ( UInt theInstr ) |
| 6474 | { |
cerion | 76de5cf | 2005-11-18 18:25:12 +0000 | [diff] [blame] | 6475 | /* Many forms - see each switch case */ |
| 6476 | UChar opc1 = ifieldOPC(theInstr); |
| 6477 | UInt opc2 = ifieldOPClo10(theInstr); |
| 6478 | UChar flag_rC = ifieldBIT0(theInstr); |
sewardj | e14bb9f | 2005-07-22 09:39:02 +0000 | [diff] [blame] | 6479 | |
| 6480 | if (opc1 != 0x3F) { |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 6481 | vex_printf("dis_fp_scr(ppc)(instr)\n"); |
sewardj | e14bb9f | 2005-07-22 09:39:02 +0000 | [diff] [blame] | 6482 | return False; |
| 6483 | } |
| 6484 | |
| 6485 | switch (opc2) { |
cerion | 3ea49ee | 2006-01-04 10:53:00 +0000 | [diff] [blame] | 6486 | case 0x026: { // mtfsb1 (Move to FPSCR Bit 1, PPC32 p479) |
| 6487 | // Bit crbD of the FPSCR is set. |
| 6488 | UChar crbD = ifieldRegDS(theInstr); |
| 6489 | UInt b11to20 = IFIELD(theInstr, 11, 10); |
| 6490 | |
| 6491 | if (b11to20 != 0) { |
| 6492 | vex_printf("dis_fp_scr(ppc)(instr,mtfsb1)\n"); |
| 6493 | return False; |
| 6494 | } |
| 6495 | DIP("mtfsb1%s crb%d \n", flag_rC ? ".":"", crbD); |
| 6496 | putGST_masked( PPC_GST_FPSCR, mkU32(1<<(31-crbD)), 1<<(31-crbD) ); |
| 6497 | break; |
| 6498 | } |
| 6499 | |
sewardj | 496b88f | 2006-10-04 17:46:11 +0000 | [diff] [blame^] | 6500 | case 0x040: { // mcrfs (Move to Condition Register from FPSCR, PPC32 p465) |
| 6501 | UChar crfD = toUChar( IFIELD( theInstr, 23, 3 ) ); |
| 6502 | UChar b21to22 = toUChar( IFIELD( theInstr, 21, 2 ) ); |
| 6503 | UChar crfS = toUChar( IFIELD( theInstr, 18, 3 ) ); |
| 6504 | UChar b11to17 = toUChar( IFIELD( theInstr, 11, 7 ) ); |
| 6505 | IRTemp tmp = newTemp(Ity_I32); |
| 6506 | IRExpr* fpscr_all; |
| 6507 | if (b21to22 != 0 || b11to17 != 0 || flag_rC != 0) { |
| 6508 | vex_printf("dis_fp_scr(ppc)(instr,mcrfs)\n"); |
| 6509 | return False; |
| 6510 | } |
| 6511 | DIP("mcrfs crf%d,crf%d\n", crfD, crfS); |
| 6512 | vassert(crfD < 8); |
| 6513 | vassert(crfS < 8); |
| 6514 | fpscr_all = getGST_masked( PPC_GST_FPSCR, MASK_FPSCR_RN ); |
| 6515 | assign( tmp, binop(Iop_And32, |
| 6516 | binop(Iop_Shr32,fpscr_all,mkU8(4 * (7-crfS))), |
| 6517 | mkU32(0xF)) ); |
| 6518 | putGST_field( PPC_GST_CR, mkexpr(tmp), crfD ); |
| 6519 | break; |
| 6520 | } |
sewardj | 0e2cc67 | 2005-07-29 21:58:51 +0000 | [diff] [blame] | 6521 | |
| 6522 | case 0x046: { // mtfsb0 (Move to FPSCR Bit 0, PPC32 p478) |
| 6523 | // Bit crbD of the FPSCR is cleared. |
cerion | 76de5cf | 2005-11-18 18:25:12 +0000 | [diff] [blame] | 6524 | UChar crbD = ifieldRegDS(theInstr); |
| 6525 | UInt b11to20 = IFIELD(theInstr, 11, 10); |
sewardj | 0e2cc67 | 2005-07-29 21:58:51 +0000 | [diff] [blame] | 6526 | |
| 6527 | if (b11to20 != 0) { |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 6528 | vex_printf("dis_fp_scr(ppc)(instr,mtfsb0)\n"); |
sewardj | 0e2cc67 | 2005-07-29 21:58:51 +0000 | [diff] [blame] | 6529 | return False; |
| 6530 | } |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 6531 | DIP("mtfsb0%s crb%d\n", flag_rC ? ".":"", crbD); |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 6532 | putGST_masked( PPC_GST_FPSCR, mkU32(0), 1<<(31-crbD) ); |
sewardj | 0e2cc67 | 2005-07-29 21:58:51 +0000 | [diff] [blame] | 6533 | break; |
| 6534 | } |
| 6535 | |
| 6536 | case 0x086: { // mtfsfi (Move to FPSCR Field Immediate, PPC32 p481) |
cerion | 76de5cf | 2005-11-18 18:25:12 +0000 | [diff] [blame] | 6537 | UChar crfD = toUChar( IFIELD( theInstr, 23, 3 ) ); |
| 6538 | UChar b16to22 = toUChar( IFIELD( theInstr, 16, 7 ) ); |
| 6539 | UChar IMM = toUChar( IFIELD( theInstr, 12, 4 ) ); |
| 6540 | UChar b11 = toUChar( IFIELD( theInstr, 11, 1 ) ); |
sewardj | 0e2cc67 | 2005-07-29 21:58:51 +0000 | [diff] [blame] | 6541 | |
| 6542 | if (b16to22 != 0 || b11 != 0) { |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 6543 | vex_printf("dis_fp_scr(ppc)(instr,mtfsfi)\n"); |
sewardj | 0e2cc67 | 2005-07-29 21:58:51 +0000 | [diff] [blame] | 6544 | return False; |
| 6545 | } |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 6546 | DIP("mtfsfi%s crf%d,%d\n", flag_rC ? ".":"", crfD, IMM); |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 6547 | putGST_field( PPC_GST_FPSCR, mkU32(IMM), crfD ); |
sewardj | 0e2cc67 | 2005-07-29 21:58:51 +0000 | [diff] [blame] | 6548 | break; |
| 6549 | } |
sewardj | e14bb9f | 2005-07-22 09:39:02 +0000 | [diff] [blame] | 6550 | |
| 6551 | case 0x247: { // mffs (Move from FPSCR, PPC32 p468) |
sewardj | 496b88f | 2006-10-04 17:46:11 +0000 | [diff] [blame^] | 6552 | UChar frD_addr = ifieldRegDS(theInstr); |
| 6553 | UInt b11to20 = IFIELD(theInstr, 11, 10); |
| 6554 | IRExpr* fpscr_all = getGST_masked( PPC_GST_FPSCR, MASK_FPSCR_RN ); |
sewardj | e14bb9f | 2005-07-22 09:39:02 +0000 | [diff] [blame] | 6555 | |
| 6556 | if (b11to20 != 0) { |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 6557 | vex_printf("dis_fp_scr(ppc)(instr,mffs)\n"); |
sewardj | e14bb9f | 2005-07-22 09:39:02 +0000 | [diff] [blame] | 6558 | return False; |
| 6559 | } |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 6560 | DIP("mffs%s fr%u\n", flag_rC ? ".":"", frD_addr); |
| 6561 | putFReg( frD_addr, |
| 6562 | unop( Iop_ReinterpI64asF64, |
sewardj | 496b88f | 2006-10-04 17:46:11 +0000 | [diff] [blame^] | 6563 | unop( Iop_32Uto64, fpscr_all ))); |
sewardj | e14bb9f | 2005-07-22 09:39:02 +0000 | [diff] [blame] | 6564 | break; |
| 6565 | } |
| 6566 | |
| 6567 | case 0x2C7: { // mtfsf (Move to FPSCR Fields, PPC32 p480) |
cerion | 76de5cf | 2005-11-18 18:25:12 +0000 | [diff] [blame] | 6568 | UChar b25 = toUChar( IFIELD(theInstr, 25, 1) ); |
| 6569 | UChar FM = toUChar( IFIELD(theInstr, 17, 8) ); |
| 6570 | UChar b16 = toUChar( IFIELD(theInstr, 16, 1) ); |
| 6571 | UChar frB_addr = ifieldRegB(theInstr); |
| 6572 | IRTemp frB = newTemp(Ity_F64); |
sewardj | e14bb9f | 2005-07-22 09:39:02 +0000 | [diff] [blame] | 6573 | IRTemp rB_32 = newTemp(Ity_I32); |
cerion | 76de5cf | 2005-11-18 18:25:12 +0000 | [diff] [blame] | 6574 | Int i, mask; |
sewardj | e14bb9f | 2005-07-22 09:39:02 +0000 | [diff] [blame] | 6575 | |
| 6576 | if (b25 != 0 || b16 != 0) { |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 6577 | vex_printf("dis_fp_scr(ppc)(instr,mtfsf)\n"); |
sewardj | e14bb9f | 2005-07-22 09:39:02 +0000 | [diff] [blame] | 6578 | return False; |
| 6579 | } |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 6580 | DIP("mtfsf%s %d,fr%u\n", flag_rC ? ".":"", FM, frB_addr); |
sewardj | e14bb9f | 2005-07-22 09:39:02 +0000 | [diff] [blame] | 6581 | assign( frB, getFReg(frB_addr)); |
| 6582 | assign( rB_32, unop( Iop_64to32, |
| 6583 | unop( Iop_ReinterpF64asI64, mkexpr(frB) ))); |
| 6584 | // Build 32bit mask from FM: |
cerion | 76de5cf | 2005-11-18 18:25:12 +0000 | [diff] [blame] | 6585 | mask = 0; |
sewardj | e14bb9f | 2005-07-22 09:39:02 +0000 | [diff] [blame] | 6586 | for (i=0; i<8; i++) { |
| 6587 | if ((FM & (1<<(7-i))) == 1) { |
| 6588 | mask |= 0xF << (7-i); |
| 6589 | } |
| 6590 | } |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 6591 | putGST_masked( PPC_GST_FPSCR, mkexpr(rB_32), mask ); |
sewardj | e14bb9f | 2005-07-22 09:39:02 +0000 | [diff] [blame] | 6592 | break; |
| 6593 | } |
| 6594 | |
| 6595 | default: |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 6596 | vex_printf("dis_fp_scr(ppc)(opc2)\n"); |
sewardj | e14bb9f | 2005-07-22 09:39:02 +0000 | [diff] [blame] | 6597 | return False; |
| 6598 | } |
| 6599 | return True; |
| 6600 | } |
| 6601 | |
| 6602 | |
| 6603 | |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 6604 | /*------------------------------------------------------------*/ |
| 6605 | /*--- AltiVec Instruction Translation ---*/ |
| 6606 | /*------------------------------------------------------------*/ |
| 6607 | |
| 6608 | /* |
| 6609 | Altivec Cache Control Instructions (Data Streams) |
| 6610 | */ |
| 6611 | static Bool dis_av_datastream ( UInt theInstr ) |
| 6612 | { |
cerion | 76de5cf | 2005-11-18 18:25:12 +0000 | [diff] [blame] | 6613 | /* X-Form */ |
| 6614 | UChar opc1 = ifieldOPC(theInstr); |
| 6615 | UChar flag_T = toUChar( IFIELD( theInstr, 25, 1 ) ); |
| 6616 | UChar flag_A = flag_T; |
| 6617 | UChar b23to24 = toUChar( IFIELD( theInstr, 23, 2 ) ); |
| 6618 | UChar STRM = toUChar( IFIELD( theInstr, 21, 2 ) ); |
| 6619 | UChar rA_addr = ifieldRegA(theInstr); |
| 6620 | UChar rB_addr = ifieldRegB(theInstr); |
| 6621 | UInt opc2 = ifieldOPClo10(theInstr); |
| 6622 | UChar b0 = ifieldBIT0(theInstr); |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 6623 | |
| 6624 | if (opc1 != 0x1F || b23to24 != 0 || b0 != 0) { |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 6625 | vex_printf("dis_av_datastream(ppc)(instr)\n"); |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 6626 | return False; |
| 6627 | } |
| 6628 | |
| 6629 | switch (opc2) { |
| 6630 | case 0x156: // dst (Data Stream Touch, AV p115) |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 6631 | DIP("dst%s r%u,r%u,%d\n", flag_T ? "t" : "", |
| 6632 | rA_addr, rB_addr, STRM); |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 6633 | DIP(" => not implemented\n"); |
| 6634 | return False; |
| 6635 | |
| 6636 | case 0x176: // dstst (Data Stream Touch for Store, AV p117) |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 6637 | DIP("dstst%s r%u,r%u,%d\n", flag_T ? "t" : "", |
| 6638 | rA_addr, rB_addr, STRM); |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 6639 | DIP(" => not implemented\n"); |
| 6640 | return False; |
| 6641 | |
| 6642 | case 0x336: // dss (Data Stream Stop, AV p114) |
| 6643 | if (rA_addr != 0 || rB_addr != 0) { |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 6644 | vex_printf("dis_av_datastream(ppc)(opc2,dst)\n"); |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 6645 | return False; |
| 6646 | } |
| 6647 | if (flag_A == 0) { |
| 6648 | DIP("dss %d\n", STRM); |
| 6649 | DIP(" => not implemented\n"); |
| 6650 | } else { |
| 6651 | DIP("dssall\n"); |
| 6652 | DIP(" => not implemented\n"); |
| 6653 | } |
| 6654 | return False; |
| 6655 | |
| 6656 | default: |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 6657 | vex_printf("dis_av_datastream(ppc)(opc2)\n"); |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 6658 | return False; |
| 6659 | } |
| 6660 | return True; |
| 6661 | } |
| 6662 | |
| 6663 | /* |
| 6664 | AltiVec Processor Control Instructions |
| 6665 | */ |
| 6666 | static Bool dis_av_procctl ( UInt theInstr ) |
| 6667 | { |
cerion | 76de5cf | 2005-11-18 18:25:12 +0000 | [diff] [blame] | 6668 | /* VX-Form */ |
| 6669 | UChar opc1 = ifieldOPC(theInstr); |
| 6670 | UChar vD_addr = ifieldRegDS(theInstr); |
| 6671 | UChar vA_addr = ifieldRegA(theInstr); |
| 6672 | UChar vB_addr = ifieldRegB(theInstr); |
| 6673 | UInt opc2 = IFIELD( theInstr, 0, 11 ); |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 6674 | |
| 6675 | if (opc1 != 0x4) { |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 6676 | vex_printf("dis_av_procctl(ppc)(instr)\n"); |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 6677 | return False; |
| 6678 | } |
| 6679 | |
| 6680 | switch (opc2) { |
| 6681 | case 0x604: // mfvscr (Move from VSCR, AV p129) |
| 6682 | if (vA_addr != 0 || vB_addr != 0) { |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 6683 | vex_printf("dis_av_procctl(ppc)(opc2,dst)\n"); |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 6684 | return False; |
| 6685 | } |
| 6686 | DIP("mfvscr v%d\n", vD_addr); |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 6687 | putVReg( vD_addr, unop(Iop_32UtoV128, getGST( PPC_GST_VSCR )) ); |
cerion | 225a034 | 2005-09-12 20:49:09 +0000 | [diff] [blame] | 6688 | break; |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 6689 | |
cerion | 225a034 | 2005-09-12 20:49:09 +0000 | [diff] [blame] | 6690 | case 0x644: { // mtvscr (Move to VSCR, AV p130) |
sewardj | 197bd17 | 2005-10-12 11:34:33 +0000 | [diff] [blame] | 6691 | IRTemp vB = newTemp(Ity_V128); |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 6692 | if (vD_addr != 0 || vA_addr != 0) { |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 6693 | vex_printf("dis_av_procctl(ppc)(opc2,dst)\n"); |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 6694 | return False; |
| 6695 | } |
| 6696 | DIP("mtvscr v%d\n", vB_addr); |
cerion | 225a034 | 2005-09-12 20:49:09 +0000 | [diff] [blame] | 6697 | assign( vB, getVReg(vB_addr)); |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 6698 | putGST( PPC_GST_VSCR, unop(Iop_V128to32, mkexpr(vB)) ); |
cerion | 225a034 | 2005-09-12 20:49:09 +0000 | [diff] [blame] | 6699 | break; |
| 6700 | } |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 6701 | default: |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 6702 | vex_printf("dis_av_procctl(ppc)(opc2)\n"); |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 6703 | return False; |
| 6704 | } |
| 6705 | return True; |
| 6706 | } |
cerion | a982c05 | 2005-06-28 17:23:09 +0000 | [diff] [blame] | 6707 | |
| 6708 | /* |
| 6709 | AltiVec Load Instructions |
| 6710 | */ |
| 6711 | static Bool dis_av_load ( UInt theInstr ) |
| 6712 | { |
cerion | 76de5cf | 2005-11-18 18:25:12 +0000 | [diff] [blame] | 6713 | /* X-Form */ |
| 6714 | UChar opc1 = ifieldOPC(theInstr); |
| 6715 | UChar vD_addr = ifieldRegDS(theInstr); |
| 6716 | UChar rA_addr = ifieldRegA(theInstr); |
| 6717 | UChar rB_addr = ifieldRegB(theInstr); |
| 6718 | UInt opc2 = ifieldOPClo10(theInstr); |
| 6719 | UChar b0 = ifieldBIT0(theInstr); |
cerion | a982c05 | 2005-06-28 17:23:09 +0000 | [diff] [blame] | 6720 | |
cerion | fb197c4 | 2005-12-24 12:32:10 +0000 | [diff] [blame] | 6721 | IRType ty = mode64 ? Ity_I64 : Ity_I32; |
| 6722 | IRTemp EA = newTemp(ty); |
| 6723 | IRTemp EA_align16 = newTemp(ty); |
cerion | 2831b00 | 2005-11-30 19:55:22 +0000 | [diff] [blame] | 6724 | |
cerion | a982c05 | 2005-06-28 17:23:09 +0000 | [diff] [blame] | 6725 | if (opc1 != 0x1F || b0 != 0) { |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 6726 | vex_printf("dis_av_load(ppc)(instr)\n"); |
cerion | a982c05 | 2005-06-28 17:23:09 +0000 | [diff] [blame] | 6727 | return False; |
| 6728 | } |
| 6729 | |
cerion | fb197c4 | 2005-12-24 12:32:10 +0000 | [diff] [blame] | 6730 | assign( EA, ea_rAor0_idxd(rA_addr, rB_addr) ); |
| 6731 | assign( EA_align16, addr_align( mkexpr(EA), 16 ) ); |
cerion | a50fde5 | 2005-07-01 21:16:10 +0000 | [diff] [blame] | 6732 | |
cerion | a982c05 | 2005-06-28 17:23:09 +0000 | [diff] [blame] | 6733 | switch (opc2) { |
| 6734 | |
cerion | 6f6c6a0 | 2005-09-13 18:41:09 +0000 | [diff] [blame] | 6735 | case 0x006: { // lvsl (Load Vector for Shift Left, AV p123) |
cerion | fb197c4 | 2005-12-24 12:32:10 +0000 | [diff] [blame] | 6736 | IRDirty* d; |
sewardj | d147094 | 2005-10-22 02:01:16 +0000 | [diff] [blame] | 6737 | UInt vD_off = vectorGuestRegOffset(vD_addr); |
| 6738 | IRExpr** args = mkIRExprVec_3( |
| 6739 | mkU32(vD_off), |
cerion | fb197c4 | 2005-12-24 12:32:10 +0000 | [diff] [blame] | 6740 | binop(Iop_And32, mkSzNarrow32(ty, mkexpr(EA)), |
| 6741 | mkU32(0xF)), |
sewardj | d147094 | 2005-10-22 02:01:16 +0000 | [diff] [blame] | 6742 | mkU32(0)/*left*/ ); |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 6743 | if (!mode64) { |
cerion | 4c4f5ef | 2006-01-02 14:41:50 +0000 | [diff] [blame] | 6744 | d = unsafeIRDirty_0_N ( |
| 6745 | 0/*regparms*/, |
| 6746 | "ppc32g_dirtyhelper_LVS", |
| 6747 | fnptr_to_fnentry(&ppc32g_dirtyhelper_LVS), |
| 6748 | args ); |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 6749 | } else { |
cerion | 4c4f5ef | 2006-01-02 14:41:50 +0000 | [diff] [blame] | 6750 | d = unsafeIRDirty_0_N ( |
| 6751 | 0/*regparms*/, |
| 6752 | "ppc64g_dirtyhelper_LVS", |
| 6753 | fnptr_to_fnentry(&ppc64g_dirtyhelper_LVS), |
| 6754 | args ); |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 6755 | } |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 6756 | DIP("lvsl v%d,r%u,r%u\n", vD_addr, rA_addr, rB_addr); |
cerion | 6f6c6a0 | 2005-09-13 18:41:09 +0000 | [diff] [blame] | 6757 | /* declare guest state effects */ |
| 6758 | d->needsBBP = True; |
| 6759 | d->nFxState = 1; |
| 6760 | d->fxState[0].fx = Ifx_Write; |
sewardj | d147094 | 2005-10-22 02:01:16 +0000 | [diff] [blame] | 6761 | d->fxState[0].offset = vD_off; |
cerion | 6f6c6a0 | 2005-09-13 18:41:09 +0000 | [diff] [blame] | 6762 | d->fxState[0].size = sizeof(U128); |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 6763 | |
cerion | 6f6c6a0 | 2005-09-13 18:41:09 +0000 | [diff] [blame] | 6764 | /* execute the dirty call, side-effecting guest state */ |
| 6765 | stmt( IRStmt_Dirty(d) ); |
| 6766 | break; |
| 6767 | } |
| 6768 | case 0x026: { // lvsr (Load Vector for Shift Right, AV p125) |
cerion | fb197c4 | 2005-12-24 12:32:10 +0000 | [diff] [blame] | 6769 | IRDirty* d; |
sewardj | d147094 | 2005-10-22 02:01:16 +0000 | [diff] [blame] | 6770 | UInt vD_off = vectorGuestRegOffset(vD_addr); |
| 6771 | IRExpr** args = mkIRExprVec_3( |
| 6772 | mkU32(vD_off), |
cerion | fb197c4 | 2005-12-24 12:32:10 +0000 | [diff] [blame] | 6773 | binop(Iop_And32, mkSzNarrow32(ty, mkexpr(EA)), |
| 6774 | mkU32(0xF)), |
sewardj | d147094 | 2005-10-22 02:01:16 +0000 | [diff] [blame] | 6775 | mkU32(1)/*right*/ ); |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 6776 | if (!mode64) { |
cerion | 4c4f5ef | 2006-01-02 14:41:50 +0000 | [diff] [blame] | 6777 | d = unsafeIRDirty_0_N ( |
| 6778 | 0/*regparms*/, |
| 6779 | "ppc32g_dirtyhelper_LVS", |
| 6780 | fnptr_to_fnentry(&ppc32g_dirtyhelper_LVS), |
| 6781 | args ); |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 6782 | } else { |
cerion | 4c4f5ef | 2006-01-02 14:41:50 +0000 | [diff] [blame] | 6783 | d = unsafeIRDirty_0_N ( |
| 6784 | 0/*regparms*/, |
| 6785 | "ppc64g_dirtyhelper_LVS", |
| 6786 | fnptr_to_fnentry(&ppc64g_dirtyhelper_LVS), |
| 6787 | args ); |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 6788 | } |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 6789 | DIP("lvsr v%d,r%u,r%u\n", vD_addr, rA_addr, rB_addr); |
cerion | 6f6c6a0 | 2005-09-13 18:41:09 +0000 | [diff] [blame] | 6790 | /* declare guest state effects */ |
| 6791 | d->needsBBP = True; |
| 6792 | d->nFxState = 1; |
| 6793 | d->fxState[0].fx = Ifx_Write; |
sewardj | d147094 | 2005-10-22 02:01:16 +0000 | [diff] [blame] | 6794 | d->fxState[0].offset = vD_off; |
cerion | 6f6c6a0 | 2005-09-13 18:41:09 +0000 | [diff] [blame] | 6795 | d->fxState[0].size = sizeof(U128); |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 6796 | |
cerion | 6f6c6a0 | 2005-09-13 18:41:09 +0000 | [diff] [blame] | 6797 | /* execute the dirty call, side-effecting guest state */ |
| 6798 | stmt( IRStmt_Dirty(d) ); |
| 6799 | break; |
| 6800 | } |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 6801 | case 0x007: // lvebx (Load Vector Element Byte Indexed, AV p119) |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 6802 | DIP("lvebx v%d,r%u,r%u\n", vD_addr, rA_addr, rB_addr); |
cerion | 61c9274 | 2005-09-14 22:59:26 +0000 | [diff] [blame] | 6803 | /* loads addressed byte into vector[EA[0:3] |
| 6804 | since all other destination bytes are undefined, |
| 6805 | can simply load entire vector from 16-aligned EA */ |
cerion | fb197c4 | 2005-12-24 12:32:10 +0000 | [diff] [blame] | 6806 | putVReg( vD_addr, loadBE(Ity_V128, mkexpr(EA_align16)) ); |
cerion | 61c9274 | 2005-09-14 22:59:26 +0000 | [diff] [blame] | 6807 | break; |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 6808 | |
| 6809 | case 0x027: // lvehx (Load Vector Element Half Word Indexed, AV p121) |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 6810 | DIP("lvehx v%d,r%u,r%u\n", vD_addr, rA_addr, rB_addr); |
cerion | 61c9274 | 2005-09-14 22:59:26 +0000 | [diff] [blame] | 6811 | /* see note for lvebx */ |
cerion | fb197c4 | 2005-12-24 12:32:10 +0000 | [diff] [blame] | 6812 | putVReg( vD_addr, loadBE(Ity_V128, mkexpr(EA_align16)) ); |
cerion | 61c9274 | 2005-09-14 22:59:26 +0000 | [diff] [blame] | 6813 | break; |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 6814 | |
| 6815 | case 0x047: // lvewx (Load Vector Element Word Indexed, AV p122) |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 6816 | DIP("lvewx v%d,r%u,r%u\n", vD_addr, rA_addr, rB_addr); |
cerion | 61c9274 | 2005-09-14 22:59:26 +0000 | [diff] [blame] | 6817 | /* see note for lvebx */ |
cerion | fb197c4 | 2005-12-24 12:32:10 +0000 | [diff] [blame] | 6818 | putVReg( vD_addr, loadBE(Ity_V128, mkexpr(EA_align16)) ); |
cerion | 61c9274 | 2005-09-14 22:59:26 +0000 | [diff] [blame] | 6819 | break; |
cerion | a982c05 | 2005-06-28 17:23:09 +0000 | [diff] [blame] | 6820 | |
| 6821 | case 0x067: // lvx (Load Vector Indexed, AV p127) |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 6822 | DIP("lvx v%d,r%u,r%u\n", vD_addr, rA_addr, rB_addr); |
cerion | fb197c4 | 2005-12-24 12:32:10 +0000 | [diff] [blame] | 6823 | putVReg( vD_addr, loadBE(Ity_V128, mkexpr(EA_align16)) ); |
cerion | a50fde5 | 2005-07-01 21:16:10 +0000 | [diff] [blame] | 6824 | break; |
cerion | a982c05 | 2005-06-28 17:23:09 +0000 | [diff] [blame] | 6825 | |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 6826 | case 0x167: // lvxl (Load Vector Indexed LRU, AV p128) |
| 6827 | // XXX: lvxl gives explicit control over cache block replacement |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 6828 | DIP("lvxl v%d,r%u,r%u\n", vD_addr, rA_addr, rB_addr); |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 6829 | DIP(" => not implemented\n"); |
| 6830 | return False; |
cerion | a982c05 | 2005-06-28 17:23:09 +0000 | [diff] [blame] | 6831 | |
| 6832 | default: |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 6833 | vex_printf("dis_av_load(ppc)(opc2)\n"); |
cerion | a982c05 | 2005-06-28 17:23:09 +0000 | [diff] [blame] | 6834 | return False; |
| 6835 | } |
| 6836 | return True; |
| 6837 | } |
| 6838 | |
cerion | 2831b00 | 2005-11-30 19:55:22 +0000 | [diff] [blame] | 6839 | |
cerion | a982c05 | 2005-06-28 17:23:09 +0000 | [diff] [blame] | 6840 | /* |
| 6841 | AltiVec Store Instructions |
| 6842 | */ |
| 6843 | static Bool dis_av_store ( UInt theInstr ) |
| 6844 | { |
cerion | 76de5cf | 2005-11-18 18:25:12 +0000 | [diff] [blame] | 6845 | /* X-Form */ |
| 6846 | UChar opc1 = ifieldOPC(theInstr); |
| 6847 | UChar vS_addr = ifieldRegDS(theInstr); |
| 6848 | UChar rA_addr = ifieldRegA(theInstr); |
| 6849 | UChar rB_addr = ifieldRegB(theInstr); |
| 6850 | UInt opc2 = ifieldOPClo10(theInstr); |
| 6851 | UChar b0 = ifieldBIT0(theInstr); |
cerion | a982c05 | 2005-06-28 17:23:09 +0000 | [diff] [blame] | 6852 | |
cerion | 2831b00 | 2005-11-30 19:55:22 +0000 | [diff] [blame] | 6853 | IRType ty = mode64 ? Ity_I64 : Ity_I32; |
| 6854 | IRTemp EA = newTemp(ty); |
cerion | dba87e2 | 2006-01-02 15:15:45 +0000 | [diff] [blame] | 6855 | IRTemp addr_aligned = newTemp(ty); |
cerion | 2831b00 | 2005-11-30 19:55:22 +0000 | [diff] [blame] | 6856 | IRTemp vS = newTemp(Ity_V128); |
| 6857 | IRTemp eb = newTemp(Ity_I8); |
| 6858 | IRTemp idx = newTemp(Ity_I8); |
cerion | a982c05 | 2005-06-28 17:23:09 +0000 | [diff] [blame] | 6859 | |
| 6860 | if (opc1 != 0x1F || b0 != 0) { |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 6861 | vex_printf("dis_av_store(ppc)(instr)\n"); |
cerion | a982c05 | 2005-06-28 17:23:09 +0000 | [diff] [blame] | 6862 | return False; |
| 6863 | } |
| 6864 | |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 6865 | assign( vS, getVReg(vS_addr)); |
cerion | 2831b00 | 2005-11-30 19:55:22 +0000 | [diff] [blame] | 6866 | assign( EA, ea_rAor0_idxd(rA_addr, rB_addr) ); |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 6867 | |
cerion | a982c05 | 2005-06-28 17:23:09 +0000 | [diff] [blame] | 6868 | switch (opc2) { |
cerion | 61c9274 | 2005-09-14 22:59:26 +0000 | [diff] [blame] | 6869 | case 0x087: { // stvebx (Store Vector Byte Indexed, AV p131) |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 6870 | DIP("stvebx v%d,r%u,r%u\n", vS_addr, rA_addr, rB_addr); |
cerion | 61c9274 | 2005-09-14 22:59:26 +0000 | [diff] [blame] | 6871 | assign( eb, binop(Iop_And8, mkU8(0xF), |
cerion | 2831b00 | 2005-11-30 19:55:22 +0000 | [diff] [blame] | 6872 | unop(Iop_32to8, |
| 6873 | mkSzNarrow32(ty, mkexpr(EA)) )) ); |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 6874 | assign( idx, binop(Iop_Shl8, |
| 6875 | binop(Iop_Sub8, mkU8(15), mkexpr(eb)), |
cerion | 61c9274 | 2005-09-14 22:59:26 +0000 | [diff] [blame] | 6876 | mkU8(3)) ); |
| 6877 | storeBE( mkexpr(EA), |
| 6878 | unop(Iop_32to8, unop(Iop_V128to32, |
| 6879 | binop(Iop_ShrV128, mkexpr(vS), mkexpr(idx)))) ); |
| 6880 | break; |
| 6881 | } |
| 6882 | case 0x0A7: { // stvehx (Store Vector Half Word Indexed, AV p132) |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 6883 | DIP("stvehx v%d,r%u,r%u\n", vS_addr, rA_addr, rB_addr); |
cerion | dba87e2 | 2006-01-02 15:15:45 +0000 | [diff] [blame] | 6884 | assign( addr_aligned, addr_align(mkexpr(EA), 2) ); |
cerion | 61c9274 | 2005-09-14 22:59:26 +0000 | [diff] [blame] | 6885 | assign( eb, binop(Iop_And8, mkU8(0xF), |
cerion | dba87e2 | 2006-01-02 15:15:45 +0000 | [diff] [blame] | 6886 | mkSzNarrow8(ty, mkexpr(addr_aligned) )) ); |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 6887 | assign( idx, binop(Iop_Shl8, |
| 6888 | binop(Iop_Sub8, mkU8(14), mkexpr(eb)), |
cerion | 61c9274 | 2005-09-14 22:59:26 +0000 | [diff] [blame] | 6889 | mkU8(3)) ); |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 6890 | storeBE( mkexpr(addr_aligned), |
cerion | 61c9274 | 2005-09-14 22:59:26 +0000 | [diff] [blame] | 6891 | unop(Iop_32to16, unop(Iop_V128to32, |
| 6892 | binop(Iop_ShrV128, mkexpr(vS), mkexpr(idx)))) ); |
| 6893 | break; |
| 6894 | } |
| 6895 | case 0x0C7: { // stvewx (Store Vector Word Indexed, AV p133) |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 6896 | DIP("stvewx v%d,r%u,r%u\n", vS_addr, rA_addr, rB_addr); |
cerion | dba87e2 | 2006-01-02 15:15:45 +0000 | [diff] [blame] | 6897 | assign( addr_aligned, addr_align(mkexpr(EA), 4) ); |
cerion | 61c9274 | 2005-09-14 22:59:26 +0000 | [diff] [blame] | 6898 | assign( eb, binop(Iop_And8, mkU8(0xF), |
cerion | dba87e2 | 2006-01-02 15:15:45 +0000 | [diff] [blame] | 6899 | mkSzNarrow8(ty, mkexpr(addr_aligned) )) ); |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 6900 | assign( idx, binop(Iop_Shl8, |
| 6901 | binop(Iop_Sub8, mkU8(12), mkexpr(eb)), |
cerion | 61c9274 | 2005-09-14 22:59:26 +0000 | [diff] [blame] | 6902 | mkU8(3)) ); |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 6903 | storeBE( mkexpr(addr_aligned), |
cerion | 61c9274 | 2005-09-14 22:59:26 +0000 | [diff] [blame] | 6904 | unop(Iop_V128to32, |
| 6905 | binop(Iop_ShrV128, mkexpr(vS), mkexpr(idx))) ); |
| 6906 | break; |
| 6907 | } |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 6908 | |
cerion | a982c05 | 2005-06-28 17:23:09 +0000 | [diff] [blame] | 6909 | case 0x0E7: // stvx (Store Vector Indexed, AV p134) |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 6910 | DIP("stvx v%d,r%u,r%u\n", vS_addr, rA_addr, rB_addr); |
| 6911 | storeBE( addr_align( mkexpr(EA), 16 ), mkexpr(vS) ); |
cerion | a982c05 | 2005-06-28 17:23:09 +0000 | [diff] [blame] | 6912 | break; |
| 6913 | |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 6914 | case 0x1E7: // stvxl (Store Vector Indexed LRU, AV p135) |
| 6915 | // XXX: stvxl can give explicit control over cache block replacement |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 6916 | DIP("stvxl v%d,r%u,r%u\n", vS_addr, rA_addr, rB_addr); |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 6917 | DIP(" => not implemented\n"); |
| 6918 | return False; |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 6919 | // STORE(vS, 16, addr_align( mkexpr(EA), 16 )); |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 6920 | // break; |
cerion | a982c05 | 2005-06-28 17:23:09 +0000 | [diff] [blame] | 6921 | |
| 6922 | default: |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 6923 | vex_printf("dis_av_store(ppc)(opc2)\n"); |
cerion | a982c05 | 2005-06-28 17:23:09 +0000 | [diff] [blame] | 6924 | return False; |
| 6925 | } |
| 6926 | return True; |
| 6927 | } |
| 6928 | |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 6929 | /* |
| 6930 | AltiVec Arithmetic Instructions |
| 6931 | */ |
| 6932 | static Bool dis_av_arith ( UInt theInstr ) |
| 6933 | { |
cerion | 76de5cf | 2005-11-18 18:25:12 +0000 | [diff] [blame] | 6934 | /* VX-Form */ |
| 6935 | UChar opc1 = ifieldOPC(theInstr); |
| 6936 | UChar vD_addr = ifieldRegDS(theInstr); |
| 6937 | UChar vA_addr = ifieldRegA(theInstr); |
| 6938 | UChar vB_addr = ifieldRegB(theInstr); |
| 6939 | UInt opc2 = IFIELD( theInstr, 0, 11 ); |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 6940 | |
cerion | d3e5241 | 2005-09-14 21:15:40 +0000 | [diff] [blame] | 6941 | IRTemp vA = newTemp(Ity_V128); |
| 6942 | IRTemp vB = newTemp(Ity_V128); |
cerion | 4a49b03 | 2005-11-08 16:23:07 +0000 | [diff] [blame] | 6943 | IRTemp z3 = newTemp(Ity_I64); |
| 6944 | IRTemp z2 = newTemp(Ity_I64); |
| 6945 | IRTemp z1 = newTemp(Ity_I64); |
| 6946 | IRTemp z0 = newTemp(Ity_I64); |
| 6947 | IRTemp aEvn, aOdd; |
| 6948 | IRTemp a15, a14, a13, a12, a11, a10, a9, a8; |
| 6949 | IRTemp a7, a6, a5, a4, a3, a2, a1, a0; |
| 6950 | IRTemp b3, b2, b1, b0; |
| 6951 | |
| 6952 | aEvn = aOdd = IRTemp_INVALID; |
| 6953 | a15 = a14 = a13 = a12 = a11 = a10 = a9 = a8 = IRTemp_INVALID; |
| 6954 | a7 = a6 = a5 = a4 = a3 = a2 = a1 = a0 = IRTemp_INVALID; |
| 6955 | b3 = b2 = b1 = b0 = IRTemp_INVALID; |
| 6956 | |
cerion | d3e5241 | 2005-09-14 21:15:40 +0000 | [diff] [blame] | 6957 | assign( vA, getVReg(vA_addr)); |
| 6958 | assign( vB, getVReg(vB_addr)); |
| 6959 | |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 6960 | if (opc1 != 0x4) { |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 6961 | vex_printf("dis_av_arith(ppc)(opc1 != 0x4)\n"); |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 6962 | return False; |
| 6963 | } |
| 6964 | |
| 6965 | switch (opc2) { |
| 6966 | /* Add */ |
cerion | d3e5241 | 2005-09-14 21:15:40 +0000 | [diff] [blame] | 6967 | case 0x180: { // vaddcuw (Add Carryout Unsigned Word, AV p136) |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 6968 | DIP("vaddcuw v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr); |
cerion | 36991ef | 2005-09-15 12:42:16 +0000 | [diff] [blame] | 6969 | /* unsigned_ov(x+y) = (y >u not(x)) */ |
cerion | d3e5241 | 2005-09-14 21:15:40 +0000 | [diff] [blame] | 6970 | putVReg( vD_addr, binop(Iop_ShrN32x4, |
cerion | 36991ef | 2005-09-15 12:42:16 +0000 | [diff] [blame] | 6971 | binop(Iop_CmpGT32Ux4, mkexpr(vB), |
| 6972 | unop(Iop_NotV128, mkexpr(vA))), |
cerion | d3e5241 | 2005-09-14 21:15:40 +0000 | [diff] [blame] | 6973 | mkU8(31)) ); |
| 6974 | break; |
| 6975 | } |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 6976 | case 0x000: // vaddubm (Add Unsigned Byte Modulo, AV p141) |
| 6977 | DIP("vaddubm v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr); |
cerion | 36991ef | 2005-09-15 12:42:16 +0000 | [diff] [blame] | 6978 | putVReg( vD_addr, binop(Iop_Add8x16, mkexpr(vA), mkexpr(vB)) ); |
| 6979 | break; |
| 6980 | |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 6981 | case 0x040: // vadduhm (Add Unsigned Half Word Modulo, AV p143) |
| 6982 | DIP("vadduhm v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr); |
cerion | 36991ef | 2005-09-15 12:42:16 +0000 | [diff] [blame] | 6983 | putVReg( vD_addr, binop(Iop_Add16x8, mkexpr(vA), mkexpr(vB)) ); |
| 6984 | break; |
| 6985 | |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 6986 | case 0x080: // vadduwm (Add Unsigned Word Modulo, AV p145) |
| 6987 | DIP("vadduwm v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr); |
cerion | 36991ef | 2005-09-15 12:42:16 +0000 | [diff] [blame] | 6988 | putVReg( vD_addr, binop(Iop_Add32x4, mkexpr(vA), mkexpr(vB)) ); |
| 6989 | break; |
| 6990 | |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 6991 | case 0x200: // vaddubs (Add Unsigned Byte Saturate, AV p142) |
| 6992 | DIP("vaddubs v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr); |
cerion | 36991ef | 2005-09-15 12:42:16 +0000 | [diff] [blame] | 6993 | putVReg( vD_addr, binop(Iop_QAdd8Ux16, mkexpr(vA), mkexpr(vB)) ); |
| 6994 | // TODO: set VSCR[SAT], perhaps via new primop: Iop_SatOfQAdd8Ux16 |
| 6995 | break; |
| 6996 | |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 6997 | case 0x240: // vadduhs (Add Unsigned Half Word Saturate, AV p144) |
| 6998 | DIP("vadduhs v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr); |
cerion | 36991ef | 2005-09-15 12:42:16 +0000 | [diff] [blame] | 6999 | putVReg( vD_addr, binop(Iop_QAdd16Ux8, mkexpr(vA), mkexpr(vB)) ); |
| 7000 | // TODO: set VSCR[SAT] |
| 7001 | break; |
| 7002 | |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 7003 | case 0x280: // vadduws (Add Unsigned Word Saturate, AV p146) |
| 7004 | DIP("vadduws v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr); |
cerion | 36991ef | 2005-09-15 12:42:16 +0000 | [diff] [blame] | 7005 | putVReg( vD_addr, binop(Iop_QAdd32Ux4, mkexpr(vA), mkexpr(vB)) ); |
| 7006 | // TODO: set VSCR[SAT] |
| 7007 | break; |
| 7008 | |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 7009 | case 0x300: // vaddsbs (Add Signed Byte Saturate, AV p138) |
| 7010 | DIP("vaddsbs v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr); |
cerion | 36991ef | 2005-09-15 12:42:16 +0000 | [diff] [blame] | 7011 | putVReg( vD_addr, binop(Iop_QAdd8Sx16, mkexpr(vA), mkexpr(vB)) ); |
| 7012 | // TODO: set VSCR[SAT] |
| 7013 | break; |
| 7014 | |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 7015 | case 0x340: // vaddshs (Add Signed Half Word Saturate, AV p139) |
| 7016 | DIP("vaddshs v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr); |
cerion | 36991ef | 2005-09-15 12:42:16 +0000 | [diff] [blame] | 7017 | putVReg( vD_addr, binop(Iop_QAdd16Sx8, mkexpr(vA), mkexpr(vB)) ); |
| 7018 | // TODO: set VSCR[SAT] |
| 7019 | break; |
| 7020 | |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 7021 | case 0x380: // vaddsws (Add Signed Word Saturate, AV p140) |
| 7022 | DIP("vaddsws v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr); |
cerion | 36991ef | 2005-09-15 12:42:16 +0000 | [diff] [blame] | 7023 | putVReg( vD_addr, binop(Iop_QAdd32Sx4, mkexpr(vA), mkexpr(vB)) ); |
| 7024 | // TODO: set VSCR[SAT] |
| 7025 | break; |
| 7026 | |
| 7027 | |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 7028 | /* Subtract */ |
cerion | 36991ef | 2005-09-15 12:42:16 +0000 | [diff] [blame] | 7029 | case 0x580: { // vsubcuw (Subtract Carryout Unsigned Word, AV p260) |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 7030 | DIP("vsubcuw v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr); |
cerion | 36991ef | 2005-09-15 12:42:16 +0000 | [diff] [blame] | 7031 | /* unsigned_ov(x-y) = (y >u x) */ |
| 7032 | putVReg( vD_addr, binop(Iop_ShrN32x4, |
| 7033 | unop(Iop_NotV128, |
| 7034 | binop(Iop_CmpGT32Ux4, mkexpr(vB), |
| 7035 | mkexpr(vA))), |
| 7036 | mkU8(31)) ); |
| 7037 | break; |
| 7038 | } |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 7039 | case 0x400: // vsububm (Subtract Unsigned Byte Modulo, AV p265) |
| 7040 | DIP("vsububm v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr); |
cerion | 36991ef | 2005-09-15 12:42:16 +0000 | [diff] [blame] | 7041 | putVReg( vD_addr, binop(Iop_Sub8x16, mkexpr(vA), mkexpr(vB)) ); |
| 7042 | break; |
| 7043 | |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 7044 | case 0x440: // vsubuhm (Subtract Unsigned Half Word Modulo, AV p267) |
| 7045 | DIP("vsubuhm v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr); |
cerion | 36991ef | 2005-09-15 12:42:16 +0000 | [diff] [blame] | 7046 | putVReg( vD_addr, binop(Iop_Sub16x8, mkexpr(vA), mkexpr(vB)) ); |
| 7047 | break; |
| 7048 | |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 7049 | case 0x480: // vsubuwm (Subtract Unsigned Word Modulo, AV p269) |
| 7050 | DIP("vsubuwm v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr); |
cerion | 36991ef | 2005-09-15 12:42:16 +0000 | [diff] [blame] | 7051 | putVReg( vD_addr, binop(Iop_Sub32x4, mkexpr(vA), mkexpr(vB)) ); |
| 7052 | break; |
| 7053 | |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 7054 | case 0x600: // vsububs (Subtract Unsigned Byte Saturate, AV p266) |
| 7055 | DIP("vsububs v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr); |
cerion | 36991ef | 2005-09-15 12:42:16 +0000 | [diff] [blame] | 7056 | putVReg( vD_addr, binop(Iop_QSub8Ux16, mkexpr(vA), mkexpr(vB)) ); |
| 7057 | // TODO: set VSCR[SAT] |
| 7058 | break; |
| 7059 | |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 7060 | case 0x640: // vsubuhs (Subtract Unsigned HWord Saturate, AV p268) |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 7061 | DIP("vsubuhs v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr); |
cerion | 36991ef | 2005-09-15 12:42:16 +0000 | [diff] [blame] | 7062 | putVReg( vD_addr, binop(Iop_QSub16Ux8, mkexpr(vA), mkexpr(vB)) ); |
| 7063 | // TODO: set VSCR[SAT] |
| 7064 | break; |
| 7065 | |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 7066 | case 0x680: // vsubuws (Subtract Unsigned Word Saturate, AV p270) |
| 7067 | DIP("vsubuws v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr); |
cerion | 36991ef | 2005-09-15 12:42:16 +0000 | [diff] [blame] | 7068 | putVReg( vD_addr, binop(Iop_QSub32Ux4, mkexpr(vA), mkexpr(vB)) ); |
| 7069 | // TODO: set VSCR[SAT] |
| 7070 | break; |
| 7071 | |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 7072 | case 0x700: // vsubsbs (Subtract Signed Byte Saturate, AV p262) |
| 7073 | DIP("vsubsbs v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr); |
cerion | 36991ef | 2005-09-15 12:42:16 +0000 | [diff] [blame] | 7074 | putVReg( vD_addr, binop(Iop_QSub8Sx16, mkexpr(vA), mkexpr(vB)) ); |
| 7075 | // TODO: set VSCR[SAT] |
| 7076 | break; |
| 7077 | |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 7078 | case 0x740: // vsubshs (Subtract Signed Half Word Saturate, AV p263) |
| 7079 | DIP("vsubshs v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr); |
cerion | 36991ef | 2005-09-15 12:42:16 +0000 | [diff] [blame] | 7080 | putVReg( vD_addr, binop(Iop_QSub16Sx8, mkexpr(vA), mkexpr(vB)) ); |
| 7081 | // TODO: set VSCR[SAT] |
| 7082 | break; |
| 7083 | |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 7084 | case 0x780: // vsubsws (Subtract Signed Word Saturate, AV p264) |
| 7085 | DIP("vsubsws v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr); |
cerion | 36991ef | 2005-09-15 12:42:16 +0000 | [diff] [blame] | 7086 | putVReg( vD_addr, binop(Iop_QSub32Sx4, mkexpr(vA), mkexpr(vB)) ); |
| 7087 | // TODO: set VSCR[SAT] |
| 7088 | break; |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 7089 | |
| 7090 | |
| 7091 | /* Maximum */ |
| 7092 | case 0x002: // vmaxub (Maximum Unsigned Byte, AV p182) |
| 7093 | DIP("vmaxub v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr); |
cerion | 36991ef | 2005-09-15 12:42:16 +0000 | [diff] [blame] | 7094 | putVReg( vD_addr, binop(Iop_Max8Ux16, mkexpr(vA), mkexpr(vB)) ); |
| 7095 | break; |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 7096 | |
| 7097 | case 0x042: // vmaxuh (Maximum Unsigned Half Word, AV p183) |
| 7098 | DIP("vmaxuh v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr); |
cerion | 36991ef | 2005-09-15 12:42:16 +0000 | [diff] [blame] | 7099 | putVReg( vD_addr, binop(Iop_Max16Ux8, mkexpr(vA), mkexpr(vB)) ); |
| 7100 | break; |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 7101 | |
| 7102 | case 0x082: // vmaxuw (Maximum Unsigned Word, AV p184) |
| 7103 | DIP("vmaxuw v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr); |
cerion | 36991ef | 2005-09-15 12:42:16 +0000 | [diff] [blame] | 7104 | putVReg( vD_addr, binop(Iop_Max32Ux4, mkexpr(vA), mkexpr(vB)) ); |
| 7105 | break; |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 7106 | |
| 7107 | case 0x102: // vmaxsb (Maximum Signed Byte, AV p179) |
| 7108 | DIP("vmaxsb v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr); |
cerion | 36991ef | 2005-09-15 12:42:16 +0000 | [diff] [blame] | 7109 | putVReg( vD_addr, binop(Iop_Max8Sx16, mkexpr(vA), mkexpr(vB)) ); |
| 7110 | break; |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 7111 | |
| 7112 | case 0x142: // vmaxsh (Maximum Signed Half Word, AV p180) |
| 7113 | DIP("vmaxsh v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr); |
cerion | 36991ef | 2005-09-15 12:42:16 +0000 | [diff] [blame] | 7114 | putVReg( vD_addr, binop(Iop_Max16Sx8, mkexpr(vA), mkexpr(vB)) ); |
| 7115 | break; |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 7116 | |
| 7117 | case 0x182: // vmaxsw (Maximum Signed Word, AV p181) |
| 7118 | DIP("vmaxsw v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr); |
cerion | 36991ef | 2005-09-15 12:42:16 +0000 | [diff] [blame] | 7119 | putVReg( vD_addr, binop(Iop_Max32Sx4, mkexpr(vA), mkexpr(vB)) ); |
| 7120 | break; |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 7121 | |
| 7122 | |
| 7123 | /* Minimum */ |
| 7124 | case 0x202: // vminub (Minimum Unsigned Byte, AV p191) |
| 7125 | DIP("vminub v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr); |
cerion | 36991ef | 2005-09-15 12:42:16 +0000 | [diff] [blame] | 7126 | putVReg( vD_addr, binop(Iop_Min8Ux16, mkexpr(vA), mkexpr(vB)) ); |
| 7127 | break; |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 7128 | |
| 7129 | case 0x242: // vminuh (Minimum Unsigned Half Word, AV p192) |
| 7130 | DIP("vminuh v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr); |
cerion | 36991ef | 2005-09-15 12:42:16 +0000 | [diff] [blame] | 7131 | putVReg( vD_addr, binop(Iop_Min16Ux8, mkexpr(vA), mkexpr(vB)) ); |
| 7132 | break; |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 7133 | |
| 7134 | case 0x282: // vminuw (Minimum Unsigned Word, AV p193) |
| 7135 | DIP("vminuw v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr); |
cerion | 36991ef | 2005-09-15 12:42:16 +0000 | [diff] [blame] | 7136 | putVReg( vD_addr, binop(Iop_Min32Ux4, mkexpr(vA), mkexpr(vB)) ); |
| 7137 | break; |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 7138 | |
| 7139 | case 0x302: // vminsb (Minimum Signed Byte, AV p188) |
| 7140 | DIP("vminsb v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr); |
cerion | 36991ef | 2005-09-15 12:42:16 +0000 | [diff] [blame] | 7141 | putVReg( vD_addr, binop(Iop_Min8Sx16, mkexpr(vA), mkexpr(vB)) ); |
| 7142 | break; |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 7143 | |
| 7144 | case 0x342: // vminsh (Minimum Signed Half Word, AV p189) |
| 7145 | DIP("vminsh v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr); |
cerion | 36991ef | 2005-09-15 12:42:16 +0000 | [diff] [blame] | 7146 | putVReg( vD_addr, binop(Iop_Min16Sx8, mkexpr(vA), mkexpr(vB)) ); |
| 7147 | break; |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 7148 | |
| 7149 | case 0x382: // vminsw (Minimum Signed Word, AV p190) |
| 7150 | DIP("vminsw v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr); |
cerion | 36991ef | 2005-09-15 12:42:16 +0000 | [diff] [blame] | 7151 | putVReg( vD_addr, binop(Iop_Min32Sx4, mkexpr(vA), mkexpr(vB)) ); |
| 7152 | break; |
| 7153 | |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 7154 | |
| 7155 | /* Average */ |
| 7156 | case 0x402: // vavgub (Average Unsigned Byte, AV p152) |
| 7157 | DIP("vavgub v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr); |
cerion | 36991ef | 2005-09-15 12:42:16 +0000 | [diff] [blame] | 7158 | putVReg( vD_addr, binop(Iop_Avg8Ux16, mkexpr(vA), mkexpr(vB)) ); |
| 7159 | break; |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 7160 | |
| 7161 | case 0x442: // vavguh (Average Unsigned Half Word, AV p153) |
| 7162 | DIP("vavguh v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr); |
cerion | 36991ef | 2005-09-15 12:42:16 +0000 | [diff] [blame] | 7163 | putVReg( vD_addr, binop(Iop_Avg16Ux8, mkexpr(vA), mkexpr(vB)) ); |
| 7164 | break; |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 7165 | |
| 7166 | case 0x482: // vavguw (Average Unsigned Word, AV p154) |
| 7167 | DIP("vavguw v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr); |
cerion | 36991ef | 2005-09-15 12:42:16 +0000 | [diff] [blame] | 7168 | putVReg( vD_addr, binop(Iop_Avg32Ux4, mkexpr(vA), mkexpr(vB)) ); |
| 7169 | break; |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 7170 | |
| 7171 | case 0x502: // vavgsb (Average Signed Byte, AV p149) |
| 7172 | DIP("vavgsb v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr); |
cerion | 36991ef | 2005-09-15 12:42:16 +0000 | [diff] [blame] | 7173 | putVReg( vD_addr, binop(Iop_Avg8Sx16, mkexpr(vA), mkexpr(vB)) ); |
| 7174 | break; |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 7175 | |
| 7176 | case 0x542: // vavgsh (Average Signed Half Word, AV p150) |
| 7177 | DIP("vavgsh v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr); |
cerion | 36991ef | 2005-09-15 12:42:16 +0000 | [diff] [blame] | 7178 | putVReg( vD_addr, binop(Iop_Avg16Sx8, mkexpr(vA), mkexpr(vB)) ); |
| 7179 | break; |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 7180 | |
| 7181 | case 0x582: // vavgsw (Average Signed Word, AV p151) |
| 7182 | DIP("vavgsw v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr); |
cerion | 36991ef | 2005-09-15 12:42:16 +0000 | [diff] [blame] | 7183 | putVReg( vD_addr, binop(Iop_Avg32Sx4, mkexpr(vA), mkexpr(vB)) ); |
| 7184 | break; |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 7185 | |
| 7186 | |
| 7187 | /* Multiply */ |
| 7188 | case 0x008: // vmuloub (Multiply Odd Unsigned Byte, AV p213) |
| 7189 | DIP("vmuloub v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr); |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 7190 | putVReg( vD_addr, |
| 7191 | binop(Iop_MullEven8Ux16, mkexpr(vA), mkexpr(vB))); |
cerion | 36991ef | 2005-09-15 12:42:16 +0000 | [diff] [blame] | 7192 | break; |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 7193 | |
| 7194 | case 0x048: // vmulouh (Multiply Odd Unsigned Half Word, AV p214) |
| 7195 | DIP("vmulouh v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr); |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 7196 | putVReg( vD_addr, |
| 7197 | binop(Iop_MullEven16Ux8, mkexpr(vA), mkexpr(vB))); |
cerion | 36991ef | 2005-09-15 12:42:16 +0000 | [diff] [blame] | 7198 | break; |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 7199 | |
| 7200 | case 0x108: // vmulosb (Multiply Odd Signed Byte, AV p211) |
| 7201 | DIP("vmulosb v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr); |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 7202 | putVReg( vD_addr, |
| 7203 | binop(Iop_MullEven8Sx16, mkexpr(vA), mkexpr(vB))); |
cerion | 36991ef | 2005-09-15 12:42:16 +0000 | [diff] [blame] | 7204 | break; |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 7205 | |
| 7206 | case 0x148: // vmulosh (Multiply Odd Signed Half Word, AV p212) |
| 7207 | DIP("vmulosh v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr); |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 7208 | putVReg( vD_addr, |
| 7209 | binop(Iop_MullEven16Sx8, mkexpr(vA), mkexpr(vB))); |
cerion | 36991ef | 2005-09-15 12:42:16 +0000 | [diff] [blame] | 7210 | break; |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 7211 | |
| 7212 | case 0x208: // vmuleub (Multiply Even Unsigned Byte, AV p209) |
| 7213 | DIP("vmuleub v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr); |
cerion | 24d06f1 | 2005-11-09 21:34:20 +0000 | [diff] [blame] | 7214 | putVReg( vD_addr, MK_Iop_MullOdd8Ux16( mkexpr(vA), mkexpr(vB) )); |
cerion | 36991ef | 2005-09-15 12:42:16 +0000 | [diff] [blame] | 7215 | break; |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 7216 | |
| 7217 | case 0x248: // vmuleuh (Multiply Even Unsigned Half Word, AV p210) |
| 7218 | DIP("vmuleuh v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr); |
cerion | 24d06f1 | 2005-11-09 21:34:20 +0000 | [diff] [blame] | 7219 | putVReg( vD_addr, MK_Iop_MullOdd16Ux8( mkexpr(vA), mkexpr(vB) )); |
cerion | 36991ef | 2005-09-15 12:42:16 +0000 | [diff] [blame] | 7220 | break; |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 7221 | |
| 7222 | case 0x308: // vmulesb (Multiply Even Signed Byte, AV p207) |
| 7223 | DIP("vmulesb v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr); |
cerion | 24d06f1 | 2005-11-09 21:34:20 +0000 | [diff] [blame] | 7224 | putVReg( vD_addr, MK_Iop_MullOdd8Sx16( mkexpr(vA), mkexpr(vB) )); |
cerion | 36991ef | 2005-09-15 12:42:16 +0000 | [diff] [blame] | 7225 | break; |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 7226 | |
| 7227 | case 0x348: // vmulesh (Multiply Even Signed Half Word, AV p208) |
| 7228 | DIP("vmulesh v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr); |
cerion | 24d06f1 | 2005-11-09 21:34:20 +0000 | [diff] [blame] | 7229 | putVReg( vD_addr, MK_Iop_MullOdd16Sx8( mkexpr(vA), mkexpr(vB) )); |
cerion | 36991ef | 2005-09-15 12:42:16 +0000 | [diff] [blame] | 7230 | break; |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 7231 | |
| 7232 | |
| 7233 | /* Sum Across Partial */ |
cerion | 4a49b03 | 2005-11-08 16:23:07 +0000 | [diff] [blame] | 7234 | case 0x608: { // vsum4ubs (Sum Partial (1/4) UB Saturate, AV p275) |
| 7235 | IRTemp aEE, aEO, aOE, aOO; |
| 7236 | aEE = aEO = aOE = aOO = IRTemp_INVALID; |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 7237 | DIP("vsum4ubs v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr); |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 7238 | |
cerion | 4a49b03 | 2005-11-08 16:23:07 +0000 | [diff] [blame] | 7239 | /* vA: V128_8Ux16 -> 4 x V128_32Ux4, sign-extended */ |
| 7240 | expand8Ux16( mkexpr(vA), &aEvn, &aOdd ); // (15,13...),(14,12...) |
| 7241 | expand16Ux8( mkexpr(aEvn), &aEE, &aEO ); // (15,11...),(13, 9...) |
| 7242 | expand16Ux8( mkexpr(aOdd), &aOE, &aOO ); // (14,10...),(12, 8...) |
| 7243 | |
| 7244 | /* break V128 to 4xI32's, zero-extending to I64's */ |
| 7245 | breakV128to4x64U( mkexpr(aEE), &a15, &a11, &a7, &a3 ); |
| 7246 | breakV128to4x64U( mkexpr(aOE), &a14, &a10, &a6, &a2 ); |
| 7247 | breakV128to4x64U( mkexpr(aEO), &a13, &a9, &a5, &a1 ); |
| 7248 | breakV128to4x64U( mkexpr(aOO), &a12, &a8, &a4, &a0 ); |
| 7249 | breakV128to4x64U( mkexpr(vB), &b3, &b2, &b1, &b0 ); |
| 7250 | |
| 7251 | /* add lanes */ |
| 7252 | assign( z3, binop(Iop_Add64, mkexpr(b3), |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 7253 | binop(Iop_Add64, |
| 7254 | binop(Iop_Add64, mkexpr(a15), mkexpr(a14)), |
| 7255 | binop(Iop_Add64, mkexpr(a13), mkexpr(a12)))) ); |
cerion | 4a49b03 | 2005-11-08 16:23:07 +0000 | [diff] [blame] | 7256 | assign( z2, binop(Iop_Add64, mkexpr(b2), |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 7257 | binop(Iop_Add64, |
| 7258 | binop(Iop_Add64, mkexpr(a11), mkexpr(a10)), |
| 7259 | binop(Iop_Add64, mkexpr(a9), mkexpr(a8)))) ); |
cerion | 4a49b03 | 2005-11-08 16:23:07 +0000 | [diff] [blame] | 7260 | assign( z1, binop(Iop_Add64, mkexpr(b1), |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 7261 | binop(Iop_Add64, |
| 7262 | binop(Iop_Add64, mkexpr(a7), mkexpr(a6)), |
| 7263 | binop(Iop_Add64, mkexpr(a5), mkexpr(a4)))) ); |
cerion | 4a49b03 | 2005-11-08 16:23:07 +0000 | [diff] [blame] | 7264 | assign( z0, binop(Iop_Add64, mkexpr(b0), |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 7265 | binop(Iop_Add64, |
| 7266 | binop(Iop_Add64, mkexpr(a3), mkexpr(a2)), |
| 7267 | binop(Iop_Add64, mkexpr(a1), mkexpr(a0)))) ); |
cerion | 4a49b03 | 2005-11-08 16:23:07 +0000 | [diff] [blame] | 7268 | |
| 7269 | /* saturate-narrow to 32bit, and combine to V128 */ |
| 7270 | putVReg( vD_addr, mkV128from4x64U( mkexpr(z3), mkexpr(z2), |
| 7271 | mkexpr(z1), mkexpr(z0)) ); |
| 7272 | break; |
| 7273 | } |
| 7274 | case 0x708: { // vsum4sbs (Sum Partial (1/4) SB Saturate, AV p273) |
| 7275 | IRTemp aEE, aEO, aOE, aOO; |
| 7276 | aEE = aEO = aOE = aOO = IRTemp_INVALID; |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 7277 | DIP("vsum4sbs v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr); |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 7278 | |
cerion | 4a49b03 | 2005-11-08 16:23:07 +0000 | [diff] [blame] | 7279 | /* vA: V128_8Sx16 -> 4 x V128_32Sx4, sign-extended */ |
| 7280 | expand8Sx16( mkexpr(vA), &aEvn, &aOdd ); // (15,13...),(14,12...) |
| 7281 | expand16Sx8( mkexpr(aEvn), &aEE, &aEO ); // (15,11...),(13, 9...) |
| 7282 | expand16Sx8( mkexpr(aOdd), &aOE, &aOO ); // (14,10...),(12, 8...) |
| 7283 | |
| 7284 | /* break V128 to 4xI32's, sign-extending to I64's */ |
| 7285 | breakV128to4x64S( mkexpr(aEE), &a15, &a11, &a7, &a3 ); |
| 7286 | breakV128to4x64S( mkexpr(aOE), &a14, &a10, &a6, &a2 ); |
| 7287 | breakV128to4x64S( mkexpr(aEO), &a13, &a9, &a5, &a1 ); |
| 7288 | breakV128to4x64S( mkexpr(aOO), &a12, &a8, &a4, &a0 ); |
| 7289 | breakV128to4x64S( mkexpr(vB), &b3, &b2, &b1, &b0 ); |
| 7290 | |
| 7291 | /* add lanes */ |
| 7292 | assign( z3, binop(Iop_Add64, mkexpr(b3), |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 7293 | binop(Iop_Add64, |
| 7294 | binop(Iop_Add64, mkexpr(a15), mkexpr(a14)), |
| 7295 | binop(Iop_Add64, mkexpr(a13), mkexpr(a12)))) ); |
cerion | 4a49b03 | 2005-11-08 16:23:07 +0000 | [diff] [blame] | 7296 | assign( z2, binop(Iop_Add64, mkexpr(b2), |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 7297 | binop(Iop_Add64, |
| 7298 | binop(Iop_Add64, mkexpr(a11), mkexpr(a10)), |
| 7299 | binop(Iop_Add64, mkexpr(a9), mkexpr(a8)))) ); |
cerion | 4a49b03 | 2005-11-08 16:23:07 +0000 | [diff] [blame] | 7300 | assign( z1, binop(Iop_Add64, mkexpr(b1), |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 7301 | binop(Iop_Add64, |
| 7302 | binop(Iop_Add64, mkexpr(a7), mkexpr(a6)), |
| 7303 | binop(Iop_Add64, mkexpr(a5), mkexpr(a4)))) ); |
cerion | 4a49b03 | 2005-11-08 16:23:07 +0000 | [diff] [blame] | 7304 | assign( z0, binop(Iop_Add64, mkexpr(b0), |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 7305 | binop(Iop_Add64, |
| 7306 | binop(Iop_Add64, mkexpr(a3), mkexpr(a2)), |
| 7307 | binop(Iop_Add64, mkexpr(a1), mkexpr(a0)))) ); |
cerion | 4a49b03 | 2005-11-08 16:23:07 +0000 | [diff] [blame] | 7308 | |
| 7309 | /* saturate-narrow to 32bit, and combine to V128 */ |
| 7310 | putVReg( vD_addr, mkV128from4x64S( mkexpr(z3), mkexpr(z2), |
| 7311 | mkexpr(z1), mkexpr(z0)) ); |
| 7312 | break; |
| 7313 | } |
| 7314 | case 0x648: { // vsum4shs (Sum Partial (1/4) SHW Saturate, AV p274) |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 7315 | DIP("vsum4shs v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr); |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 7316 | |
cerion | 4a49b03 | 2005-11-08 16:23:07 +0000 | [diff] [blame] | 7317 | /* vA: V128_16Sx8 -> 2 x V128_32Sx4, sign-extended */ |
| 7318 | expand16Sx8( mkexpr(vA), &aEvn, &aOdd ); // (7,5...),(6,4...) |
| 7319 | |
| 7320 | /* break V128 to 4xI32's, sign-extending to I64's */ |
| 7321 | breakV128to4x64S( mkexpr(aEvn), &a7, &a5, &a3, &a1 ); |
| 7322 | breakV128to4x64S( mkexpr(aOdd), &a6, &a4, &a2, &a0 ); |
| 7323 | breakV128to4x64S( mkexpr(vB), &b3, &b2, &b1, &b0 ); |
| 7324 | |
| 7325 | /* add lanes */ |
| 7326 | assign( z3, binop(Iop_Add64, mkexpr(b3), |
| 7327 | binop(Iop_Add64, mkexpr(a7), mkexpr(a6)))); |
| 7328 | assign( z2, binop(Iop_Add64, mkexpr(b2), |
| 7329 | binop(Iop_Add64, mkexpr(a5), mkexpr(a4)))); |
| 7330 | assign( z1, binop(Iop_Add64, mkexpr(b1), |
| 7331 | binop(Iop_Add64, mkexpr(a3), mkexpr(a2)))); |
| 7332 | assign( z0, binop(Iop_Add64, mkexpr(b0), |
| 7333 | binop(Iop_Add64, mkexpr(a1), mkexpr(a0)))); |
| 7334 | |
| 7335 | /* saturate-narrow to 32bit, and combine to V128 */ |
| 7336 | putVReg( vD_addr, mkV128from4x64S( mkexpr(z3), mkexpr(z2), |
| 7337 | mkexpr(z1), mkexpr(z0)) ); |
| 7338 | break; |
| 7339 | } |
| 7340 | case 0x688: { // vsum2sws (Sum Partial (1/2) SW Saturate, AV p272) |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 7341 | DIP("vsum2sws v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr); |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 7342 | |
cerion | 4a49b03 | 2005-11-08 16:23:07 +0000 | [diff] [blame] | 7343 | /* break V128 to 4xI32's, sign-extending to I64's */ |
| 7344 | breakV128to4x64S( mkexpr(vA), &a3, &a2, &a1, &a0 ); |
| 7345 | breakV128to4x64S( mkexpr(vB), &b3, &b2, &b1, &b0 ); |
| 7346 | |
| 7347 | /* add lanes */ |
| 7348 | assign( z2, binop(Iop_Add64, mkexpr(b2), |
| 7349 | binop(Iop_Add64, mkexpr(a3), mkexpr(a2))) ); |
| 7350 | assign( z0, binop(Iop_Add64, mkexpr(b0), |
| 7351 | binop(Iop_Add64, mkexpr(a1), mkexpr(a0))) ); |
| 7352 | |
| 7353 | /* saturate-narrow to 32bit, and combine to V128 */ |
| 7354 | putVReg( vD_addr, mkV128from4x64S( mkU64(0), mkexpr(z2), |
| 7355 | mkU64(0), mkexpr(z0)) ); |
| 7356 | break; |
| 7357 | } |
| 7358 | case 0x788: { // vsumsws (Sum SW Saturate, AV p271) |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 7359 | DIP("vsumsws v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr); |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 7360 | |
cerion | 4a49b03 | 2005-11-08 16:23:07 +0000 | [diff] [blame] | 7361 | /* break V128 to 4xI32's, sign-extending to I64's */ |
| 7362 | breakV128to4x64S( mkexpr(vA), &a3, &a2, &a1, &a0 ); |
| 7363 | breakV128to4x64S( mkexpr(vB), &b3, &b2, &b1, &b0 ); |
| 7364 | |
| 7365 | /* add lanes */ |
| 7366 | assign( z0, binop(Iop_Add64, mkexpr(b0), |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 7367 | binop(Iop_Add64, |
| 7368 | binop(Iop_Add64, mkexpr(a3), mkexpr(a2)), |
| 7369 | binop(Iop_Add64, mkexpr(a1), mkexpr(a0)))) ); |
cerion | 4a49b03 | 2005-11-08 16:23:07 +0000 | [diff] [blame] | 7370 | |
| 7371 | /* saturate-narrow to 32bit, and combine to V128 */ |
| 7372 | putVReg( vD_addr, mkV128from4x64S( mkU64(0), mkU64(0), |
| 7373 | mkU64(0), mkexpr(z0)) ); |
| 7374 | break; |
| 7375 | } |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 7376 | default: |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 7377 | vex_printf("dis_av_arith(ppc)(opc2=0x%x)\n", opc2); |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 7378 | return False; |
| 7379 | } |
| 7380 | return True; |
| 7381 | } |
| 7382 | |
| 7383 | /* |
| 7384 | AltiVec Logic Instructions |
| 7385 | */ |
| 7386 | static Bool dis_av_logic ( UInt theInstr ) |
| 7387 | { |
cerion | 76de5cf | 2005-11-18 18:25:12 +0000 | [diff] [blame] | 7388 | /* VX-Form */ |
| 7389 | UChar opc1 = ifieldOPC(theInstr); |
| 7390 | UChar vD_addr = ifieldRegDS(theInstr); |
| 7391 | UChar vA_addr = ifieldRegA(theInstr); |
| 7392 | UChar vB_addr = ifieldRegB(theInstr); |
| 7393 | UInt opc2 = IFIELD( theInstr, 0, 11 ); |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 7394 | |
cerion | 225a034 | 2005-09-12 20:49:09 +0000 | [diff] [blame] | 7395 | IRTemp vA = newTemp(Ity_V128); |
| 7396 | IRTemp vB = newTemp(Ity_V128); |
| 7397 | assign( vA, getVReg(vA_addr)); |
| 7398 | assign( vB, getVReg(vB_addr)); |
| 7399 | |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 7400 | if (opc1 != 0x4) { |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 7401 | vex_printf("dis_av_logic(ppc)(opc1 != 0x4)\n"); |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 7402 | return False; |
| 7403 | } |
| 7404 | |
| 7405 | switch (opc2) { |
| 7406 | case 0x404: // vand (And, AV p147) |
| 7407 | DIP("vand v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr); |
cerion | 225a034 | 2005-09-12 20:49:09 +0000 | [diff] [blame] | 7408 | putVReg( vD_addr, binop(Iop_AndV128, mkexpr(vA), mkexpr(vB)) ); |
| 7409 | break; |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 7410 | |
| 7411 | case 0x444: // vandc (And, AV p148) |
| 7412 | DIP("vandc v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr); |
cerion | 6e7a0ea | 2005-09-13 13:34:09 +0000 | [diff] [blame] | 7413 | putVReg( vD_addr, binop(Iop_AndV128, mkexpr(vA), |
cerion | 76de5cf | 2005-11-18 18:25:12 +0000 | [diff] [blame] | 7414 | unop(Iop_NotV128, mkexpr(vB))) ); |
cerion | 6e7a0ea | 2005-09-13 13:34:09 +0000 | [diff] [blame] | 7415 | break; |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 7416 | |
| 7417 | case 0x484: // vor (Or, AV p217) |
| 7418 | DIP("vor v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr); |
cerion | 225a034 | 2005-09-12 20:49:09 +0000 | [diff] [blame] | 7419 | putVReg( vD_addr, binop(Iop_OrV128, mkexpr(vA), mkexpr(vB)) ); |
| 7420 | break; |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 7421 | |
| 7422 | case 0x4C4: // vxor (Xor, AV p282) |
| 7423 | DIP("vxor v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr); |
cerion | 225a034 | 2005-09-12 20:49:09 +0000 | [diff] [blame] | 7424 | putVReg( vD_addr, binop(Iop_XorV128, mkexpr(vA), mkexpr(vB)) ); |
| 7425 | break; |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 7426 | |
| 7427 | case 0x504: // vnor (Nor, AV p216) |
| 7428 | DIP("vnor v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr); |
cerion | 6e7a0ea | 2005-09-13 13:34:09 +0000 | [diff] [blame] | 7429 | putVReg( vD_addr, |
| 7430 | unop(Iop_NotV128, binop(Iop_OrV128, mkexpr(vA), mkexpr(vB))) ); |
| 7431 | break; |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 7432 | |
| 7433 | default: |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 7434 | vex_printf("dis_av_logic(ppc)(opc2=0x%x)\n", opc2); |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 7435 | return False; |
| 7436 | } |
| 7437 | return True; |
| 7438 | } |
| 7439 | |
| 7440 | /* |
| 7441 | AltiVec Compare Instructions |
| 7442 | */ |
| 7443 | static Bool dis_av_cmp ( UInt theInstr ) |
| 7444 | { |
cerion | 76de5cf | 2005-11-18 18:25:12 +0000 | [diff] [blame] | 7445 | /* VXR-Form */ |
| 7446 | UChar opc1 = ifieldOPC(theInstr); |
| 7447 | UChar vD_addr = ifieldRegDS(theInstr); |
| 7448 | UChar vA_addr = ifieldRegA(theInstr); |
| 7449 | UChar vB_addr = ifieldRegB(theInstr); |
| 7450 | UChar flag_rC = ifieldBIT10(theInstr); |
| 7451 | UInt opc2 = IFIELD( theInstr, 0, 10 ); |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 7452 | |
cerion | 0c43922 | 2005-09-15 14:22:58 +0000 | [diff] [blame] | 7453 | IRTemp vA = newTemp(Ity_V128); |
| 7454 | IRTemp vB = newTemp(Ity_V128); |
| 7455 | IRTemp vD = newTemp(Ity_V128); |
| 7456 | assign( vA, getVReg(vA_addr)); |
| 7457 | assign( vB, getVReg(vB_addr)); |
| 7458 | |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 7459 | if (opc1 != 0x4) { |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 7460 | vex_printf("dis_av_cmp(ppc)(instr)\n"); |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 7461 | return False; |
| 7462 | } |
| 7463 | |
| 7464 | switch (opc2) { |
| 7465 | case 0x006: // vcmpequb (Compare Equal-to Unsigned B, AV p160) |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 7466 | DIP("vcmpequb%s v%d,v%d,v%d\n", (flag_rC ? ".":""), |
| 7467 | vD_addr, vA_addr, vB_addr); |
cerion | 0c43922 | 2005-09-15 14:22:58 +0000 | [diff] [blame] | 7468 | assign( vD, binop(Iop_CmpEQ8x16, mkexpr(vA), mkexpr(vB)) ); |
| 7469 | break; |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 7470 | |
| 7471 | case 0x046: // vcmpequh (Compare Equal-to Unsigned HW, AV p161) |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 7472 | DIP("vcmpequh%s v%d,v%d,v%d\n", (flag_rC ? ".":""), |
| 7473 | vD_addr, vA_addr, vB_addr); |
cerion | 0c43922 | 2005-09-15 14:22:58 +0000 | [diff] [blame] | 7474 | assign( vD, binop(Iop_CmpEQ16x8, mkexpr(vA), mkexpr(vB)) ); |
| 7475 | break; |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 7476 | |
| 7477 | case 0x086: // vcmpequw (Compare Equal-to Unsigned W, AV p162) |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 7478 | DIP("vcmpequw%s v%d,v%d,v%d\n", (flag_rC ? ".":""), |
| 7479 | vD_addr, vA_addr, vB_addr); |
cerion | 0c43922 | 2005-09-15 14:22:58 +0000 | [diff] [blame] | 7480 | assign( vD, binop(Iop_CmpEQ32x4, mkexpr(vA), mkexpr(vB)) ); |
| 7481 | break; |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 7482 | |
| 7483 | case 0x206: // vcmpgtub (Compare Greater-than Unsigned B, AV p168) |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 7484 | DIP("vcmpgtub%s v%d,v%d,v%d\n", (flag_rC ? ".":""), |
| 7485 | vD_addr, vA_addr, vB_addr); |
cerion | 0c43922 | 2005-09-15 14:22:58 +0000 | [diff] [blame] | 7486 | assign( vD, binop(Iop_CmpGT8Ux16, mkexpr(vA), mkexpr(vB)) ); |
| 7487 | break; |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 7488 | |
| 7489 | case 0x246: // vcmpgtuh (Compare Greater-than Unsigned HW, AV p169) |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 7490 | DIP("vcmpgtuh%s v%d,v%d,v%d\n", (flag_rC ? ".":""), |
| 7491 | vD_addr, vA_addr, vB_addr); |
cerion | 0c43922 | 2005-09-15 14:22:58 +0000 | [diff] [blame] | 7492 | assign( vD, binop(Iop_CmpGT16Ux8, mkexpr(vA), mkexpr(vB)) ); |
| 7493 | break; |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 7494 | |
| 7495 | case 0x286: // vcmpgtuw (Compare Greater-than Unsigned W, AV p170) |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 7496 | DIP("vcmpgtuw%s v%d,v%d,v%d\n", (flag_rC ? ".":""), |
| 7497 | vD_addr, vA_addr, vB_addr); |
cerion | 0c43922 | 2005-09-15 14:22:58 +0000 | [diff] [blame] | 7498 | assign( vD, binop(Iop_CmpGT32Ux4, mkexpr(vA), mkexpr(vB)) ); |
| 7499 | break; |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 7500 | |
| 7501 | case 0x306: // vcmpgtsb (Compare Greater-than Signed B, AV p165) |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 7502 | DIP("vcmpgtsb%s v%d,v%d,v%d\n", (flag_rC ? ".":""), |
| 7503 | vD_addr, vA_addr, vB_addr); |
cerion | 0c43922 | 2005-09-15 14:22:58 +0000 | [diff] [blame] | 7504 | assign( vD, binop(Iop_CmpGT8Sx16, mkexpr(vA), mkexpr(vB)) ); |
| 7505 | break; |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 7506 | |
| 7507 | case 0x346: // vcmpgtsh (Compare Greater-than Signed HW, AV p166) |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 7508 | DIP("vcmpgtsh%s v%d,v%d,v%d\n", (flag_rC ? ".":""), |
| 7509 | vD_addr, vA_addr, vB_addr); |
cerion | 0c43922 | 2005-09-15 14:22:58 +0000 | [diff] [blame] | 7510 | assign( vD, binop(Iop_CmpGT16Sx8, mkexpr(vA), mkexpr(vB)) ); |
| 7511 | break; |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 7512 | |
| 7513 | case 0x386: // vcmpgtsw (Compare Greater-than Signed W, AV p167) |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 7514 | DIP("vcmpgtsw%s v%d,v%d,v%d\n", (flag_rC ? ".":""), |
| 7515 | vD_addr, vA_addr, vB_addr); |
cerion | 0c43922 | 2005-09-15 14:22:58 +0000 | [diff] [blame] | 7516 | assign( vD, binop(Iop_CmpGT32Sx4, mkexpr(vA), mkexpr(vB)) ); |
| 7517 | break; |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 7518 | |
| 7519 | default: |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 7520 | vex_printf("dis_av_cmp(ppc)(opc2)\n"); |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 7521 | return False; |
| 7522 | } |
cerion | 0c43922 | 2005-09-15 14:22:58 +0000 | [diff] [blame] | 7523 | |
| 7524 | putVReg( vD_addr, mkexpr(vD) ); |
| 7525 | |
cerion | 76de5cf | 2005-11-18 18:25:12 +0000 | [diff] [blame] | 7526 | if (flag_rC) { |
cerion | 8ea0d3e | 2005-11-14 00:44:47 +0000 | [diff] [blame] | 7527 | set_AV_CR6( mkexpr(vD), True ); |
cerion | 0c43922 | 2005-09-15 14:22:58 +0000 | [diff] [blame] | 7528 | } |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 7529 | return True; |
| 7530 | } |
| 7531 | |
| 7532 | /* |
| 7533 | AltiVec Multiply-Sum Instructions |
| 7534 | */ |
| 7535 | static Bool dis_av_multarith ( UInt theInstr ) |
| 7536 | { |
cerion | 76de5cf | 2005-11-18 18:25:12 +0000 | [diff] [blame] | 7537 | /* VA-Form */ |
| 7538 | UChar opc1 = ifieldOPC(theInstr); |
| 7539 | UChar vD_addr = ifieldRegDS(theInstr); |
| 7540 | UChar vA_addr = ifieldRegA(theInstr); |
| 7541 | UChar vB_addr = ifieldRegB(theInstr); |
| 7542 | UChar vC_addr = ifieldRegC(theInstr); |
| 7543 | UChar opc2 = toUChar( IFIELD( theInstr, 0, 6 ) ); |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 7544 | |
cerion | 4a49b03 | 2005-11-08 16:23:07 +0000 | [diff] [blame] | 7545 | IRTemp vA = newTemp(Ity_V128); |
| 7546 | IRTemp vB = newTemp(Ity_V128); |
| 7547 | IRTemp vC = newTemp(Ity_V128); |
sewardj | 197bd17 | 2005-10-12 11:34:33 +0000 | [diff] [blame] | 7548 | IRTemp zeros = newTemp(Ity_V128); |
cerion | 4a49b03 | 2005-11-08 16:23:07 +0000 | [diff] [blame] | 7549 | IRTemp aLo = newTemp(Ity_V128); |
| 7550 | IRTemp bLo = newTemp(Ity_V128); |
| 7551 | IRTemp cLo = newTemp(Ity_V128); |
| 7552 | IRTemp zLo = newTemp(Ity_V128); |
| 7553 | IRTemp aHi = newTemp(Ity_V128); |
| 7554 | IRTemp bHi = newTemp(Ity_V128); |
| 7555 | IRTemp cHi = newTemp(Ity_V128); |
| 7556 | IRTemp zHi = newTemp(Ity_V128); |
| 7557 | IRTemp abEvn = newTemp(Ity_V128); |
| 7558 | IRTemp abOdd = newTemp(Ity_V128); |
| 7559 | IRTemp z3 = newTemp(Ity_I64); |
| 7560 | IRTemp z2 = newTemp(Ity_I64); |
| 7561 | IRTemp z1 = newTemp(Ity_I64); |
| 7562 | IRTemp z0 = newTemp(Ity_I64); |
| 7563 | IRTemp ab7, ab6, ab5, ab4, ab3, ab2, ab1, ab0; |
| 7564 | IRTemp c3, c2, c1, c0; |
| 7565 | |
| 7566 | ab7 = ab6 = ab5 = ab4 = ab3 = ab2 = ab1 = ab0 = IRTemp_INVALID; |
| 7567 | c3 = c2 = c1 = c0 = IRTemp_INVALID; |
| 7568 | |
cerion | 6f1cc0f | 2005-09-16 16:02:11 +0000 | [diff] [blame] | 7569 | assign( vA, getVReg(vA_addr)); |
| 7570 | assign( vB, getVReg(vB_addr)); |
| 7571 | assign( vC, getVReg(vC_addr)); |
cerion | 4a49b03 | 2005-11-08 16:23:07 +0000 | [diff] [blame] | 7572 | assign( zeros, unop(Iop_Dup32x4, mkU32(0)) ); |
cerion | 6f1cc0f | 2005-09-16 16:02:11 +0000 | [diff] [blame] | 7573 | |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 7574 | if (opc1 != 0x4) { |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 7575 | vex_printf("dis_av_multarith(ppc)(instr)\n"); |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 7576 | return False; |
| 7577 | } |
| 7578 | |
| 7579 | switch (opc2) { |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 7580 | /* Multiply-Add */ |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 7581 | case 0x20: { // vmhaddshs (Mult Hi, Add Signed HW Saturate, AV p185) |
cerion | 6f1cc0f | 2005-09-16 16:02:11 +0000 | [diff] [blame] | 7582 | IRTemp cSigns = newTemp(Ity_V128); |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 7583 | DIP("vmhaddshs v%d,v%d,v%d,v%d\n", |
| 7584 | vD_addr, vA_addr, vB_addr, vC_addr); |
| 7585 | assign(cSigns, binop(Iop_CmpGT16Sx8, mkexpr(zeros), mkexpr(vC))); |
| 7586 | assign(aLo, binop(Iop_InterleaveLO16x8, mkexpr(zeros), mkexpr(vA))); |
| 7587 | assign(bLo, binop(Iop_InterleaveLO16x8, mkexpr(zeros), mkexpr(vB))); |
| 7588 | assign(cLo, binop(Iop_InterleaveLO16x8, mkexpr(cSigns),mkexpr(vC))); |
| 7589 | assign(aHi, binop(Iop_InterleaveHI16x8, mkexpr(zeros), mkexpr(vA))); |
| 7590 | assign(bHi, binop(Iop_InterleaveHI16x8, mkexpr(zeros), mkexpr(vB))); |
| 7591 | assign(cHi, binop(Iop_InterleaveHI16x8, mkexpr(cSigns),mkexpr(vC))); |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 7592 | |
cerion | 24d06f1 | 2005-11-09 21:34:20 +0000 | [diff] [blame] | 7593 | assign( zLo, binop(Iop_Add32x4, mkexpr(cLo), |
cerion | 6f1cc0f | 2005-09-16 16:02:11 +0000 | [diff] [blame] | 7594 | binop(Iop_SarN32x4, |
cerion | 1ac656a | 2005-11-04 19:44:48 +0000 | [diff] [blame] | 7595 | binop(Iop_MullEven16Sx8, |
cerion | 24d06f1 | 2005-11-09 21:34:20 +0000 | [diff] [blame] | 7596 | mkexpr(aLo), mkexpr(bLo)), |
| 7597 | mkU8(15))) ); |
cerion | 6f1cc0f | 2005-09-16 16:02:11 +0000 | [diff] [blame] | 7598 | |
cerion | 24d06f1 | 2005-11-09 21:34:20 +0000 | [diff] [blame] | 7599 | assign( zHi, binop(Iop_Add32x4, mkexpr(cHi), |
cerion | 6f1cc0f | 2005-09-16 16:02:11 +0000 | [diff] [blame] | 7600 | binop(Iop_SarN32x4, |
cerion | 1ac656a | 2005-11-04 19:44:48 +0000 | [diff] [blame] | 7601 | binop(Iop_MullEven16Sx8, |
cerion | 24d06f1 | 2005-11-09 21:34:20 +0000 | [diff] [blame] | 7602 | mkexpr(aHi), mkexpr(bHi)), |
| 7603 | mkU8(15))) ); |
cerion | 6f1cc0f | 2005-09-16 16:02:11 +0000 | [diff] [blame] | 7604 | |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 7605 | putVReg( vD_addr, |
| 7606 | binop(Iop_QNarrow32Sx4, mkexpr(zHi), mkexpr(zLo)) ); |
cerion | 6f1cc0f | 2005-09-16 16:02:11 +0000 | [diff] [blame] | 7607 | break; |
| 7608 | } |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 7609 | case 0x21: { // vmhraddshs (Mult High Round, Add Signed HW Saturate, AV p186) |
cerion | 6f1cc0f | 2005-09-16 16:02:11 +0000 | [diff] [blame] | 7610 | IRTemp zKonst = newTemp(Ity_V128); |
cerion | 6f1cc0f | 2005-09-16 16:02:11 +0000 | [diff] [blame] | 7611 | IRTemp cSigns = newTemp(Ity_V128); |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 7612 | DIP("vmhraddshs v%d,v%d,v%d,v%d\n", |
| 7613 | vD_addr, vA_addr, vB_addr, vC_addr); |
| 7614 | assign(cSigns, binop(Iop_CmpGT16Sx8, mkexpr(zeros), mkexpr(vC)) ); |
| 7615 | assign(aLo, binop(Iop_InterleaveLO16x8, mkexpr(zeros), mkexpr(vA))); |
| 7616 | assign(bLo, binop(Iop_InterleaveLO16x8, mkexpr(zeros), mkexpr(vB))); |
| 7617 | assign(cLo, binop(Iop_InterleaveLO16x8, mkexpr(cSigns),mkexpr(vC))); |
| 7618 | assign(aHi, binop(Iop_InterleaveHI16x8, mkexpr(zeros), mkexpr(vA))); |
| 7619 | assign(bHi, binop(Iop_InterleaveHI16x8, mkexpr(zeros), mkexpr(vB))); |
| 7620 | assign(cHi, binop(Iop_InterleaveHI16x8, mkexpr(cSigns),mkexpr(vC))); |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 7621 | |
cerion | 6f1cc0f | 2005-09-16 16:02:11 +0000 | [diff] [blame] | 7622 | /* shifting our const avoids store/load version of Dup */ |
cerion | 4a49b03 | 2005-11-08 16:23:07 +0000 | [diff] [blame] | 7623 | assign( zKonst, binop(Iop_ShlN32x4, unop(Iop_Dup32x4, mkU32(0x1)), |
| 7624 | mkU8(14)) ); |
cerion | 6f1cc0f | 2005-09-16 16:02:11 +0000 | [diff] [blame] | 7625 | |
cerion | 24d06f1 | 2005-11-09 21:34:20 +0000 | [diff] [blame] | 7626 | assign( zLo, binop(Iop_Add32x4, mkexpr(cLo), |
cerion | 6f1cc0f | 2005-09-16 16:02:11 +0000 | [diff] [blame] | 7627 | binop(Iop_SarN32x4, |
| 7628 | binop(Iop_Add32x4, mkexpr(zKonst), |
cerion | 1ac656a | 2005-11-04 19:44:48 +0000 | [diff] [blame] | 7629 | binop(Iop_MullEven16Sx8, |
cerion | 24d06f1 | 2005-11-09 21:34:20 +0000 | [diff] [blame] | 7630 | mkexpr(aLo), mkexpr(bLo))), |
| 7631 | mkU8(15))) ); |
cerion | 6f1cc0f | 2005-09-16 16:02:11 +0000 | [diff] [blame] | 7632 | |
cerion | 24d06f1 | 2005-11-09 21:34:20 +0000 | [diff] [blame] | 7633 | assign( zHi, binop(Iop_Add32x4, mkexpr(cHi), |
cerion | 6f1cc0f | 2005-09-16 16:02:11 +0000 | [diff] [blame] | 7634 | binop(Iop_SarN32x4, |
| 7635 | binop(Iop_Add32x4, mkexpr(zKonst), |
cerion | 1ac656a | 2005-11-04 19:44:48 +0000 | [diff] [blame] | 7636 | binop(Iop_MullEven16Sx8, |
cerion | 24d06f1 | 2005-11-09 21:34:20 +0000 | [diff] [blame] | 7637 | mkexpr(aHi), mkexpr(bHi))), |
| 7638 | mkU8(15))) ); |
cerion | 6f1cc0f | 2005-09-16 16:02:11 +0000 | [diff] [blame] | 7639 | |
| 7640 | putVReg( vD_addr, binop(Iop_QNarrow32Sx4, mkexpr(zHi), mkexpr(zLo)) ); |
| 7641 | break; |
| 7642 | } |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 7643 | case 0x22: { // vmladduhm (Mult Low, Add Unsigned HW Modulo, AV p194) |
| 7644 | DIP("vmladduhm v%d,v%d,v%d,v%d\n", |
| 7645 | vD_addr, vA_addr, vB_addr, vC_addr); |
| 7646 | assign(aLo, binop(Iop_InterleaveLO16x8, mkexpr(zeros), mkexpr(vA))); |
| 7647 | assign(bLo, binop(Iop_InterleaveLO16x8, mkexpr(zeros), mkexpr(vB))); |
| 7648 | assign(cLo, binop(Iop_InterleaveLO16x8, mkexpr(zeros), mkexpr(vC))); |
| 7649 | assign(aHi, binop(Iop_InterleaveHI16x8, mkexpr(zeros), mkexpr(vA))); |
| 7650 | assign(bHi, binop(Iop_InterleaveHI16x8, mkexpr(zeros), mkexpr(vB))); |
| 7651 | assign(cHi, binop(Iop_InterleaveHI16x8, mkexpr(zeros), mkexpr(vC))); |
| 7652 | assign(zLo, binop(Iop_Add32x4, |
| 7653 | binop(Iop_MullEven16Ux8, mkexpr(aLo), mkexpr(bLo)), |
| 7654 | mkexpr(cLo)) ); |
| 7655 | assign(zHi, binop(Iop_Add32x4, |
| 7656 | binop(Iop_MullEven16Ux8, mkexpr(aHi), mkexpr(bHi)), |
| 7657 | mkexpr(cHi))); |
| 7658 | putVReg(vD_addr, binop(Iop_Narrow32x4, mkexpr(zHi), mkexpr(zLo))); |
cerion | 6f1cc0f | 2005-09-16 16:02:11 +0000 | [diff] [blame] | 7659 | break; |
| 7660 | } |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 7661 | |
| 7662 | |
| 7663 | /* Multiply-Sum */ |
cerion | 6f1cc0f | 2005-09-16 16:02:11 +0000 | [diff] [blame] | 7664 | case 0x24: { // vmsumubm (Multiply Sum Unsigned B Modulo, AV p204) |
cerion | 4a49b03 | 2005-11-08 16:23:07 +0000 | [diff] [blame] | 7665 | IRTemp abEE, abEO, abOE, abOO; |
| 7666 | abEE = abEO = abOE = abOO = IRTemp_INVALID; |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 7667 | DIP("vmsumubm v%d,v%d,v%d,v%d\n", |
| 7668 | vD_addr, vA_addr, vB_addr, vC_addr); |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 7669 | |
cerion | 4a49b03 | 2005-11-08 16:23:07 +0000 | [diff] [blame] | 7670 | /* multiply vA,vB (unsigned, widening) */ |
cerion | 24d06f1 | 2005-11-09 21:34:20 +0000 | [diff] [blame] | 7671 | assign( abEvn, MK_Iop_MullOdd8Ux16( mkexpr(vA), mkexpr(vB) )); |
| 7672 | assign( abOdd, binop(Iop_MullEven8Ux16, mkexpr(vA), mkexpr(vB)) ); |
cerion | 4a49b03 | 2005-11-08 16:23:07 +0000 | [diff] [blame] | 7673 | |
| 7674 | /* evn,odd: V128_16Ux8 -> 2 x V128_32Ux4, zero-extended */ |
| 7675 | expand16Ux8( mkexpr(abEvn), &abEE, &abEO ); |
| 7676 | expand16Ux8( mkexpr(abOdd), &abOE, &abOO ); |
| 7677 | |
cerion | 6f1cc0f | 2005-09-16 16:02:11 +0000 | [diff] [blame] | 7678 | putVReg( vD_addr, |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 7679 | binop(Iop_Add32x4, mkexpr(vC), |
| 7680 | binop(Iop_Add32x4, |
| 7681 | binop(Iop_Add32x4, mkexpr(abEE), mkexpr(abEO)), |
| 7682 | binop(Iop_Add32x4, mkexpr(abOE), mkexpr(abOO)))) ); |
cerion | 6f1cc0f | 2005-09-16 16:02:11 +0000 | [diff] [blame] | 7683 | break; |
| 7684 | } |
cerion | 4a49b03 | 2005-11-08 16:23:07 +0000 | [diff] [blame] | 7685 | case 0x25: { // vmsummbm (Multiply Sum Mixed-Sign B Modulo, AV p201) |
| 7686 | IRTemp aEvn, aOdd, bEvn, bOdd; |
| 7687 | IRTemp abEE = newTemp(Ity_V128); |
| 7688 | IRTemp abEO = newTemp(Ity_V128); |
| 7689 | IRTemp abOE = newTemp(Ity_V128); |
| 7690 | IRTemp abOO = newTemp(Ity_V128); |
| 7691 | aEvn = aOdd = bEvn = bOdd = IRTemp_INVALID; |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 7692 | DIP("vmsummbm v%d,v%d,v%d,v%d\n", |
| 7693 | vD_addr, vA_addr, vB_addr, vC_addr); |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 7694 | |
cerion | 4a49b03 | 2005-11-08 16:23:07 +0000 | [diff] [blame] | 7695 | /* sign-extend vA, zero-extend vB, for mixed-sign multiply |
| 7696 | (separating out adjacent lanes to different vectors) */ |
| 7697 | expand8Sx16( mkexpr(vA), &aEvn, &aOdd ); |
| 7698 | expand8Ux16( mkexpr(vB), &bEvn, &bOdd ); |
| 7699 | |
| 7700 | /* multiply vA, vB, again separating adjacent lanes */ |
cerion | 24d06f1 | 2005-11-09 21:34:20 +0000 | [diff] [blame] | 7701 | assign( abEE, MK_Iop_MullOdd16Sx8( mkexpr(aEvn), mkexpr(bEvn) )); |
| 7702 | assign( abEO, binop(Iop_MullEven16Sx8, mkexpr(aEvn), mkexpr(bEvn)) ); |
| 7703 | assign( abOE, MK_Iop_MullOdd16Sx8( mkexpr(aOdd), mkexpr(bOdd) )); |
| 7704 | assign( abOO, binop(Iop_MullEven16Sx8, mkexpr(aOdd), mkexpr(bOdd)) ); |
cerion | 4a49b03 | 2005-11-08 16:23:07 +0000 | [diff] [blame] | 7705 | |
| 7706 | /* add results together, + vC */ |
| 7707 | putVReg( vD_addr, |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 7708 | binop(Iop_QAdd32Sx4, mkexpr(vC), |
| 7709 | binop(Iop_QAdd32Sx4, |
| 7710 | binop(Iop_QAdd32Sx4, mkexpr(abEE), mkexpr(abEO)), |
| 7711 | binop(Iop_QAdd32Sx4, mkexpr(abOE), mkexpr(abOO)))) ); |
cerion | 4a49b03 | 2005-11-08 16:23:07 +0000 | [diff] [blame] | 7712 | break; |
| 7713 | } |
cerion | 6f1cc0f | 2005-09-16 16:02:11 +0000 | [diff] [blame] | 7714 | case 0x26: { // vmsumuhm (Multiply Sum Unsigned HW Modulo, AV p205) |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 7715 | DIP("vmsumuhm v%d,v%d,v%d,v%d\n", |
| 7716 | vD_addr, vA_addr, vB_addr, vC_addr); |
cerion | 24d06f1 | 2005-11-09 21:34:20 +0000 | [diff] [blame] | 7717 | assign( abEvn, MK_Iop_MullOdd16Ux8( mkexpr(vA), mkexpr(vB) )); |
| 7718 | assign( abOdd, binop(Iop_MullEven16Ux8, mkexpr(vA), mkexpr(vB)) ); |
cerion | 6f1cc0f | 2005-09-16 16:02:11 +0000 | [diff] [blame] | 7719 | putVReg( vD_addr, |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 7720 | binop(Iop_Add32x4, mkexpr(vC), |
| 7721 | binop(Iop_Add32x4, mkexpr(abEvn), mkexpr(abOdd))) ); |
cerion | 6f1cc0f | 2005-09-16 16:02:11 +0000 | [diff] [blame] | 7722 | break; |
| 7723 | } |
cerion | 4a49b03 | 2005-11-08 16:23:07 +0000 | [diff] [blame] | 7724 | case 0x27: { // vmsumuhs (Multiply Sum Unsigned HW Saturate, AV p206) |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 7725 | DIP("vmsumuhs v%d,v%d,v%d,v%d\n", |
| 7726 | vD_addr, vA_addr, vB_addr, vC_addr); |
cerion | 4a49b03 | 2005-11-08 16:23:07 +0000 | [diff] [blame] | 7727 | /* widening multiply, separating lanes */ |
cerion | 24d06f1 | 2005-11-09 21:34:20 +0000 | [diff] [blame] | 7728 | assign( abEvn, MK_Iop_MullOdd16Ux8(mkexpr(vA), mkexpr(vB) )); |
| 7729 | assign( abOdd, binop(Iop_MullEven16Ux8, mkexpr(vA), mkexpr(vB)) ); |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 7730 | |
cerion | 4a49b03 | 2005-11-08 16:23:07 +0000 | [diff] [blame] | 7731 | /* break V128 to 4xI32's, zero-extending to I64's */ |
| 7732 | breakV128to4x64U( mkexpr(abEvn), &ab7, &ab5, &ab3, &ab1 ); |
| 7733 | breakV128to4x64U( mkexpr(abOdd), &ab6, &ab4, &ab2, &ab0 ); |
| 7734 | breakV128to4x64U( mkexpr(vC), &c3, &c2, &c1, &c0 ); |
| 7735 | |
| 7736 | /* add lanes */ |
| 7737 | assign( z3, binop(Iop_Add64, mkexpr(c3), |
| 7738 | binop(Iop_Add64, mkexpr(ab7), mkexpr(ab6)))); |
| 7739 | assign( z2, binop(Iop_Add64, mkexpr(c2), |
| 7740 | binop(Iop_Add64, mkexpr(ab5), mkexpr(ab4)))); |
| 7741 | assign( z1, binop(Iop_Add64, mkexpr(c1), |
| 7742 | binop(Iop_Add64, mkexpr(ab3), mkexpr(ab2)))); |
| 7743 | assign( z0, binop(Iop_Add64, mkexpr(c0), |
| 7744 | binop(Iop_Add64, mkexpr(ab1), mkexpr(ab0)))); |
| 7745 | |
| 7746 | /* saturate-narrow to 32bit, and combine to V128 */ |
| 7747 | putVReg( vD_addr, mkV128from4x64U( mkexpr(z3), mkexpr(z2), |
| 7748 | mkexpr(z1), mkexpr(z0)) ); |
| 7749 | |
cerion | 6f1cc0f | 2005-09-16 16:02:11 +0000 | [diff] [blame] | 7750 | break; |
| 7751 | } |
cerion | 4a49b03 | 2005-11-08 16:23:07 +0000 | [diff] [blame] | 7752 | case 0x28: { // vmsumshm (Multiply Sum Signed HW Modulo, AV p202) |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 7753 | DIP("vmsumshm v%d,v%d,v%d,v%d\n", |
| 7754 | vD_addr, vA_addr, vB_addr, vC_addr); |
cerion | 24d06f1 | 2005-11-09 21:34:20 +0000 | [diff] [blame] | 7755 | assign( abEvn, MK_Iop_MullOdd16Sx8( mkexpr(vA), mkexpr(vB) )); |
| 7756 | assign( abOdd, binop(Iop_MullEven16Sx8, mkexpr(vA), mkexpr(vB)) ); |
cerion | 4a49b03 | 2005-11-08 16:23:07 +0000 | [diff] [blame] | 7757 | putVReg( vD_addr, |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 7758 | binop(Iop_Add32x4, mkexpr(vC), |
| 7759 | binop(Iop_Add32x4, mkexpr(abOdd), mkexpr(abEvn))) ); |
cerion | 4a49b03 | 2005-11-08 16:23:07 +0000 | [diff] [blame] | 7760 | break; |
| 7761 | } |
| 7762 | case 0x29: { // vmsumshs (Multiply Sum Signed HW Saturate, AV p203) |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 7763 | DIP("vmsumshs v%d,v%d,v%d,v%d\n", |
| 7764 | vD_addr, vA_addr, vB_addr, vC_addr); |
cerion | 4a49b03 | 2005-11-08 16:23:07 +0000 | [diff] [blame] | 7765 | /* widening multiply, separating lanes */ |
cerion | 24d06f1 | 2005-11-09 21:34:20 +0000 | [diff] [blame] | 7766 | assign( abEvn, MK_Iop_MullOdd16Sx8( mkexpr(vA), mkexpr(vB) )); |
| 7767 | assign( abOdd, binop(Iop_MullEven16Sx8, mkexpr(vA), mkexpr(vB)) ); |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 7768 | |
cerion | 4a49b03 | 2005-11-08 16:23:07 +0000 | [diff] [blame] | 7769 | /* break V128 to 4xI32's, sign-extending to I64's */ |
| 7770 | breakV128to4x64S( mkexpr(abEvn), &ab7, &ab5, &ab3, &ab1 ); |
| 7771 | breakV128to4x64S( mkexpr(abOdd), &ab6, &ab4, &ab2, &ab0 ); |
| 7772 | breakV128to4x64S( mkexpr(vC), &c3, &c2, &c1, &c0 ); |
| 7773 | |
| 7774 | /* add lanes */ |
| 7775 | assign( z3, binop(Iop_Add64, mkexpr(c3), |
| 7776 | binop(Iop_Add64, mkexpr(ab7), mkexpr(ab6)))); |
| 7777 | assign( z2, binop(Iop_Add64, mkexpr(c2), |
| 7778 | binop(Iop_Add64, mkexpr(ab5), mkexpr(ab4)))); |
| 7779 | assign( z1, binop(Iop_Add64, mkexpr(c1), |
| 7780 | binop(Iop_Add64, mkexpr(ab3), mkexpr(ab2)))); |
| 7781 | assign( z0, binop(Iop_Add64, mkexpr(c0), |
| 7782 | binop(Iop_Add64, mkexpr(ab1), mkexpr(ab0)))); |
| 7783 | |
| 7784 | /* saturate-narrow to 32bit, and combine to V128 */ |
| 7785 | putVReg( vD_addr, mkV128from4x64S( mkexpr(z3), mkexpr(z2), |
| 7786 | mkexpr(z1), mkexpr(z0)) ); |
| 7787 | break; |
| 7788 | } |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 7789 | default: |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 7790 | vex_printf("dis_av_multarith(ppc)(opc2)\n"); |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 7791 | return False; |
| 7792 | } |
| 7793 | return True; |
| 7794 | } |
| 7795 | |
| 7796 | /* |
| 7797 | AltiVec Shift/Rotate Instructions |
| 7798 | */ |
| 7799 | static Bool dis_av_shift ( UInt theInstr ) |
| 7800 | { |
cerion | 76de5cf | 2005-11-18 18:25:12 +0000 | [diff] [blame] | 7801 | /* VX-Form */ |
| 7802 | UChar opc1 = ifieldOPC(theInstr); |
| 7803 | UChar vD_addr = ifieldRegDS(theInstr); |
| 7804 | UChar vA_addr = ifieldRegA(theInstr); |
| 7805 | UChar vB_addr = ifieldRegB(theInstr); |
| 7806 | UInt opc2 = IFIELD( theInstr, 0, 11 ); |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 7807 | |
cerion | 27b3d7e | 2005-09-14 20:35:47 +0000 | [diff] [blame] | 7808 | IRTemp vA = newTemp(Ity_V128); |
| 7809 | IRTemp vB = newTemp(Ity_V128); |
| 7810 | assign( vA, getVReg(vA_addr)); |
| 7811 | assign( vB, getVReg(vB_addr)); |
| 7812 | |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 7813 | if (opc1 != 0x4){ |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 7814 | vex_printf("dis_av_shift(ppc)(instr)\n"); |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 7815 | return False; |
| 7816 | } |
| 7817 | |
| 7818 | switch (opc2) { |
| 7819 | /* Rotate */ |
| 7820 | case 0x004: // vrlb (Rotate Left Integer B, AV p234) |
| 7821 | DIP("vrlb v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr); |
sewardj | 1bee561 | 2005-11-10 18:10:58 +0000 | [diff] [blame] | 7822 | putVReg( vD_addr, binop(Iop_Rol8x16, mkexpr(vA), mkexpr(vB)) ); |
cerion | 0a7b4f4 | 2005-09-16 07:54:40 +0000 | [diff] [blame] | 7823 | break; |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 7824 | |
| 7825 | case 0x044: // vrlh (Rotate Left Integer HW, AV p235) |
| 7826 | DIP("vrlh v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr); |
sewardj | 1bee561 | 2005-11-10 18:10:58 +0000 | [diff] [blame] | 7827 | putVReg( vD_addr, binop(Iop_Rol16x8, mkexpr(vA), mkexpr(vB)) ); |
cerion | 0a7b4f4 | 2005-09-16 07:54:40 +0000 | [diff] [blame] | 7828 | break; |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 7829 | |
| 7830 | case 0x084: // vrlw (Rotate Left Integer W, AV p236) |
| 7831 | DIP("vrlw v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr); |
sewardj | 1bee561 | 2005-11-10 18:10:58 +0000 | [diff] [blame] | 7832 | putVReg( vD_addr, binop(Iop_Rol32x4, mkexpr(vA), mkexpr(vB)) ); |
cerion | 0a7b4f4 | 2005-09-16 07:54:40 +0000 | [diff] [blame] | 7833 | break; |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 7834 | |
| 7835 | |
| 7836 | /* Shift Left */ |
| 7837 | case 0x104: // vslb (Shift Left Integer B, AV p240) |
| 7838 | DIP("vslb v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr); |
cerion | 0a7b4f4 | 2005-09-16 07:54:40 +0000 | [diff] [blame] | 7839 | putVReg( vD_addr, binop(Iop_Shl8x16, mkexpr(vA), mkexpr(vB)) ); |
| 7840 | break; |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 7841 | |
| 7842 | case 0x144: // vslh (Shift Left Integer HW, AV p242) |
| 7843 | DIP("vslh v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr); |
cerion | 0a7b4f4 | 2005-09-16 07:54:40 +0000 | [diff] [blame] | 7844 | putVReg( vD_addr, binop(Iop_Shl16x8, mkexpr(vA), mkexpr(vB)) ); |
| 7845 | break; |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 7846 | |
| 7847 | case 0x184: // vslw (Shift Left Integer W, AV p244) |
| 7848 | DIP("vslw v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr); |
cerion | 0a7b4f4 | 2005-09-16 07:54:40 +0000 | [diff] [blame] | 7849 | putVReg( vD_addr, binop(Iop_Shl32x4, mkexpr(vA), mkexpr(vB)) ); |
| 7850 | break; |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 7851 | |
cerion | 0a7b4f4 | 2005-09-16 07:54:40 +0000 | [diff] [blame] | 7852 | case 0x1C4: { // vsl (Shift Left, AV p239) |
cerion | 0a7b4f4 | 2005-09-16 07:54:40 +0000 | [diff] [blame] | 7853 | IRTemp sh = newTemp(Ity_I8); |
sewardj | 197bd17 | 2005-10-12 11:34:33 +0000 | [diff] [blame] | 7854 | DIP("vsl v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr); |
cerion | 0a7b4f4 | 2005-09-16 07:54:40 +0000 | [diff] [blame] | 7855 | assign( sh, binop(Iop_And8, mkU8(0x7), |
| 7856 | unop(Iop_32to8, |
| 7857 | unop(Iop_V128to32, mkexpr(vB)))) ); |
| 7858 | putVReg( vD_addr, |
| 7859 | binop(Iop_ShlV128, mkexpr(vA), mkexpr(sh)) ); |
| 7860 | break; |
| 7861 | } |
| 7862 | case 0x40C: { // vslo (Shift Left by Octet, AV p243) |
cerion | 0a7b4f4 | 2005-09-16 07:54:40 +0000 | [diff] [blame] | 7863 | IRTemp sh = newTemp(Ity_I8); |
sewardj | 197bd17 | 2005-10-12 11:34:33 +0000 | [diff] [blame] | 7864 | DIP("vslo v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr); |
cerion | 0a7b4f4 | 2005-09-16 07:54:40 +0000 | [diff] [blame] | 7865 | assign( sh, binop(Iop_And8, mkU8(0x78), |
| 7866 | unop(Iop_32to8, |
| 7867 | unop(Iop_V128to32, mkexpr(vB)))) ); |
| 7868 | putVReg( vD_addr, |
| 7869 | binop(Iop_ShlV128, mkexpr(vA), mkexpr(sh)) ); |
| 7870 | break; |
| 7871 | } |
| 7872 | |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 7873 | |
| 7874 | /* Shift Right */ |
| 7875 | case 0x204: // vsrb (Shift Right B, AV p256) |
| 7876 | DIP("vsrb v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr); |
cerion | 0a7b4f4 | 2005-09-16 07:54:40 +0000 | [diff] [blame] | 7877 | putVReg( vD_addr, binop(Iop_Shr8x16, mkexpr(vA), mkexpr(vB)) ); |
| 7878 | break; |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 7879 | |
| 7880 | case 0x244: // vsrh (Shift Right HW, AV p257) |
| 7881 | DIP("vsrh v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr); |
cerion | 0a7b4f4 | 2005-09-16 07:54:40 +0000 | [diff] [blame] | 7882 | putVReg( vD_addr, binop(Iop_Shr16x8, mkexpr(vA), mkexpr(vB)) ); |
| 7883 | break; |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 7884 | |
| 7885 | case 0x284: // vsrw (Shift Right W, AV p259) |
| 7886 | DIP("vsrw v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr); |
cerion | 0a7b4f4 | 2005-09-16 07:54:40 +0000 | [diff] [blame] | 7887 | putVReg( vD_addr, binop(Iop_Shr32x4, mkexpr(vA), mkexpr(vB)) ); |
| 7888 | break; |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 7889 | |
cerion | 27b3d7e | 2005-09-14 20:35:47 +0000 | [diff] [blame] | 7890 | case 0x2C4: { // vsr (Shift Right, AV p251) |
cerion | 27b3d7e | 2005-09-14 20:35:47 +0000 | [diff] [blame] | 7891 | IRTemp sh = newTemp(Ity_I8); |
sewardj | 197bd17 | 2005-10-12 11:34:33 +0000 | [diff] [blame] | 7892 | DIP("vsr v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr); |
cerion | 27b3d7e | 2005-09-14 20:35:47 +0000 | [diff] [blame] | 7893 | assign( sh, binop(Iop_And8, mkU8(0x7), |
| 7894 | unop(Iop_32to8, |
| 7895 | unop(Iop_V128to32, mkexpr(vB)))) ); |
| 7896 | putVReg( vD_addr, |
| 7897 | binop(Iop_ShrV128, mkexpr(vA), mkexpr(sh)) ); |
| 7898 | break; |
| 7899 | } |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 7900 | case 0x304: // vsrab (Shift Right Alg B, AV p253) |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 7901 | DIP("vsrab v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr); |
cerion | 0a7b4f4 | 2005-09-16 07:54:40 +0000 | [diff] [blame] | 7902 | putVReg( vD_addr, binop(Iop_Sar8x16, mkexpr(vA), mkexpr(vB)) ); |
| 7903 | break; |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 7904 | |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 7905 | case 0x344: // vsrah (Shift Right Alg HW, AV p254) |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 7906 | DIP("vsrah v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr); |
cerion | 0a7b4f4 | 2005-09-16 07:54:40 +0000 | [diff] [blame] | 7907 | putVReg( vD_addr, binop(Iop_Sar16x8, mkexpr(vA), mkexpr(vB)) ); |
| 7908 | break; |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 7909 | |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 7910 | case 0x384: // vsraw (Shift Right Alg W, AV p255) |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 7911 | DIP("vsraw v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr); |
cerion | 0a7b4f4 | 2005-09-16 07:54:40 +0000 | [diff] [blame] | 7912 | putVReg( vD_addr, binop(Iop_Sar32x4, mkexpr(vA), mkexpr(vB)) ); |
| 7913 | break; |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 7914 | |
cerion | 0a7b4f4 | 2005-09-16 07:54:40 +0000 | [diff] [blame] | 7915 | case 0x44C: { // vsro (Shift Right by Octet, AV p258) |
cerion | 0a7b4f4 | 2005-09-16 07:54:40 +0000 | [diff] [blame] | 7916 | IRTemp sh = newTemp(Ity_I8); |
sewardj | 197bd17 | 2005-10-12 11:34:33 +0000 | [diff] [blame] | 7917 | DIP("vsro v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr); |
cerion | 0a7b4f4 | 2005-09-16 07:54:40 +0000 | [diff] [blame] | 7918 | assign( sh, binop(Iop_And8, mkU8(0x78), |
| 7919 | unop(Iop_32to8, |
| 7920 | unop(Iop_V128to32, mkexpr(vB)))) ); |
| 7921 | putVReg( vD_addr, |
| 7922 | binop(Iop_ShrV128, mkexpr(vA), mkexpr(sh)) ); |
| 7923 | break; |
| 7924 | } |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 7925 | |
| 7926 | default: |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 7927 | vex_printf("dis_av_shift(ppc)(opc2)\n"); |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 7928 | return False; |
| 7929 | } |
| 7930 | return True; |
| 7931 | } |
| 7932 | |
| 7933 | /* |
| 7934 | AltiVec Permute Instructions |
| 7935 | */ |
| 7936 | static Bool dis_av_permute ( UInt theInstr ) |
| 7937 | { |
cerion | 76de5cf | 2005-11-18 18:25:12 +0000 | [diff] [blame] | 7938 | /* VA-Form, VX-Form */ |
| 7939 | UChar opc1 = ifieldOPC(theInstr); |
| 7940 | UChar vD_addr = ifieldRegDS(theInstr); |
| 7941 | UChar vA_addr = ifieldRegA(theInstr); |
| 7942 | UChar UIMM_5 = vA_addr; |
| 7943 | UChar vB_addr = ifieldRegB(theInstr); |
| 7944 | UChar vC_addr = ifieldRegC(theInstr); |
| 7945 | UChar b10 = ifieldBIT10(theInstr); |
| 7946 | UChar SHB_uimm4 = toUChar( IFIELD( theInstr, 6, 4 ) ); |
| 7947 | UInt opc2 = toUChar( IFIELD( theInstr, 0, 6 ) ); |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 7948 | |
cerion | 76de5cf | 2005-11-18 18:25:12 +0000 | [diff] [blame] | 7949 | UChar SIMM_8 = extend_s_5to8(UIMM_5); |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 7950 | |
cerion | 6e7a0ea | 2005-09-13 13:34:09 +0000 | [diff] [blame] | 7951 | IRTemp vA = newTemp(Ity_V128); |
| 7952 | IRTemp vB = newTemp(Ity_V128); |
| 7953 | IRTemp vC = newTemp(Ity_V128); |
| 7954 | assign( vA, getVReg(vA_addr)); |
| 7955 | assign( vB, getVReg(vB_addr)); |
| 7956 | assign( vC, getVReg(vC_addr)); |
| 7957 | |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 7958 | if (opc1 != 0x4) { |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 7959 | vex_printf("dis_av_permute(ppc)(instr)\n"); |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 7960 | return False; |
| 7961 | } |
| 7962 | |
| 7963 | switch (opc2) { |
| 7964 | case 0x2A: // vsel (Conditional Select, AV p238) |
| 7965 | DIP("vsel v%d,v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr, vC_addr); |
cerion | 6e7a0ea | 2005-09-13 13:34:09 +0000 | [diff] [blame] | 7966 | /* vD = (vA & ~vC) | (vB & vC) */ |
| 7967 | putVReg( vD_addr, binop(Iop_OrV128, |
| 7968 | binop(Iop_AndV128, mkexpr(vA), unop(Iop_NotV128, mkexpr(vC))), |
| 7969 | binop(Iop_AndV128, mkexpr(vB), mkexpr(vC))) ); |
| 7970 | return True; |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 7971 | |
cerion | 92d9d87 | 2005-09-15 21:58:50 +0000 | [diff] [blame] | 7972 | case 0x2B: { // vperm (Permute, AV p218) |
cerion | 92d9d87 | 2005-09-15 21:58:50 +0000 | [diff] [blame] | 7973 | /* limited to two args for IR, so have to play games... */ |
sewardj | dc1f913 | 2005-10-22 12:49:49 +0000 | [diff] [blame] | 7974 | IRTemp a_perm = newTemp(Ity_V128); |
| 7975 | IRTemp b_perm = newTemp(Ity_V128); |
| 7976 | IRTemp mask = newTemp(Ity_V128); |
| 7977 | IRTemp vC_andF = newTemp(Ity_V128); |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 7978 | DIP("vperm v%d,v%d,v%d,v%d\n", |
| 7979 | vD_addr, vA_addr, vB_addr, vC_addr); |
sewardj | dc1f913 | 2005-10-22 12:49:49 +0000 | [diff] [blame] | 7980 | /* Limit the Perm8x16 steering values to 0 .. 15 as that is what |
| 7981 | IR specifies, and also to hide irrelevant bits from |
| 7982 | memcheck */ |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 7983 | assign( vC_andF, |
| 7984 | binop(Iop_AndV128, mkexpr(vC), |
| 7985 | unop(Iop_Dup8x16, mkU8(0xF))) ); |
| 7986 | assign( a_perm, |
| 7987 | binop(Iop_Perm8x16, mkexpr(vA), mkexpr(vC_andF)) ); |
| 7988 | assign( b_perm, |
| 7989 | binop(Iop_Perm8x16, mkexpr(vB), mkexpr(vC_andF)) ); |
cerion | 92d9d87 | 2005-09-15 21:58:50 +0000 | [diff] [blame] | 7990 | // mask[i8] = (vC[i8]_4 == 1) ? 0xFF : 0x0 |
| 7991 | assign( mask, binop(Iop_SarN8x16, |
| 7992 | binop(Iop_ShlN8x16, mkexpr(vC), mkU8(3)), |
| 7993 | mkU8(7)) ); |
| 7994 | // dst = (a & ~mask) | (b & mask) |
| 7995 | putVReg( vD_addr, binop(Iop_OrV128, |
| 7996 | binop(Iop_AndV128, mkexpr(a_perm), |
| 7997 | unop(Iop_NotV128, mkexpr(mask))), |
| 7998 | binop(Iop_AndV128, mkexpr(b_perm), |
| 7999 | mkexpr(mask))) ); |
| 8000 | return True; |
| 8001 | } |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 8002 | case 0x2C: // vsldoi (Shift Left Double by Octet Imm, AV p241) |
| 8003 | if (b10 != 0) { |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 8004 | vex_printf("dis_av_permute(ppc)(vsldoi)\n"); |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 8005 | return False; |
| 8006 | } |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 8007 | DIP("vsldoi v%d,v%d,v%d,%d\n", |
| 8008 | vD_addr, vA_addr, vB_addr, SHB_uimm4); |
cerion | 92d9d87 | 2005-09-15 21:58:50 +0000 | [diff] [blame] | 8009 | if (SHB_uimm4 == 0) |
| 8010 | putVReg( vD_addr, mkexpr(vA) ); |
| 8011 | else |
| 8012 | putVReg( vD_addr, |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 8013 | binop(Iop_OrV128, |
| 8014 | binop(Iop_ShlV128, mkexpr(vA), mkU8(SHB_uimm4*8)), |
| 8015 | binop(Iop_ShrV128, mkexpr(vB), mkU8((16-SHB_uimm4)*8))) ); |
cerion | 92d9d87 | 2005-09-15 21:58:50 +0000 | [diff] [blame] | 8016 | return True; |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 8017 | |
| 8018 | default: |
| 8019 | break; // Fall through... |
| 8020 | } |
| 8021 | |
cerion | 76de5cf | 2005-11-18 18:25:12 +0000 | [diff] [blame] | 8022 | opc2 = IFIELD( theInstr, 0, 11 ); |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 8023 | switch (opc2) { |
| 8024 | |
| 8025 | /* Merge */ |
| 8026 | case 0x00C: // vmrghb (Merge High B, AV p195) |
| 8027 | DIP("vmrghb v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr); |
cerion | 92d9d87 | 2005-09-15 21:58:50 +0000 | [diff] [blame] | 8028 | putVReg( vD_addr, |
| 8029 | binop(Iop_InterleaveHI8x16, mkexpr(vA), mkexpr(vB)) ); |
| 8030 | break; |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 8031 | |
| 8032 | case 0x04C: // vmrghh (Merge High HW, AV p196) |
| 8033 | DIP("vmrghh v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr); |
cerion | 92d9d87 | 2005-09-15 21:58:50 +0000 | [diff] [blame] | 8034 | putVReg( vD_addr, |
| 8035 | binop(Iop_InterleaveHI16x8, mkexpr(vA), mkexpr(vB)) ); |
| 8036 | break; |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 8037 | |
| 8038 | case 0x08C: // vmrghw (Merge High W, AV p197) |
| 8039 | DIP("vmrghw v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr); |
cerion | 92d9d87 | 2005-09-15 21:58:50 +0000 | [diff] [blame] | 8040 | putVReg( vD_addr, |
| 8041 | binop(Iop_InterleaveHI32x4, mkexpr(vA), mkexpr(vB)) ); |
| 8042 | break; |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 8043 | |
| 8044 | case 0x10C: // vmrglb (Merge Low B, AV p198) |
| 8045 | DIP("vmrglb v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr); |
cerion | 92d9d87 | 2005-09-15 21:58:50 +0000 | [diff] [blame] | 8046 | putVReg( vD_addr, |
| 8047 | binop(Iop_InterleaveLO8x16, mkexpr(vA), mkexpr(vB)) ); |
| 8048 | break; |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 8049 | |
| 8050 | case 0x14C: // vmrglh (Merge Low HW, AV p199) |
| 8051 | DIP("vmrglh v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr); |
cerion | 92d9d87 | 2005-09-15 21:58:50 +0000 | [diff] [blame] | 8052 | putVReg( vD_addr, |
| 8053 | binop(Iop_InterleaveLO16x8, mkexpr(vA), mkexpr(vB)) ); |
| 8054 | break; |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 8055 | |
| 8056 | case 0x18C: // vmrglw (Merge Low W, AV p200) |
| 8057 | DIP("vmrglw v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr); |
cerion | 92d9d87 | 2005-09-15 21:58:50 +0000 | [diff] [blame] | 8058 | putVReg( vD_addr, |
| 8059 | binop(Iop_InterleaveLO32x4, mkexpr(vA), mkexpr(vB)) ); |
| 8060 | break; |
| 8061 | |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 8062 | |
| 8063 | /* Splat */ |
cerion | 92d9d87 | 2005-09-15 21:58:50 +0000 | [diff] [blame] | 8064 | case 0x20C: { // vspltb (Splat Byte, AV p245) |
cerion | 92d9d87 | 2005-09-15 21:58:50 +0000 | [diff] [blame] | 8065 | /* vD = Dup8x16( vB[UIMM_5] ) */ |
sewardj | d147094 | 2005-10-22 02:01:16 +0000 | [diff] [blame] | 8066 | UChar sh_uimm = (15 - (UIMM_5 & 15)) * 8; |
sewardj | 197bd17 | 2005-10-12 11:34:33 +0000 | [diff] [blame] | 8067 | DIP("vspltb v%d,v%d,%d\n", vD_addr, vB_addr, UIMM_5); |
cerion | 92d9d87 | 2005-09-15 21:58:50 +0000 | [diff] [blame] | 8068 | putVReg( vD_addr, unop(Iop_Dup8x16, |
| 8069 | unop(Iop_32to8, unop(Iop_V128to32, |
| 8070 | binop(Iop_ShrV128, mkexpr(vB), mkU8(sh_uimm))))) ); |
| 8071 | break; |
| 8072 | } |
| 8073 | case 0x24C: { // vsplth (Splat Half Word, AV p246) |
sewardj | d147094 | 2005-10-22 02:01:16 +0000 | [diff] [blame] | 8074 | UChar sh_uimm = (7 - (UIMM_5 & 7)) * 16; |
sewardj | 197bd17 | 2005-10-12 11:34:33 +0000 | [diff] [blame] | 8075 | DIP("vsplth v%d,v%d,%d\n", vD_addr, vB_addr, UIMM_5); |
cerion | 92d9d87 | 2005-09-15 21:58:50 +0000 | [diff] [blame] | 8076 | putVReg( vD_addr, unop(Iop_Dup16x8, |
| 8077 | unop(Iop_32to16, unop(Iop_V128to32, |
| 8078 | binop(Iop_ShrV128, mkexpr(vB), mkU8(sh_uimm))))) ); |
| 8079 | break; |
| 8080 | } |
cerion | 27b3d7e | 2005-09-14 20:35:47 +0000 | [diff] [blame] | 8081 | case 0x28C: { // vspltw (Splat Word, AV p250) |
cerion | 27b3d7e | 2005-09-14 20:35:47 +0000 | [diff] [blame] | 8082 | /* vD = Dup32x4( vB[UIMM_5] ) */ |
sewardj | d147094 | 2005-10-22 02:01:16 +0000 | [diff] [blame] | 8083 | UChar sh_uimm = (3 - (UIMM_5 & 3)) * 32; |
sewardj | 197bd17 | 2005-10-12 11:34:33 +0000 | [diff] [blame] | 8084 | DIP("vspltw v%d,v%d,%d\n", vD_addr, vB_addr, UIMM_5); |
cerion | 27b3d7e | 2005-09-14 20:35:47 +0000 | [diff] [blame] | 8085 | putVReg( vD_addr, unop(Iop_Dup32x4, |
| 8086 | unop(Iop_V128to32, |
| 8087 | binop(Iop_ShrV128, mkexpr(vB), mkU8(sh_uimm)))) ); |
| 8088 | break; |
| 8089 | } |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 8090 | case 0x30C: // vspltisb (Splat Immediate Signed B, AV p247) |
| 8091 | DIP("vspltisb v%d,%d\n", vD_addr, (Char)SIMM_8); |
cerion | 92d9d87 | 2005-09-15 21:58:50 +0000 | [diff] [blame] | 8092 | putVReg( vD_addr, unop(Iop_Dup8x16, mkU8(SIMM_8)) ); |
| 8093 | break; |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 8094 | |
| 8095 | case 0x34C: // vspltish (Splat Immediate Signed HW, AV p248) |
| 8096 | DIP("vspltish v%d,%d\n", vD_addr, (Char)SIMM_8); |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 8097 | putVReg( vD_addr, |
| 8098 | unop(Iop_Dup16x8, mkU16(extend_s_8to32(SIMM_8))) ); |
cerion | 92d9d87 | 2005-09-15 21:58:50 +0000 | [diff] [blame] | 8099 | break; |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 8100 | |
| 8101 | case 0x38C: // vspltisw (Splat Immediate Signed W, AV p249) |
| 8102 | DIP("vspltisw v%d,%d\n", vD_addr, (Char)SIMM_8); |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 8103 | putVReg( vD_addr, |
| 8104 | unop(Iop_Dup32x4, mkU32(extend_s_8to32(SIMM_8))) ); |
cerion | 92d9d87 | 2005-09-15 21:58:50 +0000 | [diff] [blame] | 8105 | break; |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 8106 | |
| 8107 | default: |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 8108 | vex_printf("dis_av_permute(ppc)(opc2)\n"); |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 8109 | return False; |
| 8110 | } |
| 8111 | return True; |
| 8112 | } |
| 8113 | |
| 8114 | /* |
| 8115 | AltiVec Pack/Unpack Instructions |
| 8116 | */ |
| 8117 | static Bool dis_av_pack ( UInt theInstr ) |
| 8118 | { |
cerion | 76de5cf | 2005-11-18 18:25:12 +0000 | [diff] [blame] | 8119 | /* VX-Form */ |
| 8120 | UChar opc1 = ifieldOPC(theInstr); |
| 8121 | UChar vD_addr = ifieldRegDS(theInstr); |
| 8122 | UChar vA_addr = ifieldRegA(theInstr); |
| 8123 | UChar vB_addr = ifieldRegB(theInstr); |
| 8124 | UInt opc2 = IFIELD( theInstr, 0, 11 ); |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 8125 | |
sewardj | 197bd17 | 2005-10-12 11:34:33 +0000 | [diff] [blame] | 8126 | IRTemp signs = IRTemp_INVALID; |
| 8127 | IRTemp zeros = IRTemp_INVALID; |
cerion | 76de5cf | 2005-11-18 18:25:12 +0000 | [diff] [blame] | 8128 | IRTemp vA = newTemp(Ity_V128); |
| 8129 | IRTemp vB = newTemp(Ity_V128); |
cerion | 3c05279 | 2005-09-16 07:13:44 +0000 | [diff] [blame] | 8130 | assign( vA, getVReg(vA_addr)); |
| 8131 | assign( vB, getVReg(vB_addr)); |
| 8132 | |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 8133 | if (opc1 != 0x4) { |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 8134 | vex_printf("dis_av_pack(ppc)(instr)\n"); |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 8135 | return False; |
| 8136 | } |
| 8137 | |
| 8138 | switch (opc2) { |
| 8139 | /* Packing */ |
| 8140 | case 0x00E: // vpkuhum (Pack Unsigned HW Unsigned Modulo, AV p224) |
| 8141 | DIP("vpkuhum v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr); |
sewardj | 1bee561 | 2005-11-10 18:10:58 +0000 | [diff] [blame] | 8142 | putVReg( vD_addr, binop(Iop_Narrow16x8, mkexpr(vA), mkexpr(vB)) ); |
cerion | 3c05279 | 2005-09-16 07:13:44 +0000 | [diff] [blame] | 8143 | return True; |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 8144 | |
| 8145 | case 0x04E: // vpkuwum (Pack Unsigned W Unsigned Modulo, AV p226) |
| 8146 | DIP("vpkuwum v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr); |
sewardj | 1bee561 | 2005-11-10 18:10:58 +0000 | [diff] [blame] | 8147 | putVReg( vD_addr, binop(Iop_Narrow32x4, mkexpr(vA), mkexpr(vB)) ); |
cerion | 3c05279 | 2005-09-16 07:13:44 +0000 | [diff] [blame] | 8148 | return True; |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 8149 | |
| 8150 | case 0x08E: // vpkuhus (Pack Unsigned HW Unsigned Saturate, AV p225) |
| 8151 | DIP("vpkuhus v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr); |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 8152 | putVReg( vD_addr, |
| 8153 | binop(Iop_QNarrow16Ux8, mkexpr(vA), mkexpr(vB)) ); |
cerion | 3c05279 | 2005-09-16 07:13:44 +0000 | [diff] [blame] | 8154 | // TODO: set VSCR[SAT] |
| 8155 | return True; |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 8156 | |
| 8157 | case 0x0CE: // vpkuwus (Pack Unsigned W Unsigned Saturate, AV p227) |
| 8158 | DIP("vpkuwus v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr); |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 8159 | putVReg( vD_addr, |
| 8160 | binop(Iop_QNarrow32Ux4, mkexpr(vA), mkexpr(vB)) ); |
cerion | 3c05279 | 2005-09-16 07:13:44 +0000 | [diff] [blame] | 8161 | // TODO: set VSCR[SAT] |
| 8162 | return True; |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 8163 | |
cerion | 3c05279 | 2005-09-16 07:13:44 +0000 | [diff] [blame] | 8164 | case 0x10E: { // vpkshus (Pack Signed HW Unsigned Saturate, AV p221) |
cerion | 3c05279 | 2005-09-16 07:13:44 +0000 | [diff] [blame] | 8165 | // This insn does a signed->unsigned saturating conversion. |
| 8166 | // Conversion done here, then uses unsigned->unsigned vpk insn: |
| 8167 | // => UnsignedSaturatingNarrow( x & ~ (x >>s 15) ) |
| 8168 | IRTemp vA_tmp = newTemp(Ity_V128); |
| 8169 | IRTemp vB_tmp = newTemp(Ity_V128); |
sewardj | 197bd17 | 2005-10-12 11:34:33 +0000 | [diff] [blame] | 8170 | DIP("vpkshus v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr); |
cerion | 3c05279 | 2005-09-16 07:13:44 +0000 | [diff] [blame] | 8171 | assign( vA_tmp, binop(Iop_AndV128, mkexpr(vA), |
| 8172 | unop(Iop_NotV128, |
| 8173 | binop(Iop_SarN16x8, |
| 8174 | mkexpr(vA), mkU8(15)))) ); |
| 8175 | assign( vB_tmp, binop(Iop_AndV128, mkexpr(vB), |
| 8176 | unop(Iop_NotV128, |
| 8177 | binop(Iop_SarN16x8, |
| 8178 | mkexpr(vB), mkU8(15)))) ); |
| 8179 | putVReg( vD_addr, binop(Iop_QNarrow16Ux8, |
| 8180 | mkexpr(vA_tmp), mkexpr(vB_tmp)) ); |
| 8181 | // TODO: set VSCR[SAT] |
| 8182 | return True; |
| 8183 | } |
| 8184 | case 0x14E: { // vpkswus (Pack Signed W Unsigned Saturate, AV p223) |
cerion | 3c05279 | 2005-09-16 07:13:44 +0000 | [diff] [blame] | 8185 | // This insn does a signed->unsigned saturating conversion. |
| 8186 | // Conversion done here, then uses unsigned->unsigned vpk insn: |
| 8187 | // => UnsignedSaturatingNarrow( x & ~ (x >>s 31) ) |
| 8188 | IRTemp vA_tmp = newTemp(Ity_V128); |
| 8189 | IRTemp vB_tmp = newTemp(Ity_V128); |
sewardj | 197bd17 | 2005-10-12 11:34:33 +0000 | [diff] [blame] | 8190 | DIP("vpkswus v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr); |
cerion | 3c05279 | 2005-09-16 07:13:44 +0000 | [diff] [blame] | 8191 | assign( vA_tmp, binop(Iop_AndV128, mkexpr(vA), |
| 8192 | unop(Iop_NotV128, |
| 8193 | binop(Iop_SarN32x4, |
| 8194 | mkexpr(vA), mkU8(31)))) ); |
| 8195 | assign( vB_tmp, binop(Iop_AndV128, mkexpr(vB), |
| 8196 | unop(Iop_NotV128, |
| 8197 | binop(Iop_SarN32x4, |
| 8198 | mkexpr(vB), mkU8(31)))) ); |
| 8199 | putVReg( vD_addr, binop(Iop_QNarrow32Ux4, |
| 8200 | mkexpr(vA_tmp), mkexpr(vB_tmp)) ); |
| 8201 | // TODO: set VSCR[SAT] |
| 8202 | return True; |
| 8203 | } |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 8204 | case 0x18E: // vpkshss (Pack Signed HW Signed Saturate, AV p220) |
| 8205 | DIP("vpkshss v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr); |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 8206 | putVReg( vD_addr, |
| 8207 | binop(Iop_QNarrow16Sx8, mkexpr(vA), mkexpr(vB)) ); |
cerion | 3c05279 | 2005-09-16 07:13:44 +0000 | [diff] [blame] | 8208 | // TODO: set VSCR[SAT] |
| 8209 | return True; |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 8210 | |
| 8211 | case 0x1CE: // vpkswss (Pack Signed W Signed Saturate, AV p222) |
| 8212 | DIP("vpkswss v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr); |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 8213 | putVReg( vD_addr, |
| 8214 | binop(Iop_QNarrow32Sx4, mkexpr(vA), mkexpr(vB)) ); |
cerion | 3c05279 | 2005-09-16 07:13:44 +0000 | [diff] [blame] | 8215 | // TODO: set VSCR[SAT] |
| 8216 | return True; |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 8217 | |
cerion | 3c05279 | 2005-09-16 07:13:44 +0000 | [diff] [blame] | 8218 | case 0x30E: { // vpkpx (Pack Pixel, AV p219) |
cerion | 3c05279 | 2005-09-16 07:13:44 +0000 | [diff] [blame] | 8219 | /* CAB: Worth a new primop? */ |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 8220 | /* Using shifts to compact pixel elements, then packing them */ |
cerion | 3c05279 | 2005-09-16 07:13:44 +0000 | [diff] [blame] | 8221 | IRTemp a1 = newTemp(Ity_V128); |
| 8222 | IRTemp a2 = newTemp(Ity_V128); |
| 8223 | IRTemp a3 = newTemp(Ity_V128); |
| 8224 | IRTemp a_tmp = newTemp(Ity_V128); |
| 8225 | IRTemp b1 = newTemp(Ity_V128); |
| 8226 | IRTemp b2 = newTemp(Ity_V128); |
| 8227 | IRTemp b3 = newTemp(Ity_V128); |
| 8228 | IRTemp b_tmp = newTemp(Ity_V128); |
sewardj | 197bd17 | 2005-10-12 11:34:33 +0000 | [diff] [blame] | 8229 | DIP("vpkpx v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr); |
cerion | 3c05279 | 2005-09-16 07:13:44 +0000 | [diff] [blame] | 8230 | assign( a1, binop(Iop_ShlN16x8, |
| 8231 | binop(Iop_ShrN32x4, mkexpr(vA), mkU8(19)), |
| 8232 | mkU8(10)) ); |
| 8233 | assign( a2, binop(Iop_ShlN16x8, |
| 8234 | binop(Iop_ShrN16x8, mkexpr(vA), mkU8(11)), |
| 8235 | mkU8(5)) ); |
| 8236 | assign( a3, binop(Iop_ShrN16x8, |
| 8237 | binop(Iop_ShlN16x8, mkexpr(vA), mkU8(8)), |
| 8238 | mkU8(11)) ); |
| 8239 | assign( a_tmp, binop(Iop_OrV128, mkexpr(a1), |
| 8240 | binop(Iop_OrV128, mkexpr(a2), mkexpr(a3))) ); |
| 8241 | |
| 8242 | assign( b1, binop(Iop_ShlN16x8, |
| 8243 | binop(Iop_ShrN32x4, mkexpr(vB), mkU8(19)), |
| 8244 | mkU8(10)) ); |
| 8245 | assign( b2, binop(Iop_ShlN16x8, |
| 8246 | binop(Iop_ShrN16x8, mkexpr(vB), mkU8(11)), |
| 8247 | mkU8(5)) ); |
| 8248 | assign( b3, binop(Iop_ShrN16x8, |
| 8249 | binop(Iop_ShlN16x8, mkexpr(vB), mkU8(8)), |
| 8250 | mkU8(11)) ); |
| 8251 | assign( b_tmp, binop(Iop_OrV128, mkexpr(b1), |
| 8252 | binop(Iop_OrV128, mkexpr(b2), mkexpr(b3))) ); |
| 8253 | |
sewardj | 1bee561 | 2005-11-10 18:10:58 +0000 | [diff] [blame] | 8254 | putVReg( vD_addr, binop(Iop_Narrow32x4, |
cerion | 3c05279 | 2005-09-16 07:13:44 +0000 | [diff] [blame] | 8255 | mkexpr(a_tmp), mkexpr(b_tmp)) ); |
| 8256 | return True; |
| 8257 | } |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 8258 | |
| 8259 | default: |
| 8260 | break; // Fall through... |
| 8261 | } |
| 8262 | |
| 8263 | |
| 8264 | if (vA_addr != 0) { |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 8265 | vex_printf("dis_av_pack(ppc)(vA_addr)\n"); |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 8266 | return False; |
| 8267 | } |
| 8268 | |
sewardj | 197bd17 | 2005-10-12 11:34:33 +0000 | [diff] [blame] | 8269 | signs = newTemp(Ity_V128); |
| 8270 | zeros = newTemp(Ity_V128); |
cerion | 3c05279 | 2005-09-16 07:13:44 +0000 | [diff] [blame] | 8271 | assign( zeros, unop(Iop_Dup32x4, mkU32(0)) ); |
| 8272 | |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 8273 | switch (opc2) { |
| 8274 | /* Unpacking */ |
cerion | 3c05279 | 2005-09-16 07:13:44 +0000 | [diff] [blame] | 8275 | case 0x20E: { // vupkhsb (Unpack High Signed B, AV p277) |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 8276 | DIP("vupkhsb v%d,v%d\n", vD_addr, vB_addr); |
cerion | 3c05279 | 2005-09-16 07:13:44 +0000 | [diff] [blame] | 8277 | assign( signs, binop(Iop_CmpGT8Sx16, mkexpr(zeros), mkexpr(vB)) ); |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 8278 | putVReg( vD_addr, |
| 8279 | binop(Iop_InterleaveHI8x16, mkexpr(signs), mkexpr(vB)) ); |
cerion | 3c05279 | 2005-09-16 07:13:44 +0000 | [diff] [blame] | 8280 | break; |
| 8281 | } |
| 8282 | case 0x24E: { // vupkhsh (Unpack High Signed HW, AV p278) |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 8283 | DIP("vupkhsh v%d,v%d\n", vD_addr, vB_addr); |
cerion | 3c05279 | 2005-09-16 07:13:44 +0000 | [diff] [blame] | 8284 | assign( signs, binop(Iop_CmpGT16Sx8, mkexpr(zeros), mkexpr(vB)) ); |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 8285 | putVReg( vD_addr, |
| 8286 | binop(Iop_InterleaveHI16x8, mkexpr(signs), mkexpr(vB)) ); |
cerion | 3c05279 | 2005-09-16 07:13:44 +0000 | [diff] [blame] | 8287 | break; |
| 8288 | } |
| 8289 | case 0x28E: { // vupklsb (Unpack Low Signed B, AV p280) |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 8290 | DIP("vupklsb v%d,v%d\n", vD_addr, vB_addr); |
cerion | 3c05279 | 2005-09-16 07:13:44 +0000 | [diff] [blame] | 8291 | assign( signs, binop(Iop_CmpGT8Sx16, mkexpr(zeros), mkexpr(vB)) ); |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 8292 | putVReg( vD_addr, |
| 8293 | binop(Iop_InterleaveLO8x16, mkexpr(signs), mkexpr(vB)) ); |
cerion | 3c05279 | 2005-09-16 07:13:44 +0000 | [diff] [blame] | 8294 | break; |
| 8295 | } |
| 8296 | case 0x2CE: { // vupklsh (Unpack Low Signed HW, AV p281) |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 8297 | DIP("vupklsh v%d,v%d\n", vD_addr, vB_addr); |
cerion | 3c05279 | 2005-09-16 07:13:44 +0000 | [diff] [blame] | 8298 | assign( signs, binop(Iop_CmpGT16Sx8, mkexpr(zeros), mkexpr(vB)) ); |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 8299 | putVReg( vD_addr, |
| 8300 | binop(Iop_InterleaveLO16x8, mkexpr(signs), mkexpr(vB)) ); |
cerion | 3c05279 | 2005-09-16 07:13:44 +0000 | [diff] [blame] | 8301 | break; |
| 8302 | } |
| 8303 | case 0x34E: { // vupkhpx (Unpack High Pixel16, AV p276) |
cerion | 3c05279 | 2005-09-16 07:13:44 +0000 | [diff] [blame] | 8304 | /* CAB: Worth a new primop? */ |
| 8305 | /* Using shifts to isolate pixel elements, then expanding them */ |
| 8306 | IRTemp z0 = newTemp(Ity_V128); |
| 8307 | IRTemp z1 = newTemp(Ity_V128); |
| 8308 | IRTemp z01 = newTemp(Ity_V128); |
| 8309 | IRTemp z2 = newTemp(Ity_V128); |
| 8310 | IRTemp z3 = newTemp(Ity_V128); |
| 8311 | IRTemp z23 = newTemp(Ity_V128); |
sewardj | 197bd17 | 2005-10-12 11:34:33 +0000 | [diff] [blame] | 8312 | DIP("vupkhpx v%d,v%d\n", vD_addr, vB_addr); |
cerion | 3c05279 | 2005-09-16 07:13:44 +0000 | [diff] [blame] | 8313 | assign( z0, binop(Iop_ShlN16x8, |
| 8314 | binop(Iop_SarN16x8, mkexpr(vB), mkU8(15)), |
| 8315 | mkU8(8)) ); |
| 8316 | assign( z1, binop(Iop_ShrN16x8, |
| 8317 | binop(Iop_ShlN16x8, mkexpr(vB), mkU8(1)), |
| 8318 | mkU8(11)) ); |
| 8319 | assign( z01, binop(Iop_InterleaveHI16x8, mkexpr(zeros), |
| 8320 | binop(Iop_OrV128, mkexpr(z0), mkexpr(z1))) ); |
| 8321 | assign( z2, binop(Iop_ShrN16x8, |
| 8322 | binop(Iop_ShlN16x8, |
| 8323 | binop(Iop_ShrN16x8, mkexpr(vB), mkU8(5)), |
| 8324 | mkU8(11)), |
| 8325 | mkU8(3)) ); |
| 8326 | assign( z3, binop(Iop_ShrN16x8, |
| 8327 | binop(Iop_ShlN16x8, mkexpr(vB), mkU8(11)), |
| 8328 | mkU8(11)) ); |
| 8329 | assign( z23, binop(Iop_InterleaveHI16x8, mkexpr(zeros), |
| 8330 | binop(Iop_OrV128, mkexpr(z2), mkexpr(z3))) ); |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 8331 | putVReg( vD_addr, |
| 8332 | binop(Iop_OrV128, |
| 8333 | binop(Iop_ShlN32x4, mkexpr(z01), mkU8(16)), |
| 8334 | mkexpr(z23)) ); |
cerion | 3c05279 | 2005-09-16 07:13:44 +0000 | [diff] [blame] | 8335 | break; |
| 8336 | } |
| 8337 | case 0x3CE: { // vupklpx (Unpack Low Pixel16, AV p279) |
cerion | 3c05279 | 2005-09-16 07:13:44 +0000 | [diff] [blame] | 8338 | /* identical to vupkhpx, except interleaving LO */ |
| 8339 | IRTemp z0 = newTemp(Ity_V128); |
| 8340 | IRTemp z1 = newTemp(Ity_V128); |
| 8341 | IRTemp z01 = newTemp(Ity_V128); |
| 8342 | IRTemp z2 = newTemp(Ity_V128); |
| 8343 | IRTemp z3 = newTemp(Ity_V128); |
| 8344 | IRTemp z23 = newTemp(Ity_V128); |
sewardj | 197bd17 | 2005-10-12 11:34:33 +0000 | [diff] [blame] | 8345 | DIP("vupklpx v%d,v%d\n", vD_addr, vB_addr); |
cerion | 3c05279 | 2005-09-16 07:13:44 +0000 | [diff] [blame] | 8346 | assign( z0, binop(Iop_ShlN16x8, |
| 8347 | binop(Iop_SarN16x8, mkexpr(vB), mkU8(15)), |
| 8348 | mkU8(8)) ); |
| 8349 | assign( z1, binop(Iop_ShrN16x8, |
| 8350 | binop(Iop_ShlN16x8, mkexpr(vB), mkU8(1)), |
| 8351 | mkU8(11)) ); |
| 8352 | assign( z01, binop(Iop_InterleaveLO16x8, mkexpr(zeros), |
| 8353 | binop(Iop_OrV128, mkexpr(z0), mkexpr(z1))) ); |
| 8354 | assign( z2, binop(Iop_ShrN16x8, |
| 8355 | binop(Iop_ShlN16x8, |
| 8356 | binop(Iop_ShrN16x8, mkexpr(vB), mkU8(5)), |
| 8357 | mkU8(11)), |
| 8358 | mkU8(3)) ); |
| 8359 | assign( z3, binop(Iop_ShrN16x8, |
| 8360 | binop(Iop_ShlN16x8, mkexpr(vB), mkU8(11)), |
| 8361 | mkU8(11)) ); |
| 8362 | assign( z23, binop(Iop_InterleaveLO16x8, mkexpr(zeros), |
| 8363 | binop(Iop_OrV128, mkexpr(z2), mkexpr(z3))) ); |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 8364 | putVReg( vD_addr, |
| 8365 | binop(Iop_OrV128, |
| 8366 | binop(Iop_ShlN32x4, mkexpr(z01), mkU8(16)), |
| 8367 | mkexpr(z23)) ); |
cerion | 3c05279 | 2005-09-16 07:13:44 +0000 | [diff] [blame] | 8368 | break; |
| 8369 | } |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 8370 | default: |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 8371 | vex_printf("dis_av_pack(ppc)(opc2)\n"); |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 8372 | return False; |
| 8373 | } |
| 8374 | return True; |
| 8375 | } |
| 8376 | |
| 8377 | |
| 8378 | /* |
| 8379 | AltiVec Floating Point Arithmetic Instructions |
| 8380 | */ |
| 8381 | static Bool dis_av_fp_arith ( UInt theInstr ) |
| 8382 | { |
cerion | 76de5cf | 2005-11-18 18:25:12 +0000 | [diff] [blame] | 8383 | /* VA-Form */ |
| 8384 | UChar opc1 = ifieldOPC(theInstr); |
| 8385 | UChar vD_addr = ifieldRegDS(theInstr); |
| 8386 | UChar vA_addr = ifieldRegA(theInstr); |
| 8387 | UChar vB_addr = ifieldRegB(theInstr); |
| 8388 | UChar vC_addr = ifieldRegC(theInstr); |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 8389 | UInt opc2=0; |
| 8390 | |
cerion | 8ea0d3e | 2005-11-14 00:44:47 +0000 | [diff] [blame] | 8391 | IRTemp vA = newTemp(Ity_V128); |
| 8392 | IRTemp vB = newTemp(Ity_V128); |
| 8393 | IRTemp vC = newTemp(Ity_V128); |
| 8394 | assign( vA, getVReg(vA_addr)); |
| 8395 | assign( vB, getVReg(vB_addr)); |
| 8396 | assign( vC, getVReg(vC_addr)); |
| 8397 | |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 8398 | if (opc1 != 0x4) { |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 8399 | vex_printf("dis_av_fp_arith(ppc)(instr)\n"); |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 8400 | return False; |
| 8401 | } |
| 8402 | |
cerion | 76de5cf | 2005-11-18 18:25:12 +0000 | [diff] [blame] | 8403 | opc2 = IFIELD( theInstr, 0, 6 ); |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 8404 | switch (opc2) { |
| 8405 | case 0x2E: // vmaddfp (Multiply Add FP, AV p177) |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 8406 | DIP("vmaddfp v%d,v%d,v%d,v%d\n", |
| 8407 | vD_addr, vA_addr, vC_addr, vB_addr); |
| 8408 | putVReg( vD_addr, |
| 8409 | binop(Iop_Add32Fx4, mkexpr(vB), |
| 8410 | binop(Iop_Mul32Fx4, mkexpr(vA), mkexpr(vC))) ); |
cerion | f3f173c | 2005-11-14 02:37:44 +0000 | [diff] [blame] | 8411 | return True; |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 8412 | |
cerion | f3f173c | 2005-11-14 02:37:44 +0000 | [diff] [blame] | 8413 | case 0x2F: { // vnmsubfp (Negative Multiply-Subtract FP, AV p215) |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 8414 | DIP("vnmsubfp v%d,v%d,v%d,v%d\n", |
| 8415 | vD_addr, vA_addr, vC_addr, vB_addr); |
| 8416 | putVReg( vD_addr, |
| 8417 | binop(Iop_Sub32Fx4, |
| 8418 | mkexpr(vB), |
| 8419 | binop(Iop_Mul32Fx4, mkexpr(vA), mkexpr(vC))) ); |
cerion | f3f173c | 2005-11-14 02:37:44 +0000 | [diff] [blame] | 8420 | return True; |
| 8421 | } |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 8422 | |
| 8423 | default: |
| 8424 | break; // Fall through... |
| 8425 | } |
| 8426 | |
cerion | 76de5cf | 2005-11-18 18:25:12 +0000 | [diff] [blame] | 8427 | opc2 = IFIELD( theInstr, 0, 11 ); |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 8428 | switch (opc2) { |
| 8429 | case 0x00A: // vaddfp (Add FP, AV p137) |
| 8430 | DIP("vaddfp v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr); |
cerion | 8ea0d3e | 2005-11-14 00:44:47 +0000 | [diff] [blame] | 8431 | putVReg( vD_addr, binop(Iop_Add32Fx4, mkexpr(vA), mkexpr(vB)) ); |
| 8432 | return True; |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 8433 | |
| 8434 | case 0x04A: // vsubfp (Subtract FP, AV p261) |
| 8435 | DIP("vsubfp v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr); |
cerion | 8ea0d3e | 2005-11-14 00:44:47 +0000 | [diff] [blame] | 8436 | putVReg( vD_addr, binop(Iop_Sub32Fx4, mkexpr(vA), mkexpr(vB)) ); |
| 8437 | return True; |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 8438 | |
| 8439 | case 0x40A: // vmaxfp (Maximum FP, AV p178) |
| 8440 | DIP("vmaxfp v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr); |
cerion | 8ea0d3e | 2005-11-14 00:44:47 +0000 | [diff] [blame] | 8441 | putVReg( vD_addr, binop(Iop_Max32Fx4, mkexpr(vA), mkexpr(vB)) ); |
| 8442 | return True; |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 8443 | |
| 8444 | case 0x44A: // vminfp (Minimum FP, AV p187) |
| 8445 | DIP("vminfp v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr); |
cerion | 8ea0d3e | 2005-11-14 00:44:47 +0000 | [diff] [blame] | 8446 | putVReg( vD_addr, binop(Iop_Min32Fx4, mkexpr(vA), mkexpr(vB)) ); |
| 8447 | return True; |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 8448 | |
| 8449 | default: |
| 8450 | break; // Fall through... |
| 8451 | } |
| 8452 | |
| 8453 | |
| 8454 | if (vA_addr != 0) { |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 8455 | vex_printf("dis_av_fp_arith(ppc)(vA_addr)\n"); |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 8456 | return False; |
| 8457 | } |
| 8458 | |
| 8459 | switch (opc2) { |
| 8460 | case 0x10A: // vrefp (Reciprocal Esimate FP, AV p228) |
| 8461 | DIP("vrefp v%d,v%d\n", vD_addr, vB_addr); |
cerion | 8ea0d3e | 2005-11-14 00:44:47 +0000 | [diff] [blame] | 8462 | putVReg( vD_addr, unop(Iop_Recip32Fx4, mkexpr(vB)) ); |
| 8463 | return True; |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 8464 | |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 8465 | case 0x14A: // vrsqrtefp (Reciprocal Sqrt Estimate FP, AV p237) |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 8466 | DIP("vrsqrtefp v%d,v%d\n", vD_addr, vB_addr); |
cerion | 8ea0d3e | 2005-11-14 00:44:47 +0000 | [diff] [blame] | 8467 | putVReg( vD_addr, unop(Iop_RSqrt32Fx4, mkexpr(vB)) ); |
| 8468 | return True; |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 8469 | |
| 8470 | case 0x18A: // vexptefp (2 Raised to the Exp Est FP, AV p173) |
| 8471 | DIP("vexptefp v%d,v%d\n", vD_addr, vB_addr); |
| 8472 | DIP(" => not implemented\n"); |
| 8473 | return False; |
| 8474 | |
| 8475 | case 0x1CA: // vlogefp (Log2 Estimate FP, AV p175) |
| 8476 | DIP("vlogefp v%d,v%d\n", vD_addr, vB_addr); |
| 8477 | DIP(" => not implemented\n"); |
| 8478 | return False; |
| 8479 | |
| 8480 | default: |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 8481 | vex_printf("dis_av_fp_arith(ppc)(opc2=0x%x)\n",opc2); |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 8482 | return False; |
| 8483 | } |
| 8484 | return True; |
| 8485 | } |
| 8486 | |
| 8487 | /* |
| 8488 | AltiVec Floating Point Compare Instructions |
| 8489 | */ |
| 8490 | static Bool dis_av_fp_cmp ( UInt theInstr ) |
| 8491 | { |
cerion | 76de5cf | 2005-11-18 18:25:12 +0000 | [diff] [blame] | 8492 | /* VXR-Form */ |
| 8493 | UChar opc1 = ifieldOPC(theInstr); |
| 8494 | UChar vD_addr = ifieldRegDS(theInstr); |
| 8495 | UChar vA_addr = ifieldRegA(theInstr); |
| 8496 | UChar vB_addr = ifieldRegB(theInstr); |
| 8497 | UChar flag_rC = ifieldBIT10(theInstr); |
| 8498 | UInt opc2 = IFIELD( theInstr, 0, 10 ); |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 8499 | |
cerion | 8ea0d3e | 2005-11-14 00:44:47 +0000 | [diff] [blame] | 8500 | Bool cmp_bounds = False; |
| 8501 | |
| 8502 | IRTemp vA = newTemp(Ity_V128); |
| 8503 | IRTemp vB = newTemp(Ity_V128); |
| 8504 | IRTemp vD = newTemp(Ity_V128); |
| 8505 | assign( vA, getVReg(vA_addr)); |
| 8506 | assign( vB, getVReg(vB_addr)); |
| 8507 | |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 8508 | if (opc1 != 0x4) { |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 8509 | vex_printf("dis_av_fp_cmp(ppc)(instr)\n"); |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 8510 | return False; |
| 8511 | } |
| 8512 | |
| 8513 | switch (opc2) { |
| 8514 | case 0x0C6: // vcmpeqfp (Compare Equal-to FP, AV p159) |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 8515 | DIP("vcmpeqfp%s v%d,v%d,v%d\n", (flag_rC ? ".":""), |
| 8516 | vD_addr, vA_addr, vB_addr); |
cerion | 8ea0d3e | 2005-11-14 00:44:47 +0000 | [diff] [blame] | 8517 | assign( vD, binop(Iop_CmpEQ32Fx4, mkexpr(vA), mkexpr(vB)) ); |
| 8518 | break; |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 8519 | |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 8520 | case 0x1C6: // vcmpgefp (Compare Greater-than-or-Equal-to, AV p163) |
| 8521 | DIP("vcmpgefp%s v%d,v%d,v%d\n", (flag_rC ? ".":""), |
| 8522 | vD_addr, vA_addr, vB_addr); |
cerion | 8ea0d3e | 2005-11-14 00:44:47 +0000 | [diff] [blame] | 8523 | assign( vD, binop(Iop_CmpGE32Fx4, mkexpr(vA), mkexpr(vB)) ); |
| 8524 | break; |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 8525 | |
| 8526 | case 0x2C6: // vcmpgtfp (Compare Greater-than FP, AV p164) |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 8527 | DIP("vcmpgtfp%s v%d,v%d,v%d\n", (flag_rC ? ".":""), |
| 8528 | vD_addr, vA_addr, vB_addr); |
cerion | 8ea0d3e | 2005-11-14 00:44:47 +0000 | [diff] [blame] | 8529 | assign( vD, binop(Iop_CmpGT32Fx4, mkexpr(vA), mkexpr(vB)) ); |
| 8530 | break; |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 8531 | |
cerion | 8ea0d3e | 2005-11-14 00:44:47 +0000 | [diff] [blame] | 8532 | case 0x3C6: { // vcmpbfp (Compare Bounds FP, AV p157) |
| 8533 | IRTemp gt = newTemp(Ity_V128); |
| 8534 | IRTemp lt = newTemp(Ity_V128); |
| 8535 | IRTemp zeros = newTemp(Ity_V128); |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 8536 | DIP("vcmpbfp%s v%d,v%d,v%d\n", (flag_rC ? ".":""), |
| 8537 | vD_addr, vA_addr, vB_addr); |
cerion | 8ea0d3e | 2005-11-14 00:44:47 +0000 | [diff] [blame] | 8538 | cmp_bounds = True; |
| 8539 | assign( zeros, unop(Iop_Dup32x4, mkU32(0)) ); |
| 8540 | |
| 8541 | /* Note: making use of fact that the ppc backend for compare insns |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 8542 | return zero'd lanes if either of the corresponding arg lanes is |
| 8543 | a nan. |
cerion | 8ea0d3e | 2005-11-14 00:44:47 +0000 | [diff] [blame] | 8544 | |
| 8545 | Perhaps better to have an irop Iop_isNan32Fx4, but then we'd |
| 8546 | need this for the other compares too (vcmpeqfp etc)... |
| 8547 | Better still, tighten down the spec for compare irops. |
| 8548 | */ |
| 8549 | assign( gt, unop(Iop_NotV128, |
| 8550 | binop(Iop_CmpLE32Fx4, mkexpr(vA), mkexpr(vB))) ); |
| 8551 | assign( lt, unop(Iop_NotV128, |
| 8552 | binop(Iop_CmpGE32Fx4, mkexpr(vA), |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 8553 | binop(Iop_Sub32Fx4, mkexpr(zeros), |
| 8554 | mkexpr(vB)))) ); |
cerion | 8ea0d3e | 2005-11-14 00:44:47 +0000 | [diff] [blame] | 8555 | |
| 8556 | // finally, just shift gt,lt to correct position |
| 8557 | assign( vD, binop(Iop_ShlN32x4, |
| 8558 | binop(Iop_OrV128, |
| 8559 | binop(Iop_AndV128, mkexpr(gt), |
| 8560 | unop(Iop_Dup32x4, mkU32(0x2))), |
| 8561 | binop(Iop_AndV128, mkexpr(lt), |
| 8562 | unop(Iop_Dup32x4, mkU32(0x1)))), |
| 8563 | mkU8(30)) ); |
| 8564 | break; |
| 8565 | } |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 8566 | |
| 8567 | default: |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 8568 | vex_printf("dis_av_fp_cmp(ppc)(opc2)\n"); |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 8569 | return False; |
| 8570 | } |
cerion | 8ea0d3e | 2005-11-14 00:44:47 +0000 | [diff] [blame] | 8571 | |
| 8572 | putVReg( vD_addr, mkexpr(vD) ); |
| 8573 | |
cerion | 76de5cf | 2005-11-18 18:25:12 +0000 | [diff] [blame] | 8574 | if (flag_rC) { |
cerion | 8ea0d3e | 2005-11-14 00:44:47 +0000 | [diff] [blame] | 8575 | set_AV_CR6( mkexpr(vD), !cmp_bounds ); |
| 8576 | } |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 8577 | return True; |
| 8578 | } |
| 8579 | |
| 8580 | /* |
| 8581 | AltiVec Floating Point Convert/Round Instructions |
| 8582 | */ |
| 8583 | static Bool dis_av_fp_convert ( UInt theInstr ) |
| 8584 | { |
cerion | 76de5cf | 2005-11-18 18:25:12 +0000 | [diff] [blame] | 8585 | /* VX-Form */ |
| 8586 | UChar opc1 = ifieldOPC(theInstr); |
| 8587 | UChar vD_addr = ifieldRegDS(theInstr); |
| 8588 | UChar UIMM_5 = ifieldRegA(theInstr); |
| 8589 | UChar vB_addr = ifieldRegB(theInstr); |
| 8590 | UInt opc2 = IFIELD( theInstr, 0, 11 ); |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 8591 | |
cerion | 76de5cf | 2005-11-18 18:25:12 +0000 | [diff] [blame] | 8592 | IRTemp vB = newTemp(Ity_V128); |
| 8593 | IRTemp vScale = newTemp(Ity_V128); |
cerion | d963eb4 | 2005-11-16 18:02:58 +0000 | [diff] [blame] | 8594 | IRTemp vInvScale = newTemp(Ity_V128); |
sewardj | 41a7b70 | 2005-11-18 22:18:23 +0000 | [diff] [blame] | 8595 | |
| 8596 | float scale, inv_scale; |
| 8597 | |
cerion | d963eb4 | 2005-11-16 18:02:58 +0000 | [diff] [blame] | 8598 | assign( vB, getVReg(vB_addr)); |
| 8599 | |
| 8600 | /* scale = 2^UIMM, cast to float, reinterpreted as uint */ |
sewardj | 41a7b70 | 2005-11-18 22:18:23 +0000 | [diff] [blame] | 8601 | scale = (float)( (unsigned int) 1<<UIMM_5 ); |
sewardj | 2ead522 | 2005-11-23 03:53:45 +0000 | [diff] [blame] | 8602 | assign( vScale, unop(Iop_Dup32x4, mkU32( float_to_bits(scale) )) ); |
sewardj | 41a7b70 | 2005-11-18 22:18:23 +0000 | [diff] [blame] | 8603 | inv_scale = 1/scale; |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 8604 | assign( vInvScale, |
| 8605 | unop(Iop_Dup32x4, mkU32( float_to_bits(inv_scale) )) ); |
cerion | d963eb4 | 2005-11-16 18:02:58 +0000 | [diff] [blame] | 8606 | |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 8607 | if (opc1 != 0x4) { |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 8608 | vex_printf("dis_av_fp_convert(ppc)(instr)\n"); |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 8609 | return False; |
| 8610 | } |
| 8611 | |
| 8612 | switch (opc2) { |
| 8613 | case 0x30A: // vcfux (Convert from Unsigned Fixed-Point W, AV p156) |
| 8614 | DIP("vcfux v%d,v%d,%d\n", vD_addr, vB_addr, UIMM_5); |
cerion | d963eb4 | 2005-11-16 18:02:58 +0000 | [diff] [blame] | 8615 | putVReg( vD_addr, binop(Iop_Mul32Fx4, |
| 8616 | unop(Iop_I32UtoFx4, mkexpr(vB)), |
| 8617 | mkexpr(vInvScale)) ); |
| 8618 | return True; |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 8619 | |
| 8620 | case 0x34A: // vcfsx (Convert from Signed Fixed-Point W, AV p155) |
| 8621 | DIP("vcfsx v%d,v%d,%d\n", vD_addr, vB_addr, UIMM_5); |
cerion | d963eb4 | 2005-11-16 18:02:58 +0000 | [diff] [blame] | 8622 | |
| 8623 | putVReg( vD_addr, binop(Iop_Mul32Fx4, |
| 8624 | unop(Iop_I32StoFx4, mkexpr(vB)), |
| 8625 | mkexpr(vInvScale)) ); |
| 8626 | return True; |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 8627 | |
| 8628 | case 0x38A: // vctuxs (Convert to Unsigned Fixed-Point W Saturate, AV p172) |
| 8629 | DIP("vctuxs v%d,v%d,%d\n", vD_addr, vB_addr, UIMM_5); |
cerion | d963eb4 | 2005-11-16 18:02:58 +0000 | [diff] [blame] | 8630 | putVReg( vD_addr, |
| 8631 | unop(Iop_QFtoI32Ux4_RZ, |
| 8632 | binop(Iop_Mul32Fx4, mkexpr(vB), mkexpr(vScale))) ); |
| 8633 | return True; |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 8634 | |
| 8635 | case 0x3CA: // vctsxs (Convert to Signed Fixed-Point W Saturate, AV p171) |
| 8636 | DIP("vctsxs v%d,v%d,%d\n", vD_addr, vB_addr, UIMM_5); |
cerion | d963eb4 | 2005-11-16 18:02:58 +0000 | [diff] [blame] | 8637 | putVReg( vD_addr, |
| 8638 | unop(Iop_QFtoI32Sx4_RZ, |
| 8639 | binop(Iop_Mul32Fx4, mkexpr(vB), mkexpr(vScale))) ); |
| 8640 | return True; |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 8641 | |
| 8642 | default: |
| 8643 | break; // Fall through... |
| 8644 | } |
| 8645 | |
| 8646 | if (UIMM_5 != 0) { |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 8647 | vex_printf("dis_av_fp_convert(ppc)(UIMM_5)\n"); |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 8648 | return False; |
| 8649 | } |
| 8650 | |
| 8651 | switch (opc2) { |
| 8652 | case 0x20A: // vrfin (Round to FP Integer Nearest, AV p231) |
| 8653 | DIP("vrfin v%d,v%d\n", vD_addr, vB_addr); |
cerion | d963eb4 | 2005-11-16 18:02:58 +0000 | [diff] [blame] | 8654 | putVReg( vD_addr, unop(Iop_RoundF32x4_RN, mkexpr(vB)) ); |
| 8655 | break; |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 8656 | |
| 8657 | case 0x24A: // vrfiz (Round to FP Integer toward zero, AV p233) |
| 8658 | DIP("vrfiz v%d,v%d\n", vD_addr, vB_addr); |
cerion | d963eb4 | 2005-11-16 18:02:58 +0000 | [diff] [blame] | 8659 | putVReg( vD_addr, unop(Iop_RoundF32x4_RZ, mkexpr(vB)) ); |
| 8660 | break; |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 8661 | |
| 8662 | case 0x28A: // vrfip (Round to FP Integer toward +inf, AV p232) |
| 8663 | DIP("vrfip v%d,v%d\n", vD_addr, vB_addr); |
cerion | d963eb4 | 2005-11-16 18:02:58 +0000 | [diff] [blame] | 8664 | putVReg( vD_addr, unop(Iop_RoundF32x4_RP, mkexpr(vB)) ); |
| 8665 | break; |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 8666 | |
| 8667 | case 0x2CA: // vrfim (Round to FP Integer toward -inf, AV p230) |
| 8668 | DIP("vrfim v%d,v%d\n", vD_addr, vB_addr); |
cerion | d963eb4 | 2005-11-16 18:02:58 +0000 | [diff] [blame] | 8669 | putVReg( vD_addr, unop(Iop_RoundF32x4_RM, mkexpr(vB)) ); |
| 8670 | break; |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 8671 | |
| 8672 | default: |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 8673 | vex_printf("dis_av_fp_convert(ppc)(opc2)\n"); |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 8674 | return False; |
| 8675 | } |
| 8676 | return True; |
| 8677 | } |
cerion | 3d870a3 | 2005-03-18 12:23:33 +0000 | [diff] [blame] | 8678 | |
| 8679 | |
cerion | 91ad536 | 2005-01-27 23:02:41 +0000 | [diff] [blame] | 8680 | |
| 8681 | |
| 8682 | |
| 8683 | |
cerion | 896a137 | 2005-01-25 12:24:25 +0000 | [diff] [blame] | 8684 | /*------------------------------------------------------------*/ |
| 8685 | /*--- Disassemble a single instruction ---*/ |
| 8686 | /*------------------------------------------------------------*/ |
| 8687 | |
| 8688 | /* Disassemble a single instruction into IR. The instruction |
sewardj | 9e6491a | 2005-07-02 19:24:10 +0000 | [diff] [blame] | 8689 | is located in host memory at &guest_code[delta]. */ |
| 8690 | |
| 8691 | static |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 8692 | DisResult disInstr_PPC_WRK ( |
sewardj | 9e6491a | 2005-07-02 19:24:10 +0000 | [diff] [blame] | 8693 | Bool put_IP, |
sewardj | c716aea | 2006-01-17 01:48:46 +0000 | [diff] [blame] | 8694 | Bool (*resteerOkFn) ( /*opaque*/void*, Addr64 ), |
| 8695 | void* callback_opaque, |
sewardj | 9e6491a | 2005-07-02 19:24:10 +0000 | [diff] [blame] | 8696 | Long delta64, |
| 8697 | VexArchInfo* archinfo |
| 8698 | ) |
cerion | 896a137 | 2005-01-25 12:24:25 +0000 | [diff] [blame] | 8699 | { |
sewardj | 9e6491a | 2005-07-02 19:24:10 +0000 | [diff] [blame] | 8700 | UChar opc1; |
| 8701 | UInt opc2; |
| 8702 | DisResult dres; |
cerion | 896a137 | 2005-01-25 12:24:25 +0000 | [diff] [blame] | 8703 | UInt theInstr; |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 8704 | IRType ty = mode64 ? Ity_I64 : Ity_I32; |
sewardj | 5117ce1 | 2006-01-27 21:20:15 +0000 | [diff] [blame] | 8705 | Bool allow_F = False; |
| 8706 | Bool allow_V = False; |
| 8707 | Bool allow_FX = False; |
| 8708 | Bool allow_GX = False; |
| 8709 | UInt hwcaps = archinfo->hwcaps; |
| 8710 | Long delta; |
cerion | 896a137 | 2005-01-25 12:24:25 +0000 | [diff] [blame] | 8711 | |
sewardj | 059601a | 2005-11-13 00:53:05 +0000 | [diff] [blame] | 8712 | /* What insn variants are we supporting today? */ |
sewardj | 5117ce1 | 2006-01-27 21:20:15 +0000 | [diff] [blame] | 8713 | if (mode64) { |
| 8714 | allow_F = True; |
| 8715 | allow_V = (0 != (hwcaps & VEX_HWCAPS_PPC64_V)); |
| 8716 | allow_FX = (0 != (hwcaps & VEX_HWCAPS_PPC64_FX)); |
| 8717 | allow_GX = (0 != (hwcaps & VEX_HWCAPS_PPC64_GX)); |
| 8718 | } else { |
| 8719 | allow_F = (0 != (hwcaps & VEX_HWCAPS_PPC32_F)); |
| 8720 | allow_V = (0 != (hwcaps & VEX_HWCAPS_PPC32_V)); |
| 8721 | allow_FX = (0 != (hwcaps & VEX_HWCAPS_PPC32_FX)); |
| 8722 | allow_GX = (0 != (hwcaps & VEX_HWCAPS_PPC32_GX)); |
| 8723 | } |
sewardj | 059601a | 2005-11-13 00:53:05 +0000 | [diff] [blame] | 8724 | |
sewardj | 9e6491a | 2005-07-02 19:24:10 +0000 | [diff] [blame] | 8725 | /* The running delta */ |
sewardj | 5117ce1 | 2006-01-27 21:20:15 +0000 | [diff] [blame] | 8726 | delta = (Long)mkSzAddr(ty, (ULong)delta64); |
sewardj | 9e6491a | 2005-07-02 19:24:10 +0000 | [diff] [blame] | 8727 | |
| 8728 | /* Set result defaults. */ |
| 8729 | dres.whatNext = Dis_Continue; |
| 8730 | dres.len = 0; |
| 8731 | dres.continueAt = 0; |
cerion | 896a137 | 2005-01-25 12:24:25 +0000 | [diff] [blame] | 8732 | |
cerion | 1515db9 | 2005-01-25 17:21:23 +0000 | [diff] [blame] | 8733 | /* At least this is simple on PPC32: insns are all 4 bytes long, and |
cerion | 896a137 | 2005-01-25 12:24:25 +0000 | [diff] [blame] | 8734 | 4-aligned. So just fish the whole thing out of memory right now |
| 8735 | and have done. */ |
cerion | cf00446 | 2005-01-31 15:24:55 +0000 | [diff] [blame] | 8736 | theInstr = getUIntBigendianly( (UChar*)(&guest_code[delta]) ); |
cerion | 896a137 | 2005-01-25 12:24:25 +0000 | [diff] [blame] | 8737 | |
sewardj | 5117ce1 | 2006-01-27 21:20:15 +0000 | [diff] [blame] | 8738 | if (0) vex_printf("insn: 0x%x\n", theInstr); |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 8739 | |
sewardj | 1eb7e6b | 2006-01-12 21:13:14 +0000 | [diff] [blame] | 8740 | DIP("\t0x%llx: ", (ULong)guest_CIA_curr_instr); |
sewardj | b51f0f4 | 2005-07-18 11:38:02 +0000 | [diff] [blame] | 8741 | |
| 8742 | /* We may be asked to update the guest CIA before going further. */ |
| 8743 | if (put_IP) |
cerion | 2831b00 | 2005-11-30 19:55:22 +0000 | [diff] [blame] | 8744 | putGST( PPC_GST_CIA, mkSzImm(ty, guest_CIA_curr_instr) ); |
cerion | 896a137 | 2005-01-25 12:24:25 +0000 | [diff] [blame] | 8745 | |
sewardj | ce02aa7 | 2006-01-12 12:27:58 +0000 | [diff] [blame] | 8746 | /* Spot "Special" instructions (see comment at top of file). */ |
sewardj | 1eb7e6b | 2006-01-12 21:13:14 +0000 | [diff] [blame] | 8747 | { |
sewardj | ce02aa7 | 2006-01-12 12:27:58 +0000 | [diff] [blame] | 8748 | UChar* code = (UChar*)(guest_code + delta); |
sewardj | 1eb7e6b | 2006-01-12 21:13:14 +0000 | [diff] [blame] | 8749 | /* Spot the 16-byte preamble: |
| 8750 | 32-bit mode: |
| 8751 | 54001800 rlwinm 0,0,3,0,0 |
| 8752 | 54006800 rlwinm 0,0,13,0,0 |
| 8753 | 5400E800 rlwinm 0,0,29,0,0 |
| 8754 | 54009800 rlwinm 0,0,19,0,0 |
| 8755 | 64-bit mode: |
| 8756 | 78001800 rotldi 0,0,3 |
| 8757 | 78006800 rotldi 0,0,13 |
| 8758 | 7800E802 rotldi 0,0,61 |
| 8759 | 78009802 rotldi 0,0,51 |
cerion | 896a137 | 2005-01-25 12:24:25 +0000 | [diff] [blame] | 8760 | */ |
sewardj | 1eb7e6b | 2006-01-12 21:13:14 +0000 | [diff] [blame] | 8761 | UInt word1 = mode64 ? 0x78001800 : 0x54001800; |
| 8762 | UInt word2 = mode64 ? 0x78006800 : 0x54006800; |
| 8763 | UInt word3 = mode64 ? 0x7800E802 : 0x5400E800; |
| 8764 | UInt word4 = mode64 ? 0x78009802 : 0x54009800; |
| 8765 | if (getUIntBigendianly(code+ 0) == word1 && |
| 8766 | getUIntBigendianly(code+ 4) == word2 && |
| 8767 | getUIntBigendianly(code+ 8) == word3 && |
| 8768 | getUIntBigendianly(code+12) == word4) { |
sewardj | ce02aa7 | 2006-01-12 12:27:58 +0000 | [diff] [blame] | 8769 | /* Got a "Special" instruction preamble. Which one is it? */ |
| 8770 | if (getUIntBigendianly(code+16) == 0x7C210B78 /* or 1,1,1 */) { |
| 8771 | /* %R3 = client_request ( %R4 ) */ |
| 8772 | DIP("r3 = client_request ( %%r4 )\n"); |
| 8773 | delta += 20; |
| 8774 | irbb->next = mkSzImm( ty, guest_CIA_bbstart + delta ); |
| 8775 | irbb->jumpkind = Ijk_ClientReq; |
| 8776 | dres.whatNext = Dis_StopHere; |
| 8777 | goto decode_success; |
| 8778 | } |
| 8779 | else |
| 8780 | if (getUIntBigendianly(code+16) == 0x7C421378 /* or 2,2,2 */) { |
| 8781 | /* %R3 = guest_NRADDR */ |
| 8782 | DIP("r3 = guest_NRADDR\n"); |
| 8783 | delta += 20; |
| 8784 | dres.len = 20; |
| 8785 | putIReg(3, IRExpr_Get( OFFB_NRADDR, ty )); |
| 8786 | goto decode_success; |
| 8787 | } |
| 8788 | else |
| 8789 | if (getUIntBigendianly(code+16) == 0x7C631B78 /* or 3,3,3 */) { |
| 8790 | /* branch-and-link-to-noredir %R11 */ |
| 8791 | DIP("branch-and-link-to-noredir r11\n"); |
| 8792 | delta += 20; |
sewardj | 1eb7e6b | 2006-01-12 21:13:14 +0000 | [diff] [blame] | 8793 | putGST( PPC_GST_LR, mkSzImm(ty, guest_CIA_bbstart + (Long)delta) ); |
sewardj | ce02aa7 | 2006-01-12 12:27:58 +0000 | [diff] [blame] | 8794 | irbb->next = getIReg(11); |
| 8795 | irbb->jumpkind = Ijk_NoRedir; |
| 8796 | dres.whatNext = Dis_StopHere; |
| 8797 | goto decode_success; |
| 8798 | } |
sewardj | 5ff11dd | 2006-01-20 14:19:25 +0000 | [diff] [blame] | 8799 | else |
| 8800 | if (mode64 |
| 8801 | && getUIntBigendianly(code+16) == 0x7C842378 /* or 4,4,4 */) { |
| 8802 | /* %R3 = guest_NRADDR_GPR2 */ |
| 8803 | DIP("r3 = guest_NRADDR_GPR2\n"); |
| 8804 | delta += 20; |
| 8805 | dres.len = 20; |
| 8806 | vassert(ty == Ity_I64); |
| 8807 | putIReg(3, IRExpr_Get( OFFB64_NRADDR_GPR2, ty )); |
| 8808 | goto decode_success; |
| 8809 | } |
sewardj | ce02aa7 | 2006-01-12 12:27:58 +0000 | [diff] [blame] | 8810 | /* We don't know what it is. Set opc1/opc2 so decode_failure |
| 8811 | can print the insn following the Special-insn preamble. */ |
| 8812 | theInstr = getUIntBigendianly(code+16); |
| 8813 | opc1 = ifieldOPC(theInstr); |
| 8814 | opc2 = ifieldOPClo10(theInstr); |
| 8815 | goto decode_failure; |
| 8816 | /*NOTREACHED*/ |
cerion | 896a137 | 2005-01-25 12:24:25 +0000 | [diff] [blame] | 8817 | } |
| 8818 | } |
| 8819 | |
cerion | 76de5cf | 2005-11-18 18:25:12 +0000 | [diff] [blame] | 8820 | opc1 = ifieldOPC(theInstr); |
sewardj | b51f0f4 | 2005-07-18 11:38:02 +0000 | [diff] [blame] | 8821 | opc2 = ifieldOPClo10(theInstr); |
cerion | 932ad94 | 2005-01-30 10:18:50 +0000 | [diff] [blame] | 8822 | |
cerion | 91ad536 | 2005-01-27 23:02:41 +0000 | [diff] [blame] | 8823 | // Note: all 'reserved' bits must be cleared, else invalid |
| 8824 | switch (opc1) { |
cerion | 896a137 | 2005-01-25 12:24:25 +0000 | [diff] [blame] | 8825 | |
cerion | e9d361a | 2005-03-04 17:35:29 +0000 | [diff] [blame] | 8826 | /* Integer Arithmetic Instructions */ |
| 8827 | case 0x0C: case 0x0D: case 0x0E: // addic, addic., addi |
| 8828 | case 0x0F: case 0x07: case 0x08: // addis, mulli, subfic |
| 8829 | if (dis_int_arith( theInstr )) goto decode_success; |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 8830 | goto decode_failure; |
cerion | 7aa4bbc | 2005-01-29 09:32:07 +0000 | [diff] [blame] | 8831 | |
cerion | e9d361a | 2005-03-04 17:35:29 +0000 | [diff] [blame] | 8832 | /* Integer Compare Instructions */ |
| 8833 | case 0x0B: case 0x0A: // cmpi, cmpli |
| 8834 | if (dis_int_cmp( theInstr )) goto decode_success; |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 8835 | goto decode_failure; |
cerion | 7aa4bbc | 2005-01-29 09:32:07 +0000 | [diff] [blame] | 8836 | |
cerion | e9d361a | 2005-03-04 17:35:29 +0000 | [diff] [blame] | 8837 | /* Integer Logical Instructions */ |
| 8838 | case 0x1C: case 0x1D: case 0x18: // andi., andis., ori |
| 8839 | case 0x19: case 0x1A: case 0x1B: // oris, xori, xoris |
| 8840 | if (dis_int_logic( theInstr )) goto decode_success; |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 8841 | goto decode_failure; |
cerion | 7aa4bbc | 2005-01-29 09:32:07 +0000 | [diff] [blame] | 8842 | |
cerion | e9d361a | 2005-03-04 17:35:29 +0000 | [diff] [blame] | 8843 | /* Integer Rotate Instructions */ |
| 8844 | case 0x14: case 0x15: case 0x17: // rlwimi, rlwinm, rlwnm |
| 8845 | if (dis_int_rot( theInstr )) goto decode_success; |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 8846 | goto decode_failure; |
cerion | 645c930 | 2005-01-31 10:09:59 +0000 | [diff] [blame] | 8847 | |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 8848 | /* 64bit Integer Rotate Instructions */ |
| 8849 | case 0x1E: // rldcl, rldcr, rldic, rldicl, rldicr, rldimi |
| 8850 | if (dis_int_rot( theInstr )) goto decode_success; |
| 8851 | goto decode_failure; |
| 8852 | |
cerion | e9d361a | 2005-03-04 17:35:29 +0000 | [diff] [blame] | 8853 | /* Integer Load Instructions */ |
| 8854 | case 0x22: case 0x23: case 0x2A: // lbz, lbzu, lha |
| 8855 | case 0x2B: case 0x28: case 0x29: // lhau, lhz, lhzu |
| 8856 | case 0x20: case 0x21: // lwz, lwzu |
| 8857 | if (dis_int_load( theInstr )) goto decode_success; |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 8858 | goto decode_failure; |
cerion | 645c930 | 2005-01-31 10:09:59 +0000 | [diff] [blame] | 8859 | |
cerion | e9d361a | 2005-03-04 17:35:29 +0000 | [diff] [blame] | 8860 | /* Integer Store Instructions */ |
| 8861 | case 0x26: case 0x27: case 0x2C: // stb, stbu, sth |
| 8862 | case 0x2D: case 0x24: case 0x25: // sthu, stw, stwu |
| 8863 | if (dis_int_store( theInstr )) goto decode_success; |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 8864 | goto decode_failure; |
cerion | d23be4e | 2005-01-31 07:23:07 +0000 | [diff] [blame] | 8865 | |
sewardj | 7787af4 | 2005-08-04 18:32:19 +0000 | [diff] [blame] | 8866 | /* Integer Load and Store Multiple Instructions */ |
| 8867 | case 0x2E: case 0x2F: // lmw, stmw |
| 8868 | if (dis_int_ldst_mult( theInstr )) goto decode_success; |
| 8869 | goto decode_failure; |
cerion | 645c930 | 2005-01-31 10:09:59 +0000 | [diff] [blame] | 8870 | |
cerion | e9d361a | 2005-03-04 17:35:29 +0000 | [diff] [blame] | 8871 | /* Branch Instructions */ |
| 8872 | case 0x12: case 0x10: // b, bc |
sewardj | c716aea | 2006-01-17 01:48:46 +0000 | [diff] [blame] | 8873 | if (dis_branch(theInstr, &dres, resteerOkFn, callback_opaque)) |
| 8874 | goto decode_success; |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 8875 | goto decode_failure; |
cerion | 896a137 | 2005-01-25 12:24:25 +0000 | [diff] [blame] | 8876 | |
cerion | e9d361a | 2005-03-04 17:35:29 +0000 | [diff] [blame] | 8877 | /* System Linkage Instructions */ |
cerion | 8c3adda | 2005-01-31 11:54:05 +0000 | [diff] [blame] | 8878 | case 0x11: // sc |
sewardj | 9e6491a | 2005-07-02 19:24:10 +0000 | [diff] [blame] | 8879 | if (dis_syslink(theInstr, &dres)) goto decode_success; |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 8880 | goto decode_failure; |
cerion | 26d07b2 | 2005-02-02 17:13:28 +0000 | [diff] [blame] | 8881 | |
sewardj | 334870d | 2006-02-07 16:42:39 +0000 | [diff] [blame] | 8882 | /* Trap Instructions */ |
| 8883 | case 0x02: case 0x03: // tdi, twi |
| 8884 | if (dis_trapi(theInstr, &dres)) goto decode_success; |
| 8885 | goto decode_failure; |
cerion | 8c3adda | 2005-01-31 11:54:05 +0000 | [diff] [blame] | 8886 | |
cerion | 3d870a3 | 2005-03-18 12:23:33 +0000 | [diff] [blame] | 8887 | /* Floating Point Load Instructions */ |
cerion | 094d139 | 2005-06-20 13:45:57 +0000 | [diff] [blame] | 8888 | case 0x30: case 0x31: case 0x32: // lfs, lfsu, lfd |
| 8889 | case 0x33: // lfdu |
sewardj | 5117ce1 | 2006-01-27 21:20:15 +0000 | [diff] [blame] | 8890 | if (!allow_F) goto decode_noF; |
cerion | 3d870a3 | 2005-03-18 12:23:33 +0000 | [diff] [blame] | 8891 | if (dis_fp_load( theInstr )) goto decode_success; |
cerion | e9d361a | 2005-03-04 17:35:29 +0000 | [diff] [blame] | 8892 | goto decode_failure; |
cerion | 995bc36 | 2005-02-03 11:03:31 +0000 | [diff] [blame] | 8893 | |
cerion | 3d870a3 | 2005-03-18 12:23:33 +0000 | [diff] [blame] | 8894 | /* Floating Point Store Instructions */ |
| 8895 | case 0x34: case 0x35: case 0x36: // stfsx, stfsux, stfdx |
| 8896 | case 0x37: // stfdux |
sewardj | 5117ce1 | 2006-01-27 21:20:15 +0000 | [diff] [blame] | 8897 | if (!allow_F) goto decode_noF; |
cerion | 3d870a3 | 2005-03-18 12:23:33 +0000 | [diff] [blame] | 8898 | if (dis_fp_store( theInstr )) goto decode_success; |
| 8899 | goto decode_failure; |
| 8900 | |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 8901 | /* 64bit Integer Loads */ |
| 8902 | case 0x3A: // ld, ldu, lwa |
| 8903 | if (!mode64) goto decode_failure; |
| 8904 | if (dis_int_load( theInstr )) goto decode_success; |
| 8905 | goto decode_failure; |
| 8906 | |
sewardj | e14bb9f | 2005-07-22 09:39:02 +0000 | [diff] [blame] | 8907 | case 0x3B: |
sewardj | 5117ce1 | 2006-01-27 21:20:15 +0000 | [diff] [blame] | 8908 | if (!allow_F) goto decode_noF; |
cerion | 76de5cf | 2005-11-18 18:25:12 +0000 | [diff] [blame] | 8909 | opc2 = IFIELD(theInstr, 1, 5); |
sewardj | e14bb9f | 2005-07-22 09:39:02 +0000 | [diff] [blame] | 8910 | switch (opc2) { |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 8911 | /* Floating Point Arith Instructions */ |
| 8912 | case 0x12: case 0x14: case 0x15: // fdivs, fsubs, fadds |
sewardj | 5117ce1 | 2006-01-27 21:20:15 +0000 | [diff] [blame] | 8913 | case 0x19: // fmuls |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 8914 | if (dis_fp_arith(theInstr)) goto decode_success; |
| 8915 | goto decode_failure; |
sewardj | 5117ce1 | 2006-01-27 21:20:15 +0000 | [diff] [blame] | 8916 | case 0x16: // fsqrts |
| 8917 | if (!allow_FX) goto decode_noFX; |
| 8918 | if (dis_fp_arith(theInstr)) goto decode_success; |
| 8919 | goto decode_failure; |
| 8920 | case 0x18: // fres |
| 8921 | if (!allow_GX) goto decode_noGX; |
| 8922 | if (dis_fp_arith(theInstr)) goto decode_success; |
| 8923 | goto decode_failure; |
| 8924 | |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 8925 | /* Floating Point Mult-Add Instructions */ |
| 8926 | case 0x1C: case 0x1D: case 0x1E: // fmsubs, fmadds, fnmsubs |
| 8927 | case 0x1F: // fnmadds |
| 8928 | if (dis_fp_multadd(theInstr)) goto decode_success; |
| 8929 | goto decode_failure; |
sewardj | 79fd33f | 2006-01-29 17:07:57 +0000 | [diff] [blame] | 8930 | |
| 8931 | case 0x1A: // frsqrtes |
| 8932 | if (!allow_GX) goto decode_noGX; |
| 8933 | if (dis_fp_arith(theInstr)) goto decode_success; |
| 8934 | goto decode_failure; |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 8935 | |
| 8936 | default: |
| 8937 | goto decode_failure; |
sewardj | e14bb9f | 2005-07-22 09:39:02 +0000 | [diff] [blame] | 8938 | } |
| 8939 | break; |
cerion | 3d870a3 | 2005-03-18 12:23:33 +0000 | [diff] [blame] | 8940 | |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 8941 | /* 64bit Integer Stores */ |
| 8942 | case 0x3E: // std, stdu |
| 8943 | if (!mode64) goto decode_failure; |
| 8944 | if (dis_int_store( theInstr )) goto decode_success; |
| 8945 | goto decode_failure; |
| 8946 | |
cerion | 3d870a3 | 2005-03-18 12:23:33 +0000 | [diff] [blame] | 8947 | case 0x3F: |
sewardj | 5117ce1 | 2006-01-27 21:20:15 +0000 | [diff] [blame] | 8948 | if (!allow_F) goto decode_noF; |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 8949 | /* Instrs using opc[1:5] never overlap instrs using opc[1:10], |
cerion | 3d870a3 | 2005-03-18 12:23:33 +0000 | [diff] [blame] | 8950 | so we can simply fall through the first switch statement */ |
| 8951 | |
cerion | 76de5cf | 2005-11-18 18:25:12 +0000 | [diff] [blame] | 8952 | opc2 = IFIELD(theInstr, 1, 5); |
cerion | 3d870a3 | 2005-03-18 12:23:33 +0000 | [diff] [blame] | 8953 | switch (opc2) { |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 8954 | /* Floating Point Arith Instructions */ |
sewardj | 5117ce1 | 2006-01-27 21:20:15 +0000 | [diff] [blame] | 8955 | case 0x12: case 0x14: case 0x15: // fdiv, fsub, fadd |
| 8956 | case 0x19: // fmul |
| 8957 | if (dis_fp_arith(theInstr)) goto decode_success; |
| 8958 | goto decode_failure; |
| 8959 | case 0x16: // fsqrt |
| 8960 | if (!allow_FX) goto decode_noFX; |
| 8961 | if (dis_fp_arith(theInstr)) goto decode_success; |
| 8962 | goto decode_failure; |
| 8963 | case 0x17: case 0x1A: // fsel, frsqrte |
| 8964 | if (!allow_GX) goto decode_noGX; |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 8965 | if (dis_fp_arith(theInstr)) goto decode_success; |
| 8966 | goto decode_failure; |
sewardj | e14bb9f | 2005-07-22 09:39:02 +0000 | [diff] [blame] | 8967 | |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 8968 | /* Floating Point Mult-Add Instructions */ |
| 8969 | case 0x1C: case 0x1D: case 0x1E: // fmsub, fmadd, fnmsub |
| 8970 | case 0x1F: // fnmadd |
| 8971 | if (dis_fp_multadd(theInstr)) goto decode_success; |
| 8972 | goto decode_failure; |
sewardj | 79fd33f | 2006-01-29 17:07:57 +0000 | [diff] [blame] | 8973 | |
| 8974 | case 0x18: // fre |
| 8975 | if (!allow_GX) goto decode_noGX; |
| 8976 | if (dis_fp_arith(theInstr)) goto decode_success; |
| 8977 | goto decode_failure; |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 8978 | |
| 8979 | default: |
| 8980 | break; // Fall through |
cerion | 3d870a3 | 2005-03-18 12:23:33 +0000 | [diff] [blame] | 8981 | } |
| 8982 | |
cerion | 76de5cf | 2005-11-18 18:25:12 +0000 | [diff] [blame] | 8983 | opc2 = IFIELD(theInstr, 1, 10); |
sewardj | e14bb9f | 2005-07-22 09:39:02 +0000 | [diff] [blame] | 8984 | switch (opc2) { |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 8985 | /* Floating Point Compare Instructions */ |
| 8986 | case 0x000: // fcmpu |
| 8987 | case 0x020: // fcmpo |
| 8988 | if (dis_fp_cmp(theInstr)) goto decode_success; |
| 8989 | goto decode_failure; |
cerion | 2831b00 | 2005-11-30 19:55:22 +0000 | [diff] [blame] | 8990 | |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 8991 | /* Floating Point Rounding/Conversion Instructions */ |
| 8992 | case 0x00C: // frsp |
| 8993 | case 0x00E: // fctiw |
| 8994 | case 0x00F: // fctiwz |
sewardj | 6be6723 | 2006-01-24 19:00:05 +0000 | [diff] [blame] | 8995 | case 0x32E: // fctid |
| 8996 | case 0x32F: // fctidz |
| 8997 | case 0x34E: // fcfid |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 8998 | if (dis_fp_round(theInstr)) goto decode_success; |
| 8999 | goto decode_failure; |
| 9000 | |
| 9001 | /* Floating Point Move Instructions */ |
| 9002 | case 0x028: // fneg |
| 9003 | case 0x048: // fmr |
| 9004 | case 0x088: // fnabs |
| 9005 | case 0x108: // fabs |
| 9006 | if (dis_fp_move( theInstr )) goto decode_success; |
| 9007 | goto decode_failure; |
sewardj | e14bb9f | 2005-07-22 09:39:02 +0000 | [diff] [blame] | 9008 | |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 9009 | /* Floating Point Status/Control Register Instructions */ |
cerion | 3ea49ee | 2006-01-04 10:53:00 +0000 | [diff] [blame] | 9010 | case 0x026: // mtfsb1 |
sewardj | 496b88f | 2006-10-04 17:46:11 +0000 | [diff] [blame^] | 9011 | case 0x040: // mcrfs |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 9012 | case 0x046: // mtfsb0 |
| 9013 | case 0x086: // mtfsfi |
| 9014 | case 0x247: // mffs |
| 9015 | case 0x2C7: // mtfsf |
| 9016 | if (dis_fp_scr( theInstr )) goto decode_success; |
| 9017 | goto decode_failure; |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 9018 | |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 9019 | default: |
| 9020 | goto decode_failure; |
sewardj | e14bb9f | 2005-07-22 09:39:02 +0000 | [diff] [blame] | 9021 | } |
cerion | 3d870a3 | 2005-03-18 12:23:33 +0000 | [diff] [blame] | 9022 | break; |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 9023 | |
cerion | 91ad536 | 2005-01-27 23:02:41 +0000 | [diff] [blame] | 9024 | case 0x13: |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 9025 | switch (opc2) { |
cerion | 91ad536 | 2005-01-27 23:02:41 +0000 | [diff] [blame] | 9026 | |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 9027 | /* Condition Register Logical Instructions */ |
| 9028 | case 0x101: case 0x081: case 0x121: // crand, crandc, creqv |
| 9029 | case 0x0E1: case 0x021: case 0x1C1: // crnand, crnor, cror |
| 9030 | case 0x1A1: case 0x0C1: case 0x000: // crorc, crxor, mcrf |
| 9031 | if (dis_cond_logic( theInstr )) goto decode_success; |
| 9032 | goto decode_failure; |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 9033 | |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 9034 | /* Branch Instructions */ |
| 9035 | case 0x210: case 0x010: // bcctr, bclr |
sewardj | c716aea | 2006-01-17 01:48:46 +0000 | [diff] [blame] | 9036 | if (dis_branch(theInstr, &dres, resteerOkFn, callback_opaque)) |
| 9037 | goto decode_success; |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 9038 | goto decode_failure; |
| 9039 | |
| 9040 | /* Memory Synchronization Instructions */ |
| 9041 | case 0x096: // isync |
| 9042 | if (dis_memsync( theInstr )) goto decode_success; |
| 9043 | goto decode_failure; |
| 9044 | |
| 9045 | default: |
| 9046 | goto decode_failure; |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 9047 | } |
| 9048 | break; |
cerion | 91ad536 | 2005-01-27 23:02:41 +0000 | [diff] [blame] | 9049 | |
| 9050 | |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 9051 | case 0x1F: |
cerion | e9d361a | 2005-03-04 17:35:29 +0000 | [diff] [blame] | 9052 | |
| 9053 | /* For arith instns, bit10 is the OE flag (overflow enable) */ |
| 9054 | |
cerion | 76de5cf | 2005-11-18 18:25:12 +0000 | [diff] [blame] | 9055 | opc2 = IFIELD(theInstr, 1, 9); |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 9056 | switch (opc2) { |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 9057 | /* Integer Arithmetic Instructions */ |
| 9058 | case 0x10A: case 0x00A: case 0x08A: // add, addc, adde |
| 9059 | case 0x0EA: case 0x0CA: case 0x1EB: // addme, addze, divw |
| 9060 | case 0x1CB: case 0x04B: case 0x00B: // divwu, mulhw, mulhwu |
| 9061 | case 0x0EB: case 0x068: case 0x028: // mullw, neg, subf |
| 9062 | case 0x008: case 0x088: case 0x0E8: // subfc, subfe, subfme |
| 9063 | case 0x0C8: // subfze |
| 9064 | if (dis_int_arith( theInstr )) goto decode_success; |
| 9065 | goto decode_failure; |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 9066 | |
| 9067 | /* 64bit Integer Arithmetic */ |
| 9068 | case 0x009: case 0x049: case 0x0E9: // mulhdu, mulhd, mulld |
| 9069 | case 0x1C9: case 0x1E9: // divdu, divd |
| 9070 | if (!mode64) goto decode_failure; |
| 9071 | if (dis_int_arith( theInstr )) goto decode_success; |
| 9072 | goto decode_failure; |
| 9073 | |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 9074 | default: |
| 9075 | break; // Fall through... |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 9076 | } |
cerion | 91ad536 | 2005-01-27 23:02:41 +0000 | [diff] [blame] | 9077 | |
cerion | e9d361a | 2005-03-04 17:35:29 +0000 | [diff] [blame] | 9078 | /* All remaining opcodes use full 10 bits. */ |
| 9079 | |
cerion | 76de5cf | 2005-11-18 18:25:12 +0000 | [diff] [blame] | 9080 | opc2 = IFIELD(theInstr, 1, 10); |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 9081 | switch (opc2) { |
cerion | e9d361a | 2005-03-04 17:35:29 +0000 | [diff] [blame] | 9082 | /* Integer Compare Instructions */ |
| 9083 | case 0x000: case 0x020: // cmp, cmpl |
| 9084 | if (dis_int_cmp( theInstr )) goto decode_success; |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 9085 | goto decode_failure; |
cerion | 7aa4bbc | 2005-01-29 09:32:07 +0000 | [diff] [blame] | 9086 | |
cerion | e9d361a | 2005-03-04 17:35:29 +0000 | [diff] [blame] | 9087 | /* Integer Logical Instructions */ |
| 9088 | case 0x01C: case 0x03C: case 0x01A: // and, andc, cntlzw |
| 9089 | case 0x11C: case 0x3BA: case 0x39A: // eqv, extsb, extsh |
| 9090 | case 0x1DC: case 0x07C: case 0x1BC: // nand, nor, or |
| 9091 | case 0x19C: case 0x13C: // orc, xor |
| 9092 | if (dis_int_logic( theInstr )) goto decode_success; |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 9093 | goto decode_failure; |
cerion | 932ad94 | 2005-01-30 10:18:50 +0000 | [diff] [blame] | 9094 | |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 9095 | /* 64bit Integer Logical Instructions */ |
cerion | 07b07a9 | 2005-12-22 14:32:35 +0000 | [diff] [blame] | 9096 | case 0x3DA: case 0x03A: // extsw, cntlzd |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 9097 | if (!mode64) goto decode_failure; |
| 9098 | if (dis_int_logic( theInstr )) goto decode_success; |
| 9099 | goto decode_failure; |
| 9100 | |
cerion | e9d361a | 2005-03-04 17:35:29 +0000 | [diff] [blame] | 9101 | /* Integer Shift Instructions */ |
| 9102 | case 0x018: case 0x318: case 0x338: // slw, sraw, srawi |
| 9103 | case 0x218: // srw |
| 9104 | if (dis_int_shift( theInstr )) goto decode_success; |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 9105 | goto decode_failure; |
cerion | 7aa4bbc | 2005-01-29 09:32:07 +0000 | [diff] [blame] | 9106 | |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 9107 | /* 64bit Integer Shift Instructions */ |
| 9108 | case 0x01B: case 0x31A: // sld, srad |
cerion | 07b07a9 | 2005-12-22 14:32:35 +0000 | [diff] [blame] | 9109 | case 0x33A: case 0x33B: // sradi |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 9110 | case 0x21B: // srd |
| 9111 | if (!mode64) goto decode_failure; |
| 9112 | if (dis_int_shift( theInstr )) goto decode_success; |
| 9113 | goto decode_failure; |
| 9114 | |
cerion | e9d361a | 2005-03-04 17:35:29 +0000 | [diff] [blame] | 9115 | /* Integer Load Instructions */ |
| 9116 | case 0x057: case 0x077: case 0x157: // lbzx, lbzux, lhax |
| 9117 | case 0x177: case 0x117: case 0x137: // lhaux, lhzx, lhzux |
| 9118 | case 0x017: case 0x037: // lwzx, lwzux |
| 9119 | if (dis_int_load( theInstr )) goto decode_success; |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 9120 | goto decode_failure; |
cerion | 7aa4bbc | 2005-01-29 09:32:07 +0000 | [diff] [blame] | 9121 | |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 9122 | /* 64bit Integer Load Instructions */ |
| 9123 | case 0x035: case 0x015: // ldux, ldx |
| 9124 | case 0x175: case 0x155: // lwaux, lwax |
| 9125 | if (!mode64) goto decode_failure; |
| 9126 | if (dis_int_load( theInstr )) goto decode_success; |
| 9127 | goto decode_failure; |
| 9128 | |
sewardj | b51f0f4 | 2005-07-18 11:38:02 +0000 | [diff] [blame] | 9129 | /* Integer Store Instructions */ |
cerion | e9d361a | 2005-03-04 17:35:29 +0000 | [diff] [blame] | 9130 | case 0x0F7: case 0x0D7: case 0x1B7: // stbux, stbx, sthux |
| 9131 | case 0x197: case 0x0B7: case 0x097: // sthx, stwux, stwx |
| 9132 | if (dis_int_store( theInstr )) goto decode_success; |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 9133 | goto decode_failure; |
cerion | 91ad536 | 2005-01-27 23:02:41 +0000 | [diff] [blame] | 9134 | |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 9135 | /* 64bit Integer Store Instructions */ |
| 9136 | case 0x0B5: case 0x095: // stdux, stdx |
| 9137 | if (!mode64) goto decode_failure; |
| 9138 | if (dis_int_store( theInstr )) goto decode_success; |
| 9139 | goto decode_failure; |
| 9140 | |
sewardj | 602857d | 2005-09-06 09:10:09 +0000 | [diff] [blame] | 9141 | /* Integer Load and Store with Byte Reverse Instructions */ |
| 9142 | case 0x316: case 0x216: case 0x396: // lhbrx, lwbrx, sthbrx |
| 9143 | case 0x296: // stwbrx |
| 9144 | if (dis_int_ldst_rev( theInstr )) goto decode_success; |
| 9145 | goto decode_failure; |
| 9146 | |
sewardj | 87e651f | 2005-09-09 08:31:18 +0000 | [diff] [blame] | 9147 | /* Integer Load and Store String Instructions */ |
| 9148 | case 0x255: case 0x215: case 0x2D5: // lswi, lswx, stswi |
| 9149 | case 0x295: { // stswx |
| 9150 | Bool stopHere = False; |
| 9151 | Bool ok = dis_int_ldst_str( theInstr, &stopHere ); |
| 9152 | if (!ok) goto decode_failure; |
| 9153 | if (stopHere) { |
cerion | 2831b00 | 2005-11-30 19:55:22 +0000 | [diff] [blame] | 9154 | irbb->next = mkSzImm(ty, nextInsnAddr()); |
sewardj | 87e651f | 2005-09-09 08:31:18 +0000 | [diff] [blame] | 9155 | irbb->jumpkind = Ijk_Boring; |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 9156 | dres.whatNext = Dis_StopHere; |
sewardj | 87e651f | 2005-09-09 08:31:18 +0000 | [diff] [blame] | 9157 | } |
| 9158 | goto decode_success; |
| 9159 | } |
cerion | 645c930 | 2005-01-31 10:09:59 +0000 | [diff] [blame] | 9160 | |
cerion | e9d361a | 2005-03-04 17:35:29 +0000 | [diff] [blame] | 9161 | /* Memory Synchronization Instructions */ |
| 9162 | case 0x356: case 0x014: case 0x096: // eieio, lwarx, stwcx. |
| 9163 | case 0x256: // sync |
| 9164 | if (dis_memsync( theInstr )) goto decode_success; |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 9165 | goto decode_failure; |
| 9166 | |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 9167 | /* 64bit Memory Synchronization Instructions */ |
| 9168 | case 0x054: case 0x0D6: // ldarx, stdcx. |
| 9169 | if (!mode64) goto decode_failure; |
| 9170 | if (dis_memsync( theInstr )) goto decode_success; |
| 9171 | goto decode_failure; |
| 9172 | |
cerion | e9d361a | 2005-03-04 17:35:29 +0000 | [diff] [blame] | 9173 | /* Processor Control Instructions */ |
| 9174 | case 0x200: case 0x013: case 0x153: // mcrxr, mfcr, mfspr |
| 9175 | case 0x173: case 0x090: case 0x1D3: // mftb, mtcrf, mtspr |
| 9176 | if (dis_proc_ctl( theInstr )) goto decode_success; |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 9177 | goto decode_failure; |
cerion | 645c930 | 2005-01-31 10:09:59 +0000 | [diff] [blame] | 9178 | |
cerion | e9d361a | 2005-03-04 17:35:29 +0000 | [diff] [blame] | 9179 | /* Cache Management Instructions */ |
| 9180 | case 0x2F6: case 0x056: case 0x036: // dcba, dcbf, dcbst |
| 9181 | case 0x116: case 0x0F6: case 0x3F6: // dcbt, dcbtst, dcbz |
| 9182 | case 0x3D6: // icbi |
sewardj | 9e6491a | 2005-07-02 19:24:10 +0000 | [diff] [blame] | 9183 | if (dis_cache_manage( theInstr, &dres, archinfo )) |
sewardj | d94b73a | 2005-06-30 12:08:48 +0000 | [diff] [blame] | 9184 | goto decode_success; |
cerion | b85e8bb | 2005-02-16 08:54:33 +0000 | [diff] [blame] | 9185 | goto decode_failure; |
cerion | d23be4e | 2005-01-31 07:23:07 +0000 | [diff] [blame] | 9186 | |
sewardj | b51f0f4 | 2005-07-18 11:38:02 +0000 | [diff] [blame] | 9187 | //zz /* External Control Instructions */ |
| 9188 | //zz case 0x136: case 0x1B6: // eciwx, ecowx |
| 9189 | //zz DIP("external control op => not implemented\n"); |
| 9190 | //zz goto decode_failure; |
| 9191 | //zz |
| 9192 | //zz /* Trap Instructions */ |
| 9193 | //zz case 0x004: // tw |
| 9194 | //zz DIP("trap op (tw) => not implemented\n"); |
| 9195 | //zz goto decode_failure; |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 9196 | //zz case 0x044: // td |
| 9197 | //zz DIP("trap op (td) => not implemented\n"); |
| 9198 | //zz goto decode_failure; |
sewardj | e14bb9f | 2005-07-22 09:39:02 +0000 | [diff] [blame] | 9199 | |
| 9200 | /* Floating Point Load Instructions */ |
| 9201 | case 0x217: case 0x237: case 0x257: // lfsx, lfsux, lfdx |
| 9202 | case 0x277: // lfdux |
sewardj | 5117ce1 | 2006-01-27 21:20:15 +0000 | [diff] [blame] | 9203 | if (!allow_F) goto decode_noF; |
sewardj | e14bb9f | 2005-07-22 09:39:02 +0000 | [diff] [blame] | 9204 | if (dis_fp_load( theInstr )) goto decode_success; |
| 9205 | goto decode_failure; |
| 9206 | |
| 9207 | /* Floating Point Store Instructions */ |
| 9208 | case 0x297: case 0x2B7: case 0x2D7: // stfs, stfsu, stfd |
sewardj | 5117ce1 | 2006-01-27 21:20:15 +0000 | [diff] [blame] | 9209 | case 0x2F7: // stfdu, stfiwx |
| 9210 | if (!allow_F) goto decode_noF; |
sewardj | e14bb9f | 2005-07-22 09:39:02 +0000 | [diff] [blame] | 9211 | if (dis_fp_store( theInstr )) goto decode_success; |
| 9212 | goto decode_failure; |
sewardj | 5117ce1 | 2006-01-27 21:20:15 +0000 | [diff] [blame] | 9213 | case 0x3D7: // stfiwx |
| 9214 | if (!allow_F) goto decode_noF; |
| 9215 | if (!allow_GX) goto decode_noGX; |
| 9216 | if (dis_fp_store( theInstr )) goto decode_success; |
| 9217 | goto decode_failure; |
sewardj | e14bb9f | 2005-07-22 09:39:02 +0000 | [diff] [blame] | 9218 | |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 9219 | /* AltiVec instructions */ |
| 9220 | |
| 9221 | /* AV Cache Control - Data streams */ |
| 9222 | case 0x156: case 0x176: case 0x336: // dst, dstst, dss |
sewardj | 5117ce1 | 2006-01-27 21:20:15 +0000 | [diff] [blame] | 9223 | if (!allow_V) goto decode_noV; |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 9224 | if (dis_av_datastream( theInstr )) goto decode_success; |
| 9225 | goto decode_failure; |
cerion | a982c05 | 2005-06-28 17:23:09 +0000 | [diff] [blame] | 9226 | |
| 9227 | /* AV Load */ |
| 9228 | case 0x006: case 0x026: // lvsl, lvsr |
| 9229 | case 0x007: case 0x027: case 0x047: // lvebx, lvehx, lvewx |
| 9230 | case 0x067: case 0x167: // lvx, lvxl |
sewardj | 5117ce1 | 2006-01-27 21:20:15 +0000 | [diff] [blame] | 9231 | if (!allow_V) goto decode_noV; |
cerion | a982c05 | 2005-06-28 17:23:09 +0000 | [diff] [blame] | 9232 | if (dis_av_load( theInstr )) goto decode_success; |
| 9233 | goto decode_failure; |
| 9234 | |
| 9235 | /* AV Store */ |
| 9236 | case 0x087: case 0x0A7: case 0x0C7: // stvebx, stvehx, stvewx |
| 9237 | case 0x0E7: case 0x1E7: // stvx, stvxl |
sewardj | 5117ce1 | 2006-01-27 21:20:15 +0000 | [diff] [blame] | 9238 | if (!allow_V) goto decode_noV; |
cerion | a982c05 | 2005-06-28 17:23:09 +0000 | [diff] [blame] | 9239 | if (dis_av_store( theInstr )) goto decode_success; |
| 9240 | goto decode_failure; |
| 9241 | |
| 9242 | default: |
| 9243 | goto decode_failure; |
| 9244 | } |
| 9245 | break; |
| 9246 | |
| 9247 | |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 9248 | case 0x04: |
| 9249 | /* AltiVec instructions */ |
| 9250 | |
cerion | 76de5cf | 2005-11-18 18:25:12 +0000 | [diff] [blame] | 9251 | opc2 = IFIELD(theInstr, 0, 6); |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 9252 | switch (opc2) { |
| 9253 | /* AV Mult-Add, Mult-Sum */ |
| 9254 | case 0x20: case 0x21: case 0x22: // vmhaddshs, vmhraddshs, vmladduhm |
| 9255 | case 0x24: case 0x25: case 0x26: // vmsumubm, vmsummbm, vmsumuhm |
| 9256 | case 0x27: case 0x28: case 0x29: // vmsumuhs, vmsumshm, vmsumshs |
sewardj | 5117ce1 | 2006-01-27 21:20:15 +0000 | [diff] [blame] | 9257 | if (!allow_V) goto decode_noV; |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 9258 | if (dis_av_multarith( theInstr )) goto decode_success; |
| 9259 | goto decode_failure; |
| 9260 | |
| 9261 | /* AV Permutations */ |
| 9262 | case 0x2A: // vsel |
| 9263 | case 0x2B: // vperm |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 9264 | case 0x2C: // vsldoi |
sewardj | 5117ce1 | 2006-01-27 21:20:15 +0000 | [diff] [blame] | 9265 | if (!allow_V) goto decode_noV; |
cerion | 92d9d87 | 2005-09-15 21:58:50 +0000 | [diff] [blame] | 9266 | if (dis_av_permute( theInstr )) goto decode_success; |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 9267 | goto decode_failure; |
| 9268 | |
| 9269 | /* AV Floating Point Mult-Add/Sub */ |
| 9270 | case 0x2E: case 0x2F: // vmaddfp, vnmsubfp |
sewardj | 5117ce1 | 2006-01-27 21:20:15 +0000 | [diff] [blame] | 9271 | if (!allow_V) goto decode_noV; |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 9272 | if (dis_av_fp_arith( theInstr )) goto decode_success; |
| 9273 | goto decode_failure; |
| 9274 | |
| 9275 | default: |
| 9276 | break; // Fall through... |
| 9277 | } |
| 9278 | |
cerion | 76de5cf | 2005-11-18 18:25:12 +0000 | [diff] [blame] | 9279 | opc2 = IFIELD(theInstr, 0, 11); |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 9280 | switch (opc2) { |
| 9281 | /* AV Arithmetic */ |
| 9282 | case 0x180: // vaddcuw |
| 9283 | case 0x000: case 0x040: case 0x080: // vaddubm, vadduhm, vadduwm |
| 9284 | case 0x200: case 0x240: case 0x280: // vaddubs, vadduhs, vadduws |
| 9285 | case 0x300: case 0x340: case 0x380: // vaddsbs, vaddshs, vaddsws |
| 9286 | case 0x580: // vsubcuw |
| 9287 | case 0x400: case 0x440: case 0x480: // vsububm, vsubuhm, vsubuwm |
| 9288 | case 0x600: case 0x640: case 0x680: // vsububs, vsubuhs, vsubuws |
| 9289 | case 0x700: case 0x740: case 0x780: // vsubsbs, vsubshs, vsubsws |
| 9290 | case 0x402: case 0x442: case 0x482: // vavgub, vavguh, vavguw |
| 9291 | case 0x502: case 0x542: case 0x582: // vavgsb, vavgsh, vavgsw |
| 9292 | case 0x002: case 0x042: case 0x082: // vmaxub, vmaxuh, vmaxuw |
| 9293 | case 0x102: case 0x142: case 0x182: // vmaxsb, vmaxsh, vmaxsw |
| 9294 | case 0x202: case 0x242: case 0x282: // vminub, vminuh, vminuw |
| 9295 | case 0x302: case 0x342: case 0x382: // vminsb, vminsh, vminsw |
| 9296 | case 0x008: case 0x048: // vmuloub, vmulouh |
| 9297 | case 0x108: case 0x148: // vmulosb, vmulosh |
| 9298 | case 0x208: case 0x248: // vmuleub, vmuleuh |
| 9299 | case 0x308: case 0x348: // vmulesb, vmulesh |
| 9300 | case 0x608: case 0x708: case 0x648: // vsum4ubs, vsum4sbs, vsum4shs |
| 9301 | case 0x688: case 0x788: // vsum2sws, vsumsws |
sewardj | 5117ce1 | 2006-01-27 21:20:15 +0000 | [diff] [blame] | 9302 | if (!allow_V) goto decode_noV; |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 9303 | if (dis_av_arith( theInstr )) goto decode_success; |
| 9304 | goto decode_failure; |
| 9305 | |
| 9306 | /* AV Rotate, Shift */ |
| 9307 | case 0x004: case 0x044: case 0x084: // vrlb, vrlh, vrlw |
| 9308 | case 0x104: case 0x144: case 0x184: // vslb, vslh, vslw |
| 9309 | case 0x204: case 0x244: case 0x284: // vsrb, vsrh, vsrw |
| 9310 | case 0x304: case 0x344: case 0x384: // vsrab, vsrah, vsraw |
| 9311 | case 0x1C4: case 0x2C4: // vsl, vsr |
| 9312 | case 0x40C: case 0x44C: // vslo, vsro |
sewardj | 5117ce1 | 2006-01-27 21:20:15 +0000 | [diff] [blame] | 9313 | if (!allow_V) goto decode_noV; |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 9314 | if (dis_av_shift( theInstr )) goto decode_success; |
| 9315 | goto decode_failure; |
| 9316 | |
| 9317 | /* AV Logic */ |
| 9318 | case 0x404: case 0x444: case 0x484: // vand, vandc, vor |
| 9319 | case 0x4C4: case 0x504: // vxor, vnor |
sewardj | 5117ce1 | 2006-01-27 21:20:15 +0000 | [diff] [blame] | 9320 | if (!allow_V) goto decode_noV; |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 9321 | if (dis_av_logic( theInstr )) goto decode_success; |
| 9322 | goto decode_failure; |
| 9323 | |
| 9324 | /* AV Processor Control */ |
| 9325 | case 0x604: case 0x644: // mfvscr, mtvscr |
sewardj | 5117ce1 | 2006-01-27 21:20:15 +0000 | [diff] [blame] | 9326 | if (!allow_V) goto decode_noV; |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 9327 | if (dis_av_procctl( theInstr )) goto decode_success; |
| 9328 | goto decode_failure; |
| 9329 | |
| 9330 | /* AV Floating Point Arithmetic */ |
| 9331 | case 0x00A: case 0x04A: // vaddfp, vsubfp |
| 9332 | case 0x10A: case 0x14A: case 0x18A: // vrefp, vrsqrtefp, vexptefp |
| 9333 | case 0x1CA: // vlogefp |
| 9334 | case 0x40A: case 0x44A: // vmaxfp, vminfp |
sewardj | 5117ce1 | 2006-01-27 21:20:15 +0000 | [diff] [blame] | 9335 | if (!allow_V) goto decode_noV; |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 9336 | if (dis_av_fp_arith( theInstr )) goto decode_success; |
| 9337 | goto decode_failure; |
| 9338 | |
| 9339 | /* AV Floating Point Round/Convert */ |
| 9340 | case 0x20A: case 0x24A: case 0x28A: // vrfin, vrfiz, vrfip |
| 9341 | case 0x2CA: // vrfim |
| 9342 | case 0x30A: case 0x34A: case 0x38A: // vcfux, vcfsx, vctuxs |
| 9343 | case 0x3CA: // vctsxs |
sewardj | 5117ce1 | 2006-01-27 21:20:15 +0000 | [diff] [blame] | 9344 | if (!allow_V) goto decode_noV; |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 9345 | if (dis_av_fp_convert( theInstr )) goto decode_success; |
| 9346 | goto decode_failure; |
| 9347 | |
| 9348 | /* AV Merge, Splat */ |
| 9349 | case 0x00C: case 0x04C: case 0x08C: // vmrghb, vmrghh, vmrghw |
| 9350 | case 0x10C: case 0x14C: case 0x18C: // vmrglb, vmrglh, vmrglw |
| 9351 | case 0x20C: case 0x24C: case 0x28C: // vspltb, vsplth, vspltw |
| 9352 | case 0x30C: case 0x34C: case 0x38C: // vspltisb, vspltish, vspltisw |
sewardj | 5117ce1 | 2006-01-27 21:20:15 +0000 | [diff] [blame] | 9353 | if (!allow_V) goto decode_noV; |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 9354 | if (dis_av_permute( theInstr )) goto decode_success; |
| 9355 | goto decode_failure; |
| 9356 | |
| 9357 | /* AV Pack, Unpack */ |
| 9358 | case 0x00E: case 0x04E: case 0x08E: // vpkuhum, vpkuwum, vpkuhus |
| 9359 | case 0x0CE: // vpkuwus |
| 9360 | case 0x10E: case 0x14E: case 0x18E: // vpkshus, vpkswus, vpkshss |
| 9361 | case 0x1CE: // vpkswss |
| 9362 | case 0x20E: case 0x24E: case 0x28E: // vupkhsb, vupkhsh, vupklsb |
| 9363 | case 0x2CE: // vupklsh |
| 9364 | case 0x30E: case 0x34E: case 0x3CE: // vpkpx, vupkhpx, vupklpx |
sewardj | 5117ce1 | 2006-01-27 21:20:15 +0000 | [diff] [blame] | 9365 | if (!allow_V) goto decode_noV; |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 9366 | if (dis_av_pack( theInstr )) goto decode_success; |
| 9367 | goto decode_failure; |
| 9368 | |
| 9369 | default: |
| 9370 | break; // Fall through... |
| 9371 | } |
| 9372 | |
cerion | 76de5cf | 2005-11-18 18:25:12 +0000 | [diff] [blame] | 9373 | opc2 = IFIELD(theInstr, 0, 10); |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 9374 | switch (opc2) { |
| 9375 | |
| 9376 | /* AV Compare */ |
| 9377 | case 0x006: case 0x046: case 0x086: // vcmpequb, vcmpequh, vcmpequw |
| 9378 | case 0x206: case 0x246: case 0x286: // vcmpgtub, vcmpgtuh, vcmpgtuw |
| 9379 | case 0x306: case 0x346: case 0x386: // vcmpgtsb, vcmpgtsh, vcmpgtsw |
sewardj | 5117ce1 | 2006-01-27 21:20:15 +0000 | [diff] [blame] | 9380 | if (!allow_V) goto decode_noV; |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 9381 | if (dis_av_cmp( theInstr )) goto decode_success; |
| 9382 | goto decode_failure; |
| 9383 | |
| 9384 | /* AV Floating Point Compare */ |
| 9385 | case 0x0C6: case 0x1C6: case 0x2C6: // vcmpeqfp, vcmpgefp, vcmpgtfp |
| 9386 | case 0x3C6: // vcmpbfp |
sewardj | 5117ce1 | 2006-01-27 21:20:15 +0000 | [diff] [blame] | 9387 | if (!allow_V) goto decode_noV; |
cerion | 32aad40 | 2005-09-10 12:02:24 +0000 | [diff] [blame] | 9388 | if (dis_av_fp_cmp( theInstr )) goto decode_success; |
| 9389 | goto decode_failure; |
| 9390 | |
| 9391 | default: |
| 9392 | goto decode_failure; |
| 9393 | } |
| 9394 | break; |
cerion | 7aa4bbc | 2005-01-29 09:32:07 +0000 | [diff] [blame] | 9395 | |
cerion | 896a137 | 2005-01-25 12:24:25 +0000 | [diff] [blame] | 9396 | default: |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 9397 | goto decode_failure; |
| 9398 | |
sewardj | 5117ce1 | 2006-01-27 21:20:15 +0000 | [diff] [blame] | 9399 | decode_noF: |
| 9400 | vassert(!allow_F); |
| 9401 | vex_printf("disInstr(ppc): declined to decode an FP insn.\n"); |
| 9402 | goto decode_failure; |
| 9403 | decode_noV: |
| 9404 | vassert(!allow_V); |
| 9405 | vex_printf("disInstr(ppc): declined to decode an AltiVec insn.\n"); |
| 9406 | goto decode_failure; |
| 9407 | decode_noFX: |
sewardj | 7c54586 | 2006-01-27 21:52:19 +0000 | [diff] [blame] | 9408 | vassert(!allow_FX); |
sewardj | 5117ce1 | 2006-01-27 21:20:15 +0000 | [diff] [blame] | 9409 | vex_printf("disInstr(ppc): " |
sewardj | b183b85 | 2006-02-03 16:08:03 +0000 | [diff] [blame] | 9410 | "declined to decode a GeneralPurpose-Optional insn.\n"); |
sewardj | 5117ce1 | 2006-01-27 21:20:15 +0000 | [diff] [blame] | 9411 | goto decode_failure; |
| 9412 | decode_noGX: |
sewardj | 7c54586 | 2006-01-27 21:52:19 +0000 | [diff] [blame] | 9413 | vassert(!allow_GX); |
sewardj | 5117ce1 | 2006-01-27 21:20:15 +0000 | [diff] [blame] | 9414 | vex_printf("disInstr(ppc): " |
| 9415 | "declined to decode a Graphics-Optional insn.\n"); |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 9416 | goto decode_failure; |
| 9417 | |
cerion | 896a137 | 2005-01-25 12:24:25 +0000 | [diff] [blame] | 9418 | decode_failure: |
| 9419 | /* All decode failures end up here. */ |
cerion | 225a034 | 2005-09-12 20:49:09 +0000 | [diff] [blame] | 9420 | opc2 = (theInstr) & 0x7FF; |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 9421 | vex_printf("disInstr(ppc): unhandled instruction: " |
cerion | 896a137 | 2005-01-25 12:24:25 +0000 | [diff] [blame] | 9422 | "0x%x\n", theInstr); |
sewardj | c7cd214 | 2005-09-09 22:31:49 +0000 | [diff] [blame] | 9423 | vex_printf(" primary %d(0x%x), secondary %u(0x%x)\n", |
sewardj | b51f0f4 | 2005-07-18 11:38:02 +0000 | [diff] [blame] | 9424 | opc1, opc1, opc2, opc2); |
cerion | 995bc36 | 2005-02-03 11:03:31 +0000 | [diff] [blame] | 9425 | |
sewardj | 01a9e80 | 2005-02-01 20:46:00 +0000 | [diff] [blame] | 9426 | /* Tell the dispatcher that this insn cannot be decoded, and so has |
| 9427 | not been executed, and (is currently) the next to be executed. |
| 9428 | CIA should be up-to-date since it made so at the start of each |
| 9429 | insn, but nevertheless be paranoid and update it again right |
| 9430 | now. */ |
cerion | 2831b00 | 2005-11-30 19:55:22 +0000 | [diff] [blame] | 9431 | putGST( PPC_GST_CIA, mkSzImm(ty, guest_CIA_curr_instr) ); |
| 9432 | irbb->next = mkSzImm(ty, guest_CIA_curr_instr); |
sewardj | 01a9e80 | 2005-02-01 20:46:00 +0000 | [diff] [blame] | 9433 | irbb->jumpkind = Ijk_NoDecode; |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 9434 | dres.whatNext = Dis_StopHere; |
| 9435 | dres.len = 0; |
sewardj | 9e6491a | 2005-07-02 19:24:10 +0000 | [diff] [blame] | 9436 | return dres; |
cerion | 896a137 | 2005-01-25 12:24:25 +0000 | [diff] [blame] | 9437 | |
| 9438 | } /* switch (opc) for the main (primary) opcode switch. */ |
| 9439 | |
| 9440 | decode_success: |
| 9441 | /* All decode successes end up here. */ |
cerion | 896a137 | 2005-01-25 12:24:25 +0000 | [diff] [blame] | 9442 | DIP("\n"); |
| 9443 | |
sewardj | ce02aa7 | 2006-01-12 12:27:58 +0000 | [diff] [blame] | 9444 | if (dres.len == 0) { |
| 9445 | dres.len = 4; |
| 9446 | } else { |
| 9447 | vassert(dres.len == 20); |
| 9448 | } |
sewardj | 9e6491a | 2005-07-02 19:24:10 +0000 | [diff] [blame] | 9449 | return dres; |
cerion | 896a137 | 2005-01-25 12:24:25 +0000 | [diff] [blame] | 9450 | } |
| 9451 | |
| 9452 | #undef DIP |
| 9453 | #undef DIS |
| 9454 | |
sewardj | 9e6491a | 2005-07-02 19:24:10 +0000 | [diff] [blame] | 9455 | |
| 9456 | /*------------------------------------------------------------*/ |
| 9457 | /*--- Top-level fn ---*/ |
| 9458 | /*------------------------------------------------------------*/ |
| 9459 | |
| 9460 | /* Disassemble a single instruction into IR. The instruction |
| 9461 | is located in host memory at &guest_code[delta]. */ |
| 9462 | |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 9463 | DisResult disInstr_PPC ( IRBB* irbb_IN, |
| 9464 | Bool put_IP, |
sewardj | c716aea | 2006-01-17 01:48:46 +0000 | [diff] [blame] | 9465 | Bool (*resteerOkFn) ( void*, Addr64 ), |
| 9466 | void* callback_opaque, |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 9467 | UChar* guest_code_IN, |
| 9468 | Long delta, |
| 9469 | Addr64 guest_IP, |
sewardj | a5f55da | 2006-04-30 23:37:32 +0000 | [diff] [blame] | 9470 | VexArch guest_arch, |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 9471 | VexArchInfo* archinfo, |
| 9472 | Bool host_bigendian_IN ) |
sewardj | 9e6491a | 2005-07-02 19:24:10 +0000 | [diff] [blame] | 9473 | { |
sewardj | 5df65bb | 2005-11-29 14:47:04 +0000 | [diff] [blame] | 9474 | IRType ty; |
| 9475 | DisResult dres; |
sewardj | 5117ce1 | 2006-01-27 21:20:15 +0000 | [diff] [blame] | 9476 | UInt mask32, mask64; |
| 9477 | UInt hwcaps_guest = archinfo->hwcaps; |
| 9478 | |
sewardj | a5f55da | 2006-04-30 23:37:32 +0000 | [diff] [blame] | 9479 | vassert(guest_arch == VexArchPPC32 || guest_arch == VexArchPPC64); |
sewardj | 5df65bb | 2005-11-29 14:47:04 +0000 | [diff] [blame] | 9480 | |
sewardj | a5f55da | 2006-04-30 23:37:32 +0000 | [diff] [blame] | 9481 | /* global -- ick */ |
| 9482 | mode64 = guest_arch == VexArchPPC64; |
| 9483 | ty = mode64 ? Ity_I64 : Ity_I32; |
| 9484 | |
| 9485 | /* do some sanity checks */ |
sewardj | 5117ce1 | 2006-01-27 21:20:15 +0000 | [diff] [blame] | 9486 | mask32 = VEX_HWCAPS_PPC32_F | VEX_HWCAPS_PPC32_V |
| 9487 | | VEX_HWCAPS_PPC32_FX | VEX_HWCAPS_PPC32_GX; |
| 9488 | |
sewardj | 5117ce1 | 2006-01-27 21:20:15 +0000 | [diff] [blame] | 9489 | mask64 = VEX_HWCAPS_PPC64_V |
| 9490 | | VEX_HWCAPS_PPC64_FX | VEX_HWCAPS_PPC64_GX; |
| 9491 | |
sewardj | a5f55da | 2006-04-30 23:37:32 +0000 | [diff] [blame] | 9492 | if (mode64) { |
| 9493 | vassert((hwcaps_guest & mask32) == 0); |
| 9494 | } else { |
| 9495 | vassert((hwcaps_guest & mask64) == 0); |
| 9496 | } |
sewardj | 9e6491a | 2005-07-02 19:24:10 +0000 | [diff] [blame] | 9497 | |
| 9498 | /* Set globals (see top of this file) */ |
| 9499 | guest_code = guest_code_IN; |
| 9500 | irbb = irbb_IN; |
| 9501 | host_is_bigendian = host_bigendian_IN; |
cerion | d953ebb | 2005-11-29 13:27:20 +0000 | [diff] [blame] | 9502 | |
cerion | 2831b00 | 2005-11-30 19:55:22 +0000 | [diff] [blame] | 9503 | guest_CIA_curr_instr = mkSzAddr(ty, guest_IP); |
| 9504 | guest_CIA_bbstart = mkSzAddr(ty, guest_IP - delta); |
sewardj | 9e6491a | 2005-07-02 19:24:10 +0000 | [diff] [blame] | 9505 | |
sewardj | c716aea | 2006-01-17 01:48:46 +0000 | [diff] [blame] | 9506 | dres = disInstr_PPC_WRK ( put_IP, resteerOkFn, callback_opaque, |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 9507 | delta, archinfo ); |
sewardj | 9e6491a | 2005-07-02 19:24:10 +0000 | [diff] [blame] | 9508 | |
| 9509 | return dres; |
| 9510 | } |
| 9511 | |
| 9512 | |
sewardj | c808ef7 | 2005-08-18 11:50:43 +0000 | [diff] [blame] | 9513 | /*------------------------------------------------------------*/ |
| 9514 | /*--- Unused stuff ---*/ |
| 9515 | /*------------------------------------------------------------*/ |
| 9516 | |
| 9517 | ///* A potentially more memcheck-friendly implementation of Clz32, with |
| 9518 | // the boundary case Clz32(0) = 32, which is what ppc requires. */ |
| 9519 | // |
| 9520 | //static IRExpr* /* :: Ity_I32 */ verbose_Clz32 ( IRTemp arg ) |
| 9521 | //{ |
| 9522 | // /* Welcome ... to SSA R Us. */ |
| 9523 | // IRTemp n1 = newTemp(Ity_I32); |
| 9524 | // IRTemp n2 = newTemp(Ity_I32); |
| 9525 | // IRTemp n3 = newTemp(Ity_I32); |
| 9526 | // IRTemp n4 = newTemp(Ity_I32); |
| 9527 | // IRTemp n5 = newTemp(Ity_I32); |
| 9528 | // IRTemp n6 = newTemp(Ity_I32); |
| 9529 | // IRTemp n7 = newTemp(Ity_I32); |
| 9530 | // IRTemp n8 = newTemp(Ity_I32); |
| 9531 | // IRTemp n9 = newTemp(Ity_I32); |
| 9532 | // IRTemp n10 = newTemp(Ity_I32); |
| 9533 | // IRTemp n11 = newTemp(Ity_I32); |
| 9534 | // IRTemp n12 = newTemp(Ity_I32); |
| 9535 | // |
| 9536 | // /* First, propagate the most significant 1-bit into all lower |
| 9537 | // positions in the word. */ |
| 9538 | // /* unsigned int clz ( unsigned int n ) |
| 9539 | // { |
| 9540 | // n |= (n >> 1); |
| 9541 | // n |= (n >> 2); |
| 9542 | // n |= (n >> 4); |
| 9543 | // n |= (n >> 8); |
| 9544 | // n |= (n >> 16); |
| 9545 | // return bitcount(~n); |
| 9546 | // } |
| 9547 | // */ |
| 9548 | // assign(n1, mkexpr(arg)); |
| 9549 | // assign(n2, binop(Iop_Or32, mkexpr(n1), binop(Iop_Shr32, mkexpr(n1), mkU8(1)))); |
| 9550 | // assign(n3, binop(Iop_Or32, mkexpr(n2), binop(Iop_Shr32, mkexpr(n2), mkU8(2)))); |
| 9551 | // assign(n4, binop(Iop_Or32, mkexpr(n3), binop(Iop_Shr32, mkexpr(n3), mkU8(4)))); |
| 9552 | // assign(n5, binop(Iop_Or32, mkexpr(n4), binop(Iop_Shr32, mkexpr(n4), mkU8(8)))); |
| 9553 | // assign(n6, binop(Iop_Or32, mkexpr(n5), binop(Iop_Shr32, mkexpr(n5), mkU8(16)))); |
| 9554 | // /* This gives a word of the form 0---01---1. Now invert it, giving |
| 9555 | // a word of the form 1---10---0, then do a population-count idiom |
| 9556 | // (to count the 1s, which is the number of leading zeroes, or 32 |
| 9557 | // if the original word was 0. */ |
| 9558 | // assign(n7, unop(Iop_Not32, mkexpr(n6))); |
| 9559 | // |
| 9560 | // /* unsigned int bitcount ( unsigned int n ) |
| 9561 | // { |
| 9562 | // n = n - ((n >> 1) & 0x55555555); |
| 9563 | // n = (n & 0x33333333) + ((n >> 2) & 0x33333333); |
| 9564 | // n = (n + (n >> 4)) & 0x0F0F0F0F; |
| 9565 | // n = n + (n >> 8); |
| 9566 | // n = (n + (n >> 16)) & 0x3F; |
| 9567 | // return n; |
| 9568 | // } |
| 9569 | // */ |
| 9570 | // assign(n8, |
| 9571 | // binop(Iop_Sub32, |
| 9572 | // mkexpr(n7), |
| 9573 | // binop(Iop_And32, |
| 9574 | // binop(Iop_Shr32, mkexpr(n7), mkU8(1)), |
| 9575 | // mkU32(0x55555555)))); |
| 9576 | // assign(n9, |
| 9577 | // binop(Iop_Add32, |
| 9578 | // binop(Iop_And32, mkexpr(n8), mkU32(0x33333333)), |
| 9579 | // binop(Iop_And32, |
| 9580 | // binop(Iop_Shr32, mkexpr(n8), mkU8(2)), |
| 9581 | // mkU32(0x33333333)))); |
| 9582 | // assign(n10, |
| 9583 | // binop(Iop_And32, |
| 9584 | // binop(Iop_Add32, |
| 9585 | // mkexpr(n9), |
| 9586 | // binop(Iop_Shr32, mkexpr(n9), mkU8(4))), |
| 9587 | // mkU32(0x0F0F0F0F))); |
| 9588 | // assign(n11, |
| 9589 | // binop(Iop_Add32, |
| 9590 | // mkexpr(n10), |
| 9591 | // binop(Iop_Shr32, mkexpr(n10), mkU8(8)))); |
| 9592 | // assign(n12, |
| 9593 | // binop(Iop_Add32, |
| 9594 | // mkexpr(n11), |
| 9595 | // binop(Iop_Shr32, mkexpr(n11), mkU8(16)))); |
| 9596 | // return |
| 9597 | // binop(Iop_And32, mkexpr(n12), mkU32(0x3F)); |
| 9598 | //} |
| 9599 | |
cerion | 896a137 | 2005-01-25 12:24:25 +0000 | [diff] [blame] | 9600 | /*--------------------------------------------------------------------*/ |
cerion | d0eae2d | 2005-12-23 11:43:01 +0000 | [diff] [blame] | 9601 | /*--- end guest-ppc/toIR.c ---*/ |
cerion | 896a137 | 2005-01-25 12:24:25 +0000 | [diff] [blame] | 9602 | /*--------------------------------------------------------------------*/ |