sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1 | |
| 2 | /*--------------------------------------------------------------------*/ |
| 3 | /*--- The JITter proper: register allocation & code improvement ---*/ |
| 4 | /*--- vg_translate.c ---*/ |
| 5 | /*--------------------------------------------------------------------*/ |
| 6 | |
| 7 | /* |
njn | c953984 | 2002-10-02 13:26:35 +0000 | [diff] [blame] | 8 | This file is part of Valgrind, an extensible x86 protected-mode |
| 9 | emulator for monitoring program execution on x86-Unixes. |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 10 | |
nethercote | bb1c991 | 2004-01-04 16:43:23 +0000 | [diff] [blame] | 11 | Copyright (C) 2000-2004 Julian Seward |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 12 | jseward@acm.org |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 13 | |
| 14 | This program is free software; you can redistribute it and/or |
| 15 | modify it under the terms of the GNU General Public License as |
| 16 | published by the Free Software Foundation; either version 2 of the |
| 17 | License, or (at your option) any later version. |
| 18 | |
| 19 | This program is distributed in the hope that it will be useful, but |
| 20 | WITHOUT ANY WARRANTY; without even the implied warranty of |
| 21 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
| 22 | General Public License for more details. |
| 23 | |
| 24 | You should have received a copy of the GNU General Public License |
| 25 | along with this program; if not, write to the Free Software |
| 26 | Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA |
| 27 | 02111-1307, USA. |
| 28 | |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 29 | The GNU General Public License is contained in the file COPYING. |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 30 | */ |
| 31 | |
nethercote | f1e5e15 | 2004-09-01 23:58:16 +0000 | [diff] [blame] | 32 | #include "core.h" |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 33 | |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 34 | /*------------------------------------------------------------*/ |
| 35 | /*--- Renamings of frequently-used global functions. ---*/ |
| 36 | /*------------------------------------------------------------*/ |
| 37 | |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 38 | #define dis VG_(print_codegen) |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 39 | |
nethercote | bee3fd9 | 2004-08-02 15:17:43 +0000 | [diff] [blame] | 40 | /*------------------------------------------------------------*/ |
| 41 | /*--- Reg-alloc stats ---*/ |
| 42 | /*------------------------------------------------------------*/ |
| 43 | |
| 44 | static UInt n_uinstrs_prealloc; // # uinstrs input to reg-alloc |
| 45 | static UInt n_uinstrs_spill; // # uinstrs added due to spill code |
| 46 | static UInt n_translations_needing_spill; // # bbs requiring spill code |
| 47 | static UInt n_total_reg_rank; // total of register ranks over all translations |
| 48 | |
| 49 | void VG_(print_reg_alloc_stats)(void) |
| 50 | { |
| 51 | VG_(message)(Vg_DebugMsg, |
nethercote | 3a42fb8 | 2004-08-03 18:08:50 +0000 | [diff] [blame] | 52 | "reg-alloc: %d t-req-spill, %d+%d orig+spill uis,", |
nethercote | bee3fd9 | 2004-08-02 15:17:43 +0000 | [diff] [blame] | 53 | n_translations_needing_spill, |
nethercote | 3a42fb8 | 2004-08-03 18:08:50 +0000 | [diff] [blame] | 54 | n_uinstrs_prealloc, n_uinstrs_spill ); |
| 55 | VG_(message)(Vg_DebugMsg, |
| 56 | " %d total-reg-rank", |
| 57 | n_total_reg_rank ); |
nethercote | bee3fd9 | 2004-08-02 15:17:43 +0000 | [diff] [blame] | 58 | } |
sewardj | e104247 | 2002-09-30 12:33:11 +0000 | [diff] [blame] | 59 | |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 60 | /*------------------------------------------------------------*/ |
| 61 | /*--- Basics ---*/ |
| 62 | /*------------------------------------------------------------*/ |
| 63 | |
nethercote | 85cdd34 | 2004-08-01 22:36:40 +0000 | [diff] [blame] | 64 | #define VG_IS_FLAG_SUBSET(set1,set2) \ |
| 65 | (( ((FlagSet)set1) & ((FlagSet)set2) ) == ((FlagSet)set1) ) |
| 66 | |
| 67 | #define VG_UNION_FLAG_SETS(set1,set2) \ |
| 68 | ( ((FlagSet)set1) | ((FlagSet)set2) ) |
| 69 | |
nethercote | caee10d | 2004-08-03 17:39:06 +0000 | [diff] [blame] | 70 | // This one is local. |
| 71 | static UCodeBlock* alloc_UCodeBlock ( Addr orig_eip ) |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 72 | { |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 73 | UCodeBlock* cb = VG_(arena_malloc)(VG_AR_CORE, sizeof(UCodeBlock)); |
nethercote | caee10d | 2004-08-03 17:39:06 +0000 | [diff] [blame] | 74 | cb->orig_eip = orig_eip; |
| 75 | cb->used = 0; |
| 76 | cb->size = 0; |
| 77 | cb->instrs = NULL; |
| 78 | cb->nextTemp = 0; |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 79 | return cb; |
| 80 | } |
| 81 | |
nethercote | caee10d | 2004-08-03 17:39:06 +0000 | [diff] [blame] | 82 | // This one is called by tools. |
njn | 810086f | 2002-11-14 12:42:47 +0000 | [diff] [blame] | 83 | UCodeBlock* VG_(setup_UCodeBlock) ( UCodeBlock* cb_in ) |
| 84 | { |
nethercote | caee10d | 2004-08-03 17:39:06 +0000 | [diff] [blame] | 85 | UCodeBlock* cb = alloc_UCodeBlock( cb_in->orig_eip ); |
njn | 810086f | 2002-11-14 12:42:47 +0000 | [diff] [blame] | 86 | cb->nextTemp = cb_in->nextTemp; |
njn | 810086f | 2002-11-14 12:42:47 +0000 | [diff] [blame] | 87 | return cb; |
| 88 | } |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 89 | |
njn | 4ba5a79 | 2002-09-30 10:23:54 +0000 | [diff] [blame] | 90 | void VG_(free_UCodeBlock) ( UCodeBlock* cb ) |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 91 | { |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 92 | if (cb->instrs) VG_(arena_free)(VG_AR_CORE, cb->instrs); |
| 93 | VG_(arena_free)(VG_AR_CORE, cb); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 94 | } |
| 95 | |
| 96 | |
| 97 | /* Ensure there's enough space in a block to add one uinstr. */ |
daywalker | b18d253 | 2003-09-27 20:15:01 +0000 | [diff] [blame] | 98 | static |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 99 | void ensureUInstr ( UCodeBlock* cb ) |
| 100 | { |
| 101 | if (cb->used == cb->size) { |
| 102 | if (cb->instrs == NULL) { |
| 103 | vg_assert(cb->size == 0); |
| 104 | vg_assert(cb->used == 0); |
| 105 | cb->size = 8; |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 106 | cb->instrs = VG_(arena_malloc)(VG_AR_CORE, 8 * sizeof(UInstr)); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 107 | } else { |
| 108 | Int i; |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 109 | UInstr* instrs2 = VG_(arena_malloc)(VG_AR_CORE, |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 110 | 2 * sizeof(UInstr) * cb->size); |
| 111 | for (i = 0; i < cb->used; i++) |
| 112 | instrs2[i] = cb->instrs[i]; |
| 113 | cb->size *= 2; |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 114 | VG_(arena_free)(VG_AR_CORE, cb->instrs); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 115 | cb->instrs = instrs2; |
| 116 | } |
| 117 | } |
| 118 | |
| 119 | vg_assert(cb->used < cb->size); |
| 120 | } |
| 121 | |
| 122 | |
| 123 | __inline__ |
njn | 4ba5a79 | 2002-09-30 10:23:54 +0000 | [diff] [blame] | 124 | void VG_(new_NOP) ( UInstr* u ) |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 125 | { |
| 126 | u->val1 = u->val2 = u->val3 = 0; |
| 127 | u->tag1 = u->tag2 = u->tag3 = NoValue; |
| 128 | u->flags_r = u->flags_w = FlagsEmpty; |
sewardj | 2e93c50 | 2002-04-12 11:12:52 +0000 | [diff] [blame] | 129 | u->jmpkind = JmpBoring; |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 130 | u->signed_widen = u->has_ret_val = False; |
| 131 | u->regs_live_after = ALL_RREGS_LIVE; |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 132 | u->lit32 = 0; |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 133 | u->opcode = NOP; |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 134 | u->size = 0; |
| 135 | u->cond = 0; |
| 136 | u->extra4b = 0; |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 137 | u->argc = u->regparms_n = 0; |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 138 | } |
| 139 | |
| 140 | |
| 141 | /* Add an instruction to a ucode block, and return the index of the |
| 142 | instruction. */ |
| 143 | __inline__ |
njn | 4ba5a79 | 2002-09-30 10:23:54 +0000 | [diff] [blame] | 144 | void VG_(new_UInstr3) ( UCodeBlock* cb, Opcode opcode, Int sz, |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 145 | Tag tag1, UInt val1, |
| 146 | Tag tag2, UInt val2, |
| 147 | Tag tag3, UInt val3 ) |
| 148 | { |
| 149 | UInstr* ui; |
| 150 | ensureUInstr(cb); |
| 151 | ui = & cb->instrs[cb->used]; |
| 152 | cb->used++; |
njn | 4ba5a79 | 2002-09-30 10:23:54 +0000 | [diff] [blame] | 153 | VG_(new_NOP)(ui); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 154 | ui->val1 = val1; |
| 155 | ui->val2 = val2; |
| 156 | ui->val3 = val3; |
| 157 | ui->opcode = opcode; |
| 158 | ui->tag1 = tag1; |
| 159 | ui->tag2 = tag2; |
| 160 | ui->tag3 = tag3; |
| 161 | ui->size = sz; |
| 162 | if (tag1 == TempReg) vg_assert(val1 != INVALID_TEMPREG); |
| 163 | if (tag2 == TempReg) vg_assert(val2 != INVALID_TEMPREG); |
| 164 | if (tag3 == TempReg) vg_assert(val3 != INVALID_TEMPREG); |
| 165 | } |
| 166 | |
| 167 | |
| 168 | __inline__ |
njn | 4ba5a79 | 2002-09-30 10:23:54 +0000 | [diff] [blame] | 169 | void VG_(new_UInstr2) ( UCodeBlock* cb, Opcode opcode, Int sz, |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 170 | Tag tag1, UInt val1, |
| 171 | Tag tag2, UInt val2 ) |
| 172 | { |
| 173 | UInstr* ui; |
| 174 | ensureUInstr(cb); |
| 175 | ui = & cb->instrs[cb->used]; |
| 176 | cb->used++; |
njn | 4ba5a79 | 2002-09-30 10:23:54 +0000 | [diff] [blame] | 177 | VG_(new_NOP)(ui); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 178 | ui->val1 = val1; |
| 179 | ui->val2 = val2; |
| 180 | ui->opcode = opcode; |
| 181 | ui->tag1 = tag1; |
| 182 | ui->tag2 = tag2; |
| 183 | ui->size = sz; |
| 184 | if (tag1 == TempReg) vg_assert(val1 != INVALID_TEMPREG); |
| 185 | if (tag2 == TempReg) vg_assert(val2 != INVALID_TEMPREG); |
| 186 | } |
| 187 | |
| 188 | |
| 189 | __inline__ |
njn | 4ba5a79 | 2002-09-30 10:23:54 +0000 | [diff] [blame] | 190 | void VG_(new_UInstr1) ( UCodeBlock* cb, Opcode opcode, Int sz, |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 191 | Tag tag1, UInt val1 ) |
| 192 | { |
| 193 | UInstr* ui; |
| 194 | ensureUInstr(cb); |
| 195 | ui = & cb->instrs[cb->used]; |
| 196 | cb->used++; |
njn | 4ba5a79 | 2002-09-30 10:23:54 +0000 | [diff] [blame] | 197 | VG_(new_NOP)(ui); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 198 | ui->val1 = val1; |
| 199 | ui->opcode = opcode; |
| 200 | ui->tag1 = tag1; |
| 201 | ui->size = sz; |
| 202 | if (tag1 == TempReg) vg_assert(val1 != INVALID_TEMPREG); |
| 203 | } |
| 204 | |
| 205 | |
| 206 | __inline__ |
njn | 4ba5a79 | 2002-09-30 10:23:54 +0000 | [diff] [blame] | 207 | void VG_(new_UInstr0) ( UCodeBlock* cb, Opcode opcode, Int sz ) |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 208 | { |
| 209 | UInstr* ui; |
| 210 | ensureUInstr(cb); |
| 211 | ui = & cb->instrs[cb->used]; |
| 212 | cb->used++; |
njn | 4ba5a79 | 2002-09-30 10:23:54 +0000 | [diff] [blame] | 213 | VG_(new_NOP)(ui); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 214 | ui->opcode = opcode; |
| 215 | ui->size = sz; |
| 216 | } |
| 217 | |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 218 | /* Copy an instruction into the given codeblock. */ |
njn | 4f9c934 | 2002-04-29 16:03:24 +0000 | [diff] [blame] | 219 | __inline__ |
njn | 4ba5a79 | 2002-09-30 10:23:54 +0000 | [diff] [blame] | 220 | void VG_(copy_UInstr) ( UCodeBlock* cb, UInstr* instr ) |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 221 | { |
| 222 | ensureUInstr(cb); |
| 223 | cb->instrs[cb->used] = *instr; |
| 224 | cb->used++; |
| 225 | } |
| 226 | |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 227 | /* Set the lit32 field of the most recent uinsn. */ |
njn | 4ba5a79 | 2002-09-30 10:23:54 +0000 | [diff] [blame] | 228 | void VG_(set_lit_field) ( UCodeBlock* cb, UInt lit32 ) |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 229 | { |
| 230 | LAST_UINSTR(cb).lit32 = lit32; |
| 231 | } |
| 232 | |
| 233 | |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 234 | /* Set the C call info fields of the most recent uinsn. */ |
njn | 4ba5a79 | 2002-09-30 10:23:54 +0000 | [diff] [blame] | 235 | void VG_(set_ccall_fields) ( UCodeBlock* cb, Addr fn, UChar argc, UChar |
| 236 | regparms_n, Bool has_ret_val ) |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 237 | { |
| 238 | vg_assert(argc < 4); |
| 239 | vg_assert(regparms_n <= argc); |
| 240 | LAST_UINSTR(cb).lit32 = fn; |
| 241 | LAST_UINSTR(cb).argc = argc; |
| 242 | LAST_UINSTR(cb).regparms_n = regparms_n; |
| 243 | LAST_UINSTR(cb).has_ret_val = has_ret_val; |
| 244 | } |
| 245 | |
njn | 810086f | 2002-11-14 12:42:47 +0000 | [diff] [blame] | 246 | /* For the last uinsn inserted into cb, set the read, written and |
| 247 | undefined flags. Undefined flags are counted as written, but it |
| 248 | seems worthwhile to distinguish them. |
| 249 | */ |
| 250 | __inline__ |
| 251 | void VG_(set_flag_fields) ( UCodeBlock* cb, |
| 252 | FlagSet rr, FlagSet ww, FlagSet uu ) |
| 253 | { |
| 254 | FlagSet uw = VG_UNION_FLAG_SETS(ww,uu); |
| 255 | |
| 256 | vg_assert(rr == (rr & FlagsALL)); |
| 257 | vg_assert(uw == (uw & FlagsALL)); |
| 258 | LAST_UINSTR(cb).flags_r = rr; |
| 259 | LAST_UINSTR(cb).flags_w = uw; |
| 260 | } |
| 261 | |
nethercote | 911cc37 | 2004-04-18 12:23:02 +0000 | [diff] [blame] | 262 | void VG_(set_cond_field) ( UCodeBlock* cb, Condcode cond ) |
| 263 | { |
| 264 | LAST_UINSTR(cb).cond = cond; |
| 265 | } |
| 266 | |
| 267 | void VG_(set_widen_fields) ( UCodeBlock* cb, UInt szs, Bool is_signed ) |
| 268 | { |
| 269 | LAST_UINSTR(cb).extra4b = szs; |
| 270 | LAST_UINSTR(cb).signed_widen = is_signed; |
| 271 | } |
| 272 | |
njn | 810086f | 2002-11-14 12:42:47 +0000 | [diff] [blame] | 273 | |
njn | 4ba5a79 | 2002-09-30 10:23:54 +0000 | [diff] [blame] | 274 | Bool VG_(any_flag_use) ( UInstr* u ) |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 275 | { |
| 276 | return (u->flags_r != FlagsEmpty |
| 277 | || u->flags_w != FlagsEmpty); |
| 278 | } |
| 279 | |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 280 | #if 1 |
| 281 | # define BEST_ALLOC_ORDER |
| 282 | #endif |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 283 | |
| 284 | /* Convert a rank in the range 0 .. VG_MAX_REALREGS-1 into an Intel |
| 285 | register number. This effectively defines the order in which real |
| 286 | registers are allocated. %ebp is excluded since it is permanently |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 287 | reserved for pointing at VG_(baseBlock). |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 288 | |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 289 | Important! This function must correspond with the value of |
| 290 | VG_MAX_REALREGS (actually, VG_MAX_REALREGS can be reduced without |
| 291 | a problem, except the generated code will obviously be worse). |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 292 | */ |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 293 | __inline__ |
njn | 4ba5a79 | 2002-09-30 10:23:54 +0000 | [diff] [blame] | 294 | Int VG_(rank_to_realreg) ( Int rank ) |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 295 | { |
| 296 | switch (rank) { |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 297 | # ifdef BEST_ALLOC_ORDER |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 298 | /* Probably the best allocation ordering. */ |
| 299 | case 0: return R_EAX; |
| 300 | case 1: return R_EBX; |
| 301 | case 2: return R_ECX; |
| 302 | case 3: return R_EDX; |
| 303 | case 4: return R_ESI; |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 304 | case 5: return R_EDI; |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 305 | # else |
| 306 | /* Contrary; probably the worst. Helpful for debugging, tho. */ |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 307 | case 5: return R_EAX; |
| 308 | case 4: return R_EBX; |
| 309 | case 3: return R_ECX; |
| 310 | case 2: return R_EDX; |
| 311 | case 1: return R_ESI; |
| 312 | case 0: return R_EDI; |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 313 | # endif |
njn | e427a66 | 2002-10-02 11:08:25 +0000 | [diff] [blame] | 314 | default: VG_(core_panic)("VG_(rank_to_realreg)"); |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 315 | } |
| 316 | } |
| 317 | |
| 318 | /* Convert an Intel register number into a rank in the range 0 .. |
njn | 4ba5a79 | 2002-09-30 10:23:54 +0000 | [diff] [blame] | 319 | VG_MAX_REALREGS-1. See related comments for rank_to_realreg() |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 320 | above. */ |
| 321 | __inline__ |
njn | 4ba5a79 | 2002-09-30 10:23:54 +0000 | [diff] [blame] | 322 | Int VG_(realreg_to_rank) ( Int realReg ) |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 323 | { |
| 324 | switch (realReg) { |
| 325 | # ifdef BEST_ALLOC_ORDER |
| 326 | case R_EAX: return 0; |
| 327 | case R_EBX: return 1; |
| 328 | case R_ECX: return 2; |
| 329 | case R_EDX: return 3; |
| 330 | case R_ESI: return 4; |
| 331 | case R_EDI: return 5; |
| 332 | # else |
| 333 | case R_EAX: return 5; |
| 334 | case R_EBX: return 4; |
| 335 | case R_ECX: return 3; |
| 336 | case R_EDX: return 2; |
| 337 | case R_ESI: return 1; |
| 338 | case R_EDI: return 0; |
| 339 | # endif |
njn | e427a66 | 2002-10-02 11:08:25 +0000 | [diff] [blame] | 340 | default: VG_(core_panic)("VG_(realreg_to_rank)"); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 341 | } |
| 342 | } |
| 343 | |
nethercote | 0973f70 | 2004-08-03 15:49:50 +0000 | [diff] [blame] | 344 | Int VG_(get_num_instrs) ( UCodeBlock* cb ) |
| 345 | { |
| 346 | return cb->used; |
| 347 | } |
| 348 | |
| 349 | Int VG_(get_num_temps) ( UCodeBlock* cb ) |
| 350 | { |
| 351 | return cb->nextTemp; |
| 352 | } |
| 353 | |
| 354 | UInstr* VG_(get_instr) ( UCodeBlock* cb, Int i ) |
| 355 | { |
| 356 | return & cb->instrs[i]; |
| 357 | } |
| 358 | |
| 359 | UInstr* VG_(get_last_instr) ( UCodeBlock* cb ) |
| 360 | { |
| 361 | return & cb->instrs[cb->used-1]; |
| 362 | } |
| 363 | |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 364 | |
| 365 | /*------------------------------------------------------------*/ |
| 366 | /*--- Sanity checking uinstrs. ---*/ |
| 367 | /*------------------------------------------------------------*/ |
| 368 | |
nethercote | 885dd91 | 2004-08-03 23:14:00 +0000 | [diff] [blame] | 369 | // Global variables that indicate where we are in the translation of a basic |
| 370 | // block, and affect exactly how UInstrs are sanity-checked. |
| 371 | static Bool beforeRA = True; |
| 372 | static Bool beforeLiveness = True; |
| 373 | |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 374 | /* This seems as good a place as any to record some important stuff |
| 375 | about ucode semantics. |
| 376 | |
| 377 | * TempRegs are 32 bits wide. LOADs of 8/16 bit values into a |
| 378 | TempReg are defined to zero-extend the loaded value to 32 bits. |
| 379 | This is needed to make the translation of movzbl et al work |
| 380 | properly. |
| 381 | |
| 382 | * Similarly, GETs of a 8/16 bit ArchRegs are zero-extended. |
| 383 | |
| 384 | * Arithmetic on TempRegs is at the specified size. For example, |
| 385 | SUBW t1, t2 has to result in a real 16 bit x86 subtraction |
| 386 | being emitted -- not a 32 bit one. |
| 387 | |
| 388 | * On some insns we allow the cc bit to be set. If so, the |
| 389 | intention is that the simulated machine's %eflags register |
| 390 | is copied into that of the real machine before the insn, |
| 391 | and copied back again afterwards. This means that the |
| 392 | code generated for that insn must be very careful only to |
| 393 | update %eflags in the intended way. This is particularly |
| 394 | important for the routines referenced by CALL insns. |
| 395 | */ |
| 396 | |
| 397 | /* Meaning of operand kinds is as follows: |
| 398 | |
| 399 | ArchReg is a register of the simulated CPU, stored in memory, |
| 400 | in vg_m_state.m_eax .. m_edi. These values are stored |
| 401 | using the Intel register encoding. |
| 402 | |
| 403 | RealReg is a register of the real CPU. There are VG_MAX_REALREGS |
| 404 | available for allocation. As with ArchRegs, these values |
| 405 | are stored using the Intel register encoding. |
| 406 | |
| 407 | TempReg is a temporary register used to express the results of |
| 408 | disassembly. There is an unlimited supply of them -- |
| 409 | register allocation and spilling eventually assigns them |
| 410 | to RealRegs. |
| 411 | |
| 412 | SpillNo is a spill slot number. The number of required spill |
| 413 | slots is VG_MAX_PSEUDOS, in general. Only allowed |
| 414 | as the ArchReg operand of GET and PUT. |
| 415 | |
| 416 | Lit16 is a signed 16-bit literal value. |
| 417 | |
| 418 | Literal is a 32-bit literal value. Each uinstr can only hold |
| 419 | one of these. |
| 420 | |
| 421 | The disassembled code is expressed purely in terms of ArchReg, |
| 422 | TempReg and Literal operands. Eventually, register allocation |
| 423 | removes all the TempRegs, giving a result using ArchRegs, RealRegs, |
| 424 | and Literals. New x86 code can easily be synthesised from this. |
| 425 | There are carefully designed restrictions on which insns can have |
| 426 | which operands, intended to make it possible to generate x86 code |
| 427 | from the result of register allocation on the ucode efficiently and |
| 428 | without need of any further RealRegs. |
| 429 | |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 430 | Restrictions for the individual UInstrs are clear from the checks below. |
| 431 | Abbreviations: A=ArchReg S=SpillNo T=TempReg L=Literal |
| 432 | Ls=Lit16 R=RealReg N=NoValue |
sewardj | e104247 | 2002-09-30 12:33:11 +0000 | [diff] [blame] | 433 | As=ArchRegS |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 434 | |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 435 | Before register allocation, S operands should not appear anywhere. |
| 436 | After register allocation, all T operands should have been |
| 437 | converted into Rs, and S operands are allowed in GET and PUT -- |
| 438 | denoting spill saves/restores. |
| 439 | |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 440 | Before liveness analysis, save_e[acd]x fields should all be True. |
| 441 | Afterwards, they may be False. |
| 442 | |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 443 | The size field should be 0 for insns for which it is meaningless, |
| 444 | ie those which do not directly move/operate on data. |
| 445 | */ |
nethercote | 885dd91 | 2004-08-03 23:14:00 +0000 | [diff] [blame] | 446 | static Bool is_sane_UInstr ( UInstr* u ) |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 447 | { |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 448 | # define LIT0 (u->lit32 == 0) |
sewardj | b31b06d | 2003-06-13 00:26:02 +0000 | [diff] [blame] | 449 | # define LIT8 (((u->lit32) & 0xFFFFFF00) == 0) |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 450 | # define LIT1 (!(LIT0)) |
| 451 | # define LITm (u->tag1 == Literal ? True : LIT0 ) |
sewardj | 77d30a2 | 2003-10-19 08:18:52 +0000 | [diff] [blame] | 452 | # define SZ16 (u->size == 16) |
sewardj | 3d7c9c8 | 2003-03-26 21:08:13 +0000 | [diff] [blame] | 453 | # define SZ8 (u->size == 8) |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 454 | # define SZ4 (u->size == 4) |
| 455 | # define SZ2 (u->size == 2) |
| 456 | # define SZ1 (u->size == 1) |
| 457 | # define SZ0 (u->size == 0) |
| 458 | # define SZ42 (u->size == 4 || u->size == 2) |
sewardj | d797101 | 2003-04-04 00:21:58 +0000 | [diff] [blame] | 459 | # define SZ48 (u->size == 4 || u->size == 8) |
sewardj | febaa3b | 2003-05-25 01:07:34 +0000 | [diff] [blame] | 460 | # define SZ416 (u->size == 4 || u->size == 16) |
nethercote | b1affa8 | 2004-01-19 19:14:18 +0000 | [diff] [blame] | 461 | # define SZ816 (u->size == 8 || u->size == 16) |
| 462 | # define SZsse2 (u->size == 4 || u->size == 8 || u->size == 16 || u->size == 512) |
jseward | fca6018 | 2004-01-04 23:30:55 +0000 | [diff] [blame] | 463 | # define SZsse3 (u->size == 4 || u->size == 8 || u->size == 16) |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 464 | # define SZi (u->size == 4 || u->size == 2 || u->size == 1) |
| 465 | # define SZf ( u->size == 4 || u->size == 8 || u->size == 2 \ |
| 466 | || u->size == 10 || u->size == 28 || u->size == 108) |
| 467 | # define SZ4m ((u->tag1 == TempReg || u->tag1 == RealReg) \ |
nethercote | afa17ef | 2004-04-26 09:21:25 +0000 | [diff] [blame] | 468 | ? (u->size == 4) : SZi) |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 469 | |
| 470 | /* For these ones, two cases: |
| 471 | * |
| 472 | * 1. They are transliterations of the corresponding x86 instruction, in |
| 473 | * which case they should have its flags (except that redundant write |
| 474 | * flags can be annulled by the optimisation pass). |
| 475 | * |
| 476 | * 2. They are being used generally for other purposes, eg. helping with a |
| 477 | * 'rep'-prefixed instruction, in which case should have empty flags . |
| 478 | */ |
| 479 | # define emptyR (u->flags_r == FlagsEmpty) |
| 480 | # define emptyW (u->flags_w == FlagsEmpty) |
| 481 | # define CC0 (emptyR && emptyW) |
| 482 | # define CCr (u->flags_r == FlagsALL && emptyW) |
| 483 | # define CCw (emptyR && u->flags_w == FlagsALL) |
| 484 | # define CCa (emptyR && (u->flags_w == FlagsOSZACP || emptyW)) |
| 485 | # define CCc (emptyR && (u->flags_w == FlagsOC || emptyW)) |
| 486 | # define CCe (emptyR && (u->flags_w == FlagsOSZAP || emptyW)) |
| 487 | # define CCb ((u->flags_r==FlagC || emptyR) && \ |
| 488 | (u->flags_w==FlagsOSZACP || emptyW)) |
| 489 | # define CCd ((u->flags_r==FlagC || emptyR) && \ |
| 490 | (u->flags_w==FlagsOC || emptyW)) |
sewardj | c232b21 | 2002-12-10 22:24:03 +0000 | [diff] [blame] | 491 | # define CCf (CC0 || (emptyR && u->flags_w==FlagsZCP) \ |
| 492 | || (u->flags_r==FlagsZCP && emptyW)) |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 493 | # define CCg ((u->flags_r==FlagsOSZACP || emptyR) && emptyW) |
| 494 | # define CCj (u->cond==CondAlways ? CC0 : CCg) |
| 495 | |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 496 | # define TR1 (beforeRA ? (u->tag1 == TempReg) : (u->tag1 == RealReg)) |
| 497 | # define TR2 (beforeRA ? (u->tag2 == TempReg) : (u->tag2 == RealReg)) |
| 498 | # define TR3 (beforeRA ? (u->tag3 == TempReg) : (u->tag3 == RealReg)) |
| 499 | # define A1 (u->tag1 == ArchReg) |
| 500 | # define A2 (u->tag2 == ArchReg) |
| 501 | # define AS1 ((u->tag1 == ArchReg) || ((!beforeRA && (u->tag1 == SpillNo)))) |
| 502 | # define AS2 ((u->tag2 == ArchReg) || ((!beforeRA && (u->tag2 == SpillNo)))) |
| 503 | # define AS3 ((u->tag3 == ArchReg) || ((!beforeRA && (u->tag3 == SpillNo)))) |
| 504 | # define L1 (u->tag1 == Literal && u->val1 == 0) |
| 505 | # define L2 (u->tag2 == Literal && u->val2 == 0) |
| 506 | # define Ls1 (u->tag1 == Lit16) |
sewardj | febaa3b | 2003-05-25 01:07:34 +0000 | [diff] [blame] | 507 | # define Ls2 (u->tag2 == Lit16) |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 508 | # define Ls3 (u->tag3 == Lit16) |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 509 | # define TRL1 (TR1 || L1) |
| 510 | # define TRAL1 (TR1 || A1 || L1) |
jsgf | 5efa4fd | 2003-10-14 21:49:11 +0000 | [diff] [blame] | 511 | # define TRA1 (TR1 || A1) |
| 512 | # define TRA2 (TR2 || A2) |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 513 | # define N1 (u->tag1 == NoValue) |
| 514 | # define N2 (u->tag2 == NoValue) |
| 515 | # define N3 (u->tag3 == NoValue) |
sewardj | e104247 | 2002-09-30 12:33:11 +0000 | [diff] [blame] | 516 | # define Se1 (u->tag1 == ArchRegS) |
| 517 | # define Se2 (u->tag2 == ArchRegS) |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 518 | |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 519 | # define COND0 (u->cond == 0) |
| 520 | # define EXTRA4b0 (u->extra4b == 0) |
nethercote | 4a12dbd | 2004-04-16 16:16:34 +0000 | [diff] [blame] | 521 | # define EXTRA4b12 (u->extra4b == 1 || u->extra4b == 2) |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 522 | # define SG_WD0 (u->signed_widen == 0) |
| 523 | # define JMPKIND0 (u->jmpkind == 0) |
| 524 | # define CCALL0 (u->argc==0 && u->regparms_n==0 && u->has_ret_val==0 && \ |
| 525 | ( beforeLiveness \ |
| 526 | ? u->regs_live_after == ALL_RREGS_LIVE \ |
| 527 | : True )) |
| 528 | |
| 529 | # define XCONDi ( EXTRA4b0 && SG_WD0 && JMPKIND0 && CCALL0) |
nethercote | 4a12dbd | 2004-04-16 16:16:34 +0000 | [diff] [blame] | 530 | # define XLEA2 (COND0 && SG_WD0 && JMPKIND0 && CCALL0) |
| 531 | # define XWIDEN (COND0 && EXTRA4b12 && JMPKIND0 && CCALL0) |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 532 | # define XJMP ( SG_WD0 && CCALL0) |
| 533 | # define XCCALL (COND0 && EXTRA4b0 && SG_WD0 && JMPKIND0 ) |
| 534 | # define XOTHER (COND0 && EXTRA4b0 && SG_WD0 && JMPKIND0 && CCALL0) |
| 535 | |
| 536 | /* 0 or 1 Literal args per UInstr */ |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 537 | Int n_lits = 0; |
| 538 | if (u->tag1 == Literal) n_lits++; |
| 539 | if (u->tag2 == Literal) n_lits++; |
| 540 | if (u->tag3 == Literal) n_lits++; |
| 541 | if (n_lits > 1) |
| 542 | return False; |
| 543 | |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 544 | /* Fields not checked: val1, val2, val3 */ |
| 545 | |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 546 | switch (u->opcode) { |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 547 | |
| 548 | /* Fields checked: lit32 size flags_r/w tag1 tag2 tag3 (rest) */ |
sewardj | e104247 | 2002-09-30 12:33:11 +0000 | [diff] [blame] | 549 | case PUTSEG: return LIT0 && SZ2 && CC0 && TR1 && Se2 && N3 && XOTHER; |
| 550 | case GETSEG: return LIT0 && SZ2 && CC0 && Se1 && TR2 && N3 && XOTHER; |
| 551 | case USESEG: return LIT0 && SZ0 && CC0 && TR1 && TR2 && N3 && XOTHER; |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 552 | case NOP: return LIT0 && SZ0 && CC0 && N1 && N2 && N3 && XOTHER; |
sewardj | 7a5ebcf | 2002-11-13 22:42:13 +0000 | [diff] [blame] | 553 | case LOCK: return LIT0 && SZ0 && CC0 && N1 && N2 && N3 && XOTHER; |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 554 | case GETF: return LIT0 && SZ42 && CCr && TR1 && N2 && N3 && XOTHER; |
| 555 | case PUTF: return LIT0 && SZ42 && CCw && TR1 && N2 && N3 && XOTHER; |
| 556 | case GET: return LIT0 && SZi && CC0 && AS1 && TR2 && N3 && XOTHER; |
| 557 | case PUT: return LIT0 && SZi && CC0 && TR1 && AS2 && N3 && XOTHER; |
| 558 | case LOAD: |
| 559 | case STORE: return LIT0 && SZi && CC0 && TR1 && TR2 && N3 && XOTHER; |
| 560 | case MOV: return LITm && SZ4m && CC0 && TRL1 && TR2 && N3 && XOTHER; |
| 561 | case CMOV: return LIT0 && SZ4 && CCg && TR1 && TR2 && N3 && XCONDi; |
njn | 95bc386 | 2003-09-30 13:22:30 +0000 | [diff] [blame] | 562 | case WIDEN: return LIT0 && SZ42 && CC0 && TR1 && N2 && N3 && XWIDEN; |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 563 | case JMP: return LITm && SZ0 && CCj && TRL1 && N2 && N3 && XJMP; |
| 564 | case CALLM: return LIT0 && SZ0 /*any*/ && Ls1 && N2 && N3 && XOTHER; |
| 565 | case CALLM_S: |
| 566 | case CALLM_E:return LIT0 && SZ0 && CC0 && N1 && N2 && N3 && XOTHER; |
| 567 | case PUSH: |
| 568 | case POP: return LIT0 && SZi && CC0 && TR1 && N2 && N3 && XOTHER; |
| 569 | case CLEAR: return LIT0 && SZ0 && CC0 && Ls1 && N2 && N3 && XOTHER; |
| 570 | case AND: |
| 571 | case OR: return LIT0 && SZi && CCa && TR1 && TR2 && N3 && XOTHER; |
jsgf | 5efa4fd | 2003-10-14 21:49:11 +0000 | [diff] [blame] | 572 | case MUL: return LIT0 && SZ42 && CCa && TRA1 &&TRA2 && N3 && XOTHER; |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 573 | case ADD: |
| 574 | case XOR: |
| 575 | case SUB: return LITm && SZi && CCa &&TRAL1 && TR2 && N3 && XOTHER; |
| 576 | case SBB: |
| 577 | case ADC: return LITm && SZi && CCb &&TRAL1 && TR2 && N3 && XOTHER; |
| 578 | case SHL: |
| 579 | case SHR: |
| 580 | case SAR: return LITm && SZi && CCa && TRL1 && TR2 && N3 && XOTHER; |
| 581 | case ROL: |
| 582 | case ROR: return LITm && SZi && CCc && TRL1 && TR2 && N3 && XOTHER; |
| 583 | case RCL: |
| 584 | case RCR: return LITm && SZi && CCd && TRL1 && TR2 && N3 && XOTHER; |
| 585 | case NOT: return LIT0 && SZi && CC0 && TR1 && N2 && N3 && XOTHER; |
| 586 | case NEG: return LIT0 && SZi && CCa && TR1 && N2 && N3 && XOTHER; |
| 587 | case INC: |
| 588 | case DEC: return LIT0 && SZi && CCe && TR1 && N2 && N3 && XOTHER; |
| 589 | case CC2VAL: return LIT0 && SZ1 && CCg && TR1 && N2 && N3 && XCONDi; |
| 590 | case BSWAP: return LIT0 && SZ4 && CC0 && TR1 && N2 && N3 && XOTHER; |
| 591 | case JIFZ: return LIT1 && SZ4 && CC0 && TR1 && L2 && N3 && XOTHER; |
| 592 | case FPU_R: |
| 593 | case FPU_W: return LIT0 && SZf && CC0 && Ls1 && TR2 && N3 && XOTHER; |
| 594 | case FPU: return LIT0 && SZ0 && CCf && Ls1 && N2 && N3 && XOTHER; |
| 595 | case LEA1: return /*any*/ SZ4 && CC0 && TR1 && TR2 && N3 && XOTHER; |
nethercote | 4a12dbd | 2004-04-16 16:16:34 +0000 | [diff] [blame] | 596 | case LEA2: return /*any*/ SZ4 && CC0 && TR1 && TR2 && TR3 && XLEA2; |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 597 | case INCEIP: return LIT0 && SZ0 && CC0 && Ls1 && N2 && N3 && XOTHER; |
| 598 | case CCALL: return LIT1 && SZ0 && CC0 && |
| 599 | (u->argc > 0 ? TR1 : N1) && |
| 600 | (u->argc > 1 ? TR2 : N2) && |
| 601 | (u->argc > 2 || u->has_ret_val ? TR3 : N3) && |
| 602 | u->regparms_n <= u->argc && XCCALL; |
thughes | 96b466a | 2004-03-15 16:43:58 +0000 | [diff] [blame] | 603 | /* Fields checked: lit32 size flags_r/w tag1 tag2 tag3 (rest) */ |
sewardj | 3d7c9c8 | 2003-03-26 21:08:13 +0000 | [diff] [blame] | 604 | case MMX1: |
thughes | 96b466a | 2004-03-15 16:43:58 +0000 | [diff] [blame] | 605 | case MMX2: return LIT0 && SZ0 && CC0 && Ls1 && N2 && N3 && XOTHER; |
| 606 | case MMX3: return LIT0 && SZ0 && CC0 && Ls1 && Ls2 && N3 && XOTHER; |
| 607 | case MMX2_MemRd: return LIT0 && SZ48 && CC0 && Ls1 && TR2 && N3 && XOTHER; |
| 608 | case MMX2_MemWr: return LIT0 && SZ48 && CC0 && Ls1 && TR2 && N3 && XOTHER; |
| 609 | case MMX2a1_MemRd: return LIT0 && SZ8 && CC0 && Ls1 && Ls2 && TR3 && XOTHER; |
| 610 | case MMX2_ERegRd: return LIT0 && SZ4 && CC0 && Ls1 && TR2 && N3 && XOTHER; |
| 611 | case MMX2_ERegWr: return LIT0 && SZ4 && CC0 && Ls1 && TR2 && N3 && XOTHER; |
sewardj | febaa3b | 2003-05-25 01:07:34 +0000 | [diff] [blame] | 612 | |
| 613 | /* Fields checked: lit32 size flags_r/w tag1 tag2 tag3 (rest) */ |
jseward | fca6018 | 2004-01-04 23:30:55 +0000 | [diff] [blame] | 614 | case SSE2a_MemWr: return LIT0 && SZsse2 && CC0 && Ls1 && Ls2 && TR3 && XOTHER; |
| 615 | case SSE2a_MemRd: return LIT0 && SZsse2 && CCa && Ls1 && Ls2 && TR3 && XOTHER; |
nethercote | 1018bdd | 2004-02-11 23:33:29 +0000 | [diff] [blame] | 616 | case SSE2a1_MemRd: return LIT0 && SZsse3 && CC0 && Ls1 && Ls2 && TR3 && XOTHER; |
nethercote | b1affa8 | 2004-01-19 19:14:18 +0000 | [diff] [blame] | 617 | case SSE2g_RegWr: return LIT0 && SZ4 && CC0 && Ls1 && Ls2 && TR3 && XOTHER; |
| 618 | case SSE2g1_RegWr: return LIT8 && SZ4 && CC0 && Ls1 && Ls2 && TR3 && XOTHER; |
| 619 | case SSE2e1_RegRd: return LIT8 && SZ2 && CC0 && Ls1 && Ls2 && TR3 && XOTHER; |
jseward | fca6018 | 2004-01-04 23:30:55 +0000 | [diff] [blame] | 620 | case SSE3a_MemWr: return LIT0 && SZsse3 && CC0 && Ls1 && Ls2 && TR3 && XOTHER; |
| 621 | case SSE3a_MemRd: return LIT0 && SZsse3 && CCa && Ls1 && Ls2 && TR3 && XOTHER; |
| 622 | case SSE3e_RegRd: return LIT0 && SZ4 && CC0 && Ls1 && Ls2 && TR3 && XOTHER; |
| 623 | case SSE3e_RegWr: return LIT0 && SZ4 && CC0 && Ls1 && Ls2 && TR3 && XOTHER; |
nethercote | b1affa8 | 2004-01-19 19:14:18 +0000 | [diff] [blame] | 624 | case SSE3a1_MemRd: return LIT8 && SZ816 && CC0 && Ls1 && Ls2 && TR3 && XOTHER; |
jseward | fca6018 | 2004-01-04 23:30:55 +0000 | [diff] [blame] | 625 | case SSE3g_RegWr: return LIT0 && SZ4 && CC0 && Ls1 && Ls2 && TR3 && XOTHER; |
| 626 | case SSE3g1_RegWr: return LIT8 && SZ4 && CC0 && Ls1 && Ls2 && TR3 && XOTHER; |
| 627 | case SSE3e1_RegRd: return LIT8 && SZ2 && CC0 && Ls1 && Ls2 && TR3 && XOTHER; |
| 628 | case SSE3: return LIT0 && SZ0 && CCa && Ls1 && Ls2 && N3 && XOTHER; |
| 629 | case SSE4: return LIT0 && SZ0 && CCa && Ls1 && Ls2 && N3 && XOTHER; |
| 630 | case SSE5: return LIT0 && SZ0 && CC0 && Ls1 && Ls2 && Ls3 && XOTHER; |
sewardj | e3891fa | 2003-06-15 03:13:48 +0000 | [diff] [blame] | 631 | case SSE3ag_MemRd_RegWr: |
jseward | fca6018 | 2004-01-04 23:30:55 +0000 | [diff] [blame] | 632 | return SZ48 && CC0 && TR1 && TR2 && N3 && XOTHER; |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 633 | default: |
| 634 | if (VG_(needs).extended_UCode) |
njn | 4ba5a79 | 2002-09-30 10:23:54 +0000 | [diff] [blame] | 635 | return SK_(sane_XUInstr)(beforeRA, beforeLiveness, u); |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 636 | else { |
| 637 | VG_(printf)("unhandled opcode: %u. Perhaps " |
| 638 | "VG_(needs).extended_UCode should be set?", |
| 639 | u->opcode); |
njn | e427a66 | 2002-10-02 11:08:25 +0000 | [diff] [blame] | 640 | VG_(core_panic)("VG_(saneUInstr): unhandled opcode"); |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 641 | } |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 642 | } |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 643 | # undef LIT0 |
| 644 | # undef LIT1 |
sewardj | b31b06d | 2003-06-13 00:26:02 +0000 | [diff] [blame] | 645 | # undef LIT8 |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 646 | # undef LITm |
sewardj | 77d30a2 | 2003-10-19 08:18:52 +0000 | [diff] [blame] | 647 | # undef SZ16 |
sewardj | 3d7c9c8 | 2003-03-26 21:08:13 +0000 | [diff] [blame] | 648 | # undef SZ8 |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 649 | # undef SZ4 |
| 650 | # undef SZ2 |
| 651 | # undef SZ1 |
| 652 | # undef SZ0 |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 653 | # undef SZ42 |
sewardj | d797101 | 2003-04-04 00:21:58 +0000 | [diff] [blame] | 654 | # undef SZ48 |
sewardj | febaa3b | 2003-05-25 01:07:34 +0000 | [diff] [blame] | 655 | # undef SZ416 |
nethercote | 4a12dbd | 2004-04-16 16:16:34 +0000 | [diff] [blame] | 656 | # undef SZ816 |
jseward | fca6018 | 2004-01-04 23:30:55 +0000 | [diff] [blame] | 657 | # undef SZsse2 |
| 658 | # undef SZsse3 |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 659 | # undef SZi |
| 660 | # undef SZf |
| 661 | # undef SZ4m |
| 662 | # undef emptyR |
| 663 | # undef emptyW |
| 664 | # undef CC0 |
| 665 | # undef CCr |
| 666 | # undef CCw |
| 667 | # undef CCa |
| 668 | # undef CCb |
| 669 | # undef CCc |
| 670 | # undef CCd |
| 671 | # undef CCe |
| 672 | # undef CCf |
| 673 | # undef CCg |
| 674 | # undef CCj |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 675 | # undef TR1 |
| 676 | # undef TR2 |
| 677 | # undef TR3 |
| 678 | # undef A1 |
| 679 | # undef A2 |
| 680 | # undef AS1 |
| 681 | # undef AS2 |
| 682 | # undef AS3 |
| 683 | # undef L1 |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 684 | # undef L2 |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 685 | # undef Ls1 |
sewardj | febaa3b | 2003-05-25 01:07:34 +0000 | [diff] [blame] | 686 | # undef Ls2 |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 687 | # undef Ls3 |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 688 | # undef TRL1 |
| 689 | # undef TRAL1 |
nethercote | 4a12dbd | 2004-04-16 16:16:34 +0000 | [diff] [blame] | 690 | # undef TRA1 |
| 691 | # undef TRA2 |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 692 | # undef N1 |
| 693 | # undef N2 |
| 694 | # undef N3 |
sewardj | e104247 | 2002-09-30 12:33:11 +0000 | [diff] [blame] | 695 | # undef Se2 |
| 696 | # undef Se1 |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 697 | # undef COND0 |
| 698 | # undef EXTRA4b0 |
nethercote | 4a12dbd | 2004-04-16 16:16:34 +0000 | [diff] [blame] | 699 | # undef EXTRA4b12 |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 700 | # undef SG_WD0 |
| 701 | # undef JMPKIND0 |
| 702 | # undef CCALL0 |
nethercote | 4a12dbd | 2004-04-16 16:16:34 +0000 | [diff] [blame] | 703 | # undef XCONDi |
| 704 | # undef XLEA2 |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 705 | # undef XWIDEN |
| 706 | # undef XJMP |
| 707 | # undef XCCALL |
| 708 | # undef XOTHER |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 709 | } |
| 710 | |
nethercote | 885dd91 | 2004-08-03 23:14:00 +0000 | [diff] [blame] | 711 | void VG_(sanity_check_UInstr)( UInt n, UInstr* u ) |
| 712 | { |
| 713 | Bool sane = is_sane_UInstr(u); |
| 714 | if (!sane) { |
| 715 | VG_(printf)("\nInsane instruction:\n"); |
| 716 | VG_(pp_UInstr)(n, u); |
| 717 | VG_(up_UInstr)(n, u); |
| 718 | vg_assert(sane); |
| 719 | } |
| 720 | } |
| 721 | |
| 722 | static void sanity_check_UCodeBlock ( UCodeBlock* cb ) |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 723 | { |
| 724 | Int i; |
| 725 | |
| 726 | for (i = 0; i < cb->used; i++) { |
nethercote | 885dd91 | 2004-08-03 23:14:00 +0000 | [diff] [blame] | 727 | Bool sane = is_sane_UInstr(&cb->instrs[i]); |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 728 | if (!sane) { |
| 729 | VG_(printf)("Instruction failed sanity check:\n"); |
njn | 4ba5a79 | 2002-09-30 10:23:54 +0000 | [diff] [blame] | 730 | VG_(up_UInstr)(i, &cb->instrs[i]); |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 731 | } |
| 732 | vg_assert(sane); |
| 733 | } |
| 734 | } |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 735 | |
| 736 | /* Sanity checks to do with CALLMs in UCodeBlocks. */ |
nethercote | 885dd91 | 2004-08-03 23:14:00 +0000 | [diff] [blame] | 737 | static Bool is_sane_UCodeBlockCalls ( UCodeBlock* cb ) |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 738 | { |
| 739 | Int callm = 0; |
| 740 | Int callm_s = 0; |
| 741 | Int callm_e = 0; |
| 742 | Int callm_ptr, calls_ptr; |
| 743 | Int i, j, t; |
| 744 | Bool incall = False; |
| 745 | |
| 746 | /* Ensure the number of CALLM, CALLM_S and CALLM_E are the same. */ |
| 747 | |
| 748 | for (i = 0; i < cb->used; i++) { |
| 749 | switch (cb->instrs[i].opcode) { |
| 750 | case CALLM: |
| 751 | if (!incall) return False; |
| 752 | callm++; |
| 753 | break; |
| 754 | case CALLM_S: |
| 755 | if (incall) return False; |
| 756 | incall = True; |
| 757 | callm_s++; |
| 758 | break; |
| 759 | case CALLM_E: |
| 760 | if (!incall) return False; |
| 761 | incall = False; |
| 762 | callm_e++; |
| 763 | break; |
| 764 | case PUSH: case POP: case CLEAR: |
| 765 | if (!incall) return False; |
| 766 | break; |
| 767 | default: |
| 768 | break; |
| 769 | } |
| 770 | } |
| 771 | if (incall) return False; |
| 772 | if (callm != callm_s || callm != callm_e) return False; |
| 773 | |
| 774 | /* Check the sections between CALLM_S and CALLM's. Ensure that no |
| 775 | PUSH uinsn pushes any TempReg that any other PUSH in the same |
| 776 | section pushes. Ie, check that the TempReg args to PUSHes in |
| 777 | the section are unique. If not, the instrumenter generates |
| 778 | incorrect code for CALLM insns. */ |
| 779 | |
| 780 | callm_ptr = 0; |
| 781 | |
| 782 | find_next_CALLM: |
| 783 | /* Search for the next interval, making calls_ptr .. callm_ptr |
| 784 | bracket it. */ |
| 785 | while (callm_ptr < cb->used |
| 786 | && cb->instrs[callm_ptr].opcode != CALLM) |
| 787 | callm_ptr++; |
| 788 | if (callm_ptr == cb->used) |
| 789 | return True; |
| 790 | vg_assert(cb->instrs[callm_ptr].opcode == CALLM); |
| 791 | |
| 792 | calls_ptr = callm_ptr - 1; |
| 793 | while (cb->instrs[calls_ptr].opcode != CALLM_S) |
| 794 | calls_ptr--; |
| 795 | vg_assert(cb->instrs[calls_ptr].opcode == CALLM_S); |
| 796 | vg_assert(calls_ptr >= 0); |
| 797 | |
| 798 | /* VG_(printf)("interval from %d to %d\n", calls_ptr, callm_ptr ); */ |
| 799 | |
| 800 | /* For each PUSH insn in the interval ... */ |
| 801 | for (i = calls_ptr + 1; i < callm_ptr; i++) { |
| 802 | if (cb->instrs[i].opcode != PUSH) continue; |
| 803 | t = cb->instrs[i].val1; |
| 804 | /* Ensure no later PUSH insns up to callm_ptr push the same |
| 805 | TempReg. Return False if any such are found. */ |
| 806 | for (j = i+1; j < callm_ptr; j++) { |
| 807 | if (cb->instrs[j].opcode == PUSH && |
| 808 | cb->instrs[j].val1 == t) |
| 809 | return False; |
| 810 | } |
| 811 | } |
| 812 | |
| 813 | /* This interval is clean. Keep going ... */ |
| 814 | callm_ptr++; |
| 815 | goto find_next_CALLM; |
| 816 | } |
| 817 | |
nethercote | 885dd91 | 2004-08-03 23:14:00 +0000 | [diff] [blame] | 818 | static void sanity_check_UCodeBlockCalls( UCodeBlock* cb ) |
| 819 | { |
| 820 | if ( ! is_sane_UCodeBlockCalls( cb ) ) { |
| 821 | VG_(pp_UCodeBlock)(cb, "block failing calls sanity check"); |
| 822 | VG_(core_panic)("bad block"); |
| 823 | } |
| 824 | } |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 825 | |
| 826 | /*------------------------------------------------------------*/ |
| 827 | /*--- Printing uinstrs. ---*/ |
| 828 | /*------------------------------------------------------------*/ |
| 829 | |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 830 | /* Global that dictates whether to print generated code at all stages */ |
| 831 | Bool VG_(print_codegen); |
| 832 | |
njn | 563f96f | 2003-02-03 11:17:46 +0000 | [diff] [blame] | 833 | Char* VG_(name_UCondcode) ( Condcode cond ) |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 834 | { |
| 835 | switch (cond) { |
| 836 | case CondO: return "o"; |
| 837 | case CondNO: return "no"; |
| 838 | case CondB: return "b"; |
| 839 | case CondNB: return "nb"; |
| 840 | case CondZ: return "z"; |
| 841 | case CondNZ: return "nz"; |
| 842 | case CondBE: return "be"; |
| 843 | case CondNBE: return "nbe"; |
| 844 | case CondS: return "s"; |
sewardj | e104247 | 2002-09-30 12:33:11 +0000 | [diff] [blame] | 845 | case CondNS: return "ns"; |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 846 | case CondP: return "p"; |
| 847 | case CondNP: return "np"; |
| 848 | case CondL: return "l"; |
| 849 | case CondNL: return "nl"; |
| 850 | case CondLE: return "le"; |
| 851 | case CondNLE: return "nle"; |
| 852 | case CondAlways: return "MP"; /* hack! */ |
njn | 563f96f | 2003-02-03 11:17:46 +0000 | [diff] [blame] | 853 | default: VG_(core_panic)("name_UCondcode"); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 854 | } |
| 855 | } |
| 856 | |
| 857 | |
| 858 | static void vg_ppFlagSet ( Char* prefix, FlagSet set ) |
| 859 | { |
| 860 | VG_(printf)("%s", prefix); |
| 861 | if (set & FlagD) VG_(printf)("D"); |
| 862 | if (set & FlagO) VG_(printf)("O"); |
| 863 | if (set & FlagS) VG_(printf)("S"); |
| 864 | if (set & FlagZ) VG_(printf)("Z"); |
| 865 | if (set & FlagA) VG_(printf)("A"); |
| 866 | if (set & FlagC) VG_(printf)("C"); |
| 867 | if (set & FlagP) VG_(printf)("P"); |
| 868 | } |
| 869 | |
| 870 | |
| 871 | static void ppTempReg ( Int tt ) |
| 872 | { |
| 873 | if ((tt & 1) == 0) |
| 874 | VG_(printf)("t%d", tt); |
| 875 | else |
| 876 | VG_(printf)("q%d", tt-1); |
| 877 | } |
| 878 | |
| 879 | |
njn | 4ba5a79 | 2002-09-30 10:23:54 +0000 | [diff] [blame] | 880 | void VG_(pp_UOperand) ( UInstr* u, Int operandNo, Int sz, Bool parens ) |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 881 | { |
| 882 | UInt tag, val; |
| 883 | switch (operandNo) { |
| 884 | case 1: tag = u->tag1; val = u->val1; break; |
| 885 | case 2: tag = u->tag2; val = u->val2; break; |
| 886 | case 3: tag = u->tag3; val = u->val3; break; |
njn | e427a66 | 2002-10-02 11:08:25 +0000 | [diff] [blame] | 887 | default: VG_(core_panic)("VG_(pp_UOperand)(1)"); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 888 | } |
| 889 | if (tag == Literal) val = u->lit32; |
| 890 | |
| 891 | if (parens) VG_(printf)("("); |
| 892 | switch (tag) { |
sewardj | e104247 | 2002-09-30 12:33:11 +0000 | [diff] [blame] | 893 | case TempReg: ppTempReg(val); break; |
| 894 | case RealReg: VG_(printf)("%s",nameIReg(sz==0 ? 4 : sz,val)); break; |
| 895 | case Literal: VG_(printf)("$0x%x", val); break; |
| 896 | case Lit16: VG_(printf)("$0x%x", val); break; |
| 897 | case NoValue: VG_(printf)("NoValue"); break; |
| 898 | case ArchReg: VG_(printf)("%S",nameIReg(sz,val)); break; |
| 899 | case ArchRegS: VG_(printf)("%S",nameSReg(val)); break; |
| 900 | case SpillNo: VG_(printf)("spill%d", val); break; |
njn | e427a66 | 2002-10-02 11:08:25 +0000 | [diff] [blame] | 901 | default: VG_(core_panic)("VG_(ppUOperand)(2)"); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 902 | } |
| 903 | if (parens) VG_(printf)(")"); |
| 904 | } |
| 905 | |
| 906 | |
njn | 4ba5a79 | 2002-09-30 10:23:54 +0000 | [diff] [blame] | 907 | Char* VG_(name_UOpcode) ( Bool upper, Opcode opc ) |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 908 | { |
| 909 | switch (opc) { |
| 910 | case ADD: return (upper ? "ADD" : "add"); |
| 911 | case ADC: return (upper ? "ADC" : "adc"); |
| 912 | case AND: return (upper ? "AND" : "and"); |
| 913 | case OR: return (upper ? "OR" : "or"); |
| 914 | case XOR: return (upper ? "XOR" : "xor"); |
| 915 | case SUB: return (upper ? "SUB" : "sub"); |
| 916 | case SBB: return (upper ? "SBB" : "sbb"); |
| 917 | case SHL: return (upper ? "SHL" : "shl"); |
| 918 | case SHR: return (upper ? "SHR" : "shr"); |
| 919 | case SAR: return (upper ? "SAR" : "sar"); |
| 920 | case ROL: return (upper ? "ROL" : "rol"); |
| 921 | case ROR: return (upper ? "ROR" : "ror"); |
| 922 | case RCL: return (upper ? "RCL" : "rcl"); |
| 923 | case RCR: return (upper ? "RCR" : "rcr"); |
jsgf | 5efa4fd | 2003-10-14 21:49:11 +0000 | [diff] [blame] | 924 | case MUL: return (upper ? "MUL" : "mul"); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 925 | case NOT: return (upper ? "NOT" : "not"); |
| 926 | case NEG: return (upper ? "NEG" : "neg"); |
| 927 | case INC: return (upper ? "INC" : "inc"); |
| 928 | case DEC: return (upper ? "DEC" : "dec"); |
| 929 | case BSWAP: return (upper ? "BSWAP" : "bswap"); |
| 930 | default: break; |
| 931 | } |
njn | e427a66 | 2002-10-02 11:08:25 +0000 | [diff] [blame] | 932 | if (!upper) VG_(core_panic)("vg_name_UOpcode: invalid !upper"); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 933 | switch (opc) { |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 934 | case CALLM_S: return "CALLM_S"; |
| 935 | case CALLM_E: return "CALLM_E"; |
| 936 | case INCEIP: return "INCEIP"; |
| 937 | case LEA1: return "LEA1"; |
| 938 | case LEA2: return "LEA2"; |
| 939 | case NOP: return "NOP"; |
sewardj | 7a5ebcf | 2002-11-13 22:42:13 +0000 | [diff] [blame] | 940 | case LOCK: return "LOCK"; |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 941 | case GET: return "GET"; |
| 942 | case PUT: return "PUT"; |
| 943 | case GETF: return "GETF"; |
| 944 | case PUTF: return "PUTF"; |
sewardj | e104247 | 2002-09-30 12:33:11 +0000 | [diff] [blame] | 945 | case GETSEG: return "GETSEG"; |
| 946 | case PUTSEG: return "PUTSEG"; |
| 947 | case USESEG: return "USESEG"; |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 948 | case LOAD: return "LD" ; |
| 949 | case STORE: return "ST" ; |
| 950 | case MOV: return "MOV"; |
| 951 | case CMOV: return "CMOV"; |
| 952 | case WIDEN: return "WIDEN"; |
| 953 | case JMP: return "J" ; |
| 954 | case JIFZ: return "JIFZ" ; |
| 955 | case CALLM: return "CALLM"; |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 956 | case CCALL: return "CCALL"; |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 957 | case PUSH: return "PUSH" ; |
| 958 | case POP: return "POP" ; |
| 959 | case CLEAR: return "CLEAR"; |
| 960 | case CC2VAL: return "CC2VAL"; |
| 961 | case FPU_R: return "FPU_R"; |
| 962 | case FPU_W: return "FPU_W"; |
| 963 | case FPU: return "FPU" ; |
sewardj | 3d7c9c8 | 2003-03-26 21:08:13 +0000 | [diff] [blame] | 964 | case MMX1: return "MMX1" ; |
| 965 | case MMX2: return "MMX2" ; |
sewardj | ca86001 | 2003-03-27 23:52:58 +0000 | [diff] [blame] | 966 | case MMX3: return "MMX3" ; |
sewardj | 3d7c9c8 | 2003-03-26 21:08:13 +0000 | [diff] [blame] | 967 | case MMX2_MemRd: return "MMX2_MRd" ; |
| 968 | case MMX2_MemWr: return "MMX2_MWr" ; |
thughes | 96b466a | 2004-03-15 16:43:58 +0000 | [diff] [blame] | 969 | case MMX2a1_MemRd: return "MMX2a1_MRd" ; |
sewardj | 4fbe6e9 | 2003-06-15 21:54:34 +0000 | [diff] [blame] | 970 | case MMX2_ERegRd: return "MMX2_eRRd" ; |
| 971 | case MMX2_ERegWr: return "MMX2_eRWr" ; |
sewardj | febaa3b | 2003-05-25 01:07:34 +0000 | [diff] [blame] | 972 | case SSE2a_MemWr: return "SSE2a_MWr"; |
| 973 | case SSE2a_MemRd: return "SSE2a_MRd"; |
nethercote | b1affa8 | 2004-01-19 19:14:18 +0000 | [diff] [blame] | 974 | case SSE2g_RegWr: return "SSE2g_RWr"; |
sewardj | 9dd209f | 2003-06-18 23:30:52 +0000 | [diff] [blame] | 975 | case SSE2a1_MemRd: return "SSE2a1_MRd"; |
nethercote | b1affa8 | 2004-01-19 19:14:18 +0000 | [diff] [blame] | 976 | case SSE2g1_RegWr: return "SSE2g1_RWr"; |
| 977 | case SSE2e1_RegRd: return "SSE2e1_RRd"; |
sewardj | 4fbe6e9 | 2003-06-15 21:54:34 +0000 | [diff] [blame] | 978 | case SSE3e_RegRd: return "SSE3e_RRd"; |
sewardj | abf8bf8 | 2003-06-15 22:28:05 +0000 | [diff] [blame] | 979 | case SSE3e_RegWr: return "SSE3e_RWr"; |
sewardj | 02af6bc | 2003-06-12 00:56:06 +0000 | [diff] [blame] | 980 | case SSE3g_RegWr: return "SSE3g_RWr"; |
sewardj | 77d30a2 | 2003-10-19 08:18:52 +0000 | [diff] [blame] | 981 | case SSE3a1_MemRd: return "SSE3a1_MRd"; |
sewardj | b31b06d | 2003-06-13 00:26:02 +0000 | [diff] [blame] | 982 | case SSE3g1_RegWr: return "SSE3g1_RWr"; |
sewardj | 4fbe6e9 | 2003-06-15 21:54:34 +0000 | [diff] [blame] | 983 | case SSE3e1_RegRd: return "SSE3e1_RRd"; |
sewardj | a60be0e | 2003-05-26 08:47:27 +0000 | [diff] [blame] | 984 | case SSE3: return "SSE3"; |
sewardj | febaa3b | 2003-05-25 01:07:34 +0000 | [diff] [blame] | 985 | case SSE4: return "SSE4"; |
sewardj | a453fb0 | 2003-06-14 13:22:36 +0000 | [diff] [blame] | 986 | case SSE5: return "SSE5"; |
sewardj | febaa3b | 2003-05-25 01:07:34 +0000 | [diff] [blame] | 987 | case SSE3a_MemWr: return "SSE3a_MWr"; |
| 988 | case SSE3a_MemRd: return "SSE3a_MRd"; |
sewardj | e3891fa | 2003-06-15 03:13:48 +0000 | [diff] [blame] | 989 | case SSE3ag_MemRd_RegWr: return "SSE3ag_MemRd_RegWr"; |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 990 | default: |
| 991 | if (VG_(needs).extended_UCode) |
njn | 4ba5a79 | 2002-09-30 10:23:54 +0000 | [diff] [blame] | 992 | return SK_(name_XUOpcode)(opc); |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 993 | else { |
| 994 | VG_(printf)("unhandled opcode: %u. Perhaps " |
| 995 | "VG_(needs).extended_UCode should be set?", |
| 996 | opc); |
njn | e427a66 | 2002-10-02 11:08:25 +0000 | [diff] [blame] | 997 | VG_(core_panic)("name_UOpcode: unhandled opcode"); |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 998 | } |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 999 | } |
| 1000 | } |
| 1001 | |
sewardj | a38e092 | 2002-10-01 00:50:47 +0000 | [diff] [blame] | 1002 | static |
njn | 4ba5a79 | 2002-09-30 10:23:54 +0000 | [diff] [blame] | 1003 | void pp_realregs_liveness ( UInstr* u ) |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 1004 | { |
| 1005 | # define PRINT_RREG_LIVENESS(realReg,s) \ |
njn | 4ba5a79 | 2002-09-30 10:23:54 +0000 | [diff] [blame] | 1006 | VG_(printf)( IS_RREG_LIVE(VG_(realreg_to_rank)(realReg), \ |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 1007 | u->regs_live_after) \ |
| 1008 | ? s : "-"); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1009 | |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 1010 | VG_(printf)("["); |
| 1011 | PRINT_RREG_LIVENESS(R_EAX, "a"); |
| 1012 | PRINT_RREG_LIVENESS(R_EBX, "b"); |
| 1013 | PRINT_RREG_LIVENESS(R_ECX, "c"); |
| 1014 | PRINT_RREG_LIVENESS(R_EDX, "d"); |
| 1015 | PRINT_RREG_LIVENESS(R_ESI, "S"); |
| 1016 | PRINT_RREG_LIVENESS(R_EDI, "D"); |
| 1017 | VG_(printf)("]"); |
| 1018 | |
| 1019 | # undef PRINT_RREG_LIVENESS |
| 1020 | } |
| 1021 | |
| 1022 | /* Ugly-print UInstr :) */ |
njn | 4ba5a79 | 2002-09-30 10:23:54 +0000 | [diff] [blame] | 1023 | void VG_(up_UInstr) ( Int i, UInstr* u ) |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 1024 | { |
njn | 4ba5a79 | 2002-09-30 10:23:54 +0000 | [diff] [blame] | 1025 | VG_(pp_UInstr_regs)(i, u); |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 1026 | |
| 1027 | VG_(printf)("opcode: %d\n", u->opcode); |
sewardj | c1b8688 | 2002-10-06 21:43:50 +0000 | [diff] [blame] | 1028 | VG_(printf)("lit32: 0x%x\n", u->lit32); |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 1029 | VG_(printf)("size: %d\n", u->size); |
| 1030 | VG_(printf)("val1,val2,val3: %d, %d, %d\n", u->val1, u->val2, u->val3); |
| 1031 | VG_(printf)("tag1,tag2,tag3: %d, %d, %d\n", u->tag1, u->tag2, u->tag3); |
sewardj | c1b8688 | 2002-10-06 21:43:50 +0000 | [diff] [blame] | 1032 | VG_(printf)("flags_r: 0x%x\n", u->flags_r); |
| 1033 | VG_(printf)("flags_w: 0x%x\n", u->flags_w); |
| 1034 | VG_(printf)("extra4b: 0x%x\n", u->extra4b); |
| 1035 | VG_(printf)("cond: 0x%x\n", u->cond); |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 1036 | VG_(printf)("signed_widen: %d\n", u->signed_widen); |
| 1037 | VG_(printf)("jmpkind: %d\n", u->jmpkind); |
| 1038 | VG_(printf)("argc,regparms_n: %d, %d\n", u->argc, u->regparms_n); |
| 1039 | VG_(printf)("has_ret_val: %d\n", u->has_ret_val); |
| 1040 | VG_(printf)("regs_live_after: "); |
njn | 4ba5a79 | 2002-09-30 10:23:54 +0000 | [diff] [blame] | 1041 | pp_realregs_liveness(u); |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 1042 | VG_(printf)("\n"); |
| 1043 | } |
| 1044 | |
sewardj | a38e092 | 2002-10-01 00:50:47 +0000 | [diff] [blame] | 1045 | static |
njn | 4ba5a79 | 2002-09-30 10:23:54 +0000 | [diff] [blame] | 1046 | void pp_UInstrWorker ( Int instrNo, UInstr* u, Bool ppRegsLiveness ) |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1047 | { |
| 1048 | VG_(printf)("\t%4d: %s", instrNo, |
njn | 4ba5a79 | 2002-09-30 10:23:54 +0000 | [diff] [blame] | 1049 | VG_(name_UOpcode)(True, u->opcode)); |
nethercote | e00f1ff | 2004-04-16 11:33:53 +0000 | [diff] [blame] | 1050 | // For JMP, the condition goes before the size |
| 1051 | if (u->opcode == JMP) |
njn | 563f96f | 2003-02-03 11:17:46 +0000 | [diff] [blame] | 1052 | VG_(printf)("%s", VG_(name_UCondcode)(u->cond)); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1053 | |
| 1054 | switch (u->size) { |
| 1055 | case 0: VG_(printf)("o"); break; |
| 1056 | case 1: VG_(printf)("B"); break; |
| 1057 | case 2: VG_(printf)("W"); break; |
| 1058 | case 4: VG_(printf)("L"); break; |
| 1059 | case 8: VG_(printf)("Q"); break; |
sewardj | febaa3b | 2003-05-25 01:07:34 +0000 | [diff] [blame] | 1060 | case 16: VG_(printf)("QQ"); break; |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1061 | default: VG_(printf)("%d", (Int)u->size); break; |
| 1062 | } |
| 1063 | |
nethercote | e00f1ff | 2004-04-16 11:33:53 +0000 | [diff] [blame] | 1064 | // For CC2VAL and CMOV, the condition goes after the size |
| 1065 | if (u->opcode == CC2VAL || u->opcode == CMOV) |
| 1066 | VG_(printf)("%s", VG_(name_UCondcode)(u->cond)); |
| 1067 | |
nethercote | bbcfb58 | 2004-04-16 15:39:22 +0000 | [diff] [blame] | 1068 | // Append extra bits |
| 1069 | switch (u->opcode) { |
| 1070 | case JMP: |
nethercote | e00f1ff | 2004-04-16 11:33:53 +0000 | [diff] [blame] | 1071 | switch (u->jmpkind) { |
| 1072 | case JmpCall: VG_(printf)("-c"); break; |
| 1073 | case JmpRet: VG_(printf)("-r"); break; |
| 1074 | case JmpSyscall: VG_(printf)("-sys"); break; |
| 1075 | case JmpClientReq: VG_(printf)("-cli"); break; |
| 1076 | case JmpYield: VG_(printf)("-yld"); break; |
| 1077 | default: break; |
| 1078 | } |
nethercote | bbcfb58 | 2004-04-16 15:39:22 +0000 | [diff] [blame] | 1079 | break; |
| 1080 | |
| 1081 | case WIDEN: |
| 1082 | VG_(printf)("_%c%c", VG_(toupper)(nameISize(u->extra4b)), |
| 1083 | u->signed_widen?'s':'z'); |
| 1084 | } |
sewardj | febaa3b | 2003-05-25 01:07:34 +0000 | [diff] [blame] | 1085 | VG_(printf)(" \t"); |
| 1086 | |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1087 | switch (u->opcode) { |
| 1088 | |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1089 | case CALLM_S: case CALLM_E: |
| 1090 | break; |
| 1091 | |
| 1092 | case INCEIP: |
sewardj | febaa3b | 2003-05-25 01:07:34 +0000 | [diff] [blame] | 1093 | VG_(printf)("$%d", u->val1); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1094 | break; |
| 1095 | |
| 1096 | case LEA2: |
sewardj | febaa3b | 2003-05-25 01:07:34 +0000 | [diff] [blame] | 1097 | VG_(printf)("%d(" , u->lit32); |
njn | 4ba5a79 | 2002-09-30 10:23:54 +0000 | [diff] [blame] | 1098 | VG_(pp_UOperand)(u, 1, 4, False); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1099 | VG_(printf)(","); |
njn | 4ba5a79 | 2002-09-30 10:23:54 +0000 | [diff] [blame] | 1100 | VG_(pp_UOperand)(u, 2, 4, False); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1101 | VG_(printf)(",%d), ", (Int)u->extra4b); |
njn | 4ba5a79 | 2002-09-30 10:23:54 +0000 | [diff] [blame] | 1102 | VG_(pp_UOperand)(u, 3, 4, False); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1103 | break; |
| 1104 | |
| 1105 | case LEA1: |
sewardj | febaa3b | 2003-05-25 01:07:34 +0000 | [diff] [blame] | 1106 | VG_(printf)("%d" , u->lit32); |
njn | 4ba5a79 | 2002-09-30 10:23:54 +0000 | [diff] [blame] | 1107 | VG_(pp_UOperand)(u, 1, 4, True); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1108 | VG_(printf)(", "); |
njn | 4ba5a79 | 2002-09-30 10:23:54 +0000 | [diff] [blame] | 1109 | VG_(pp_UOperand)(u, 2, 4, False); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1110 | break; |
| 1111 | |
sewardj | 7a5ebcf | 2002-11-13 22:42:13 +0000 | [diff] [blame] | 1112 | case NOP: case LOCK: |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1113 | break; |
| 1114 | |
| 1115 | case FPU_W: |
sewardj | febaa3b | 2003-05-25 01:07:34 +0000 | [diff] [blame] | 1116 | VG_(printf)("0x%x:0x%x, ", |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1117 | (u->val1 >> 8) & 0xFF, u->val1 & 0xFF ); |
njn | 4ba5a79 | 2002-09-30 10:23:54 +0000 | [diff] [blame] | 1118 | VG_(pp_UOperand)(u, 2, 4, True); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1119 | break; |
| 1120 | |
| 1121 | case FPU_R: |
sewardj | febaa3b | 2003-05-25 01:07:34 +0000 | [diff] [blame] | 1122 | VG_(printf)(""); |
njn | 4ba5a79 | 2002-09-30 10:23:54 +0000 | [diff] [blame] | 1123 | VG_(pp_UOperand)(u, 2, 4, True); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1124 | VG_(printf)(", 0x%x:0x%x", |
| 1125 | (u->val1 >> 8) & 0xFF, u->val1 & 0xFF ); |
| 1126 | break; |
| 1127 | |
| 1128 | case FPU: |
sewardj | febaa3b | 2003-05-25 01:07:34 +0000 | [diff] [blame] | 1129 | VG_(printf)("0x%x:0x%x", |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1130 | (u->val1 >> 8) & 0xFF, u->val1 & 0xFF ); |
| 1131 | break; |
| 1132 | |
sewardj | 3d7c9c8 | 2003-03-26 21:08:13 +0000 | [diff] [blame] | 1133 | case MMX1: |
sewardj | febaa3b | 2003-05-25 01:07:34 +0000 | [diff] [blame] | 1134 | VG_(printf)("0x%x", |
sewardj | 3d7c9c8 | 2003-03-26 21:08:13 +0000 | [diff] [blame] | 1135 | u->val1 & 0xFF ); |
| 1136 | break; |
| 1137 | |
| 1138 | case MMX2: |
sewardj | febaa3b | 2003-05-25 01:07:34 +0000 | [diff] [blame] | 1139 | VG_(printf)("0x%x:0x%x", |
sewardj | 3d7c9c8 | 2003-03-26 21:08:13 +0000 | [diff] [blame] | 1140 | (u->val1 >> 8) & 0xFF, u->val1 & 0xFF ); |
| 1141 | break; |
| 1142 | |
sewardj | ca86001 | 2003-03-27 23:52:58 +0000 | [diff] [blame] | 1143 | case MMX3: |
sewardj | febaa3b | 2003-05-25 01:07:34 +0000 | [diff] [blame] | 1144 | VG_(printf)("0x%x:0x%x:0x%x", |
sewardj | ca86001 | 2003-03-27 23:52:58 +0000 | [diff] [blame] | 1145 | (u->val1 >> 8) & 0xFF, u->val1 & 0xFF, u->val2 & 0xFF ); |
| 1146 | break; |
| 1147 | |
sewardj | 4fbe6e9 | 2003-06-15 21:54:34 +0000 | [diff] [blame] | 1148 | case MMX2_ERegWr: |
| 1149 | case MMX2_ERegRd: |
sewardj | febaa3b | 2003-05-25 01:07:34 +0000 | [diff] [blame] | 1150 | VG_(printf)("0x%x:0x%x, ", |
sewardj | ca86001 | 2003-03-27 23:52:58 +0000 | [diff] [blame] | 1151 | (u->val1 >> 8) & 0xFF, u->val1 & 0xFF ); |
| 1152 | VG_(pp_UOperand)(u, 2, 4, False); |
| 1153 | break; |
| 1154 | |
sewardj | 3d7c9c8 | 2003-03-26 21:08:13 +0000 | [diff] [blame] | 1155 | case MMX2_MemWr: |
| 1156 | case MMX2_MemRd: |
sewardj | febaa3b | 2003-05-25 01:07:34 +0000 | [diff] [blame] | 1157 | VG_(printf)("0x%x:0x%x", |
sewardj | 3d7c9c8 | 2003-03-26 21:08:13 +0000 | [diff] [blame] | 1158 | (u->val1 >> 8) & 0xFF, u->val1 & 0xFF ); |
| 1159 | VG_(pp_UOperand)(u, 2, 4, True); |
| 1160 | break; |
| 1161 | |
thughes | 96b466a | 2004-03-15 16:43:58 +0000 | [diff] [blame] | 1162 | case MMX2a1_MemRd: |
| 1163 | VG_(printf)("0x%x:0x%x:0x%x", |
| 1164 | (u->val1 >> 8) & 0xFF, u->val1 & 0xFF, u->val2 & 0xFF ); |
| 1165 | VG_(pp_UOperand)(u, 3, 4, True); |
| 1166 | break; |
| 1167 | |
sewardj | febaa3b | 2003-05-25 01:07:34 +0000 | [diff] [blame] | 1168 | case SSE2a_MemWr: |
| 1169 | case SSE2a_MemRd: |
nethercote | b1affa8 | 2004-01-19 19:14:18 +0000 | [diff] [blame] | 1170 | case SSE2g_RegWr: |
| 1171 | case SSE2g1_RegWr: |
| 1172 | case SSE2e1_RegRd: |
sewardj | febaa3b | 2003-05-25 01:07:34 +0000 | [diff] [blame] | 1173 | VG_(printf)("0x%x:0x%x:0x%x", |
| 1174 | (u->val1 >> 8) & 0xFF, u->val1 & 0xFF, u->val2 & 0xFF ); |
| 1175 | VG_(pp_UOperand)(u, 3, 4, True); |
| 1176 | break; |
| 1177 | |
sewardj | 9dd209f | 2003-06-18 23:30:52 +0000 | [diff] [blame] | 1178 | case SSE2a1_MemRd: |
sewardj | febaa3b | 2003-05-25 01:07:34 +0000 | [diff] [blame] | 1179 | case SSE3a_MemWr: |
| 1180 | case SSE3a_MemRd: |
| 1181 | VG_(printf)("0x%x:0x%x:0x%x:0x%x", |
| 1182 | (u->val1 >> 8) & 0xFF, u->val1 & 0xFF, |
sewardj | de8aecf | 2003-05-27 00:46:28 +0000 | [diff] [blame] | 1183 | (u->val2 >> 8) & 0xFF, u->val2 & 0xFF ); |
sewardj | febaa3b | 2003-05-25 01:07:34 +0000 | [diff] [blame] | 1184 | VG_(pp_UOperand)(u, 3, 4, True); |
| 1185 | break; |
| 1186 | |
sewardj | abf8bf8 | 2003-06-15 22:28:05 +0000 | [diff] [blame] | 1187 | case SSE3e_RegWr: |
sewardj | 4fbe6e9 | 2003-06-15 21:54:34 +0000 | [diff] [blame] | 1188 | case SSE3e_RegRd: |
sewardj | 02af6bc | 2003-06-12 00:56:06 +0000 | [diff] [blame] | 1189 | case SSE3g_RegWr: |
sewardj | febaa3b | 2003-05-25 01:07:34 +0000 | [diff] [blame] | 1190 | VG_(printf)("0x%x:0x%x:0x%x:0x%x", |
| 1191 | (u->val1 >> 8) & 0xFF, u->val1 & 0xFF, |
| 1192 | (u->val2 >> 8) & 0xFF, u->val2 & 0xFF ); |
| 1193 | VG_(pp_UOperand)(u, 3, 4, True); |
| 1194 | break; |
| 1195 | |
sewardj | b31b06d | 2003-06-13 00:26:02 +0000 | [diff] [blame] | 1196 | case SSE3g1_RegWr: |
sewardj | 4fbe6e9 | 2003-06-15 21:54:34 +0000 | [diff] [blame] | 1197 | case SSE3e1_RegRd: |
sewardj | 77d30a2 | 2003-10-19 08:18:52 +0000 | [diff] [blame] | 1198 | case SSE3a1_MemRd: |
sewardj | b31b06d | 2003-06-13 00:26:02 +0000 | [diff] [blame] | 1199 | VG_(printf)("0x%x:0x%x:0x%x:0x%x:0x%x", |
| 1200 | (u->val1 >> 8) & 0xFF, u->val1 & 0xFF, |
| 1201 | (u->val2 >> 8) & 0xFF, u->val2 & 0xFF, |
| 1202 | u->lit32 ); |
| 1203 | VG_(pp_UOperand)(u, 3, 4, True); |
| 1204 | break; |
| 1205 | |
sewardj | a60be0e | 2003-05-26 08:47:27 +0000 | [diff] [blame] | 1206 | case SSE3: |
| 1207 | VG_(printf)("0x%x:0x%x:0x%x", |
| 1208 | (u->val1 >> 8) & 0xFF, u->val1 & 0xFF, |
| 1209 | u->val2 & 0xFF ); |
| 1210 | break; |
| 1211 | |
sewardj | febaa3b | 2003-05-25 01:07:34 +0000 | [diff] [blame] | 1212 | case SSE4: |
| 1213 | VG_(printf)("0x%x:0x%x:0x%x:0x%x", |
| 1214 | (u->val1 >> 8) & 0xFF, u->val1 & 0xFF, |
| 1215 | (u->val2 >> 8) & 0xFF, u->val2 & 0xFF ); |
| 1216 | break; |
| 1217 | |
sewardj | a453fb0 | 2003-06-14 13:22:36 +0000 | [diff] [blame] | 1218 | case SSE5: |
| 1219 | VG_(printf)("0x%x:0x%x:0x%x:0x%x:0x%x", |
| 1220 | (u->val1 >> 8) & 0xFF, u->val1 & 0xFF, |
| 1221 | (u->val2 >> 8) & 0xFF, u->val2 & 0xFF, |
| 1222 | u->val3 & 0xFF ); |
| 1223 | break; |
| 1224 | |
sewardj | e3891fa | 2003-06-15 03:13:48 +0000 | [diff] [blame] | 1225 | case SSE3ag_MemRd_RegWr: |
| 1226 | VG_(printf)("0x%x(addr=", u->lit32 ); |
| 1227 | VG_(pp_UOperand)(u, 1, 4, False); |
| 1228 | VG_(printf)(", dst="); |
| 1229 | VG_(pp_UOperand)(u, 2, 4, False); |
| 1230 | VG_(printf)(")"); |
| 1231 | break; |
| 1232 | |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1233 | case GET: case PUT: case MOV: case LOAD: case STORE: case CMOV: |
sewardj | e104247 | 2002-09-30 12:33:11 +0000 | [diff] [blame] | 1234 | case GETSEG: case PUTSEG: |
njn | 4ba5a79 | 2002-09-30 10:23:54 +0000 | [diff] [blame] | 1235 | VG_(pp_UOperand)(u, 1, u->size, u->opcode==LOAD); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1236 | VG_(printf)(", "); |
njn | 4ba5a79 | 2002-09-30 10:23:54 +0000 | [diff] [blame] | 1237 | VG_(pp_UOperand)(u, 2, u->size, u->opcode==STORE); |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 1238 | break; |
| 1239 | |
| 1240 | case JMP: |
njn | 4ba5a79 | 2002-09-30 10:23:54 +0000 | [diff] [blame] | 1241 | VG_(pp_UOperand)(u, 1, u->size, False); |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 1242 | if (CondAlways == u->cond) { |
| 1243 | /* Print x86 instruction size if filled in */ |
| 1244 | if (0 != u->extra4b) |
| 1245 | VG_(printf)(" ($%u)", u->extra4b); |
| 1246 | } |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1247 | break; |
| 1248 | |
| 1249 | case GETF: case PUTF: |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 1250 | case CC2VAL: case PUSH: case POP: case CLEAR: case CALLM: |
| 1251 | case NOT: case NEG: case INC: case DEC: case BSWAP: |
njn | 4ba5a79 | 2002-09-30 10:23:54 +0000 | [diff] [blame] | 1252 | VG_(pp_UOperand)(u, 1, u->size, False); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1253 | break; |
| 1254 | |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 1255 | /* Print a "(s)" after args passed on stack */ |
| 1256 | case CCALL: |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 1257 | if (u->has_ret_val) { |
njn | 4ba5a79 | 2002-09-30 10:23:54 +0000 | [diff] [blame] | 1258 | VG_(pp_UOperand)(u, 3, 0, False); |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 1259 | VG_(printf)(" = "); |
sewardj | 2e93c50 | 2002-04-12 11:12:52 +0000 | [diff] [blame] | 1260 | } |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 1261 | VG_(printf)("%p(", u->lit32); |
| 1262 | if (u->argc > 0) { |
njn | 4ba5a79 | 2002-09-30 10:23:54 +0000 | [diff] [blame] | 1263 | VG_(pp_UOperand)(u, 1, 0, False); |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 1264 | if (u->regparms_n < 1) |
| 1265 | VG_(printf)("(s)"); |
| 1266 | } |
| 1267 | if (u->argc > 1) { |
| 1268 | VG_(printf)(", "); |
njn | 4ba5a79 | 2002-09-30 10:23:54 +0000 | [diff] [blame] | 1269 | VG_(pp_UOperand)(u, 2, 0, False); |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 1270 | if (u->regparms_n < 2) |
| 1271 | VG_(printf)("(s)"); |
| 1272 | } |
| 1273 | if (u->argc > 2) { |
| 1274 | VG_(printf)(", "); |
njn | 4ba5a79 | 2002-09-30 10:23:54 +0000 | [diff] [blame] | 1275 | VG_(pp_UOperand)(u, 3, 0, False); |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 1276 | if (u->regparms_n < 3) |
| 1277 | VG_(printf)("(s)"); |
| 1278 | } |
| 1279 | VG_(printf)(") "); |
njn | 6431be7 | 2002-07-28 09:53:34 +0000 | [diff] [blame] | 1280 | break; |
| 1281 | |
sewardj | e104247 | 2002-09-30 12:33:11 +0000 | [diff] [blame] | 1282 | case USESEG: |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1283 | case JIFZ: |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1284 | case ADD: case ADC: case AND: case OR: |
| 1285 | case XOR: case SUB: case SBB: |
| 1286 | case SHL: case SHR: case SAR: |
jsgf | 5efa4fd | 2003-10-14 21:49:11 +0000 | [diff] [blame] | 1287 | case ROL: case ROR: case RCL: case RCR: |
| 1288 | case MUL: |
njn | 4ba5a79 | 2002-09-30 10:23:54 +0000 | [diff] [blame] | 1289 | VG_(pp_UOperand)(u, 1, u->size, False); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1290 | VG_(printf)(", "); |
njn | 4ba5a79 | 2002-09-30 10:23:54 +0000 | [diff] [blame] | 1291 | VG_(pp_UOperand)(u, 2, u->size, False); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1292 | break; |
| 1293 | |
| 1294 | case WIDEN: |
njn | 4ba5a79 | 2002-09-30 10:23:54 +0000 | [diff] [blame] | 1295 | VG_(pp_UOperand)(u, 1, u->size, False); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1296 | break; |
| 1297 | |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 1298 | default: |
| 1299 | if (VG_(needs).extended_UCode) |
njn | 4ba5a79 | 2002-09-30 10:23:54 +0000 | [diff] [blame] | 1300 | SK_(pp_XUInstr)(u); |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 1301 | else { |
| 1302 | VG_(printf)("unhandled opcode: %u. Perhaps " |
| 1303 | "VG_(needs).extended_UCode should be set?", |
| 1304 | u->opcode); |
njn | e427a66 | 2002-10-02 11:08:25 +0000 | [diff] [blame] | 1305 | VG_(core_panic)("pp_UInstr: unhandled opcode"); |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 1306 | } |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1307 | } |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1308 | if (u->flags_r != FlagsEmpty || u->flags_w != FlagsEmpty) { |
| 1309 | VG_(printf)(" ("); |
| 1310 | if (u->flags_r != FlagsEmpty) |
| 1311 | vg_ppFlagSet("-r", u->flags_r); |
| 1312 | if (u->flags_w != FlagsEmpty) |
| 1313 | vg_ppFlagSet("-w", u->flags_w); |
| 1314 | VG_(printf)(")"); |
| 1315 | } |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 1316 | |
| 1317 | if (ppRegsLiveness) { |
| 1318 | VG_(printf)("\t\t"); |
njn | 4ba5a79 | 2002-09-30 10:23:54 +0000 | [diff] [blame] | 1319 | pp_realregs_liveness ( u ); |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 1320 | } |
| 1321 | |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1322 | VG_(printf)("\n"); |
| 1323 | } |
| 1324 | |
njn | 4ba5a79 | 2002-09-30 10:23:54 +0000 | [diff] [blame] | 1325 | void VG_(pp_UInstr) ( Int instrNo, UInstr* u ) |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 1326 | { |
njn | 4ba5a79 | 2002-09-30 10:23:54 +0000 | [diff] [blame] | 1327 | pp_UInstrWorker ( instrNo, u, /*ppRegsLiveness*/False ); |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 1328 | } |
| 1329 | |
njn | 4ba5a79 | 2002-09-30 10:23:54 +0000 | [diff] [blame] | 1330 | void VG_(pp_UInstr_regs) ( Int instrNo, UInstr* u ) |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 1331 | { |
njn | 4ba5a79 | 2002-09-30 10:23:54 +0000 | [diff] [blame] | 1332 | pp_UInstrWorker ( instrNo, u, /*ppRegsLiveness*/True ); |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 1333 | } |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1334 | |
njn | 4ba5a79 | 2002-09-30 10:23:54 +0000 | [diff] [blame] | 1335 | void VG_(pp_UCodeBlock) ( UCodeBlock* cb, Char* title ) |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1336 | { |
| 1337 | Int i; |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 1338 | VG_(printf)("%s\n", title); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1339 | for (i = 0; i < cb->used; i++) |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 1340 | if (cb->instrs[i].opcode != NOP) |
njn | 4ba5a79 | 2002-09-30 10:23:54 +0000 | [diff] [blame] | 1341 | VG_(pp_UInstr) ( i, &cb->instrs[i] ); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1342 | VG_(printf)("\n"); |
| 1343 | } |
| 1344 | |
| 1345 | |
| 1346 | /*------------------------------------------------------------*/ |
| 1347 | /*--- uinstr helpers for register allocation ---*/ |
| 1348 | /*--- and code improvement. ---*/ |
| 1349 | /*------------------------------------------------------------*/ |
| 1350 | |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 1351 | /* Get the temp/reg use of a uinstr, parking them in an array supplied by |
njn | 810086f | 2002-11-14 12:42:47 +0000 | [diff] [blame] | 1352 | the caller (regs), which is assumed to be big enough. Return the number |
| 1353 | of entries. Written regs are indicated in parallel array isWrites. |
| 1354 | Insns which read _and_ write a register wind up mentioning it twice. |
| 1355 | Entries are placed in the array in program order, so that if a reg is |
| 1356 | read-modified-written, it appears first as a read and then as a write. |
| 1357 | 'tag' indicates whether we are looking at TempRegs or RealRegs. |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1358 | */ |
njn | 810086f | 2002-11-14 12:42:47 +0000 | [diff] [blame] | 1359 | Int VG_(get_reg_usage) ( UInstr* u, Tag tag, Int* regs, Bool* isWrites ) |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1360 | { |
njn | 810086f | 2002-11-14 12:42:47 +0000 | [diff] [blame] | 1361 | # define RD(ono) VG_UINSTR_READS_REG(ono, regs, isWrites) |
| 1362 | # define WR(ono) VG_UINSTR_WRITES_REG(ono, regs, isWrites) |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1363 | |
| 1364 | Int n = 0; |
| 1365 | switch (u->opcode) { |
| 1366 | case LEA1: RD(1); WR(2); break; |
| 1367 | case LEA2: RD(1); RD(2); WR(3); break; |
| 1368 | |
sewardj | 77d30a2 | 2003-10-19 08:18:52 +0000 | [diff] [blame] | 1369 | case SSE3a1_MemRd: |
sewardj | 9dd209f | 2003-06-18 23:30:52 +0000 | [diff] [blame] | 1370 | case SSE2a1_MemRd: |
nethercote | b1affa8 | 2004-01-19 19:14:18 +0000 | [diff] [blame] | 1371 | case SSE2e1_RegRd: |
sewardj | 4fbe6e9 | 2003-06-15 21:54:34 +0000 | [diff] [blame] | 1372 | case SSE3e_RegRd: |
sewardj | febaa3b | 2003-05-25 01:07:34 +0000 | [diff] [blame] | 1373 | case SSE3a_MemWr: |
| 1374 | case SSE3a_MemRd: |
| 1375 | case SSE2a_MemWr: |
sewardj | 4fbe6e9 | 2003-06-15 21:54:34 +0000 | [diff] [blame] | 1376 | case SSE3e1_RegRd: |
sewardj | 02af6bc | 2003-06-12 00:56:06 +0000 | [diff] [blame] | 1377 | case SSE2a_MemRd: RD(3); break; |
| 1378 | |
nethercote | b1affa8 | 2004-01-19 19:14:18 +0000 | [diff] [blame] | 1379 | case SSE2g_RegWr: |
| 1380 | case SSE2g1_RegWr: |
sewardj | abf8bf8 | 2003-06-15 22:28:05 +0000 | [diff] [blame] | 1381 | case SSE3e_RegWr: |
sewardj | b31b06d | 2003-06-13 00:26:02 +0000 | [diff] [blame] | 1382 | case SSE3g1_RegWr: |
sewardj | 02af6bc | 2003-06-12 00:56:06 +0000 | [diff] [blame] | 1383 | case SSE3g_RegWr: WR(3); break; |
sewardj | febaa3b | 2003-05-25 01:07:34 +0000 | [diff] [blame] | 1384 | |
sewardj | e3891fa | 2003-06-15 03:13:48 +0000 | [diff] [blame] | 1385 | case SSE3ag_MemRd_RegWr: RD(1); WR(2); break; |
| 1386 | |
thughes | 96b466a | 2004-03-15 16:43:58 +0000 | [diff] [blame] | 1387 | case MMX2a1_MemRd: RD(3); break; |
sewardj | 4fbe6e9 | 2003-06-15 21:54:34 +0000 | [diff] [blame] | 1388 | case MMX2_ERegRd: RD(2); break; |
| 1389 | case MMX2_ERegWr: WR(2); break; |
sewardj | ca86001 | 2003-03-27 23:52:58 +0000 | [diff] [blame] | 1390 | |
sewardj | a453fb0 | 2003-06-14 13:22:36 +0000 | [diff] [blame] | 1391 | case SSE4: case SSE3: case SSE5: |
sewardj | ca86001 | 2003-03-27 23:52:58 +0000 | [diff] [blame] | 1392 | case MMX1: case MMX2: case MMX3: |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 1393 | case NOP: case FPU: case INCEIP: case CALLM_S: case CALLM_E: |
sewardj | 7a5ebcf | 2002-11-13 22:42:13 +0000 | [diff] [blame] | 1394 | case CLEAR: case CALLM: case LOCK: break; |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 1395 | |
| 1396 | case CCALL: |
| 1397 | if (u->argc > 0) RD(1); |
| 1398 | if (u->argc > 1) RD(2); |
| 1399 | if (u->argc > 2) RD(3); |
| 1400 | if (u->has_ret_val) WR(3); |
| 1401 | break; |
| 1402 | |
sewardj | 3d7c9c8 | 2003-03-26 21:08:13 +0000 | [diff] [blame] | 1403 | case MMX2_MemRd: case MMX2_MemWr: |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1404 | case FPU_R: case FPU_W: RD(2); break; |
| 1405 | |
sewardj | e104247 | 2002-09-30 12:33:11 +0000 | [diff] [blame] | 1406 | case GETSEG: WR(2); break; |
| 1407 | case PUTSEG: RD(1); break; |
| 1408 | |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1409 | case GETF: WR(1); break; |
| 1410 | case PUTF: RD(1); break; |
| 1411 | |
| 1412 | case GET: WR(2); break; |
| 1413 | case PUT: RD(1); break; |
| 1414 | case LOAD: RD(1); WR(2); break; |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 1415 | case STORE: RD(1); RD(2); break; |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1416 | case MOV: RD(1); WR(2); break; |
| 1417 | |
| 1418 | case JMP: RD(1); break; |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1419 | |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 1420 | case PUSH: RD(1); break; |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1421 | case POP: WR(1); break; |
| 1422 | |
sewardj | e104247 | 2002-09-30 12:33:11 +0000 | [diff] [blame] | 1423 | case USESEG: |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1424 | case CMOV: |
| 1425 | case ADD: case ADC: case AND: case OR: |
| 1426 | case XOR: case SUB: case SBB: |
jsgf | 5efa4fd | 2003-10-14 21:49:11 +0000 | [diff] [blame] | 1427 | case MUL: |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1428 | RD(1); RD(2); WR(2); break; |
| 1429 | |
| 1430 | case SHL: case SHR: case SAR: |
| 1431 | case ROL: case ROR: case RCL: case RCR: |
| 1432 | RD(1); RD(2); WR(2); break; |
| 1433 | |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 1434 | case NOT: case NEG: case INC: case DEC: case BSWAP: |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1435 | RD(1); WR(1); break; |
| 1436 | |
| 1437 | case WIDEN: RD(1); WR(1); break; |
| 1438 | |
| 1439 | case CC2VAL: WR(1); break; |
| 1440 | case JIFZ: RD(1); break; |
| 1441 | |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 1442 | default: |
| 1443 | if (VG_(needs).extended_UCode) |
njn | 810086f | 2002-11-14 12:42:47 +0000 | [diff] [blame] | 1444 | return SK_(get_Xreg_usage)(u, tag, regs, isWrites); |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 1445 | else { |
| 1446 | VG_(printf)("unhandled opcode: %u. Perhaps " |
| 1447 | "VG_(needs).extended_UCode should be set?", |
| 1448 | u->opcode); |
njn | e427a66 | 2002-10-02 11:08:25 +0000 | [diff] [blame] | 1449 | VG_(core_panic)("VG_(get_reg_usage): unhandled opcode"); |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 1450 | } |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1451 | } |
| 1452 | return n; |
| 1453 | |
| 1454 | # undef RD |
| 1455 | # undef WR |
| 1456 | } |
| 1457 | |
| 1458 | |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 1459 | /* Change temp regs in u into real regs, as directed by the |
| 1460 | * temps[i]-->reals[i] mapping. */ |
sewardj | 5686735 | 2003-10-12 10:27:06 +0000 | [diff] [blame] | 1461 | static |
njn | 810086f | 2002-11-14 12:42:47 +0000 | [diff] [blame] | 1462 | void patchUInstr ( UInstr* u, Int temps[], UInt reals[], Int n_tmap ) |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1463 | { |
| 1464 | Int i; |
| 1465 | if (u->tag1 == TempReg) { |
| 1466 | for (i = 0; i < n_tmap; i++) |
njn | 810086f | 2002-11-14 12:42:47 +0000 | [diff] [blame] | 1467 | if (temps[i] == u->val1) break; |
njn | e427a66 | 2002-10-02 11:08:25 +0000 | [diff] [blame] | 1468 | if (i == n_tmap) VG_(core_panic)("patchUInstr(1)"); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1469 | u->tag1 = RealReg; |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 1470 | u->val1 = reals[i]; |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1471 | } |
| 1472 | if (u->tag2 == TempReg) { |
| 1473 | for (i = 0; i < n_tmap; i++) |
njn | 810086f | 2002-11-14 12:42:47 +0000 | [diff] [blame] | 1474 | if (temps[i] == u->val2) break; |
njn | e427a66 | 2002-10-02 11:08:25 +0000 | [diff] [blame] | 1475 | if (i == n_tmap) VG_(core_panic)("patchUInstr(2)"); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1476 | u->tag2 = RealReg; |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 1477 | u->val2 = reals[i]; |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1478 | } |
| 1479 | if (u->tag3 == TempReg) { |
| 1480 | for (i = 0; i < n_tmap; i++) |
njn | 810086f | 2002-11-14 12:42:47 +0000 | [diff] [blame] | 1481 | if (temps[i] == u->val3) break; |
njn | e427a66 | 2002-10-02 11:08:25 +0000 | [diff] [blame] | 1482 | if (i == n_tmap) VG_(core_panic)("patchUInstr(3)"); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1483 | u->tag3 = RealReg; |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 1484 | u->val3 = reals[i]; |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1485 | } |
| 1486 | } |
| 1487 | |
| 1488 | |
| 1489 | /* Tedious x86-specific hack which compensates for the fact that the |
| 1490 | register numbers for %ah .. %dh do not correspond to those for %eax |
| 1491 | .. %edx. It maps a (reg size, reg no) pair to the number of the |
| 1492 | containing 32-bit reg. */ |
| 1493 | static __inline__ |
| 1494 | Int containingArchRegOf ( Int sz, Int aregno ) |
| 1495 | { |
| 1496 | switch (sz) { |
| 1497 | case 4: return aregno; |
| 1498 | case 2: return aregno; |
| 1499 | case 1: return aregno >= 4 ? aregno-4 : aregno; |
njn | e427a66 | 2002-10-02 11:08:25 +0000 | [diff] [blame] | 1500 | default: VG_(core_panic)("containingArchRegOf"); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1501 | } |
| 1502 | } |
| 1503 | |
| 1504 | |
| 1505 | /* If u reads an ArchReg, return the number of the containing arch |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 1506 | reg. Otherwise return -1. Used in redundant-PUT elimination. |
nethercote | 996901a | 2004-08-03 13:29:09 +0000 | [diff] [blame] | 1507 | Note that this is not required for tools extending UCode because |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 1508 | this happens before instrumentation. */ |
sewardj | 5686735 | 2003-10-12 10:27:06 +0000 | [diff] [blame] | 1509 | static |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1510 | Int maybe_uinstrReadsArchReg ( UInstr* u ) |
| 1511 | { |
| 1512 | switch (u->opcode) { |
| 1513 | case GET: |
| 1514 | case ADD: case ADC: case AND: case OR: |
| 1515 | case XOR: case SUB: case SBB: |
| 1516 | case SHL: case SHR: case SAR: case ROL: |
| 1517 | case ROR: case RCL: case RCR: |
jsgf | 5efa4fd | 2003-10-14 21:49:11 +0000 | [diff] [blame] | 1518 | case MUL: |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1519 | if (u->tag1 == ArchReg) |
| 1520 | return containingArchRegOf ( u->size, u->val1 ); |
| 1521 | else |
| 1522 | return -1; |
| 1523 | |
| 1524 | case GETF: case PUTF: |
| 1525 | case CALLM_S: case CALLM_E: |
| 1526 | case INCEIP: |
| 1527 | case LEA1: |
| 1528 | case LEA2: |
| 1529 | case NOP: |
sewardj | 7a5ebcf | 2002-11-13 22:42:13 +0000 | [diff] [blame] | 1530 | case LOCK: |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1531 | case PUT: |
| 1532 | case LOAD: |
| 1533 | case STORE: |
| 1534 | case MOV: |
| 1535 | case CMOV: |
| 1536 | case JMP: |
| 1537 | case CALLM: case CLEAR: case PUSH: case POP: |
| 1538 | case NOT: case NEG: case INC: case DEC: case BSWAP: |
| 1539 | case CC2VAL: |
| 1540 | case JIFZ: |
| 1541 | case FPU: case FPU_R: case FPU_W: |
sewardj | ca86001 | 2003-03-27 23:52:58 +0000 | [diff] [blame] | 1542 | case MMX1: case MMX2: case MMX3: |
thughes | 96b466a | 2004-03-15 16:43:58 +0000 | [diff] [blame] | 1543 | case MMX2_MemRd: case MMX2_MemWr: case MMX2a1_MemRd: |
sewardj | 4fbe6e9 | 2003-06-15 21:54:34 +0000 | [diff] [blame] | 1544 | case MMX2_ERegRd: case MMX2_ERegWr: |
sewardj | 9dd209f | 2003-06-18 23:30:52 +0000 | [diff] [blame] | 1545 | case SSE2a_MemWr: case SSE2a_MemRd: case SSE2a1_MemRd: |
nethercote | b1affa8 | 2004-01-19 19:14:18 +0000 | [diff] [blame] | 1546 | case SSE2g_RegWr: case SSE2g1_RegWr: case SSE2e1_RegRd: |
sewardj | 77d30a2 | 2003-10-19 08:18:52 +0000 | [diff] [blame] | 1547 | case SSE3a_MemWr: case SSE3a_MemRd: case SSE3a1_MemRd: |
sewardj | abf8bf8 | 2003-06-15 22:28:05 +0000 | [diff] [blame] | 1548 | case SSE3e_RegRd: case SSE3g_RegWr: case SSE3e_RegWr: |
sewardj | 4fbe6e9 | 2003-06-15 21:54:34 +0000 | [diff] [blame] | 1549 | case SSE3g1_RegWr: case SSE3e1_RegRd: |
sewardj | e3891fa | 2003-06-15 03:13:48 +0000 | [diff] [blame] | 1550 | case SSE4: case SSE3: case SSE5: case SSE3ag_MemRd_RegWr: |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1551 | case WIDEN: |
sewardj | e104247 | 2002-09-30 12:33:11 +0000 | [diff] [blame] | 1552 | /* GETSEG and USESEG are to do with ArchRegS, not ArchReg */ |
| 1553 | case GETSEG: case PUTSEG: |
| 1554 | case USESEG: |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1555 | return -1; |
| 1556 | |
| 1557 | default: |
njn | 4ba5a79 | 2002-09-30 10:23:54 +0000 | [diff] [blame] | 1558 | VG_(pp_UInstr)(0,u); |
njn | e427a66 | 2002-10-02 11:08:25 +0000 | [diff] [blame] | 1559 | VG_(core_panic)("maybe_uinstrReadsArchReg: unhandled opcode"); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1560 | } |
| 1561 | } |
| 1562 | |
| 1563 | static __inline__ |
| 1564 | Bool uInstrMentionsTempReg ( UInstr* u, Int tempreg ) |
| 1565 | { |
| 1566 | Int i, k; |
njn | f4ce3d3 | 2003-02-10 10:17:26 +0000 | [diff] [blame] | 1567 | Int tempUse[VG_MAX_REGS_USED]; |
| 1568 | Bool notUsed[VG_MAX_REGS_USED]; |
njn | 810086f | 2002-11-14 12:42:47 +0000 | [diff] [blame] | 1569 | |
| 1570 | k = VG_(get_reg_usage) ( u, TempReg, &tempUse[0], ¬Used[0] ); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1571 | for (i = 0; i < k; i++) |
njn | 810086f | 2002-11-14 12:42:47 +0000 | [diff] [blame] | 1572 | if (tempUse[i] == tempreg) |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1573 | return True; |
| 1574 | return False; |
| 1575 | } |
| 1576 | |
| 1577 | |
| 1578 | /*------------------------------------------------------------*/ |
| 1579 | /*--- ucode improvement. ---*/ |
| 1580 | /*------------------------------------------------------------*/ |
| 1581 | |
| 1582 | /* Improve the code in cb by doing |
| 1583 | -- Redundant ArchReg-fetch elimination |
| 1584 | -- Redundant PUT elimination |
| 1585 | -- Redundant cond-code restore/save elimination |
| 1586 | The overall effect of these is to allow target registers to be |
| 1587 | cached in host registers over multiple target insns. |
| 1588 | */ |
| 1589 | static void vg_improve ( UCodeBlock* cb ) |
| 1590 | { |
| 1591 | Int i, j, k, m, n, ar, tr, told, actual_areg; |
nethercote | c06e213 | 2004-09-03 13:45:29 +0000 | [diff] [blame] | 1592 | Int areg_map[N_ARCH_REGS]; |
| 1593 | Bool annul_put[N_ARCH_REGS]; |
njn | f4ce3d3 | 2003-02-10 10:17:26 +0000 | [diff] [blame] | 1594 | Int tempUse[VG_MAX_REGS_USED]; |
| 1595 | Bool isWrites[VG_MAX_REGS_USED]; |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1596 | UInstr* u; |
| 1597 | Bool wr; |
| 1598 | Int* last_live_before; |
| 1599 | FlagSet future_dead_flags; |
| 1600 | |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 1601 | if (dis) |
| 1602 | VG_(printf) ("Improvements:\n"); |
| 1603 | |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1604 | if (cb->nextTemp > 0) |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 1605 | last_live_before = VG_(arena_malloc) ( VG_AR_JITTER, |
| 1606 | cb->nextTemp * sizeof(Int) ); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1607 | else |
| 1608 | last_live_before = NULL; |
| 1609 | |
| 1610 | |
| 1611 | /* PASS 1: redundant GET elimination. (Actually, more general than |
| 1612 | that -- eliminates redundant fetches of ArchRegs). */ |
| 1613 | |
| 1614 | /* Find the live-range-ends for all temporaries. Duplicates code |
| 1615 | in the register allocator :-( */ |
| 1616 | |
| 1617 | for (i = 0; i < cb->nextTemp; i++) last_live_before[i] = -1; |
| 1618 | |
| 1619 | for (i = cb->used-1; i >= 0; i--) { |
| 1620 | u = &cb->instrs[i]; |
| 1621 | |
njn | 810086f | 2002-11-14 12:42:47 +0000 | [diff] [blame] | 1622 | k = VG_(get_reg_usage)(u, TempReg, &tempUse[0], &isWrites[0]); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1623 | |
| 1624 | /* For each temp usage ... bwds in program order. */ |
| 1625 | for (j = k-1; j >= 0; j--) { |
njn | 810086f | 2002-11-14 12:42:47 +0000 | [diff] [blame] | 1626 | tr = tempUse[j]; |
| 1627 | wr = isWrites[j]; |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1628 | if (last_live_before[tr] == -1) { |
| 1629 | vg_assert(tr >= 0 && tr < cb->nextTemp); |
| 1630 | last_live_before[tr] = wr ? (i+1) : i; |
| 1631 | } |
| 1632 | } |
| 1633 | |
| 1634 | } |
| 1635 | |
| 1636 | # define BIND_ARCH_TO_TEMP(archreg,tempreg)\ |
| 1637 | { Int q; \ |
| 1638 | /* Invalidate any old binding(s) to tempreg. */ \ |
nethercote | c06e213 | 2004-09-03 13:45:29 +0000 | [diff] [blame] | 1639 | for (q = 0; q < N_ARCH_REGS; q++) \ |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1640 | if (areg_map[q] == tempreg) areg_map[q] = -1; \ |
| 1641 | /* Add the new binding. */ \ |
| 1642 | areg_map[archreg] = (tempreg); \ |
| 1643 | } |
| 1644 | |
| 1645 | /* Set up the A-reg map. */ |
nethercote | c06e213 | 2004-09-03 13:45:29 +0000 | [diff] [blame] | 1646 | for (i = 0; i < N_ARCH_REGS; i++) areg_map[i] = -1; |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1647 | |
| 1648 | /* Scan insns. */ |
| 1649 | for (i = 0; i < cb->used; i++) { |
| 1650 | u = &cb->instrs[i]; |
| 1651 | if (u->opcode == GET && u->size == 4) { |
| 1652 | /* GET; see if it can be annulled. */ |
| 1653 | vg_assert(u->tag1 == ArchReg); |
| 1654 | vg_assert(u->tag2 == TempReg); |
| 1655 | ar = u->val1; |
| 1656 | tr = u->val2; |
| 1657 | told = areg_map[ar]; |
| 1658 | if (told != -1 && last_live_before[told] <= i) { |
| 1659 | /* ar already has an old mapping to told, but that runs |
| 1660 | out here. Annul this GET, rename tr to told for the |
| 1661 | rest of the block, and extend told's live range to that |
| 1662 | of tr. */ |
njn | 4ba5a79 | 2002-09-30 10:23:54 +0000 | [diff] [blame] | 1663 | VG_(new_NOP)(u); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1664 | n = last_live_before[tr] + 1; |
| 1665 | if (n > cb->used) n = cb->used; |
| 1666 | last_live_before[told] = last_live_before[tr]; |
| 1667 | last_live_before[tr] = i-1; |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 1668 | if (dis) |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1669 | VG_(printf)( |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 1670 | " at %2d: delete GET, rename t%d to t%d in (%d .. %d)\n", |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1671 | i, tr, told,i+1, n-1); |
| 1672 | for (m = i+1; m < n; m++) { |
| 1673 | if (cb->instrs[m].tag1 == TempReg |
| 1674 | && cb->instrs[m].val1 == tr) |
| 1675 | cb->instrs[m].val1 = told; |
| 1676 | if (cb->instrs[m].tag2 == TempReg |
| 1677 | && cb->instrs[m].val2 == tr) |
| 1678 | cb->instrs[m].val2 = told; |
sewardj | febaa3b | 2003-05-25 01:07:34 +0000 | [diff] [blame] | 1679 | if (cb->instrs[m].tag3 == TempReg |
| 1680 | && cb->instrs[m].val3 == tr) |
| 1681 | cb->instrs[m].val3 = told; |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1682 | } |
| 1683 | BIND_ARCH_TO_TEMP(ar,told); |
| 1684 | } |
| 1685 | else |
| 1686 | BIND_ARCH_TO_TEMP(ar,tr); |
| 1687 | } |
| 1688 | else if (u->opcode == GET && u->size != 4) { |
| 1689 | /* Invalidate any mapping for this archreg. */ |
| 1690 | actual_areg = containingArchRegOf ( u->size, u->val1 ); |
| 1691 | areg_map[actual_areg] = -1; |
| 1692 | } |
| 1693 | else if (u->opcode == PUT && u->size == 4) { |
| 1694 | /* PUT; re-establish t -> a binding */ |
| 1695 | vg_assert(u->tag1 == TempReg); |
| 1696 | vg_assert(u->tag2 == ArchReg); |
| 1697 | BIND_ARCH_TO_TEMP(u->val2, u->val1); |
| 1698 | } |
| 1699 | else if (u->opcode == PUT && u->size != 4) { |
| 1700 | /* Invalidate any mapping for this archreg. */ |
| 1701 | actual_areg = containingArchRegOf ( u->size, u->val2 ); |
| 1702 | areg_map[actual_areg] = -1; |
| 1703 | } else { |
| 1704 | |
| 1705 | /* see if insn has an archreg as a read operand; if so try to |
| 1706 | map it. */ |
| 1707 | if (u->tag1 == ArchReg && u->size == 4 |
| 1708 | && areg_map[u->val1] != -1) { |
| 1709 | switch (u->opcode) { |
| 1710 | case ADD: case SUB: case AND: case OR: case XOR: |
| 1711 | case ADC: case SBB: |
| 1712 | case SHL: case SHR: case SAR: case ROL: case ROR: |
| 1713 | case RCL: case RCR: |
jsgf | 5efa4fd | 2003-10-14 21:49:11 +0000 | [diff] [blame] | 1714 | case MUL: |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 1715 | if (dis) |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1716 | VG_(printf)( |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 1717 | " at %2d: change ArchReg %S to TempReg t%d\n", |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1718 | i, nameIReg(4,u->val1), areg_map[u->val1]); |
| 1719 | u->tag1 = TempReg; |
| 1720 | u->val1 = areg_map[u->val1]; |
| 1721 | /* Remember to extend the live range of the TempReg, |
| 1722 | if necessary. */ |
| 1723 | if (last_live_before[u->val1] < i) |
| 1724 | last_live_before[u->val1] = i; |
| 1725 | break; |
| 1726 | default: |
| 1727 | break; |
| 1728 | } |
| 1729 | } |
| 1730 | |
| 1731 | /* boring insn; invalidate any mappings to temps it writes */ |
njn | 810086f | 2002-11-14 12:42:47 +0000 | [diff] [blame] | 1732 | k = VG_(get_reg_usage)(u, TempReg, &tempUse[0], &isWrites[0]); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1733 | |
| 1734 | for (j = 0; j < k; j++) { |
njn | 810086f | 2002-11-14 12:42:47 +0000 | [diff] [blame] | 1735 | wr = isWrites[j]; |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1736 | if (!wr) continue; |
njn | 810086f | 2002-11-14 12:42:47 +0000 | [diff] [blame] | 1737 | tr = tempUse[j]; |
nethercote | c06e213 | 2004-09-03 13:45:29 +0000 | [diff] [blame] | 1738 | for (m = 0; m < N_ARCH_REGS; m++) |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1739 | if (areg_map[m] == tr) areg_map[m] = -1; |
| 1740 | } |
| 1741 | } |
| 1742 | |
| 1743 | } |
| 1744 | |
| 1745 | # undef BIND_ARCH_TO_TEMP |
| 1746 | |
sewardj | 05f1aa1 | 2002-04-30 00:29:36 +0000 | [diff] [blame] | 1747 | /* PASS 2: redundant PUT elimination. Don't annul (delay) puts of |
| 1748 | %ESP, since the memory check machinery always requires the |
| 1749 | in-memory value of %ESP to be up to date. Although this isn't |
| 1750 | actually required by other analyses (cache simulation), it's |
| 1751 | simplest to be consistent for all end-uses. */ |
nethercote | c06e213 | 2004-09-03 13:45:29 +0000 | [diff] [blame] | 1752 | for (j = 0; j < N_ARCH_REGS; j++) |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1753 | annul_put[j] = False; |
| 1754 | |
| 1755 | for (i = cb->used-1; i >= 0; i--) { |
| 1756 | u = &cb->instrs[i]; |
| 1757 | if (u->opcode == NOP) continue; |
| 1758 | |
| 1759 | if (u->opcode == PUT && u->size == 4) { |
| 1760 | vg_assert(u->tag2 == ArchReg); |
| 1761 | actual_areg = containingArchRegOf ( 4, u->val2 ); |
| 1762 | if (annul_put[actual_areg]) { |
sewardj | 05f1aa1 | 2002-04-30 00:29:36 +0000 | [diff] [blame] | 1763 | vg_assert(actual_areg != R_ESP); |
njn | 4ba5a79 | 2002-09-30 10:23:54 +0000 | [diff] [blame] | 1764 | VG_(new_NOP)(u); |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 1765 | if (dis) |
| 1766 | VG_(printf)(" at %2d: delete PUT\n", i ); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1767 | } else { |
sewardj | 05f1aa1 | 2002-04-30 00:29:36 +0000 | [diff] [blame] | 1768 | if (actual_areg != R_ESP) |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1769 | annul_put[actual_areg] = True; |
| 1770 | } |
| 1771 | } |
| 1772 | else if (u->opcode == PUT && u->size != 4) { |
| 1773 | actual_areg = containingArchRegOf ( u->size, u->val2 ); |
| 1774 | annul_put[actual_areg] = False; |
| 1775 | } |
| 1776 | else if (u->opcode == JMP || u->opcode == JIFZ |
| 1777 | || u->opcode == CALLM) { |
nethercote | c06e213 | 2004-09-03 13:45:29 +0000 | [diff] [blame] | 1778 | for (j = 0; j < N_ARCH_REGS; j++) |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1779 | annul_put[j] = False; |
| 1780 | } |
| 1781 | else { |
| 1782 | /* If an instruction reads an ArchReg, the immediately |
| 1783 | preceding PUT cannot be annulled. */ |
| 1784 | actual_areg = maybe_uinstrReadsArchReg ( u ); |
| 1785 | if (actual_areg != -1) |
| 1786 | annul_put[actual_areg] = False; |
| 1787 | } |
| 1788 | } |
| 1789 | |
| 1790 | /* PASS 2a: redundant-move elimination. Given MOV t1, t2 and t1 is |
| 1791 | dead after this point, annul the MOV insn and rename t2 to t1. |
| 1792 | Further modifies the last_live_before map. */ |
| 1793 | |
| 1794 | # if 0 |
njn | 4ba5a79 | 2002-09-30 10:23:54 +0000 | [diff] [blame] | 1795 | VG_(pp_UCodeBlock)(cb, "Before MOV elimination" ); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1796 | for (i = 0; i < cb->nextTemp; i++) |
| 1797 | VG_(printf)("llb[t%d]=%d ", i, last_live_before[i]); |
| 1798 | VG_(printf)("\n"); |
| 1799 | # endif |
| 1800 | |
| 1801 | for (i = 0; i < cb->used-1; i++) { |
| 1802 | u = &cb->instrs[i]; |
| 1803 | if (u->opcode != MOV) continue; |
| 1804 | if (u->tag1 == Literal) continue; |
| 1805 | vg_assert(u->tag1 == TempReg); |
| 1806 | vg_assert(u->tag2 == TempReg); |
| 1807 | if (last_live_before[u->val1] == i) { |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 1808 | if (dis) |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1809 | VG_(printf)( |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 1810 | " at %2d: delete MOV, rename t%d to t%d in (%d .. %d)\n", |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1811 | i, u->val2, u->val1, i+1, last_live_before[u->val2] ); |
| 1812 | for (j = i+1; j <= last_live_before[u->val2]; j++) { |
| 1813 | if (cb->instrs[j].tag1 == TempReg |
| 1814 | && cb->instrs[j].val1 == u->val2) |
| 1815 | cb->instrs[j].val1 = u->val1; |
| 1816 | if (cb->instrs[j].tag2 == TempReg |
| 1817 | && cb->instrs[j].val2 == u->val2) |
| 1818 | cb->instrs[j].val2 = u->val1; |
sewardj | febaa3b | 2003-05-25 01:07:34 +0000 | [diff] [blame] | 1819 | if (cb->instrs[j].tag3 == TempReg |
| 1820 | && cb->instrs[j].val3 == u->val2) |
| 1821 | cb->instrs[j].val3 = u->val1; |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1822 | } |
| 1823 | last_live_before[u->val1] = last_live_before[u->val2]; |
| 1824 | last_live_before[u->val2] = i-1; |
njn | 4ba5a79 | 2002-09-30 10:23:54 +0000 | [diff] [blame] | 1825 | VG_(new_NOP)(u); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1826 | } |
| 1827 | } |
| 1828 | |
| 1829 | /* PASS 3: redundant condition-code restore/save elimination. |
| 1830 | Scan backwards from the end. future_dead_flags records the set |
| 1831 | of flags which are dead at this point, that is, will be written |
| 1832 | before they are next read. Earlier uinsns which write flags |
| 1833 | already in future_dead_flags can have their writes annulled. |
| 1834 | */ |
| 1835 | future_dead_flags = FlagsEmpty; |
| 1836 | |
| 1837 | for (i = cb->used-1; i >= 0; i--) { |
| 1838 | u = &cb->instrs[i]; |
| 1839 | |
| 1840 | /* We might never make it to insns beyond this one, so be |
| 1841 | conservative. */ |
| 1842 | if (u->opcode == JIFZ || u->opcode == JMP) { |
| 1843 | future_dead_flags = FlagsEmpty; |
| 1844 | continue; |
| 1845 | } |
| 1846 | |
sewardj | fbb6cda | 2002-07-24 09:33:52 +0000 | [diff] [blame] | 1847 | /* PUTF modifies the %EFLAGS in essentially unpredictable ways. |
| 1848 | For example people try to mess with bit 21 to see if CPUID |
| 1849 | works. The setting may or may not actually take hold. So we |
| 1850 | play safe here. */ |
| 1851 | if (u->opcode == PUTF) { |
| 1852 | future_dead_flags = FlagsEmpty; |
| 1853 | continue; |
| 1854 | } |
| 1855 | |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1856 | /* We can annul the flags written by this insn if it writes a |
| 1857 | subset (or eq) of the set of flags known to be dead after |
| 1858 | this insn. If not, just record the flags also written by |
| 1859 | this insn.*/ |
| 1860 | if (u->flags_w != FlagsEmpty |
| 1861 | && VG_IS_FLAG_SUBSET(u->flags_w, future_dead_flags)) { |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 1862 | if (dis) { |
| 1863 | VG_(printf)(" at %2d: annul flag write ", i); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1864 | vg_ppFlagSet("", u->flags_w); |
| 1865 | VG_(printf)(" due to later "); |
| 1866 | vg_ppFlagSet("", future_dead_flags); |
| 1867 | VG_(printf)("\n"); |
| 1868 | } |
| 1869 | u->flags_w = FlagsEmpty; |
| 1870 | } else { |
| 1871 | future_dead_flags |
| 1872 | = VG_UNION_FLAG_SETS ( u->flags_w, future_dead_flags ); |
| 1873 | } |
| 1874 | |
| 1875 | /* If this insn also reads flags, empty out future_dead_flags so |
| 1876 | as to force preceding writes not to be annulled. */ |
| 1877 | if (u->flags_r != FlagsEmpty) |
| 1878 | future_dead_flags = FlagsEmpty; |
| 1879 | } |
| 1880 | |
| 1881 | if (last_live_before) |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 1882 | VG_(arena_free) ( VG_AR_JITTER, last_live_before ); |
| 1883 | |
| 1884 | if (dis) { |
| 1885 | VG_(printf)("\n"); |
njn | 4ba5a79 | 2002-09-30 10:23:54 +0000 | [diff] [blame] | 1886 | VG_(pp_UCodeBlock) ( cb, "Improved UCode:" ); |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 1887 | } |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1888 | } |
| 1889 | |
njn | 9b007f6 | 2003-04-07 14:40:25 +0000 | [diff] [blame] | 1890 | /*------------------------------------------------------------*/ |
| 1891 | /*--- %ESP-update pass ---*/ |
| 1892 | /*------------------------------------------------------------*/ |
| 1893 | |
nethercote | 996901a | 2004-08-03 13:29:09 +0000 | [diff] [blame] | 1894 | /* For tools that want to know about %ESP changes, this pass adds |
| 1895 | in the appropriate hooks. We have to do it after the tool's |
| 1896 | instrumentation, so the tool doesn't have to worry about the CCALLs |
njn | 9b007f6 | 2003-04-07 14:40:25 +0000 | [diff] [blame] | 1897 | it adds in, and we must do it before register allocation because |
| 1898 | spilled temps make it much harder to work out the %esp deltas. |
njn | ed61971 | 2003-10-01 16:45:04 +0000 | [diff] [blame] | 1899 | Thus we have it as an extra phase between the two. |
| 1900 | |
| 1901 | We look for "GETL %ESP, t_ESP", then track ADDs and SUBs of |
| 1902 | literal values to t_ESP, and the total delta of the ADDs/SUBs. Then if |
| 1903 | "PUTL t_ESP, %ESP" happens, we call the helper with the known delta. We |
| 1904 | also cope with "MOVL t_ESP, tX", making tX the new t_ESP. If any other |
| 1905 | instruction clobbers t_ESP, we don't track it anymore, and fall back to |
| 1906 | the delta-is-unknown case. That case is also used when the delta is not |
| 1907 | a nice small amount, or an unknown amount. |
| 1908 | */ |
njn | 9b007f6 | 2003-04-07 14:40:25 +0000 | [diff] [blame] | 1909 | static |
| 1910 | UCodeBlock* vg_ESP_update_pass(UCodeBlock* cb_in) |
| 1911 | { |
| 1912 | UCodeBlock* cb; |
| 1913 | UInstr* u; |
| 1914 | Int delta = 0; |
| 1915 | UInt t_ESP = INVALID_TEMPREG; |
sewardj | 05bcdcb | 2003-05-18 10:05:38 +0000 | [diff] [blame] | 1916 | Int i; |
njn | 9b007f6 | 2003-04-07 14:40:25 +0000 | [diff] [blame] | 1917 | |
| 1918 | cb = VG_(setup_UCodeBlock)(cb_in); |
| 1919 | |
| 1920 | for (i = 0; i < VG_(get_num_instrs)(cb_in); i++) { |
| 1921 | u = VG_(get_instr)(cb_in, i); |
| 1922 | |
| 1923 | if (GET == u->opcode && R_ESP == u->val1) { |
| 1924 | t_ESP = u->val2; |
| 1925 | delta = 0; |
| 1926 | |
| 1927 | } else if (PUT == u->opcode && R_ESP == u->val2 && 4 == u->size) { |
| 1928 | |
fitzhardinge | 98abfc7 | 2003-12-16 02:05:15 +0000 | [diff] [blame] | 1929 | # define DO_GENERIC \ |
| 1930 | if (VG_(defined_new_mem_stack)() || \ |
| 1931 | VG_(defined_die_mem_stack)()) { \ |
| 1932 | uInstr1(cb, CCALL, 0, TempReg, u->val1); \ |
| 1933 | uCCall(cb, (Addr) VG_(unknown_esp_update), \ |
| 1934 | 1, 1, False); \ |
njn | 9b007f6 | 2003-04-07 14:40:25 +0000 | [diff] [blame] | 1935 | } |
| 1936 | |
fitzhardinge | 98abfc7 | 2003-12-16 02:05:15 +0000 | [diff] [blame] | 1937 | # define DO(kind, size) \ |
| 1938 | if (VG_(defined_##kind##_mem_stack_##size)()) { \ |
| 1939 | uInstr1(cb, CCALL, 0, TempReg, u->val1); \ |
| 1940 | uCCall(cb, (Addr) VG_(tool_interface).track_##kind##_mem_stack_##size, \ |
| 1941 | 1, 1, False); \ |
| 1942 | \ |
| 1943 | } else \ |
| 1944 | DO_GENERIC \ |
njn | 9b007f6 | 2003-04-07 14:40:25 +0000 | [diff] [blame] | 1945 | break |
| 1946 | |
| 1947 | if (u->val1 == t_ESP) { |
| 1948 | /* Known delta, common cases handled specially. */ |
| 1949 | switch (delta) { |
njn | ed61971 | 2003-10-01 16:45:04 +0000 | [diff] [blame] | 1950 | case 0: break; |
njn | 9b007f6 | 2003-04-07 14:40:25 +0000 | [diff] [blame] | 1951 | case 4: DO(die, 4); |
| 1952 | case -4: DO(new, 4); |
| 1953 | case 8: DO(die, 8); |
| 1954 | case -8: DO(new, 8); |
| 1955 | case 12: DO(die, 12); |
| 1956 | case -12: DO(new, 12); |
| 1957 | case 16: DO(die, 16); |
| 1958 | case -16: DO(new, 16); |
| 1959 | case 32: DO(die, 32); |
| 1960 | case -32: DO(new, 32); |
| 1961 | default: DO_GENERIC; break; |
| 1962 | } |
| 1963 | } else { |
| 1964 | /* Unknown delta */ |
| 1965 | DO_GENERIC; |
njn | ed61971 | 2003-10-01 16:45:04 +0000 | [diff] [blame] | 1966 | |
daywalker | 972a759 | 2003-10-01 10:19:08 +0000 | [diff] [blame] | 1967 | /* now we know the temp that points to %ESP */ |
njn | ed61971 | 2003-10-01 16:45:04 +0000 | [diff] [blame] | 1968 | t_ESP = u->val1; |
njn | 9b007f6 | 2003-04-07 14:40:25 +0000 | [diff] [blame] | 1969 | } |
| 1970 | delta = 0; |
| 1971 | |
| 1972 | # undef DO |
| 1973 | # undef DO_GENERIC |
| 1974 | |
njn | ed61971 | 2003-10-01 16:45:04 +0000 | [diff] [blame] | 1975 | } else if (ADD == u->opcode && Literal == u->tag1 && t_ESP == u->val2) { |
| 1976 | delta += u->lit32; |
| 1977 | |
| 1978 | } else if (SUB == u->opcode && Literal == u->tag1 && t_ESP == u->val2) { |
| 1979 | delta -= u->lit32; |
njn | 9b007f6 | 2003-04-07 14:40:25 +0000 | [diff] [blame] | 1980 | |
| 1981 | } else if (MOV == u->opcode && TempReg == u->tag1 && t_ESP == u->val1 && |
| 1982 | TempReg == u->tag2) { |
njn | ed61971 | 2003-10-01 16:45:04 +0000 | [diff] [blame] | 1983 | // t_ESP is transferred |
njn | 9b007f6 | 2003-04-07 14:40:25 +0000 | [diff] [blame] | 1984 | t_ESP = u->val2; |
njn | ed61971 | 2003-10-01 16:45:04 +0000 | [diff] [blame] | 1985 | |
| 1986 | } else { |
| 1987 | // Stop tracking t_ESP if it's clobbered by this instruction. |
| 1988 | Int tempUse [VG_MAX_REGS_USED]; |
| 1989 | Bool isWrites[VG_MAX_REGS_USED]; |
| 1990 | Int j, n = VG_(get_reg_usage)(u, TempReg, tempUse, isWrites); |
| 1991 | |
| 1992 | for (j = 0; j < n; j++) { |
| 1993 | if (tempUse[j] == t_ESP && isWrites[j]) |
| 1994 | t_ESP = INVALID_TEMPREG; |
| 1995 | } |
njn | 9b007f6 | 2003-04-07 14:40:25 +0000 | [diff] [blame] | 1996 | } |
| 1997 | VG_(copy_UInstr) ( cb, u ); |
| 1998 | } |
| 1999 | |
| 2000 | VG_(free_UCodeBlock)(cb_in); |
| 2001 | return cb; |
| 2002 | } |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 2003 | |
| 2004 | /*------------------------------------------------------------*/ |
| 2005 | /*--- The new register allocator. ---*/ |
| 2006 | /*------------------------------------------------------------*/ |
| 2007 | |
| 2008 | typedef |
| 2009 | struct { |
| 2010 | /* Becomes live for the first time after this insn ... */ |
| 2011 | Int live_after; |
jseward | fa70a8e | 2004-07-01 11:38:36 +0000 | [diff] [blame] | 2012 | /* Becomes dead for the last time before this insn ... */ |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 2013 | Int dead_before; |
| 2014 | /* The "home" spill slot, if needed. Never changes. */ |
| 2015 | Int spill_no; |
| 2016 | /* Where is it? VG_NOVALUE==in a spill slot; else in reg. */ |
| 2017 | Int real_no; |
| 2018 | } |
| 2019 | TempInfo; |
| 2020 | |
| 2021 | |
| 2022 | /* Take a ucode block and allocate its TempRegs to RealRegs, or put |
| 2023 | them in spill locations, and add spill code, if there are not |
| 2024 | enough real regs. The usual register allocation deal, in short. |
| 2025 | |
| 2026 | Important redundancy of representation: |
| 2027 | |
| 2028 | real_to_temp maps real reg ranks (RRRs) to TempReg nos, or |
| 2029 | to VG_NOVALUE if the real reg has no currently assigned TempReg. |
| 2030 | |
| 2031 | The .real_no field of a TempInfo gives the current RRR for |
| 2032 | this TempReg, or VG_NOVALUE if the TempReg is currently |
| 2033 | in memory, in which case it is in the SpillNo denoted by |
| 2034 | spillno. |
| 2035 | |
| 2036 | These pieces of information (a fwds-bwds mapping, really) must |
| 2037 | be kept consistent! |
| 2038 | |
| 2039 | This allocator uses the so-called Second Chance Bin Packing |
| 2040 | algorithm, as described in "Quality and Speed in Linear-scan |
| 2041 | Register Allocation" (Traub, Holloway and Smith, ACM PLDI98, |
| 2042 | pp142-151). It is simple and fast and remarkably good at |
| 2043 | minimising the amount of spill code introduced. |
| 2044 | */ |
| 2045 | |
| 2046 | static |
| 2047 | UCodeBlock* vg_do_register_allocation ( UCodeBlock* c1 ) |
| 2048 | { |
| 2049 | TempInfo* temp_info; |
njn | ed61971 | 2003-10-01 16:45:04 +0000 | [diff] [blame] | 2050 | Int real_to_temp [VG_MAX_REALREGS]; |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 2051 | Bool is_spill_cand[VG_MAX_REALREGS]; |
| 2052 | Int ss_busy_until_before[VG_MAX_SPILLSLOTS]; |
| 2053 | Int i, j, k, m, r, tno, max_ss_no; |
| 2054 | Bool wr, defer, isRead, spill_reqd; |
njn | ed61971 | 2003-10-01 16:45:04 +0000 | [diff] [blame] | 2055 | UInt realUse [VG_MAX_REGS_USED]; |
| 2056 | Int tempUse [VG_MAX_REGS_USED]; |
njn | f4ce3d3 | 2003-02-10 10:17:26 +0000 | [diff] [blame] | 2057 | Bool isWrites[VG_MAX_REGS_USED]; |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 2058 | UCodeBlock* c2; |
| 2059 | |
| 2060 | /* Used to denote ... well, "no value" in this fn. */ |
| 2061 | # define VG_NOTHING (-2) |
| 2062 | |
| 2063 | /* Initialise the TempReg info. */ |
| 2064 | if (c1->nextTemp > 0) |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 2065 | temp_info = VG_(arena_malloc)(VG_AR_JITTER, |
| 2066 | c1->nextTemp * sizeof(TempInfo) ); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 2067 | else |
| 2068 | temp_info = NULL; |
| 2069 | |
| 2070 | for (i = 0; i < c1->nextTemp; i++) { |
| 2071 | temp_info[i].live_after = VG_NOTHING; |
| 2072 | temp_info[i].dead_before = VG_NOTHING; |
| 2073 | temp_info[i].spill_no = VG_NOTHING; |
| 2074 | /* temp_info[i].real_no is not yet relevant. */ |
| 2075 | } |
| 2076 | |
| 2077 | spill_reqd = False; |
| 2078 | |
| 2079 | /* Scan fwds to establish live ranges. */ |
| 2080 | |
| 2081 | for (i = 0; i < c1->used; i++) { |
njn | 810086f | 2002-11-14 12:42:47 +0000 | [diff] [blame] | 2082 | k = VG_(get_reg_usage)(&c1->instrs[i], TempReg, &tempUse[0], |
| 2083 | &isWrites[0]); |
njn | f4ce3d3 | 2003-02-10 10:17:26 +0000 | [diff] [blame] | 2084 | vg_assert(k >= 0 && k <= VG_MAX_REGS_USED); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 2085 | |
| 2086 | /* For each temp usage ... fwds in program order */ |
| 2087 | for (j = 0; j < k; j++) { |
njn | 810086f | 2002-11-14 12:42:47 +0000 | [diff] [blame] | 2088 | tno = tempUse[j]; |
| 2089 | wr = isWrites[j]; |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 2090 | if (wr) { |
| 2091 | /* Writes hold a reg live until after this insn. */ |
| 2092 | if (temp_info[tno].live_after == VG_NOTHING) |
| 2093 | temp_info[tno].live_after = i; |
| 2094 | if (temp_info[tno].dead_before < i + 1) |
| 2095 | temp_info[tno].dead_before = i + 1; |
| 2096 | } else { |
| 2097 | /* First use of a tmp should be a write. */ |
njn | fa0ad42 | 2003-02-03 11:07:03 +0000 | [diff] [blame] | 2098 | if (temp_info[tno].live_after == VG_NOTHING) { |
| 2099 | VG_(printf)("At instr %d...\n", i); |
| 2100 | VG_(core_panic)("First use of tmp not a write," |
nethercote | 996901a | 2004-08-03 13:29:09 +0000 | [diff] [blame] | 2101 | " probably a tool instrumentation error"); |
njn | fa0ad42 | 2003-02-03 11:07:03 +0000 | [diff] [blame] | 2102 | } |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 2103 | /* Reads only hold it live until before this insn. */ |
| 2104 | if (temp_info[tno].dead_before < i) |
| 2105 | temp_info[tno].dead_before = i; |
| 2106 | } |
| 2107 | } |
| 2108 | } |
| 2109 | |
| 2110 | # if 0 |
| 2111 | /* Sanity check on live ranges. Expensive but correct. */ |
| 2112 | for (i = 0; i < c1->nextTemp; i++) { |
| 2113 | vg_assert( (temp_info[i].live_after == VG_NOTHING |
| 2114 | && temp_info[i].dead_before == VG_NOTHING) |
| 2115 | || (temp_info[i].live_after != VG_NOTHING |
| 2116 | && temp_info[i].dead_before != VG_NOTHING) ); |
| 2117 | } |
| 2118 | # endif |
| 2119 | |
| 2120 | /* Do a rank-based allocation of TempRegs to spill slot numbers. |
| 2121 | We put as few as possible values in spill slots, but |
| 2122 | nevertheless need to have an assignment to them just in case. */ |
| 2123 | |
| 2124 | max_ss_no = -1; |
| 2125 | |
| 2126 | for (i = 0; i < VG_MAX_SPILLSLOTS; i++) |
| 2127 | ss_busy_until_before[i] = 0; |
| 2128 | |
| 2129 | for (i = 0; i < c1->nextTemp; i++) { |
| 2130 | |
| 2131 | /* True iff this temp is unused. */ |
| 2132 | if (temp_info[i].live_after == VG_NOTHING) |
| 2133 | continue; |
| 2134 | |
| 2135 | /* Find the lowest-numbered spill slot which is available at the |
| 2136 | start point of this interval, and assign the interval to |
| 2137 | it. */ |
| 2138 | for (j = 0; j < VG_MAX_SPILLSLOTS; j++) |
| 2139 | if (ss_busy_until_before[j] <= temp_info[i].live_after) |
| 2140 | break; |
| 2141 | if (j == VG_MAX_SPILLSLOTS) { |
| 2142 | VG_(printf)("VG_MAX_SPILLSLOTS is too low; increase and recompile.\n"); |
njn | e427a66 | 2002-10-02 11:08:25 +0000 | [diff] [blame] | 2143 | VG_(core_panic)("register allocation failed -- out of spill slots"); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 2144 | } |
| 2145 | ss_busy_until_before[j] = temp_info[i].dead_before; |
| 2146 | temp_info[i].spill_no = j; |
| 2147 | if (j > max_ss_no) |
| 2148 | max_ss_no = j; |
| 2149 | } |
| 2150 | |
nethercote | bee3fd9 | 2004-08-02 15:17:43 +0000 | [diff] [blame] | 2151 | n_total_reg_rank += (max_ss_no+1); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 2152 | |
| 2153 | /* Show live ranges and assigned spill slot nos. */ |
| 2154 | |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 2155 | if (dis) { |
| 2156 | VG_(printf)("Live range assignments:\n"); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 2157 | |
| 2158 | for (i = 0; i < c1->nextTemp; i++) { |
| 2159 | if (temp_info[i].live_after == VG_NOTHING) |
| 2160 | continue; |
| 2161 | VG_(printf)( |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 2162 | " LR %d is after %d to before %d\tspillno %d\n", |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 2163 | i, |
| 2164 | temp_info[i].live_after, |
| 2165 | temp_info[i].dead_before, |
| 2166 | temp_info[i].spill_no |
| 2167 | ); |
| 2168 | } |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 2169 | VG_(printf)("\n"); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 2170 | } |
| 2171 | |
| 2172 | /* Now that we've established a spill slot number for each used |
| 2173 | temporary, we can go ahead and do the core of the "Second-chance |
| 2174 | binpacking" allocation algorithm. */ |
| 2175 | |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 2176 | if (dis) VG_(printf)("Register allocated UCode:\n"); |
| 2177 | |
| 2178 | |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 2179 | /* Resulting code goes here. We generate it all in a forwards |
| 2180 | pass. */ |
nethercote | caee10d | 2004-08-03 17:39:06 +0000 | [diff] [blame] | 2181 | c2 = alloc_UCodeBlock( c1->orig_eip ); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 2182 | |
| 2183 | /* At the start, no TempRegs are assigned to any real register. |
| 2184 | Correspondingly, all temps claim to be currently resident in |
| 2185 | their spill slots, as computed by the previous two passes. */ |
| 2186 | for (i = 0; i < VG_MAX_REALREGS; i++) |
| 2187 | real_to_temp[i] = VG_NOTHING; |
| 2188 | for (i = 0; i < c1->nextTemp; i++) |
| 2189 | temp_info[i].real_no = VG_NOTHING; |
| 2190 | |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 2191 | /* Process each insn in turn. */ |
| 2192 | for (i = 0; i < c1->used; i++) { |
| 2193 | |
| 2194 | if (c1->instrs[i].opcode == NOP) continue; |
nethercote | bee3fd9 | 2004-08-02 15:17:43 +0000 | [diff] [blame] | 2195 | n_uinstrs_prealloc++; |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 2196 | |
| 2197 | # if 0 |
| 2198 | /* Check map consistency. Expensive but correct. */ |
| 2199 | for (r = 0; r < VG_MAX_REALREGS; r++) { |
| 2200 | if (real_to_temp[r] != VG_NOTHING) { |
| 2201 | tno = real_to_temp[r]; |
| 2202 | vg_assert(tno >= 0 && tno < c1->nextTemp); |
| 2203 | vg_assert(temp_info[tno].real_no == r); |
| 2204 | } |
| 2205 | } |
| 2206 | for (tno = 0; tno < c1->nextTemp; tno++) { |
| 2207 | if (temp_info[tno].real_no != VG_NOTHING) { |
| 2208 | r = temp_info[tno].real_no; |
| 2209 | vg_assert(r >= 0 && r < VG_MAX_REALREGS); |
| 2210 | vg_assert(real_to_temp[r] == tno); |
| 2211 | } |
| 2212 | } |
| 2213 | # endif |
| 2214 | |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 2215 | if (dis) |
njn | 4ba5a79 | 2002-09-30 10:23:54 +0000 | [diff] [blame] | 2216 | VG_(pp_UInstr)(i, &c1->instrs[i]); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 2217 | |
| 2218 | /* First, free up enough real regs for this insn. This may |
| 2219 | generate spill stores since we may have to evict some TempRegs |
| 2220 | currently in real regs. Also generates spill loads. */ |
| 2221 | |
njn | 810086f | 2002-11-14 12:42:47 +0000 | [diff] [blame] | 2222 | k = VG_(get_reg_usage)(&c1->instrs[i], TempReg, &tempUse[0], |
| 2223 | &isWrites[0]); |
njn | f4ce3d3 | 2003-02-10 10:17:26 +0000 | [diff] [blame] | 2224 | vg_assert(k >= 0 && k <= VG_MAX_REGS_USED); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 2225 | |
| 2226 | /* For each ***different*** temp mentioned in the insn .... */ |
| 2227 | for (j = 0; j < k; j++) { |
| 2228 | |
| 2229 | /* First check if the temp is mentioned again later; if so, |
| 2230 | ignore this mention. We only want to process each temp |
| 2231 | used by the insn once, even if it is mentioned more than |
| 2232 | once. */ |
| 2233 | defer = False; |
njn | 810086f | 2002-11-14 12:42:47 +0000 | [diff] [blame] | 2234 | tno = tempUse[j]; |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 2235 | for (m = j+1; m < k; m++) |
njn | 810086f | 2002-11-14 12:42:47 +0000 | [diff] [blame] | 2236 | if (tempUse[m] == tno) |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 2237 | defer = True; |
| 2238 | if (defer) |
| 2239 | continue; |
| 2240 | |
njn | 810086f | 2002-11-14 12:42:47 +0000 | [diff] [blame] | 2241 | /* Now we're trying to find a register for tempUse[j]. |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 2242 | First of all, if it already has a register assigned, we |
| 2243 | don't need to do anything more. */ |
| 2244 | if (temp_info[tno].real_no != VG_NOTHING) |
| 2245 | continue; |
| 2246 | |
| 2247 | /* No luck. The next thing to do is see if there is a |
| 2248 | currently unassigned register available. If so, bag it. */ |
| 2249 | for (r = 0; r < VG_MAX_REALREGS; r++) { |
| 2250 | if (real_to_temp[r] == VG_NOTHING) |
| 2251 | break; |
| 2252 | } |
| 2253 | if (r < VG_MAX_REALREGS) { |
| 2254 | real_to_temp[r] = tno; |
| 2255 | temp_info[tno].real_no = r; |
| 2256 | continue; |
| 2257 | } |
| 2258 | |
| 2259 | /* Unfortunately, that didn't pan out either. So we'll have |
| 2260 | to eject some other unfortunate TempReg into a spill slot |
| 2261 | in order to free up a register. Of course, we need to be |
| 2262 | careful not to eject some other TempReg needed by this |
| 2263 | insn. |
| 2264 | |
| 2265 | Select r in 0 .. VG_MAX_REALREGS-1 such that |
| 2266 | real_to_temp[r] is not mentioned in |
njn | 810086f | 2002-11-14 12:42:47 +0000 | [diff] [blame] | 2267 | tempUse[0 .. k-1], since it would be just plain |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 2268 | wrong to eject some other TempReg which we need to use in |
| 2269 | this insn. |
| 2270 | |
| 2271 | It is here that it is important to make a good choice of |
| 2272 | register to spill. */ |
| 2273 | |
| 2274 | /* First, mark those regs which are not spill candidates. */ |
| 2275 | for (r = 0; r < VG_MAX_REALREGS; r++) { |
| 2276 | is_spill_cand[r] = True; |
| 2277 | for (m = 0; m < k; m++) { |
njn | 810086f | 2002-11-14 12:42:47 +0000 | [diff] [blame] | 2278 | if (real_to_temp[r] == tempUse[m]) { |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 2279 | is_spill_cand[r] = False; |
| 2280 | break; |
| 2281 | } |
| 2282 | } |
| 2283 | } |
| 2284 | |
| 2285 | /* We can choose any r satisfying is_spill_cand[r]. However, |
| 2286 | try to make a good choice. First, try and find r such |
| 2287 | that the associated TempReg is already dead. */ |
| 2288 | for (r = 0; r < VG_MAX_REALREGS; r++) { |
| 2289 | if (is_spill_cand[r] && |
| 2290 | temp_info[real_to_temp[r]].dead_before <= i) |
| 2291 | goto have_spill_cand; |
| 2292 | } |
| 2293 | |
| 2294 | /* No spill cand is mapped to a dead TempReg. Now we really |
| 2295 | _do_ have to generate spill code. Choose r so that the |
| 2296 | next use of its associated TempReg is as far ahead as |
| 2297 | possible, in the hope that this will minimise the number of |
| 2298 | consequent reloads required. This is a bit expensive, but |
| 2299 | we don't have to do it very often. */ |
| 2300 | { |
| 2301 | Int furthest_r = VG_MAX_REALREGS; |
| 2302 | Int furthest = 0; |
| 2303 | for (r = 0; r < VG_MAX_REALREGS; r++) { |
| 2304 | if (!is_spill_cand[r]) continue; |
| 2305 | for (m = i+1; m < c1->used; m++) |
| 2306 | if (uInstrMentionsTempReg(&c1->instrs[m], |
| 2307 | real_to_temp[r])) |
| 2308 | break; |
| 2309 | if (m > furthest) { |
| 2310 | furthest = m; |
| 2311 | furthest_r = r; |
| 2312 | } |
| 2313 | } |
| 2314 | r = furthest_r; |
| 2315 | goto have_spill_cand; |
| 2316 | } |
| 2317 | |
| 2318 | have_spill_cand: |
| 2319 | if (r == VG_MAX_REALREGS) |
njn | e427a66 | 2002-10-02 11:08:25 +0000 | [diff] [blame] | 2320 | VG_(core_panic)("new reg alloc: out of registers ?!"); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 2321 | |
| 2322 | /* Eject r. Important refinement: don't bother if the |
| 2323 | associated TempReg is now dead. */ |
| 2324 | vg_assert(real_to_temp[r] != VG_NOTHING); |
| 2325 | vg_assert(real_to_temp[r] != tno); |
| 2326 | temp_info[real_to_temp[r]].real_no = VG_NOTHING; |
| 2327 | if (temp_info[real_to_temp[r]].dead_before > i) { |
| 2328 | uInstr2(c2, PUT, 4, |
njn | 4ba5a79 | 2002-09-30 10:23:54 +0000 | [diff] [blame] | 2329 | RealReg, VG_(rank_to_realreg)(r), |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 2330 | SpillNo, temp_info[real_to_temp[r]].spill_no); |
nethercote | bee3fd9 | 2004-08-02 15:17:43 +0000 | [diff] [blame] | 2331 | n_uinstrs_spill++; |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 2332 | spill_reqd = True; |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 2333 | if (dis) |
njn | 4ba5a79 | 2002-09-30 10:23:54 +0000 | [diff] [blame] | 2334 | VG_(pp_UInstr)(c2->used-1, &LAST_UINSTR(c2)); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 2335 | } |
| 2336 | |
| 2337 | /* Decide if tno is read. */ |
| 2338 | isRead = False; |
| 2339 | for (m = 0; m < k; m++) |
njn | 810086f | 2002-11-14 12:42:47 +0000 | [diff] [blame] | 2340 | if (tempUse[m] == tno && !isWrites[m]) |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 2341 | isRead = True; |
| 2342 | |
| 2343 | /* If so, generate a spill load. */ |
| 2344 | if (isRead) { |
| 2345 | uInstr2(c2, GET, 4, |
| 2346 | SpillNo, temp_info[tno].spill_no, |
njn | 4ba5a79 | 2002-09-30 10:23:54 +0000 | [diff] [blame] | 2347 | RealReg, VG_(rank_to_realreg)(r) ); |
nethercote | bee3fd9 | 2004-08-02 15:17:43 +0000 | [diff] [blame] | 2348 | n_uinstrs_spill++; |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 2349 | spill_reqd = True; |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 2350 | if (dis) |
njn | 4ba5a79 | 2002-09-30 10:23:54 +0000 | [diff] [blame] | 2351 | VG_(pp_UInstr)(c2->used-1, &LAST_UINSTR(c2)); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 2352 | } |
| 2353 | |
| 2354 | /* Update the forwards and backwards maps. */ |
| 2355 | real_to_temp[r] = tno; |
| 2356 | temp_info[tno].real_no = r; |
| 2357 | } |
| 2358 | |
| 2359 | /* By this point, all TempRegs mentioned by the insn have been |
| 2360 | bought into real regs. We now copy the insn to the output |
| 2361 | and use patchUInstr to convert its rTempRegs into |
| 2362 | realregs. */ |
| 2363 | for (j = 0; j < k; j++) |
njn | 810086f | 2002-11-14 12:42:47 +0000 | [diff] [blame] | 2364 | realUse[j] = VG_(rank_to_realreg)(temp_info[tempUse[j]].real_no); |
njn | 4ba5a79 | 2002-09-30 10:23:54 +0000 | [diff] [blame] | 2365 | VG_(copy_UInstr)(c2, &c1->instrs[i]); |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 2366 | patchUInstr(&LAST_UINSTR(c2), &tempUse[0], &realUse[0], k); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 2367 | |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 2368 | if (dis) { |
njn | 4ba5a79 | 2002-09-30 10:23:54 +0000 | [diff] [blame] | 2369 | VG_(pp_UInstr)(c2->used-1, &LAST_UINSTR(c2)); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 2370 | VG_(printf)("\n"); |
| 2371 | } |
| 2372 | } |
| 2373 | |
| 2374 | if (temp_info != NULL) |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 2375 | VG_(arena_free)(VG_AR_JITTER, temp_info); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 2376 | |
njn | 4ba5a79 | 2002-09-30 10:23:54 +0000 | [diff] [blame] | 2377 | VG_(free_UCodeBlock)(c1); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 2378 | |
| 2379 | if (spill_reqd) |
nethercote | bee3fd9 | 2004-08-02 15:17:43 +0000 | [diff] [blame] | 2380 | n_translations_needing_spill++; |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 2381 | |
| 2382 | return c2; |
| 2383 | |
| 2384 | # undef VG_NOTHING |
| 2385 | |
| 2386 | } |
sewardj | 7c4b604 | 2003-06-14 15:47:15 +0000 | [diff] [blame] | 2387 | |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 2388 | /* Analysis records liveness of all general-use RealRegs in the UCode. */ |
| 2389 | static void vg_realreg_liveness_analysis ( UCodeBlock* cb ) |
| 2390 | { |
| 2391 | Int i, j, k; |
| 2392 | RRegSet rregs_live; |
njn | f4ce3d3 | 2003-02-10 10:17:26 +0000 | [diff] [blame] | 2393 | Int regUse[VG_MAX_REGS_USED]; |
| 2394 | Bool isWrites[VG_MAX_REGS_USED]; |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 2395 | UInstr* u; |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 2396 | |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 2397 | /* All regs are dead at the end of the block */ |
| 2398 | rregs_live = ALL_RREGS_DEAD; |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 2399 | |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 2400 | for (i = cb->used-1; i >= 0; i--) { |
| 2401 | u = &cb->instrs[i]; |
| 2402 | |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 2403 | u->regs_live_after = rregs_live; |
sewardj | 97ced73 | 2002-03-25 00:07:36 +0000 | [diff] [blame] | 2404 | |
njn | 810086f | 2002-11-14 12:42:47 +0000 | [diff] [blame] | 2405 | k = VG_(get_reg_usage)(u, RealReg, ®Use[0], &isWrites[0]); |
sewardj | 97ced73 | 2002-03-25 00:07:36 +0000 | [diff] [blame] | 2406 | |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 2407 | /* For each reg usage ... bwds in program order. Variable is live |
| 2408 | before this UInstr if it is read by this UInstr. |
njn | 810086f | 2002-11-14 12:42:47 +0000 | [diff] [blame] | 2409 | Note that regUse[j] holds the Intel reg number, so we must |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 2410 | convert it to our rank number. */ |
| 2411 | for (j = k-1; j >= 0; j--) { |
njn | 810086f | 2002-11-14 12:42:47 +0000 | [diff] [blame] | 2412 | SET_RREG_LIVENESS ( VG_(realreg_to_rank)(regUse[j]), |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 2413 | rregs_live, |
njn | 810086f | 2002-11-14 12:42:47 +0000 | [diff] [blame] | 2414 | !isWrites[j] ); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 2415 | } |
| 2416 | } |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 2417 | } |
| 2418 | |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 2419 | /*------------------------------------------------------------*/ |
| 2420 | /*--- Main entry point for the JITter. ---*/ |
| 2421 | /*------------------------------------------------------------*/ |
| 2422 | |
nethercote | 59a122d | 2004-08-03 17:16:51 +0000 | [diff] [blame] | 2423 | /* Translate the basic block beginning at orig_addr, and add it to |
| 2424 | the translation cache & translation table. Unless 'debugging' is true, |
| 2425 | in which case the call is being done for debugging purposes, so |
| 2426 | (a) throw away the translation once it is made, and (b) produce a |
| 2427 | load of debugging output. |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 2428 | |
nethercote | 59a122d | 2004-08-03 17:16:51 +0000 | [diff] [blame] | 2429 | 'tid' is the identity of the thread needing this block. |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 2430 | */ |
nethercote | 4d71438 | 2004-10-13 09:47:24 +0000 | [diff] [blame^] | 2431 | Bool VG_(translate) ( ThreadId tid, Addr orig_addr, |
nethercote | 59a122d | 2004-08-03 17:16:51 +0000 | [diff] [blame] | 2432 | Bool debugging_translation ) |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 2433 | { |
nethercote | 59a122d | 2004-08-03 17:16:51 +0000 | [diff] [blame] | 2434 | Addr trans_addr, redir, orig_addr0 = orig_addr; |
| 2435 | UShort jumps[VG_MAX_JUMPS]; |
| 2436 | Int i, orig_size, trans_size; |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 2437 | UCodeBlock* cb; |
sewardj | a60be0e | 2003-05-26 08:47:27 +0000 | [diff] [blame] | 2438 | Bool notrace_until_done; |
sewardj | 1e86b8b | 2003-06-16 23:34:12 +0000 | [diff] [blame] | 2439 | UInt notrace_until_limit = 0; |
fitzhardinge | 98abfc7 | 2003-12-16 02:05:15 +0000 | [diff] [blame] | 2440 | Segment *seg; |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 2441 | |
| 2442 | VGP_PUSHCC(VgpTranslate); |
nethercote | 59a122d | 2004-08-03 17:16:51 +0000 | [diff] [blame] | 2443 | |
nethercote | 885dd91 | 2004-08-03 23:14:00 +0000 | [diff] [blame] | 2444 | beforeRA = True; |
| 2445 | beforeLiveness = True; |
| 2446 | |
nethercote | 59a122d | 2004-08-03 17:16:51 +0000 | [diff] [blame] | 2447 | for (i = 0; i < VG_MAX_JUMPS; i++) |
| 2448 | jumps[i] = (UShort)-1; |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 2449 | |
sewardj | 25c7c3a | 2003-07-10 00:17:58 +0000 | [diff] [blame] | 2450 | /* Look in the code redirect table to see if we should |
| 2451 | translate an alternative address for orig_addr. */ |
fitzhardinge | 98abfc7 | 2003-12-16 02:05:15 +0000 | [diff] [blame] | 2452 | redir = VG_(code_redirect)(orig_addr); |
| 2453 | |
nethercote | 59a122d | 2004-08-03 17:16:51 +0000 | [diff] [blame] | 2454 | if (redir != orig_addr && VG_(clo_verbosity) >= 2) { |
fitzhardinge | 98abfc7 | 2003-12-16 02:05:15 +0000 | [diff] [blame] | 2455 | VG_(message)(Vg_UserMsg, |
| 2456 | "TRANSLATE: %p redirected to %p", |
| 2457 | orig_addr, |
| 2458 | redir ); |
nethercote | 59a122d | 2004-08-03 17:16:51 +0000 | [diff] [blame] | 2459 | } |
fitzhardinge | 98abfc7 | 2003-12-16 02:05:15 +0000 | [diff] [blame] | 2460 | orig_addr = redir; |
sewardj | 25c7c3a | 2003-07-10 00:17:58 +0000 | [diff] [blame] | 2461 | |
sewardj | a60be0e | 2003-05-26 08:47:27 +0000 | [diff] [blame] | 2462 | /* If codegen tracing, don't start tracing until |
| 2463 | notrace_until_limit blocks have gone by. This avoids printing |
| 2464 | huge amounts of useless junk when all we want to see is the last |
| 2465 | few blocks translated prior to a failure. Set |
| 2466 | notrace_until_limit to be the number of translations to be made |
| 2467 | before --trace-codegen= style printing takes effect. */ |
nethercote | 92e7b7f | 2004-08-07 17:52:25 +0000 | [diff] [blame] | 2468 | notrace_until_done = VG_(get_bbs_translated)() >= notrace_until_limit; |
sewardj | a60be0e | 2003-05-26 08:47:27 +0000 | [diff] [blame] | 2469 | |
fitzhardinge | 98abfc7 | 2003-12-16 02:05:15 +0000 | [diff] [blame] | 2470 | seg = VG_(find_segment)(orig_addr); |
| 2471 | |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 2472 | if (!debugging_translation) |
njn | 7271864 | 2003-07-24 08:45:32 +0000 | [diff] [blame] | 2473 | VG_TRACK( pre_mem_read, Vg_CoreTranslate, tid, "", orig_addr, 1 ); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 2474 | |
fitzhardinge | 98abfc7 | 2003-12-16 02:05:15 +0000 | [diff] [blame] | 2475 | if (seg == NULL || |
| 2476 | !VG_(seg_contains)(seg, orig_addr, 1) || |
| 2477 | (seg->prot & (VKI_PROT_READ|VKI_PROT_EXEC)) == 0) { |
fitzhardinge | 98abfc7 | 2003-12-16 02:05:15 +0000 | [diff] [blame] | 2478 | /* Code address is bad - deliver a signal instead */ |
| 2479 | vg_assert(!VG_(is_addressable)(orig_addr, 1)); |
| 2480 | |
fitzhardinge | 98abfc7 | 2003-12-16 02:05:15 +0000 | [diff] [blame] | 2481 | if (seg != NULL && VG_(seg_contains)(seg, orig_addr, 1)) { |
| 2482 | vg_assert((seg->prot & VKI_PROT_EXEC) == 0); |
fitzhardinge | f1beb25 | 2004-03-16 09:49:08 +0000 | [diff] [blame] | 2483 | VG_(synth_fault_perms)(tid, orig_addr); |
fitzhardinge | 98abfc7 | 2003-12-16 02:05:15 +0000 | [diff] [blame] | 2484 | } else |
fitzhardinge | f1beb25 | 2004-03-16 09:49:08 +0000 | [diff] [blame] | 2485 | VG_(synth_fault_mapping)(tid, orig_addr); |
jsgf | 855d93d | 2003-10-13 22:26:55 +0000 | [diff] [blame] | 2486 | |
nethercote | 4d71438 | 2004-10-13 09:47:24 +0000 | [diff] [blame^] | 2487 | return False; |
fitzhardinge | 98abfc7 | 2003-12-16 02:05:15 +0000 | [diff] [blame] | 2488 | } else |
| 2489 | seg->flags |= SF_CODE; /* contains cached code */ |
jsgf | 855d93d | 2003-10-13 22:26:55 +0000 | [diff] [blame] | 2490 | |
nethercote | caee10d | 2004-08-03 17:39:06 +0000 | [diff] [blame] | 2491 | cb = alloc_UCodeBlock( orig_addr ); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 2492 | |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 2493 | /* If doing any code printing, print a basic block start marker */ |
sewardj | a60be0e | 2003-05-26 08:47:27 +0000 | [diff] [blame] | 2494 | if (VG_(clo_trace_codegen) && notrace_until_done) { |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 2495 | Char fnname[64] = ""; |
| 2496 | VG_(get_fnname_if_entry)(orig_addr, fnname, 64); |
| 2497 | VG_(printf)( |
nethercote | 92e7b7f | 2004-08-07 17:52:25 +0000 | [diff] [blame] | 2498 | "==== BB %d %s(%p) approx BBs exec'd %llu ====\n\n", |
| 2499 | VG_(get_bbs_translated)(), fnname, orig_addr, |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 2500 | VG_(bbs_done)); |
| 2501 | } |
| 2502 | |
| 2503 | /* True if a debug trans., or if bit N set in VG_(clo_trace_codegen). */ |
sewardj | a60be0e | 2003-05-26 08:47:27 +0000 | [diff] [blame] | 2504 | # define DECIDE_IF_PRINTING_CODEGEN_FOR_PHASE(n) \ |
| 2505 | ( debugging_translation \ |
| 2506 | || (notrace_until_done \ |
| 2507 | && (VG_(clo_trace_codegen) & (1 << (n-1))) )) |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 2508 | |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 2509 | /* Disassemble this basic block into cb. */ |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 2510 | VG_(print_codegen) = DECIDE_IF_PRINTING_CODEGEN_FOR_PHASE(1); |
| 2511 | VGP_PUSHCC(VgpToUCode); |
nethercote | 59a122d | 2004-08-03 17:16:51 +0000 | [diff] [blame] | 2512 | orig_size = VG_(disBB) ( cb, orig_addr ); |
nethercote | 885dd91 | 2004-08-03 23:14:00 +0000 | [diff] [blame] | 2513 | sanity_check_UCodeBlock ( cb ); |
| 2514 | // Only sanity-check calls now because tools might remove the |
| 2515 | // CALLM_[ES] pairs. |
| 2516 | sanity_check_UCodeBlockCalls ( cb ); |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 2517 | VGP_POPCC(VgpToUCode); |
| 2518 | |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 2519 | /* Try and improve the code a bit. */ |
| 2520 | if (VG_(clo_optimise)) { |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 2521 | VG_(print_codegen) = DECIDE_IF_PRINTING_CODEGEN_FOR_PHASE(2); |
| 2522 | VGP_PUSHCC(VgpImprove); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 2523 | vg_improve ( cb ); |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 2524 | VGP_POPCC(VgpImprove); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 2525 | } |
| 2526 | |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 2527 | /* Skin's instrumentation (Nb: must set VG_(print_codegen) in case |
| 2528 | SK_(instrument) looks at it. */ |
| 2529 | VG_(print_codegen) = DECIDE_IF_PRINTING_CODEGEN_FOR_PHASE(3); |
| 2530 | VGP_PUSHCC(VgpInstrument); |
| 2531 | cb = SK_(instrument) ( cb, orig_addr ); |
| 2532 | if (VG_(print_codegen)) |
njn | 4ba5a79 | 2002-09-30 10:23:54 +0000 | [diff] [blame] | 2533 | VG_(pp_UCodeBlock) ( cb, "Instrumented UCode:" ); |
nethercote | 885dd91 | 2004-08-03 23:14:00 +0000 | [diff] [blame] | 2534 | sanity_check_UCodeBlock( cb ); |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 2535 | VGP_POPCC(VgpInstrument); |
njn | 4f9c934 | 2002-04-29 16:03:24 +0000 | [diff] [blame] | 2536 | |
nethercote | 996901a | 2004-08-03 13:29:09 +0000 | [diff] [blame] | 2537 | /* Add %ESP-update hooks if the tool requires them */ |
njn | 9b007f6 | 2003-04-07 14:40:25 +0000 | [diff] [blame] | 2538 | /* Nb: We don't print out this phase, because it doesn't do much */ |
| 2539 | if (VG_(need_to_handle_esp_assignment)()) { |
| 2540 | VGP_PUSHCC(VgpESPUpdate); |
| 2541 | cb = vg_ESP_update_pass ( cb ); |
| 2542 | VGP_POPCC(VgpESPUpdate); |
| 2543 | } |
| 2544 | |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 2545 | /* Allocate registers. */ |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 2546 | VG_(print_codegen) = DECIDE_IF_PRINTING_CODEGEN_FOR_PHASE(4); |
| 2547 | VGP_PUSHCC(VgpRegAlloc); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 2548 | cb = vg_do_register_allocation ( cb ); |
nethercote | 885dd91 | 2004-08-03 23:14:00 +0000 | [diff] [blame] | 2549 | beforeRA = False; |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 2550 | VGP_POPCC(VgpRegAlloc); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 2551 | |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 2552 | /* Do post reg-alloc %e[acd]x liveness analysis (too boring to print |
| 2553 | * anything; results can be seen when emitting final code). */ |
| 2554 | VGP_PUSHCC(VgpLiveness); |
| 2555 | vg_realreg_liveness_analysis ( cb ); |
nethercote | 885dd91 | 2004-08-03 23:14:00 +0000 | [diff] [blame] | 2556 | beforeLiveness = False; |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 2557 | VGP_POPCC(VgpLiveness); |
| 2558 | |
| 2559 | /* Emit final code */ |
| 2560 | VG_(print_codegen) = DECIDE_IF_PRINTING_CODEGEN_FOR_PHASE(5); |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 2561 | VGP_PUSHCC(VgpFromUcode); |
nethercote | 59a122d | 2004-08-03 17:16:51 +0000 | [diff] [blame] | 2562 | trans_addr = (Addr)VG_(emit_code)(cb, &trans_size, jumps ); |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 2563 | VGP_POPCC(VgpFromUcode); |
njn | 4ba5a79 | 2002-09-30 10:23:54 +0000 | [diff] [blame] | 2564 | VG_(free_UCodeBlock)(cb); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 2565 | |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 2566 | #undef DECIDE_IF_PRINTING_CODEGEN_FOR_PHASE |
| 2567 | |
nethercote | 59a122d | 2004-08-03 17:16:51 +0000 | [diff] [blame] | 2568 | /* Copy data at trans_addr into the translation cache. */ |
| 2569 | /* Since the .orig_size and .trans_size fields are UShort, be paranoid. */ |
| 2570 | vg_assert(orig_size > 0 && orig_size < 65536); |
| 2571 | vg_assert(trans_size > 0 && trans_size < 65536); |
| 2572 | |
| 2573 | // If debugging, don't do anything with the translated block; we |
| 2574 | // only did this for the debugging output produced along the way. |
| 2575 | if (!debugging_translation) { |
| 2576 | // Note that we use orig_addr0, not orig_addr, which might have been |
| 2577 | // changed by the redirection |
| 2578 | VG_(add_to_trans_tab)( orig_addr0, orig_size, trans_addr, trans_size, |
| 2579 | jumps ); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 2580 | } |
nethercote | 59a122d | 2004-08-03 17:16:51 +0000 | [diff] [blame] | 2581 | |
| 2582 | /* Free the intermediary -- was allocated by VG_(emit_code). */ |
| 2583 | VG_(arena_free)( VG_AR_JITTER, (void*)trans_addr ); |
| 2584 | |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 2585 | VGP_POPCC(VgpTranslate); |
nethercote | 4d71438 | 2004-10-13 09:47:24 +0000 | [diff] [blame^] | 2586 | |
| 2587 | return True; |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 2588 | } |
| 2589 | |
nethercote | 59a122d | 2004-08-03 17:16:51 +0000 | [diff] [blame] | 2590 | |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 2591 | /*--------------------------------------------------------------------*/ |
| 2592 | /*--- end vg_translate.c ---*/ |
| 2593 | /*--------------------------------------------------------------------*/ |
njn | ed61971 | 2003-10-01 16:45:04 +0000 | [diff] [blame] | 2594 | |