cerion | bcf8c3e | 2005-02-04 16:17:07 +0000 | [diff] [blame] | 1 | |
| 2 | /*---------------------------------------------------------------*/ |
sewardj | 752f906 | 2010-05-03 21:38:49 +0000 | [diff] [blame] | 3 | /*--- begin host_ppc_defs.h ---*/ |
cerion | bcf8c3e | 2005-02-04 16:17:07 +0000 | [diff] [blame] | 4 | /*---------------------------------------------------------------*/ |
| 5 | |
| 6 | /* |
sewardj | 752f906 | 2010-05-03 21:38:49 +0000 | [diff] [blame] | 7 | This file is part of Valgrind, a dynamic binary instrumentation |
| 8 | framework. |
cerion | bcf8c3e | 2005-02-04 16:17:07 +0000 | [diff] [blame] | 9 | |
sewardj | 752f906 | 2010-05-03 21:38:49 +0000 | [diff] [blame] | 10 | Copyright (C) 2004-2010 OpenWorks LLP |
| 11 | info@open-works.net |
cerion | bcf8c3e | 2005-02-04 16:17:07 +0000 | [diff] [blame] | 12 | |
sewardj | 752f906 | 2010-05-03 21:38:49 +0000 | [diff] [blame] | 13 | This program is free software; you can redistribute it and/or |
| 14 | modify it under the terms of the GNU General Public License as |
| 15 | published by the Free Software Foundation; either version 2 of the |
| 16 | License, or (at your option) any later version. |
cerion | bcf8c3e | 2005-02-04 16:17:07 +0000 | [diff] [blame] | 17 | |
sewardj | 752f906 | 2010-05-03 21:38:49 +0000 | [diff] [blame] | 18 | This program is distributed in the hope that it will be useful, but |
| 19 | WITHOUT ANY WARRANTY; without even the implied warranty of |
| 20 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
| 21 | General Public License for more details. |
| 22 | |
| 23 | You should have received a copy of the GNU General Public License |
| 24 | along with this program; if not, write to the Free Software |
| 25 | Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA |
sewardj | 7bd6ffe | 2005-08-03 16:07:36 +0000 | [diff] [blame] | 26 | 02110-1301, USA. |
| 27 | |
sewardj | 752f906 | 2010-05-03 21:38:49 +0000 | [diff] [blame] | 28 | The GNU General Public License is contained in the file COPYING. |
cerion | bcf8c3e | 2005-02-04 16:17:07 +0000 | [diff] [blame] | 29 | |
| 30 | Neither the names of the U.S. Department of Energy nor the |
| 31 | University of California nor the names of its contributors may be |
| 32 | used to endorse or promote products derived from this software |
| 33 | without prior written permission. |
cerion | bcf8c3e | 2005-02-04 16:17:07 +0000 | [diff] [blame] | 34 | */ |
| 35 | |
sewardj | cef7d3e | 2009-07-02 12:21:59 +0000 | [diff] [blame] | 36 | #ifndef __VEX_HOST_PPC_DEFS_H |
| 37 | #define __VEX_HOST_PPC_DEFS_H |
cerion | bcf8c3e | 2005-02-04 16:17:07 +0000 | [diff] [blame] | 38 | |
cerion | 2c49e03 | 2005-02-09 17:29:49 +0000 | [diff] [blame] | 39 | /* Num registers used for function calls */ |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 40 | #define PPC_N_REGPARMS 8 |
cerion | 2c49e03 | 2005-02-09 17:29:49 +0000 | [diff] [blame] | 41 | |
cerion | bcf8c3e | 2005-02-04 16:17:07 +0000 | [diff] [blame] | 42 | |
| 43 | /* --------- Registers. --------- */ |
| 44 | |
| 45 | /* The usual HReg abstraction. There are 32 real int regs, |
cerion | 225a034 | 2005-09-12 20:49:09 +0000 | [diff] [blame] | 46 | 32 real float regs, and 32 real vector regs. |
cerion | bcf8c3e | 2005-02-04 16:17:07 +0000 | [diff] [blame] | 47 | */ |
| 48 | |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 49 | extern void ppHRegPPC ( HReg ); |
cerion | bcf8c3e | 2005-02-04 16:17:07 +0000 | [diff] [blame] | 50 | |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 51 | extern HReg hregPPC_GPR0 ( Bool mode64 ); // scratch reg / zero reg |
| 52 | extern HReg hregPPC_GPR1 ( Bool mode64 ); // Stack Frame Pointer |
| 53 | extern HReg hregPPC_GPR2 ( Bool mode64 ); // not used: TOC pointer |
| 54 | extern HReg hregPPC_GPR3 ( Bool mode64 ); |
| 55 | extern HReg hregPPC_GPR4 ( Bool mode64 ); |
| 56 | extern HReg hregPPC_GPR5 ( Bool mode64 ); |
| 57 | extern HReg hregPPC_GPR6 ( Bool mode64 ); |
| 58 | extern HReg hregPPC_GPR7 ( Bool mode64 ); |
| 59 | extern HReg hregPPC_GPR8 ( Bool mode64 ); |
| 60 | extern HReg hregPPC_GPR9 ( Bool mode64 ); |
| 61 | extern HReg hregPPC_GPR10 ( Bool mode64 ); |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 62 | extern HReg hregPPC_GPR11 ( Bool mode64 ); |
| 63 | extern HReg hregPPC_GPR12 ( Bool mode64 ); |
| 64 | extern HReg hregPPC_GPR13 ( Bool mode64 ); |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 65 | extern HReg hregPPC_GPR14 ( Bool mode64 ); |
| 66 | extern HReg hregPPC_GPR15 ( Bool mode64 ); |
| 67 | extern HReg hregPPC_GPR16 ( Bool mode64 ); |
| 68 | extern HReg hregPPC_GPR17 ( Bool mode64 ); |
| 69 | extern HReg hregPPC_GPR18 ( Bool mode64 ); |
| 70 | extern HReg hregPPC_GPR19 ( Bool mode64 ); |
| 71 | extern HReg hregPPC_GPR20 ( Bool mode64 ); |
| 72 | extern HReg hregPPC_GPR21 ( Bool mode64 ); |
| 73 | extern HReg hregPPC_GPR22 ( Bool mode64 ); |
| 74 | extern HReg hregPPC_GPR23 ( Bool mode64 ); |
| 75 | extern HReg hregPPC_GPR24 ( Bool mode64 ); |
| 76 | extern HReg hregPPC_GPR25 ( Bool mode64 ); |
| 77 | extern HReg hregPPC_GPR26 ( Bool mode64 ); |
| 78 | extern HReg hregPPC_GPR27 ( Bool mode64 ); |
| 79 | extern HReg hregPPC_GPR28 ( Bool mode64 ); |
sewardj | b8a8dba | 2005-12-15 21:33:50 +0000 | [diff] [blame] | 80 | extern HReg hregPPC_GPR29 ( Bool mode64 ); // reserved for dispatcher |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 81 | extern HReg hregPPC_GPR30 ( Bool mode64 ); // used as VMX spill temp |
sewardj | b8a8dba | 2005-12-15 21:33:50 +0000 | [diff] [blame] | 82 | extern HReg hregPPC_GPR31 ( Bool mode64 ); // GuestStatePtr (callee-saved) |
cerion | bcf8c3e | 2005-02-04 16:17:07 +0000 | [diff] [blame] | 83 | |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 84 | extern HReg hregPPC_FPR0 ( void ); |
| 85 | extern HReg hregPPC_FPR1 ( void ); |
| 86 | extern HReg hregPPC_FPR2 ( void ); |
| 87 | extern HReg hregPPC_FPR3 ( void ); |
| 88 | extern HReg hregPPC_FPR4 ( void ); |
| 89 | extern HReg hregPPC_FPR5 ( void ); |
| 90 | extern HReg hregPPC_FPR6 ( void ); |
| 91 | extern HReg hregPPC_FPR7 ( void ); |
| 92 | extern HReg hregPPC_FPR8 ( void ); |
| 93 | extern HReg hregPPC_FPR9 ( void ); |
| 94 | extern HReg hregPPC_FPR10 ( void ); |
| 95 | extern HReg hregPPC_FPR11 ( void ); |
| 96 | extern HReg hregPPC_FPR12 ( void ); |
| 97 | extern HReg hregPPC_FPR13 ( void ); |
| 98 | extern HReg hregPPC_FPR14 ( void ); |
| 99 | extern HReg hregPPC_FPR15 ( void ); |
| 100 | extern HReg hregPPC_FPR16 ( void ); |
| 101 | extern HReg hregPPC_FPR17 ( void ); |
| 102 | extern HReg hregPPC_FPR18 ( void ); |
| 103 | extern HReg hregPPC_FPR19 ( void ); |
| 104 | extern HReg hregPPC_FPR20 ( void ); |
| 105 | extern HReg hregPPC_FPR21 ( void ); |
| 106 | extern HReg hregPPC_FPR22 ( void ); |
| 107 | extern HReg hregPPC_FPR23 ( void ); |
| 108 | extern HReg hregPPC_FPR24 ( void ); |
| 109 | extern HReg hregPPC_FPR25 ( void ); |
| 110 | extern HReg hregPPC_FPR26 ( void ); |
| 111 | extern HReg hregPPC_FPR27 ( void ); |
| 112 | extern HReg hregPPC_FPR28 ( void ); |
| 113 | extern HReg hregPPC_FPR29 ( void ); |
| 114 | extern HReg hregPPC_FPR30 ( void ); |
| 115 | extern HReg hregPPC_FPR31 ( void ); |
cerion | bcf8c3e | 2005-02-04 16:17:07 +0000 | [diff] [blame] | 116 | |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 117 | extern HReg hregPPC_VR0 ( void ); |
| 118 | extern HReg hregPPC_VR1 ( void ); |
| 119 | extern HReg hregPPC_VR2 ( void ); |
| 120 | extern HReg hregPPC_VR3 ( void ); |
| 121 | extern HReg hregPPC_VR4 ( void ); |
| 122 | extern HReg hregPPC_VR5 ( void ); |
| 123 | extern HReg hregPPC_VR6 ( void ); |
| 124 | extern HReg hregPPC_VR7 ( void ); |
| 125 | extern HReg hregPPC_VR8 ( void ); |
| 126 | extern HReg hregPPC_VR9 ( void ); |
| 127 | extern HReg hregPPC_VR10 ( void ); |
| 128 | extern HReg hregPPC_VR11 ( void ); |
| 129 | extern HReg hregPPC_VR12 ( void ); |
| 130 | extern HReg hregPPC_VR13 ( void ); |
| 131 | extern HReg hregPPC_VR14 ( void ); |
| 132 | extern HReg hregPPC_VR15 ( void ); |
| 133 | extern HReg hregPPC_VR16 ( void ); |
| 134 | extern HReg hregPPC_VR17 ( void ); |
| 135 | extern HReg hregPPC_VR18 ( void ); |
| 136 | extern HReg hregPPC_VR19 ( void ); |
| 137 | extern HReg hregPPC_VR20 ( void ); |
| 138 | extern HReg hregPPC_VR21 ( void ); |
| 139 | extern HReg hregPPC_VR22 ( void ); |
| 140 | extern HReg hregPPC_VR23 ( void ); |
| 141 | extern HReg hregPPC_VR24 ( void ); |
| 142 | extern HReg hregPPC_VR25 ( void ); |
| 143 | extern HReg hregPPC_VR26 ( void ); |
| 144 | extern HReg hregPPC_VR27 ( void ); |
| 145 | extern HReg hregPPC_VR28 ( void ); |
| 146 | extern HReg hregPPC_VR29 ( void ); |
| 147 | extern HReg hregPPC_VR30 ( void ); |
| 148 | extern HReg hregPPC_VR31 ( void ); |
cerion | bcf8c3e | 2005-02-04 16:17:07 +0000 | [diff] [blame] | 149 | |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 150 | #define StackFramePtr(_mode64) hregPPC_GPR1(_mode64) |
| 151 | #define GuestStatePtr(_mode64) hregPPC_GPR31(_mode64) |
cerion | bcf8c3e | 2005-02-04 16:17:07 +0000 | [diff] [blame] | 152 | |
cerion | 2c49e03 | 2005-02-09 17:29:49 +0000 | [diff] [blame] | 153 | |
| 154 | |
sewardj | b51f0f4 | 2005-07-18 11:38:02 +0000 | [diff] [blame] | 155 | /* --------- Condition codes --------- */ |
cerion | 2c49e03 | 2005-02-09 17:29:49 +0000 | [diff] [blame] | 156 | |
sewardj | b51f0f4 | 2005-07-18 11:38:02 +0000 | [diff] [blame] | 157 | /* This gives names from bitfields in CR; hence it names BI numbers */ |
| 158 | /* Using IBM/hardware indexing convention */ |
cerion | 2c49e03 | 2005-02-09 17:29:49 +0000 | [diff] [blame] | 159 | typedef |
sewardj | b51f0f4 | 2005-07-18 11:38:02 +0000 | [diff] [blame] | 160 | enum { |
| 161 | // CR7, which we use for integer compares |
| 162 | Pcf_7LT = 28, /* neg | lt */ |
| 163 | Pcf_7GT = 29, /* pos | gt */ |
| 164 | Pcf_7EQ = 30, /* zero | equal */ |
sewardj | 7e30807 | 2011-05-04 09:50:48 +0000 | [diff] [blame] | 165 | Pcf_7SO = 31, /* summary overflow */ |
| 166 | Pcf_NONE = 32 /* no condition; used with Pct_ALWAYS */ |
cerion | ab9132d | 2005-02-15 15:46:59 +0000 | [diff] [blame] | 167 | } |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 168 | PPCCondFlag; |
cerion | 2c49e03 | 2005-02-09 17:29:49 +0000 | [diff] [blame] | 169 | |
cerion | ab9132d | 2005-02-15 15:46:59 +0000 | [diff] [blame] | 170 | typedef |
cerion | 7cf8e4e | 2005-02-16 16:08:17 +0000 | [diff] [blame] | 171 | enum { /* Maps bc bitfield BO */ |
sewardj | 7e30807 | 2011-05-04 09:50:48 +0000 | [diff] [blame] | 172 | Pct_FALSE = 0x4, /* associated PPCCondFlag must not be Pcf_NONE */ |
| 173 | Pct_TRUE = 0xC, /* associated PPCCondFlag must not be Pcf_NONE */ |
| 174 | Pct_ALWAYS = 0x14 /* associated PPCCondFlag must be Pcf_NONE */ |
cerion | ab9132d | 2005-02-15 15:46:59 +0000 | [diff] [blame] | 175 | } |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 176 | PPCCondTest; |
cerion | ab9132d | 2005-02-15 15:46:59 +0000 | [diff] [blame] | 177 | |
| 178 | typedef |
| 179 | struct { |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 180 | PPCCondFlag flag; |
| 181 | PPCCondTest test; |
cerion | 2c49e03 | 2005-02-09 17:29:49 +0000 | [diff] [blame] | 182 | } |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 183 | PPCCondCode; |
cerion | 2c49e03 | 2005-02-09 17:29:49 +0000 | [diff] [blame] | 184 | |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 185 | extern HChar* showPPCCondCode ( PPCCondCode ); |
cerion | bcf8c3e | 2005-02-04 16:17:07 +0000 | [diff] [blame] | 186 | |
cerion | 7cf8e4e | 2005-02-16 16:08:17 +0000 | [diff] [blame] | 187 | /* constructor */ |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 188 | extern PPCCondCode mk_PPCCondCode ( PPCCondTest, PPCCondFlag ); |
cerion | 7cf8e4e | 2005-02-16 16:08:17 +0000 | [diff] [blame] | 189 | |
| 190 | /* false->true, true->false */ |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 191 | extern PPCCondTest invertCondTest ( PPCCondTest ); |
cerion | bcf8c3e | 2005-02-04 16:17:07 +0000 | [diff] [blame] | 192 | |
cerion | ab9132d | 2005-02-15 15:46:59 +0000 | [diff] [blame] | 193 | |
| 194 | |
cerion | 33aa6da | 2005-02-16 10:25:26 +0000 | [diff] [blame] | 195 | |
cerion | bcf8c3e | 2005-02-04 16:17:07 +0000 | [diff] [blame] | 196 | /* --------- Memory address expressions (amodes). --------- */ |
| 197 | |
| 198 | typedef |
| 199 | enum { |
sewardj | 92923de | 2006-01-25 21:29:48 +0000 | [diff] [blame] | 200 | Pam_IR=1, /* Immediate (signed 16-bit) + Reg */ |
| 201 | Pam_RR=2 /* Reg1 + Reg2 */ |
cerion | bcf8c3e | 2005-02-04 16:17:07 +0000 | [diff] [blame] | 202 | } |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 203 | PPCAModeTag; |
cerion | bcf8c3e | 2005-02-04 16:17:07 +0000 | [diff] [blame] | 204 | |
| 205 | typedef |
| 206 | struct { |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 207 | PPCAModeTag tag; |
cerion | bcf8c3e | 2005-02-04 16:17:07 +0000 | [diff] [blame] | 208 | union { |
| 209 | struct { |
| 210 | HReg base; |
sewardj | a5f957d | 2005-07-02 01:29:32 +0000 | [diff] [blame] | 211 | Int index; |
cerion | bcf8c3e | 2005-02-04 16:17:07 +0000 | [diff] [blame] | 212 | } IR; |
| 213 | struct { |
| 214 | HReg base; |
| 215 | HReg index; |
| 216 | } RR; |
| 217 | } Pam; |
| 218 | } |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 219 | PPCAMode; |
cerion | bcf8c3e | 2005-02-04 16:17:07 +0000 | [diff] [blame] | 220 | |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 221 | extern PPCAMode* PPCAMode_IR ( Int, HReg ); |
| 222 | extern PPCAMode* PPCAMode_RR ( HReg, HReg ); |
cerion | bcf8c3e | 2005-02-04 16:17:07 +0000 | [diff] [blame] | 223 | |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 224 | extern PPCAMode* dopyPPCAMode ( PPCAMode* ); |
cerion | bcf8c3e | 2005-02-04 16:17:07 +0000 | [diff] [blame] | 225 | |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 226 | extern void ppPPCAMode ( PPCAMode* ); |
cerion | bcf8c3e | 2005-02-04 16:17:07 +0000 | [diff] [blame] | 227 | |
| 228 | |
sewardj | b51f0f4 | 2005-07-18 11:38:02 +0000 | [diff] [blame] | 229 | /* --------- Operand, which can be a reg or a u16/s16. --------- */ |
| 230 | /* ("RH" == "Register or Halfword immediate") */ |
cerion | bcf8c3e | 2005-02-04 16:17:07 +0000 | [diff] [blame] | 231 | typedef |
| 232 | enum { |
sewardj | 92923de | 2006-01-25 21:29:48 +0000 | [diff] [blame] | 233 | Prh_Imm=3, |
| 234 | Prh_Reg=4 |
cerion | bcf8c3e | 2005-02-04 16:17:07 +0000 | [diff] [blame] | 235 | } |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 236 | PPCRHTag; |
sewardj | b51f0f4 | 2005-07-18 11:38:02 +0000 | [diff] [blame] | 237 | |
| 238 | typedef |
| 239 | struct { |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 240 | PPCRHTag tag; |
sewardj | b51f0f4 | 2005-07-18 11:38:02 +0000 | [diff] [blame] | 241 | union { |
| 242 | struct { |
| 243 | Bool syned; |
| 244 | UShort imm16; |
| 245 | } Imm; |
| 246 | struct { |
| 247 | HReg reg; |
| 248 | } Reg; |
| 249 | } |
| 250 | Prh; |
| 251 | } |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 252 | PPCRH; |
sewardj | b51f0f4 | 2005-07-18 11:38:02 +0000 | [diff] [blame] | 253 | |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 254 | extern PPCRH* PPCRH_Imm ( Bool, UShort ); |
| 255 | extern PPCRH* PPCRH_Reg ( HReg ); |
sewardj | b51f0f4 | 2005-07-18 11:38:02 +0000 | [diff] [blame] | 256 | |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 257 | extern void ppPPCRH ( PPCRH* ); |
sewardj | b51f0f4 | 2005-07-18 11:38:02 +0000 | [diff] [blame] | 258 | |
| 259 | |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 260 | /* --------- Operand, which can be a reg or a u32/64. --------- */ |
sewardj | b51f0f4 | 2005-07-18 11:38:02 +0000 | [diff] [blame] | 261 | |
| 262 | typedef |
| 263 | enum { |
sewardj | 92923de | 2006-01-25 21:29:48 +0000 | [diff] [blame] | 264 | Pri_Imm=5, |
| 265 | Pri_Reg=6 |
sewardj | b51f0f4 | 2005-07-18 11:38:02 +0000 | [diff] [blame] | 266 | } |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 267 | PPCRITag; |
cerion | bcf8c3e | 2005-02-04 16:17:07 +0000 | [diff] [blame] | 268 | |
| 269 | typedef |
| 270 | struct { |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 271 | PPCRITag tag; |
cerion | bcf8c3e | 2005-02-04 16:17:07 +0000 | [diff] [blame] | 272 | union { |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 273 | ULong Imm; |
| 274 | HReg Reg; |
cerion | bcf8c3e | 2005-02-04 16:17:07 +0000 | [diff] [blame] | 275 | } |
| 276 | Pri; |
| 277 | } |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 278 | PPCRI; |
cerion | bcf8c3e | 2005-02-04 16:17:07 +0000 | [diff] [blame] | 279 | |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 280 | extern PPCRI* PPCRI_Imm ( ULong ); |
sewardj | 478646f | 2008-05-01 20:13:04 +0000 | [diff] [blame] | 281 | extern PPCRI* PPCRI_Reg( HReg ); |
cerion | bcf8c3e | 2005-02-04 16:17:07 +0000 | [diff] [blame] | 282 | |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 283 | extern void ppPPCRI ( PPCRI* ); |
cerion | bcf8c3e | 2005-02-04 16:17:07 +0000 | [diff] [blame] | 284 | |
| 285 | |
cerion | 27b3d7e | 2005-09-14 20:35:47 +0000 | [diff] [blame] | 286 | /* --------- Operand, which can be a vector reg or a s6. --------- */ |
| 287 | /* ("VI" == "Vector Register or Immediate") */ |
| 288 | typedef |
| 289 | enum { |
sewardj | 92923de | 2006-01-25 21:29:48 +0000 | [diff] [blame] | 290 | Pvi_Imm=7, |
| 291 | Pvi_Reg=8 |
cerion | 27b3d7e | 2005-09-14 20:35:47 +0000 | [diff] [blame] | 292 | } |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 293 | PPCVI5sTag; |
cerion | 27b3d7e | 2005-09-14 20:35:47 +0000 | [diff] [blame] | 294 | |
| 295 | typedef |
| 296 | struct { |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 297 | PPCVI5sTag tag; |
cerion | 27b3d7e | 2005-09-14 20:35:47 +0000 | [diff] [blame] | 298 | union { |
| 299 | Char Imm5s; |
| 300 | HReg Reg; |
| 301 | } |
| 302 | Pvi; |
| 303 | } |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 304 | PPCVI5s; |
cerion | 27b3d7e | 2005-09-14 20:35:47 +0000 | [diff] [blame] | 305 | |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 306 | extern PPCVI5s* PPCVI5s_Imm ( Char ); |
| 307 | extern PPCVI5s* PPCVI5s_Reg ( HReg ); |
cerion | 27b3d7e | 2005-09-14 20:35:47 +0000 | [diff] [blame] | 308 | |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 309 | extern void ppPPCVI5s ( PPCVI5s* ); |
cerion | 27b3d7e | 2005-09-14 20:35:47 +0000 | [diff] [blame] | 310 | |
| 311 | |
cerion | cd30449 | 2005-02-08 19:40:24 +0000 | [diff] [blame] | 312 | /* --------- Instructions. --------- */ |
cerion | bcf8c3e | 2005-02-04 16:17:07 +0000 | [diff] [blame] | 313 | |
cerion | 2c49e03 | 2005-02-09 17:29:49 +0000 | [diff] [blame] | 314 | /* --------- */ |
| 315 | typedef |
| 316 | enum { |
| 317 | Pun_NEG, |
cerion | e13bb31 | 2005-02-10 19:51:03 +0000 | [diff] [blame] | 318 | Pun_NOT, |
cerion | 07b07a9 | 2005-12-22 14:32:35 +0000 | [diff] [blame] | 319 | Pun_CLZ32, |
sewardj | 7fd5bb0 | 2006-01-26 02:24:17 +0000 | [diff] [blame] | 320 | Pun_CLZ64, |
| 321 | Pun_EXTSW |
cerion | 2c49e03 | 2005-02-09 17:29:49 +0000 | [diff] [blame] | 322 | } |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 323 | PPCUnaryOp; |
cerion | 2c49e03 | 2005-02-09 17:29:49 +0000 | [diff] [blame] | 324 | |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 325 | extern HChar* showPPCUnaryOp ( PPCUnaryOp ); |
cerion | cd30449 | 2005-02-08 19:40:24 +0000 | [diff] [blame] | 326 | |
| 327 | |
| 328 | /* --------- */ |
| 329 | typedef |
| 330 | enum { |
| 331 | Palu_INVALID, |
sewardj | b51f0f4 | 2005-07-18 11:38:02 +0000 | [diff] [blame] | 332 | Palu_ADD, Palu_SUB, |
| 333 | Palu_AND, Palu_OR, Palu_XOR, |
cerion | cd30449 | 2005-02-08 19:40:24 +0000 | [diff] [blame] | 334 | } |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 335 | PPCAluOp; |
cerion | cd30449 | 2005-02-08 19:40:24 +0000 | [diff] [blame] | 336 | |
sewardj | b51f0f4 | 2005-07-18 11:38:02 +0000 | [diff] [blame] | 337 | extern |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 338 | HChar* showPPCAluOp ( PPCAluOp, |
| 339 | Bool /* is the 2nd operand an immediate? */); |
cerion | bb01b7c | 2005-12-16 13:40:18 +0000 | [diff] [blame] | 340 | |
| 341 | |
| 342 | /* --------- */ |
| 343 | typedef |
| 344 | enum { |
| 345 | Pshft_INVALID, |
| 346 | Pshft_SHL, Pshft_SHR, Pshft_SAR, |
| 347 | } |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 348 | PPCShftOp; |
cerion | bb01b7c | 2005-12-16 13:40:18 +0000 | [diff] [blame] | 349 | |
| 350 | extern |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 351 | HChar* showPPCShftOp ( PPCShftOp, |
| 352 | Bool /* is the 2nd operand an immediate? */, |
| 353 | Bool /* is this a 32bit or 64bit op? */ ); |
cerion | ab9132d | 2005-02-15 15:46:59 +0000 | [diff] [blame] | 354 | |
| 355 | |
cerion | 094d139 | 2005-06-20 13:45:57 +0000 | [diff] [blame] | 356 | /* --------- */ |
| 357 | typedef |
| 358 | enum { |
| 359 | Pfp_INVALID, |
sewardj | 40c8026 | 2006-02-08 19:30:46 +0000 | [diff] [blame] | 360 | |
| 361 | /* Ternary */ |
| 362 | Pfp_MADDD, Pfp_MSUBD, |
| 363 | Pfp_MADDS, Pfp_MSUBS, |
| 364 | |
cerion | 094d139 | 2005-06-20 13:45:57 +0000 | [diff] [blame] | 365 | /* Binary */ |
sewardj | b183b85 | 2006-02-03 16:08:03 +0000 | [diff] [blame] | 366 | Pfp_ADDD, Pfp_SUBD, Pfp_MULD, Pfp_DIVD, |
| 367 | Pfp_ADDS, Pfp_SUBS, Pfp_MULS, Pfp_DIVS, |
cerion | 094d139 | 2005-06-20 13:45:57 +0000 | [diff] [blame] | 368 | |
| 369 | /* Unary */ |
sewardj | 0f1ef86 | 2008-08-08 08:37:06 +0000 | [diff] [blame] | 370 | Pfp_SQRT, Pfp_ABS, Pfp_NEG, Pfp_MOV, Pfp_RES, Pfp_RSQRTE, |
| 371 | Pfp_FRIN, Pfp_FRIM, Pfp_FRIP, Pfp_FRIZ |
cerion | 094d139 | 2005-06-20 13:45:57 +0000 | [diff] [blame] | 372 | } |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 373 | PPCFpOp; |
cerion | 094d139 | 2005-06-20 13:45:57 +0000 | [diff] [blame] | 374 | |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 375 | extern HChar* showPPCFpOp ( PPCFpOp ); |
cerion | bcf8c3e | 2005-02-04 16:17:07 +0000 | [diff] [blame] | 376 | |
| 377 | |
| 378 | /* --------- */ |
| 379 | typedef |
| 380 | enum { |
cerion | c3d8bdc | 2005-06-28 18:06:23 +0000 | [diff] [blame] | 381 | Pav_INVALID, |
| 382 | |
| 383 | /* Integer Unary */ |
| 384 | Pav_MOV, /* Mov */ |
| 385 | Pav_NOT, /* Bitwise */ |
| 386 | Pav_UNPCKH8S, Pav_UNPCKH16S, /* Unpack */ |
| 387 | Pav_UNPCKL8S, Pav_UNPCKL16S, |
| 388 | Pav_UNPCKHPIX, Pav_UNPCKLPIX, |
| 389 | |
| 390 | /* Integer Binary */ |
cerion | 8ea0d3e | 2005-11-14 00:44:47 +0000 | [diff] [blame] | 391 | Pav_AND, Pav_OR, Pav_XOR, /* Bitwise */ |
cerion | f34ccc4 | 2005-09-16 08:55:50 +0000 | [diff] [blame] | 392 | Pav_ADDU, Pav_QADDU, Pav_QADDS, |
cerion | f34ccc4 | 2005-09-16 08:55:50 +0000 | [diff] [blame] | 393 | Pav_SUBU, Pav_QSUBU, Pav_QSUBS, |
cerion | 6b6f59e | 2005-06-28 20:59:18 +0000 | [diff] [blame] | 394 | Pav_OMULU, Pav_OMULS, Pav_EMULU, Pav_EMULS, |
cerion | 6b6f59e | 2005-06-28 20:59:18 +0000 | [diff] [blame] | 395 | Pav_AVGU, Pav_AVGS, |
| 396 | Pav_MAXU, Pav_MAXS, |
| 397 | Pav_MINU, Pav_MINS, |
cerion | c3d8bdc | 2005-06-28 18:06:23 +0000 | [diff] [blame] | 398 | |
| 399 | /* Compare (always affects CR field 6) */ |
cerion | 6b6f59e | 2005-06-28 20:59:18 +0000 | [diff] [blame] | 400 | Pav_CMPEQU, Pav_CMPGTU, Pav_CMPGTS, |
cerion | c3d8bdc | 2005-06-28 18:06:23 +0000 | [diff] [blame] | 401 | |
| 402 | /* Shift */ |
cerion | 6b6f59e | 2005-06-28 20:59:18 +0000 | [diff] [blame] | 403 | Pav_SHL, Pav_SHR, Pav_SAR, Pav_ROTL, |
cerion | c3d8bdc | 2005-06-28 18:06:23 +0000 | [diff] [blame] | 404 | |
| 405 | /* Pack */ |
cerion | f34ccc4 | 2005-09-16 08:55:50 +0000 | [diff] [blame] | 406 | Pav_PACKUU, Pav_QPACKUU, Pav_QPACKSU, Pav_QPACKSS, |
cerion | 6b6f59e | 2005-06-28 20:59:18 +0000 | [diff] [blame] | 407 | Pav_PACKPXL, |
cerion | c3d8bdc | 2005-06-28 18:06:23 +0000 | [diff] [blame] | 408 | |
| 409 | /* Merge */ |
cerion | 6b6f59e | 2005-06-28 20:59:18 +0000 | [diff] [blame] | 410 | Pav_MRGHI, Pav_MRGLO, |
cerion | c3d8bdc | 2005-06-28 18:06:23 +0000 | [diff] [blame] | 411 | } |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 412 | PPCAvOp; |
cerion | c3d8bdc | 2005-06-28 18:06:23 +0000 | [diff] [blame] | 413 | |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 414 | extern HChar* showPPCAvOp ( PPCAvOp ); |
cerion | c3d8bdc | 2005-06-28 18:06:23 +0000 | [diff] [blame] | 415 | |
| 416 | |
| 417 | /* --------- */ |
| 418 | typedef |
| 419 | enum { |
cerion | 8ea0d3e | 2005-11-14 00:44:47 +0000 | [diff] [blame] | 420 | Pavfp_INVALID, |
| 421 | |
| 422 | /* Floating point binary */ |
| 423 | Pavfp_ADDF, Pavfp_SUBF, Pavfp_MULF, |
| 424 | Pavfp_MAXF, Pavfp_MINF, |
| 425 | Pavfp_CMPEQF, Pavfp_CMPGTF, Pavfp_CMPGEF, |
| 426 | |
| 427 | /* Floating point unary */ |
| 428 | Pavfp_RCPF, Pavfp_RSQRTF, |
cerion | d963eb4 | 2005-11-16 18:02:58 +0000 | [diff] [blame] | 429 | Pavfp_CVTU2F, Pavfp_CVTS2F, Pavfp_QCVTF2U, Pavfp_QCVTF2S, |
| 430 | Pavfp_ROUNDM, Pavfp_ROUNDP, Pavfp_ROUNDN, Pavfp_ROUNDZ, |
cerion | 8ea0d3e | 2005-11-14 00:44:47 +0000 | [diff] [blame] | 431 | } |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 432 | PPCAvFpOp; |
cerion | 8ea0d3e | 2005-11-14 00:44:47 +0000 | [diff] [blame] | 433 | |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 434 | extern HChar* showPPCAvFpOp ( PPCAvFpOp ); |
cerion | 8ea0d3e | 2005-11-14 00:44:47 +0000 | [diff] [blame] | 435 | |
| 436 | |
| 437 | /* --------- */ |
| 438 | typedef |
| 439 | enum { |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 440 | Pin_LI, /* load word (32/64-bit) immediate (fake insn) */ |
cerion | bb01b7c | 2005-12-16 13:40:18 +0000 | [diff] [blame] | 441 | Pin_Alu, /* word add/sub/and/or/xor */ |
| 442 | Pin_Shft, /* word shl/shr/sar */ |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 443 | Pin_AddSubC, /* add/sub with read/write carry */ |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 444 | Pin_Cmp, /* word compare */ |
| 445 | Pin_Unary, /* not, neg, clz */ |
cerion | ed623db | 2005-06-20 12:42:04 +0000 | [diff] [blame] | 446 | Pin_MulL, /* widening multiply */ |
| 447 | Pin_Div, /* div */ |
| 448 | Pin_Call, /* call to address in register */ |
| 449 | Pin_Goto, /* conditional/unconditional jmp to dst */ |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 450 | Pin_CMov, /* conditional move */ |
sewardj | 7fd5bb0 | 2006-01-26 02:24:17 +0000 | [diff] [blame] | 451 | Pin_Load, /* zero-extending load a 8|16|32|64 bit value from mem */ |
sewardj | e9d8a26 | 2009-07-01 08:06:34 +0000 | [diff] [blame] | 452 | Pin_LoadL, /* load-linked (lwarx/ldarx) 32|64 bit value from mem */ |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 453 | Pin_Store, /* store a 8|16|32|64 bit value to mem */ |
sewardj | e9d8a26 | 2009-07-01 08:06:34 +0000 | [diff] [blame] | 454 | Pin_StoreC, /* store-conditional (stwcx./stdcx.) 32|64 bit val */ |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 455 | Pin_Set, /* convert condition code to value 0 or 1 */ |
sewardj | b51f0f4 | 2005-07-18 11:38:02 +0000 | [diff] [blame] | 456 | Pin_MfCR, /* move from condition register to GPR */ |
| 457 | Pin_MFence, /* mem fence */ |
cerion | c3d8bdc | 2005-06-28 18:06:23 +0000 | [diff] [blame] | 458 | |
cerion | 094d139 | 2005-06-20 13:45:57 +0000 | [diff] [blame] | 459 | Pin_FpUnary, /* FP unary op */ |
| 460 | Pin_FpBinary, /* FP binary op */ |
sewardj | 40c8026 | 2006-02-08 19:30:46 +0000 | [diff] [blame] | 461 | Pin_FpMulAcc, /* FP multipy-accumulate style op */ |
cerion | 094d139 | 2005-06-20 13:45:57 +0000 | [diff] [blame] | 462 | Pin_FpLdSt, /* FP load/store */ |
sewardj | 92923de | 2006-01-25 21:29:48 +0000 | [diff] [blame] | 463 | Pin_FpSTFIW, /* stfiwx */ |
| 464 | Pin_FpRSP, /* FP round IEEE754 double to IEEE754 single */ |
sewardj | 7d810d7 | 2011-05-08 22:05:10 +0000 | [diff] [blame] | 465 | Pin_FpCftI, /* fcfid[u,s,us]/fctid[u]/fctiw[u] */ |
cerion | 094d139 | 2005-06-20 13:45:57 +0000 | [diff] [blame] | 466 | Pin_FpCMov, /* FP floating point conditional move */ |
| 467 | Pin_FpLdFPSCR, /* mtfsf */ |
| 468 | Pin_FpCmp, /* FP compare, generating value into int reg */ |
sewardj | 92923de | 2006-01-25 21:29:48 +0000 | [diff] [blame] | 469 | |
cerion | c3d8bdc | 2005-06-28 18:06:23 +0000 | [diff] [blame] | 470 | Pin_RdWrLR, /* Read/Write Link Register */ |
| 471 | |
cerion | c3d8bdc | 2005-06-28 18:06:23 +0000 | [diff] [blame] | 472 | Pin_AvLdSt, /* AV load/store (kludging for AMode_IR) */ |
| 473 | Pin_AvUnary, /* AV unary general reg=>reg */ |
cerion | 6b6f59e | 2005-06-28 20:59:18 +0000 | [diff] [blame] | 474 | |
cerion | c3d8bdc | 2005-06-28 18:06:23 +0000 | [diff] [blame] | 475 | Pin_AvBinary, /* AV binary general reg,reg=>reg */ |
cerion | 6b6f59e | 2005-06-28 20:59:18 +0000 | [diff] [blame] | 476 | Pin_AvBin8x16, /* AV binary, 8x4 */ |
| 477 | Pin_AvBin16x8, /* AV binary, 16x4 */ |
| 478 | Pin_AvBin32x4, /* AV binary, 32x4 */ |
| 479 | |
| 480 | Pin_AvBin32Fx4, /* AV FP binary, 32Fx4 */ |
cerion | 8ea0d3e | 2005-11-14 00:44:47 +0000 | [diff] [blame] | 481 | Pin_AvUn32Fx4, /* AV FP unary, 32Fx4 */ |
cerion | c3d8bdc | 2005-06-28 18:06:23 +0000 | [diff] [blame] | 482 | |
| 483 | Pin_AvPerm, /* AV permute (shuffle) */ |
| 484 | Pin_AvSel, /* AV select */ |
| 485 | Pin_AvShlDbl, /* AV shift-left double by imm */ |
| 486 | Pin_AvSplat, /* One elem repeated throughout dst */ |
cerion | 6b6f59e | 2005-06-28 20:59:18 +0000 | [diff] [blame] | 487 | Pin_AvLdVSCR, /* mtvscr */ |
| 488 | Pin_AvCMov /* AV conditional move */ |
cerion | bcf8c3e | 2005-02-04 16:17:07 +0000 | [diff] [blame] | 489 | } |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 490 | PPCInstrTag; |
cerion | bcf8c3e | 2005-02-04 16:17:07 +0000 | [diff] [blame] | 491 | |
cerion | cd30449 | 2005-02-08 19:40:24 +0000 | [diff] [blame] | 492 | /* Destinations are on the LEFT (first operand) */ |
cerion | bcf8c3e | 2005-02-04 16:17:07 +0000 | [diff] [blame] | 493 | |
| 494 | typedef |
| 495 | struct { |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 496 | PPCInstrTag tag; |
cerion | cd30449 | 2005-02-08 19:40:24 +0000 | [diff] [blame] | 497 | union { |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 498 | /* Get a 32/64-bit literal into a register. |
| 499 | May turn into a number of real insns. */ |
sewardj | b51f0f4 | 2005-07-18 11:38:02 +0000 | [diff] [blame] | 500 | struct { |
| 501 | HReg dst; |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 502 | ULong imm64; |
| 503 | } LI; |
cerion | bb01b7c | 2005-12-16 13:40:18 +0000 | [diff] [blame] | 504 | /* Integer add/sub/and/or/xor. Limitations: |
sewardj | b51f0f4 | 2005-07-18 11:38:02 +0000 | [diff] [blame] | 505 | - For add, the immediate, if it exists, is a signed 16. |
| 506 | - For sub, the immediate, if it exists, is a signed 16 |
| 507 | which may not be -32768, since no such instruction |
| 508 | exists, and so we have to emit addi with +32768, but |
| 509 | that is not possible. |
| 510 | - For and/or/xor, the immediate, if it exists, |
| 511 | is an unsigned 16. |
sewardj | b51f0f4 | 2005-07-18 11:38:02 +0000 | [diff] [blame] | 512 | */ |
cerion | cd30449 | 2005-02-08 19:40:24 +0000 | [diff] [blame] | 513 | struct { |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 514 | PPCAluOp op; |
| 515 | HReg dst; |
| 516 | HReg srcL; |
| 517 | PPCRH* srcR; |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 518 | } Alu; |
cerion | bb01b7c | 2005-12-16 13:40:18 +0000 | [diff] [blame] | 519 | /* Integer shl/shr/sar. |
| 520 | Limitations: the immediate, if it exists, |
| 521 | is a signed 5-bit value between 1 and 31 inclusive. |
| 522 | */ |
| 523 | struct { |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 524 | PPCShftOp op; |
| 525 | Bool sz32; /* mode64 has both 32 and 64bit shft */ |
| 526 | HReg dst; |
| 527 | HReg srcL; |
| 528 | PPCRH* srcR; |
cerion | bb01b7c | 2005-12-16 13:40:18 +0000 | [diff] [blame] | 529 | } Shft; |
cerion | 4a49b03 | 2005-11-08 16:23:07 +0000 | [diff] [blame] | 530 | /* */ |
| 531 | struct { |
| 532 | Bool isAdd; /* else sub */ |
| 533 | Bool setC; /* else read carry */ |
| 534 | HReg dst; |
| 535 | HReg srcL; |
| 536 | HReg srcR; |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 537 | } AddSubC; |
sewardj | b51f0f4 | 2005-07-18 11:38:02 +0000 | [diff] [blame] | 538 | /* If signed, the immediate, if it exists, is a signed 16, |
| 539 | else it is an unsigned 16. */ |
cerion | cd30449 | 2005-02-08 19:40:24 +0000 | [diff] [blame] | 540 | struct { |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 541 | Bool syned; |
| 542 | Bool sz32; /* mode64 has both 32 and 64bit cmp */ |
| 543 | UInt crfD; |
| 544 | HReg srcL; |
| 545 | PPCRH* srcR; |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 546 | } Cmp; |
sewardj | 7fd5bb0 | 2006-01-26 02:24:17 +0000 | [diff] [blame] | 547 | /* Not, Neg, Clz32/64, Extsw */ |
cerion | 2c49e03 | 2005-02-09 17:29:49 +0000 | [diff] [blame] | 548 | struct { |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 549 | PPCUnaryOp op; |
| 550 | HReg dst; |
| 551 | HReg src; |
| 552 | } Unary; |
cerion | 92f5dc7 | 2005-02-10 16:11:35 +0000 | [diff] [blame] | 553 | struct { |
sewardj | b51f0f4 | 2005-07-18 11:38:02 +0000 | [diff] [blame] | 554 | Bool syned; /* meaningless if hi32==False */ |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 555 | Bool hi; /* False=>low, True=>high */ |
cerion | bb01b7c | 2005-12-16 13:40:18 +0000 | [diff] [blame] | 556 | Bool sz32; /* mode64 has both 32 & 64bit mull */ |
sewardj | b51f0f4 | 2005-07-18 11:38:02 +0000 | [diff] [blame] | 557 | HReg dst; |
| 558 | HReg srcL; |
| 559 | HReg srcR; |
cerion | 92f5dc7 | 2005-02-10 16:11:35 +0000 | [diff] [blame] | 560 | } MulL; |
cerion | 9e263e3 | 2005-03-03 17:21:51 +0000 | [diff] [blame] | 561 | /* ppc32 div/divu instruction. */ |
cerion | c0e707e | 2005-02-10 22:35:34 +0000 | [diff] [blame] | 562 | struct { |
cerion | 33aa6da | 2005-02-16 10:25:26 +0000 | [diff] [blame] | 563 | Bool syned; |
cerion | bb01b7c | 2005-12-16 13:40:18 +0000 | [diff] [blame] | 564 | Bool sz32; /* mode64 has both 32 & 64bit div */ |
cerion | 33aa6da | 2005-02-16 10:25:26 +0000 | [diff] [blame] | 565 | HReg dst; |
cerion | a2f7588 | 2005-03-15 16:33:38 +0000 | [diff] [blame] | 566 | HReg srcL; |
| 567 | HReg srcR; |
cerion | c0e707e | 2005-02-10 22:35:34 +0000 | [diff] [blame] | 568 | } Div; |
cerion | 2c49e03 | 2005-02-09 17:29:49 +0000 | [diff] [blame] | 569 | /* Pseudo-insn. Call target (an absolute address), on given |
sewardj | 6a64a9f | 2005-08-21 00:48:37 +0000 | [diff] [blame] | 570 | condition (which could be Pct_ALWAYS). argiregs indicates |
| 571 | which of r3 .. r10 carries argument values for this call, |
| 572 | using a bit mask (1<<N is set if rN holds an arg, for N in |
| 573 | 3 .. 10 inclusive). */ |
cerion | 2c49e03 | 2005-02-09 17:29:49 +0000 | [diff] [blame] | 574 | struct { |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 575 | PPCCondCode cond; |
| 576 | Addr64 target; |
| 577 | UInt argiregs; |
cerion | 2c49e03 | 2005-02-09 17:29:49 +0000 | [diff] [blame] | 578 | } Call; |
| 579 | /* Pseudo-insn. Goto dst, on given condition (which could be |
sewardj | b51f0f4 | 2005-07-18 11:38:02 +0000 | [diff] [blame] | 580 | Pct_ALWAYS). */ |
cerion | 2c49e03 | 2005-02-09 17:29:49 +0000 | [diff] [blame] | 581 | struct { |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 582 | IRJumpKind jk; |
| 583 | PPCCondCode cond; |
| 584 | PPCRI* dst; |
cerion | 2c49e03 | 2005-02-09 17:29:49 +0000 | [diff] [blame] | 585 | } Goto; |
cerion | b536af9 | 2005-02-10 15:03:19 +0000 | [diff] [blame] | 586 | /* Mov src to dst on the given condition, which may not |
cerion | 9abfcbc | 2005-02-25 11:16:58 +0000 | [diff] [blame] | 587 | be the bogus Pct_ALWAYS. */ |
cerion | b536af9 | 2005-02-10 15:03:19 +0000 | [diff] [blame] | 588 | struct { |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 589 | PPCCondCode cond; |
cerion | cd30449 | 2005-02-08 19:40:24 +0000 | [diff] [blame] | 590 | HReg dst; |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 591 | PPCRI* src; |
| 592 | } CMov; |
sewardj | 7fd5bb0 | 2006-01-26 02:24:17 +0000 | [diff] [blame] | 593 | /* Zero extending loads. Dst size is host word size */ |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 594 | struct { |
| 595 | UChar sz; /* 1|2|4|8 */ |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 596 | HReg dst; |
| 597 | PPCAMode* src; |
cerion | 7cf8e4e | 2005-02-16 16:08:17 +0000 | [diff] [blame] | 598 | } Load; |
sewardj | e9d8a26 | 2009-07-01 08:06:34 +0000 | [diff] [blame] | 599 | /* Load-and-reserve (lwarx, ldarx) */ |
| 600 | struct { |
| 601 | UChar sz; /* 4|8 */ |
| 602 | HReg dst; |
| 603 | HReg src; |
| 604 | } LoadL; |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 605 | /* 64/32/16/8 bit stores */ |
cerion | cd30449 | 2005-02-08 19:40:24 +0000 | [diff] [blame] | 606 | struct { |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 607 | UChar sz; /* 1|2|4|8 */ |
| 608 | PPCAMode* dst; |
| 609 | HReg src; |
cerion | cd30449 | 2005-02-08 19:40:24 +0000 | [diff] [blame] | 610 | } Store; |
sewardj | e9d8a26 | 2009-07-01 08:06:34 +0000 | [diff] [blame] | 611 | /* Store-conditional (stwcx., stdcx.) */ |
| 612 | struct { |
| 613 | UChar sz; /* 4|8 */ |
| 614 | HReg dst; |
| 615 | HReg src; |
| 616 | } StoreC; |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 617 | /* Convert a ppc condition code to value 0 or 1. */ |
cerion | b536af9 | 2005-02-10 15:03:19 +0000 | [diff] [blame] | 618 | struct { |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 619 | PPCCondCode cond; |
| 620 | HReg dst; |
| 621 | } Set; |
sewardj | b51f0f4 | 2005-07-18 11:38:02 +0000 | [diff] [blame] | 622 | /* Move the entire CR to a GPR */ |
| 623 | struct { |
| 624 | HReg dst; |
| 625 | } MfCR; |
cerion | 98411db | 2005-02-16 14:14:49 +0000 | [diff] [blame] | 626 | /* Mem fence. In short, an insn which flushes all preceding |
| 627 | loads and stores as much as possible before continuing. |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 628 | On PPC we emit a "sync". */ |
cerion | 92f5dc7 | 2005-02-10 16:11:35 +0000 | [diff] [blame] | 629 | struct { |
cerion | 92f5dc7 | 2005-02-10 16:11:35 +0000 | [diff] [blame] | 630 | } MFence; |
cerion | cd30449 | 2005-02-08 19:40:24 +0000 | [diff] [blame] | 631 | |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 632 | /* PPC Floating point */ |
cerion | 094d139 | 2005-06-20 13:45:57 +0000 | [diff] [blame] | 633 | struct { |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 634 | PPCFpOp op; |
| 635 | HReg dst; |
| 636 | HReg src; |
cerion | 094d139 | 2005-06-20 13:45:57 +0000 | [diff] [blame] | 637 | } FpUnary; |
| 638 | struct { |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 639 | PPCFpOp op; |
| 640 | HReg dst; |
| 641 | HReg srcL; |
| 642 | HReg srcR; |
cerion | 094d139 | 2005-06-20 13:45:57 +0000 | [diff] [blame] | 643 | } FpBinary; |
| 644 | struct { |
sewardj | 40c8026 | 2006-02-08 19:30:46 +0000 | [diff] [blame] | 645 | PPCFpOp op; |
| 646 | HReg dst; |
| 647 | HReg srcML; |
| 648 | HReg srcMR; |
| 649 | HReg srcAcc; |
| 650 | } FpMulAcc; |
| 651 | struct { |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 652 | Bool isLoad; |
| 653 | UChar sz; /* only 4 (IEEE single) or 8 (IEEE double) */ |
| 654 | HReg reg; |
| 655 | PPCAMode* addr; |
cerion | 094d139 | 2005-06-20 13:45:57 +0000 | [diff] [blame] | 656 | } FpLdSt; |
sewardj | 92923de | 2006-01-25 21:29:48 +0000 | [diff] [blame] | 657 | struct { |
| 658 | HReg addr; /* int reg */ |
| 659 | HReg data; /* float reg */ |
| 660 | } FpSTFIW; |
| 661 | /* Round 64-bit FP value to 32-bit FP value in an FP reg. */ |
cerion | 094d139 | 2005-06-20 13:45:57 +0000 | [diff] [blame] | 662 | struct { |
| 663 | HReg src; |
| 664 | HReg dst; |
sewardj | 92923de | 2006-01-25 21:29:48 +0000 | [diff] [blame] | 665 | } FpRSP; |
sewardj | 7d810d7 | 2011-05-08 22:05:10 +0000 | [diff] [blame] | 666 | /* fcfid[u,s,us]/fctid[u]/fctiw[u]. Only some combinations |
| 667 | of the various fields are allowed. This is asserted for |
| 668 | and documented in the code for the constructor, |
| 669 | PPCInstr_FpCftI, in host_ppc_defs.c. */ |
cerion | 094d139 | 2005-06-20 13:45:57 +0000 | [diff] [blame] | 670 | struct { |
sewardj | 7d810d7 | 2011-05-08 22:05:10 +0000 | [diff] [blame] | 671 | Bool fromI; /* True== I->F, False== F->I */ |
| 672 | Bool int32; /* True== I is 32, False== I is 64 */ |
sewardj | 66d5ef2 | 2011-04-15 11:55:00 +0000 | [diff] [blame] | 673 | Bool syned; |
sewardj | 7d810d7 | 2011-05-08 22:05:10 +0000 | [diff] [blame] | 674 | Bool flt64; /* True== F is 64, False== F is 32 */ |
cerion | 094d139 | 2005-06-20 13:45:57 +0000 | [diff] [blame] | 675 | HReg src; |
| 676 | HReg dst; |
sewardj | 92923de | 2006-01-25 21:29:48 +0000 | [diff] [blame] | 677 | } FpCftI; |
| 678 | /* FP mov src to dst on the given condition. */ |
cerion | 094d139 | 2005-06-20 13:45:57 +0000 | [diff] [blame] | 679 | struct { |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 680 | PPCCondCode cond; |
| 681 | HReg dst; |
| 682 | HReg src; |
cerion | 094d139 | 2005-06-20 13:45:57 +0000 | [diff] [blame] | 683 | } FpCMov; |
| 684 | /* Load FP Status & Control Register */ |
| 685 | struct { |
| 686 | HReg src; |
| 687 | } FpLdFPSCR; |
sewardj | b51f0f4 | 2005-07-18 11:38:02 +0000 | [diff] [blame] | 688 | /* Do a compare, generating result into an int register. */ |
cerion | 094d139 | 2005-06-20 13:45:57 +0000 | [diff] [blame] | 689 | struct { |
| 690 | UChar crfD; |
| 691 | HReg dst; |
| 692 | HReg srcL; |
| 693 | HReg srcR; |
| 694 | } FpCmp; |
cerion | cd30449 | 2005-02-08 19:40:24 +0000 | [diff] [blame] | 695 | |
cerion | 7f000af | 2005-02-22 20:36:49 +0000 | [diff] [blame] | 696 | /* Read/Write Link Register */ |
| 697 | struct { |
| 698 | Bool wrLR; |
| 699 | HReg gpr; |
| 700 | } RdWrLR; |
cerion | c3d8bdc | 2005-06-28 18:06:23 +0000 | [diff] [blame] | 701 | |
| 702 | /* Simplistic AltiVec */ |
| 703 | struct { |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 704 | Bool isLoad; |
| 705 | UChar sz; /* 8|16|32|128 */ |
| 706 | HReg reg; |
| 707 | PPCAMode* addr; |
cerion | c3d8bdc | 2005-06-28 18:06:23 +0000 | [diff] [blame] | 708 | } AvLdSt; |
| 709 | struct { |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 710 | PPCAvOp op; |
| 711 | HReg dst; |
| 712 | HReg src; |
cerion | c3d8bdc | 2005-06-28 18:06:23 +0000 | [diff] [blame] | 713 | } AvUnary; |
| 714 | struct { |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 715 | PPCAvOp op; |
| 716 | HReg dst; |
| 717 | HReg srcL; |
| 718 | HReg srcR; |
cerion | c3d8bdc | 2005-06-28 18:06:23 +0000 | [diff] [blame] | 719 | } AvBinary; |
cerion | 6b6f59e | 2005-06-28 20:59:18 +0000 | [diff] [blame] | 720 | struct { |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 721 | PPCAvOp op; |
| 722 | HReg dst; |
| 723 | HReg srcL; |
| 724 | HReg srcR; |
cerion | 6b6f59e | 2005-06-28 20:59:18 +0000 | [diff] [blame] | 725 | } AvBin8x16; |
| 726 | struct { |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 727 | PPCAvOp op; |
| 728 | HReg dst; |
| 729 | HReg srcL; |
| 730 | HReg srcR; |
cerion | 6b6f59e | 2005-06-28 20:59:18 +0000 | [diff] [blame] | 731 | } AvBin16x8; |
| 732 | struct { |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 733 | PPCAvOp op; |
| 734 | HReg dst; |
| 735 | HReg srcL; |
| 736 | HReg srcR; |
cerion | 6b6f59e | 2005-06-28 20:59:18 +0000 | [diff] [blame] | 737 | } AvBin32x4; |
| 738 | struct { |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 739 | PPCAvFpOp op; |
cerion | 6b6f59e | 2005-06-28 20:59:18 +0000 | [diff] [blame] | 740 | HReg dst; |
| 741 | HReg srcL; |
| 742 | HReg srcR; |
| 743 | } AvBin32Fx4; |
cerion | 8ea0d3e | 2005-11-14 00:44:47 +0000 | [diff] [blame] | 744 | struct { |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 745 | PPCAvFpOp op; |
cerion | 8ea0d3e | 2005-11-14 00:44:47 +0000 | [diff] [blame] | 746 | HReg dst; |
| 747 | HReg src; |
| 748 | } AvUn32Fx4; |
cerion | c3d8bdc | 2005-06-28 18:06:23 +0000 | [diff] [blame] | 749 | /* Perm,Sel,SlDbl,Splat are all weird AV permutations */ |
| 750 | struct { |
cerion | c3d8bdc | 2005-06-28 18:06:23 +0000 | [diff] [blame] | 751 | HReg dst; |
| 752 | HReg srcL; |
| 753 | HReg srcR; |
cerion | 92d9d87 | 2005-09-15 21:58:50 +0000 | [diff] [blame] | 754 | HReg ctl; |
cerion | c3d8bdc | 2005-06-28 18:06:23 +0000 | [diff] [blame] | 755 | } AvPerm; |
| 756 | struct { |
cerion | c3d8bdc | 2005-06-28 18:06:23 +0000 | [diff] [blame] | 757 | HReg dst; |
| 758 | HReg srcL; |
| 759 | HReg srcR; |
cerion | 92d9d87 | 2005-09-15 21:58:50 +0000 | [diff] [blame] | 760 | HReg ctl; |
cerion | c3d8bdc | 2005-06-28 18:06:23 +0000 | [diff] [blame] | 761 | } AvSel; |
| 762 | struct { |
| 763 | UChar shift; |
| 764 | HReg dst; |
| 765 | HReg srcL; |
| 766 | HReg srcR; |
| 767 | } AvShlDbl; |
| 768 | struct { |
| 769 | UChar sz; /* 8,16,32 */ |
| 770 | HReg dst; |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 771 | PPCVI5s* src; |
cerion | c3d8bdc | 2005-06-28 18:06:23 +0000 | [diff] [blame] | 772 | } AvSplat; |
cerion | 6b6f59e | 2005-06-28 20:59:18 +0000 | [diff] [blame] | 773 | /* Mov src to dst on the given condition, which may not |
| 774 | be the bogus Xcc_ALWAYS. */ |
| 775 | struct { |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 776 | PPCCondCode cond; |
| 777 | HReg dst; |
| 778 | HReg src; |
cerion | 6b6f59e | 2005-06-28 20:59:18 +0000 | [diff] [blame] | 779 | } AvCMov; |
sewardj | b51f0f4 | 2005-07-18 11:38:02 +0000 | [diff] [blame] | 780 | /* Load AltiVec Status & Control Register */ |
cerion | c3d8bdc | 2005-06-28 18:06:23 +0000 | [diff] [blame] | 781 | struct { |
| 782 | HReg src; |
| 783 | } AvLdVSCR; |
cerion | cd30449 | 2005-02-08 19:40:24 +0000 | [diff] [blame] | 784 | } Pin; |
cerion | bcf8c3e | 2005-02-04 16:17:07 +0000 | [diff] [blame] | 785 | } |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 786 | PPCInstr; |
cerion | bcf8c3e | 2005-02-04 16:17:07 +0000 | [diff] [blame] | 787 | |
cerion | cd30449 | 2005-02-08 19:40:24 +0000 | [diff] [blame] | 788 | |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 789 | extern PPCInstr* PPCInstr_LI ( HReg, ULong, Bool ); |
| 790 | extern PPCInstr* PPCInstr_Alu ( PPCAluOp, HReg, HReg, PPCRH* ); |
| 791 | extern PPCInstr* PPCInstr_Shft ( PPCShftOp, Bool sz32, HReg, HReg, PPCRH* ); |
| 792 | extern PPCInstr* PPCInstr_AddSubC ( Bool, Bool, HReg, HReg, HReg ); |
| 793 | extern PPCInstr* PPCInstr_Cmp ( Bool, Bool, UInt, HReg, PPCRH* ); |
| 794 | extern PPCInstr* PPCInstr_Unary ( PPCUnaryOp op, HReg dst, HReg src ); |
| 795 | extern PPCInstr* PPCInstr_MulL ( Bool syned, Bool hi32, Bool sz32, HReg, HReg, HReg ); |
| 796 | extern PPCInstr* PPCInstr_Div ( Bool syned, Bool sz32, HReg dst, HReg srcL, HReg srcR ); |
| 797 | extern PPCInstr* PPCInstr_Call ( PPCCondCode, Addr64, UInt ); |
| 798 | extern PPCInstr* PPCInstr_Goto ( IRJumpKind, PPCCondCode cond, PPCRI* dst ); |
| 799 | extern PPCInstr* PPCInstr_CMov ( PPCCondCode, HReg dst, PPCRI* src ); |
sewardj | 7fd5bb0 | 2006-01-26 02:24:17 +0000 | [diff] [blame] | 800 | extern PPCInstr* PPCInstr_Load ( UChar sz, |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 801 | HReg dst, PPCAMode* src, Bool mode64 ); |
sewardj | e9d8a26 | 2009-07-01 08:06:34 +0000 | [diff] [blame] | 802 | extern PPCInstr* PPCInstr_LoadL ( UChar sz, |
| 803 | HReg dst, HReg src, Bool mode64 ); |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 804 | extern PPCInstr* PPCInstr_Store ( UChar sz, PPCAMode* dst, |
| 805 | HReg src, Bool mode64 ); |
sewardj | e9d8a26 | 2009-07-01 08:06:34 +0000 | [diff] [blame] | 806 | extern PPCInstr* PPCInstr_StoreC ( UChar sz, HReg dst, HReg src, |
| 807 | Bool mode64 ); |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 808 | extern PPCInstr* PPCInstr_Set ( PPCCondCode cond, HReg dst ); |
| 809 | extern PPCInstr* PPCInstr_MfCR ( HReg dst ); |
| 810 | extern PPCInstr* PPCInstr_MFence ( void ); |
cerion | ed623db | 2005-06-20 12:42:04 +0000 | [diff] [blame] | 811 | |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 812 | extern PPCInstr* PPCInstr_FpUnary ( PPCFpOp op, HReg dst, HReg src ); |
| 813 | extern PPCInstr* PPCInstr_FpBinary ( PPCFpOp op, HReg dst, HReg srcL, HReg srcR ); |
sewardj | 40c8026 | 2006-02-08 19:30:46 +0000 | [diff] [blame] | 814 | extern PPCInstr* PPCInstr_FpMulAcc ( PPCFpOp op, HReg dst, HReg srcML, |
| 815 | HReg srcMR, HReg srcAcc ); |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 816 | extern PPCInstr* PPCInstr_FpLdSt ( Bool isLoad, UChar sz, HReg, PPCAMode* ); |
sewardj | 92923de | 2006-01-25 21:29:48 +0000 | [diff] [blame] | 817 | extern PPCInstr* PPCInstr_FpSTFIW ( HReg addr, HReg data ); |
| 818 | extern PPCInstr* PPCInstr_FpRSP ( HReg dst, HReg src ); |
sewardj | 66d5ef2 | 2011-04-15 11:55:00 +0000 | [diff] [blame] | 819 | extern PPCInstr* PPCInstr_FpCftI ( Bool fromI, Bool int32, Bool syned, |
| 820 | Bool dst64, HReg dst, HReg src ); |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 821 | extern PPCInstr* PPCInstr_FpCMov ( PPCCondCode, HReg dst, HReg src ); |
| 822 | extern PPCInstr* PPCInstr_FpLdFPSCR ( HReg src ); |
| 823 | extern PPCInstr* PPCInstr_FpCmp ( HReg dst, HReg srcL, HReg srcR ); |
cerion | bcf8c3e | 2005-02-04 16:17:07 +0000 | [diff] [blame] | 824 | |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 825 | extern PPCInstr* PPCInstr_RdWrLR ( Bool wrLR, HReg gpr ); |
cerion | 7f000af | 2005-02-22 20:36:49 +0000 | [diff] [blame] | 826 | |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 827 | extern PPCInstr* PPCInstr_AvLdSt ( Bool isLoad, UChar sz, HReg, PPCAMode* ); |
| 828 | extern PPCInstr* PPCInstr_AvUnary ( PPCAvOp op, HReg dst, HReg src ); |
| 829 | extern PPCInstr* PPCInstr_AvBinary ( PPCAvOp op, HReg dst, HReg srcL, HReg srcR ); |
| 830 | extern PPCInstr* PPCInstr_AvBin8x16 ( PPCAvOp op, HReg dst, HReg srcL, HReg srcR ); |
| 831 | extern PPCInstr* PPCInstr_AvBin16x8 ( PPCAvOp op, HReg dst, HReg srcL, HReg srcR ); |
| 832 | extern PPCInstr* PPCInstr_AvBin32x4 ( PPCAvOp op, HReg dst, HReg srcL, HReg srcR ); |
sewardj | e522d4b | 2011-04-26 21:36:09 +0000 | [diff] [blame] | 833 | extern PPCInstr* PPCInstr_AvBin32Fx4 ( PPCAvFpOp op, HReg dst, HReg srcL, HReg srcR ); |
| 834 | extern PPCInstr* PPCInstr_AvUn32Fx4 ( PPCAvFpOp op, HReg dst, HReg src ); |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 835 | extern PPCInstr* PPCInstr_AvPerm ( HReg dst, HReg srcL, HReg srcR, HReg ctl ); |
| 836 | extern PPCInstr* PPCInstr_AvSel ( HReg ctl, HReg dst, HReg srcL, HReg srcR ); |
| 837 | extern PPCInstr* PPCInstr_AvShlDbl ( UChar shift, HReg dst, HReg srcL, HReg srcR ); |
| 838 | extern PPCInstr* PPCInstr_AvSplat ( UChar sz, HReg dst, PPCVI5s* src ); |
| 839 | extern PPCInstr* PPCInstr_AvCMov ( PPCCondCode, HReg dst, HReg src ); |
| 840 | extern PPCInstr* PPCInstr_AvLdVSCR ( HReg src ); |
cerion | bcf8c3e | 2005-02-04 16:17:07 +0000 | [diff] [blame] | 841 | |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 842 | extern void ppPPCInstr ( PPCInstr*, Bool mode64 ); |
cerion | bcf8c3e | 2005-02-04 16:17:07 +0000 | [diff] [blame] | 843 | |
| 844 | /* Some functions that insulate the register allocator from details |
| 845 | of the underlying instruction set. */ |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 846 | extern void getRegUsage_PPCInstr ( HRegUsage*, PPCInstr*, Bool mode64 ); |
| 847 | extern void mapRegs_PPCInstr ( HRegRemap*, PPCInstr* , Bool mode64); |
| 848 | extern Bool isMove_PPCInstr ( PPCInstr*, HReg*, HReg* ); |
| 849 | extern Int emit_PPCInstr ( UChar* buf, Int nbuf, PPCInstr*, |
sewardj | 010ac54 | 2011-05-29 09:29:18 +0000 | [diff] [blame] | 850 | Bool mode64, |
| 851 | void* dispatch_unassisted, |
| 852 | void* dispatch_assisted ); |
sewardj | 2a0cc85 | 2010-01-02 13:23:54 +0000 | [diff] [blame] | 853 | |
| 854 | extern void genSpill_PPC ( /*OUT*/HInstr** i1, /*OUT*/HInstr** i2, |
| 855 | HReg rreg, Int offsetB, Bool mode64 ); |
| 856 | extern void genReload_PPC ( /*OUT*/HInstr** i1, /*OUT*/HInstr** i2, |
| 857 | HReg rreg, Int offsetB, Bool mode64 ); |
| 858 | |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 859 | extern void getAllocableRegs_PPC ( Int*, HReg**, Bool mode64 ); |
sewardj | dd40fdf | 2006-12-24 02:20:24 +0000 | [diff] [blame] | 860 | extern HInstrArray* iselSB_PPC ( IRSB*, VexArch, |
sewardj | aca070a | 2006-10-17 00:28:22 +0000 | [diff] [blame] | 861 | VexArchInfo*, |
sewardj | dd40fdf | 2006-12-24 02:20:24 +0000 | [diff] [blame] | 862 | VexAbiInfo* ); |
cerion | bcf8c3e | 2005-02-04 16:17:07 +0000 | [diff] [blame] | 863 | |
sewardj | cef7d3e | 2009-07-02 12:21:59 +0000 | [diff] [blame] | 864 | #endif /* ndef __VEX_HOST_PPC_DEFS_H */ |
cerion | bcf8c3e | 2005-02-04 16:17:07 +0000 | [diff] [blame] | 865 | |
| 866 | /*---------------------------------------------------------------*/ |
sewardj | cef7d3e | 2009-07-02 12:21:59 +0000 | [diff] [blame] | 867 | /*--- end host_ppc_defs.h ---*/ |
cerion | bcf8c3e | 2005-02-04 16:17:07 +0000 | [diff] [blame] | 868 | /*---------------------------------------------------------------*/ |