sewardj | a3e9830 | 2005-02-01 15:55:05 +0000 | [diff] [blame] | 1 | |
| 2 | /*---------------------------------------------------------------*/ |
| 3 | /*--- ---*/ |
| 4 | /*--- This file (host-amd64/hdefs.h) is ---*/ |
sewardj | dbcfae7 | 2005-08-02 11:14:04 +0000 | [diff] [blame] | 5 | /*--- Copyright (C) OpenWorks LLP. All rights reserved. ---*/ |
sewardj | a3e9830 | 2005-02-01 15:55:05 +0000 | [diff] [blame] | 6 | /*--- ---*/ |
| 7 | /*---------------------------------------------------------------*/ |
| 8 | |
| 9 | /* |
| 10 | This file is part of LibVEX, a library for dynamic binary |
| 11 | instrumentation and translation. |
| 12 | |
sewardj | e744153 | 2007-01-08 05:51:05 +0000 | [diff] [blame] | 13 | Copyright (C) 2004-2007 OpenWorks LLP. All rights reserved. |
sewardj | a3e9830 | 2005-02-01 15:55:05 +0000 | [diff] [blame] | 14 | |
sewardj | 7bd6ffe | 2005-08-03 16:07:36 +0000 | [diff] [blame] | 15 | This library is made available under a dual licensing scheme. |
sewardj | a3e9830 | 2005-02-01 15:55:05 +0000 | [diff] [blame] | 16 | |
sewardj | 7bd6ffe | 2005-08-03 16:07:36 +0000 | [diff] [blame] | 17 | If you link LibVEX against other code all of which is itself |
| 18 | licensed under the GNU General Public License, version 2 dated June |
| 19 | 1991 ("GPL v2"), then you may use LibVEX under the terms of the GPL |
| 20 | v2, as appearing in the file LICENSE.GPL. If the file LICENSE.GPL |
| 21 | is missing, you can obtain a copy of the GPL v2 from the Free |
| 22 | Software Foundation Inc., 51 Franklin St, Fifth Floor, Boston, MA |
| 23 | 02110-1301, USA. |
| 24 | |
| 25 | For any other uses of LibVEX, you must first obtain a commercial |
| 26 | license from OpenWorks LLP. Please contact info@open-works.co.uk |
| 27 | for information about commercial licensing. |
| 28 | |
| 29 | This software is provided by OpenWorks LLP "as is" and any express |
| 30 | or implied warranties, including, but not limited to, the implied |
| 31 | warranties of merchantability and fitness for a particular purpose |
| 32 | are disclaimed. In no event shall OpenWorks LLP be liable for any |
| 33 | direct, indirect, incidental, special, exemplary, or consequential |
| 34 | damages (including, but not limited to, procurement of substitute |
| 35 | goods or services; loss of use, data, or profits; or business |
| 36 | interruption) however caused and on any theory of liability, |
| 37 | whether in contract, strict liability, or tort (including |
| 38 | negligence or otherwise) arising in any way out of the use of this |
| 39 | software, even if advised of the possibility of such damage. |
sewardj | a3e9830 | 2005-02-01 15:55:05 +0000 | [diff] [blame] | 40 | |
| 41 | Neither the names of the U.S. Department of Energy nor the |
| 42 | University of California nor the names of its contributors may be |
| 43 | used to endorse or promote products derived from this software |
| 44 | without prior written permission. |
sewardj | a3e9830 | 2005-02-01 15:55:05 +0000 | [diff] [blame] | 45 | */ |
| 46 | |
| 47 | #ifndef __LIBVEX_HOST_AMD64_HDEFS_H |
| 48 | #define __LIBVEX_HOST_AMD64_HDEFS_H |
| 49 | |
sewardj | c33671d | 2005-02-01 20:30:00 +0000 | [diff] [blame] | 50 | |
| 51 | /* --------- Registers. --------- */ |
| 52 | |
| 53 | /* The usual HReg abstraction. There are 16 real int regs, 6 real |
| 54 | float regs, and 16 real vector regs. |
| 55 | */ |
| 56 | |
| 57 | extern void ppHRegAMD64 ( HReg ); |
| 58 | |
| 59 | extern HReg hregAMD64_RAX ( void ); |
| 60 | extern HReg hregAMD64_RBX ( void ); |
| 61 | extern HReg hregAMD64_RCX ( void ); |
| 62 | extern HReg hregAMD64_RDX ( void ); |
| 63 | extern HReg hregAMD64_RSP ( void ); |
| 64 | extern HReg hregAMD64_RBP ( void ); |
| 65 | extern HReg hregAMD64_RSI ( void ); |
| 66 | extern HReg hregAMD64_RDI ( void ); |
| 67 | extern HReg hregAMD64_R8 ( void ); |
| 68 | extern HReg hregAMD64_R9 ( void ); |
| 69 | extern HReg hregAMD64_R10 ( void ); |
| 70 | extern HReg hregAMD64_R11 ( void ); |
| 71 | extern HReg hregAMD64_R12 ( void ); |
| 72 | extern HReg hregAMD64_R13 ( void ); |
| 73 | extern HReg hregAMD64_R14 ( void ); |
| 74 | extern HReg hregAMD64_R15 ( void ); |
| 75 | |
| 76 | extern HReg hregAMD64_FAKE0 ( void ); |
| 77 | extern HReg hregAMD64_FAKE1 ( void ); |
| 78 | extern HReg hregAMD64_FAKE2 ( void ); |
| 79 | extern HReg hregAMD64_FAKE3 ( void ); |
| 80 | extern HReg hregAMD64_FAKE4 ( void ); |
| 81 | extern HReg hregAMD64_FAKE5 ( void ); |
| 82 | |
| 83 | extern HReg hregAMD64_XMM0 ( void ); |
| 84 | extern HReg hregAMD64_XMM1 ( void ); |
sewardj | 53df061 | 2005-02-04 21:15:39 +0000 | [diff] [blame] | 85 | extern HReg hregAMD64_XMM2 ( void ); |
sewardj | c33671d | 2005-02-01 20:30:00 +0000 | [diff] [blame] | 86 | extern HReg hregAMD64_XMM3 ( void ); |
| 87 | extern HReg hregAMD64_XMM4 ( void ); |
| 88 | extern HReg hregAMD64_XMM5 ( void ); |
| 89 | extern HReg hregAMD64_XMM6 ( void ); |
| 90 | extern HReg hregAMD64_XMM7 ( void ); |
| 91 | extern HReg hregAMD64_XMM8 ( void ); |
| 92 | extern HReg hregAMD64_XMM9 ( void ); |
| 93 | extern HReg hregAMD64_XMM10 ( void ); |
| 94 | extern HReg hregAMD64_XMM11 ( void ); |
| 95 | extern HReg hregAMD64_XMM12 ( void ); |
| 96 | extern HReg hregAMD64_XMM13 ( void ); |
| 97 | extern HReg hregAMD64_XMM14 ( void ); |
| 98 | extern HReg hregAMD64_XMM15 ( void ); |
| 99 | |
| 100 | |
| 101 | /* --------- Condition codes, AMD encoding. --------- */ |
| 102 | |
| 103 | typedef |
| 104 | enum { |
| 105 | Acc_O = 0, /* overflow */ |
| 106 | Acc_NO = 1, /* no overflow */ |
| 107 | |
| 108 | Acc_B = 2, /* below */ |
| 109 | Acc_NB = 3, /* not below */ |
| 110 | |
| 111 | Acc_Z = 4, /* zero */ |
| 112 | Acc_NZ = 5, /* not zero */ |
| 113 | |
| 114 | Acc_BE = 6, /* below or equal */ |
| 115 | Acc_NBE = 7, /* not below or equal */ |
| 116 | |
| 117 | Acc_S = 8, /* negative */ |
| 118 | Acc_NS = 9, /* not negative */ |
| 119 | |
| 120 | Acc_P = 10, /* parity even */ |
| 121 | Acc_NP = 11, /* not parity even */ |
| 122 | |
| 123 | Acc_L = 12, /* jump less */ |
| 124 | Acc_NL = 13, /* not less */ |
| 125 | |
| 126 | Acc_LE = 14, /* less or equal */ |
| 127 | Acc_NLE = 15, /* not less or equal */ |
| 128 | |
| 129 | Acc_ALWAYS = 16 /* the usual hack */ |
| 130 | } |
| 131 | AMD64CondCode; |
| 132 | |
| 133 | extern HChar* showAMD64CondCode ( AMD64CondCode ); |
| 134 | |
| 135 | |
| 136 | /* --------- Memory address expressions (amodes). --------- */ |
| 137 | |
| 138 | typedef |
| 139 | enum { |
| 140 | Aam_IR, /* Immediate + Reg */ |
| 141 | Aam_IRRS /* Immediate + Reg1 + (Reg2 << Shift) */ |
| 142 | } |
| 143 | AMD64AModeTag; |
| 144 | |
| 145 | typedef |
| 146 | struct { |
| 147 | AMD64AModeTag tag; |
| 148 | union { |
| 149 | struct { |
| 150 | UInt imm; |
| 151 | HReg reg; |
| 152 | } IR; |
| 153 | struct { |
| 154 | UInt imm; |
| 155 | HReg base; |
| 156 | HReg index; |
| 157 | Int shift; /* 0, 1, 2 or 3 only */ |
| 158 | } IRRS; |
| 159 | } Aam; |
| 160 | } |
| 161 | AMD64AMode; |
| 162 | |
| 163 | extern AMD64AMode* AMD64AMode_IR ( UInt, HReg ); |
| 164 | extern AMD64AMode* AMD64AMode_IRRS ( UInt, HReg, HReg, Int ); |
| 165 | |
| 166 | extern AMD64AMode* dopyAMD64AMode ( AMD64AMode* ); |
| 167 | |
| 168 | extern void ppAMD64AMode ( AMD64AMode* ); |
| 169 | |
| 170 | |
| 171 | /* --------- Operand, which can be reg, immediate or memory. --------- */ |
| 172 | |
| 173 | typedef |
| 174 | enum { |
| 175 | Armi_Imm, |
| 176 | Armi_Reg, |
| 177 | Armi_Mem |
| 178 | } |
| 179 | AMD64RMITag; |
| 180 | |
| 181 | typedef |
| 182 | struct { |
| 183 | AMD64RMITag tag; |
| 184 | union { |
| 185 | struct { |
| 186 | UInt imm32; |
| 187 | } Imm; |
| 188 | struct { |
| 189 | HReg reg; |
| 190 | } Reg; |
| 191 | struct { |
| 192 | AMD64AMode* am; |
| 193 | } Mem; |
| 194 | } |
| 195 | Armi; |
| 196 | } |
| 197 | AMD64RMI; |
| 198 | |
| 199 | extern AMD64RMI* AMD64RMI_Imm ( UInt ); |
| 200 | extern AMD64RMI* AMD64RMI_Reg ( HReg ); |
| 201 | extern AMD64RMI* AMD64RMI_Mem ( AMD64AMode* ); |
| 202 | |
| 203 | extern void ppAMD64RMI ( AMD64RMI* ); |
| 204 | |
| 205 | |
| 206 | /* --------- Operand, which can be reg or immediate only. --------- */ |
| 207 | |
| 208 | typedef |
| 209 | enum { |
| 210 | Ari_Imm, |
| 211 | Ari_Reg |
| 212 | } |
| 213 | AMD64RITag; |
| 214 | |
| 215 | typedef |
| 216 | struct { |
| 217 | AMD64RITag tag; |
| 218 | union { |
| 219 | struct { |
| 220 | UInt imm32; |
| 221 | } Imm; |
| 222 | struct { |
| 223 | HReg reg; |
| 224 | } Reg; |
| 225 | } |
| 226 | Ari; |
| 227 | } |
| 228 | AMD64RI; |
| 229 | |
| 230 | extern AMD64RI* AMD64RI_Imm ( UInt ); |
| 231 | extern AMD64RI* AMD64RI_Reg ( HReg ); |
| 232 | |
| 233 | extern void ppAMD64RI ( AMD64RI* ); |
| 234 | |
| 235 | |
| 236 | /* --------- Operand, which can be reg or memory only. --------- */ |
| 237 | |
| 238 | typedef |
| 239 | enum { |
| 240 | Arm_Reg, |
| 241 | Arm_Mem |
| 242 | } |
| 243 | AMD64RMTag; |
| 244 | |
| 245 | typedef |
| 246 | struct { |
| 247 | AMD64RMTag tag; |
| 248 | union { |
| 249 | struct { |
| 250 | HReg reg; |
| 251 | } Reg; |
| 252 | struct { |
| 253 | AMD64AMode* am; |
| 254 | } Mem; |
| 255 | } |
| 256 | Arm; |
| 257 | } |
| 258 | AMD64RM; |
| 259 | |
| 260 | extern AMD64RM* AMD64RM_Reg ( HReg ); |
| 261 | extern AMD64RM* AMD64RM_Mem ( AMD64AMode* ); |
| 262 | |
| 263 | extern void ppAMD64RM ( AMD64RM* ); |
| 264 | |
| 265 | |
sewardj | d0a12df | 2005-02-10 02:07:43 +0000 | [diff] [blame] | 266 | /* --------- Instructions. --------- */ |
| 267 | |
| 268 | /* --------- */ |
| 269 | typedef |
| 270 | enum { |
| 271 | Aun_NEG, |
| 272 | Aun_NOT |
| 273 | } |
| 274 | AMD64UnaryOp; |
| 275 | |
| 276 | extern HChar* showAMD64UnaryOp ( AMD64UnaryOp ); |
sewardj | 614b3fb | 2005-02-02 02:16:03 +0000 | [diff] [blame] | 277 | |
| 278 | |
| 279 | /* --------- */ |
| 280 | typedef |
| 281 | enum { |
| 282 | Aalu_INVALID, |
| 283 | Aalu_MOV, |
| 284 | Aalu_CMP, |
| 285 | Aalu_ADD, Aalu_SUB, Aalu_ADC, Aalu_SBB, |
| 286 | Aalu_AND, Aalu_OR, Aalu_XOR, |
| 287 | Aalu_MUL |
| 288 | } |
| 289 | AMD64AluOp; |
| 290 | |
| 291 | extern HChar* showAMD64AluOp ( AMD64AluOp ); |
| 292 | |
| 293 | |
sewardj | 8258a8c | 2005-02-02 03:11:24 +0000 | [diff] [blame] | 294 | /* --------- */ |
| 295 | typedef |
| 296 | enum { |
| 297 | Ash_INVALID, |
| 298 | Ash_SHL, Ash_SHR, Ash_SAR |
| 299 | } |
| 300 | AMD64ShiftOp; |
| 301 | |
| 302 | extern HChar* showAMD64ShiftOp ( AMD64ShiftOp ); |
| 303 | |
| 304 | |
sewardj | 25a8581 | 2005-05-08 23:03:48 +0000 | [diff] [blame] | 305 | /* --------- */ |
| 306 | typedef |
| 307 | enum { |
| 308 | Afp_INVALID, |
| 309 | /* Binary */ |
sewardj | f4c803b | 2006-09-11 11:07:34 +0000 | [diff] [blame] | 310 | Afp_SCALE, Afp_ATAN, Afp_YL2X, Afp_YL2XP1, Afp_PREM, |
sewardj | 25a8581 | 2005-05-08 23:03:48 +0000 | [diff] [blame] | 311 | /* Unary */ |
sewardj | 4796d66 | 2006-02-05 16:06:26 +0000 | [diff] [blame] | 312 | Afp_SQRT, |
sewardj | 5e20537 | 2005-05-09 02:57:08 +0000 | [diff] [blame] | 313 | Afp_SIN, Afp_COS, Afp_TAN, |
sewardj | 25a8581 | 2005-05-08 23:03:48 +0000 | [diff] [blame] | 314 | Afp_ROUND, Afp_2XM1 |
| 315 | } |
| 316 | A87FpOp; |
| 317 | |
| 318 | extern HChar* showA87FpOp ( A87FpOp ); |
sewardj | 1001dc4 | 2005-02-21 08:25:55 +0000 | [diff] [blame] | 319 | |
| 320 | |
| 321 | /* --------- */ |
| 322 | typedef |
| 323 | enum { |
| 324 | Asse_INVALID, |
| 325 | /* mov */ |
| 326 | Asse_MOV, |
| 327 | /* Floating point binary */ |
| 328 | Asse_ADDF, Asse_SUBF, Asse_MULF, Asse_DIVF, |
sewardj | 1a01e65 | 2005-02-23 11:39:21 +0000 | [diff] [blame] | 329 | Asse_MAXF, Asse_MINF, |
sewardj | 8d96531 | 2005-02-25 02:48:47 +0000 | [diff] [blame] | 330 | Asse_CMPEQF, Asse_CMPLTF, Asse_CMPLEF, Asse_CMPUNF, |
sewardj | 1001dc4 | 2005-02-21 08:25:55 +0000 | [diff] [blame] | 331 | /* Floating point unary */ |
| 332 | Asse_RCPF, Asse_RSQRTF, Asse_SQRTF, |
| 333 | /* Bitwise */ |
| 334 | Asse_AND, Asse_OR, Asse_XOR, Asse_ANDN, |
sewardj | 9762859 | 2005-05-10 22:42:54 +0000 | [diff] [blame] | 335 | Asse_ADD8, Asse_ADD16, Asse_ADD32, Asse_ADD64, |
sewardj | 5992bd0 | 2005-05-11 02:13:42 +0000 | [diff] [blame] | 336 | Asse_QADD8U, Asse_QADD16U, |
| 337 | Asse_QADD8S, Asse_QADD16S, |
sewardj | 9762859 | 2005-05-10 22:42:54 +0000 | [diff] [blame] | 338 | Asse_SUB8, Asse_SUB16, Asse_SUB32, Asse_SUB64, |
| 339 | Asse_QSUB8U, Asse_QSUB16U, |
| 340 | Asse_QSUB8S, Asse_QSUB16S, |
sewardj | adffcef | 2005-05-11 00:03:06 +0000 | [diff] [blame] | 341 | Asse_MUL16, |
| 342 | Asse_MULHI16U, |
| 343 | Asse_MULHI16S, |
sewardj | 5992bd0 | 2005-05-11 02:13:42 +0000 | [diff] [blame] | 344 | Asse_AVG8U, Asse_AVG16U, |
sewardj | adffcef | 2005-05-11 00:03:06 +0000 | [diff] [blame] | 345 | Asse_MAX16S, |
| 346 | Asse_MAX8U, |
| 347 | Asse_MIN16S, |
| 348 | Asse_MIN8U, |
sewardj | 5992bd0 | 2005-05-11 02:13:42 +0000 | [diff] [blame] | 349 | Asse_CMPEQ8, Asse_CMPEQ16, Asse_CMPEQ32, |
| 350 | Asse_CMPGT8S, Asse_CMPGT16S, Asse_CMPGT32S, |
sewardj | adffcef | 2005-05-11 00:03:06 +0000 | [diff] [blame] | 351 | Asse_SHL16, Asse_SHL32, Asse_SHL64, |
| 352 | Asse_SHR16, Asse_SHR32, Asse_SHR64, |
| 353 | Asse_SAR16, Asse_SAR32, |
sewardj | 9762859 | 2005-05-10 22:42:54 +0000 | [diff] [blame] | 354 | Asse_PACKSSD, Asse_PACKSSW, Asse_PACKUSW, |
| 355 | Asse_UNPCKHB, Asse_UNPCKHW, Asse_UNPCKHD, Asse_UNPCKHQ, |
| 356 | Asse_UNPCKLB, Asse_UNPCKLW, Asse_UNPCKLD, Asse_UNPCKLQ |
sewardj | 1001dc4 | 2005-02-21 08:25:55 +0000 | [diff] [blame] | 357 | } |
| 358 | AMD64SseOp; |
| 359 | |
| 360 | extern HChar* showAMD64SseOp ( AMD64SseOp ); |
sewardj | c33671d | 2005-02-01 20:30:00 +0000 | [diff] [blame] | 361 | |
| 362 | |
| 363 | /* --------- */ |
| 364 | typedef |
| 365 | enum { |
sewardj | 25a8581 | 2005-05-08 23:03:48 +0000 | [diff] [blame] | 366 | Ain_Imm64, /* Generate 64-bit literal to register */ |
| 367 | Ain_Alu64R, /* 64-bit mov/arith/logical, dst=REG */ |
| 368 | Ain_Alu64M, /* 64-bit mov/arith/logical, dst=MEM */ |
| 369 | Ain_Sh64, /* 64-bit shift/rotate, dst=REG or MEM */ |
| 370 | Ain_Test64, /* 64-bit test (AND, set flags, discard result) */ |
| 371 | Ain_Unary64, /* 64-bit not and neg */ |
sewardj | 6ce1a23 | 2007-03-31 19:12:38 +0000 | [diff] [blame^] | 372 | Ain_Lea64, /* 64-bit compute EA into a reg */ |
sewardj | 25a8581 | 2005-05-08 23:03:48 +0000 | [diff] [blame] | 373 | Ain_MulL, /* widening multiply */ |
| 374 | Ain_Div, /* div and mod */ |
sewardj | a3e9830 | 2005-02-01 15:55:05 +0000 | [diff] [blame] | 375 | //.. Xin_Sh3232, /* shldl or shrdl */ |
sewardj | 25a8581 | 2005-05-08 23:03:48 +0000 | [diff] [blame] | 376 | Ain_Push, /* push 64-bit value on stack */ |
| 377 | Ain_Call, /* call to address in register */ |
| 378 | Ain_Goto, /* conditional/unconditional jmp to dst */ |
| 379 | Ain_CMov64, /* conditional move */ |
| 380 | Ain_MovZLQ, /* reg-reg move, zeroing out top half */ |
| 381 | Ain_LoadEX, /* mov{s,z}{b,w,l}q from mem to reg */ |
| 382 | Ain_Store, /* store 32/16/8 bit value in memory */ |
| 383 | Ain_Set64, /* convert condition code to 64-bit value */ |
| 384 | Ain_Bsfr64, /* 64-bit bsf/bsr */ |
| 385 | Ain_MFence, /* mem fence */ |
| 386 | Ain_A87Free, /* free up x87 registers */ |
| 387 | Ain_A87PushPop, /* x87 loads/stores */ |
| 388 | Ain_A87FpOp, /* x87 operations */ |
| 389 | Ain_A87LdCW, /* load x87 control word */ |
sewardj | f4c803b | 2006-09-11 11:07:34 +0000 | [diff] [blame] | 390 | Ain_A87StSW, /* store x87 status word */ |
sewardj | a3e9830 | 2005-02-01 15:55:05 +0000 | [diff] [blame] | 391 | //.. |
| 392 | //.. Xin_FpUnary, /* FP fake unary op */ |
| 393 | //.. Xin_FpBinary, /* FP fake binary op */ |
| 394 | //.. Xin_FpLdSt, /* FP fake load/store */ |
| 395 | //.. Xin_FpLdStI, /* FP fake load/store, converting to/from Int */ |
| 396 | //.. Xin_Fp64to32, /* FP round IEEE754 double to IEEE754 single */ |
| 397 | //.. Xin_FpCMov, /* FP fake floating point conditional move */ |
sewardj | 25a8581 | 2005-05-08 23:03:48 +0000 | [diff] [blame] | 398 | Ain_LdMXCSR, /* load %mxcsr */ |
sewardj | a3e9830 | 2005-02-01 15:55:05 +0000 | [diff] [blame] | 399 | //.. Xin_FpStSW_AX, /* fstsw %ax */ |
sewardj | 25a8581 | 2005-05-08 23:03:48 +0000 | [diff] [blame] | 400 | Ain_SseUComIS, /* ucomisd/ucomiss, then get %rflags into int |
| 401 | register */ |
| 402 | Ain_SseSI2SF, /* scalar 32/64 int to 32/64 float conversion */ |
| 403 | Ain_SseSF2SI, /* scalar 32/64 float to 32/64 int conversion */ |
| 404 | Ain_SseSDSS, /* scalar float32 to/from float64 */ |
sewardj | a3e9830 | 2005-02-01 15:55:05 +0000 | [diff] [blame] | 405 | //.. |
| 406 | //.. Xin_SseConst, /* Generate restricted SSE literal */ |
sewardj | 25a8581 | 2005-05-08 23:03:48 +0000 | [diff] [blame] | 407 | Ain_SseLdSt, /* SSE load/store 32/64/128 bits, no alignment |
| 408 | constraints, upper 96/64/0 bits arbitrary */ |
| 409 | Ain_SseLdzLO, /* SSE load low 32/64 bits, zero remainder of reg */ |
| 410 | Ain_Sse32Fx4, /* SSE binary, 32Fx4 */ |
| 411 | Ain_Sse32FLo, /* SSE binary, 32F in lowest lane only */ |
| 412 | Ain_Sse64Fx2, /* SSE binary, 64Fx2 */ |
| 413 | Ain_Sse64FLo, /* SSE binary, 64F in lowest lane only */ |
| 414 | Ain_SseReRg, /* SSE binary general reg-reg, Re, Rg */ |
| 415 | Ain_SseCMov, /* SSE conditional move */ |
| 416 | Ain_SseShuf /* SSE2 shuffle (pshufd) */ |
sewardj | c33671d | 2005-02-01 20:30:00 +0000 | [diff] [blame] | 417 | } |
| 418 | AMD64InstrTag; |
| 419 | |
| 420 | /* Destinations are on the RIGHT (second operand) */ |
| 421 | |
| 422 | typedef |
| 423 | struct { |
| 424 | AMD64InstrTag tag; |
sewardj | 614b3fb | 2005-02-02 02:16:03 +0000 | [diff] [blame] | 425 | union { |
| 426 | struct { |
sewardj | 53df061 | 2005-02-04 21:15:39 +0000 | [diff] [blame] | 427 | ULong imm64; |
| 428 | HReg dst; |
| 429 | } Imm64; |
| 430 | struct { |
sewardj | 614b3fb | 2005-02-02 02:16:03 +0000 | [diff] [blame] | 431 | AMD64AluOp op; |
| 432 | AMD64RMI* src; |
| 433 | HReg dst; |
| 434 | } Alu64R; |
| 435 | struct { |
| 436 | AMD64AluOp op; |
| 437 | AMD64RI* src; |
| 438 | AMD64AMode* dst; |
| 439 | } Alu64M; |
sewardj | 8258a8c | 2005-02-02 03:11:24 +0000 | [diff] [blame] | 440 | struct { |
| 441 | AMD64ShiftOp op; |
| 442 | UInt src; /* shift amount, or 0 means %cl */ |
sewardj | 501a339 | 2005-05-11 15:37:50 +0000 | [diff] [blame] | 443 | HReg dst; |
sewardj | 8258a8c | 2005-02-02 03:11:24 +0000 | [diff] [blame] | 444 | } Sh64; |
sewardj | 05b3b6a | 2005-02-04 01:44:33 +0000 | [diff] [blame] | 445 | struct { |
sewardj | 501a339 | 2005-05-11 15:37:50 +0000 | [diff] [blame] | 446 | UInt imm32; |
| 447 | HReg dst; |
sewardj | 05b3b6a | 2005-02-04 01:44:33 +0000 | [diff] [blame] | 448 | } Test64; |
sewardj | d0a12df | 2005-02-10 02:07:43 +0000 | [diff] [blame] | 449 | /* Not and Neg */ |
| 450 | struct { |
| 451 | AMD64UnaryOp op; |
sewardj | 501a339 | 2005-05-11 15:37:50 +0000 | [diff] [blame] | 452 | HReg dst; |
sewardj | d0a12df | 2005-02-10 02:07:43 +0000 | [diff] [blame] | 453 | } Unary64; |
sewardj | 6ce1a23 | 2007-03-31 19:12:38 +0000 | [diff] [blame^] | 454 | /* 64-bit compute EA into a reg */ |
| 455 | struct { |
| 456 | AMD64AMode* am; |
| 457 | HReg dst; |
| 458 | } Lea64; |
sewardj | 501a339 | 2005-05-11 15:37:50 +0000 | [diff] [blame] | 459 | /* 64 x 64 -> 128 bit widening multiply: RDX:RAX = RAX *s/u |
| 460 | r/m64 */ |
sewardj | 9b96767 | 2005-02-08 11:13:09 +0000 | [diff] [blame] | 461 | struct { |
| 462 | Bool syned; |
sewardj | 9b96767 | 2005-02-08 11:13:09 +0000 | [diff] [blame] | 463 | AMD64RM* src; |
| 464 | } MulL; |
sewardj | 7de0d3c | 2005-02-13 02:26:41 +0000 | [diff] [blame] | 465 | /* amd64 div/idiv instruction. Modifies RDX and RAX and |
| 466 | reads src. */ |
| 467 | struct { |
| 468 | Bool syned; |
| 469 | Int sz; /* 4 or 8 only */ |
| 470 | AMD64RM* src; |
| 471 | } Div; |
sewardj | a3e9830 | 2005-02-01 15:55:05 +0000 | [diff] [blame] | 472 | //.. /* shld/shrd. op may only be Xsh_SHL or Xsh_SHR */ |
| 473 | //.. struct { |
| 474 | //.. X86ShiftOp op; |
| 475 | //.. UInt amt; /* shift amount, or 0 means %cl */ |
| 476 | //.. HReg src; |
| 477 | //.. HReg dst; |
| 478 | //.. } Sh3232; |
sewardj | 1001dc4 | 2005-02-21 08:25:55 +0000 | [diff] [blame] | 479 | struct { |
| 480 | AMD64RMI* src; |
| 481 | } Push; |
sewardj | 05b3b6a | 2005-02-04 01:44:33 +0000 | [diff] [blame] | 482 | /* Pseudo-insn. Call target (an absolute address), on given |
| 483 | condition (which could be Xcc_ALWAYS). */ |
| 484 | struct { |
| 485 | AMD64CondCode cond; |
| 486 | Addr64 target; |
| 487 | Int regparms; /* 0 .. 6 */ |
| 488 | } Call; |
sewardj | f67eadf | 2005-02-03 03:53:52 +0000 | [diff] [blame] | 489 | /* Pseudo-insn. Goto dst, on given condition (which could be |
| 490 | Acc_ALWAYS). */ |
| 491 | struct { |
| 492 | IRJumpKind jk; |
| 493 | AMD64CondCode cond; |
| 494 | AMD64RI* dst; |
| 495 | } Goto; |
sewardj | 05b3b6a | 2005-02-04 01:44:33 +0000 | [diff] [blame] | 496 | /* Mov src to dst on the given condition, which may not |
| 497 | be the bogus Acc_ALWAYS. */ |
| 498 | struct { |
| 499 | AMD64CondCode cond; |
| 500 | AMD64RM* src; |
| 501 | HReg dst; |
| 502 | } CMov64; |
sewardj | f67eadf | 2005-02-03 03:53:52 +0000 | [diff] [blame] | 503 | /* reg-reg move, zeroing out top half */ |
| 504 | struct { |
| 505 | HReg src; |
| 506 | HReg dst; |
| 507 | } MovZLQ; |
sewardj | 8258a8c | 2005-02-02 03:11:24 +0000 | [diff] [blame] | 508 | /* Sign/Zero extending loads. Dst size is always 64 bits. */ |
| 509 | struct { |
sewardj | 1830386 | 2005-02-21 12:36:54 +0000 | [diff] [blame] | 510 | UChar szSmall; /* only 1, 2 or 4 */ |
sewardj | 8258a8c | 2005-02-02 03:11:24 +0000 | [diff] [blame] | 511 | Bool syned; |
| 512 | AMD64AMode* src; |
| 513 | HReg dst; |
| 514 | } LoadEX; |
sewardj | f67eadf | 2005-02-03 03:53:52 +0000 | [diff] [blame] | 515 | /* 32/16/8 bit stores. */ |
| 516 | struct { |
| 517 | UChar sz; /* only 1, 2 or 4 */ |
| 518 | HReg src; |
| 519 | AMD64AMode* dst; |
| 520 | } Store; |
sewardj | a5bd0af | 2005-03-24 20:40:12 +0000 | [diff] [blame] | 521 | /* Convert an amd64 condition code to a 64-bit value (0 or 1). */ |
| 522 | struct { |
| 523 | AMD64CondCode cond; |
| 524 | HReg dst; |
| 525 | } Set64; |
sewardj | f53b735 | 2005-04-06 20:01:56 +0000 | [diff] [blame] | 526 | /* 64-bit bsf or bsr. */ |
| 527 | struct { |
| 528 | Bool isFwds; |
| 529 | HReg src; |
| 530 | HReg dst; |
| 531 | } Bsfr64; |
sewardj | d0a12df | 2005-02-10 02:07:43 +0000 | [diff] [blame] | 532 | /* Mem fence. In short, an insn which flushes all preceding |
| 533 | loads and stores as much as possible before continuing. |
| 534 | On AMD64 we emit a real "mfence". */ |
| 535 | struct { |
| 536 | } MFence; |
| 537 | |
sewardj | 25a8581 | 2005-05-08 23:03:48 +0000 | [diff] [blame] | 538 | /* --- X87 --- */ |
| 539 | |
| 540 | /* A very minimal set of x87 insns, that operate exactly in a |
| 541 | stack-like way so no need to think about x87 registers. */ |
| 542 | |
| 543 | /* Do 'ffree' on %st(7) .. %st(7-nregs) */ |
| 544 | struct { |
| 545 | Int nregs; /* 1 <= nregs <= 7 */ |
| 546 | } A87Free; |
| 547 | |
| 548 | /* Push a 64-bit FP value from memory onto the stack, or move |
| 549 | a value from the stack to memory and remove it from the |
| 550 | stack. */ |
| 551 | struct { |
| 552 | AMD64AMode* addr; |
| 553 | Bool isPush; |
| 554 | } A87PushPop; |
| 555 | |
| 556 | /* Do an operation on the top-of-stack. This can be unary, in |
| 557 | which case it is %st0 = OP( %st0 ), or binary: %st0 = OP( |
| 558 | %st0, %st1 ). */ |
| 559 | struct { |
| 560 | A87FpOp op; |
| 561 | } A87FpOp; |
| 562 | |
| 563 | /* Load the FPU control word. */ |
| 564 | struct { |
| 565 | AMD64AMode* addr; |
| 566 | } A87LdCW; |
| 567 | |
sewardj | f4c803b | 2006-09-11 11:07:34 +0000 | [diff] [blame] | 568 | /* Store the FPU status word (fstsw m16) */ |
| 569 | struct { |
| 570 | AMD64AMode* addr; |
| 571 | } A87StSW; |
| 572 | |
sewardj | 25a8581 | 2005-05-08 23:03:48 +0000 | [diff] [blame] | 573 | /* --- SSE --- */ |
| 574 | |
sewardj | 1a01e65 | 2005-02-23 11:39:21 +0000 | [diff] [blame] | 575 | /* Load 32 bits into %mxcsr. */ |
| 576 | struct { |
| 577 | AMD64AMode* addr; |
| 578 | } |
| 579 | LdMXCSR; |
sewardj | a3e9830 | 2005-02-01 15:55:05 +0000 | [diff] [blame] | 580 | //.. /* fstsw %ax */ |
| 581 | //.. struct { |
| 582 | //.. /* no fields */ |
| 583 | //.. } |
| 584 | //.. FpStSW_AX; |
sewardj | 1830386 | 2005-02-21 12:36:54 +0000 | [diff] [blame] | 585 | /* ucomisd/ucomiss, then get %rflags into int register */ |
| 586 | struct { |
| 587 | UChar sz; /* 4 or 8 only */ |
| 588 | HReg srcL; /* xmm */ |
| 589 | HReg srcR; /* xmm */ |
| 590 | HReg dst; /* int */ |
| 591 | } SseUComIS; |
sewardj | 1a01e65 | 2005-02-23 11:39:21 +0000 | [diff] [blame] | 592 | /* scalar 32/64 int to 32/64 float conversion */ |
| 593 | struct { |
| 594 | UChar szS; /* 4 or 8 */ |
| 595 | UChar szD; /* 4 or 8 */ |
| 596 | HReg src; /* i class */ |
| 597 | HReg dst; /* v class */ |
| 598 | } SseSI2SF; |
| 599 | /* scalar 32/64 float to 32/64 int conversion */ |
| 600 | struct { |
| 601 | UChar szS; /* 4 or 8 */ |
| 602 | UChar szD; /* 4 or 8 */ |
| 603 | HReg src; /* v class */ |
| 604 | HReg dst; /* i class */ |
| 605 | } SseSF2SI; |
sewardj | 8d96531 | 2005-02-25 02:48:47 +0000 | [diff] [blame] | 606 | /* scalar float32 to/from float64 */ |
| 607 | struct { |
| 608 | Bool from64; /* True: 64->32; False: 32->64 */ |
| 609 | HReg src; |
| 610 | HReg dst; |
| 611 | } SseSDSS; |
sewardj | a3e9830 | 2005-02-01 15:55:05 +0000 | [diff] [blame] | 612 | //.. |
| 613 | //.. /* Simplistic SSE[123] */ |
| 614 | //.. struct { |
| 615 | //.. UShort con; |
| 616 | //.. HReg dst; |
| 617 | //.. } SseConst; |
sewardj | 1001dc4 | 2005-02-21 08:25:55 +0000 | [diff] [blame] | 618 | struct { |
| 619 | Bool isLoad; |
sewardj | 1830386 | 2005-02-21 12:36:54 +0000 | [diff] [blame] | 620 | UChar sz; /* 4, 8 or 16 only */ |
sewardj | 1001dc4 | 2005-02-21 08:25:55 +0000 | [diff] [blame] | 621 | HReg reg; |
| 622 | AMD64AMode* addr; |
| 623 | } SseLdSt; |
| 624 | struct { |
| 625 | Int sz; /* 4 or 8 only */ |
| 626 | HReg reg; |
| 627 | AMD64AMode* addr; |
| 628 | } SseLdzLO; |
sewardj | 8d96531 | 2005-02-25 02:48:47 +0000 | [diff] [blame] | 629 | struct { |
| 630 | AMD64SseOp op; |
| 631 | HReg src; |
| 632 | HReg dst; |
| 633 | } Sse32Fx4; |
| 634 | struct { |
| 635 | AMD64SseOp op; |
| 636 | HReg src; |
| 637 | HReg dst; |
| 638 | } Sse32FLo; |
sewardj | 4c328cf | 2005-05-05 12:05:54 +0000 | [diff] [blame] | 639 | struct { |
| 640 | AMD64SseOp op; |
| 641 | HReg src; |
| 642 | HReg dst; |
| 643 | } Sse64Fx2; |
sewardj | 1001dc4 | 2005-02-21 08:25:55 +0000 | [diff] [blame] | 644 | struct { |
| 645 | AMD64SseOp op; |
| 646 | HReg src; |
| 647 | HReg dst; |
| 648 | } Sse64FLo; |
| 649 | struct { |
| 650 | AMD64SseOp op; |
| 651 | HReg src; |
| 652 | HReg dst; |
| 653 | } SseReRg; |
sewardj | 8d96531 | 2005-02-25 02:48:47 +0000 | [diff] [blame] | 654 | /* Mov src to dst on the given condition, which may not |
| 655 | be the bogus Xcc_ALWAYS. */ |
| 656 | struct { |
| 657 | AMD64CondCode cond; |
| 658 | HReg src; |
| 659 | HReg dst; |
| 660 | } SseCMov; |
sewardj | 0971734 | 2005-05-05 21:34:02 +0000 | [diff] [blame] | 661 | struct { |
| 662 | Int order; /* 0 <= order <= 0xFF */ |
| 663 | HReg src; |
| 664 | HReg dst; |
| 665 | } SseShuf; |
sewardj | 614b3fb | 2005-02-02 02:16:03 +0000 | [diff] [blame] | 666 | |
| 667 | } Ain; |
sewardj | c33671d | 2005-02-01 20:30:00 +0000 | [diff] [blame] | 668 | } |
| 669 | AMD64Instr; |
| 670 | |
sewardj | 25a8581 | 2005-05-08 23:03:48 +0000 | [diff] [blame] | 671 | extern AMD64Instr* AMD64Instr_Imm64 ( ULong imm64, HReg dst ); |
| 672 | extern AMD64Instr* AMD64Instr_Alu64R ( AMD64AluOp, AMD64RMI*, HReg ); |
| 673 | extern AMD64Instr* AMD64Instr_Alu64M ( AMD64AluOp, AMD64RI*, AMD64AMode* ); |
sewardj | 501a339 | 2005-05-11 15:37:50 +0000 | [diff] [blame] | 674 | extern AMD64Instr* AMD64Instr_Unary64 ( AMD64UnaryOp op, HReg dst ); |
sewardj | 6ce1a23 | 2007-03-31 19:12:38 +0000 | [diff] [blame^] | 675 | extern AMD64Instr* AMD64Instr_Lea64 ( AMD64AMode* am, HReg dst ); |
sewardj | 501a339 | 2005-05-11 15:37:50 +0000 | [diff] [blame] | 676 | extern AMD64Instr* AMD64Instr_Sh64 ( AMD64ShiftOp, UInt, HReg ); |
| 677 | extern AMD64Instr* AMD64Instr_Test64 ( UInt imm32, HReg dst ); |
| 678 | extern AMD64Instr* AMD64Instr_MulL ( Bool syned, AMD64RM* ); |
sewardj | 25a8581 | 2005-05-08 23:03:48 +0000 | [diff] [blame] | 679 | extern AMD64Instr* AMD64Instr_Div ( Bool syned, Int sz, AMD64RM* ); |
sewardj | 614b3fb | 2005-02-02 02:16:03 +0000 | [diff] [blame] | 680 | //.. extern AMD64Instr* AMD64Instr_Sh3232 ( AMD64ShiftOp, UInt amt, HReg src, HReg dst ); |
sewardj | 25a8581 | 2005-05-08 23:03:48 +0000 | [diff] [blame] | 681 | extern AMD64Instr* AMD64Instr_Push ( AMD64RMI* ); |
| 682 | extern AMD64Instr* AMD64Instr_Call ( AMD64CondCode, Addr64, Int ); |
| 683 | extern AMD64Instr* AMD64Instr_Goto ( IRJumpKind, AMD64CondCode cond, AMD64RI* dst ); |
| 684 | extern AMD64Instr* AMD64Instr_CMov64 ( AMD64CondCode, AMD64RM* src, HReg dst ); |
| 685 | extern AMD64Instr* AMD64Instr_MovZLQ ( HReg src, HReg dst ); |
| 686 | extern AMD64Instr* AMD64Instr_LoadEX ( UChar szSmall, Bool syned, |
| 687 | AMD64AMode* src, HReg dst ); |
| 688 | extern AMD64Instr* AMD64Instr_Store ( UChar sz, HReg src, AMD64AMode* dst ); |
| 689 | extern AMD64Instr* AMD64Instr_Set64 ( AMD64CondCode cond, HReg dst ); |
| 690 | extern AMD64Instr* AMD64Instr_Bsfr64 ( Bool isFwds, HReg src, HReg dst ); |
| 691 | extern AMD64Instr* AMD64Instr_MFence ( void ); |
| 692 | extern AMD64Instr* AMD64Instr_A87Free ( Int nregs ); |
| 693 | extern AMD64Instr* AMD64Instr_A87PushPop ( AMD64AMode* addr, Bool isPush ); |
| 694 | extern AMD64Instr* AMD64Instr_A87FpOp ( A87FpOp op ); |
| 695 | extern AMD64Instr* AMD64Instr_A87LdCW ( AMD64AMode* addr ); |
sewardj | f4c803b | 2006-09-11 11:07:34 +0000 | [diff] [blame] | 696 | extern AMD64Instr* AMD64Instr_A87StSW ( AMD64AMode* addr ); |
sewardj | a3e9830 | 2005-02-01 15:55:05 +0000 | [diff] [blame] | 697 | //.. |
sewardj | 614b3fb | 2005-02-02 02:16:03 +0000 | [diff] [blame] | 698 | //.. extern AMD64Instr* AMD64Instr_FpUnary ( AMD64FpOp op, HReg src, HReg dst ); |
| 699 | //.. extern AMD64Instr* AMD64Instr_FpBinary ( AMD64FpOp op, HReg srcL, HReg srcR, HReg dst ); |
| 700 | //.. extern AMD64Instr* AMD64Instr_FpLdSt ( Bool isLoad, UChar sz, HReg reg, AMD64AMode* ); |
| 701 | //.. extern AMD64Instr* AMD64Instr_FpLdStI ( Bool isLoad, UChar sz, HReg reg, AMD64AMode* ); |
| 702 | //.. extern AMD64Instr* AMD64Instr_Fp64to32 ( HReg src, HReg dst ); |
| 703 | //.. extern AMD64Instr* AMD64Instr_FpCMov ( AMD64CondCode, HReg src, HReg dst ); |
sewardj | 25a8581 | 2005-05-08 23:03:48 +0000 | [diff] [blame] | 704 | extern AMD64Instr* AMD64Instr_LdMXCSR ( AMD64AMode* ); |
sewardj | 614b3fb | 2005-02-02 02:16:03 +0000 | [diff] [blame] | 705 | //.. extern AMD64Instr* AMD64Instr_FpStSW_AX ( void ); |
sewardj | 25a8581 | 2005-05-08 23:03:48 +0000 | [diff] [blame] | 706 | extern AMD64Instr* AMD64Instr_SseUComIS ( Int sz, HReg srcL, HReg srcR, HReg dst ); |
| 707 | extern AMD64Instr* AMD64Instr_SseSI2SF ( Int szS, Int szD, HReg src, HReg dst ); |
| 708 | extern AMD64Instr* AMD64Instr_SseSF2SI ( Int szS, Int szD, HReg src, HReg dst ); |
| 709 | extern AMD64Instr* AMD64Instr_SseSDSS ( Bool from64, HReg src, HReg dst ); |
sewardj | a3e9830 | 2005-02-01 15:55:05 +0000 | [diff] [blame] | 710 | //.. |
sewardj | 614b3fb | 2005-02-02 02:16:03 +0000 | [diff] [blame] | 711 | //.. extern AMD64Instr* AMD64Instr_SseConst ( UShort con, HReg dst ); |
sewardj | 25a8581 | 2005-05-08 23:03:48 +0000 | [diff] [blame] | 712 | extern AMD64Instr* AMD64Instr_SseLdSt ( Bool isLoad, Int sz, HReg, AMD64AMode* ); |
| 713 | extern AMD64Instr* AMD64Instr_SseLdzLO ( Int sz, HReg, AMD64AMode* ); |
| 714 | extern AMD64Instr* AMD64Instr_Sse32Fx4 ( AMD64SseOp, HReg, HReg ); |
| 715 | extern AMD64Instr* AMD64Instr_Sse32FLo ( AMD64SseOp, HReg, HReg ); |
| 716 | extern AMD64Instr* AMD64Instr_Sse64Fx2 ( AMD64SseOp, HReg, HReg ); |
| 717 | extern AMD64Instr* AMD64Instr_Sse64FLo ( AMD64SseOp, HReg, HReg ); |
| 718 | extern AMD64Instr* AMD64Instr_SseReRg ( AMD64SseOp, HReg, HReg ); |
| 719 | extern AMD64Instr* AMD64Instr_SseCMov ( AMD64CondCode, HReg src, HReg dst ); |
| 720 | extern AMD64Instr* AMD64Instr_SseShuf ( Int order, HReg src, HReg dst ); |
sewardj | c33671d | 2005-02-01 20:30:00 +0000 | [diff] [blame] | 721 | |
| 722 | |
cerion | 92b6436 | 2005-12-13 12:02:26 +0000 | [diff] [blame] | 723 | extern void ppAMD64Instr ( AMD64Instr*, Bool ); |
sewardj | c33671d | 2005-02-01 20:30:00 +0000 | [diff] [blame] | 724 | |
| 725 | /* Some functions that insulate the register allocator from details |
| 726 | of the underlying instruction set. */ |
cerion | 92b6436 | 2005-12-13 12:02:26 +0000 | [diff] [blame] | 727 | extern void getRegUsage_AMD64Instr ( HRegUsage*, AMD64Instr*, Bool ); |
| 728 | extern void mapRegs_AMD64Instr ( HRegRemap*, AMD64Instr*, Bool ); |
sewardj | c33671d | 2005-02-01 20:30:00 +0000 | [diff] [blame] | 729 | extern Bool isMove_AMD64Instr ( AMD64Instr*, HReg*, HReg* ); |
sewardj | 0528bb5 | 2005-12-15 15:45:20 +0000 | [diff] [blame] | 730 | extern Int emit_AMD64Instr ( UChar* buf, Int nbuf, AMD64Instr*, |
| 731 | Bool, void* dispatch ); |
cerion | 92b6436 | 2005-12-13 12:02:26 +0000 | [diff] [blame] | 732 | extern AMD64Instr* genSpill_AMD64 ( HReg rreg, Int offset, Bool ); |
| 733 | extern AMD64Instr* genReload_AMD64 ( HReg rreg, Int offset, Bool ); |
sewardj | c33671d | 2005-02-01 20:30:00 +0000 | [diff] [blame] | 734 | extern void getAllocableRegs_AMD64 ( Int*, HReg** ); |
sewardj | dd40fdf | 2006-12-24 02:20:24 +0000 | [diff] [blame] | 735 | extern HInstrArray* iselSB_AMD64 ( IRSB*, VexArch, |
sewardj | aca070a | 2006-10-17 00:28:22 +0000 | [diff] [blame] | 736 | VexArchInfo*, |
sewardj | dd40fdf | 2006-12-24 02:20:24 +0000 | [diff] [blame] | 737 | VexAbiInfo* ); |
sewardj | a3e9830 | 2005-02-01 15:55:05 +0000 | [diff] [blame] | 738 | |
| 739 | #endif /* ndef __LIBVEX_HOST_AMD64_HDEFS_H */ |
| 740 | |
| 741 | /*---------------------------------------------------------------*/ |
| 742 | /*--- end host-amd64/hdefs.h ---*/ |
| 743 | /*---------------------------------------------------------------*/ |