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gerrit-public.fairphone.software / platform / external / valgrind / 92882e51ca7a3393849f422fee10350d59ae81d5 / . / memcheck / mc_machine.c
blob: ed46eba566e7fc75da526e465f4db9810f6c7fb4 [file] [log] [blame]
sewardj7cf4e6b2008-05-01 20:24:26 +0000[diff] [blame]1
2/*--------------------------------------------------------------------*/
3/*--- Contains machine-specific (guest-state-layout-specific) ---*/
4/*--- support for origin tracking. ---*/
5/*--- mc_machine.c ---*/
6/*--------------------------------------------------------------------*/
7
8/*
9 This file is part of MemCheck, a heavyweight Valgrind tool for
10 detecting memory errors.
11
sewardj0f157dd2013-10-18 14:27:36 +0000[diff] [blame]12 Copyright (C) 2008-2013 OpenWorks Ltd
sewardj7cf4e6b2008-05-01 20:24:26 +0000[diff] [blame]13 info@open-works.co.uk
14
15 This program is free software; you can redistribute it and/or
16 modify it under the terms of the GNU General Public License as
17 published by the Free Software Foundation; either version 2 of the
18 License, or (at your option) any later version.
19
20 This program is distributed in the hope that it will be useful, but
21 WITHOUT ANY WARRANTY; without even the implied warranty of
22 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
23 General Public License for more details.
24
25 You should have received a copy of the GNU General Public License
26 along with this program; if not, write to the Free Software
27 Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
28 02111-1307, USA.
29
30 The GNU General Public License is contained in the file COPYING.
31
32 Neither the names of the U.S. Department of Energy nor the
33 University of California nor the names of its contributors may be
34 used to endorse or promote products derived from this software
35 without prior written permission.
36*/
37
38#include "pub_tool_basics.h"
philippe6643e962012-01-17 21:16:30 +0000[diff] [blame]39#include "pub_tool_poolalloc.h" // For mc_include.h
sewardj7cf4e6b2008-05-01 20:24:26 +0000[diff] [blame]40#include "pub_tool_hashtable.h" // For mc_include.h
41#include "pub_tool_libcassert.h"
42#include "pub_tool_libcprint.h"
43#include "pub_tool_tooliface.h"
44
45#include "mc_include.h"
46
47#undef MC_SIZEOF_GUEST_STATE
48
49#if defined(VGA_x86)
50# include "libvex_guest_x86.h"
51# define MC_SIZEOF_GUEST_STATE sizeof(VexGuestX86State)
52#endif
53
54#if defined(VGA_amd64)
55# include "libvex_guest_amd64.h"
56# define MC_SIZEOF_GUEST_STATE sizeof(VexGuestAMD64State)
57#endif
58
59#if defined(VGA_ppc32)
60# include "libvex_guest_ppc32.h"
61# define MC_SIZEOF_GUEST_STATE sizeof(VexGuestPPC32State)
62#endif
63
carllcae0cc22014-08-07 23:17:29 +0000[diff] [blame]64#if defined(VGA_ppc64be) || defined(VGA_ppc64le)
sewardj7cf4e6b2008-05-01 20:24:26 +0000[diff] [blame]65# include "libvex_guest_ppc64.h"
66# define MC_SIZEOF_GUEST_STATE sizeof(VexGuestPPC64State)
67#endif
68
sewardjb5b87402011-03-07 16:05:35 +0000[diff] [blame]69#if defined(VGA_s390x)
70# include "libvex_guest_s390x.h"
71# define MC_SIZEOF_GUEST_STATE sizeof(VexGuestS390XState)
72#endif
73
sewardj59570ff2010-01-01 11:59:33 +0000[diff] [blame]74#if defined(VGA_arm)
75# include "libvex_guest_arm.h"
76# define MC_SIZEOF_GUEST_STATE sizeof(VexGuestARMState)
77#endif
78
sewardjf0c12502014-01-12 12:54:00 +0000[diff] [blame]79#if defined(VGA_arm64)
80# include "libvex_guest_arm64.h"
81# define MC_SIZEOF_GUEST_STATE sizeof(VexGuestARM64State)
82#endif
83
sewardj5db15402012-06-07 09:13:21 +0000[diff] [blame]84#if defined(VGA_mips32)
85# include "libvex_guest_mips32.h"
86# define MC_SIZEOF_GUEST_STATE sizeof(VexGuestMIPS32State)
87#endif
88
petarj4df0bfc2013-02-27 23:17:33 +0000[diff] [blame]89#if defined(VGA_mips64)
90# include "libvex_guest_mips64.h"
91# define MC_SIZEOF_GUEST_STATE sizeof(VexGuestMIPS64State)
92#endif
93
sewardj7cf4e6b2008-05-01 20:24:26 +0000[diff] [blame]94static inline Bool host_is_big_endian ( void ) {
95 UInt x = 0x11223344;
96 return 0x1122 == *(UShort*)(&x);
97}
98static inline Bool host_is_little_endian ( void ) {
99 UInt x = 0x11223344;
100 return 0x3344 == *(UShort*)(&x);
101}
102
103
104/* Let (offset,szB) describe a reference to the guest state section
105 [offset, offset+szB).
106
107 This function returns the corresponding guest state reference to be
108 used for the origin tag (which of course will be in the second
109 shadow area), or -1 if this piece of guest state is not to be
110 tracked.
111
112 Since origin tags are 32-bits long, we expect any returned value
113 (except -1) to be a multiple of 4, between 0 and
114 sizeof(guest-state)-4 inclusive.
115
116 This is inherently (guest-)architecture specific. For x86 and
117 amd64 we do some somewhat tricky things to give %AH .. %DH their
118 own tags. On ppc32/64 we do some marginally tricky things to give
119 all 16 %CR components their own tags.
120
121 This function only deals with references to the guest state whose
122 offsets are known at translation time (that is, references arising
123 from Put and Get). References whose offset is not known until run
124 time (that is, arise from PutI and GetI) are handled by
125 MC_(get_otrack_reg_array_equiv_int_type) below.
126
127 Note that since some guest state arrays (eg, the x86 FP reg stack)
128 are accessed both as arrays (eg, x87 insns) and directly (eg, MMX
129 insns), the two functions must be consistent for those sections of
130 guest state -- that is, they must both say the area is shadowed, or
131 both say it is not.
132
133 This function is dependent on the host's endianness, hence we
134 assert that the use case is supported.
135*/
136static Int get_otrack_shadow_offset_wrk ( Int offset, Int szB ); /*fwds*/
137
138Int MC_(get_otrack_shadow_offset) ( Int offset, Int szB )
139{
140 Int cand = get_otrack_shadow_offset_wrk( offset, szB );
141 if (cand == -1)
142 return cand;
143 tl_assert(0 == (cand & 3));
144 tl_assert(cand <= MC_SIZEOF_GUEST_STATE-4);
145 return cand;
146}
147
148
149static Int get_otrack_shadow_offset_wrk ( Int offset, Int szB )
150{
151 /* -------------------- ppc64 -------------------- */
152
carllcae0cc22014-08-07 23:17:29 +0000[diff] [blame]153# if defined(VGA_ppc64be) || defined(VGA_ppc64le)
sewardj7cf4e6b2008-05-01 20:24:26 +0000[diff] [blame]154
155# define GOF(_fieldname) \
156 (offsetof(VexGuestPPC64State,guest_##_fieldname))
157# define SZB(_fieldname) \
158 (sizeof(((VexGuestPPC64State*)0)->guest_##_fieldname))
159
160 Int sz = szB;
161 Int o = offset;
162 tl_assert(sz > 0);
sewardj7cf4e6b2008-05-01 20:24:26 +0000[diff] [blame]163
florian17804f62014-09-05 14:49:17 +0000[diff] [blame]164#if defined(VGA_ppc64be)
165 tl_assert(host_is_big_endian());
166#elif defined(VGA_ppc64le)
167 tl_assert(host_is_little_endian());
168#endif
169
sewardj7cf4e6b2008-05-01 20:24:26 +0000[diff] [blame]170 if (sz == 8 || sz == 4) {
171 /* The point of this is to achieve
172 if ((o == GOF(GPRn) && sz == 8) || (o == 4+GOF(GPRn) && sz == 4))
173 return GOF(GPRn);
174 by testing ox instead of o, and setting ox back 4 bytes when sz == 4.
175 */
carll582d5822014-08-07 23:35:54 +0000[diff] [blame]176#if defined(VGA_ppc64le)
177 Int ox = o;
178#else
sewardj85857ab2008-05-06 15:40:32 +0000[diff] [blame]179 Int ox = sz == 8 ? o : (o - 4);
carll582d5822014-08-07 23:35:54 +0000[diff] [blame]180#endif
sewardj7cf4e6b2008-05-01 20:24:26 +0000[diff] [blame]181 if (ox == GOF(GPR0)) return ox;
182 if (ox == GOF(GPR1)) return ox;
183 if (ox == GOF(GPR2)) return ox;
184 if (ox == GOF(GPR3)) return ox;
185 if (ox == GOF(GPR4)) return ox;
186 if (ox == GOF(GPR5)) return ox;
187 if (ox == GOF(GPR6)) return ox;
188 if (ox == GOF(GPR7)) return ox;
189 if (ox == GOF(GPR8)) return ox;
190 if (ox == GOF(GPR9)) return ox;
191 if (ox == GOF(GPR10)) return ox;
192 if (ox == GOF(GPR11)) return ox;
193 if (ox == GOF(GPR12)) return ox;
194 if (ox == GOF(GPR13)) return ox;
195 if (ox == GOF(GPR14)) return ox;
196 if (ox == GOF(GPR15)) return ox;
197 if (ox == GOF(GPR16)) return ox;
198 if (ox == GOF(GPR17)) return ox;
199 if (ox == GOF(GPR18)) return ox;
200 if (ox == GOF(GPR19)) return ox;
201 if (ox == GOF(GPR20)) return ox;
202 if (ox == GOF(GPR21)) return ox;
203 if (ox == GOF(GPR22)) return ox;
204 if (ox == GOF(GPR23)) return ox;
205 if (ox == GOF(GPR24)) return ox;
206 if (ox == GOF(GPR25)) return ox;
207 if (ox == GOF(GPR26)) return ox;
208 if (ox == GOF(GPR27)) return ox;
209 if (ox == GOF(GPR28)) return ox;
210 if (ox == GOF(GPR29)) return ox;
211 if (ox == GOF(GPR30)) return ox;
212 if (ox == GOF(GPR31)) return ox;
213 }
214
215 if (o == GOF(LR) && sz == 8) return o;
216 if (o == GOF(CTR) && sz == 8) return o;
217
218 if (o == GOF(CIA) && sz == 8) return -1;
sewardj71633b12009-03-30 02:27:29 +0000[diff] [blame]219 if (o == GOF(IP_AT_SYSCALL) && sz == 8) return -1; /* slot unused */
sewardjb0ccb4d2012-04-02 10:22:05 +0000[diff] [blame]220 if (o == GOF(FPROUND) && sz == 1) return -1;
221 if (o == GOF(DFPROUND) && sz == 1) return -1;
florian2e497412012-08-26 03:22:09 +0000[diff] [blame]222 if (o == GOF(EMNOTE) && sz == 4) return -1;
sewardj1146ae62014-05-04 10:54:08 +0000[diff] [blame]223 if (o == GOF(CMSTART) && sz == 8) return -1;
224 if (o == GOF(CMLEN) && sz == 8) return -1;
sewardj7cf4e6b2008-05-01 20:24:26 +0000[diff] [blame]225 if (o == GOF(VSCR) && sz == 4) return -1;
226 if (o == GOF(VRSAVE) && sz == 4) return -1;
227 if (o == GOF(REDIR_SP) && sz == 8) return -1;
228
sewardjf34eb492011-04-15 11:57:05 +0000[diff] [blame]229 // With ISA 2.06, the "Vector-Scalar Floating-point" category
230 // provides facilities to support vector and scalar binary floating-
231 // point operations. A unified register file is an integral part
232 // of this new facility, combining floating point and vector registers
233 // using a 64x128-bit vector. These are referred to as VSR[0..63].
234 // The floating point registers are now mapped into double word element 0
235 // of VSR[0..31]. The 32x128-bit vector registers defined by the "Vector
236 // Facility [Category: Vector]" are now mapped to VSR[32..63].
237
238 // Floating point registers . . .
239 if (o == GOF(VSR0) && sz == 8) return o;
240 if (o == GOF(VSR1) && sz == 8) return o;
241 if (o == GOF(VSR2) && sz == 8) return o;
242 if (o == GOF(VSR3) && sz == 8) return o;
243 if (o == GOF(VSR4) && sz == 8) return o;
244 if (o == GOF(VSR5) && sz == 8) return o;
245 if (o == GOF(VSR6) && sz == 8) return o;
246 if (o == GOF(VSR7) && sz == 8) return o;
247 if (o == GOF(VSR8) && sz == 8) return o;
248 if (o == GOF(VSR9) && sz == 8) return o;
249 if (o == GOF(VSR10) && sz == 8) return o;
250 if (o == GOF(VSR11) && sz == 8) return o;
251 if (o == GOF(VSR12) && sz == 8) return o;
252 if (o == GOF(VSR13) && sz == 8) return o;
253 if (o == GOF(VSR14) && sz == 8) return o;
254 if (o == GOF(VSR15) && sz == 8) return o;
255 if (o == GOF(VSR16) && sz == 8) return o;
256 if (o == GOF(VSR17) && sz == 8) return o;
257 if (o == GOF(VSR18) && sz == 8) return o;
258 if (o == GOF(VSR19) && sz == 8) return o;
259 if (o == GOF(VSR20) && sz == 8) return o;
260 if (o == GOF(VSR21) && sz == 8) return o;
261 if (o == GOF(VSR22) && sz == 8) return o;
262 if (o == GOF(VSR23) && sz == 8) return o;
263 if (o == GOF(VSR24) && sz == 8) return o;
264 if (o == GOF(VSR25) && sz == 8) return o;
265 if (o == GOF(VSR26) && sz == 8) return o;
266 if (o == GOF(VSR27) && sz == 8) return o;
267 if (o == GOF(VSR28) && sz == 8) return o;
268 if (o == GOF(VSR29) && sz == 8) return o;
269 if (o == GOF(VSR30) && sz == 8) return o;
270 if (o == GOF(VSR31) && sz == 8) return o;
sewardj7cf4e6b2008-05-01 20:24:26 +0000[diff] [blame]271
272 /* For the various byte sized XER/CR pieces, use offset 8
sewardjf34eb492011-04-15 11:57:05 +0000[diff] [blame]273 in VSR0 .. VSR19. */
274 tl_assert(SZB(VSR0) == 16);
275 if (o == GOF(XER_SO) && sz == 1) return 8 +GOF(VSR0);
276 if (o == GOF(XER_OV) && sz == 1) return 8 +GOF(VSR1);
277 if (o == GOF(XER_CA) && sz == 1) return 8 +GOF(VSR2);
278 if (o == GOF(XER_BC) && sz == 1) return 8 +GOF(VSR3);
sewardj7cf4e6b2008-05-01 20:24:26 +0000[diff] [blame]279
sewardjf34eb492011-04-15 11:57:05 +0000[diff] [blame]280 if (o == GOF(CR0_321) && sz == 1) return 8 +GOF(VSR4);
281 if (o == GOF(CR0_0) && sz == 1) return 8 +GOF(VSR5);
282 if (o == GOF(CR1_321) && sz == 1) return 8 +GOF(VSR6);
283 if (o == GOF(CR1_0) && sz == 1) return 8 +GOF(VSR7);
284 if (o == GOF(CR2_321) && sz == 1) return 8 +GOF(VSR8);
285 if (o == GOF(CR2_0) && sz == 1) return 8 +GOF(VSR9);
286 if (o == GOF(CR3_321) && sz == 1) return 8 +GOF(VSR10);
287 if (o == GOF(CR3_0) && sz == 1) return 8 +GOF(VSR11);
288 if (o == GOF(CR4_321) && sz == 1) return 8 +GOF(VSR12);
289 if (o == GOF(CR4_0) && sz == 1) return 8 +GOF(VSR13);
290 if (o == GOF(CR5_321) && sz == 1) return 8 +GOF(VSR14);
291 if (o == GOF(CR5_0) && sz == 1) return 8 +GOF(VSR15);
292 if (o == GOF(CR6_321) && sz == 1) return 8 +GOF(VSR16);
293 if (o == GOF(CR6_0) && sz == 1) return 8 +GOF(VSR17);
294 if (o == GOF(CR7_321) && sz == 1) return 8 +GOF(VSR18);
295 if (o == GOF(CR7_0) && sz == 1) return 8 +GOF(VSR19);
sewardj7cf4e6b2008-05-01 20:24:26 +0000[diff] [blame]296
sewardjf34eb492011-04-15 11:57:05 +0000[diff] [blame]297 /* Vector registers .. use offset 0 in VSR0 .. VSR63. */
298 if (o >= GOF(VSR0) && o+sz <= GOF(VSR0) +SZB(VSR0)) return 0+ GOF(VSR0);
299 if (o >= GOF(VSR1) && o+sz <= GOF(VSR1) +SZB(VSR1)) return 0+ GOF(VSR1);
300 if (o >= GOF(VSR2) && o+sz <= GOF(VSR2) +SZB(VSR2)) return 0+ GOF(VSR2);
301 if (o >= GOF(VSR3) && o+sz <= GOF(VSR3) +SZB(VSR3)) return 0+ GOF(VSR3);
302 if (o >= GOF(VSR4) && o+sz <= GOF(VSR4) +SZB(VSR4)) return 0+ GOF(VSR4);
303 if (o >= GOF(VSR5) && o+sz <= GOF(VSR5) +SZB(VSR5)) return 0+ GOF(VSR5);
304 if (o >= GOF(VSR6) && o+sz <= GOF(VSR6) +SZB(VSR6)) return 0+ GOF(VSR6);
305 if (o >= GOF(VSR7) && o+sz <= GOF(VSR7) +SZB(VSR7)) return 0+ GOF(VSR7);
306 if (o >= GOF(VSR8) && o+sz <= GOF(VSR8) +SZB(VSR8)) return 0+ GOF(VSR8);
307 if (o >= GOF(VSR9) && o+sz <= GOF(VSR9) +SZB(VSR9)) return 0+ GOF(VSR9);
308 if (o >= GOF(VSR10) && o+sz <= GOF(VSR10)+SZB(VSR10)) return 0+ GOF(VSR10);
309 if (o >= GOF(VSR11) && o+sz <= GOF(VSR11)+SZB(VSR11)) return 0+ GOF(VSR11);
310 if (o >= GOF(VSR12) && o+sz <= GOF(VSR12)+SZB(VSR12)) return 0+ GOF(VSR12);
311 if (o >= GOF(VSR13) && o+sz <= GOF(VSR13)+SZB(VSR13)) return 0+ GOF(VSR13);
312 if (o >= GOF(VSR14) && o+sz <= GOF(VSR14)+SZB(VSR14)) return 0+ GOF(VSR14);
313 if (o >= GOF(VSR15) && o+sz <= GOF(VSR15)+SZB(VSR15)) return 0+ GOF(VSR15);
314 if (o >= GOF(VSR16) && o+sz <= GOF(VSR16)+SZB(VSR16)) return 0+ GOF(VSR16);
315 if (o >= GOF(VSR17) && o+sz <= GOF(VSR17)+SZB(VSR17)) return 0+ GOF(VSR17);
316 if (o >= GOF(VSR18) && o+sz <= GOF(VSR18)+SZB(VSR18)) return 0+ GOF(VSR18);
317 if (o >= GOF(VSR19) && o+sz <= GOF(VSR19)+SZB(VSR19)) return 0+ GOF(VSR19);
318 if (o >= GOF(VSR20) && o+sz <= GOF(VSR20)+SZB(VSR20)) return 0+ GOF(VSR20);
319 if (o >= GOF(VSR21) && o+sz <= GOF(VSR21)+SZB(VSR21)) return 0+ GOF(VSR21);
320 if (o >= GOF(VSR22) && o+sz <= GOF(VSR22)+SZB(VSR22)) return 0+ GOF(VSR22);
321 if (o >= GOF(VSR23) && o+sz <= GOF(VSR23)+SZB(VSR23)) return 0+ GOF(VSR23);
322 if (o >= GOF(VSR24) && o+sz <= GOF(VSR24)+SZB(VSR24)) return 0+ GOF(VSR24);
323 if (o >= GOF(VSR25) && o+sz <= GOF(VSR25)+SZB(VSR25)) return 0+ GOF(VSR25);
324 if (o >= GOF(VSR26) && o+sz <= GOF(VSR26)+SZB(VSR26)) return 0+ GOF(VSR26);
325 if (o >= GOF(VSR27) && o+sz <= GOF(VSR27)+SZB(VSR27)) return 0+ GOF(VSR27);
326 if (o >= GOF(VSR28) && o+sz <= GOF(VSR28)+SZB(VSR28)) return 0+ GOF(VSR28);
327 if (o >= GOF(VSR29) && o+sz <= GOF(VSR29)+SZB(VSR29)) return 0+ GOF(VSR29);
328 if (o >= GOF(VSR30) && o+sz <= GOF(VSR30)+SZB(VSR30)) return 0+ GOF(VSR30);
329 if (o >= GOF(VSR31) && o+sz <= GOF(VSR31)+SZB(VSR31)) return 0+ GOF(VSR31);
330 if (o >= GOF(VSR32) && o+sz <= GOF(VSR32)+SZB(VSR32)) return 0+ GOF(VSR32);
331 if (o >= GOF(VSR33) && o+sz <= GOF(VSR33)+SZB(VSR33)) return 0+ GOF(VSR33);
332 if (o >= GOF(VSR34) && o+sz <= GOF(VSR34)+SZB(VSR34)) return 0+ GOF(VSR34);
333 if (o >= GOF(VSR35) && o+sz <= GOF(VSR35)+SZB(VSR35)) return 0+ GOF(VSR35);
334 if (o >= GOF(VSR36) && o+sz <= GOF(VSR36)+SZB(VSR36)) return 0+ GOF(VSR36);
335 if (o >= GOF(VSR37) && o+sz <= GOF(VSR37)+SZB(VSR37)) return 0+ GOF(VSR37);
336 if (o >= GOF(VSR38) && o+sz <= GOF(VSR38)+SZB(VSR38)) return 0+ GOF(VSR38);
337 if (o >= GOF(VSR39) && o+sz <= GOF(VSR39)+SZB(VSR39)) return 0+ GOF(VSR39);
338 if (o >= GOF(VSR40) && o+sz <= GOF(VSR40)+SZB(VSR40)) return 0+ GOF(VSR40);
339 if (o >= GOF(VSR41) && o+sz <= GOF(VSR41)+SZB(VSR41)) return 0+ GOF(VSR41);
340 if (o >= GOF(VSR42) && o+sz <= GOF(VSR42)+SZB(VSR42)) return 0+ GOF(VSR42);
341 if (o >= GOF(VSR43) && o+sz <= GOF(VSR43)+SZB(VSR43)) return 0+ GOF(VSR43);
342 if (o >= GOF(VSR44) && o+sz <= GOF(VSR44)+SZB(VSR44)) return 0+ GOF(VSR44);
343 if (o >= GOF(VSR45) && o+sz <= GOF(VSR45)+SZB(VSR45)) return 0+ GOF(VSR45);
344 if (o >= GOF(VSR46) && o+sz <= GOF(VSR46)+SZB(VSR46)) return 0+ GOF(VSR46);
345 if (o >= GOF(VSR47) && o+sz <= GOF(VSR47)+SZB(VSR47)) return 0+ GOF(VSR47);
346 if (o >= GOF(VSR48) && o+sz <= GOF(VSR48)+SZB(VSR48)) return 0+ GOF(VSR48);
347 if (o >= GOF(VSR49) && o+sz <= GOF(VSR49)+SZB(VSR49)) return 0+ GOF(VSR49);
348 if (o >= GOF(VSR50) && o+sz <= GOF(VSR50)+SZB(VSR50)) return 0+ GOF(VSR50);
349 if (o >= GOF(VSR51) && o+sz <= GOF(VSR51)+SZB(VSR51)) return 0+ GOF(VSR51);
350 if (o >= GOF(VSR52) && o+sz <= GOF(VSR52)+SZB(VSR52)) return 0+ GOF(VSR52);
351 if (o >= GOF(VSR53) && o+sz <= GOF(VSR53)+SZB(VSR53)) return 0+ GOF(VSR53);
352 if (o >= GOF(VSR54) && o+sz <= GOF(VSR54)+SZB(VSR54)) return 0+ GOF(VSR54);
353 if (o >= GOF(VSR55) && o+sz <= GOF(VSR55)+SZB(VSR55)) return 0+ GOF(VSR55);
354 if (o >= GOF(VSR56) && o+sz <= GOF(VSR56)+SZB(VSR56)) return 0+ GOF(VSR56);
355 if (o >= GOF(VSR57) && o+sz <= GOF(VSR57)+SZB(VSR57)) return 0+ GOF(VSR57);
356 if (o >= GOF(VSR58) && o+sz <= GOF(VSR58)+SZB(VSR58)) return 0+ GOF(VSR58);
357 if (o >= GOF(VSR59) && o+sz <= GOF(VSR59)+SZB(VSR59)) return 0+ GOF(VSR59);
358 if (o >= GOF(VSR60) && o+sz <= GOF(VSR60)+SZB(VSR60)) return 0+ GOF(VSR60);
359 if (o >= GOF(VSR61) && o+sz <= GOF(VSR61)+SZB(VSR61)) return 0+ GOF(VSR61);
360 if (o >= GOF(VSR62) && o+sz <= GOF(VSR62)+SZB(VSR62)) return 0+ GOF(VSR62);
361 if (o >= GOF(VSR63) && o+sz <= GOF(VSR63)+SZB(VSR63)) return 0+ GOF(VSR63);
sewardj7cf4e6b2008-05-01 20:24:26 +0000[diff] [blame]362
363 VG_(printf)("MC_(get_otrack_shadow_offset)(ppc64)(off=%d,sz=%d)\n",
364 offset,szB);
365 tl_assert(0);
366# undef GOF
367# undef SZB
368
369 /* -------------------- ppc32 -------------------- */
370
371# elif defined(VGA_ppc32)
372
373# define GOF(_fieldname) \
374 (offsetof(VexGuestPPC32State,guest_##_fieldname))
375# define SZB(_fieldname) \
376 (sizeof(((VexGuestPPC32State*)0)->guest_##_fieldname))
377 Int o = offset;
378 Int sz = szB;
379 tl_assert(sz > 0);
sewardj7cf4e6b2008-05-01 20:24:26 +0000[diff] [blame]380
381 if (o == GOF(GPR0) && sz == 4) return o;
382 if (o == GOF(GPR1) && sz == 4) return o;
383 if (o == GOF(GPR2) && sz == 4) return o;
384 if (o == GOF(GPR3) && sz == 4) return o;
385 if (o == GOF(GPR4) && sz == 4) return o;
386 if (o == GOF(GPR5) && sz == 4) return o;
387 if (o == GOF(GPR6) && sz == 4) return o;
388 if (o == GOF(GPR7) && sz == 4) return o;
389 if (o == GOF(GPR8) && sz == 4) return o;
390 if (o == GOF(GPR9) && sz == 4) return o;
391 if (o == GOF(GPR10) && sz == 4) return o;
392 if (o == GOF(GPR11) && sz == 4) return o;
393 if (o == GOF(GPR12) && sz == 4) return o;
394 if (o == GOF(GPR13) && sz == 4) return o;
395 if (o == GOF(GPR14) && sz == 4) return o;
396 if (o == GOF(GPR15) && sz == 4) return o;
397 if (o == GOF(GPR16) && sz == 4) return o;
398 if (o == GOF(GPR17) && sz == 4) return o;
399 if (o == GOF(GPR18) && sz == 4) return o;
400 if (o == GOF(GPR19) && sz == 4) return o;
401 if (o == GOF(GPR20) && sz == 4) return o;
402 if (o == GOF(GPR21) && sz == 4) return o;
403 if (o == GOF(GPR22) && sz == 4) return o;
404 if (o == GOF(GPR23) && sz == 4) return o;
405 if (o == GOF(GPR24) && sz == 4) return o;
406 if (o == GOF(GPR25) && sz == 4) return o;
407 if (o == GOF(GPR26) && sz == 4) return o;
408 if (o == GOF(GPR27) && sz == 4) return o;
409 if (o == GOF(GPR28) && sz == 4) return o;
410 if (o == GOF(GPR29) && sz == 4) return o;
411 if (o == GOF(GPR30) && sz == 4) return o;
412 if (o == GOF(GPR31) && sz == 4) return o;
413
414 if (o == GOF(LR) && sz == 4) return o;
415 if (o == GOF(CTR) && sz == 4) return o;
416
417 if (o == GOF(CIA) && sz == 4) return -1;
sewardj71633b12009-03-30 02:27:29 +0000[diff] [blame]418 if (o == GOF(IP_AT_SYSCALL) && sz == 4) return -1; /* slot unused */
sewardjf06eabf2012-04-02 15:10:37 +0000[diff] [blame]419 if (o == GOF(FPROUND) && sz == 1) return -1;
420 if (o == GOF(DFPROUND) && sz == 1) return -1;
sewardj3b507352009-02-14 15:28:46 +0000[diff] [blame]421 if (o == GOF(VRSAVE) && sz == 4) return -1;
florian2e497412012-08-26 03:22:09 +0000[diff] [blame]422 if (o == GOF(EMNOTE) && sz == 4) return -1;
sewardj1146ae62014-05-04 10:54:08 +0000[diff] [blame]423 if (o == GOF(CMSTART) && sz == 4) return -1;
424 if (o == GOF(CMLEN) && sz == 4) return -1;
sewardj7cf4e6b2008-05-01 20:24:26 +0000[diff] [blame]425 if (o == GOF(VSCR) && sz == 4) return -1;
426 if (o == GOF(REDIR_SP) && sz == 4) return -1;
427 if (o == GOF(SPRG3_RO) && sz == 4) return -1;
428
sewardjf34eb492011-04-15 11:57:05 +0000[diff] [blame]429 // With ISA 2.06, the "Vector-Scalar Floating-point" category
430 // provides facilities to support vector and scalar binary floating-
431 // point operations. A unified register file is an integral part
432 // of this new facility, combining floating point and vector registers
433 // using a 64x128-bit vector. These are referred to as VSR[0..63].
434 // The floating point registers are now mapped into double word element 0
435 // of VSR[0..31]. The 32x128-bit vector registers defined by the "Vector
436 // Facility [Category: Vector]" are now mapped to VSR[32..63].
437
438 // Floating point registers . . .
439 if (o == GOF(VSR0) && sz == 8) return o;
440 if (o == GOF(VSR1) && sz == 8) return o;
441 if (o == GOF(VSR2) && sz == 8) return o;
442 if (o == GOF(VSR3) && sz == 8) return o;
443 if (o == GOF(VSR4) && sz == 8) return o;
444 if (o == GOF(VSR5) && sz == 8) return o;
445 if (o == GOF(VSR6) && sz == 8) return o;
446 if (o == GOF(VSR7) && sz == 8) return o;
447 if (o == GOF(VSR8) && sz == 8) return o;
448 if (o == GOF(VSR9) && sz == 8) return o;
449 if (o == GOF(VSR10) && sz == 8) return o;
450 if (o == GOF(VSR11) && sz == 8) return o;
451 if (o == GOF(VSR12) && sz == 8) return o;
452 if (o == GOF(VSR13) && sz == 8) return o;
453 if (o == GOF(VSR14) && sz == 8) return o;
454 if (o == GOF(VSR15) && sz == 8) return o;
455 if (o == GOF(VSR16) && sz == 8) return o;
456 if (o == GOF(VSR17) && sz == 8) return o;
457 if (o == GOF(VSR18) && sz == 8) return o;
458 if (o == GOF(VSR19) && sz == 8) return o;
459 if (o == GOF(VSR20) && sz == 8) return o;
460 if (o == GOF(VSR21) && sz == 8) return o;
461 if (o == GOF(VSR22) && sz == 8) return o;
462 if (o == GOF(VSR23) && sz == 8) return o;
463 if (o == GOF(VSR24) && sz == 8) return o;
464 if (o == GOF(VSR25) && sz == 8) return o;
465 if (o == GOF(VSR26) && sz == 8) return o;
466 if (o == GOF(VSR27) && sz == 8) return o;
467 if (o == GOF(VSR28) && sz == 8) return o;
468 if (o == GOF(VSR29) && sz == 8) return o;
469 if (o == GOF(VSR30) && sz == 8) return o;
470 if (o == GOF(VSR31) && sz == 8) return o;
sewardj7cf4e6b2008-05-01 20:24:26 +0000[diff] [blame]471
472 /* For the various byte sized XER/CR pieces, use offset 8
sewardjf34eb492011-04-15 11:57:05 +0000[diff] [blame]473 in VSR0 .. VSR19. */
474 tl_assert(SZB(VSR0) == 16);
475 if (o == GOF(XER_SO) && sz == 1) return 8 +GOF(VSR0);
476 if (o == GOF(XER_OV) && sz == 1) return 8 +GOF(VSR1);
477 if (o == GOF(XER_CA) && sz == 1) return 8 +GOF(VSR2);
478 if (o == GOF(XER_BC) && sz == 1) return 8 +GOF(VSR3);
sewardj7cf4e6b2008-05-01 20:24:26 +0000[diff] [blame]479
sewardjf34eb492011-04-15 11:57:05 +0000[diff] [blame]480 if (o == GOF(CR0_321) && sz == 1) return 8 +GOF(VSR4);
481 if (o == GOF(CR0_0) && sz == 1) return 8 +GOF(VSR5);
482 if (o == GOF(CR1_321) && sz == 1) return 8 +GOF(VSR6);
483 if (o == GOF(CR1_0) && sz == 1) return 8 +GOF(VSR7);
484 if (o == GOF(CR2_321) && sz == 1) return 8 +GOF(VSR8);
485 if (o == GOF(CR2_0) && sz == 1) return 8 +GOF(VSR9);
486 if (o == GOF(CR3_321) && sz == 1) return 8 +GOF(VSR10);
487 if (o == GOF(CR3_0) && sz == 1) return 8 +GOF(VSR11);
488 if (o == GOF(CR4_321) && sz == 1) return 8 +GOF(VSR12);
489 if (o == GOF(CR4_0) && sz == 1) return 8 +GOF(VSR13);
490 if (o == GOF(CR5_321) && sz == 1) return 8 +GOF(VSR14);
491 if (o == GOF(CR5_0) && sz == 1) return 8 +GOF(VSR15);
492 if (o == GOF(CR6_321) && sz == 1) return 8 +GOF(VSR16);
493 if (o == GOF(CR6_0) && sz == 1) return 8 +GOF(VSR17);
494 if (o == GOF(CR7_321) && sz == 1) return 8 +GOF(VSR18);
495 if (o == GOF(CR7_0) && sz == 1) return 8 +GOF(VSR19);
sewardj7cf4e6b2008-05-01 20:24:26 +0000[diff] [blame]496
sewardjf34eb492011-04-15 11:57:05 +0000[diff] [blame]497 /* Vector registers .. use offset 0 in VSR0 .. VSR63. */
498 if (o >= GOF(VSR0) && o+sz <= GOF(VSR0) +SZB(VSR0)) return 0+ GOF(VSR0);
499 if (o >= GOF(VSR1) && o+sz <= GOF(VSR1) +SZB(VSR1)) return 0+ GOF(VSR1);
500 if (o >= GOF(VSR2) && o+sz <= GOF(VSR2) +SZB(VSR2)) return 0+ GOF(VSR2);
501 if (o >= GOF(VSR3) && o+sz <= GOF(VSR3) +SZB(VSR3)) return 0+ GOF(VSR3);
502 if (o >= GOF(VSR4) && o+sz <= GOF(VSR4) +SZB(VSR4)) return 0+ GOF(VSR4);
503 if (o >= GOF(VSR5) && o+sz <= GOF(VSR5) +SZB(VSR5)) return 0+ GOF(VSR5);
504 if (o >= GOF(VSR6) && o+sz <= GOF(VSR6) +SZB(VSR6)) return 0+ GOF(VSR6);
505 if (o >= GOF(VSR7) && o+sz <= GOF(VSR7) +SZB(VSR7)) return 0+ GOF(VSR7);
506 if (o >= GOF(VSR8) && o+sz <= GOF(VSR8) +SZB(VSR8)) return 0+ GOF(VSR8);
507 if (o >= GOF(VSR9) && o+sz <= GOF(VSR9) +SZB(VSR9)) return 0+ GOF(VSR9);
508 if (o >= GOF(VSR10) && o+sz <= GOF(VSR10)+SZB(VSR10)) return 0+ GOF(VSR10);
509 if (o >= GOF(VSR11) && o+sz <= GOF(VSR11)+SZB(VSR11)) return 0+ GOF(VSR11);
510 if (o >= GOF(VSR12) && o+sz <= GOF(VSR12)+SZB(VSR12)) return 0+ GOF(VSR12);
511 if (o >= GOF(VSR13) && o+sz <= GOF(VSR13)+SZB(VSR13)) return 0+ GOF(VSR13);
512 if (o >= GOF(VSR14) && o+sz <= GOF(VSR14)+SZB(VSR14)) return 0+ GOF(VSR14);
513 if (o >= GOF(VSR15) && o+sz <= GOF(VSR15)+SZB(VSR15)) return 0+ GOF(VSR15);
514 if (o >= GOF(VSR16) && o+sz <= GOF(VSR16)+SZB(VSR16)) return 0+ GOF(VSR16);
515 if (o >= GOF(VSR17) && o+sz <= GOF(VSR17)+SZB(VSR17)) return 0+ GOF(VSR17);
516 if (o >= GOF(VSR18) && o+sz <= GOF(VSR18)+SZB(VSR18)) return 0+ GOF(VSR18);
517 if (o >= GOF(VSR19) && o+sz <= GOF(VSR19)+SZB(VSR19)) return 0+ GOF(VSR19);
518 if (o >= GOF(VSR20) && o+sz <= GOF(VSR20)+SZB(VSR20)) return 0+ GOF(VSR20);
519 if (o >= GOF(VSR21) && o+sz <= GOF(VSR21)+SZB(VSR21)) return 0+ GOF(VSR21);
520 if (o >= GOF(VSR22) && o+sz <= GOF(VSR22)+SZB(VSR22)) return 0+ GOF(VSR22);
521 if (o >= GOF(VSR23) && o+sz <= GOF(VSR23)+SZB(VSR23)) return 0+ GOF(VSR23);
522 if (o >= GOF(VSR24) && o+sz <= GOF(VSR24)+SZB(VSR24)) return 0+ GOF(VSR24);
523 if (o >= GOF(VSR25) && o+sz <= GOF(VSR25)+SZB(VSR25)) return 0+ GOF(VSR25);
524 if (o >= GOF(VSR26) && o+sz <= GOF(VSR26)+SZB(VSR26)) return 0+ GOF(VSR26);
525 if (o >= GOF(VSR27) && o+sz <= GOF(VSR27)+SZB(VSR27)) return 0+ GOF(VSR27);
526 if (o >= GOF(VSR28) && o+sz <= GOF(VSR28)+SZB(VSR28)) return 0+ GOF(VSR28);
527 if (o >= GOF(VSR29) && o+sz <= GOF(VSR29)+SZB(VSR29)) return 0+ GOF(VSR29);
528 if (o >= GOF(VSR30) && o+sz <= GOF(VSR30)+SZB(VSR30)) return 0+ GOF(VSR30);
529 if (o >= GOF(VSR31) && o+sz <= GOF(VSR31)+SZB(VSR31)) return 0+ GOF(VSR31);
530 if (o >= GOF(VSR32) && o+sz <= GOF(VSR32)+SZB(VSR32)) return 0+ GOF(VSR32);
531 if (o >= GOF(VSR33) && o+sz <= GOF(VSR33)+SZB(VSR33)) return 0+ GOF(VSR33);
532 if (o >= GOF(VSR34) && o+sz <= GOF(VSR34)+SZB(VSR34)) return 0+ GOF(VSR34);
533 if (o >= GOF(VSR35) && o+sz <= GOF(VSR35)+SZB(VSR35)) return 0+ GOF(VSR35);
534 if (o >= GOF(VSR36) && o+sz <= GOF(VSR36)+SZB(VSR36)) return 0+ GOF(VSR36);
535 if (o >= GOF(VSR37) && o+sz <= GOF(VSR37)+SZB(VSR37)) return 0+ GOF(VSR37);
536 if (o >= GOF(VSR38) && o+sz <= GOF(VSR38)+SZB(VSR38)) return 0+ GOF(VSR38);
537 if (o >= GOF(VSR39) && o+sz <= GOF(VSR39)+SZB(VSR39)) return 0+ GOF(VSR39);
538 if (o >= GOF(VSR40) && o+sz <= GOF(VSR40)+SZB(VSR40)) return 0+ GOF(VSR40);
539 if (o >= GOF(VSR41) && o+sz <= GOF(VSR41)+SZB(VSR41)) return 0+ GOF(VSR41);
540 if (o >= GOF(VSR42) && o+sz <= GOF(VSR42)+SZB(VSR42)) return 0+ GOF(VSR42);
541 if (o >= GOF(VSR43) && o+sz <= GOF(VSR43)+SZB(VSR43)) return 0+ GOF(VSR43);
542 if (o >= GOF(VSR44) && o+sz <= GOF(VSR44)+SZB(VSR44)) return 0+ GOF(VSR44);
543 if (o >= GOF(VSR45) && o+sz <= GOF(VSR45)+SZB(VSR45)) return 0+ GOF(VSR45);
544 if (o >= GOF(VSR46) && o+sz <= GOF(VSR46)+SZB(VSR46)) return 0+ GOF(VSR46);
545 if (o >= GOF(VSR47) && o+sz <= GOF(VSR47)+SZB(VSR47)) return 0+ GOF(VSR47);
546 if (o >= GOF(VSR48) && o+sz <= GOF(VSR48)+SZB(VSR48)) return 0+ GOF(VSR48);
547 if (o >= GOF(VSR49) && o+sz <= GOF(VSR49)+SZB(VSR49)) return 0+ GOF(VSR49);
548 if (o >= GOF(VSR50) && o+sz <= GOF(VSR50)+SZB(VSR50)) return 0+ GOF(VSR50);
549 if (o >= GOF(VSR51) && o+sz <= GOF(VSR51)+SZB(VSR51)) return 0+ GOF(VSR51);
550 if (o >= GOF(VSR52) && o+sz <= GOF(VSR52)+SZB(VSR52)) return 0+ GOF(VSR52);
551 if (o >= GOF(VSR53) && o+sz <= GOF(VSR53)+SZB(VSR53)) return 0+ GOF(VSR53);
552 if (o >= GOF(VSR54) && o+sz <= GOF(VSR54)+SZB(VSR54)) return 0+ GOF(VSR54);
553 if (o >= GOF(VSR55) && o+sz <= GOF(VSR55)+SZB(VSR55)) return 0+ GOF(VSR55);
554 if (o >= GOF(VSR56) && o+sz <= GOF(VSR56)+SZB(VSR56)) return 0+ GOF(VSR56);
555 if (o >= GOF(VSR57) && o+sz <= GOF(VSR57)+SZB(VSR57)) return 0+ GOF(VSR57);
556 if (o >= GOF(VSR58) && o+sz <= GOF(VSR58)+SZB(VSR58)) return 0+ GOF(VSR58);
557 if (o >= GOF(VSR59) && o+sz <= GOF(VSR59)+SZB(VSR59)) return 0+ GOF(VSR59);
558 if (o >= GOF(VSR60) && o+sz <= GOF(VSR60)+SZB(VSR60)) return 0+ GOF(VSR60);
559 if (o >= GOF(VSR61) && o+sz <= GOF(VSR61)+SZB(VSR61)) return 0+ GOF(VSR61);
560 if (o >= GOF(VSR62) && o+sz <= GOF(VSR62)+SZB(VSR62)) return 0+ GOF(VSR62);
561 if (o >= GOF(VSR63) && o+sz <= GOF(VSR63)+SZB(VSR63)) return 0+ GOF(VSR63);
sewardj7cf4e6b2008-05-01 20:24:26 +0000[diff] [blame]562
563 VG_(printf)("MC_(get_otrack_shadow_offset)(ppc32)(off=%d,sz=%d)\n",
564 offset,szB);
565 tl_assert(0);
566# undef GOF
567# undef SZB
568
569 /* -------------------- amd64 -------------------- */
570
571# elif defined(VGA_amd64)
572
573# define GOF(_fieldname) \
574 (offsetof(VexGuestAMD64State,guest_##_fieldname))
575# define SZB(_fieldname) \
576 (sizeof(((VexGuestAMD64State*)0)->guest_##_fieldname))
577 Int o = offset;
578 Int sz = szB;
579 Bool is1248 = sz == 8 || sz == 4 || sz == 2 || sz == 1;
580 tl_assert(sz > 0);
581 tl_assert(host_is_little_endian());
582
583 if (o == GOF(RAX) && is1248) return o;
584 if (o == GOF(RCX) && is1248) return o;
585 if (o == GOF(RDX) && is1248) return o;
586 if (o == GOF(RBX) && is1248) return o;
587 if (o == GOF(RSP) && is1248) return o;
588 if (o == GOF(RBP) && is1248) return o;
589 if (o == GOF(RSI) && is1248) return o;
590 if (o == GOF(RDI) && is1248) return o;
591 if (o == GOF(R8) && is1248) return o;
592 if (o == GOF(R9) && is1248) return o;
593 if (o == GOF(R10) && is1248) return o;
594 if (o == GOF(R11) && is1248) return o;
595 if (o == GOF(R12) && is1248) return o;
596 if (o == GOF(R13) && is1248) return o;
597 if (o == GOF(R14) && is1248) return o;
598 if (o == GOF(R15) && is1248) return o;
599
600 if (o == GOF(CC_DEP1) && sz == 8) return o;
601 if (o == GOF(CC_DEP2) && sz == 8) return o;
602
603 if (o == GOF(CC_OP) && sz == 8) return -1; /* slot used for %AH */
604 if (o == GOF(CC_NDEP) && sz == 8) return -1; /* slot used for %BH */
605 if (o == GOF(DFLAG) && sz == 8) return -1; /* slot used for %CH */
606 if (o == GOF(RIP) && sz == 8) return -1; /* slot unused */
sewardj71633b12009-03-30 02:27:29 +0000[diff] [blame]607 if (o == GOF(IP_AT_SYSCALL) && sz == 8) return -1; /* slot unused */
sewardj7cf4e6b2008-05-01 20:24:26 +0000[diff] [blame]608 if (o == GOF(IDFLAG) && sz == 8) return -1; /* slot used for %DH */
sewardj65864932010-09-28 16:00:11 +0000[diff] [blame]609 if (o == GOF(ACFLAG) && sz == 8) return -1; /* slot unused */
sewardj7cf4e6b2008-05-01 20:24:26 +0000[diff] [blame]610 if (o == GOF(FS_ZERO) && sz == 8) return -1; /* slot unused */
njnf76d27a2009-05-28 01:53:07 +0000[diff] [blame]611 if (o == GOF(GS_0x60) && sz == 8) return -1; /* slot unused */
sewardj1146ae62014-05-04 10:54:08 +0000[diff] [blame]612 if (o == GOF(CMSTART) && sz == 8) return -1; /* slot unused */
613 if (o == GOF(CMLEN) && sz == 8) return -1; /* slot unused */
sewardj3d5246f2013-01-29 21:13:00 +0000[diff] [blame]614 if (o == GOF(NRADDR) && sz == 8) return -1; /* slot unused */
sewardj7cf4e6b2008-05-01 20:24:26 +0000[diff] [blame]615
616 /* Treat %AH, %BH, %CH, %DH as independent registers. To do this
617 requires finding 4 unused 32-bit slots in the second-shadow
618 guest state, respectively: CC_OP CC_NDEP DFLAG IDFLAG, since
619 none of those are tracked. */
620 tl_assert(SZB(CC_OP) == 8);
621 tl_assert(SZB(CC_NDEP) == 8);
622 tl_assert(SZB(IDFLAG) == 8);
623 tl_assert(SZB(DFLAG) == 8);
624
625 if (o == 1+ GOF(RAX) && szB == 1) return GOF(CC_OP);
626 if (o == 1+ GOF(RBX) && szB == 1) return GOF(CC_NDEP);
627 if (o == 1+ GOF(RCX) && szB == 1) return GOF(DFLAG);
628 if (o == 1+ GOF(RDX) && szB == 1) return GOF(IDFLAG);
629
630 /* skip XMM and FP admin stuff */
631 if (o == GOF(SSEROUND) && szB == 8) return -1;
632 if (o == GOF(FTOP) && szB == 4) return -1;
633 if (o == GOF(FPROUND) && szB == 8) return -1;
florian2e497412012-08-26 03:22:09 +0000[diff] [blame]634 if (o == GOF(EMNOTE) && szB == 4) return -1;
sewardj89ea7ab2008-05-27 16:08:24 +0000[diff] [blame]635 if (o == GOF(FC3210) && szB == 8) return -1;
sewardj7cf4e6b2008-05-01 20:24:26 +0000[diff] [blame]636
637 /* XMM registers */
sewardj45fa9f42012-05-21 10:18:10 +0000[diff] [blame]638 if (o >= GOF(YMM0) && o+sz <= GOF(YMM0) +SZB(YMM0)) return GOF(YMM0);
639 if (o >= GOF(YMM1) && o+sz <= GOF(YMM1) +SZB(YMM1)) return GOF(YMM1);
640 if (o >= GOF(YMM2) && o+sz <= GOF(YMM2) +SZB(YMM2)) return GOF(YMM2);
641 if (o >= GOF(YMM3) && o+sz <= GOF(YMM3) +SZB(YMM3)) return GOF(YMM3);
642 if (o >= GOF(YMM4) && o+sz <= GOF(YMM4) +SZB(YMM4)) return GOF(YMM4);
643 if (o >= GOF(YMM5) && o+sz <= GOF(YMM5) +SZB(YMM5)) return GOF(YMM5);
644 if (o >= GOF(YMM6) && o+sz <= GOF(YMM6) +SZB(YMM6)) return GOF(YMM6);
645 if (o >= GOF(YMM7) && o+sz <= GOF(YMM7) +SZB(YMM7)) return GOF(YMM7);
646 if (o >= GOF(YMM8) && o+sz <= GOF(YMM8) +SZB(YMM8)) return GOF(YMM8);
647 if (o >= GOF(YMM9) && o+sz <= GOF(YMM9) +SZB(YMM9)) return GOF(YMM9);
648 if (o >= GOF(YMM10) && o+sz <= GOF(YMM10)+SZB(YMM10)) return GOF(YMM10);
649 if (o >= GOF(YMM11) && o+sz <= GOF(YMM11)+SZB(YMM11)) return GOF(YMM11);
650 if (o >= GOF(YMM12) && o+sz <= GOF(YMM12)+SZB(YMM12)) return GOF(YMM12);
651 if (o >= GOF(YMM13) && o+sz <= GOF(YMM13)+SZB(YMM13)) return GOF(YMM13);
652 if (o >= GOF(YMM14) && o+sz <= GOF(YMM14)+SZB(YMM14)) return GOF(YMM14);
653 if (o >= GOF(YMM15) && o+sz <= GOF(YMM15)+SZB(YMM15)) return GOF(YMM15);
654 if (o >= GOF(YMM16) && o+sz <= GOF(YMM16)+SZB(YMM16)) return GOF(YMM16);
sewardj7cf4e6b2008-05-01 20:24:26 +0000[diff] [blame]655
sewardjf1a483a2008-06-13 07:44:02 +0000[diff] [blame]656 /* MMX accesses to FP regs. Need to allow for 32-bit references
657 due to dirty helpers for frstor etc, which reference the entire
658 64-byte block in one go. */
659 if (o >= GOF(FPREG[0])
660 && o+sz <= GOF(FPREG[0])+SZB(FPREG[0])) return GOF(FPREG[0]);
661 if (o >= GOF(FPREG[1])
662 && o+sz <= GOF(FPREG[1])+SZB(FPREG[1])) return GOF(FPREG[1]);
663 if (o >= GOF(FPREG[2])
664 && o+sz <= GOF(FPREG[2])+SZB(FPREG[2])) return GOF(FPREG[2]);
665 if (o >= GOF(FPREG[3])
666 && o+sz <= GOF(FPREG[3])+SZB(FPREG[3])) return GOF(FPREG[3]);
667 if (o >= GOF(FPREG[4])
668 && o+sz <= GOF(FPREG[4])+SZB(FPREG[4])) return GOF(FPREG[4]);
669 if (o >= GOF(FPREG[5])
670 && o+sz <= GOF(FPREG[5])+SZB(FPREG[5])) return GOF(FPREG[5]);
671 if (o >= GOF(FPREG[6])
672 && o+sz <= GOF(FPREG[6])+SZB(FPREG[6])) return GOF(FPREG[6]);
673 if (o >= GOF(FPREG[7])
674 && o+sz <= GOF(FPREG[7])+SZB(FPREG[7])) return GOF(FPREG[7]);
sewardj7cf4e6b2008-05-01 20:24:26 +0000[diff] [blame]675
676 /* Map high halves of %RAX,%RCX,%RDX,%RBX to the whole register.
677 This is needed because the general handling of dirty helper
678 calls is done in 4 byte chunks. Hence we will see these.
679 Currently we only expect to see artefacts from CPUID. */
680 if (o == 4+ GOF(RAX) && sz == 4) return GOF(RAX);
681 if (o == 4+ GOF(RCX) && sz == 4) return GOF(RCX);
682 if (o == 4+ GOF(RDX) && sz == 4) return GOF(RDX);
683 if (o == 4+ GOF(RBX) && sz == 4) return GOF(RBX);
684
685 VG_(printf)("MC_(get_otrack_shadow_offset)(amd64)(off=%d,sz=%d)\n",
686 offset,szB);
687 tl_assert(0);
688# undef GOF
689# undef SZB
690
691 /* --------------------- x86 --------------------- */
692
693# elif defined(VGA_x86)
694
695# define GOF(_fieldname) \
696 (offsetof(VexGuestX86State,guest_##_fieldname))
697# define SZB(_fieldname) \
698 (sizeof(((VexGuestX86State*)0)->guest_##_fieldname))
699
700 Int o = offset;
701 Int sz = szB;
702 Bool is124 = sz == 4 || sz == 2 || sz == 1;
703 tl_assert(sz > 0);
704 tl_assert(host_is_little_endian());
705
706 if (o == GOF(EAX) && is124) return o;
707 if (o == GOF(ECX) && is124) return o;
708 if (o == GOF(EDX) && is124) return o;
709 if (o == GOF(EBX) && is124) return o;
710 if (o == GOF(ESP) && is124) return o;
711 if (o == GOF(EBP) && is124) return o;
712 if (o == GOF(ESI) && is124) return o;
713 if (o == GOF(EDI) && is124) return o;
714
715 if (o == GOF(CC_DEP1) && sz == 4) return o;
716 if (o == GOF(CC_DEP2) && sz == 4) return o;
717
718 if (o == GOF(CC_OP) && sz == 4) return -1; /* slot used for %AH */
719 if (o == GOF(CC_NDEP) && sz == 4) return -1; /* slot used for %BH */
720 if (o == GOF(DFLAG) && sz == 4) return -1; /* slot used for %CH */
721 if (o == GOF(EIP) && sz == 4) return -1; /* slot unused */
sewardj71633b12009-03-30 02:27:29 +0000[diff] [blame]722 if (o == GOF(IP_AT_SYSCALL) && sz == 4) return -1; /* slot unused */
sewardj7cf4e6b2008-05-01 20:24:26 +0000[diff] [blame]723 if (o == GOF(IDFLAG) && sz == 4) return -1; /* slot used for %DH */
724 if (o == GOF(ACFLAG) && sz == 4) return -1; /* slot unused */
sewardj1146ae62014-05-04 10:54:08 +0000[diff] [blame]725 if (o == GOF(CMSTART) && sz == 4) return -1; /* slot unused */
726 if (o == GOF(CMLEN) && sz == 4) return -1; /* slot unused */
sewardj5575f052011-01-28 00:53:37 +0000[diff] [blame]727 if (o == GOF(NRADDR) && sz == 4) return -1; /* slot unused */
sewardj7cf4e6b2008-05-01 20:24:26 +0000[diff] [blame]728
729 /* Treat %AH, %BH, %CH, %DH as independent registers. To do this
730 requires finding 4 unused 32-bit slots in the second-shadow
731 guest state, respectively: CC_OP CC_NDEP DFLAG IDFLAG since none
732 of those are tracked. */
733 tl_assert(SZB(CC_OP) == 4);
734 tl_assert(SZB(CC_NDEP) == 4);
735 tl_assert(SZB(DFLAG) == 4);
736 tl_assert(SZB(IDFLAG) == 4);
737 if (o == 1+ GOF(EAX) && szB == 1) return GOF(CC_OP);
738 if (o == 1+ GOF(EBX) && szB == 1) return GOF(CC_NDEP);
739 if (o == 1+ GOF(ECX) && szB == 1) return GOF(DFLAG);
740 if (o == 1+ GOF(EDX) && szB == 1) return GOF(IDFLAG);
741
742 /* skip XMM and FP admin stuff */
743 if (o == GOF(SSEROUND) && szB == 4) return -1;
744 if (o == GOF(FTOP) && szB == 4) return -1;
745 if (o == GOF(FPROUND) && szB == 4) return -1;
florian2e497412012-08-26 03:22:09 +0000[diff] [blame]746 if (o == GOF(EMNOTE) && szB == 4) return -1;
sewardj7cf4e6b2008-05-01 20:24:26 +0000[diff] [blame]747 if (o == GOF(FC3210) && szB == 4) return -1;
748
749 /* XMM registers */
750 if (o >= GOF(XMM0) && o+sz <= GOF(XMM0)+SZB(XMM0)) return GOF(XMM0);
751 if (o >= GOF(XMM1) && o+sz <= GOF(XMM1)+SZB(XMM1)) return GOF(XMM1);
752 if (o >= GOF(XMM2) && o+sz <= GOF(XMM2)+SZB(XMM2)) return GOF(XMM2);
753 if (o >= GOF(XMM3) && o+sz <= GOF(XMM3)+SZB(XMM3)) return GOF(XMM3);
754 if (o >= GOF(XMM4) && o+sz <= GOF(XMM4)+SZB(XMM4)) return GOF(XMM4);
755 if (o >= GOF(XMM5) && o+sz <= GOF(XMM5)+SZB(XMM5)) return GOF(XMM5);
756 if (o >= GOF(XMM6) && o+sz <= GOF(XMM6)+SZB(XMM6)) return GOF(XMM6);
757 if (o >= GOF(XMM7) && o+sz <= GOF(XMM7)+SZB(XMM7)) return GOF(XMM7);
758
759 /* MMX accesses to FP regs. Need to allow for 32-bit references
760 due to dirty helpers for frstor etc, which reference the entire
761 64-byte block in one go. */
762 if (o >= GOF(FPREG[0])
763 && o+sz <= GOF(FPREG[0])+SZB(FPREG[0])) return GOF(FPREG[0]);
764 if (o >= GOF(FPREG[1])
765 && o+sz <= GOF(FPREG[1])+SZB(FPREG[1])) return GOF(FPREG[1]);
766 if (o >= GOF(FPREG[2])
767 && o+sz <= GOF(FPREG[2])+SZB(FPREG[2])) return GOF(FPREG[2]);
768 if (o >= GOF(FPREG[3])
769 && o+sz <= GOF(FPREG[3])+SZB(FPREG[3])) return GOF(FPREG[3]);
770 if (o >= GOF(FPREG[4])
771 && o+sz <= GOF(FPREG[4])+SZB(FPREG[4])) return GOF(FPREG[4]);
772 if (o >= GOF(FPREG[5])
773 && o+sz <= GOF(FPREG[5])+SZB(FPREG[5])) return GOF(FPREG[5]);
774 if (o >= GOF(FPREG[6])
775 && o+sz <= GOF(FPREG[6])+SZB(FPREG[6])) return GOF(FPREG[6]);
776 if (o >= GOF(FPREG[7])
777 && o+sz <= GOF(FPREG[7])+SZB(FPREG[7])) return GOF(FPREG[7]);
778
779 /* skip %GS and other segment related stuff. We could shadow
780 guest_LDT and guest_GDT, although it seems pointless.
781 guest_CS .. guest_SS are too small to shadow directly and it
782 also seems pointless to shadow them indirectly (that is, in
783 the style of %AH .. %DH). */
784 if (o == GOF(CS) && sz == 2) return -1;
785 if (o == GOF(DS) && sz == 2) return -1;
786 if (o == GOF(ES) && sz == 2) return -1;
787 if (o == GOF(FS) && sz == 2) return -1;
788 if (o == GOF(GS) && sz == 2) return -1;
789 if (o == GOF(SS) && sz == 2) return -1;
790 if (o == GOF(LDT) && sz == 4) return -1;
791 if (o == GOF(GDT) && sz == 4) return -1;
792
793 VG_(printf)("MC_(get_otrack_shadow_offset)(x86)(off=%d,sz=%d)\n",
794 offset,szB);
795 tl_assert(0);
796# undef GOF
797# undef SZB
798
sewardjb5b87402011-03-07 16:05:35 +0000[diff] [blame]799 /* -------------------- s390x -------------------- */
800
801# elif defined(VGA_s390x)
802# define GOF(_fieldname) \
803 (offsetof(VexGuestS390XState,guest_##_fieldname))
804 Int o = offset;
805 Int sz = szB;
806 tl_assert(sz > 0);
807 tl_assert(host_is_big_endian());
808
809 /* no matter what byte(s) we change, we have changed the full 8 byte value
810 and need to track this change for the whole register */
811 if (o >= GOF(r0) && sz <= 8 && o <= (GOF(r15) + 8 - sz))
812 return GOF(r0) + ((o-GOF(r0)) & -8) ;
813
814
815 /* fprs are accessed 4 or 8 byte at once. Again, we track that change for
816 the full register */
817 if ((sz == 8 || sz == 4) && o >= GOF(f0) && o <= GOF(f15)+8-sz)
818 return GOF(f0) + ((o-GOF(f0)) & -8) ;
819
820 /* access registers are accessed 4 bytes at once */
821 if (sz == 4 && o >= GOF(a0) && o <= GOF(a15))
florian30e2d652012-09-03 17:34:22 +0000[diff] [blame]822 return o;
sewardjb5b87402011-03-07 16:05:35 +0000[diff] [blame]823
824 /* we access the guest counter either fully or one of the 4byte words */
825 if (o == GOF(counter) && (sz == 8 || sz ==4))
826 return o;
827 if (o == GOF(counter) + 4 && sz == 4)
828 return o;
829
florian30e2d652012-09-03 17:34:22 +0000[diff] [blame]830 if (o == GOF(EMNOTE) && sz == 4) return -1;
831
832 if (o == GOF(CC_OP) && sz == 8) return -1;
florian234955d2013-05-31 15:44:06 +0000[diff] [blame]833 /* We access CC_DEP1 either fully or bits [0:31] */
834 if (o == GOF(CC_DEP1) && (sz == 8 || sz ==4))
835 return o;
florian30e2d652012-09-03 17:34:22 +0000[diff] [blame]836 if (o == GOF(CC_DEP2) && sz == 8) return o;
837 if (o == GOF(CC_NDEP) && sz == 8) return -1;
sewardj1146ae62014-05-04 10:54:08 +0000[diff] [blame]838 if (o == GOF(CMSTART) && sz == 8) return -1;
839 if (o == GOF(CMLEN) && sz == 8) return -1;
florian30e2d652012-09-03 17:34:22 +0000[diff] [blame]840 if (o == GOF(NRADDR) && sz == 8) return -1;
841 if (o == GOF(IP_AT_SYSCALL) && sz == 8) return -1;
florian4fea8402012-09-11 23:06:02 +0000[diff] [blame]842 if (o == GOF(fpc) && sz == 4) return -1;
florian30e2d652012-09-03 17:34:22 +0000[diff] [blame]843 if (o == GOF(IA) && sz == 8) return -1;
844 if (o == (GOF(IA) + 4) && sz == 4) return -1;
845 if (o == GOF(SYSNO) && sz == 8) return -1;
sewardjb5b87402011-03-07 16:05:35 +0000[diff] [blame]846 VG_(printf)("MC_(get_otrack_shadow_offset)(s390x)(off=%d,sz=%d)\n",
847 offset,szB);
848 tl_assert(0);
849# undef GOF
850
851
sewardj59570ff2010-01-01 11:59:33 +0000[diff] [blame]852 /* --------------------- arm --------------------- */
853
854# elif defined(VGA_arm)
855
856# define GOF(_fieldname) \
857 (offsetof(VexGuestARMState,guest_##_fieldname))
858# define SZB(_fieldname) \
859 (sizeof(((VexGuestARMState*)0)->guest_##_fieldname))
860
861 Int o = offset;
862 Int sz = szB;
863 tl_assert(sz > 0);
864 tl_assert(host_is_little_endian());
865
866 if (o == GOF(R0) && sz == 4) return o;
867 if (o == GOF(R1) && sz == 4) return o;
868 if (o == GOF(R2) && sz == 4) return o;
869 if (o == GOF(R3) && sz == 4) return o;
870 if (o == GOF(R4) && sz == 4) return o;
871 if (o == GOF(R5) && sz == 4) return o;
872 if (o == GOF(R6) && sz == 4) return o;
873 if (o == GOF(R7) && sz == 4) return o;
874 if (o == GOF(R8) && sz == 4) return o;
875 if (o == GOF(R9) && sz == 4) return o;
876 if (o == GOF(R10) && sz == 4) return o;
877 if (o == GOF(R11) && sz == 4) return o;
878 if (o == GOF(R12) && sz == 4) return o;
879 if (o == GOF(R13) && sz == 4) return o;
880 if (o == GOF(R14) && sz == 4) return o;
881
882 /* EAZG: These may be completely wrong. */
sewardjca9054a2010-08-22 12:16:25 +0000[diff] [blame]883 if (o == GOF(R15T) && sz == 4) return -1; /* slot unused */
sewardj59570ff2010-01-01 11:59:33 +0000[diff] [blame]884 if (o == GOF(CC_OP) && sz == 4) return -1; /* slot unused */
885
886 if (o == GOF(CC_DEP1) && sz == 4) return o;
887 if (o == GOF(CC_DEP2) && sz == 4) return o;
888
889 if (o == GOF(CC_NDEP) && sz == 4) return -1; /* slot unused */
890
sewardjca9054a2010-08-22 12:16:25 +0000[diff] [blame]891 if (o == GOF(QFLAG32) && sz == 4) return o;
892
sewardj6fede422010-09-22 22:27:41 +0000[diff] [blame]893 if (o == GOF(GEFLAG0) && sz == 4) return o;
894 if (o == GOF(GEFLAG1) && sz == 4) return o;
895 if (o == GOF(GEFLAG2) && sz == 4) return o;
896 if (o == GOF(GEFLAG3) && sz == 4) return o;
897
sewardj59570ff2010-01-01 11:59:33 +0000[diff] [blame]898 //if (o == GOF(SYSCALLNO) && sz == 4) return -1; /* slot unused */
899 //if (o == GOF(CC) && sz == 4) return -1; /* slot unused */
florian2e497412012-08-26 03:22:09 +0000[diff] [blame]900 //if (o == GOF(EMNOTE) && sz == 4) return -1; /* slot unused */
sewardj1146ae62014-05-04 10:54:08 +0000[diff] [blame]901 //if (o == GOF(CMSTART) && sz == 4) return -1; /* slot unused */
sewardj59570ff2010-01-01 11:59:33 +0000[diff] [blame]902 //if (o == GOF(NRADDR) && sz == 4) return -1; /* slot unused */
903
904 if (o == GOF(FPSCR) && sz == 4) return -1;
905 if (o == GOF(TPIDRURO) && sz == 4) return -1;
sewardjca9054a2010-08-22 12:16:25 +0000[diff] [blame]906 if (o == GOF(ITSTATE) && sz == 4) return -1;
sewardj59570ff2010-01-01 11:59:33 +0000[diff] [blame]907
sewardj8f6ec702010-09-29 21:40:44 +0000[diff] [blame]908 /* Accesses to F or D registers */
909 if (sz == 4 || sz == 8) {
910 if (o >= GOF(D0) && o+sz <= GOF(D0) +SZB(D0)) return GOF(D0);
911 if (o >= GOF(D1) && o+sz <= GOF(D1) +SZB(D1)) return GOF(D1);
912 if (o >= GOF(D2) && o+sz <= GOF(D2) +SZB(D2)) return GOF(D2);
913 if (o >= GOF(D3) && o+sz <= GOF(D3) +SZB(D3)) return GOF(D3);
914 if (o >= GOF(D4) && o+sz <= GOF(D4) +SZB(D4)) return GOF(D4);
915 if (o >= GOF(D5) && o+sz <= GOF(D5) +SZB(D5)) return GOF(D5);
916 if (o >= GOF(D6) && o+sz <= GOF(D6) +SZB(D6)) return GOF(D6);
917 if (o >= GOF(D7) && o+sz <= GOF(D7) +SZB(D7)) return GOF(D7);
918 if (o >= GOF(D8) && o+sz <= GOF(D8) +SZB(D8)) return GOF(D8);
919 if (o >= GOF(D9) && o+sz <= GOF(D9) +SZB(D9)) return GOF(D9);
920 if (o >= GOF(D10) && o+sz <= GOF(D10)+SZB(D10)) return GOF(D10);
921 if (o >= GOF(D11) && o+sz <= GOF(D11)+SZB(D11)) return GOF(D11);
922 if (o >= GOF(D12) && o+sz <= GOF(D12)+SZB(D12)) return GOF(D12);
923 if (o >= GOF(D13) && o+sz <= GOF(D13)+SZB(D13)) return GOF(D13);
924 if (o >= GOF(D14) && o+sz <= GOF(D14)+SZB(D14)) return GOF(D14);
925 if (o >= GOF(D15) && o+sz <= GOF(D15)+SZB(D15)) return GOF(D15);
926 if (o >= GOF(D16) && o+sz <= GOF(D16)+SZB(D16)) return GOF(D16);
927 if (o >= GOF(D17) && o+sz <= GOF(D17)+SZB(D17)) return GOF(D17);
928 if (o >= GOF(D18) && o+sz <= GOF(D18)+SZB(D18)) return GOF(D18);
929 if (o >= GOF(D19) && o+sz <= GOF(D19)+SZB(D19)) return GOF(D19);
930 if (o >= GOF(D20) && o+sz <= GOF(D20)+SZB(D20)) return GOF(D20);
931 if (o >= GOF(D21) && o+sz <= GOF(D21)+SZB(D21)) return GOF(D21);
932 if (o >= GOF(D22) && o+sz <= GOF(D22)+SZB(D22)) return GOF(D22);
933 if (o >= GOF(D23) && o+sz <= GOF(D23)+SZB(D23)) return GOF(D23);
934 if (o >= GOF(D24) && o+sz <= GOF(D24)+SZB(D24)) return GOF(D24);
935 if (o >= GOF(D25) && o+sz <= GOF(D25)+SZB(D25)) return GOF(D25);
936 if (o >= GOF(D26) && o+sz <= GOF(D26)+SZB(D26)) return GOF(D26);
937 if (o >= GOF(D27) && o+sz <= GOF(D27)+SZB(D27)) return GOF(D27);
938 if (o >= GOF(D28) && o+sz <= GOF(D28)+SZB(D28)) return GOF(D28);
939 if (o >= GOF(D29) && o+sz <= GOF(D29)+SZB(D29)) return GOF(D29);
940 if (o >= GOF(D30) && o+sz <= GOF(D30)+SZB(D30)) return GOF(D30);
941 if (o >= GOF(D31) && o+sz <= GOF(D31)+SZB(D31)) return GOF(D31);
942 }
943
944 /* Accesses to Q registers */
945 if (sz == 16) {
946 if (o >= GOF(D0) && o+sz <= GOF(D0) +2*SZB(D0)) return GOF(D0); // Q0
947 if (o >= GOF(D2) && o+sz <= GOF(D2) +2*SZB(D2)) return GOF(D2); // Q1
948 if (o >= GOF(D4) && o+sz <= GOF(D4) +2*SZB(D4)) return GOF(D4); // Q2
949 if (o >= GOF(D6) && o+sz <= GOF(D6) +2*SZB(D6)) return GOF(D6); // Q3
950 if (o >= GOF(D8) && o+sz <= GOF(D8) +2*SZB(D8)) return GOF(D8); // Q4
951 if (o >= GOF(D10) && o+sz <= GOF(D10)+2*SZB(D10)) return GOF(D10); // Q5
952 if (o >= GOF(D12) && o+sz <= GOF(D12)+2*SZB(D12)) return GOF(D12); // Q6
953 if (o >= GOF(D14) && o+sz <= GOF(D14)+2*SZB(D14)) return GOF(D14); // Q7
954 if (o >= GOF(D16) && o+sz <= GOF(D16)+2*SZB(D16)) return GOF(D16); // Q8
955 if (o >= GOF(D18) && o+sz <= GOF(D18)+2*SZB(D18)) return GOF(D18); // Q9
956 if (o >= GOF(D20) && o+sz <= GOF(D20)+2*SZB(D20)) return GOF(D20); // Q10
957 if (o >= GOF(D22) && o+sz <= GOF(D22)+2*SZB(D22)) return GOF(D22); // Q11
958 if (o >= GOF(D24) && o+sz <= GOF(D24)+2*SZB(D24)) return GOF(D24); // Q12
959 if (o >= GOF(D26) && o+sz <= GOF(D26)+2*SZB(D26)) return GOF(D26); // Q13
960 if (o >= GOF(D28) && o+sz <= GOF(D28)+2*SZB(D28)) return GOF(D28); // Q14
961 if (o >= GOF(D30) && o+sz <= GOF(D30)+2*SZB(D30)) return GOF(D30); // Q15
962 }
sewardj59570ff2010-01-01 11:59:33 +0000[diff] [blame]963
sewardj1146ae62014-05-04 10:54:08 +0000[diff] [blame]964 if (o == GOF(CMSTART) && sz == 4) return -1;
965 if (o == GOF(CMLEN) && sz == 4) return -1;
sewardjb29b6492012-12-13 15:17:40 +0000[diff] [blame]966
sewardj59570ff2010-01-01 11:59:33 +0000[diff] [blame]967 VG_(printf)("MC_(get_otrack_shadow_offset)(arm)(off=%d,sz=%d)\n",
968 offset,szB);
969 tl_assert(0);
970# undef GOF
971# undef SZB
972
sewardjf0c12502014-01-12 12:54:00 +0000[diff] [blame]973 /* --------------------- arm64 --------------------- */
974
975# elif defined(VGA_arm64)
976
977# define GOF(_fieldname) \
978 (offsetof(VexGuestARM64State,guest_##_fieldname))
979# define SZB(_fieldname) \
980 (sizeof(((VexGuestARM64State*)0)->guest_##_fieldname))
981
sewardjda7e0462014-02-27 11:15:58 +0000[diff] [blame]982 Int o = offset;
983 Int sz = szB;
984 Bool is48 = sz == 8 || sz == 4;
985
sewardjf0c12502014-01-12 12:54:00 +0000[diff] [blame]986 tl_assert(sz > 0);
987 tl_assert(host_is_little_endian());
sewardjda7e0462014-02-27 11:15:58 +0000[diff] [blame]988
989 if (o == GOF(X0) && is48) return o;
990 if (o == GOF(X1) && is48) return o;
991 if (o == GOF(X2) && is48) return o;
992 if (o == GOF(X3) && is48) return o;
sewardj85d45142014-04-08 15:26:12 +0000[diff] [blame]993 if (o == GOF(X4) && is48) return o;
994 if (o == GOF(X5) && is48) return o;
995 if (o == GOF(X6) && is48) return o;
996 if (o == GOF(X7) && is48) return o;
997 if (o == GOF(X8) && is48) return o;
998 if (o == GOF(X9) && is48) return o;
999 if (o == GOF(X10) && is48) return o;
1000 if (o == GOF(X11) && is48) return o;
1001 if (o == GOF(X12) && is48) return o;
1002 if (o == GOF(X13) && is48) return o;
1003 if (o == GOF(X14) && is48) return o;
1004 if (o == GOF(X15) && is48) return o;
1005 if (o == GOF(X16) && is48) return o;
1006 if (o == GOF(X17) && is48) return o;
1007 if (o == GOF(X18) && is48) return o;
1008 if (o == GOF(X19) && is48) return o;
1009 if (o == GOF(X20) && is48) return o;
1010 if (o == GOF(X21) && is48) return o;
1011 if (o == GOF(X22) && is48) return o;
1012 if (o == GOF(X23) && is48) return o;
1013 if (o == GOF(X24) && is48) return o;
1014 if (o == GOF(X25) && is48) return o;
1015 if (o == GOF(X26) && is48) return o;
1016 if (o == GOF(X27) && is48) return o;
1017 if (o == GOF(X28) && is48) return o;
1018 if (o == GOF(X29) && is48) return o;
1019 if (o == GOF(X30) && is48) return o;
1020 if (o == GOF(XSP) && is48) return o;
1021
1022 if (o == GOF(PC) && is48) return -1; // untracked
1023 if (o == GOF(CC_DEP1) && sz == 8) return o;
1024 if (o == GOF(CC_DEP2) && sz == 8) return o;
1025
1026 if (o == GOF(CC_OP) && sz == 8) return -1; // untracked
1027 if (o == GOF(CC_NDEP) && sz == 8) return -1; // untracked
1028 if (o == GOF(TPIDR_EL0) && sz == 8) return -1; // untracked
1029
1030 if (o >= GOF(Q0) && o+sz <= GOF(Q0) +SZB(Q0)) return GOF(Q0);
1031 if (o >= GOF(Q1) && o+sz <= GOF(Q1) +SZB(Q1)) return GOF(Q1);
1032 if (o >= GOF(Q2) && o+sz <= GOF(Q2) +SZB(Q2)) return GOF(Q2);
1033 if (o >= GOF(Q3) && o+sz <= GOF(Q3) +SZB(Q3)) return GOF(Q3);
1034 if (o >= GOF(Q4) && o+sz <= GOF(Q4) +SZB(Q4)) return GOF(Q4);
1035 if (o >= GOF(Q5) && o+sz <= GOF(Q5) +SZB(Q5)) return GOF(Q5);
1036 if (o >= GOF(Q6) && o+sz <= GOF(Q6) +SZB(Q6)) return GOF(Q6);
1037 if (o >= GOF(Q7) && o+sz <= GOF(Q7) +SZB(Q7)) return GOF(Q7);
1038 if (o >= GOF(Q8) && o+sz <= GOF(Q8) +SZB(Q8)) return GOF(Q8);
1039 if (o >= GOF(Q9) && o+sz <= GOF(Q9) +SZB(Q9)) return GOF(Q9);
1040 if (o >= GOF(Q10) && o+sz <= GOF(Q10)+SZB(Q10)) return GOF(Q10);
1041 if (o >= GOF(Q11) && o+sz <= GOF(Q11)+SZB(Q11)) return GOF(Q11);
1042 if (o >= GOF(Q12) && o+sz <= GOF(Q12)+SZB(Q12)) return GOF(Q12);
1043 if (o >= GOF(Q13) && o+sz <= GOF(Q13)+SZB(Q13)) return GOF(Q13);
1044 if (o >= GOF(Q14) && o+sz <= GOF(Q14)+SZB(Q14)) return GOF(Q14);
1045 if (o >= GOF(Q15) && o+sz <= GOF(Q15)+SZB(Q15)) return GOF(Q15);
1046 if (o >= GOF(Q16) && o+sz <= GOF(Q16)+SZB(Q16)) return GOF(Q16);
1047 if (o >= GOF(Q17) && o+sz <= GOF(Q17)+SZB(Q17)) return GOF(Q17);
1048 if (o >= GOF(Q18) && o+sz <= GOF(Q18)+SZB(Q18)) return GOF(Q18);
1049 if (o >= GOF(Q19) && o+sz <= GOF(Q19)+SZB(Q19)) return GOF(Q19);
1050 if (o >= GOF(Q20) && o+sz <= GOF(Q20)+SZB(Q20)) return GOF(Q20);
1051 if (o >= GOF(Q21) && o+sz <= GOF(Q21)+SZB(Q21)) return GOF(Q21);
1052 if (o >= GOF(Q22) && o+sz <= GOF(Q22)+SZB(Q22)) return GOF(Q22);
1053 if (o >= GOF(Q23) && o+sz <= GOF(Q23)+SZB(Q23)) return GOF(Q23);
1054 if (o >= GOF(Q24) && o+sz <= GOF(Q24)+SZB(Q24)) return GOF(Q24);
1055 if (o >= GOF(Q25) && o+sz <= GOF(Q25)+SZB(Q25)) return GOF(Q25);
1056 if (o >= GOF(Q26) && o+sz <= GOF(Q26)+SZB(Q26)) return GOF(Q26);
1057 if (o >= GOF(Q27) && o+sz <= GOF(Q27)+SZB(Q27)) return GOF(Q27);
1058 if (o >= GOF(Q28) && o+sz <= GOF(Q28)+SZB(Q28)) return GOF(Q28);
1059 if (o >= GOF(Q29) && o+sz <= GOF(Q29)+SZB(Q29)) return GOF(Q29);
1060 if (o >= GOF(Q30) && o+sz <= GOF(Q30)+SZB(Q30)) return GOF(Q30);
1061 if (o >= GOF(Q31) && o+sz <= GOF(Q31)+SZB(Q31)) return GOF(Q31);
1062
1063 if (o == GOF(FPCR) && sz == 4) return -1; // untracked
sewardjc69477a2014-06-28 22:12:34 +0000[diff] [blame]1064 if (o == GOF(QCFLAG) && sz == 16) return o;
sewardjf0c12502014-01-12 12:54:00 +0000[diff] [blame]1065
sewardj1146ae62014-05-04 10:54:08 +0000[diff] [blame]1066 if (o == GOF(CMSTART) && sz == 8) return -1; // untracked
1067 if (o == GOF(CMLEN) && sz == 8) return -1; // untracked
sewardjc76d0e52014-05-03 21:22:55 +0000[diff] [blame]1068
sewardjf0c12502014-01-12 12:54:00 +0000[diff] [blame]1069 VG_(printf)("MC_(get_otrack_shadow_offset)(arm64)(off=%d,sz=%d)\n",
1070 offset,szB);
1071 tl_assert(0);
1072# undef GOF
1073# undef SZB
1074
sewardj5db15402012-06-07 09:13:21 +0000[diff] [blame]1075 /* --------------------- mips32 --------------------- */
1076
1077# elif defined(VGA_mips32)
1078
1079# define GOF(_fieldname) \
1080 (offsetof(VexGuestMIPS32State,guest_##_fieldname))
1081# define SZB(_fieldname) \
1082 (sizeof(((VexGuestMIPS32State*)0)->guest_##_fieldname))
1083
1084 Int o = offset;
1085 Int sz = szB;
1086 tl_assert(sz > 0);
1087# if defined (VG_LITTLEENDIAN)
1088 tl_assert(host_is_little_endian());
1089# elif defined (VG_BIGENDIAN)
1090 tl_assert(host_is_big_endian());
1091# else
1092# error "Unknown endianness"
1093# endif
1094
1095 if (o == GOF(r0) && sz == 4) return o;
1096 if (o == GOF(r1) && sz == 4) return o;
1097 if (o == GOF(r2) && sz == 4) return o;
1098 if (o == GOF(r3) && sz == 4) return o;
1099 if (o == GOF(r4) && sz == 4) return o;
1100 if (o == GOF(r5) && sz == 4) return o;
1101 if (o == GOF(r6) && sz == 4) return o;
1102 if (o == GOF(r7) && sz == 4) return o;
1103 if (o == GOF(r8) && sz == 4) return o;
1104 if (o == GOF(r9) && sz == 4) return o;
1105 if (o == GOF(r10) && sz == 4) return o;
1106 if (o == GOF(r11) && sz == 4) return o;
1107 if (o == GOF(r12) && sz == 4) return o;
1108 if (o == GOF(r13) && sz == 4) return o;
1109 if (o == GOF(r14) && sz == 4) return o;
1110 if (o == GOF(r15) && sz == 4) return o;
1111 if (o == GOF(r16) && sz == 4) return o;
1112 if (o == GOF(r17) && sz == 4) return o;
1113 if (o == GOF(r18) && sz == 4) return o;
1114 if (o == GOF(r19) && sz == 4) return o;
1115 if (o == GOF(r20) && sz == 4) return o;
1116 if (o == GOF(r21) && sz == 4) return o;
1117 if (o == GOF(r22) && sz == 4) return o;
1118 if (o == GOF(r23) && sz == 4) return o;
1119 if (o == GOF(r24) && sz == 4) return o;
1120 if (o == GOF(r25) && sz == 4) return o;
1121 if (o == GOF(r26) && sz == 4) return o;
1122 if (o == GOF(r27) && sz == 4) return o;
1123 if (o == GOF(r28) && sz == 4) return o;
1124 if (o == GOF(r29) && sz == 4) return o;
1125 if (o == GOF(r30) && sz == 4) return o;
1126 if (o == GOF(r31) && sz == 4) return o;
1127 if (o == GOF(PC) && sz == 4) return -1; /* slot unused */
1128
1129 if (o == GOF(HI) && sz == 4) return o;
1130 if (o == GOF(LO) && sz == 4) return o;
1131
1132 if (o == GOF(FIR) && sz == 4) return -1; /* slot unused */
1133 if (o == GOF(FCCR) && sz == 4) return -1; /* slot unused */
1134 if (o == GOF(FEXR) && sz == 4) return -1; /* slot unused */
1135 if (o == GOF(FENR) && sz == 4) return -1; /* slot unused */
1136 if (o == GOF(FCSR) && sz == 4) return -1; /* slot unused */
1137 if (o == GOF(ULR) && sz == 4) return -1;
1138
florian2e497412012-08-26 03:22:09 +0000[diff] [blame]1139 if (o == GOF(EMNOTE) && sz == 4) return -1; /* slot unused */
sewardj1146ae62014-05-04 10:54:08 +0000[diff] [blame]1140 if (o == GOF(CMSTART) && sz == 4) return -1; /* slot unused */
1141 if (o == GOF(CMLEN) && sz == 4) return -1; /* slot unused */
sewardj5db15402012-06-07 09:13:21 +0000[diff] [blame]1142 if (o == GOF(NRADDR) && sz == 4) return -1; /* slot unused */
1143
1144 if (o >= GOF(f0) && o+sz <= GOF(f0) +SZB(f0)) return GOF(f0);
1145 if (o >= GOF(f1) && o+sz <= GOF(f1) +SZB(f1)) return GOF(f1);
1146 if (o >= GOF(f2) && o+sz <= GOF(f2) +SZB(f2)) return GOF(f2);
1147 if (o >= GOF(f3) && o+sz <= GOF(f3) +SZB(f3)) return GOF(f3);
1148 if (o >= GOF(f4) && o+sz <= GOF(f4) +SZB(f4)) return GOF(f4);
1149 if (o >= GOF(f5) && o+sz <= GOF(f5) +SZB(f5)) return GOF(f5);
1150 if (o >= GOF(f6) && o+sz <= GOF(f6) +SZB(f6)) return GOF(f6);
1151 if (o >= GOF(f7) && o+sz <= GOF(f7) +SZB(f7)) return GOF(f7);
1152 if (o >= GOF(f8) && o+sz <= GOF(f8) +SZB(f8)) return GOF(f8);
1153 if (o >= GOF(f9) && o+sz <= GOF(f9) +SZB(f9)) return GOF(f9);
1154 if (o >= GOF(f10) && o+sz <= GOF(f10)+SZB(f10)) return GOF(f10);
1155 if (o >= GOF(f11) && o+sz <= GOF(f11)+SZB(f11)) return GOF(f11);
1156 if (o >= GOF(f12) && o+sz <= GOF(f12)+SZB(f12)) return GOF(f12);
1157 if (o >= GOF(f13) && o+sz <= GOF(f13)+SZB(f13)) return GOF(f13);
1158 if (o >= GOF(f14) && o+sz <= GOF(f14)+SZB(f14)) return GOF(f14);
1159 if (o >= GOF(f15) && o+sz <= GOF(f15)+SZB(f15)) return GOF(f15);
1160
1161 if (o >= GOF(f16) && o+sz <= GOF(f16)+SZB(f16)) return GOF(f16);
1162 if (o >= GOF(f17) && o+sz <= GOF(f17) +SZB(f17)) return GOF(f17);
1163 if (o >= GOF(f18) && o+sz <= GOF(f18) +SZB(f18)) return GOF(f18);
1164 if (o >= GOF(f19) && o+sz <= GOF(f19) +SZB(f19)) return GOF(f19);
1165 if (o >= GOF(f20) && o+sz <= GOF(f20) +SZB(f20)) return GOF(f20);
1166 if (o >= GOF(f21) && o+sz <= GOF(f21) +SZB(f21)) return GOF(f21);
1167 if (o >= GOF(f22) && o+sz <= GOF(f22) +SZB(f22)) return GOF(f22);
1168 if (o >= GOF(f23) && o+sz <= GOF(f23) +SZB(f23)) return GOF(f23);
1169 if (o >= GOF(f24) && o+sz <= GOF(f24) +SZB(f24)) return GOF(f24);
1170 if (o >= GOF(f25) && o+sz <= GOF(f25) +SZB(f25)) return GOF(f25);
1171 if (o >= GOF(f26) && o+sz <= GOF(f26)+SZB(f26)) return GOF(f26);
1172 if (o >= GOF(f27) && o+sz <= GOF(f27)+SZB(f27)) return GOF(f27);
1173 if (o >= GOF(f28) && o+sz <= GOF(f28)+SZB(f28)) return GOF(f28);
1174 if (o >= GOF(f29) && o+sz <= GOF(f29)+SZB(f29)) return GOF(f29);
1175 if (o >= GOF(f30) && o+sz <= GOF(f30)+SZB(f30)) return GOF(f30);
1176 if (o >= GOF(f31) && o+sz <= GOF(f31)+SZB(f31)) return GOF(f31);
1177
dejanj5f790e82013-07-25 08:22:08 +0000[diff] [blame]1178 /* Slot unused. */
1179 if ((o > GOF(NRADDR)) && (o <= GOF(NRADDR) +12 )) return -1;
1180
1181 /* MIPS32 DSP ASE(r2) specific registers. */
1182 if (o == GOF(DSPControl) && sz == 4) return o;
1183 if (o == GOF(ac0) && sz == 8) return o;
1184 if (o == GOF(ac1) && sz == 8) return o;
1185 if (o == GOF(ac2) && sz == 8) return o;
1186 if (o == GOF(ac3) && sz == 8) return o;
sewardj5db15402012-06-07 09:13:21 +0000[diff] [blame]1187
1188 VG_(printf)("MC_(get_otrack_shadow_offset)(mips)(off=%d,sz=%d)\n",
1189 offset,szB);
1190 tl_assert(0);
1191# undef GOF
1192# undef SZB
1193
petarj4df0bfc2013-02-27 23:17:33 +0000[diff] [blame]1194 /* --------------------- mips64 --------------------- */
1195
1196# elif defined(VGA_mips64)
1197
1198# define GOF(_fieldname) \
1199 (offsetof(VexGuestMIPS64State,guest_##_fieldname))
1200# define SZB(_fieldname) \
1201 (sizeof(((VexGuestMIPS64State*)0)->guest_##_fieldname))
1202
1203 Int o = offset;
1204 Int sz = szB;
1205 tl_assert(sz > 0);
1206#if defined (VG_LITTLEENDIAN)
1207 tl_assert(host_is_little_endian());
1208#elif defined (VG_BIGENDIAN)
1209 tl_assert(host_is_big_endian());
1210#endif
1211
1212 if (o >= GOF(r0) && sz <= 8 && o <= (GOF(r31) + 8 - sz))
1213 return GOF(r0) + ((o-GOF(r0)) & -8) ;
1214
1215 if (o == GOF(PC) && sz == 8) return -1; /* slot unused */
1216
1217 if (o == GOF(HI) && sz == 8) return o;
1218 if (o == GOF(LO) && sz == 8) return o;
1219
1220 if (o == GOF(FIR) && sz == 4) return -1; /* slot unused */
1221 if (o == GOF(FCCR) && sz == 4) return -1; /* slot unused */
1222 if (o == GOF(FEXR) && sz == 4) return -1; /* slot unused */
1223 if (o == GOF(FENR) && sz == 4) return -1; /* slot unused */
1224 if (o == GOF(FCSR) && sz == 4) return -1; /* slot unused */
1225 if (o == GOF(ULR) && sz == 8) return o;
1226
1227 if (o == GOF(EMNOTE) && sz == 4) return -1; /* slot unused */
sewardj1146ae62014-05-04 10:54:08 +0000[diff] [blame]1228 if (o == GOF(CMSTART) && sz == 4) return -1; /* slot unused */
1229 if (o == GOF(CMLEN) && sz == 4) return -1; /* slot unused */
petarj4df0bfc2013-02-27 23:17:33 +0000[diff] [blame]1230 if (o == GOF(NRADDR) && sz == 4) return -1; /* slot unused */
1231
1232 if (o >= GOF(f0) && o+sz <= GOF(f0) +SZB(f0)) return GOF(f0);
1233 if (o >= GOF(f1) && o+sz <= GOF(f1) +SZB(f1)) return GOF(f1);
1234 if (o >= GOF(f2) && o+sz <= GOF(f2) +SZB(f2)) return GOF(f2);
1235 if (o >= GOF(f3) && o+sz <= GOF(f3) +SZB(f3)) return GOF(f3);
1236 if (o >= GOF(f4) && o+sz <= GOF(f4) +SZB(f4)) return GOF(f4);
1237 if (o >= GOF(f5) && o+sz <= GOF(f5) +SZB(f5)) return GOF(f5);
1238 if (o >= GOF(f6) && o+sz <= GOF(f6) +SZB(f6)) return GOF(f6);
1239 if (o >= GOF(f7) && o+sz <= GOF(f7) +SZB(f7)) return GOF(f7);
1240 if (o >= GOF(f8) && o+sz <= GOF(f8) +SZB(f8)) return GOF(f8);
1241 if (o >= GOF(f9) && o+sz <= GOF(f9) +SZB(f9)) return GOF(f9);
1242 if (o >= GOF(f10) && o+sz <= GOF(f10)+SZB(f10)) return GOF(f10);
1243 if (o >= GOF(f11) && o+sz <= GOF(f11)+SZB(f11)) return GOF(f11);
1244 if (o >= GOF(f12) && o+sz <= GOF(f12)+SZB(f12)) return GOF(f12);
1245 if (o >= GOF(f13) && o+sz <= GOF(f13)+SZB(f13)) return GOF(f13);
1246 if (o >= GOF(f14) && o+sz <= GOF(f14)+SZB(f14)) return GOF(f14);
1247 if (o >= GOF(f15) && o+sz <= GOF(f15)+SZB(f15)) return GOF(f15);
1248 if (o >= GOF(f16) && o+sz <= GOF(f16)+SZB(f16)) return GOF(f16);
1249 if (o >= GOF(f17) && o+sz <= GOF(f17)+SZB(f17)) return GOF(f17);
1250 if (o >= GOF(f18) && o+sz <= GOF(f18)+SZB(f18)) return GOF(f18);
1251 if (o >= GOF(f19) && o+sz <= GOF(f19)+SZB(f19)) return GOF(f19);
1252 if (o >= GOF(f20) && o+sz <= GOF(f20)+SZB(f20)) return GOF(f20);
1253 if (o >= GOF(f21) && o+sz <= GOF(f21)+SZB(f21)) return GOF(f21);
1254 if (o >= GOF(f22) && o+sz <= GOF(f22)+SZB(f22)) return GOF(f22);
1255 if (o >= GOF(f23) && o+sz <= GOF(f23)+SZB(f23)) return GOF(f23);
1256 if (o >= GOF(f24) && o+sz <= GOF(f24)+SZB(f24)) return GOF(f24);
1257 if (o >= GOF(f25) && o+sz <= GOF(f25)+SZB(f25)) return GOF(f25);
1258 if (o >= GOF(f26) && o+sz <= GOF(f26)+SZB(f26)) return GOF(f26);
1259 if (o >= GOF(f27) && o+sz <= GOF(f27)+SZB(f27)) return GOF(f27);
1260 if (o >= GOF(f28) && o+sz <= GOF(f28)+SZB(f28)) return GOF(f28);
1261 if (o >= GOF(f29) && o+sz <= GOF(f29)+SZB(f29)) return GOF(f29);
1262 if (o >= GOF(f30) && o+sz <= GOF(f30)+SZB(f30)) return GOF(f30);
1263 if (o >= GOF(f31) && o+sz <= GOF(f31)+SZB(f31)) return GOF(f31);
1264
1265 if ((o > GOF(NRADDR)) && (o <= GOF(NRADDR) +12 )) return -1;
1266
1267 VG_(printf)("MC_(get_otrack_shadow_offset)(mips)(off=%d,sz=%d)\n",
1268 offset,szB);
1269 tl_assert(0);
1270# undef GOF
1271# undef SZB
1272
sewardj7cf4e6b2008-05-01 20:24:26 +0000[diff] [blame]1273# else
1274# error "FIXME: not implemented for this architecture"
1275# endif
1276}
1277
1278
1279/* Let 'arr' describe an indexed reference to a guest state section
1280 (guest state array).
1281
1282 This function returns the corresponding guest state type to be used
1283 when indexing the corresponding array in the second shadow (origin
1284 tracking) area. If the array is not to be origin-tracked, return
1285 Ity_INVALID.
1286
1287 This function must agree with MC_(get_otrack_shadow_offset) above.
1288 See comments at the start of MC_(get_otrack_shadow_offset).
1289*/
1290IRType MC_(get_otrack_reg_array_equiv_int_type) ( IRRegArray* arr )
1291{
1292 /* -------------------- ppc64 -------------------- */
carllcae0cc22014-08-07 23:17:29 +0000[diff] [blame]1293# if defined(VGA_ppc64be) || defined(VGA_ppc64le)
sewardj7cf4e6b2008-05-01 20:24:26 +0000[diff] [blame]1294 /* The redir stack. */
1295 if (arr->base == offsetof(VexGuestPPC64State,guest_REDIR_STACK[0])
1296 && arr->elemTy == Ity_I64
1297 && arr->nElems == VEX_GUEST_PPC64_REDIR_STACK_SIZE)
1298 return Ity_I64;
1299
1300 VG_(printf)("get_reg_array_equiv_int_type(ppc64): unhandled: ");
1301 ppIRRegArray(arr);
1302 VG_(printf)("\n");
1303 tl_assert(0);
1304
1305 /* -------------------- ppc32 -------------------- */
1306# elif defined(VGA_ppc32)
1307 /* The redir stack. */
1308 if (arr->base == offsetof(VexGuestPPC32State,guest_REDIR_STACK[0])
1309 && arr->elemTy == Ity_I32
1310 && arr->nElems == VEX_GUEST_PPC32_REDIR_STACK_SIZE)
1311 return Ity_I32;
1312
1313 VG_(printf)("get_reg_array_equiv_int_type(ppc32): unhandled: ");
1314 ppIRRegArray(arr);
1315 VG_(printf)("\n");
1316 tl_assert(0);
1317
1318 /* -------------------- amd64 -------------------- */
1319# elif defined(VGA_amd64)
1320 /* Ignore the FP tag array - pointless to shadow, and in any case
1321 the elements are too small */
1322 if (arr->base == offsetof(VexGuestAMD64State,guest_FPTAG)
1323 && arr->elemTy == Ity_I8 && arr->nElems == 8)
1324 return Ity_INVALID;
1325
1326 /* The FP register array */
1327 if (arr->base == offsetof(VexGuestAMD64State,guest_FPREG[0])
1328 && arr->elemTy == Ity_F64 && arr->nElems == 8)
1329 return Ity_I64;
1330
1331 VG_(printf)("get_reg_array_equiv_int_type(amd64): unhandled: ");
1332 ppIRRegArray(arr);
1333 VG_(printf)("\n");
1334 tl_assert(0);
1335
1336 /* --------------------- x86 --------------------- */
1337# elif defined(VGA_x86)
1338 /* Ignore the FP tag array - pointless to shadow, and in any case
1339 the elements are too small */
1340 if (arr->base == offsetof(VexGuestX86State,guest_FPTAG)
1341 && arr->elemTy == Ity_I8 && arr->nElems == 8)
1342 return Ity_INVALID;
1343
1344 /* The FP register array */
1345 if (arr->base == offsetof(VexGuestX86State,guest_FPREG[0])
1346 && arr->elemTy == Ity_F64 && arr->nElems == 8)
1347 return Ity_I64;
1348
1349 VG_(printf)("get_reg_array_equiv_int_type(x86): unhandled: ");
1350 ppIRRegArray(arr);
1351 VG_(printf)("\n");
1352 tl_assert(0);
1353
sewardj59570ff2010-01-01 11:59:33 +0000[diff] [blame]1354 /* --------------------- arm --------------------- */
1355# elif defined(VGA_arm)
sewardj59570ff2010-01-01 11:59:33 +0000[diff] [blame]1356 VG_(printf)("get_reg_array_equiv_int_type(arm): unhandled: ");
1357 ppIRRegArray(arr);
1358 VG_(printf)("\n");
1359 tl_assert(0);
1360
sewardjf0c12502014-01-12 12:54:00 +0000[diff] [blame]1361 /* --------------------- arm64 --------------------- */
1362# elif defined(VGA_arm64)
1363 VG_(printf)("get_reg_array_equiv_int_type(arm64): unhandled: ");
1364 ppIRRegArray(arr);
1365 VG_(printf)("\n");
1366 tl_assert(0);
1367
sewardjb5b87402011-03-07 16:05:35 +0000[diff] [blame]1368 /* --------------------- s390x --------------------- */
1369# elif defined(VGA_s390x)
1370 /* Should never het here because s390x does not use Ist_PutI
1371 and Iex_GetI. */
1372 tl_assert(0);
sewardj5db15402012-06-07 09:13:21 +0000[diff] [blame]1373
1374/* --------------------- mips32 --------------------- */
1375# elif defined(VGA_mips32)
1376 VG_(printf)("get_reg_array_equiv_int_type(mips32): unhandled: ");
1377 ppIRRegArray(arr);
1378 VG_(printf)("\n");
1379 tl_assert(0);
1380
petarj4df0bfc2013-02-27 23:17:33 +0000[diff] [blame]1381 /* --------------------- mips64 --------------------- */
1382# elif defined(VGA_mips64)
1383 VG_(printf)("get_reg_array_equiv_int_type(mips64): unhandled: ");
1384 ppIRRegArray(arr);
1385 VG_(printf)("\n");
1386 tl_assert(0);
sewardj7cf4e6b2008-05-01 20:24:26 +0000[diff] [blame]1387# else
1388# error "FIXME: not implemented for this architecture"
1389# endif
1390}
1391
1392
1393/*--------------------------------------------------------------------*/
1394/*--- end mc_machine.c ---*/
1395/*--------------------------------------------------------------------*/