nethercote | b35a8b9 | 2004-09-11 16:45:27 +0000 | [diff] [blame] | 1 | |
| 2 | /*--------------------------------------------------------------------*/ |
njn | 528b07e | 2005-06-10 04:46:19 +0000 | [diff] [blame] | 3 | /*--- x86-specific definitions. cg-x86.c ---*/ |
nethercote | b35a8b9 | 2004-09-11 16:45:27 +0000 | [diff] [blame] | 4 | /*--------------------------------------------------------------------*/ |
| 5 | |
| 6 | /* |
| 7 | This file is part of Cachegrind, a Valgrind tool for cache |
| 8 | profiling programs. |
| 9 | |
sewardj | e4b0bf0 | 2006-06-05 23:21:15 +0000 | [diff] [blame] | 10 | Copyright (C) 2002-2006 Nicholas Nethercote |
njn | 2bc1012 | 2005-05-08 02:10:27 +0000 | [diff] [blame] | 11 | njn@valgrind.org |
nethercote | b35a8b9 | 2004-09-11 16:45:27 +0000 | [diff] [blame] | 12 | |
| 13 | This program is free software; you can redistribute it and/or |
| 14 | modify it under the terms of the GNU General Public License as |
| 15 | published by the Free Software Foundation; either version 2 of the |
| 16 | License, or (at your option) any later version. |
| 17 | |
| 18 | This program is distributed in the hope that it will be useful, but |
| 19 | WITHOUT ANY WARRANTY; without even the implied warranty of |
| 20 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
| 21 | General Public License for more details. |
| 22 | |
| 23 | You should have received a copy of the GNU General Public License |
| 24 | along with this program; if not, write to the Free Software |
| 25 | Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA |
| 26 | 02111-1307, USA. |
| 27 | |
| 28 | The GNU General Public License is contained in the file COPYING. |
| 29 | */ |
| 30 | |
njn | c7561b9 | 2005-06-19 01:24:32 +0000 | [diff] [blame] | 31 | #include "pub_tool_basics.h" |
njn | 6898086 | 2005-06-18 18:31:26 +0000 | [diff] [blame] | 32 | #include "pub_tool_cpuid.h" |
njn | 97405b2 | 2005-06-02 03:39:33 +0000 | [diff] [blame] | 33 | #include "pub_tool_libcbase.h" |
njn | f39e9a3 | 2005-06-12 02:43:17 +0000 | [diff] [blame] | 34 | #include "pub_tool_libcassert.h" |
njn | 36a20fa | 2005-06-03 03:08:39 +0000 | [diff] [blame] | 35 | #include "pub_tool_libcprint.h" |
njn | c7561b9 | 2005-06-19 01:24:32 +0000 | [diff] [blame] | 36 | |
nethercote | b35a8b9 | 2004-09-11 16:45:27 +0000 | [diff] [blame] | 37 | #include "cg_arch.h" |
| 38 | |
| 39 | // All CPUID info taken from sandpile.org/a32/cpuid.htm */ |
| 40 | // Probably only works for Intel and AMD chips, and probably only for some of |
| 41 | // them. |
| 42 | |
| 43 | static void micro_ops_warn(Int actual_size, Int used_size, Int line_size) |
| 44 | { |
| 45 | VG_(message)(Vg_DebugMsg, |
sewardj | c32ba46 | 2005-10-19 23:49:45 +0000 | [diff] [blame] | 46 | "warning: Pentium 4 with %d KB micro-op instruction trace cache", |
nethercote | b35a8b9 | 2004-09-11 16:45:27 +0000 | [diff] [blame] | 47 | actual_size); |
| 48 | VG_(message)(Vg_DebugMsg, |
sewardj | c32ba46 | 2005-10-19 23:49:45 +0000 | [diff] [blame] | 49 | " Simulating a %d KB I-cache with %d B lines", |
nethercote | b35a8b9 | 2004-09-11 16:45:27 +0000 | [diff] [blame] | 50 | used_size, line_size); |
| 51 | } |
| 52 | |
| 53 | /* Intel method is truly wretched. We have to do an insane indexing into an |
| 54 | * array of pre-defined configurations for various parts of the memory |
| 55 | * hierarchy. |
| 56 | */ |
| 57 | static |
| 58 | Int Intel_cache_info(Int level, cache_t* I1c, cache_t* D1c, cache_t* L2c) |
| 59 | { |
| 60 | UChar info[16]; |
| 61 | Int i, trials; |
| 62 | Bool L2_found = False; |
| 63 | |
| 64 | if (level < 2) { |
| 65 | VG_(message)(Vg_DebugMsg, |
| 66 | "warning: CPUID level < 2 for Intel processor (%d)", |
| 67 | level); |
| 68 | return -1; |
| 69 | } |
| 70 | |
| 71 | VG_(cpuid)(2, (Int*)&info[0], (Int*)&info[4], |
| 72 | (Int*)&info[8], (Int*)&info[12]); |
| 73 | trials = info[0] - 1; /* AL register - bits 0..7 of %eax */ |
| 74 | info[0] = 0x0; /* reset AL */ |
| 75 | |
| 76 | if (0 != trials) { |
| 77 | VG_(message)(Vg_DebugMsg, |
| 78 | "warning: non-zero CPUID trials for Intel processor (%d)", |
| 79 | trials); |
| 80 | return -1; |
| 81 | } |
| 82 | |
| 83 | for (i = 0; i < 16; i++) { |
| 84 | |
| 85 | switch (info[i]) { |
| 86 | |
| 87 | case 0x0: /* ignore zeros */ |
| 88 | break; |
| 89 | |
| 90 | /* TLB info, ignore */ |
| 91 | case 0x01: case 0x02: case 0x03: case 0x04: |
| 92 | case 0x50: case 0x51: case 0x52: case 0x5b: case 0x5c: case 0x5d: |
| 93 | case 0xb0: case 0xb3: |
| 94 | break; |
| 95 | |
| 96 | case 0x06: *I1c = (cache_t) { 8, 4, 32 }; break; |
| 97 | case 0x08: *I1c = (cache_t) { 16, 4, 32 }; break; |
| 98 | case 0x30: *I1c = (cache_t) { 32, 8, 64 }; break; |
| 99 | |
| 100 | case 0x0a: *D1c = (cache_t) { 8, 2, 32 }; break; |
| 101 | case 0x0c: *D1c = (cache_t) { 16, 4, 32 }; break; |
| 102 | case 0x2c: *D1c = (cache_t) { 32, 8, 64 }; break; |
| 103 | |
| 104 | /* IA-64 info -- panic! */ |
| 105 | case 0x10: case 0x15: case 0x1a: |
| 106 | case 0x88: case 0x89: case 0x8a: case 0x8d: |
| 107 | case 0x90: case 0x96: case 0x9b: |
njn | 6799325 | 2004-11-22 18:02:32 +0000 | [diff] [blame] | 108 | VG_(tool_panic)("IA-64 cache detected?!"); |
nethercote | b35a8b9 | 2004-09-11 16:45:27 +0000 | [diff] [blame] | 109 | |
| 110 | case 0x22: case 0x23: case 0x25: case 0x29: |
njn | 4fe4943 | 2005-08-16 02:30:24 +0000 | [diff] [blame] | 111 | VG_(message)(Vg_DebugMsg, "warning: L3 cache detected but ignored"); |
nethercote | b35a8b9 | 2004-09-11 16:45:27 +0000 | [diff] [blame] | 112 | break; |
| 113 | |
| 114 | /* These are sectored, whatever that means */ |
| 115 | case 0x39: *L2c = (cache_t) { 128, 4, 64 }; L2_found = True; break; |
| 116 | case 0x3c: *L2c = (cache_t) { 256, 4, 64 }; L2_found = True; break; |
| 117 | |
| 118 | /* If a P6 core, this means "no L2 cache". |
| 119 | If a P4 core, this means "no L3 cache". |
| 120 | We don't know what core it is, so don't issue a warning. To detect |
| 121 | a missing L2 cache, we use 'L2_found'. */ |
| 122 | case 0x40: |
| 123 | break; |
| 124 | |
| 125 | case 0x41: *L2c = (cache_t) { 128, 4, 32 }; L2_found = True; break; |
| 126 | case 0x42: *L2c = (cache_t) { 256, 4, 32 }; L2_found = True; break; |
| 127 | case 0x43: *L2c = (cache_t) { 512, 4, 32 }; L2_found = True; break; |
| 128 | case 0x44: *L2c = (cache_t) { 1024, 4, 32 }; L2_found = True; break; |
| 129 | case 0x45: *L2c = (cache_t) { 2048, 4, 32 }; L2_found = True; break; |
| 130 | |
| 131 | /* These are sectored, whatever that means */ |
nethercote | ac7ecd7 | 2004-10-13 11:30:14 +0000 | [diff] [blame] | 132 | case 0x60: *D1c = (cache_t) { 16, 8, 64 }; break; /* sectored */ |
nethercote | b35a8b9 | 2004-09-11 16:45:27 +0000 | [diff] [blame] | 133 | case 0x66: *D1c = (cache_t) { 8, 4, 64 }; break; /* sectored */ |
| 134 | case 0x67: *D1c = (cache_t) { 16, 4, 64 }; break; /* sectored */ |
| 135 | case 0x68: *D1c = (cache_t) { 32, 4, 64 }; break; /* sectored */ |
| 136 | |
| 137 | /* HACK ALERT: Instruction trace cache -- capacity is micro-ops based. |
| 138 | * conversion to byte size is a total guess; treat the 12K and 16K |
| 139 | * cases the same since the cache byte size must be a power of two for |
| 140 | * everything to work!. Also guessing 32 bytes for the line size... |
| 141 | */ |
| 142 | case 0x70: /* 12K micro-ops, 8-way */ |
| 143 | *I1c = (cache_t) { 16, 8, 32 }; |
| 144 | micro_ops_warn(12, 16, 32); |
| 145 | break; |
| 146 | case 0x71: /* 16K micro-ops, 8-way */ |
| 147 | *I1c = (cache_t) { 16, 8, 32 }; |
| 148 | micro_ops_warn(16, 16, 32); |
| 149 | break; |
| 150 | case 0x72: /* 32K micro-ops, 8-way */ |
| 151 | *I1c = (cache_t) { 32, 8, 32 }; |
| 152 | micro_ops_warn(32, 32, 32); |
| 153 | break; |
| 154 | |
| 155 | /* These are sectored, whatever that means */ |
| 156 | case 0x79: *L2c = (cache_t) { 128, 8, 64 }; L2_found = True; break; |
| 157 | case 0x7a: *L2c = (cache_t) { 256, 8, 64 }; L2_found = True; break; |
| 158 | case 0x7b: *L2c = (cache_t) { 512, 8, 64 }; L2_found = True; break; |
| 159 | case 0x7c: *L2c = (cache_t) { 1024, 8, 64 }; L2_found = True; break; |
njn | 8bc8582 | 2005-07-20 04:32:44 +0000 | [diff] [blame] | 160 | case 0x7d: *L2c = (cache_t) { 2048, 8, 64 }; L2_found = True; break; |
nethercote | b35a8b9 | 2004-09-11 16:45:27 +0000 | [diff] [blame] | 161 | case 0x7e: *L2c = (cache_t) { 256, 8, 128 }; L2_found = True; break; |
| 162 | |
| 163 | case 0x81: *L2c = (cache_t) { 128, 8, 32 }; L2_found = True; break; |
| 164 | case 0x82: *L2c = (cache_t) { 256, 8, 32 }; L2_found = True; break; |
| 165 | case 0x83: *L2c = (cache_t) { 512, 8, 32 }; L2_found = True; break; |
| 166 | case 0x84: *L2c = (cache_t) { 1024, 8, 32 }; L2_found = True; break; |
| 167 | case 0x85: *L2c = (cache_t) { 2048, 8, 32 }; L2_found = True; break; |
| 168 | case 0x86: *L2c = (cache_t) { 512, 4, 64 }; L2_found = True; break; |
| 169 | case 0x87: *L2c = (cache_t) { 1024, 8, 64 }; L2_found = True; break; |
| 170 | |
tom | 942d9ef | 2005-07-27 22:59:50 +0000 | [diff] [blame] | 171 | /* Ignore prefetch information */ |
| 172 | case 0xf0: case 0xf1: |
| 173 | break; |
| 174 | |
nethercote | b35a8b9 | 2004-09-11 16:45:27 +0000 | [diff] [blame] | 175 | default: |
| 176 | VG_(message)(Vg_DebugMsg, |
| 177 | "warning: Unknown Intel cache config value " |
| 178 | "(0x%x), ignoring", info[i]); |
| 179 | break; |
| 180 | } |
| 181 | } |
| 182 | |
| 183 | if (!L2_found) |
| 184 | VG_(message)(Vg_DebugMsg, |
| 185 | "warning: L2 cache not installed, ignore L2 results."); |
| 186 | |
| 187 | return 0; |
| 188 | } |
| 189 | |
| 190 | /* AMD method is straightforward, just extract appropriate bits from the |
| 191 | * result registers. |
| 192 | * |
| 193 | * Bits, for D1 and I1: |
| 194 | * 31..24 data L1 cache size in KBs |
| 195 | * 23..16 data L1 cache associativity (FFh=full) |
| 196 | * 15.. 8 data L1 cache lines per tag |
| 197 | * 7.. 0 data L1 cache line size in bytes |
| 198 | * |
| 199 | * Bits, for L2: |
| 200 | * 31..16 unified L2 cache size in KBs |
| 201 | * 15..12 unified L2 cache associativity (0=off, FFh=full) |
| 202 | * 11.. 8 unified L2 cache lines per tag |
| 203 | * 7.. 0 unified L2 cache line size in bytes |
| 204 | * |
| 205 | * #3 The AMD K7 processor's L2 cache must be configured prior to relying |
| 206 | * upon this information. (Whatever that means -- njn) |
| 207 | * |
| 208 | * Also, according to Cyrille Chepelov, Duron stepping A0 processors (model |
| 209 | * 0x630) have a bug and misreport their L2 size as 1KB (it's really 64KB), |
| 210 | * so we detect that. |
| 211 | * |
| 212 | * Returns 0 on success, non-zero on failure. |
| 213 | */ |
| 214 | static |
| 215 | Int AMD_cache_info(cache_t* I1c, cache_t* D1c, cache_t* L2c) |
| 216 | { |
| 217 | UInt ext_level; |
| 218 | UInt dummy, model; |
| 219 | UInt I1i, D1i, L2i; |
| 220 | |
| 221 | VG_(cpuid)(0x80000000, &ext_level, &dummy, &dummy, &dummy); |
| 222 | |
| 223 | if (0 == (ext_level & 0x80000000) || ext_level < 0x80000006) { |
| 224 | VG_(message)(Vg_UserMsg, |
| 225 | "warning: ext_level < 0x80000006 for AMD processor (0x%x)", |
| 226 | ext_level); |
| 227 | return -1; |
| 228 | } |
| 229 | |
| 230 | VG_(cpuid)(0x80000005, &dummy, &dummy, &D1i, &I1i); |
| 231 | VG_(cpuid)(0x80000006, &dummy, &dummy, &L2i, &dummy); |
| 232 | |
| 233 | VG_(cpuid)(0x1, &model, &dummy, &dummy, &dummy); |
| 234 | |
| 235 | /* Check for Duron bug */ |
| 236 | if (model == 0x630) { |
| 237 | VG_(message)(Vg_UserMsg, |
| 238 | "Buggy Duron stepping A0. Assuming L2 size=65536 bytes"); |
| 239 | L2i = (64 << 16) | (L2i & 0xffff); |
| 240 | } |
| 241 | |
| 242 | D1c->size = (D1i >> 24) & 0xff; |
| 243 | D1c->assoc = (D1i >> 16) & 0xff; |
| 244 | D1c->line_size = (D1i >> 0) & 0xff; |
| 245 | |
| 246 | I1c->size = (I1i >> 24) & 0xff; |
| 247 | I1c->assoc = (I1i >> 16) & 0xff; |
| 248 | I1c->line_size = (I1i >> 0) & 0xff; |
| 249 | |
| 250 | L2c->size = (L2i >> 16) & 0xffff; /* Nb: different bits used for L2 */ |
| 251 | L2c->assoc = (L2i >> 12) & 0xf; |
| 252 | L2c->line_size = (L2i >> 0) & 0xff; |
| 253 | |
| 254 | return 0; |
| 255 | } |
| 256 | |
nethercote | b35a8b9 | 2004-09-11 16:45:27 +0000 | [diff] [blame] | 257 | static |
| 258 | Int get_caches_from_CPUID(cache_t* I1c, cache_t* D1c, cache_t* L2c) |
| 259 | { |
sewardj | b5f6f51 | 2005-03-10 23:59:00 +0000 | [diff] [blame] | 260 | Int level, ret; |
nethercote | b35a8b9 | 2004-09-11 16:45:27 +0000 | [diff] [blame] | 261 | Char vendor_id[13]; |
nethercote | b35a8b9 | 2004-09-11 16:45:27 +0000 | [diff] [blame] | 262 | |
sewardj | b5f6f51 | 2005-03-10 23:59:00 +0000 | [diff] [blame] | 263 | if (!VG_(has_cpuid)()) { |
nethercote | b35a8b9 | 2004-09-11 16:45:27 +0000 | [diff] [blame] | 264 | VG_(message)(Vg_DebugMsg, "CPUID instruction not supported"); |
nethercote | b35a8b9 | 2004-09-11 16:45:27 +0000 | [diff] [blame] | 265 | return -1; |
| 266 | } |
tom | f4ed059 | 2005-04-02 17:30:19 +0000 | [diff] [blame] | 267 | |
sewardj | b5f6f51 | 2005-03-10 23:59:00 +0000 | [diff] [blame] | 268 | VG_(cpuid)(0, &level, (int*)&vendor_id[0], |
| 269 | (int*)&vendor_id[8], (int*)&vendor_id[4]); |
| 270 | vendor_id[12] = '\0'; |
nethercote | b35a8b9 | 2004-09-11 16:45:27 +0000 | [diff] [blame] | 271 | |
| 272 | if (0 == level) { |
| 273 | VG_(message)(Vg_DebugMsg, "CPUID level is 0, early Pentium?\n"); |
| 274 | return -1; |
| 275 | } |
| 276 | |
| 277 | /* Only handling Intel and AMD chips... no Cyrix, Transmeta, etc */ |
| 278 | if (0 == VG_(strcmp)(vendor_id, "GenuineIntel")) { |
| 279 | ret = Intel_cache_info(level, I1c, D1c, L2c); |
| 280 | |
| 281 | } else if (0 == VG_(strcmp)(vendor_id, "AuthenticAMD")) { |
| 282 | ret = AMD_cache_info(I1c, D1c, L2c); |
| 283 | |
| 284 | } else if (0 == VG_(strcmp)(vendor_id, "CentaurHauls")) { |
| 285 | /* Total kludge. Pretend to be a VIA Nehemiah. */ |
| 286 | D1c->size = 64; |
| 287 | D1c->assoc = 16; |
| 288 | D1c->line_size = 16; |
| 289 | I1c->size = 64; |
| 290 | I1c->assoc = 4; |
| 291 | I1c->line_size = 16; |
| 292 | L2c->size = 64; |
| 293 | L2c->assoc = 16; |
| 294 | L2c->line_size = 16; |
| 295 | ret = 0; |
| 296 | |
| 297 | } else { |
| 298 | VG_(message)(Vg_DebugMsg, "CPU vendor ID not recognised (%s)", |
| 299 | vendor_id); |
| 300 | return -1; |
| 301 | } |
| 302 | |
| 303 | /* Successful! Convert sizes from KB to bytes */ |
| 304 | I1c->size *= 1024; |
| 305 | D1c->size *= 1024; |
| 306 | L2c->size *= 1024; |
| 307 | |
| 308 | return ret; |
| 309 | } |
| 310 | |
| 311 | |
njn | af839f5 | 2005-06-23 03:27:57 +0000 | [diff] [blame] | 312 | void VG_(configure_caches)(cache_t* I1c, cache_t* D1c, cache_t* L2c, |
| 313 | Bool all_caches_clo_defined) |
nethercote | b35a8b9 | 2004-09-11 16:45:27 +0000 | [diff] [blame] | 314 | { |
| 315 | Int res; |
| 316 | |
| 317 | // Set caches to default. |
njn | a1d1a64 | 2004-11-26 18:36:02 +0000 | [diff] [blame] | 318 | *I1c = (cache_t) { 65536, 2, 64 }; |
| 319 | *D1c = (cache_t) { 65536, 2, 64 }; |
| 320 | *L2c = (cache_t) { 262144, 8, 64 }; |
nethercote | b35a8b9 | 2004-09-11 16:45:27 +0000 | [diff] [blame] | 321 | |
| 322 | // Then replace with any info we can get from CPUID. |
| 323 | res = get_caches_from_CPUID(I1c, D1c, L2c); |
| 324 | |
| 325 | // Warn if CPUID failed and config not completely specified from cmd line. |
| 326 | if (res != 0 && !all_caches_clo_defined) { |
| 327 | VG_(message)(Vg_DebugMsg, |
| 328 | "Warning: Couldn't auto-detect cache config, using one " |
| 329 | "or more defaults "); |
| 330 | } |
| 331 | } |
| 332 | |
| 333 | /*--------------------------------------------------------------------*/ |
| 334 | /*--- end ---*/ |
| 335 | /*--------------------------------------------------------------------*/ |