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gerrit-public.fairphone.software / platform / external / valgrind / 70dbeb0232ebafbf0977549b1c72ff53c8ef9863 / priv / host_amd64_isel.c
  1. 70dbeb0 Implement XSAVE/XRSTOR for AVX (state components 0, 1 and 2) by sewardj · 9 years ago
  2. 3e5d82d Bug 345248 - add support for Solaris OS in valgrind by sewardj · 9 years ago
  3. cd4637e amd64 front and back ends: track the change of type of Iop_Sqrt32Fx4 by sewardj · 9 years ago
  4. a5b5022 Bug 345215 - Performance improvements for the register allocator by sewardj · 10 years ago
  5. d8e3eca r2974 moved the inline definition of LibVEX_Alloc from libvex.h by florian · 10 years ago
  6. 108e03f Fix a few undefined behaviours that were found by compiling valgrind by florian · 10 years ago
  7. 6f1ec58 Use IR conditional stores (IRStoreG) to implement AVX-2 conditional by sewardj · 10 years ago
  8. e357c67 Change AMD64Instr_CMov64 so that the source can only be a register by sewardj · 10 years ago
  9. bdea550 AMD64 front end: translate AVX2 PMASKMOV load instructions (vector by sewardj · 10 years ago
  10. 93a0974 Remove the definitons of Ptr_to_ULong and ULong_to_Ptr. by florian · 10 years ago
  11. dcd6d23 Change the IMark statement. The address is now type Addr and the by florian · 10 years ago
  12. cacba8e More constification. by florian · 10 years ago
  13. d8c64e0 Constification part 5. by florian · 10 years ago
  14. 1ddee21 Rename IROps for reciprocal estimate, reciprocal step, reciprocal sqrt by sewardj · 10 years ago
  15. 9b76916 Improve infrastructure for dealing with endianness in VEX. This patch by sewardj · 10 years ago
  16. 05f5e01 Renaming only (no functional change): rename IR artefacts to do by sewardj · 10 years ago
  17. e9c51c9 x87 instructions FSIN, FCOS, FSINCOS and FPTAN: handle out-of-range by sewardj · 10 years ago
  18. 9571dc0 Make the following primops take a third (initial) argument to by sewardj · 11 years ago
  19. 89ae847 Update copyright dates (20XY-2012 ==> 20XY-2013) by sewardj · 11 years ago
  20. 54eea4e Comment-only change. by sewardj · 11 years ago
  21. 82cc37c Add support for 256-bit return values for dirty helpers (amd64 only). by sewardj · 11 years ago
  22. 9041956 Eliminate IRExprP__VECRET and IRExprP__BBPTR and introduce two new by florian · 11 years ago
  23. 74142b8 Add infrastructural support (IR, VEX) to allow returns of 128- by sewardj · 11 years ago
  24. cc3d219 AMD64: Add support for AVX2, BMI1, BMI2 and FMA instructions (VEX side). by sewardj · 12 years ago
  25. 818c730 Implement RDTSCP on amd64, finally. This fixes #251569 and dups by sewardj · 12 years ago
  26. 79efdc6 Make HReg a struct. In the past there were several occurences where by florian · 12 years ago
  27. e6be61f Fix a few more HReg <-> UInt mixups. by florian · 12 years ago
  28. 99dd03e Infrastructure cleanup part 2. by florian · 12 years ago
  29. 009230b Infrastructure cleanup: change type of the condition field of by sewardj · 12 years ago
  30. cfe046e Merge, from branches/COMEM, revisions 2568 to 2641. by sewardj · 12 years ago
  31. 9213c61 Iop_GetMSBs8x16: remove a copy-n-paste error introduced in r2590. by sewardj · 12 years ago
  32. 78a2059 Implement 128-bit PMOVMSKB using a single new primop (Iop_GetMSBs8x16) by sewardj · 12 years ago
  33. e13074c Improve accuracy of definedness tracking through the x86 PMOVMSKB and by sewardj · 12 years ago
  34. 25e5473 Update copyright dates to include 2012. by sewardj · 12 years ago
  35. c862f28 Handle Iop_32to1 in the amd64 insn selector. by florian · 12 years ago
  36. 37a505b Add a new IRConst kind -- V256 -- containing an abbreviated vector by sewardj · 12 years ago
  37. 23db8a0 Add IR ops Iop_CmpNEZ32x8 and Iop_CmpNEZ64x4, needed for Memcheck by sewardj · 12 years ago
  38. 8209692 More AVX insns: by sewardj · 12 years ago
  39. 8eb7ae8 by sewardj · 12 years ago
  40. d8bca7e Implement by sewardj · 12 years ago
  41. 66becf3 More AVX insns: by sewardj · 12 years ago
  42. 2a2bda9 Fill in some missing AVX insns: by sewardj · 12 years ago
  43. 4b1cc83 Implement even more instructions generated by "gcc-4.7.0 -mavx -O3". by sewardj · 12 years ago
  44. 56c3031 Make a start at implementing 256-bit AVX instructions generated by by sewardj · 12 years ago
  45. 420bfa9 Put the Triop member into a separate struct (IRTriop) and link to that by florian · 12 years ago
  46. 96d7cc3 Put the Qop member into a separate struct (IRQop) and link to that by florian · 12 years ago
  47. d6f38b3 Reduce size of an IRStmt from 40 bytes to 32 bytes on LP64 by florian · 12 years ago
  48. 3616a2e Remove, or (where it might later come in handy) comment out artefacts by sewardj · 12 years ago
  49. c4530ae Add initial support for Intel AVX instructions (VEX side). by sewardj · 12 years ago
  50. f350a42 Add a feature check flag for AVX. by sewardj · 12 years ago
  51. 2f6902b For each backend, unify the sets of IRJumpKinds handled for Ist_Exit by sewardj · 12 years ago
  52. 3d0e38e (post-tchain-merge cleanup) Stop x86/amd64 asserting on illegal insns. by sewardj · 12 years ago
  53. 96c5f26 Deal with CLFLUSH, which were not correctly dealt with (w.r.t. new IR by sewardj · 12 years ago
  54. c6f970f Add translation chaining support for amd64, x86 and ARM (VEX side). See #296422. by sewardj · 12 years ago
  55. e6c53e0 Update all copyright dates, from 20xy-2010 to 20xy-2011. by sewardj · 13 years ago
  56. ad2c9ea VEX side fixes to match r12190, which is a fix for #279698 (incorrect by sewardj · 13 years ago
  57. d881562 Implement the SSE4.1 insn PCMPEQQ. n-i-bz. (VEX side changes) by sewardj · 13 years ago
  58. 5f438dd Rename and rationalise the vector narrowing and widening primops, so by sewardj · 13 years ago
  59. 2260b99 Implement PACKUSDW (SSE4.1). Fixes #274776. by sewardj · 13 years ago
  60. c9bff7d Partially fix underspecification of saturating narrowing primops that by sewardj · 13 years ago
  61. 9cc2bbf Improvements to code generation for 32 bit instructions. When by sewardj · 13 years ago
  62. 13f12a5 Fix a nonsensical assertion observed by Florian Krohm. by sewardj · 13 years ago
  63. 0874bee Implement SSE4.x EXTRACTPS. Fixes #258870. by sewardj · 14 years ago
  64. 50d89bf Save an instruction on the normal idiom generated for smc-checks. by sewardj · 14 years ago
  65. ca257bc Minor amd64 instruction selection improvements, leading to a by sewardj · 14 years ago
  66. acfbd7d Add a moderately comprehensive implementation of the SSE4.2 string by sewardj · 14 years ago
  67. 536fbab Only decode LZCNT if the host supports it, since otherwise we risk by sewardj · 14 years ago
  68. d15b597 Implement ROUNDSS (partial implementation, in the case where by sewardj · 14 years ago
  69. 69d98e3 Implement SSE4 instructions: PCMPGTQ PMAXUD PMINUD PMAXSB PMINSB PMULLD by sewardj · 14 years ago
  70. 752f906 Update copyright dates to 2010 and change license to standard GPL2+. by sewardj · 14 years ago
  71. d403e79 iselVecExpr_wrk: 128-bit constants: handle all 16 cases by de · 15 years ago
  72. 9ba870d Handle a few more cases in 128-bit constant generation, needed by by sewardj · 15 years ago
  73. 5a70f5c by de · 15 years ago
  74. 6c299f3 Merge r1925:1948 from branches/ARM. This temporarily breaks all other by sewardj · 15 years ago
  75. e768e92 by sewardj · 15 years ago
  76. 1fb8c92 Add new integer comparison primitives Iop_CasCmp{EQ,NE}{8,16,32,64}, by sewardj · 15 years ago
  77. cef7d3e by sewardj · 15 years ago[Renamed (98%) from priv/host-amd64/isel.c]
  78. e9d8a26 Merge in branches/DCAS: by sewardj · 15 years ago
  79. 4970e4e Support FPREM1 on amd64. Fixes #172563. by sewardj · 16 years ago
  80. 7950111 Handle Iop_ReinterpF32asI32, as needed for exp-ptrcheck. by sewardj · 16 years ago
  81. 80d6e6d Fix a couple of longstanding enum inconsistencies discovered by by sewardj · 16 years ago
  82. 478646f Merge branches/OTRACK_BY_INSTRUMENTATION into the trunk. This by sewardj · 16 years ago
  83. a26d820 Update copyright dates ("200X-2007" --> "200X-2008"). by sewardj · 17 years ago
  84. d166e28 by sewardj · 17 years ago
  85. bf0d86c Fix stupid bug in x86 isel: when generating code for a 64-bit integer by sewardj · 17 years ago
  86. c4356f0 by sewardj · 17 years ago
  87. 02f79f1 Implement maskmovq and maskmovdq. by sewardj · 17 years ago
  88. 4d77a9c Merge from CGTUNE branch, code generation improvements for amd64: by sewardj · 17 years ago
  89. eb17e49 Merge from CGTUNE branch: by sewardj · 17 years ago
  90. 6ce1a23 Counterpart to r1745: teach the amd64 back end how to generate 'lea' by sewardj · 18 years ago
  91. e744153 Update copyright dates. by sewardj · 18 years ago
  92. dd40fdf by sewardj · 18 years ago
  93. aca070a Merge r1663-r1666: by sewardj · 18 years ago
  94. f4c803b Add support for amd64 'fprem' (fixes bug 132918). This isn't exactly by sewardj · 18 years ago
  95. f355f6b amd64 insn printing fix. by sewardj · 18 years ago
  96. a33e9a4 Update copyright dates. by sewardj · 18 years ago
  97. 8f07359 Counterpart to r1605: in the ppc insn selector, don't use the bits by sewardj · 18 years ago
  98. 4796d66 Fixups following recent FP rounding mode changes. by sewardj · 19 years ago
  99. b183b85 by sewardj · 19 years ago
  100. 5117ce1 Change the way Vex represents architecture variants into something by sewardj · 19 years ago