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gerrit-public.fairphone.software / platform / external / valgrind / ad00ea9f40f930d98bb2d278291a6c4c6636d6d6 / priv / guest_ppc_toIR.c
  1. d2c19b4 Add detection of old ppc32 magic instructions from bug 278808. by mjw · 10 years ago
  2. 85175a7 This patch makes the needed changes to the lxvw4x for Little Endian. by carll · 10 years ago
  3. 4e303f2 ppc64: lxvw4x instruction uses four 32-byte loads. When run on an by carll · 10 years ago
  4. 8462d11 Constification part 4. by florian · 10 years ago
  5. a5c17c6 The PPC64 store quad instruction is updating the address register with the by carll · 10 years ago
  6. 1ddee21 Rename IROps for reciprocal estimate, reciprocal step, reciprocal sqrt by sewardj · 10 years ago
  7. 150794d putGST_masked: correctly handle the case where the mask is for by sewardj · 10 years ago
  8. 2faf591 Small cleanups in VEX: by philippe · 10 years ago
  9. 99af243 Unbreak the build by philippe · 10 years ago
  10. 94e2de3 This commit is for Bugzilla 334834. by carll · 10 years ago
  11. 1f5fe1f This commit is for Bugzilla 334834. The Bugzilla contains patch 2 of 3 by carll · 10 years ago
  12. 9b76916 Improve infrastructure for dealing with endianness in VEX. This patch by sewardj · 10 years ago
  13. d1526f2 Remove fields from VexAbiInfo that only had relevance to the old AIX5 by sewardj · 10 years ago
  14. a8c7b0f The vector versions of the count leading zeros/sign bits primops by sewardj · 10 years ago
  15. 20a760e Fix assertion failures resulting from change of arity of by sewardj · 10 years ago
  16. 05f5e01 Renaming only (no functional change): rename IR artefacts to do by sewardj · 10 years ago
  17. 2171afd Fix the ppc32 special-instruction magic sequence so it really does by sewardj · 10 years ago
  18. 9fcbb9a This patch by adrian.sendroiu@freescale.com fixes the lrmw and stmw by carll · 10 years ago
  19. 89ae847 Update copyright dates (20XY-2012 ==> 20XY-2013) by sewardj · 11 years ago
  20. 60c6bac This commit adds support for the following instructions: by carll · 11 years ago
  21. 7deaf95 Power 8 support, phase 5 by carll · 11 years ago
  22. 2691a61 PPC32/64: Allow 16 byte icache lines. by sewardj · 11 years ago
  23. fcce5f8 Power PC, add the two privileged Transactional Memory instructions. by carll · 11 years ago
  24. 6c758b6 Phase 4 support for IBM Power ISA 2.07 by carll · 11 years ago
  25. 8943d02 Power PC, Approach 1, add Transactional Memory instruction support by carll · 11 years ago
  26. 48ae46b Phase 3 support for IBM Power ISA 2.07 by carll · 11 years ago
  27. 6fef87a The Power ISA 2.07 document includes a correction to the description for the by carll · 11 years ago
  28. 78850ae Bugzilla 323437, this is phase 2 in a series of patches adding support for IBM by carll · 11 years ago
  29. 38b79ac The existing overflow detection in VEX/priv/guest_ppc_toIR.c/set_XER_OV_64() by carll · 11 years ago
  30. 9708b6a The patch used the binary constants 0b10000 and 0b10001. The 0b designator by carll · 11 years ago
  31. b77db0e The current code is not properly handling a non-zero TH field in the by carll · 11 years ago
  32. 9041956 Eliminate IRExprP__VECRET and IRExprP__BBPTR and introduce two new by florian · 11 years ago
  33. 0c74bb5 Initial ISA 2.07 support for POWER8-tuned libc by carll · 11 years ago
  34. 74142b8 Add infrastructural support (IR, VEX) to allow returns of 128- by sewardj · 11 years ago
  35. 9138b17 Rename ppc_cache_line_szB to indicate that this is the size by florian · 11 years ago
  36. 654b7f9 Shifting an int and assigning it to a long could be trouble. by florian · 11 years ago
  37. 9884af0 The Coverity tool was run against the Valgrind source code and identified a by carll · 11 years ago
  38. 99dd03e Infrastructure cleanup part 2. by florian · 11 years ago
  39. 009230b Infrastructure cleanup: change type of the condition field of by sewardj · 11 years ago
  40. cea07cc Fix implementation of the DFP integer operands. by carll · 12 years ago
  41. f704eb2 The 32-bit DFP value is stored in a 64-bit register in by carll · 12 years ago
  42. 442e51a Make diagnostics for SIGILL more controllable (VEX part). by sewardj · 12 years ago
  43. 55085f8 Changes for -Wwrite-strings by florian · 12 years ago
  44. bb3f401 Valgrind, ppc: Fix missing checks for 64-bit instructions operating in 32-bit mode, Bugzilla 308573 by carll · 12 years ago
  45. 5df8ab0 Fix HChar / UCHar / Char mixups. VEX now compiles without by florian · 12 years ago
  46. 58a637b Make header files compilable by itself to get two benefits: by florian · 12 years ago
  47. 9e23873 Fix IR injection for ppc32. Need to use mkSzImm not mkU64... by florian · 12 years ago
  48. 2245ce9 VEX-side support for the V-bit tester. by florian · 12 years ago
  49. 6ef84be Followup to r2483, purely mechanical. Rename: by florian · 12 years ago
  50. 25e5473 Update copyright dates to include 2012. by sewardj · 12 years ago
  51. 2bcdd65 ppc front end: fnmadd, fnmsub, fnmadds, fnmsubs: don't negate the by sewardj · 12 years ago
  52. 738d9dd fix 303116 Add support for the POWER instruction popcntb (VEX part) by philippe · 12 years ago
  53. 4c96e61 POWER Processor decimal FP support, part 5 (VEX side). Bug #299694. by sewardj · 12 years ago
  54. c9069f2 Enhance the guest state effects notation on IRDirty calls, so as to be by sewardj · 12 years ago
  55. cb06d5e Don't use constants of the form 0b...; apparently older compilers by sewardj · 12 years ago
  56. 5eff1c5 Add support for POWER Power Decimal Floating Point (DFP) test class, by sewardj · 12 years ago
  57. cdc376d POWER Processor decimal floating point instruction support, part 3 by sewardj · 12 years ago
  58. db01409 Merge branches/TCHAIN from r2271 (its creation point) into trunk. by sewardj · 12 years ago
  59. 3dee849 Add translation chaining support for ppc32 (tested) and to by sewardj · 12 years ago
  60. 26217b0 by sewardj · 12 years ago
  61. c6f970f Add translation chaining support for amd64, x86 and ARM (VEX side). See #296422. by sewardj · 12 years ago
  62. c66d6fa Fixes for capabilities checking w.r.t. Power DFP instructions (VEX by sewardj · 12 years ago
  63. c6bbd47 Initial support for POWER Processor decimal floating point instruction by sewardj · 12 years ago
  64. dc7948f Add some VEX sanity checks for ppc64 unhandled instructions. by florian · 12 years ago
  65. e6c53e0 Update all copyright dates, from 20xy-2010 to 20xy-2011. by sewardj · 13 years ago
  66. e71e56a Add support for IBM Power ISA 2.06 -- stage 3. by sewardj · 13 years ago
  67. 4aa412a Add support for IBM Power ISA 2.06 -- stage 2. Bug 276784. by sewardj · 13 years ago
  68. 5f438dd Rename and rationalise the vector narrowing and widening primops, so by sewardj · 13 years ago
  69. c9bff7d Partially fix underspecification of saturating narrowing primops that by sewardj · 13 years ago
  70. 95d6f3a Fix up incorrect usage of Iop_I64UtoF32 in the PowerPC front and back by sewardj · 13 years ago
  71. 66d5ef2 Add support for IBM Power ISA 2.06 -- stage 1. Bug #267630 and by sewardj · 13 years ago
  72. 7e84630 Support new PowerISA_2.05 instructions available on Power6 CPUs. by sewardj · 14 years ago
  73. e971c6a Support the DCBZL instruction. Also, query the host CPU at startup by sewardj · 14 years ago
  74. 752f906 Update copyright dates to 2010 and change license to standard GPL2+. by sewardj · 14 years ago
  75. 984d9b1 by sewardj · 15 years ago
  76. 6c299f3 Merge r1925:1948 from branches/ARM. This temporarily breaks all other by sewardj · 15 years ago
  77. e768e92 by sewardj · 15 years ago
  78. 37b2ee8 Implement mfpvr (mfspr 287) (bug #201585). by sewardj · 15 years ago
  79. cef7d3e by sewardj · 15 years ago[Renamed (99%) from priv/guest-ppc/toIR.c]
  80. e9d8a26 Merge in branches/DCAS: by sewardj · 15 years ago
  81. e86310f In order to make it possible for Valgrind to restart client syscalls by sewardj · 15 years ago
  82. 1685c28 Tighten up decoding of isel instruction. by sewardj · 16 years ago
  83. cb07be2 Support isel (integer conditional move). by sewardj · 16 years ago
  84. 2b8db3e C89 fixes (stop gcc complaining). by sewardj · 16 years ago
  85. 0f1ef86 Handle frin, frim, frip, friz, in 64-bit mode only, for now. by sewardj · 16 years ago
  86. fe397a2 Ignore .EH bit in lwarx / ldarx as it appears to be merely a hint. by sewardj · 16 years ago
  87. 019f406 Add Imbe_SnoopedStoreBegin and Imbe_SnoopedStoreEnd, to be used for by sewardj · 16 years ago
  88. c85bf02 Allow 64-byte line sizes (PA6T cpu). by sewardj · 16 years ago
  89. 478646f Merge branches/OTRACK_BY_INSTRUMENTATION into the trunk. This by sewardj · 16 years ago
  90. a26d820 Update copyright dates ("200X-2007" --> "200X-2008"). by sewardj · 16 years ago
  91. c4356f0 by sewardj · 17 years ago
  92. 0f50004 Support x86 $int 0x40 .. 0x43 instructions on Linux. Apparently these by sewardj · 17 years ago
  93. b4f6d6b Support td (64-bit counterpart to r1784). by sewardj · 17 years ago
  94. 59c0d8f Better support for trap insns. This adds support for tw (previously twi and by sewardj · 17 years ago
  95. eb17e49 Merge from CGTUNE branch: by sewardj · 17 years ago
  96. 6d83422 Comment-only changes. by sewardj · 17 years ago
  97. e744153 Update copyright dates. by sewardj · 18 years ago
  98. 923c65b Enable support for altivec prefetches: dss, dst, dstt, dstst, dststt. by sewardj · 18 years ago
  99. d2fd864 Enable lvxl and stvxl. by sewardj · 18 years ago
  100. abb321c Implement mfspr 268 and 269. Fixes #139050. by sewardj · 18 years ago