1. 85175a7 This patch makes the needed changes to the lxvw4x for Little Endian. by carll · 10 years ago
  2. d8c64e0 Constification part 5. by florian · 10 years ago
  3. 99de41e This commit just makes white space changes to the three files in commit by carll · 10 years ago
  4. 9877fe5 msg by carll · 10 years ago
  5. 678ede2 The function mk_AvDuplicateRI() stores 16 bytes to memory and then by carll · 10 years ago
  6. 7842caf iselStmt, case Ist_Dirty: remove pointless conditional. Spotted by by sewardj · 10 years ago
  7. 1ddee21 Rename IROps for reciprocal estimate, reciprocal step, reciprocal sqrt by sewardj · 10 years ago
  8. 1f5fe1f This commit is for Bugzilla 334834. The Bugzilla contains patch 2 of 3 by carll · 10 years ago
  9. 9b76916 Improve infrastructure for dealing with endianness in VEX. This patch by sewardj · 10 years ago
  10. d1526f2 Remove fields from VexAbiInfo that only had relevance to the old AIX5 by sewardj · 10 years ago
  11. a8c7b0f The vector versions of the count leading zeros/sign bits primops by sewardj · 10 years ago
  12. c4fa725 Fix an enum type confusion, PPCAvFpOp vs PPCAvOp, as excellently by sewardj · 10 years ago
  13. 20a760e Fix assertion failures resulting from change of arity of by sewardj · 10 years ago
  14. 05f5e01 Renaming only (no functional change): rename IR artefacts to do by sewardj · 10 years ago
  15. f5530ec In 64 bit mode, allow 64 bit return values from clean helper calls. by sewardj · 11 years ago
  16. 89ae847 Update copyright dates (20XY-2012 ==> 20XY-2013) by sewardj · 11 years ago
  17. 60c6bac This commit adds support for the following instructions: by carll · 11 years ago
  18. 7deaf95 Power 8 support, phase 5 by carll · 11 years ago
  19. 48ae46b Phase 3 support for IBM Power ISA 2.07 by carll · 11 years ago
  20. 9041956 Eliminate IRExprP__VECRET and IRExprP__BBPTR and introduce two new by florian · 11 years ago
  21. 0c74bb5 Initial ISA 2.07 support for POWER8-tuned libc by carll · 11 years ago
  22. 74142b8 Add infrastructural support (IR, VEX) to allow returns of 128- by sewardj · 11 years ago
  23. 8bde7f1 Implement ARM SDIV and UDIV instructions. Fixes #314178. Partially by sewardj · 11 years ago
  24. 2a8d070 VEX, ppc code cleanup by carll · 11 years ago
  25. 79efdc6 Make HReg a struct. In the past there were several occurences where by florian · 11 years ago
  26. e6be61f Fix a few more HReg <-> UInt mixups. by florian · 11 years ago
  27. 99dd03e Infrastructure cleanup part 2. by florian · 11 years ago
  28. 60733f8 Fix up a non-handled Mux0X case following r2664, and verify that by sewardj · 11 years ago
  29. 009230b Infrastructure cleanup: change type of the condition field of by sewardj · 11 years ago
  30. cea07cc Fix implementation of the DFP integer operands. by carll · 12 years ago
  31. f704eb2 The 32-bit DFP value is stored in a 64-bit register in by carll · 12 years ago
  32. cfe046e Merge, from branches/COMEM, revisions 2568 to 2641. by sewardj · 12 years ago
  33. 2b4890f The call to set the rounding mode for DFP iops: Iop_AddD128, Iop_SubD128, by carll · 12 years ago
  34. 9163968 VEX, ppc fix use of modified value in the Iop_32HLto64 implementation by carll · 12 years ago
  35. e83db48 Add vassert for DFP shift value to make sure shift value is an immediate value. by carll · 12 years ago
  36. a25732d Handle Iop_Left16 so And16 / Sub16 work properly with memcheck. by florian · 12 years ago
  37. 25e5473 Update copyright dates to include 2012. by sewardj · 12 years ago
  38. a7b0d10 Fix a few issues as reported by the BEAM tool. by florian · 12 years ago
  39. 878f151 Fix two Binop / Unop mixups. by florian · 12 years ago
  40. 4c96e61 POWER Processor decimal FP support, part 5 (VEX side). Bug #299694. by sewardj · 12 years ago
  41. 420bfa9 Put the Triop member into a separate struct (IRTriop) and link to that by florian · 12 years ago
  42. 96d7cc3 Put the Qop member into a separate struct (IRQop) and link to that by florian · 12 years ago
  43. d6f38b3 Reduce size of an IRStmt from 40 bytes to 32 bytes on LP64 by florian · 12 years ago
  44. 5eff1c5 Add support for POWER Power Decimal Floating Point (DFP) test class, by sewardj · 12 years ago
  45. cdc376d POWER Processor decimal floating point instruction support, part 3 by sewardj · 12 years ago
  46. 2f6902b For each backend, unify the sets of IRJumpKinds handled for Ist_Exit by sewardj · 12 years ago
  47. db01409 Merge branches/TCHAIN from r2271 (its creation point) into trunk. by sewardj · 12 years ago
  48. f252de5 Changes to make t-chaining work on ppc64-linux. More fun than a by sewardj · 12 years ago
  49. 9e1cf15 Fill in some more bits to do with t-chaining for ppc64 by sewardj · 12 years ago
  50. 3dee849 Add translation chaining support for ppc32 (tested) and to by sewardj · 12 years ago
  51. 26217b0 by sewardj · 12 years ago
  52. c66d6fa Fixes for capabilities checking w.r.t. Power DFP instructions (VEX by sewardj · 12 years ago
  53. c6bbd47 Initial support for POWER Processor decimal floating point instruction by sewardj · 12 years ago
  54. 9627fe8 Iop_1Uto64 was not handled in the ppc insn selector. by florian · 13 years ago
  55. e6c53e0 Update all copyright dates, from 20xy-2010 to 20xy-2011. by sewardj · 13 years ago
  56. e71e56a Add support for IBM Power ISA 2.06 -- stage 3. by sewardj · 13 years ago
  57. 7a08c10 Remove a redundant check. Found by Coverity. by florian · 13 years ago
  58. 4aa412a Add support for IBM Power ISA 2.06 -- stage 2. Bug 276784. by sewardj · 13 years ago
  59. 5f438dd Rename and rationalise the vector narrowing and widening primops, so by sewardj · 13 years ago
  60. c9bff7d Partially fix underspecification of saturating narrowing primops that by sewardj · 13 years ago
  61. 7d810d7 Handle Iop_I64UtoF32 in the ppc32/ppc64 insn selector. Fixes #270851. by sewardj · 13 years ago
  62. 54d75f7 Fix an assertion failure caused by r2144 (improved assertions to do by sewardj · 13 years ago
  63. 7e30807 Tighten up condition code handling in the back end, so as to placate by sewardj · 13 years ago
  64. d34e449 Handle Iop_Not64 when doing 32-bit code generation. Also, assert that by sewardj · 13 years ago
  65. 95d6f3a Fix up incorrect usage of Iop_I64UtoF32 in the PowerPC front and back by sewardj · 13 years ago
  66. e522d4b Fix up enum confusion between PPCAvOp and PPCAvFpOp, as found by by sewardj · 13 years ago
  67. 66d5ef2 Add support for IBM Power ISA 2.06 -- stage 1. Bug #267630 and by sewardj · 13 years ago
  68. d2b1816 Handle Ico_V128(0xFFFF), created by more aggressive constant folding by sewardj · 13 years ago
  69. 752f906 Update copyright dates to 2010 and change license to standard GPL2+. by sewardj · 14 years ago
  70. 6c299f3 Merge r1925:1948 from branches/ARM. This temporarily breaks all other by sewardj · 15 years ago
  71. e768e92 by sewardj · 15 years ago
  72. cef7d3e by sewardj · 15 years ago[Renamed (99%) from priv/host-ppc/isel.c]
  73. e9d8a26 Merge in branches/DCAS: by sewardj · 15 years ago
  74. 0f1ef86 Handle frin, frim, frip, friz, in 64-bit mode only, for now. by sewardj · 16 years ago
  75. c07349e Add support needed for exp-ptrcheck on ppc32/64. by sewardj · 16 years ago
  76. 019f406 Add Imbe_SnoopedStoreBegin and Imbe_SnoopedStoreEnd, to be used for by sewardj · 16 years ago
  77. 478646f Merge branches/OTRACK_BY_INSTRUMENTATION into the trunk. This by sewardj · 16 years ago
  78. a26d820 Update copyright dates ("200X-2007" --> "200X-2008"). by sewardj · 16 years ago
  79. e2957d6 Generate code to handle 64-bit integer loads and stores on 32-bit by sewardj · 17 years ago
  80. c4356f0 by sewardj · 17 years ago
  81. eb17e49 Merge from CGTUNE branch: by sewardj · 17 years ago
  82. 34085e3 When generating 64-bit code, ensure that any addresses used in 4 or 8 by sewardj · 17 years ago
  83. e744153 Update copyright dates. by sewardj · 18 years ago
  84. dd40fdf by sewardj · 18 years ago
  85. aca070a Merge r1663-r1666: by sewardj · 18 years ago
  86. a33e9a4 Update copyright dates. by sewardj · 18 years ago
  87. cd90bfe ppc backend: handle vector constant of zero. by cerion · 18 years ago
  88. 8f07359 Counterpart to r1605: in the ppc insn selector, don't use the bits by sewardj · 18 years ago
  89. 40c8026 Redo the way FP multiply-accumulate insns are done on ppc32/64. by sewardj · 18 years ago
  90. fa7fc6b Comment-only changes by sewardj · 18 years ago
  91. 1a3bfac Followup to r1562: fixes for ppc64 by sewardj · 18 years ago
  92. b183b85 by sewardj · 18 years ago
  93. 7bbac21 F64i isel fix. by sewardj · 18 years ago
  94. 7c54586 Unbreak ppc32 following recent hw-capabilities hackery. by sewardj · 18 years ago
  95. 5117ce1 Change the way Vex represents architecture variants into something by sewardj · 18 years ago
  96. baf971a Handle ppc32/64 fres, frsqrte. by sewardj · 18 years ago
  97. c74373d In 32-bit mode, handle F64toI64 and I64toF64. by sewardj · 18 years ago
  98. 7fd5bb0 A bit more backend tidying: by sewardj · 19 years ago
  99. 92923de by sewardj · 19 years ago
  100. 6332740 C89 fixes. by sewardj · 19 years ago