blob: 53215fe673a952c5773c99c678aa8541ca46432c [file] [log] [blame]
Chia-I Wuc14d1562014-10-17 09:49:22 +08001/*
2 * XGL
3 *
4 * Copyright (C) 2014 LunarG, Inc.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included
14 * in all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE.
23 *
24 * Authors:
25 * Chia-I Wu <olv@lunarg.com>
26 */
27
28#include "img.h"
29#include "mem.h"
Chia-I Wu429a0aa2014-10-24 11:57:51 +080030#include "state.h"
Chia-I Wuc14d1562014-10-17 09:49:22 +080031#include "cmd_priv.h"
32
33static void cmd_meta_init_mem_view(struct intel_cmd *cmd,
34 XGL_GPU_MEMORY mem,
35 XGL_GPU_SIZE range,
36 XGL_FORMAT format,
37 XGL_MEMORY_STATE state,
38 struct intel_mem_view *view)
39{
40 XGL_MEMORY_VIEW_ATTACH_INFO info;
41
42 memset(&info, 0, sizeof(info));
43 info.sType = XGL_STRUCTURE_TYPE_MEMORY_VIEW_ATTACH_INFO;
44 info.mem = mem;
45 info.range = range;
46 info.stride = icd_format_get_size(format);
47 info.format = format;
48 info.state = state;
49
50 intel_mem_view_init(view, cmd->dev, &info);
51}
52
53static void cmd_meta_set_src_for_mem(struct intel_cmd *cmd,
54 const struct intel_mem *mem,
55 XGL_FORMAT format,
56 struct intel_cmd_meta *meta)
57{
58 struct intel_mem_view view;
59
60 cmd_meta_init_mem_view(cmd, (XGL_GPU_MEMORY) mem, mem->size, format,
61 XGL_MEMORY_STATE_GRAPHICS_SHADER_READ_ONLY, &view);
62
63 meta->src.valid = true;
64
65 memcpy(meta->src.surface, view.cmd, sizeof(view.cmd[0]) * view.cmd_len);
66 meta->src.surface_len = view.cmd_len;
67
68 meta->src.reloc_target = (intptr_t) mem->bo;
69 meta->src.reloc_offset = 0;
70 meta->src.reloc_flags = 0;
71}
72
73static void cmd_meta_set_dst_for_mem(struct intel_cmd *cmd,
74 const struct intel_mem *mem,
75 XGL_FORMAT format,
76 struct intel_cmd_meta *meta)
77{
78 struct intel_mem_view view;
79
80 cmd_meta_init_mem_view(cmd, (XGL_GPU_MEMORY) mem, mem->size, format,
81 XGL_MEMORY_STATE_GRAPHICS_SHADER_WRITE_ONLY, &view);
82
83 meta->dst.valid = true;
84
85 memcpy(meta->dst.surface, view.cmd, sizeof(view.cmd[0]) * view.cmd_len);
86 meta->dst.surface_len = view.cmd_len;
87
88 meta->dst.reloc_target = (intptr_t) mem->bo;
89 meta->dst.reloc_offset = 0;
90 meta->dst.reloc_flags = 0;
91}
92
93static void cmd_meta_set_src_for_img(struct intel_cmd *cmd,
94 const struct intel_img *img,
95 XGL_FORMAT format,
96 XGL_IMAGE_ASPECT aspect,
97 struct intel_cmd_meta *meta)
98{
99 XGL_IMAGE_VIEW_CREATE_INFO info;
100 struct intel_img_view *view;
101 XGL_RESULT ret;
102
103 memset(&info, 0, sizeof(info));
104 info.sType = XGL_STRUCTURE_TYPE_IMAGE_VIEW_CREATE_INFO;
105 info.image = (XGL_IMAGE) img;
106
107 switch (img->type) {
108 case XGL_IMAGE_1D:
109 info.viewType = XGL_IMAGE_VIEW_1D;
110 break;
111 case XGL_IMAGE_2D:
112 info.viewType = XGL_IMAGE_VIEW_2D;
113 break;
114 case XGL_IMAGE_3D:
115 info.viewType = XGL_IMAGE_VIEW_3D;
116 break;
117 default:
118 break;
119 }
120
121 info.format = format;
122 info.channels.r = XGL_CHANNEL_SWIZZLE_R;
123 info.channels.g = XGL_CHANNEL_SWIZZLE_G;
124 info.channels.b = XGL_CHANNEL_SWIZZLE_B;
125 info.channels.a = XGL_CHANNEL_SWIZZLE_A;
126 info.subresourceRange.aspect = aspect;
127 info.subresourceRange.baseMipLevel = 0;
128 info.subresourceRange.mipLevels = XGL_LAST_MIP_OR_SLICE;
129 info.subresourceRange.baseArraySlice = 0;
130 info.subresourceRange.arraySize = XGL_LAST_MIP_OR_SLICE;
131
132 ret = intel_img_view_create(cmd->dev, &info, &view);
133 if (ret != XGL_SUCCESS) {
134 cmd->result = ret;
135 return;
136 }
137
138 meta->src.valid = true;
139
140 memcpy(meta->src.surface, view->cmd,
141 sizeof(view->cmd[0]) * view->cmd_len);
142 meta->src.surface_len = view->cmd_len;
143
144 meta->src.reloc_target = (intptr_t) img->obj.mem->bo;
145 meta->src.reloc_offset = 0;
146 meta->src.reloc_flags = 0;
147
148 intel_img_view_destroy(view);
149}
150
151static void cmd_meta_set_dst_for_img(struct intel_cmd *cmd,
152 const struct intel_img *img,
153 XGL_FORMAT format,
154 XGL_UINT lod, XGL_UINT layer,
155 struct intel_cmd_meta *meta)
156{
157 XGL_COLOR_ATTACHMENT_VIEW_CREATE_INFO info;
158 struct intel_rt_view *rt;
159 XGL_RESULT ret;
160
161 memset(&info, 0, sizeof(info));
162 info.sType = XGL_STRUCTURE_TYPE_COLOR_ATTACHMENT_VIEW_CREATE_INFO;
163 info.image = (XGL_IMAGE) img;
164 info.format = format;
165 info.mipLevel = lod;
166 info.baseArraySlice = layer;
167 info.arraySize = 1;
168
169 ret = intel_rt_view_create(cmd->dev, &info, &rt);
170 if (ret != XGL_SUCCESS) {
171 cmd->result = ret;
172 return;
173 }
174
175 meta->dst.valid = true;
176
177 memcpy(meta->dst.surface, rt->cmd, sizeof(rt->cmd[0]) * rt->cmd_len);
178 meta->dst.surface_len = rt->cmd_len;
179
180 meta->dst.reloc_target = (intptr_t) img->obj.mem->bo;
181 meta->dst.reloc_offset = 0;
182 meta->dst.reloc_flags = 0;
183
184 intel_rt_view_destroy(rt);
185}
186
187static void cmd_meta_set_src_for_writer(struct intel_cmd *cmd,
188 enum intel_cmd_writer_type writer,
189 XGL_GPU_SIZE size,
190 XGL_FORMAT format,
191 struct intel_cmd_meta *meta)
192{
193 struct intel_mem_view view;
194
195 cmd_meta_init_mem_view(cmd, XGL_NULL_HANDLE, size, format,
196 XGL_MEMORY_STATE_GRAPHICS_SHADER_READ_ONLY, &view);
197
198 meta->src.valid = true;
199
200 memcpy(meta->src.surface, view.cmd, sizeof(view.cmd[0]) * view.cmd_len);
201 meta->src.surface_len = view.cmd_len;
202
203 meta->src.reloc_target = (intptr_t) writer;
204 meta->src.reloc_offset = 0;
205 meta->src.reloc_flags = INTEL_CMD_RELOC_TARGET_IS_WRITER;
206}
207
Chia-I Wu429a0aa2014-10-24 11:57:51 +0800208static void cmd_meta_set_ds_view(struct intel_cmd *cmd,
209 const struct intel_img *img,
210 XGL_UINT lod, XGL_UINT layer,
211 struct intel_cmd_meta *meta)
Chia-I Wuc14d1562014-10-17 09:49:22 +0800212{
213 XGL_DEPTH_STENCIL_VIEW_CREATE_INFO info;
214 struct intel_ds_view *ds;
215 XGL_RESULT ret;
216
217 memset(&info, 0, sizeof(info));
218 info.sType = XGL_STRUCTURE_TYPE_DEPTH_STENCIL_VIEW_CREATE_INFO;
219 info.image = (XGL_IMAGE) img;
220 info.mipLevel = lod;
221 info.baseArraySlice = layer;
222 info.arraySize = 1;
223
224 ret = intel_ds_view_create(cmd->dev, &info, &ds);
225 if (ret != XGL_SUCCESS) {
226 cmd->result = ret;
227 return;
228 }
229
Chia-I Wu429a0aa2014-10-24 11:57:51 +0800230 meta->ds.view = ds;
231}
232
233static void cmd_meta_set_ds_state(struct intel_cmd *cmd,
234 XGL_IMAGE_ASPECT aspect,
235 XGL_UINT32 stencil_ref,
236 struct intel_cmd_meta *meta)
237{
238 XGL_DEPTH_STENCIL_STATE_CREATE_INFO info;
239 struct intel_ds_state *state;
240 XGL_RESULT ret;
241
242 memset(&info, 0, sizeof(info));
243 info.sType = XGL_STRUCTURE_TYPE_DEPTH_STENCIL_STATE_CREATE_INFO;
244
245 if (aspect == XGL_IMAGE_ASPECT_DEPTH) {
246 info.depthWriteEnable = XGL_TRUE;
247 }
248 else if (aspect == XGL_IMAGE_ASPECT_STENCIL) {
249 info.stencilTestEnable = XGL_TRUE;
250 info.stencilReadMask = 0xff;
251 info.stencilWriteMask = 0xff;
252 info.front.stencilFailOp = XGL_STENCIL_OP_KEEP;
253 info.front.stencilPassOp = XGL_STENCIL_OP_REPLACE;
254 info.front.stencilDepthFailOp = XGL_STENCIL_OP_KEEP;
255 info.front.stencilFunc = XGL_COMPARE_ALWAYS;
256 info.front.stencilRef = stencil_ref;
257 info.back = info.front;
258 }
259
260 ret = intel_ds_state_create(cmd->dev, &info, &state);
261 if (ret != XGL_SUCCESS) {
262 cmd->result = ret;
263 return;
264 }
265
266 meta->ds.state = state;
Chia-I Wuc14d1562014-10-17 09:49:22 +0800267}
268
269static enum intel_dev_meta_shader get_shader_id(const struct intel_dev *dev,
270 const struct intel_img *img,
271 bool copy_array)
272{
273 enum intel_dev_meta_shader shader_id;
274
275 switch (img->type) {
276 case XGL_IMAGE_1D:
277 shader_id = (copy_array) ?
278 INTEL_DEV_META_FS_COPY_1D_ARRAY : INTEL_DEV_META_FS_COPY_1D;
279 break;
280 case XGL_IMAGE_2D:
281 shader_id = (img->samples > 1) ? INTEL_DEV_META_FS_COPY_2D_MS :
282 (copy_array) ? INTEL_DEV_META_FS_COPY_2D_ARRAY :
283 INTEL_DEV_META_FS_COPY_2D;
284 break;
285 case XGL_IMAGE_3D:
286 default:
287 shader_id = INTEL_DEV_META_FS_COPY_2D_ARRAY;
288 break;
289 }
290
291 return shader_id;
292}
293
294/**
295 * Return the suitable format for copying between memories. The
296 * format is sampleable, renderable, and the offsets and copy size are
297 * multiples of the format size.
298 */
299static XGL_CHANNEL_FORMAT cmd_meta_mem_channel_format(const struct intel_cmd *cmd,
300 XGL_GPU_SIZE src_offset,
301 XGL_GPU_SIZE dst_offset,
302 XGL_GPU_SIZE size,
303 XGL_SIZE *format_size)
304{
305 const XGL_GPU_SIZE align = (src_offset | dst_offset | size) & 0xf;
306
307 if (align & 0x1) {
308 *format_size = 1;
309 return XGL_CH_FMT_R8;
310 } else if (align & 0x2) {
311 *format_size = 2;
312 return XGL_CH_FMT_R16;
313 } else if (align & 0x4) {
314 *format_size = 4;
315 return XGL_CH_FMT_R32;
316 } else if (align & 0x8) {
317 *format_size = 8;
318 return XGL_CH_FMT_R32G32;
319 } else {
320 *format_size = 16;
321 return XGL_CH_FMT_R32G32B32A32;
322 }
323}
324
325static XGL_FORMAT cmd_meta_img_raw_format(const struct intel_cmd *cmd,
326 XGL_FORMAT format)
327{
328 format.numericFormat = XGL_NUM_FMT_UINT;
329
330 if (icd_format_is_compressed(format)) {
331 switch (icd_format_get_size(format)) {
332 case 1:
333 format.channelFormat = XGL_CH_FMT_R8;
334 break;
335 case 2:
336 format.channelFormat = XGL_CH_FMT_R16;
337 break;
338 case 4:
339 format.channelFormat = XGL_CH_FMT_R32;
340 break;
341 case 8:
342 format.channelFormat = XGL_CH_FMT_R32G32;
343 break;
344 case 16:
345 format.channelFormat = XGL_CH_FMT_R32G32B32A32;
346 break;
347 default:
348 assert(!"unsupported compressed block size");
349 format.channelFormat = XGL_CH_FMT_R8;
350 break;
351 }
352 }
353
354 return format;
355}
356
357XGL_VOID XGLAPI intelCmdCopyMemory(
358 XGL_CMD_BUFFER cmdBuffer,
359 XGL_GPU_MEMORY srcMem,
360 XGL_GPU_MEMORY destMem,
361 XGL_UINT regionCount,
362 const XGL_MEMORY_COPY* pRegions)
363{
364 struct intel_cmd *cmd = intel_cmd(cmdBuffer);
365 struct intel_mem *src = intel_mem(srcMem);
366 struct intel_mem *dst = intel_mem(destMem);
367 struct intel_cmd_meta meta;
368 XGL_FORMAT format;
369 XGL_UINT i;
370
371 memset(&meta, 0, sizeof(meta));
372
373 meta.shader_id = INTEL_DEV_META_FS_COPY_MEM;
374 meta.height = 1;
375 meta.samples = 1;
376
377 format.channelFormat = XGL_CH_FMT_UNDEFINED;
378 format.numericFormat = XGL_NUM_FMT_UINT;
379
380 for (i = 0; i < regionCount; i++) {
381 const XGL_MEMORY_COPY *region = &pRegions[i];
382 XGL_CHANNEL_FORMAT ch;
383 XGL_SIZE format_size;
384
385 ch = cmd_meta_mem_channel_format(cmd, region->srcOffset,
386 region->destOffset, region->copySize, &format_size);
387
388 if (format.channelFormat != ch) {
389 format.channelFormat = ch;
390
391 cmd_meta_set_src_for_mem(cmd, src, format, &meta);
392 cmd_meta_set_dst_for_mem(cmd, dst, format, &meta);
393 }
394
395 meta.src.x = region->srcOffset / format_size;
396 meta.dst.x = region->destOffset / format_size;
397 meta.width = region->copySize / format_size;
398
399 cmd_draw_meta(cmd, &meta);
400 }
401}
402
403XGL_VOID XGLAPI intelCmdCopyImage(
404 XGL_CMD_BUFFER cmdBuffer,
405 XGL_IMAGE srcImage,
406 XGL_IMAGE destImage,
407 XGL_UINT regionCount,
408 const XGL_IMAGE_COPY* pRegions)
409{
410 struct intel_cmd *cmd = intel_cmd(cmdBuffer);
411 struct intel_img *src = intel_img(srcImage);
412 struct intel_img *dst = intel_img(destImage);
413 struct intel_cmd_meta meta;
414 XGL_FORMAT raw_format;
415 bool raw_copy;
416 XGL_UINT i;
417
418 if (src->type != dst->type) {
419 cmd->result = XGL_ERROR_UNKNOWN;
420 return;
421 }
422
423 if (icd_format_is_equal(src->layout.format, dst->layout.format)) {
424 raw_copy = true;
425 raw_format = cmd_meta_img_raw_format(cmd, src->layout.format);
426 } else if (icd_format_is_compressed(src->layout.format) ||
427 icd_format_is_compressed(dst->layout.format)) {
428 cmd->result = XGL_ERROR_UNKNOWN;
429 return;
430 }
431
432 memset(&meta, 0, sizeof(meta));
433
434 cmd_meta_set_src_for_img(cmd, src,
435 (raw_copy) ? raw_format : src->layout.format,
436 XGL_IMAGE_ASPECT_COLOR, &meta);
437
438 meta.samples = dst->samples;
439
440 for (i = 0; i < regionCount; i++) {
441 const XGL_IMAGE_COPY *region = &pRegions[i];
442 XGL_UINT j;
443
444 meta.shader_id = get_shader_id(cmd->dev, src,
445 (region->extent.depth > 1));
446
447 meta.src.lod = region->srcSubresource.mipLevel;
448 meta.src.layer = region->srcSubresource.arraySlice +
449 region->srcOffset.z;
450 meta.src.x = region->srcOffset.x;
451 meta.src.y = region->srcOffset.y;
452
453 meta.dst.lod = region->destSubresource.mipLevel;
454 meta.dst.layer = region->destSubresource.arraySlice +
455 region->destOffset.z;
456 meta.dst.x = region->destOffset.x;
457 meta.dst.y = region->destOffset.y;
458
459 meta.width = region->extent.width;
460 meta.height = region->extent.height;
461
462 for (j = 0; j < region->extent.depth; j++) {
463 cmd_meta_set_dst_for_img(cmd, dst,
464 (raw_copy) ? raw_format : dst->layout.format,
465 meta.dst.lod, meta.dst.layer, &meta);
466
467 cmd_draw_meta(cmd, &meta);
468
469 meta.src.layer++;
470 meta.dst.layer++;
471 }
472 }
473}
474
475XGL_VOID XGLAPI intelCmdCopyMemoryToImage(
476 XGL_CMD_BUFFER cmdBuffer,
477 XGL_GPU_MEMORY srcMem,
478 XGL_IMAGE destImage,
479 XGL_UINT regionCount,
480 const XGL_MEMORY_IMAGE_COPY* pRegions)
481{
482 struct intel_cmd *cmd = intel_cmd(cmdBuffer);
483 struct intel_mem *mem = intel_mem(srcMem);
484 struct intel_img *img = intel_img(destImage);
485 struct intel_cmd_meta meta;
486 XGL_FORMAT format;
487 XGL_UINT i;
488
489 memset(&meta, 0, sizeof(meta));
490
491 meta.shader_id = INTEL_DEV_META_FS_COPY_MEM_TO_IMG;
492 meta.samples = img->samples;
493
494 format = cmd_meta_img_raw_format(cmd, img->layout.format);
495 cmd_meta_set_src_for_mem(cmd, mem, format, &meta);
496
497 for (i = 0; i < regionCount; i++) {
498 const XGL_MEMORY_IMAGE_COPY *region = &pRegions[i];
499 XGL_UINT j;
500
501 meta.src.x = region->memOffset / icd_format_get_size(format);
502
503 meta.dst.lod = region->imageSubresource.mipLevel;
504 meta.dst.layer = region->imageSubresource.arraySlice +
505 region->imageOffset.z;
506 meta.dst.x = region->imageOffset.x;
507 meta.dst.y = region->imageOffset.y;
508
509 meta.width = region->imageExtent.width;
510 meta.height = region->imageExtent.height;
511
512 for (j = 0; j < region->imageExtent.depth; j++) {
513 cmd_meta_set_dst_for_img(cmd, img, format,
514 meta.dst.lod, meta.dst.layer, &meta);
515
516 cmd_draw_meta(cmd, &meta);
517
518 meta.src.x += meta.width * meta.height;
519 meta.dst.layer++;
520 }
521 }
522}
523
524XGL_VOID XGLAPI intelCmdCopyImageToMemory(
525 XGL_CMD_BUFFER cmdBuffer,
526 XGL_IMAGE srcImage,
527 XGL_GPU_MEMORY destMem,
528 XGL_UINT regionCount,
529 const XGL_MEMORY_IMAGE_COPY* pRegions)
530{
531 struct intel_cmd *cmd = intel_cmd(cmdBuffer);
532 struct intel_img *img = intel_img(srcImage);
533 struct intel_mem *mem = intel_mem(destMem);
534 struct intel_cmd_meta meta;
535 XGL_FORMAT format;
536 XGL_UINT i;
537
538 memset(&meta, 0, sizeof(meta));
539
540 format = cmd_meta_img_raw_format(cmd, img->layout.format);
541 cmd_meta_set_src_for_img(cmd, img, format, XGL_IMAGE_ASPECT_COLOR, &meta);
542 cmd_meta_set_dst_for_mem(cmd, mem, format, &meta);
543
544 meta.height = 1;
545 meta.samples = 1;
546
547 for (i = 0; i < regionCount; i++) {
548 const XGL_MEMORY_IMAGE_COPY *region = &pRegions[i];
549 XGL_UINT j;
550
551 meta.shader_id = get_shader_id(cmd->dev, img,
552 (region->imageExtent.depth > 1));
553
554 meta.src.lod = region->imageSubresource.mipLevel;
555 meta.src.layer = region->imageSubresource.arraySlice +
556 region->imageOffset.z;
557 meta.src.x = region->imageOffset.x;
558 meta.src.y = region->imageOffset.y;
559
560 meta.dst.x = region->memOffset / icd_format_get_size(format);
561
562 meta.width = region->imageExtent.width * region->imageExtent.height;
563
564 for (j = 0; j < region->imageExtent.depth; j++) {
565 cmd_draw_meta(cmd, &meta);
566
567 meta.src.layer++;
568 meta.dst.x += meta.width;
569 }
570 }
571}
572
573XGL_VOID XGLAPI intelCmdCloneImageData(
574 XGL_CMD_BUFFER cmdBuffer,
575 XGL_IMAGE srcImage,
576 XGL_IMAGE_STATE srcImageState,
577 XGL_IMAGE destImage,
578 XGL_IMAGE_STATE destImageState)
579{
580 const struct intel_img *src = intel_img(srcImage);
581 XGL_IMAGE_COPY region;
582 XGL_UINT lv;
583
584 memset(&region, 0, sizeof(region));
585 region.srcSubresource.aspect = XGL_IMAGE_ASPECT_COLOR;
586 region.destSubresource.aspect = XGL_IMAGE_ASPECT_COLOR;
587
588 for (lv = 0; lv < src->mip_levels; lv++) {
589 region.srcSubresource.mipLevel = lv;
590 region.destSubresource.mipLevel = lv;
591
592 region.extent.width = u_minify(src->layout.width0, lv);
593 region.extent.height = u_minify(src->layout.height0, lv);
594 region.extent.depth = src->array_size;
595
596 intelCmdCopyImage(cmdBuffer, srcImage, destImage, 1, &region);
597 }
598}
599
600XGL_VOID XGLAPI intelCmdUpdateMemory(
601 XGL_CMD_BUFFER cmdBuffer,
602 XGL_GPU_MEMORY destMem,
603 XGL_GPU_SIZE destOffset,
604 XGL_GPU_SIZE dataSize,
605 const XGL_UINT32* pData)
606{
607 struct intel_cmd *cmd = intel_cmd(cmdBuffer);
608 struct intel_mem *dst = intel_mem(destMem);
609 struct intel_cmd_meta meta;
610 XGL_FORMAT format;
611 XGL_SIZE format_size;
612 uint32_t *ptr;
613 uint32_t offset;
614
615 /* write to dynamic state writer first */
616 offset = cmd_state_pointer(cmd, INTEL_CMD_ITEM_BLOB, 32,
617 (dataSize + 3) / 4, &ptr);
618 memcpy(ptr, pData, dataSize);
619
620 format.channelFormat = cmd_meta_mem_channel_format(cmd,
621 offset, destOffset, dataSize, &format_size);
622 format.numericFormat = XGL_NUM_FMT_UINT;
623
624 memset(&meta, 0, sizeof(meta));
625
626 meta.shader_id = INTEL_DEV_META_FS_COPY_MEM;
627
628 cmd_meta_set_src_for_writer(cmd, INTEL_CMD_WRITER_STATE,
629 offset + dataSize, format, &meta);
630 cmd_meta_set_dst_for_mem(cmd, dst, format, &meta);
631
632 meta.src.x = offset / format_size;
633 meta.dst.x = destOffset / format_size;
634 meta.width = dataSize / format_size;
635 meta.height = 1;
636 meta.samples = 1;
637
638 cmd_draw_meta(cmd, &meta);
639}
640
641XGL_VOID XGLAPI intelCmdFillMemory(
642 XGL_CMD_BUFFER cmdBuffer,
643 XGL_GPU_MEMORY destMem,
644 XGL_GPU_SIZE destOffset,
645 XGL_GPU_SIZE fillSize,
646 XGL_UINT32 data)
647{
648 struct intel_cmd *cmd = intel_cmd(cmdBuffer);
649 struct intel_mem *dst = intel_mem(destMem);
650 struct intel_cmd_meta meta;
651 XGL_FORMAT format;
652 XGL_SIZE format_size;
653
654 /* must be 4-byte aligned */
655 if ((destOffset | fillSize) & 3) {
656 cmd->result = XGL_ERROR_UNKNOWN;
657 return;
658 }
659
660 memset(&meta, 0, sizeof(meta));
661
662 meta.shader_id = INTEL_DEV_META_FS_CLEAR_COLOR;
663
664 meta.clear_val[0] = data;
665 meta.clear_val[1] = data;
666 meta.clear_val[2] = data;
667 meta.clear_val[3] = data;
668
669 format.channelFormat = cmd_meta_mem_channel_format(cmd,
670 0, destOffset, fillSize, &format_size);;
671 format.numericFormat = XGL_NUM_FMT_UINT;
672 cmd_meta_set_dst_for_mem(cmd, dst, format, &meta);
673
674 meta.dst.x = destOffset / format_size;
675 meta.width = fillSize / format_size;
676 meta.height = 1;
677 meta.samples = 1;
678
679 cmd_draw_meta(cmd, &meta);
680}
681
682static void cmd_meta_clear_image(struct intel_cmd *cmd,
683 struct intel_img *img,
684 XGL_FORMAT format,
685 struct intel_cmd_meta *meta,
686 const XGL_IMAGE_SUBRESOURCE_RANGE *range)
687{
688 XGL_UINT mip_levels, array_size;
689 XGL_UINT i, j;
690
691 if (range->baseMipLevel >= img->mip_levels ||
692 range->baseArraySlice >= img->array_size)
693 return;
694
695 mip_levels = img->mip_levels - range->baseMipLevel;
696 if (mip_levels > range->mipLevels)
697 mip_levels = range->mipLevels;
698
699 array_size = img->array_size - range->baseArraySlice;
700 if (array_size > range->arraySize)
701 array_size = range->arraySize;
702
Chia-I Wuc14d1562014-10-17 09:49:22 +0800703 for (i = 0; i < mip_levels; i++) {
Chia-I Wufaaed472014-10-28 14:17:43 +0800704 meta->dst.lod = range->baseMipLevel + i;
705 meta->dst.layer = range->baseArraySlice;
706
Chia-I Wuc14d1562014-10-17 09:49:22 +0800707 meta->width = u_minify(img->layout.width0, meta->dst.lod);
708 meta->height = u_minify(img->layout.height0, meta->dst.lod);
709
710 for (j = 0; j < array_size; j++) {
711 if (range->aspect == XGL_IMAGE_ASPECT_COLOR) {
712 cmd_meta_set_dst_for_img(cmd, img, format,
713 meta->dst.lod, meta->dst.layer, meta);
714
715 cmd_draw_meta(cmd, meta);
716 } else {
Chia-I Wu429a0aa2014-10-24 11:57:51 +0800717 cmd_meta_set_ds_view(cmd, img, meta->dst.lod,
Chia-I Wuc14d1562014-10-17 09:49:22 +0800718 meta->dst.layer, meta);
Chia-I Wu429a0aa2014-10-24 11:57:51 +0800719 cmd_meta_set_ds_state(cmd, range->aspect,
720 meta->clear_val[1], meta);
Chia-I Wuc14d1562014-10-17 09:49:22 +0800721
722 cmd_draw_meta(cmd, meta);
723
Chia-I Wu429a0aa2014-10-24 11:57:51 +0800724 intel_ds_view_destroy(meta->ds.view);
725 intel_ds_state_destroy(meta->ds.state);
Chia-I Wuc14d1562014-10-17 09:49:22 +0800726 }
727
728 meta->dst.layer++;
729 }
Chia-I Wuc14d1562014-10-17 09:49:22 +0800730 }
731}
732
733XGL_VOID XGLAPI intelCmdClearColorImage(
734 XGL_CMD_BUFFER cmdBuffer,
735 XGL_IMAGE image,
736 const XGL_FLOAT color[4],
737 XGL_UINT rangeCount,
738 const XGL_IMAGE_SUBRESOURCE_RANGE* pRanges)
739{
740 struct intel_cmd *cmd = intel_cmd(cmdBuffer);
741 struct intel_img *img = intel_img(image);
742 struct intel_cmd_meta meta;
743 XGL_UINT i;
744
745 memset(&meta, 0, sizeof(meta));
746
747 meta.shader_id = INTEL_DEV_META_FS_CLEAR_COLOR;
748 meta.samples = img->samples;
749
750 meta.clear_val[0] = u_fui(color[0]);
751 meta.clear_val[1] = u_fui(color[1]);
752 meta.clear_val[2] = u_fui(color[2]);
753 meta.clear_val[3] = u_fui(color[3]);
754
755 for (i = 0; i < rangeCount; i++) {
756 cmd_meta_clear_image(cmd, img, img->layout.format,
757 &meta, &pRanges[i]);
758 }
759}
760
761XGL_VOID XGLAPI intelCmdClearColorImageRaw(
762 XGL_CMD_BUFFER cmdBuffer,
763 XGL_IMAGE image,
764 const XGL_UINT32 color[4],
765 XGL_UINT rangeCount,
766 const XGL_IMAGE_SUBRESOURCE_RANGE* pRanges)
767{
768 struct intel_cmd *cmd = intel_cmd(cmdBuffer);
769 struct intel_img *img = intel_img(image);
770 struct intel_cmd_meta meta;
771 XGL_FORMAT format;
772 XGL_UINT i;
773
774 memset(&meta, 0, sizeof(meta));
775
776 meta.shader_id = INTEL_DEV_META_FS_CLEAR_COLOR;
777 meta.samples = img->samples;
778
779 meta.clear_val[0] = color[0];
780 meta.clear_val[1] = color[1];
781 meta.clear_val[2] = color[2];
782 meta.clear_val[3] = color[3];
783
784 format = cmd_meta_img_raw_format(cmd, img->layout.format);
785
786 for (i = 0; i < rangeCount; i++)
787 cmd_meta_clear_image(cmd, img, format, &meta, &pRanges[i]);
788}
789
790XGL_VOID XGLAPI intelCmdClearDepthStencil(
791 XGL_CMD_BUFFER cmdBuffer,
792 XGL_IMAGE image,
793 XGL_FLOAT depth,
794 XGL_UINT32 stencil,
795 XGL_UINT rangeCount,
796 const XGL_IMAGE_SUBRESOURCE_RANGE* pRanges)
797{
798 struct intel_cmd *cmd = intel_cmd(cmdBuffer);
799 struct intel_img *img = intel_img(image);
800 struct intel_cmd_meta meta;
801 XGL_UINT i;
802
803 memset(&meta, 0, sizeof(meta));
804
805 meta.shader_id = INTEL_DEV_META_FS_CLEAR_DEPTH;
806 meta.samples = img->samples;
807
Chia-I Wu429a0aa2014-10-24 11:57:51 +0800808 meta.clear_val[0] = u_fui(depth);
809 meta.clear_val[1] = stencil;
810
Chia-I Wuc14d1562014-10-17 09:49:22 +0800811 for (i = 0; i < rangeCount; i++) {
812 const XGL_IMAGE_SUBRESOURCE_RANGE *range = &pRanges[i];
813
Chia-I Wuc14d1562014-10-17 09:49:22 +0800814 cmd_meta_clear_image(cmd, img, img->layout.format,
815 &meta, range);
816 }
817}
818
819XGL_VOID XGLAPI intelCmdResolveImage(
820 XGL_CMD_BUFFER cmdBuffer,
821 XGL_IMAGE srcImage,
822 XGL_IMAGE destImage,
823 XGL_UINT rectCount,
824 const XGL_IMAGE_RESOLVE* pRects)
825{
826 struct intel_cmd *cmd = intel_cmd(cmdBuffer);
827 struct intel_img *src = intel_img(srcImage);
828 struct intel_img *dst = intel_img(destImage);
829 struct intel_cmd_meta meta;
830 XGL_FORMAT format;
831 XGL_UINT i;
832
833 if (src->samples <= 1 || dst->samples > 1 ||
834 !icd_format_is_equal(src->layout.format, dst->layout.format)) {
835 cmd->result = XGL_ERROR_UNKNOWN;
836 return;
837 }
838
839 memset(&meta, 0, sizeof(meta));
840
841 switch (src->samples) {
842 case 2:
843 default:
844 meta.shader_id = INTEL_DEV_META_FS_RESOLVE_2X;
845 break;
846 case 4:
847 meta.shader_id = INTEL_DEV_META_FS_RESOLVE_4X;
848 break;
849 case 8:
850 meta.shader_id = INTEL_DEV_META_FS_RESOLVE_8X;
851 break;
852 case 16:
853 meta.shader_id = INTEL_DEV_META_FS_RESOLVE_16X;
854 break;
855 }
856
857 meta.samples = 1;
858
859 format = cmd_meta_img_raw_format(cmd, src->layout.format);
860 cmd_meta_set_src_for_img(cmd, src, format, XGL_IMAGE_ASPECT_COLOR, &meta);
861
862 for (i = 0; i < rectCount; i++) {
863 const XGL_IMAGE_RESOLVE *rect = &pRects[i];
864
865 meta.src.lod = rect->srcSubresource.mipLevel;
866 meta.src.layer = rect->srcSubresource.arraySlice;
867 meta.src.x = rect->srcOffset.x;
868 meta.src.y = rect->srcOffset.y;
869
870 meta.dst.lod = rect->destSubresource.mipLevel;
871 meta.dst.layer = rect->destSubresource.arraySlice;
872 meta.dst.x = rect->destOffset.x;
873 meta.dst.y = rect->destOffset.y;
874
875 meta.width = rect->extent.width;
876 meta.height = rect->extent.height;
877
878 cmd_meta_set_dst_for_img(cmd, dst, format,
879 meta.dst.lod, meta.dst.layer, &meta);
880
881 cmd_draw_meta(cmd, &meta);
882 }
883}