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Chia-I Wue54854a2014-08-05 10:23:50 +08001/*
2 * XGL
3 *
4 * Copyright (C) 2014 LunarG, Inc.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included
14 * in all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE.
23 */
24
25#ifndef DEV_H
26#define DEV_H
27
28#include "obj.h"
29#include "gpu.h"
30#include "intel.h"
31
Chia-I Wu49dbee82014-08-06 12:48:47 +080032struct intel_bo;
Chia-I Wue54854a2014-08-05 10:23:50 +080033struct intel_gpu;
34struct intel_queue;
35struct intel_winsys;
36
37struct intel_dev_dbg_msg_filter {
38 XGL_INT msg_code;
39 XGL_DBG_MSG_FILTER filter;
40 bool triggered;
41
42 struct intel_dev_dbg_msg_filter *next;
43};
44
45struct intel_dev_dbg {
46 struct intel_base_dbg base;
47
48 struct intel_dev_dbg_msg_filter *filters;
49};
50
51struct intel_dev {
52 struct intel_base base;
53
54 struct intel_gpu *gpu;
55 struct intel_winsys *winsys;
56 struct intel_queue *queues[INTEL_GPU_ENGINE_COUNT];
57};
58
59struct intel_queue {
60 struct intel_base base;
61
62 struct intel_dev *dev;
Chia-I Wu49dbee82014-08-06 12:48:47 +080063 struct intel_bo *last_submitted_bo;
Chia-I Wue54854a2014-08-05 10:23:50 +080064};
65
66static inline struct intel_dev *intel_dev(XGL_DEVICE dev)
67{
68 return (struct intel_dev *) dev;
69}
70
71static inline struct intel_dev_dbg *intel_dev_dbg(struct intel_dev *dev)
72{
73 return (struct intel_dev_dbg *) dev->base.dbg;
74}
75
76static inline struct intel_queue *intel_queue(XGL_QUEUE queue)
77{
78 return (struct intel_queue *) queue;
79}
80
81XGL_RESULT intel_dev_create(struct intel_gpu *gpu,
82 const XGL_DEVICE_CREATE_INFO *info,
83 struct intel_dev **dev_ret);
84void intel_dev_destroy(struct intel_dev *dev);
85
86void intel_dev_get_heap_props(const struct intel_dev *dev,
87 XGL_MEMORY_HEAP_PROPERTIES *props);
88
89XGL_RESULT intel_dev_add_msg_filter(struct intel_dev *dev,
90 XGL_INT msg_code,
91 XGL_DBG_MSG_FILTER filter);
92
93void intel_dev_remove_msg_filter(struct intel_dev *dev,
94 XGL_INT msg_code);
95
Chia-I Wua207aba2014-08-05 15:13:37 +080096XGL_RESULT XGLAPI intelCreateDevice(
97 XGL_PHYSICAL_GPU gpu,
98 const XGL_DEVICE_CREATE_INFO* pCreateInfo,
99 XGL_DEVICE* pDevice);
100
101XGL_RESULT XGLAPI intelDestroyDevice(
102 XGL_DEVICE device);
103
104XGL_RESULT XGLAPI intelGetMemoryHeapCount(
105 XGL_DEVICE device,
106 XGL_UINT* pCount);
107
108XGL_RESULT XGLAPI intelGetMemoryHeapInfo(
109 XGL_DEVICE device,
110 XGL_UINT heapId,
111 XGL_MEMORY_HEAP_INFO_TYPE infoType,
112 XGL_SIZE* pDataSize,
113 XGL_VOID* pData);
114
Chia-I Wu49dbee82014-08-06 12:48:47 +0800115XGL_RESULT XGLAPI intelGetDeviceQueue(
116 XGL_DEVICE device,
117 XGL_QUEUE_TYPE queueType,
118 XGL_UINT queueIndex,
119 XGL_QUEUE* pQueue);
120
121XGL_RESULT XGLAPI intelQueueSetGlobalMemReferences(
122 XGL_QUEUE queue,
123 XGL_UINT memRefCount,
124 const XGL_MEMORY_REF* pMemRefs);
125
126XGL_RESULT XGLAPI intelQueueWaitIdle(
127 XGL_QUEUE queue);
128
129XGL_RESULT XGLAPI intelDeviceWaitIdle(
130 XGL_DEVICE device);
131
Chia-I Wue54854a2014-08-05 10:23:50 +0800132#endif /* DEV_H */