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Chia-I Wub2755562014-08-20 13:38:52 +08001/*
2 * XGL
3 *
4 * Copyright (C) 2014 LunarG, Inc.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included
14 * in all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE.
23 */
24
Chia-I Wu9f039862014-08-20 15:39:56 +080025#include "genhw/genhw.h"
Chia-I Wub2755562014-08-20 13:38:52 +080026#include "dset.h"
27#include "mem.h"
Chia-I Wu018a3962014-08-21 10:37:52 +080028#include "pipeline.h"
Chia-I Wub2755562014-08-20 13:38:52 +080029#include "state.h"
30#include "view.h"
31#include "cmd_priv.h"
32
Chia-I Wu59c097e2014-08-21 10:51:07 +080033static int translate_primitive_topology(XGL_PRIMITIVE_TOPOLOGY topo)
34{
35 switch (topo) {
36 case XGL_TOPOLOGY_POINT_LIST: return GEN6_3DPRIM_POINTLIST;
37 case XGL_TOPOLOGY_LINE_LIST: return GEN6_3DPRIM_LINELIST;
38 case XGL_TOPOLOGY_LINE_STRIP: return GEN6_3DPRIM_LINESTRIP;
39 case XGL_TOPOLOGY_TRIANGLE_LIST: return GEN6_3DPRIM_TRILIST;
40 case XGL_TOPOLOGY_TRIANGLE_STRIP: return GEN6_3DPRIM_TRISTRIP;
41 case XGL_TOPOLOGY_RECT_LIST: return GEN6_3DPRIM_RECTLIST;
42 case XGL_TOPOLOGY_QUAD_LIST: return GEN6_3DPRIM_QUADLIST;
43 case XGL_TOPOLOGY_QUAD_STRIP: return GEN6_3DPRIM_QUADSTRIP;
44 case XGL_TOPOLOGY_LINE_LIST_ADJ: return GEN6_3DPRIM_LINELIST_ADJ;
45 case XGL_TOPOLOGY_LINE_STRIP_ADJ: return GEN6_3DPRIM_LINESTRIP_ADJ;
46 case XGL_TOPOLOGY_TRIANGLE_LIST_ADJ: return GEN6_3DPRIM_TRILIST_ADJ;
47 case XGL_TOPOLOGY_TRIANGLE_STRIP_ADJ: return GEN6_3DPRIM_TRISTRIP_ADJ;
48 case XGL_TOPOLOGY_PATCH: return GEN7_3DPRIM_PATCHLIST_1;
49 default:
50 assert(!"unknown primitive topology");
51 return GEN6_3DPRIM_POINTLIST;
52 }
53}
54
55static void gen6_3DPRIMITIVE(struct intel_cmd *cmd,
56 XGL_PRIMITIVE_TOPOLOGY topo,
57 bool indexed,
58 uint32_t vertex_count,
59 uint32_t vertex_start,
60 uint32_t instance_count,
61 uint32_t instance_start,
62 uint32_t vertex_base)
63{
64 const uint8_t cmd_len = 6;
65 uint32_t dw0;
66
67 CMD_ASSERT(cmd, 6, 6);
68
69 dw0 = GEN_RENDER_CMD(3D, 3DPRIMITIVE) |
70 translate_primitive_topology(topo) << GEN6_3DPRIM_DW0_TYPE__SHIFT |
71 (cmd_len - 2);
72
73 if (indexed)
74 dw0 |= GEN6_3DPRIM_DW0_ACCESS_RANDOM;
75
76 cmd_reserve(cmd, cmd_len);
77 cmd_write(cmd, dw0);
78 cmd_write(cmd, vertex_count);
79 cmd_write(cmd, vertex_start);
80 cmd_write(cmd, instance_count);
81 cmd_write(cmd, instance_start);
82 cmd_write(cmd, vertex_base);
83}
84
85static void gen7_3DPRIMITIVE(struct intel_cmd *cmd,
86 XGL_PRIMITIVE_TOPOLOGY topo,
87 bool indexed,
88 uint32_t vertex_count,
89 uint32_t vertex_start,
90 uint32_t instance_count,
91 uint32_t instance_start,
92 uint32_t vertex_base)
93{
94 const uint8_t cmd_len = 7;
95 uint32_t dw0, dw1;
96
97 CMD_ASSERT(cmd, 7, 7.5);
98
99 dw0 = GEN_RENDER_CMD(3D, 3DPRIMITIVE) | (cmd_len - 2);
100 dw1 = translate_primitive_topology(topo) << GEN7_3DPRIM_DW1_TYPE__SHIFT;
101
102 if (indexed)
103 dw1 |= GEN7_3DPRIM_DW1_ACCESS_RANDOM;
104
105 cmd_reserve(cmd, cmd_len);
106 cmd_write(cmd, dw0);
107 cmd_write(cmd, dw1);
108 cmd_write(cmd, vertex_count);
109 cmd_write(cmd, vertex_start);
110 cmd_write(cmd, instance_count);
111 cmd_write(cmd, instance_start);
112 cmd_write(cmd, vertex_base);
113}
114
115static void gen6_3DSTATE_INDEX_BUFFER(struct intel_cmd *cmd,
116 struct intel_mem *mem,
117 XGL_GPU_SIZE offset,
118 XGL_INDEX_TYPE type,
119 bool enable_cut_index)
120{
121 const uint8_t cmd_len = 3;
122 uint32_t dw0, end_offset;
123 unsigned offset_align;
124
125 CMD_ASSERT(cmd, 6, 7.5);
126
127 dw0 = GEN_RENDER_CMD(3D, 3DSTATE_INDEX_BUFFER) | (cmd_len - 2);
128
129 /* the bit is moved to 3DSTATE_VF */
130 if (cmd_gen(cmd) >= INTEL_GEN(7.5))
131 assert(!enable_cut_index);
132 if (enable_cut_index)
133 dw0 |= GEN6_IB_DW0_CUT_INDEX_ENABLE;
134
135 switch (type) {
136 case XGL_INDEX_8:
137 dw0 |= GEN6_IB_DW0_FORMAT_BYTE;
138 offset_align = 1;
139 break;
140 case XGL_INDEX_16:
141 dw0 |= GEN6_IB_DW0_FORMAT_WORD;
142 offset_align = 2;
143 break;
144 case XGL_INDEX_32:
145 dw0 |= GEN6_IB_DW0_FORMAT_DWORD;
146 offset_align = 4;
147 break;
148 default:
149 cmd->result = XGL_ERROR_INVALID_VALUE;
150 return;
151 break;
152 }
153
154 if (offset % offset_align) {
155 cmd->result = XGL_ERROR_INVALID_VALUE;
156 return;
157 }
158
159 /* aligned and inclusive */
160 end_offset = mem->size - (mem->size % offset_align) - 1;
161
162 cmd_reserve(cmd, cmd_len);
163 cmd_write(cmd, dw0);
164 cmd_write_r(cmd, offset, mem, INTEL_DOMAIN_VERTEX, 0);
165 cmd_write_r(cmd, end_offset, mem, INTEL_DOMAIN_VERTEX, 0);
166}
167
Chia-I Wub2755562014-08-20 13:38:52 +0800168XGL_VOID XGLAPI intelCmdBindPipeline(
169 XGL_CMD_BUFFER cmdBuffer,
170 XGL_PIPELINE_BIND_POINT pipelineBindPoint,
171 XGL_PIPELINE pipeline)
172{
173 struct intel_cmd *cmd = intel_cmd(cmdBuffer);
174
175 switch (pipelineBindPoint) {
176 case XGL_PIPELINE_BIND_POINT_COMPUTE:
Chia-I Wu018a3962014-08-21 10:37:52 +0800177 cmd->bind.pipeline.compute = intel_pipeline(pipeline);
Chia-I Wub2755562014-08-20 13:38:52 +0800178 break;
179 case XGL_PIPELINE_BIND_POINT_GRAPHICS:
Chia-I Wu018a3962014-08-21 10:37:52 +0800180 cmd->bind.pipeline.graphics = intel_pipeline(pipeline);
Chia-I Wub2755562014-08-20 13:38:52 +0800181 break;
182 default:
183 break;
184 }
185}
186
187XGL_VOID XGLAPI intelCmdBindPipelineDelta(
188 XGL_CMD_BUFFER cmdBuffer,
189 XGL_PIPELINE_BIND_POINT pipelineBindPoint,
190 XGL_PIPELINE_DELTA delta)
191{
192 struct intel_cmd *cmd = intel_cmd(cmdBuffer);
193
194 switch (pipelineBindPoint) {
195 case XGL_PIPELINE_BIND_POINT_COMPUTE:
196 cmd->bind.pipeline.compute_delta = delta;
197 break;
198 case XGL_PIPELINE_BIND_POINT_GRAPHICS:
199 cmd->bind.pipeline.graphics_delta = delta;
200 break;
201 default:
202 break;
203 }
204}
205
206XGL_VOID XGLAPI intelCmdBindStateObject(
207 XGL_CMD_BUFFER cmdBuffer,
208 XGL_STATE_BIND_POINT stateBindPoint,
209 XGL_STATE_OBJECT state)
210{
211 struct intel_cmd *cmd = intel_cmd(cmdBuffer);
212
213 switch (stateBindPoint) {
214 case XGL_STATE_BIND_VIEWPORT:
215 cmd->bind.state.viewport =
216 intel_viewport_state((XGL_VIEWPORT_STATE_OBJECT) state);
217 break;
218 case XGL_STATE_BIND_RASTER:
219 cmd->bind.state.raster =
220 intel_raster_state((XGL_RASTER_STATE_OBJECT) state);
221 break;
222 case XGL_STATE_BIND_DEPTH_STENCIL:
223 cmd->bind.state.ds =
224 intel_ds_state((XGL_DEPTH_STENCIL_STATE_OBJECT) state);
225 break;
226 case XGL_STATE_BIND_COLOR_BLEND:
227 cmd->bind.state.blend =
228 intel_blend_state((XGL_COLOR_BLEND_STATE_OBJECT) state);
229 break;
230 case XGL_STATE_BIND_MSAA:
231 cmd->bind.state.msaa =
232 intel_msaa_state((XGL_MSAA_STATE_OBJECT) state);
233 break;
234 default:
235 break;
236 }
237}
238
239XGL_VOID XGLAPI intelCmdBindDescriptorSet(
240 XGL_CMD_BUFFER cmdBuffer,
241 XGL_PIPELINE_BIND_POINT pipelineBindPoint,
242 XGL_UINT index,
243 XGL_DESCRIPTOR_SET descriptorSet,
244 XGL_UINT slotOffset)
245{
246 struct intel_cmd *cmd = intel_cmd(cmdBuffer);
247 struct intel_dset *dset = intel_dset(descriptorSet);
248
249 assert(!index);
250
251 switch (pipelineBindPoint) {
252 case XGL_PIPELINE_BIND_POINT_COMPUTE:
253 cmd->bind.dset.compute = dset;
254 cmd->bind.dset.compute_offset = slotOffset;
255 break;
256 case XGL_PIPELINE_BIND_POINT_GRAPHICS:
257 cmd->bind.dset.graphics = dset;
258 cmd->bind.dset.graphics_offset = slotOffset;
259 break;
260 default:
261 break;
262 }
263}
264
265XGL_VOID XGLAPI intelCmdBindDynamicMemoryView(
266 XGL_CMD_BUFFER cmdBuffer,
267 XGL_PIPELINE_BIND_POINT pipelineBindPoint,
268 const XGL_MEMORY_VIEW_ATTACH_INFO* pMemView)
269{
270 struct intel_cmd *cmd = intel_cmd(cmdBuffer);
271
272 switch (pipelineBindPoint) {
273 case XGL_PIPELINE_BIND_POINT_COMPUTE:
274 intel_mem_view_init(&cmd->bind.mem_view.compute, cmd->dev, pMemView);
275 break;
276 case XGL_PIPELINE_BIND_POINT_GRAPHICS:
277 intel_mem_view_init(&cmd->bind.mem_view.graphics, cmd->dev, pMemView);
278 break;
279 default:
280 break;
281 }
282}
283
284XGL_VOID XGLAPI intelCmdBindIndexData(
285 XGL_CMD_BUFFER cmdBuffer,
286 XGL_GPU_MEMORY mem_,
287 XGL_GPU_SIZE offset,
288 XGL_INDEX_TYPE indexType)
289{
290 struct intel_cmd *cmd = intel_cmd(cmdBuffer);
291 struct intel_mem *mem = intel_mem(mem_);
292
Chia-I Wu9f039862014-08-20 15:39:56 +0800293 if (cmd_gen(cmd) >= INTEL_GEN(7.5)) {
294 gen6_3DSTATE_INDEX_BUFFER(cmd, mem, offset, indexType, false);
295 } else {
296 cmd->bind.index.mem = mem;
297 cmd->bind.index.offset = offset;
298 cmd->bind.index.type = indexType;
299 }
Chia-I Wub2755562014-08-20 13:38:52 +0800300}
301
302XGL_VOID XGLAPI intelCmdBindAttachments(
303 XGL_CMD_BUFFER cmdBuffer,
304 XGL_UINT colorAttachmentCount,
305 const XGL_COLOR_ATTACHMENT_BIND_INFO* pColorAttachments,
306 const XGL_DEPTH_STENCIL_BIND_INFO* pDepthStencilAttachment)
307{
308 struct intel_cmd *cmd = intel_cmd(cmdBuffer);
309 XGL_UINT i;
310
311 for (i = 0; i < colorAttachmentCount; i++) {
312 const XGL_COLOR_ATTACHMENT_BIND_INFO *att = &pColorAttachments[i];
313 struct intel_rt_view *rt = intel_rt_view(att->view);
314
315 cmd->bind.att.rt[i] = rt;
316 }
317
318 cmd->bind.att.rt_count = colorAttachmentCount;
319
320 if (pDepthStencilAttachment) {
321 struct intel_ds_view *ds = intel_ds_view(pDepthStencilAttachment->view);
322 cmd->bind.att.ds = ds;
323 } else {
324 cmd->bind.att.ds = NULL;
325 }
326}
327
328XGL_VOID XGLAPI intelCmdDraw(
329 XGL_CMD_BUFFER cmdBuffer,
330 XGL_UINT firstVertex,
331 XGL_UINT vertexCount,
332 XGL_UINT firstInstance,
333 XGL_UINT instanceCount)
334{
Chia-I Wu59c097e2014-08-21 10:51:07 +0800335 struct intel_cmd *cmd = intel_cmd(cmdBuffer);
336 XGL_PRIMITIVE_TOPOLOGY topo;
337
338 /* TODO emit bounded states */
339 topo = XGL_TOPOLOGY_TRIANGLE_LIST;
340
341 if (cmd_gen(cmd) >= INTEL_GEN(7)) {
342 gen7_3DPRIMITIVE(cmd, topo, false, vertexCount, firstVertex,
343 instanceCount, firstInstance, 0);
344 } else {
345 gen6_3DPRIMITIVE(cmd, topo, false, vertexCount, firstVertex,
346 instanceCount, firstInstance, 0);
347 }
Chia-I Wub2755562014-08-20 13:38:52 +0800348}
349
350XGL_VOID XGLAPI intelCmdDrawIndexed(
351 XGL_CMD_BUFFER cmdBuffer,
352 XGL_UINT firstIndex,
353 XGL_UINT indexCount,
354 XGL_INT vertexOffset,
355 XGL_UINT firstInstance,
356 XGL_UINT instanceCount)
357{
Chia-I Wu59c097e2014-08-21 10:51:07 +0800358 struct intel_cmd *cmd = intel_cmd(cmdBuffer);
359 XGL_PRIMITIVE_TOPOLOGY topo;
360
361 /* TODO emit bounded states */
362 topo = XGL_TOPOLOGY_TRIANGLE_LIST;
363
364 if (cmd_gen(cmd) >= INTEL_GEN(7)) {
365 gen7_3DPRIMITIVE(cmd, topo, true, indexCount, firstIndex,
366 instanceCount, firstInstance, vertexOffset);
367 } else {
368 gen6_3DPRIMITIVE(cmd, topo, true, indexCount, firstIndex,
369 instanceCount, firstInstance, vertexOffset);
370 }
Chia-I Wub2755562014-08-20 13:38:52 +0800371}
372
373XGL_VOID XGLAPI intelCmdDrawIndirect(
374 XGL_CMD_BUFFER cmdBuffer,
375 XGL_GPU_MEMORY mem,
376 XGL_GPU_SIZE offset,
377 XGL_UINT32 count,
378 XGL_UINT32 stride)
379{
Chia-I Wu59c097e2014-08-21 10:51:07 +0800380 struct intel_cmd *cmd = intel_cmd(cmdBuffer);
381
382 cmd->result = XGL_ERROR_UNKNOWN;
Chia-I Wub2755562014-08-20 13:38:52 +0800383}
384
385XGL_VOID XGLAPI intelCmdDrawIndexedIndirect(
386 XGL_CMD_BUFFER cmdBuffer,
387 XGL_GPU_MEMORY mem,
388 XGL_GPU_SIZE offset,
389 XGL_UINT32 count,
390 XGL_UINT32 stride)
391{
Chia-I Wu59c097e2014-08-21 10:51:07 +0800392 struct intel_cmd *cmd = intel_cmd(cmdBuffer);
393
394 cmd->result = XGL_ERROR_UNKNOWN;
Chia-I Wub2755562014-08-20 13:38:52 +0800395}
396
397XGL_VOID XGLAPI intelCmdDispatch(
398 XGL_CMD_BUFFER cmdBuffer,
399 XGL_UINT x,
400 XGL_UINT y,
401 XGL_UINT z)
402{
Chia-I Wu59c097e2014-08-21 10:51:07 +0800403 struct intel_cmd *cmd = intel_cmd(cmdBuffer);
404
405 cmd->result = XGL_ERROR_UNKNOWN;
Chia-I Wub2755562014-08-20 13:38:52 +0800406}
407
408XGL_VOID XGLAPI intelCmdDispatchIndirect(
409 XGL_CMD_BUFFER cmdBuffer,
410 XGL_GPU_MEMORY mem,
411 XGL_GPU_SIZE offset)
412{
Chia-I Wu59c097e2014-08-21 10:51:07 +0800413 struct intel_cmd *cmd = intel_cmd(cmdBuffer);
414
415 cmd->result = XGL_ERROR_UNKNOWN;
Chia-I Wub2755562014-08-20 13:38:52 +0800416}