blob: 84e1e28d9aa55458c25e1d57d602b2c0c622165a [file] [log] [blame]
Chia-I Wuf8385062015-01-04 16:27:24 +08001/*
2 * XGL
3 *
4 * Copyright (C) 2015 LunarG, Inc.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included
14 * in all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE.
23 *
24 * Authors:
25 * Chia-I Wu <olv@lunarg.com>
26 */
27
28#include "buf.h"
29#include "cmd.h"
30#include "dev.h"
31#include "gpu.h"
32#include "img.h"
33#include "sampler.h"
34#include "view.h"
35#include "desc.h"
36
37enum intel_desc_surface_type {
38 INTEL_DESC_SURFACE_UNUSED,
39 INTEL_DESC_SURFACE_BUF,
40 INTEL_DESC_SURFACE_IMG,
41};
42
43struct intel_desc_surface {
44 const struct intel_mem *mem;
45 bool read_only;
46
47 enum intel_desc_surface_type type;
48 union {
49 const void *unused;
50 const struct intel_buf_view *buf;
51 const struct intel_img_view *img;
52 } u;
53};
54
55struct intel_desc_sampler {
56 const struct intel_sampler *sampler;
57};
58
Chia-I Wu7732cb22015-03-26 15:27:55 +080059bool intel_desc_iter_init_for_binding(struct intel_desc_iter *iter,
60 const struct intel_desc_layout *layout,
61 uint32_t binding_index, uint32_t array_base)
62{
63 const struct intel_desc_layout_binding *binding;
64
65 if (binding_index >= layout->binding_count ||
66 array_base >= layout->bindings[binding_index].array_size)
67 return false;
68
69 binding = &layout->bindings[binding_index];
70
71 iter->type = binding->type;
72 iter->increment = binding->increment;
73 iter->size = binding->array_size;
74
75 intel_desc_offset_mad(&iter->begin, &binding->increment,
76 &binding->offset, array_base);
77 intel_desc_offset_add(&iter->end, &iter->begin, &binding->increment);
78 iter->cur = array_base;
79
80 return true;
81}
82
83static bool desc_iter_init_for_update(struct intel_desc_iter *iter,
84 const struct intel_desc_set *set,
85 XGL_DESCRIPTOR_TYPE type,
86 uint32_t binding_index, uint32_t array_base)
87{
88 if (!intel_desc_iter_init_for_binding(iter, set->layout,
89 binding_index, array_base) || iter->type != type)
90 return false;
91
92 intel_desc_offset_add(&iter->begin, &iter->begin, &set->region_begin);
93 intel_desc_offset_add(&iter->end, &iter->end, &set->region_begin);
94
95 return true;
96}
97
98bool intel_desc_iter_advance(struct intel_desc_iter *iter)
99{
100 if (iter->cur >= iter->size)
101 return false;
102
103 iter->cur++;
104
105 iter->begin = iter->end;
106 intel_desc_offset_add(&iter->end, &iter->end, &iter->increment);
107
108 return true;
109}
110
Chia-I Wu8d24b3b2015-03-26 13:14:16 +0800111static bool desc_region_init_desc_sizes(struct intel_desc_region *region,
112 const struct intel_gpu *gpu)
Chia-I Wuf8385062015-01-04 16:27:24 +0800113{
Chia-I Wu8d24b3b2015-03-26 13:14:16 +0800114 region->surface_desc_size = sizeof(struct intel_desc_surface);
115 region->sampler_desc_size = sizeof(struct intel_desc_sampler);
Chia-I Wuf8385062015-01-04 16:27:24 +0800116
117 return true;
118}
119
Chia-I Wu8d24b3b2015-03-26 13:14:16 +0800120XGL_RESULT intel_desc_region_create(struct intel_dev *dev,
121 struct intel_desc_region **region_ret)
Chia-I Wuf8385062015-01-04 16:27:24 +0800122{
123 const uint32_t surface_count = 16384;
124 const uint32_t sampler_count = 16384;
Chia-I Wu8d24b3b2015-03-26 13:14:16 +0800125 struct intel_desc_region *region;
Chia-I Wuf8385062015-01-04 16:27:24 +0800126
Chia-I Wu8d24b3b2015-03-26 13:14:16 +0800127 region = intel_alloc(dev, sizeof(*region), 0, XGL_SYSTEM_ALLOC_INTERNAL);
128 if (!region)
Chia-I Wuf8385062015-01-04 16:27:24 +0800129 return XGL_ERROR_OUT_OF_MEMORY;
130
Chia-I Wu8d24b3b2015-03-26 13:14:16 +0800131 memset(region, 0, sizeof(*region));
Chia-I Wuf8385062015-01-04 16:27:24 +0800132
Chia-I Wu8d24b3b2015-03-26 13:14:16 +0800133 if (!desc_region_init_desc_sizes(region, dev->gpu)) {
134 intel_free(dev, region);
Chia-I Wuf8385062015-01-04 16:27:24 +0800135 return XGL_ERROR_UNKNOWN;
136 }
137
Chia-I Wu8d24b3b2015-03-26 13:14:16 +0800138 intel_desc_offset_set(&region->size,
139 region->surface_desc_size * surface_count,
140 region->sampler_desc_size * sampler_count);
Chia-I Wuf8385062015-01-04 16:27:24 +0800141
Chia-I Wu8d24b3b2015-03-26 13:14:16 +0800142 region->surfaces = intel_alloc(dev, region->size.surface,
Chia-I Wuf8385062015-01-04 16:27:24 +0800143 64, XGL_SYSTEM_ALLOC_INTERNAL);
Chia-I Wu8d24b3b2015-03-26 13:14:16 +0800144 if (!region->surfaces) {
145 intel_free(dev, region);
Chia-I Wuf8385062015-01-04 16:27:24 +0800146 return XGL_ERROR_OUT_OF_MEMORY;
147 }
148
Chia-I Wu8d24b3b2015-03-26 13:14:16 +0800149 region->samplers = intel_alloc(dev, region->size.sampler,
Chia-I Wuf8385062015-01-04 16:27:24 +0800150 64, XGL_SYSTEM_ALLOC_INTERNAL);
Chia-I Wu8d24b3b2015-03-26 13:14:16 +0800151 if (!region->samplers) {
152 intel_free(dev, region->surfaces);
153 intel_free(dev, region);
Chia-I Wuf8385062015-01-04 16:27:24 +0800154 return XGL_ERROR_OUT_OF_MEMORY;
155 }
156
Chia-I Wu8d24b3b2015-03-26 13:14:16 +0800157 *region_ret = region;
Chia-I Wuf8385062015-01-04 16:27:24 +0800158
159 return XGL_SUCCESS;
160}
161
Chia-I Wu8d24b3b2015-03-26 13:14:16 +0800162void intel_desc_region_destroy(struct intel_dev *dev,
163 struct intel_desc_region *region)
Chia-I Wuf8385062015-01-04 16:27:24 +0800164{
Chia-I Wu8d24b3b2015-03-26 13:14:16 +0800165 intel_free(dev, region->samplers);
166 intel_free(dev, region->surfaces);
167 intel_free(dev, region);
Chia-I Wuf8385062015-01-04 16:27:24 +0800168}
169
170/**
Chia-I Wu8d24b3b2015-03-26 13:14:16 +0800171 * Get the size of a descriptor in the region.
Chia-I Wuf8385062015-01-04 16:27:24 +0800172 */
Chia-I Wu8d24b3b2015-03-26 13:14:16 +0800173static XGL_RESULT desc_region_get_desc_size(const struct intel_desc_region *region,
Chia-I Wuf8385062015-01-04 16:27:24 +0800174 XGL_DESCRIPTOR_TYPE type,
175 struct intel_desc_offset *size)
176{
177 uint32_t surface_size = 0, sampler_size = 0;
178
179 switch (type) {
180 case XGL_DESCRIPTOR_TYPE_SAMPLER:
Chia-I Wu8d24b3b2015-03-26 13:14:16 +0800181 sampler_size = region->sampler_desc_size;
Chia-I Wuf8385062015-01-04 16:27:24 +0800182 break;
183 case XGL_DESCRIPTOR_TYPE_SAMPLER_TEXTURE:
Chia-I Wu8d24b3b2015-03-26 13:14:16 +0800184 surface_size = region->surface_desc_size;
185 sampler_size = region->sampler_desc_size;
Chia-I Wuf8385062015-01-04 16:27:24 +0800186 break;
187 case XGL_DESCRIPTOR_TYPE_TEXTURE:
188 case XGL_DESCRIPTOR_TYPE_TEXTURE_BUFFER:
189 case XGL_DESCRIPTOR_TYPE_IMAGE:
190 case XGL_DESCRIPTOR_TYPE_IMAGE_BUFFER:
191 case XGL_DESCRIPTOR_TYPE_UNIFORM_BUFFER:
192 case XGL_DESCRIPTOR_TYPE_SHADER_STORAGE_BUFFER:
Chia-I Wuf8385062015-01-04 16:27:24 +0800193 case XGL_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC:
194 case XGL_DESCRIPTOR_TYPE_SHADER_STORAGE_BUFFER_DYNAMIC:
Chia-I Wu8d24b3b2015-03-26 13:14:16 +0800195 surface_size = region->surface_desc_size;
Chia-I Wuf8385062015-01-04 16:27:24 +0800196 break;
197 default:
198 assert(!"unknown descriptor type");
199 return XGL_ERROR_INVALID_VALUE;
200 break;
201 }
202
203 intel_desc_offset_set(size, surface_size, sampler_size);
204
205 return XGL_SUCCESS;
206}
207
Chia-I Wu8d24b3b2015-03-26 13:14:16 +0800208XGL_RESULT intel_desc_region_alloc(struct intel_desc_region *region,
209 const XGL_DESCRIPTOR_POOL_CREATE_INFO *info,
210 struct intel_desc_offset *begin,
211 struct intel_desc_offset *end)
Chia-I Wuf8385062015-01-04 16:27:24 +0800212{
213 uint32_t surface_size = 0, sampler_size = 0;
214 struct intel_desc_offset alloc;
215 uint32_t i;
216
217 /* calculate sizes needed */
218 for (i = 0; i < info->count; i++) {
219 const XGL_DESCRIPTOR_TYPE_COUNT *tc = &info->pTypeCount[i];
220 struct intel_desc_offset size;
221 XGL_RESULT ret;
222
Chia-I Wu8d24b3b2015-03-26 13:14:16 +0800223 ret = desc_region_get_desc_size(region, tc->type, &size);
Chia-I Wuf8385062015-01-04 16:27:24 +0800224 if (ret != XGL_SUCCESS)
225 return ret;
226
227 surface_size += size.surface * tc->count;
228 sampler_size += size.sampler * tc->count;
229 }
230
231 intel_desc_offset_set(&alloc, surface_size, sampler_size);
232
Chia-I Wu8d24b3b2015-03-26 13:14:16 +0800233 *begin = region->cur;
234 intel_desc_offset_add(end, &region->cur, &alloc);
Chia-I Wuf8385062015-01-04 16:27:24 +0800235
Chia-I Wu8d24b3b2015-03-26 13:14:16 +0800236 if (!intel_desc_offset_within(end, &region->size))
Chia-I Wuf8385062015-01-04 16:27:24 +0800237 return XGL_ERROR_OUT_OF_MEMORY;
238
239 /* increment the writer pointer */
Chia-I Wu8d24b3b2015-03-26 13:14:16 +0800240 region->cur = *end;
Chia-I Wuf8385062015-01-04 16:27:24 +0800241
242 return XGL_SUCCESS;
243}
244
Chia-I Wu8d24b3b2015-03-26 13:14:16 +0800245static void desc_region_validate_begin_end(const struct intel_desc_region *region,
246 const struct intel_desc_offset *begin,
247 const struct intel_desc_offset *end)
Chia-I Wuf8385062015-01-04 16:27:24 +0800248{
Chia-I Wu8d24b3b2015-03-26 13:14:16 +0800249 assert(begin->surface % region->surface_desc_size == 0 &&
250 begin->sampler % region->sampler_desc_size == 0);
251 assert(end->surface % region->surface_desc_size == 0 &&
252 end->sampler % region->sampler_desc_size == 0);
253 assert(intel_desc_offset_within(end, &region->size));
Chia-I Wuf8385062015-01-04 16:27:24 +0800254}
255
Chia-I Wu8d24b3b2015-03-26 13:14:16 +0800256void intel_desc_region_free(struct intel_desc_region *region,
257 const struct intel_desc_offset *begin,
258 const struct intel_desc_offset *end)
Chia-I Wuf8385062015-01-04 16:27:24 +0800259{
Chia-I Wu8d24b3b2015-03-26 13:14:16 +0800260 desc_region_validate_begin_end(region, begin, end);
Chia-I Wuf8385062015-01-04 16:27:24 +0800261
262 /* is it ok not to reclaim? */
263}
264
Chia-I Wu8d24b3b2015-03-26 13:14:16 +0800265XGL_RESULT intel_desc_region_begin_update(struct intel_desc_region *region,
266 XGL_DESCRIPTOR_UPDATE_MODE mode)
Chia-I Wuf8385062015-01-04 16:27:24 +0800267{
268 /* no-op */
269 return XGL_SUCCESS;
270}
271
Chia-I Wu8d24b3b2015-03-26 13:14:16 +0800272XGL_RESULT intel_desc_region_end_update(struct intel_desc_region *region,
273 struct intel_cmd *cmd)
Chia-I Wuf8385062015-01-04 16:27:24 +0800274{
275 /* No pipelined update. cmd_draw() will do the work. */
276 return XGL_SUCCESS;
277}
278
Chia-I Wu8d24b3b2015-03-26 13:14:16 +0800279void intel_desc_region_clear(struct intel_desc_region *region,
280 const struct intel_desc_offset *begin,
281 const struct intel_desc_offset *end)
Chia-I Wuf8385062015-01-04 16:27:24 +0800282{
283 uint32_t i;
284
Chia-I Wu8d24b3b2015-03-26 13:14:16 +0800285 desc_region_validate_begin_end(region, begin, end);
Chia-I Wuf8385062015-01-04 16:27:24 +0800286
Chia-I Wu8d24b3b2015-03-26 13:14:16 +0800287 for (i = begin->surface; i < end->surface; i += region->surface_desc_size) {
Chia-I Wuf8385062015-01-04 16:27:24 +0800288 struct intel_desc_surface *desc = (struct intel_desc_surface *)
Chia-I Wu8d24b3b2015-03-26 13:14:16 +0800289 ((char *) region->surfaces + i);
Chia-I Wuf8385062015-01-04 16:27:24 +0800290
291 desc->mem = NULL;
292 desc->type = INTEL_DESC_SURFACE_UNUSED;
293 desc->u.unused = NULL;
294 }
295
Chia-I Wu8d24b3b2015-03-26 13:14:16 +0800296 for (i = begin->sampler; i < end->sampler; i += region->sampler_desc_size) {
Chia-I Wuf8385062015-01-04 16:27:24 +0800297 struct intel_desc_sampler *desc = (struct intel_desc_sampler *)
Chia-I Wu8d24b3b2015-03-26 13:14:16 +0800298 ((char *) region->samplers + i);
Chia-I Wuf8385062015-01-04 16:27:24 +0800299
300 desc->sampler = NULL;
301 }
302}
303
Chia-I Wu8d24b3b2015-03-26 13:14:16 +0800304void intel_desc_region_update(struct intel_desc_region *region,
305 const struct intel_desc_offset *begin,
306 const struct intel_desc_offset *end,
307 const struct intel_desc_surface *surfaces,
308 const struct intel_desc_sampler *samplers)
Chia-I Wuf8385062015-01-04 16:27:24 +0800309{
Chia-I Wu8d24b3b2015-03-26 13:14:16 +0800310 desc_region_validate_begin_end(region, begin, end);
Chia-I Wuf8385062015-01-04 16:27:24 +0800311
312 if (begin->surface < end->surface) {
Chia-I Wu8d24b3b2015-03-26 13:14:16 +0800313 memcpy((char *) region->surfaces + begin->surface, surfaces,
Chia-I Wuf8385062015-01-04 16:27:24 +0800314 end->surface - begin->surface);
315 }
316
317 if (begin->sampler < end->sampler) {
Chia-I Wu8d24b3b2015-03-26 13:14:16 +0800318 memcpy((char *) region->samplers + begin->sampler, samplers,
Chia-I Wuf8385062015-01-04 16:27:24 +0800319 end->sampler - begin->sampler);
320 }
321}
322
Chia-I Wu8d24b3b2015-03-26 13:14:16 +0800323void intel_desc_region_copy(struct intel_desc_region *region,
324 const struct intel_desc_offset *begin,
325 const struct intel_desc_offset *end,
326 const struct intel_desc_offset *src)
Chia-I Wuf8385062015-01-04 16:27:24 +0800327{
328 struct intel_desc_offset src_end;
329 const struct intel_desc_surface *surfaces;
330 const struct intel_desc_sampler *samplers;
331
332 /* no overlap */
333 assert(intel_desc_offset_within(src, begin) ||
334 intel_desc_offset_within(end, src));
335
Chia-I Wu8d24b3b2015-03-26 13:14:16 +0800336 /* no read past region */
Chia-I Wuf8385062015-01-04 16:27:24 +0800337 intel_desc_offset_sub(&src_end, end, begin);
338 intel_desc_offset_add(&src_end, src, &src_end);
Chia-I Wu8d24b3b2015-03-26 13:14:16 +0800339 assert(intel_desc_offset_within(&src_end, &region->size));
Chia-I Wuf8385062015-01-04 16:27:24 +0800340
341 surfaces = (const struct intel_desc_surface *)
Chia-I Wu8d24b3b2015-03-26 13:14:16 +0800342 ((const char *) region->surfaces + src->surface);
Tony Barbour379e0a72015-02-05 11:09:34 -0700343 samplers = (const struct intel_desc_sampler *)
Chia-I Wu8d24b3b2015-03-26 13:14:16 +0800344 ((const char *) region->samplers + src->sampler);
Chia-I Wuf8385062015-01-04 16:27:24 +0800345
Chia-I Wu8d24b3b2015-03-26 13:14:16 +0800346 intel_desc_region_update(region, begin, end, surfaces, samplers);
Chia-I Wuf8385062015-01-04 16:27:24 +0800347}
348
Chia-I Wu8d24b3b2015-03-26 13:14:16 +0800349static void desc_pool_destroy(struct intel_obj *obj)
Chia-I Wuf8385062015-01-04 16:27:24 +0800350{
Chia-I Wu8d24b3b2015-03-26 13:14:16 +0800351 struct intel_desc_pool *pool = intel_desc_pool_from_obj(obj);
Chia-I Wuf8385062015-01-04 16:27:24 +0800352
Chia-I Wu8d24b3b2015-03-26 13:14:16 +0800353 intel_desc_pool_destroy(pool);
Chia-I Wuf8385062015-01-04 16:27:24 +0800354}
355
Chia-I Wu8d24b3b2015-03-26 13:14:16 +0800356XGL_RESULT intel_desc_pool_create(struct intel_dev *dev,
357 XGL_DESCRIPTOR_POOL_USAGE usage,
358 uint32_t max_sets,
359 const XGL_DESCRIPTOR_POOL_CREATE_INFO *info,
360 struct intel_desc_pool **pool_ret)
Chia-I Wuf8385062015-01-04 16:27:24 +0800361{
Chia-I Wu8d24b3b2015-03-26 13:14:16 +0800362 struct intel_desc_pool *pool;
Chia-I Wuf8385062015-01-04 16:27:24 +0800363 XGL_RESULT ret;
364
Chia-I Wu8d24b3b2015-03-26 13:14:16 +0800365 pool = (struct intel_desc_pool *) intel_base_create(&dev->base.handle,
366 sizeof(*pool), dev->base.dbg, XGL_DBG_OBJECT_DESCRIPTOR_POOL,
Chia-I Wu545c2e12015-02-22 13:19:54 +0800367 info, 0);
Chia-I Wu8d24b3b2015-03-26 13:14:16 +0800368 if (!pool)
Chia-I Wuf8385062015-01-04 16:27:24 +0800369 return XGL_ERROR_OUT_OF_MEMORY;
370
Chia-I Wu8d24b3b2015-03-26 13:14:16 +0800371 pool->dev = dev;
Chia-I Wuf8385062015-01-04 16:27:24 +0800372
Chia-I Wu8d24b3b2015-03-26 13:14:16 +0800373 ret = intel_desc_region_alloc(dev->desc_region, info,
374 &pool->region_begin, &pool->region_end);
Chia-I Wuf8385062015-01-04 16:27:24 +0800375 if (ret != XGL_SUCCESS) {
Chia-I Wu8d24b3b2015-03-26 13:14:16 +0800376 intel_base_destroy(&pool->obj.base);
Chia-I Wuf8385062015-01-04 16:27:24 +0800377 return ret;
378 }
379
380 /* point to head */
Chia-I Wu8d24b3b2015-03-26 13:14:16 +0800381 pool->cur = pool->region_begin;
Chia-I Wuf8385062015-01-04 16:27:24 +0800382
Chia-I Wu8d24b3b2015-03-26 13:14:16 +0800383 pool->obj.destroy = desc_pool_destroy;
Chia-I Wuf8385062015-01-04 16:27:24 +0800384
Chia-I Wu8d24b3b2015-03-26 13:14:16 +0800385 *pool_ret = pool;
Chia-I Wuf8385062015-01-04 16:27:24 +0800386
387 return XGL_SUCCESS;
388}
389
Chia-I Wu8d24b3b2015-03-26 13:14:16 +0800390void intel_desc_pool_destroy(struct intel_desc_pool *pool)
Chia-I Wuf8385062015-01-04 16:27:24 +0800391{
Chia-I Wu8d24b3b2015-03-26 13:14:16 +0800392 intel_desc_region_free(pool->dev->desc_region,
393 &pool->region_begin, &pool->region_end);
394 intel_base_destroy(&pool->obj.base);
Chia-I Wuf8385062015-01-04 16:27:24 +0800395}
396
Chia-I Wu8d24b3b2015-03-26 13:14:16 +0800397XGL_RESULT intel_desc_pool_alloc(struct intel_desc_pool *pool,
398 const struct intel_desc_layout *layout,
399 struct intel_desc_offset *begin,
400 struct intel_desc_offset *end)
Chia-I Wuf8385062015-01-04 16:27:24 +0800401{
Chia-I Wu8d24b3b2015-03-26 13:14:16 +0800402 *begin = pool->cur;
403 intel_desc_offset_add(end, &pool->cur, &layout->region_size);
Chia-I Wuf8385062015-01-04 16:27:24 +0800404
Chia-I Wu8d24b3b2015-03-26 13:14:16 +0800405 if (!intel_desc_offset_within(end, &pool->region_end))
Chia-I Wuf8385062015-01-04 16:27:24 +0800406 return XGL_ERROR_OUT_OF_MEMORY;
407
408 /* increment the writer pointer */
Chia-I Wu8d24b3b2015-03-26 13:14:16 +0800409 pool->cur = *end;
Chia-I Wuf8385062015-01-04 16:27:24 +0800410
411 return XGL_SUCCESS;
412}
413
Chia-I Wudee95612015-03-26 15:23:52 +0800414void intel_desc_pool_reset(struct intel_desc_pool *pool)
Chia-I Wuf8385062015-01-04 16:27:24 +0800415{
416 /* reset to head */
Chia-I Wu8d24b3b2015-03-26 13:14:16 +0800417 pool->cur = pool->region_begin;
Chia-I Wuf8385062015-01-04 16:27:24 +0800418}
419
420static void desc_set_destroy(struct intel_obj *obj)
421{
422 struct intel_desc_set *set = intel_desc_set_from_obj(obj);
423
424 intel_desc_set_destroy(set);
425}
426
427XGL_RESULT intel_desc_set_create(struct intel_dev *dev,
Chia-I Wu8d24b3b2015-03-26 13:14:16 +0800428 struct intel_desc_pool *pool,
Chia-I Wuf8385062015-01-04 16:27:24 +0800429 XGL_DESCRIPTOR_SET_USAGE usage,
430 const struct intel_desc_layout *layout,
431 struct intel_desc_set **set_ret)
432{
433 struct intel_desc_set *set;
434 XGL_RESULT ret;
435
Chia-I Wu545c2e12015-02-22 13:19:54 +0800436 set = (struct intel_desc_set *) intel_base_create(&dev->base.handle,
437 sizeof(*set), dev->base.dbg, XGL_DBG_OBJECT_DESCRIPTOR_SET,
438 NULL, 0);
Chia-I Wuf8385062015-01-04 16:27:24 +0800439 if (!set)
440 return XGL_ERROR_OUT_OF_MEMORY;
441
Chia-I Wu8d24b3b2015-03-26 13:14:16 +0800442 set->region = dev->desc_region;
443 ret = intel_desc_pool_alloc(pool, layout,
444 &set->region_begin, &set->region_end);
Chia-I Wuf8385062015-01-04 16:27:24 +0800445 if (ret != XGL_SUCCESS) {
446 intel_base_destroy(&set->obj.base);
447 return ret;
448 }
449
450 set->layout = layout;
451
452 set->obj.destroy = desc_set_destroy;
453
454 *set_ret = set;
455
456 return XGL_SUCCESS;
457}
458
459void intel_desc_set_destroy(struct intel_desc_set *set)
460{
461 intel_base_destroy(&set->obj.base);
462}
463
Chia-I Wuf8385062015-01-04 16:27:24 +0800464static bool desc_set_img_layout_read_only(XGL_IMAGE_LAYOUT layout)
465{
466 switch (layout) {
467 case XGL_IMAGE_LAYOUT_DEPTH_STENCIL_READ_ONLY_OPTIMAL:
468 case XGL_IMAGE_LAYOUT_SHADER_READ_ONLY_OPTIMAL:
469 case XGL_IMAGE_LAYOUT_TRANSFER_SOURCE_OPTIMAL:
470 return true;
471 default:
472 return false;
473 }
474}
475
476void intel_desc_set_update_samplers(struct intel_desc_set *set,
477 const XGL_UPDATE_SAMPLERS *update)
478{
Chia-I Wu7732cb22015-03-26 15:27:55 +0800479 struct intel_desc_iter iter;
Chia-I Wuf8385062015-01-04 16:27:24 +0800480 uint32_t i;
481
Chia-I Wu7732cb22015-03-26 15:27:55 +0800482 if (!desc_iter_init_for_update(&iter, set, XGL_DESCRIPTOR_TYPE_SAMPLER,
483 update->binding, update->arrayIndex))
Chia-I Wuf8385062015-01-04 16:27:24 +0800484 return;
485
486 for (i = 0; i < update->count; i++) {
487 const struct intel_sampler *sampler =
488 intel_sampler((XGL_SAMPLER) update->pSamplers[i]);
489 struct intel_desc_sampler desc;
490
Chia-I Wuf8385062015-01-04 16:27:24 +0800491 desc.sampler = sampler;
Chia-I Wu7732cb22015-03-26 15:27:55 +0800492 intel_desc_region_update(set->region, &iter.begin, &iter.end,
493 NULL, &desc);
Chia-I Wuf8385062015-01-04 16:27:24 +0800494
Chia-I Wu7732cb22015-03-26 15:27:55 +0800495 if (!intel_desc_iter_advance(&iter))
Chia-I Wuf8385062015-01-04 16:27:24 +0800496 break;
497 }
498}
499
500void intel_desc_set_update_sampler_textures(struct intel_desc_set *set,
501 const XGL_UPDATE_SAMPLER_TEXTURES *update)
502{
Chia-I Wu7732cb22015-03-26 15:27:55 +0800503 struct intel_desc_iter iter;
504 const struct intel_desc_layout_binding *binding;
Chia-I Wuf8385062015-01-04 16:27:24 +0800505 uint32_t i;
506
Chia-I Wu7732cb22015-03-26 15:27:55 +0800507 if (!desc_iter_init_for_update(&iter, set, XGL_DESCRIPTOR_TYPE_SAMPLER_TEXTURE,
508 update->binding, update->arrayIndex))
Chia-I Wuf8385062015-01-04 16:27:24 +0800509 return;
510
Chia-I Wu7732cb22015-03-26 15:27:55 +0800511 binding = &set->layout->bindings[update->binding];
512
513 if (binding->immutable_sampler) {
514 struct intel_desc_offset end;
515 struct intel_desc_sampler sampler_desc;
516
517 assert(!iter.increment.sampler);
518 intel_desc_offset_set(&end, iter.begin.surface,
519 iter.begin.sampler + set->region->sampler_desc_size);
520
521 sampler_desc.sampler = binding->immutable_sampler;
522 intel_desc_region_update(set->region, &iter.begin, &end,
523 NULL, &sampler_desc);
524 }
525
Chia-I Wuf8385062015-01-04 16:27:24 +0800526 for (i = 0; i < update->count; i++) {
527 const struct intel_sampler *sampler =
Chia-I Wu7732cb22015-03-26 15:27:55 +0800528 intel_sampler(update->pSamplerImageViews[i].sampler);
Chia-I Wuf8385062015-01-04 16:27:24 +0800529 const XGL_IMAGE_VIEW_ATTACH_INFO *info =
530 update->pSamplerImageViews[i].pImageView;
531 const struct intel_img_view *view = intel_img_view(info->view);
532 struct intel_desc_surface view_desc;
533 struct intel_desc_sampler sampler_desc;
534
Chia-I Wuf8385062015-01-04 16:27:24 +0800535 view_desc.mem = view->img->obj.mem;
536 view_desc.read_only = desc_set_img_layout_read_only(info->layout);
537 view_desc.type = INTEL_DESC_SURFACE_IMG;
538 view_desc.u.img = view;
539
540 sampler_desc.sampler = sampler;
541
Chia-I Wu7732cb22015-03-26 15:27:55 +0800542 intel_desc_region_update(set->region, &iter.begin, &iter.end,
543 &view_desc, &sampler_desc);
Chia-I Wuf8385062015-01-04 16:27:24 +0800544
Chia-I Wu7732cb22015-03-26 15:27:55 +0800545 if (!intel_desc_iter_advance(&iter))
Chia-I Wuf8385062015-01-04 16:27:24 +0800546 break;
547 }
548}
549
550void intel_desc_set_update_images(struct intel_desc_set *set,
551 const XGL_UPDATE_IMAGES *update)
552{
Chia-I Wu7732cb22015-03-26 15:27:55 +0800553 struct intel_desc_iter iter;
Chia-I Wuf8385062015-01-04 16:27:24 +0800554 uint32_t i;
555
Chia-I Wu7732cb22015-03-26 15:27:55 +0800556 if (!desc_iter_init_for_update(&iter, set, update->descriptorType,
557 update->binding, update->arrayIndex))
Chia-I Wuf8385062015-01-04 16:27:24 +0800558 return;
559
560 for (i = 0; i < update->count; i++) {
Chia-I Wu7732cb22015-03-26 15:27:55 +0800561 const XGL_IMAGE_VIEW_ATTACH_INFO *info = &update->pImageViews[i];
Chia-I Wuf8385062015-01-04 16:27:24 +0800562 const struct intel_img_view *view = intel_img_view(info->view);
563 struct intel_desc_surface desc;
564
Chia-I Wuf8385062015-01-04 16:27:24 +0800565 desc.mem = view->img->obj.mem;
566 desc.read_only = desc_set_img_layout_read_only(info->layout);
567 desc.type = INTEL_DESC_SURFACE_IMG;
568 desc.u.img = view;
Chia-I Wu7732cb22015-03-26 15:27:55 +0800569 intel_desc_region_update(set->region, &iter.begin, &iter.end,
570 &desc, NULL);
Chia-I Wuf8385062015-01-04 16:27:24 +0800571
Chia-I Wu7732cb22015-03-26 15:27:55 +0800572 if (!intel_desc_iter_advance(&iter))
Chia-I Wuf8385062015-01-04 16:27:24 +0800573 break;
574 }
575}
576
577void intel_desc_set_update_buffers(struct intel_desc_set *set,
578 const XGL_UPDATE_BUFFERS *update)
579{
Chia-I Wu7732cb22015-03-26 15:27:55 +0800580 struct intel_desc_iter iter;
Chia-I Wuf8385062015-01-04 16:27:24 +0800581 uint32_t i;
582
Chia-I Wu7732cb22015-03-26 15:27:55 +0800583 if (!desc_iter_init_for_update(&iter, set, update->descriptorType,
584 update->binding, update->arrayIndex))
Chia-I Wuf8385062015-01-04 16:27:24 +0800585 return;
586
587 for (i = 0; i < update->count; i++) {
Chia-I Wu7732cb22015-03-26 15:27:55 +0800588 const XGL_BUFFER_VIEW_ATTACH_INFO *info = &update->pBufferViews[i];
Chia-I Wuf8385062015-01-04 16:27:24 +0800589 const struct intel_buf_view *view = intel_buf_view(info->view);
590 struct intel_desc_surface desc;
591
Chia-I Wuf8385062015-01-04 16:27:24 +0800592 desc.mem = view->buf->obj.mem;
593 desc.read_only = false;
594 desc.type = INTEL_DESC_SURFACE_BUF;
595 desc.u.buf = view;
Chia-I Wu7732cb22015-03-26 15:27:55 +0800596 intel_desc_region_update(set->region, &iter.begin, &iter.end,
597 &desc, NULL);
Chia-I Wuf8385062015-01-04 16:27:24 +0800598
Chia-I Wu7732cb22015-03-26 15:27:55 +0800599 if (!intel_desc_iter_advance(&iter))
Chia-I Wuf8385062015-01-04 16:27:24 +0800600 break;
601 }
602}
603
604void intel_desc_set_update_as_copy(struct intel_desc_set *set,
605 const XGL_UPDATE_AS_COPY *update)
606{
607 const struct intel_desc_set *src_set =
608 intel_desc_set(update->descriptorSet);
Chia-I Wu7732cb22015-03-26 15:27:55 +0800609 struct intel_desc_iter iter, src_iter;
610 struct intel_desc_offset begin, src_begin;
Chia-I Wuf8385062015-01-04 16:27:24 +0800611 uint32_t i;
612
613 /* disallow combined sampler textures */
614 if (update->descriptorType == XGL_DESCRIPTOR_TYPE_SAMPLER_TEXTURE)
615 return;
616
Chia-I Wu7732cb22015-03-26 15:27:55 +0800617 if (!desc_iter_init_for_update(&iter, set, update->descriptorType,
618 update->binding, update->arrayElement) ||
619 !desc_iter_init_for_update(&src_iter, src_set, update->descriptorType,
620 update->binding, update->arrayElement))
Chia-I Wuf8385062015-01-04 16:27:24 +0800621 return;
622
Chia-I Wu7732cb22015-03-26 15:27:55 +0800623 /* save the begin offsets */
624 begin = iter.begin;
625 src_begin = src_iter.begin;
Chia-I Wuf8385062015-01-04 16:27:24 +0800626
Chia-I Wu7732cb22015-03-26 15:27:55 +0800627 /* advance to the end */
Chia-I Wuf8385062015-01-04 16:27:24 +0800628 for (i = 0; i < update->count; i++) {
Chia-I Wu7732cb22015-03-26 15:27:55 +0800629 if (!intel_desc_iter_advance(&iter) ||
630 !intel_desc_iter_advance(&src_iter)) {
631 /* out of bound */
632 return;
633 }
Chia-I Wuf8385062015-01-04 16:27:24 +0800634 }
Chia-I Wuf8385062015-01-04 16:27:24 +0800635
Chia-I Wu7732cb22015-03-26 15:27:55 +0800636 intel_desc_region_copy(set->region, &begin, &iter.end, &src_begin);
Chia-I Wuf8385062015-01-04 16:27:24 +0800637}
638
Chia-I Wu2f0cba82015-02-12 10:15:42 -0700639static void desc_set_read(const struct intel_desc_set *set,
640 const struct intel_desc_offset *offset,
641 const struct intel_desc_surface **surface,
642 const struct intel_desc_sampler **sampler)
643{
644 struct intel_desc_offset begin, end;
645
Chia-I Wu8d24b3b2015-03-26 13:14:16 +0800646 intel_desc_offset_add(&begin, &set->region_begin, offset);
Chia-I Wu2f0cba82015-02-12 10:15:42 -0700647 intel_desc_offset_set(&end, 0, 0);
648
649 if (surface) {
650 *surface = (const struct intel_desc_surface *)
Chia-I Wu8d24b3b2015-03-26 13:14:16 +0800651 ((const char *) set->region->surfaces + begin.surface);
Chia-I Wu2f0cba82015-02-12 10:15:42 -0700652
Chia-I Wu8d24b3b2015-03-26 13:14:16 +0800653 end.surface = set->region->surface_desc_size;
Chia-I Wu2f0cba82015-02-12 10:15:42 -0700654 }
655
656 if (sampler) {
657 *sampler = (const struct intel_desc_sampler *)
Chia-I Wu8d24b3b2015-03-26 13:14:16 +0800658 ((const char *) set->region->samplers + begin.sampler);
Chia-I Wu2f0cba82015-02-12 10:15:42 -0700659
Chia-I Wu8d24b3b2015-03-26 13:14:16 +0800660 end.sampler = set->region->sampler_desc_size;
Chia-I Wu2f0cba82015-02-12 10:15:42 -0700661 }
662
663 intel_desc_offset_add(&end, &begin, &end);
Chia-I Wu8d24b3b2015-03-26 13:14:16 +0800664 desc_region_validate_begin_end(set->region, &begin, &end);
Chia-I Wu2f0cba82015-02-12 10:15:42 -0700665}
666
667void intel_desc_set_read_surface(const struct intel_desc_set *set,
668 const struct intel_desc_offset *offset,
669 XGL_PIPELINE_SHADER_STAGE stage,
670 const struct intel_mem **mem,
671 bool *read_only,
672 const uint32_t **cmd,
673 uint32_t *cmd_len)
674{
675 const struct intel_desc_surface *desc;
676
677 desc_set_read(set, offset, &desc, NULL);
678
679 *mem = desc->mem;
680 *read_only = desc->read_only;
681 switch (desc->type) {
682 case INTEL_DESC_SURFACE_BUF:
683 *cmd = (stage == XGL_SHADER_STAGE_FRAGMENT) ?
684 desc->u.buf->fs_cmd : desc->u.buf->cmd;
685 *cmd_len = desc->u.buf->cmd_len;
686 break;
687 case INTEL_DESC_SURFACE_IMG:
688 *cmd = desc->u.img->cmd;
689 *cmd_len = desc->u.img->cmd_len;
690 break;
691 case INTEL_DESC_SURFACE_UNUSED:
692 default:
693 *cmd = NULL;
694 *cmd_len = 0;
695 break;
696 }
697}
698
699void intel_desc_set_read_sampler(const struct intel_desc_set *set,
700 const struct intel_desc_offset *offset,
701 const struct intel_sampler **sampler)
702{
703 const struct intel_desc_sampler *desc;
704
705 desc_set_read(set, offset, NULL, &desc);
706
707 *sampler = desc->sampler;
708}
709
Chia-I Wuf8385062015-01-04 16:27:24 +0800710static void desc_layout_destroy(struct intel_obj *obj)
711{
712 struct intel_desc_layout *layout = intel_desc_layout_from_obj(obj);
713
714 intel_desc_layout_destroy(layout);
715}
716
Chia-I Wufc9d9132015-03-26 15:04:41 +0800717static XGL_RESULT desc_layout_init_bindings(struct intel_desc_layout *layout,
718 const struct intel_desc_region *region,
719 const XGL_DESCRIPTOR_SET_LAYOUT_CREATE_INFO *info)
Chia-I Wuf8385062015-01-04 16:27:24 +0800720{
721 struct intel_desc_offset offset;
Chia-I Wu7732cb22015-03-26 15:27:55 +0800722 uint32_t i;
Chia-I Wuf8385062015-01-04 16:27:24 +0800723 XGL_RESULT ret;
724
Chia-I Wu7732cb22015-03-26 15:27:55 +0800725 intel_desc_offset_set(&offset, 0, 0);
Chia-I Wuf8385062015-01-04 16:27:24 +0800726
Chia-I Wufc9d9132015-03-26 15:04:41 +0800727 /* allocate bindings */
728 layout->bindings = intel_alloc(layout, sizeof(layout->bindings[0]) *
729 info->count, 0, XGL_SYSTEM_ALLOC_INTERNAL);
730 if (!layout->bindings)
731 return XGL_ERROR_OUT_OF_MEMORY;
732
733 memset(layout->bindings, 0, sizeof(layout->bindings[0]) * info->count);
734 layout->binding_count = info->count;
735
736 /* initialize bindings */
737 for (i = 0; i < info->count; i++) {
738 const XGL_DESCRIPTOR_SET_LAYOUT_BINDING *lb = &info->pBinding[i];
739 struct intel_desc_layout_binding *binding = &layout->bindings[i];
Chia-I Wuf8385062015-01-04 16:27:24 +0800740 struct intel_desc_offset size;
741
Chia-I Wufc9d9132015-03-26 15:04:41 +0800742 switch (lb->descriptorType) {
743 case XGL_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC:
744 case XGL_DESCRIPTOR_TYPE_SHADER_STORAGE_BUFFER_DYNAMIC:
Chia-I Wufc9d9132015-03-26 15:04:41 +0800745 layout->dynamic_desc_count += lb->count;
746 break;
747 default:
748 break;
749 }
750
Chia-I Wu7732cb22015-03-26 15:27:55 +0800751 /* lb->stageFlags does not gain us anything */
752 binding->type = lb->descriptorType;
753 binding->array_size = lb->count;
754 binding->offset = offset;
755
Chia-I Wufc9d9132015-03-26 15:04:41 +0800756 ret = desc_region_get_desc_size(region,
757 lb->descriptorType, &size);
Chia-I Wuf8385062015-01-04 16:27:24 +0800758 if (ret != XGL_SUCCESS)
759 return ret;
760
Chia-I Wufc9d9132015-03-26 15:04:41 +0800761 if (lb->immutableSampler != XGL_NULL_HANDLE) {
762 binding->immutable_sampler = intel_sampler(lb->immutableSampler);
Chia-I Wuf8385062015-01-04 16:27:24 +0800763 /* do not increment sampler offset */
Chia-I Wufc9d9132015-03-26 15:04:41 +0800764 intel_desc_offset_set(&binding->increment, size.surface, 0);
Chia-I Wuf8385062015-01-04 16:27:24 +0800765 } else {
Chia-I Wufc9d9132015-03-26 15:04:41 +0800766 binding->immutable_sampler = NULL;
767 binding->increment = size;
Chia-I Wuf8385062015-01-04 16:27:24 +0800768 }
769
Chia-I Wu7732cb22015-03-26 15:27:55 +0800770 /* increment offset */
Chia-I Wufc9d9132015-03-26 15:04:41 +0800771 intel_desc_offset_mad(&size, &binding->increment, &size,
772 lb->count - 1);
Chia-I Wuf8385062015-01-04 16:27:24 +0800773 intel_desc_offset_add(&offset, &offset, &size);
Chia-I Wuf8385062015-01-04 16:27:24 +0800774 }
775
Chia-I Wu8d24b3b2015-03-26 13:14:16 +0800776 layout->region_size = offset;
Chia-I Wuf8385062015-01-04 16:27:24 +0800777
778 return XGL_SUCCESS;
779}
780
Chia-I Wuf8385062015-01-04 16:27:24 +0800781XGL_RESULT intel_desc_layout_create(struct intel_dev *dev,
Chia-I Wuf8385062015-01-04 16:27:24 +0800782 const XGL_DESCRIPTOR_SET_LAYOUT_CREATE_INFO *info,
783 struct intel_desc_layout **layout_ret)
784{
785 struct intel_desc_layout *layout;
786 XGL_RESULT ret;
787
Chia-I Wu545c2e12015-02-22 13:19:54 +0800788 layout = (struct intel_desc_layout *) intel_base_create(&dev->base.handle,
789 sizeof(*layout), dev->base.dbg,
790 XGL_DBG_OBJECT_DESCRIPTOR_SET_LAYOUT, info, 0);
Chia-I Wuf8385062015-01-04 16:27:24 +0800791 if (!layout)
792 return XGL_ERROR_OUT_OF_MEMORY;
793
Chia-I Wu7732cb22015-03-26 15:27:55 +0800794 ret = desc_layout_init_bindings(layout, dev->desc_region, info);
Chia-I Wuf8385062015-01-04 16:27:24 +0800795 if (ret != XGL_SUCCESS) {
796 intel_desc_layout_destroy(layout);
797 return ret;
798 }
799
800 layout->obj.destroy = desc_layout_destroy;
801
802 *layout_ret = layout;
803
804 return XGL_SUCCESS;
805}
806
807void intel_desc_layout_destroy(struct intel_desc_layout *layout)
808{
Chia-I Wufc9d9132015-03-26 15:04:41 +0800809 intel_free(layout, layout->bindings);
Chia-I Wuf8385062015-01-04 16:27:24 +0800810 intel_base_destroy(&layout->obj.base);
811}
812
Chia-I Wu7732cb22015-03-26 15:27:55 +0800813static void desc_layout_chain_destroy(struct intel_obj *obj)
Chia-I Wuf8385062015-01-04 16:27:24 +0800814{
Chia-I Wu7732cb22015-03-26 15:27:55 +0800815 struct intel_desc_layout_chain *chain =
816 intel_desc_layout_chain_from_obj(obj);
Chia-I Wuf8385062015-01-04 16:27:24 +0800817
Chia-I Wu7732cb22015-03-26 15:27:55 +0800818 intel_desc_layout_chain_destroy(chain);
Chia-I Wuf8385062015-01-04 16:27:24 +0800819}
820
Chia-I Wu7732cb22015-03-26 15:27:55 +0800821XGL_RESULT intel_desc_layout_chain_create(struct intel_dev *dev,
822 const XGL_DESCRIPTOR_SET_LAYOUT *layouts,
823 uint32_t count,
824 struct intel_desc_layout_chain **chain_ret)
Chia-I Wuf8385062015-01-04 16:27:24 +0800825{
Chia-I Wu7732cb22015-03-26 15:27:55 +0800826 struct intel_desc_layout_chain *chain;
827 uint32_t i;
828
829 chain = (struct intel_desc_layout_chain *)
830 intel_base_create(&dev->base.handle, sizeof(*chain), dev->base.dbg,
831 XGL_DBG_OBJECT_DESCRIPTOR_SET_LAYOUT_CHAIN, NULL, 0);
832 if (!chain)
833 return XGL_ERROR_OUT_OF_MEMORY;
834
835 chain->layouts = intel_alloc(chain, sizeof(chain->layouts[0]) * count,
836 0, XGL_SYSTEM_ALLOC_INTERNAL);
837 if (!chain) {
838 intel_desc_layout_chain_destroy(chain);
839 return XGL_ERROR_OUT_OF_MEMORY;
Chia-I Wuf8385062015-01-04 16:27:24 +0800840 }
841
Chia-I Wu7732cb22015-03-26 15:27:55 +0800842 for (i = 0; i < count; i++)
843 chain->layouts[i] = intel_desc_layout(layouts[i]);
Chia-I Wuf8385062015-01-04 16:27:24 +0800844
Chia-I Wu7732cb22015-03-26 15:27:55 +0800845 chain->layout_count = count;
Chia-I Wuf8385062015-01-04 16:27:24 +0800846
Chia-I Wu7732cb22015-03-26 15:27:55 +0800847 chain->obj.destroy = desc_layout_chain_destroy;
848
849 *chain_ret = chain;
850
851 return XGL_SUCCESS;
Chia-I Wuf8385062015-01-04 16:27:24 +0800852}
853
Chia-I Wu7732cb22015-03-26 15:27:55 +0800854void intel_desc_layout_chain_destroy(struct intel_desc_layout_chain *chain)
Chia-I Wuf8385062015-01-04 16:27:24 +0800855{
Chia-I Wu7732cb22015-03-26 15:27:55 +0800856 if (chain->layouts)
857 intel_free(chain, chain->layouts);
858 intel_base_destroy(&chain->obj.base);
Chia-I Wuf8385062015-01-04 16:27:24 +0800859}
860
Chia-I Wude26bdf2015-02-18 15:47:12 -0700861ICD_EXPORT XGL_RESULT XGLAPI xglCreateDescriptorSetLayout(
Chia-I Wuf8385062015-01-04 16:27:24 +0800862 XGL_DEVICE device,
Chia-I Wufc9d9132015-03-26 15:04:41 +0800863 const XGL_DESCRIPTOR_SET_LAYOUT_CREATE_INFO* pCreateInfo,
Chia-I Wuf8385062015-01-04 16:27:24 +0800864 XGL_DESCRIPTOR_SET_LAYOUT* pSetLayout)
865{
866 struct intel_dev *dev = intel_dev(device);
Chia-I Wuf8385062015-01-04 16:27:24 +0800867
Chia-I Wu7732cb22015-03-26 15:27:55 +0800868 return intel_desc_layout_create(dev, pCreateInfo,
Chia-I Wuf8385062015-01-04 16:27:24 +0800869 (struct intel_desc_layout **) pSetLayout);
870}
871
Chia-I Wu7732cb22015-03-26 15:27:55 +0800872ICD_EXPORT XGL_RESULT XGLAPI xglCreateDescriptorSetLayoutChain(
873 XGL_DEVICE device,
874 uint32_t setLayoutArrayCount,
875 const XGL_DESCRIPTOR_SET_LAYOUT* pSetLayoutArray,
876 XGL_DESCRIPTOR_SET_LAYOUT_CHAIN* pLayoutChain)
877{
878 struct intel_dev *dev = intel_dev(device);
879
880 return intel_desc_layout_chain_create(dev,
881 pSetLayoutArray, setLayoutArrayCount,
882 (struct intel_desc_layout_chain **) pLayoutChain);
883}
884
Chia-I Wu8d24b3b2015-03-26 13:14:16 +0800885ICD_EXPORT XGL_RESULT XGLAPI xglBeginDescriptorPoolUpdate(
Chia-I Wuf8385062015-01-04 16:27:24 +0800886 XGL_DEVICE device,
887 XGL_DESCRIPTOR_UPDATE_MODE updateMode)
888{
889 struct intel_dev *dev = intel_dev(device);
Chia-I Wu8d24b3b2015-03-26 13:14:16 +0800890 struct intel_desc_region *region = dev->desc_region;
Chia-I Wuf8385062015-01-04 16:27:24 +0800891
Chia-I Wu8d24b3b2015-03-26 13:14:16 +0800892 return intel_desc_region_begin_update(region, updateMode);
Chia-I Wuf8385062015-01-04 16:27:24 +0800893}
894
Chia-I Wu8d24b3b2015-03-26 13:14:16 +0800895ICD_EXPORT XGL_RESULT XGLAPI xglEndDescriptorPoolUpdate(
Chia-I Wuf8385062015-01-04 16:27:24 +0800896 XGL_DEVICE device,
897 XGL_CMD_BUFFER cmd_)
898{
899 struct intel_dev *dev = intel_dev(device);
Chia-I Wu8d24b3b2015-03-26 13:14:16 +0800900 struct intel_desc_region *region = dev->desc_region;
Chia-I Wuf8385062015-01-04 16:27:24 +0800901 struct intel_cmd *cmd = intel_cmd(cmd_);
902
Chia-I Wu8d24b3b2015-03-26 13:14:16 +0800903 return intel_desc_region_end_update(region, cmd);
Chia-I Wuf8385062015-01-04 16:27:24 +0800904}
905
Chia-I Wu8d24b3b2015-03-26 13:14:16 +0800906ICD_EXPORT XGL_RESULT XGLAPI xglCreateDescriptorPool(
Chia-I Wuf8385062015-01-04 16:27:24 +0800907 XGL_DEVICE device,
Chia-I Wu8d24b3b2015-03-26 13:14:16 +0800908 XGL_DESCRIPTOR_POOL_USAGE poolUsage,
Mark Lobodzinskie2d07a52015-01-29 08:55:56 -0600909 uint32_t maxSets,
Chia-I Wu8d24b3b2015-03-26 13:14:16 +0800910 const XGL_DESCRIPTOR_POOL_CREATE_INFO* pCreateInfo,
911 XGL_DESCRIPTOR_POOL* pDescriptorPool)
Chia-I Wuf8385062015-01-04 16:27:24 +0800912{
913 struct intel_dev *dev = intel_dev(device);
914
Chia-I Wu8d24b3b2015-03-26 13:14:16 +0800915 return intel_desc_pool_create(dev, poolUsage, maxSets, pCreateInfo,
916 (struct intel_desc_pool **) pDescriptorPool);
Chia-I Wuf8385062015-01-04 16:27:24 +0800917}
918
Chia-I Wudee95612015-03-26 15:23:52 +0800919ICD_EXPORT XGL_RESULT XGLAPI xglResetDescriptorPool(
Chia-I Wu8d24b3b2015-03-26 13:14:16 +0800920 XGL_DESCRIPTOR_POOL descriptorPool)
Chia-I Wuf8385062015-01-04 16:27:24 +0800921{
Chia-I Wu8d24b3b2015-03-26 13:14:16 +0800922 struct intel_desc_pool *pool = intel_desc_pool(descriptorPool);
Chia-I Wuf8385062015-01-04 16:27:24 +0800923
Chia-I Wudee95612015-03-26 15:23:52 +0800924 intel_desc_pool_reset(pool);
Chia-I Wuf8385062015-01-04 16:27:24 +0800925
926 return XGL_SUCCESS;
927}
928
Chia-I Wude26bdf2015-02-18 15:47:12 -0700929ICD_EXPORT XGL_RESULT XGLAPI xglAllocDescriptorSets(
Chia-I Wu8d24b3b2015-03-26 13:14:16 +0800930 XGL_DESCRIPTOR_POOL descriptorPool,
Chia-I Wuf8385062015-01-04 16:27:24 +0800931 XGL_DESCRIPTOR_SET_USAGE setUsage,
Mark Lobodzinskie2d07a52015-01-29 08:55:56 -0600932 uint32_t count,
Chia-I Wuf8385062015-01-04 16:27:24 +0800933 const XGL_DESCRIPTOR_SET_LAYOUT* pSetLayouts,
934 XGL_DESCRIPTOR_SET* pDescriptorSets,
Mark Lobodzinskie2d07a52015-01-29 08:55:56 -0600935 uint32_t* pCount)
Chia-I Wuf8385062015-01-04 16:27:24 +0800936{
Chia-I Wu8d24b3b2015-03-26 13:14:16 +0800937 struct intel_desc_pool *pool = intel_desc_pool(descriptorPool);
938 struct intel_dev *dev = pool->dev;
Chia-I Wuf8385062015-01-04 16:27:24 +0800939 XGL_RESULT ret = XGL_SUCCESS;
940 uint32_t i;
941
942 for (i = 0; i < count; i++) {
943 const struct intel_desc_layout *layout =
944 intel_desc_layout((XGL_DESCRIPTOR_SET_LAYOUT) pSetLayouts[i]);
945
Chia-I Wu8d24b3b2015-03-26 13:14:16 +0800946 ret = intel_desc_set_create(dev, pool, setUsage, layout,
Chia-I Wuf8385062015-01-04 16:27:24 +0800947 (struct intel_desc_set **) &pDescriptorSets[i]);
948 if (ret != XGL_SUCCESS)
949 break;
950 }
951
952 if (pCount)
953 *pCount = i;
954
955 return ret;
956}
957
Chia-I Wude26bdf2015-02-18 15:47:12 -0700958ICD_EXPORT void XGLAPI xglClearDescriptorSets(
Chia-I Wu8d24b3b2015-03-26 13:14:16 +0800959 XGL_DESCRIPTOR_POOL descriptorPool,
Mark Lobodzinskie2d07a52015-01-29 08:55:56 -0600960 uint32_t count,
Chia-I Wuf8385062015-01-04 16:27:24 +0800961 const XGL_DESCRIPTOR_SET* pDescriptorSets)
962{
963 uint32_t i;
964
965 for (i = 0; i < count; i++) {
966 struct intel_desc_set *set =
967 intel_desc_set((XGL_DESCRIPTOR_SET) pDescriptorSets[i]);
968
Chia-I Wu8d24b3b2015-03-26 13:14:16 +0800969 intel_desc_region_clear(set->region, &set->region_begin, &set->region_end);
Chia-I Wuf8385062015-01-04 16:27:24 +0800970 }
971}
972
Chia-I Wude26bdf2015-02-18 15:47:12 -0700973ICD_EXPORT void XGLAPI xglUpdateDescriptors(
Chia-I Wuf8385062015-01-04 16:27:24 +0800974 XGL_DESCRIPTOR_SET descriptorSet,
Chia-I Wu7732cb22015-03-26 15:27:55 +0800975 uint32_t updateCount,
976 const void** ppUpdateArray)
Chia-I Wuf8385062015-01-04 16:27:24 +0800977{
978 struct intel_desc_set *set = intel_desc_set(descriptorSet);
Chia-I Wu7732cb22015-03-26 15:27:55 +0800979 uint32_t i;
Chia-I Wuf8385062015-01-04 16:27:24 +0800980
Chia-I Wu7732cb22015-03-26 15:27:55 +0800981 for (i = 0; i < updateCount; i++) {
982 const union {
983 struct {
984 XGL_STRUCTURE_TYPE sType;
985 const void* pNext;
986 } common;
Chia-I Wuf8385062015-01-04 16:27:24 +0800987
Chia-I Wu7732cb22015-03-26 15:27:55 +0800988 XGL_UPDATE_SAMPLERS samplers;
989 XGL_UPDATE_SAMPLER_TEXTURES sampler_textures;
990 XGL_UPDATE_IMAGES images;
991 XGL_UPDATE_BUFFERS buffers;
992 XGL_UPDATE_AS_COPY as_copy;
993 } *u = ppUpdateArray[i];
994
Chia-I Wuf8385062015-01-04 16:27:24 +0800995 switch (u->common.sType) {
996 case XGL_STRUCTURE_TYPE_UPDATE_SAMPLERS:
997 intel_desc_set_update_samplers(set, &u->samplers);
998 break;
999 case XGL_STRUCTURE_TYPE_UPDATE_SAMPLER_TEXTURES:
1000 intel_desc_set_update_sampler_textures(set, &u->sampler_textures);
1001 break;
1002 case XGL_STRUCTURE_TYPE_UPDATE_IMAGES:
1003 intel_desc_set_update_images(set, &u->images);
1004 break;
1005 case XGL_STRUCTURE_TYPE_UPDATE_BUFFERS:
1006 intel_desc_set_update_buffers(set, &u->buffers);
1007 break;
1008 case XGL_STRUCTURE_TYPE_UPDATE_AS_COPY:
1009 intel_desc_set_update_as_copy(set, &u->as_copy);
1010 break;
1011 default:
1012 assert(!"unknown descriptor update");
1013 break;
1014 }
Chia-I Wuf8385062015-01-04 16:27:24 +08001015 }
1016}