Chia-I Wu | f838506 | 2015-01-04 16:27:24 +0800 | [diff] [blame] | 1 | /* |
| 2 | * XGL |
| 3 | * |
| 4 | * Copyright (C) 2015 LunarG, Inc. |
| 5 | * |
| 6 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 7 | * copy of this software and associated documentation files (the "Software"), |
| 8 | * to deal in the Software without restriction, including without limitation |
| 9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| 10 | * and/or sell copies of the Software, and to permit persons to whom the |
| 11 | * Software is furnished to do so, subject to the following conditions: |
| 12 | * |
| 13 | * The above copyright notice and this permission notice shall be included |
| 14 | * in all copies or substantial portions of the Software. |
| 15 | * |
| 16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
| 20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING |
| 21 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER |
| 22 | * DEALINGS IN THE SOFTWARE. |
| 23 | * |
| 24 | * Authors: |
| 25 | * Chia-I Wu <olv@lunarg.com> |
| 26 | */ |
| 27 | |
| 28 | #include "buf.h" |
| 29 | #include "cmd.h" |
| 30 | #include "dev.h" |
| 31 | #include "gpu.h" |
| 32 | #include "img.h" |
| 33 | #include "sampler.h" |
| 34 | #include "view.h" |
| 35 | #include "desc.h" |
| 36 | |
| 37 | enum intel_desc_surface_type { |
| 38 | INTEL_DESC_SURFACE_UNUSED, |
| 39 | INTEL_DESC_SURFACE_BUF, |
| 40 | INTEL_DESC_SURFACE_IMG, |
| 41 | }; |
| 42 | |
| 43 | struct intel_desc_surface { |
| 44 | const struct intel_mem *mem; |
| 45 | bool read_only; |
| 46 | |
| 47 | enum intel_desc_surface_type type; |
| 48 | union { |
| 49 | const void *unused; |
| 50 | const struct intel_buf_view *buf; |
| 51 | const struct intel_img_view *img; |
| 52 | } u; |
| 53 | }; |
| 54 | |
| 55 | struct intel_desc_sampler { |
| 56 | const struct intel_sampler *sampler; |
| 57 | }; |
| 58 | |
Chia-I Wu | 7732cb2 | 2015-03-26 15:27:55 +0800 | [diff] [blame^] | 59 | bool intel_desc_iter_init_for_binding(struct intel_desc_iter *iter, |
| 60 | const struct intel_desc_layout *layout, |
| 61 | uint32_t binding_index, uint32_t array_base) |
| 62 | { |
| 63 | const struct intel_desc_layout_binding *binding; |
| 64 | |
| 65 | if (binding_index >= layout->binding_count || |
| 66 | array_base >= layout->bindings[binding_index].array_size) |
| 67 | return false; |
| 68 | |
| 69 | binding = &layout->bindings[binding_index]; |
| 70 | |
| 71 | iter->type = binding->type; |
| 72 | iter->increment = binding->increment; |
| 73 | iter->size = binding->array_size; |
| 74 | |
| 75 | intel_desc_offset_mad(&iter->begin, &binding->increment, |
| 76 | &binding->offset, array_base); |
| 77 | intel_desc_offset_add(&iter->end, &iter->begin, &binding->increment); |
| 78 | iter->cur = array_base; |
| 79 | |
| 80 | return true; |
| 81 | } |
| 82 | |
| 83 | static bool desc_iter_init_for_update(struct intel_desc_iter *iter, |
| 84 | const struct intel_desc_set *set, |
| 85 | XGL_DESCRIPTOR_TYPE type, |
| 86 | uint32_t binding_index, uint32_t array_base) |
| 87 | { |
| 88 | if (!intel_desc_iter_init_for_binding(iter, set->layout, |
| 89 | binding_index, array_base) || iter->type != type) |
| 90 | return false; |
| 91 | |
| 92 | intel_desc_offset_add(&iter->begin, &iter->begin, &set->region_begin); |
| 93 | intel_desc_offset_add(&iter->end, &iter->end, &set->region_begin); |
| 94 | |
| 95 | return true; |
| 96 | } |
| 97 | |
| 98 | bool intel_desc_iter_advance(struct intel_desc_iter *iter) |
| 99 | { |
| 100 | if (iter->cur >= iter->size) |
| 101 | return false; |
| 102 | |
| 103 | iter->cur++; |
| 104 | |
| 105 | iter->begin = iter->end; |
| 106 | intel_desc_offset_add(&iter->end, &iter->end, &iter->increment); |
| 107 | |
| 108 | return true; |
| 109 | } |
| 110 | |
Chia-I Wu | 8d24b3b | 2015-03-26 13:14:16 +0800 | [diff] [blame] | 111 | static bool desc_region_init_desc_sizes(struct intel_desc_region *region, |
| 112 | const struct intel_gpu *gpu) |
Chia-I Wu | f838506 | 2015-01-04 16:27:24 +0800 | [diff] [blame] | 113 | { |
Chia-I Wu | 8d24b3b | 2015-03-26 13:14:16 +0800 | [diff] [blame] | 114 | region->surface_desc_size = sizeof(struct intel_desc_surface); |
| 115 | region->sampler_desc_size = sizeof(struct intel_desc_sampler); |
Chia-I Wu | f838506 | 2015-01-04 16:27:24 +0800 | [diff] [blame] | 116 | |
| 117 | return true; |
| 118 | } |
| 119 | |
Chia-I Wu | 8d24b3b | 2015-03-26 13:14:16 +0800 | [diff] [blame] | 120 | XGL_RESULT intel_desc_region_create(struct intel_dev *dev, |
| 121 | struct intel_desc_region **region_ret) |
Chia-I Wu | f838506 | 2015-01-04 16:27:24 +0800 | [diff] [blame] | 122 | { |
| 123 | const uint32_t surface_count = 16384; |
| 124 | const uint32_t sampler_count = 16384; |
Chia-I Wu | 8d24b3b | 2015-03-26 13:14:16 +0800 | [diff] [blame] | 125 | struct intel_desc_region *region; |
Chia-I Wu | f838506 | 2015-01-04 16:27:24 +0800 | [diff] [blame] | 126 | |
Chia-I Wu | 8d24b3b | 2015-03-26 13:14:16 +0800 | [diff] [blame] | 127 | region = intel_alloc(dev, sizeof(*region), 0, XGL_SYSTEM_ALLOC_INTERNAL); |
| 128 | if (!region) |
Chia-I Wu | f838506 | 2015-01-04 16:27:24 +0800 | [diff] [blame] | 129 | return XGL_ERROR_OUT_OF_MEMORY; |
| 130 | |
Chia-I Wu | 8d24b3b | 2015-03-26 13:14:16 +0800 | [diff] [blame] | 131 | memset(region, 0, sizeof(*region)); |
Chia-I Wu | f838506 | 2015-01-04 16:27:24 +0800 | [diff] [blame] | 132 | |
Chia-I Wu | 8d24b3b | 2015-03-26 13:14:16 +0800 | [diff] [blame] | 133 | if (!desc_region_init_desc_sizes(region, dev->gpu)) { |
| 134 | intel_free(dev, region); |
Chia-I Wu | f838506 | 2015-01-04 16:27:24 +0800 | [diff] [blame] | 135 | return XGL_ERROR_UNKNOWN; |
| 136 | } |
| 137 | |
Chia-I Wu | 8d24b3b | 2015-03-26 13:14:16 +0800 | [diff] [blame] | 138 | intel_desc_offset_set(®ion->size, |
| 139 | region->surface_desc_size * surface_count, |
| 140 | region->sampler_desc_size * sampler_count); |
Chia-I Wu | f838506 | 2015-01-04 16:27:24 +0800 | [diff] [blame] | 141 | |
Chia-I Wu | 8d24b3b | 2015-03-26 13:14:16 +0800 | [diff] [blame] | 142 | region->surfaces = intel_alloc(dev, region->size.surface, |
Chia-I Wu | f838506 | 2015-01-04 16:27:24 +0800 | [diff] [blame] | 143 | 64, XGL_SYSTEM_ALLOC_INTERNAL); |
Chia-I Wu | 8d24b3b | 2015-03-26 13:14:16 +0800 | [diff] [blame] | 144 | if (!region->surfaces) { |
| 145 | intel_free(dev, region); |
Chia-I Wu | f838506 | 2015-01-04 16:27:24 +0800 | [diff] [blame] | 146 | return XGL_ERROR_OUT_OF_MEMORY; |
| 147 | } |
| 148 | |
Chia-I Wu | 8d24b3b | 2015-03-26 13:14:16 +0800 | [diff] [blame] | 149 | region->samplers = intel_alloc(dev, region->size.sampler, |
Chia-I Wu | f838506 | 2015-01-04 16:27:24 +0800 | [diff] [blame] | 150 | 64, XGL_SYSTEM_ALLOC_INTERNAL); |
Chia-I Wu | 8d24b3b | 2015-03-26 13:14:16 +0800 | [diff] [blame] | 151 | if (!region->samplers) { |
| 152 | intel_free(dev, region->surfaces); |
| 153 | intel_free(dev, region); |
Chia-I Wu | f838506 | 2015-01-04 16:27:24 +0800 | [diff] [blame] | 154 | return XGL_ERROR_OUT_OF_MEMORY; |
| 155 | } |
| 156 | |
Chia-I Wu | 8d24b3b | 2015-03-26 13:14:16 +0800 | [diff] [blame] | 157 | *region_ret = region; |
Chia-I Wu | f838506 | 2015-01-04 16:27:24 +0800 | [diff] [blame] | 158 | |
| 159 | return XGL_SUCCESS; |
| 160 | } |
| 161 | |
Chia-I Wu | 8d24b3b | 2015-03-26 13:14:16 +0800 | [diff] [blame] | 162 | void intel_desc_region_destroy(struct intel_dev *dev, |
| 163 | struct intel_desc_region *region) |
Chia-I Wu | f838506 | 2015-01-04 16:27:24 +0800 | [diff] [blame] | 164 | { |
Chia-I Wu | 8d24b3b | 2015-03-26 13:14:16 +0800 | [diff] [blame] | 165 | intel_free(dev, region->samplers); |
| 166 | intel_free(dev, region->surfaces); |
| 167 | intel_free(dev, region); |
Chia-I Wu | f838506 | 2015-01-04 16:27:24 +0800 | [diff] [blame] | 168 | } |
| 169 | |
| 170 | /** |
Chia-I Wu | 8d24b3b | 2015-03-26 13:14:16 +0800 | [diff] [blame] | 171 | * Get the size of a descriptor in the region. |
Chia-I Wu | f838506 | 2015-01-04 16:27:24 +0800 | [diff] [blame] | 172 | */ |
Chia-I Wu | 8d24b3b | 2015-03-26 13:14:16 +0800 | [diff] [blame] | 173 | static XGL_RESULT desc_region_get_desc_size(const struct intel_desc_region *region, |
Chia-I Wu | f838506 | 2015-01-04 16:27:24 +0800 | [diff] [blame] | 174 | XGL_DESCRIPTOR_TYPE type, |
| 175 | struct intel_desc_offset *size) |
| 176 | { |
| 177 | uint32_t surface_size = 0, sampler_size = 0; |
| 178 | |
| 179 | switch (type) { |
| 180 | case XGL_DESCRIPTOR_TYPE_SAMPLER: |
Chia-I Wu | 8d24b3b | 2015-03-26 13:14:16 +0800 | [diff] [blame] | 181 | sampler_size = region->sampler_desc_size; |
Chia-I Wu | f838506 | 2015-01-04 16:27:24 +0800 | [diff] [blame] | 182 | break; |
| 183 | case XGL_DESCRIPTOR_TYPE_SAMPLER_TEXTURE: |
Chia-I Wu | 8d24b3b | 2015-03-26 13:14:16 +0800 | [diff] [blame] | 184 | surface_size = region->surface_desc_size; |
| 185 | sampler_size = region->sampler_desc_size; |
Chia-I Wu | f838506 | 2015-01-04 16:27:24 +0800 | [diff] [blame] | 186 | break; |
| 187 | case XGL_DESCRIPTOR_TYPE_TEXTURE: |
| 188 | case XGL_DESCRIPTOR_TYPE_TEXTURE_BUFFER: |
| 189 | case XGL_DESCRIPTOR_TYPE_IMAGE: |
| 190 | case XGL_DESCRIPTOR_TYPE_IMAGE_BUFFER: |
| 191 | case XGL_DESCRIPTOR_TYPE_UNIFORM_BUFFER: |
| 192 | case XGL_DESCRIPTOR_TYPE_SHADER_STORAGE_BUFFER: |
Chia-I Wu | f838506 | 2015-01-04 16:27:24 +0800 | [diff] [blame] | 193 | case XGL_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC: |
| 194 | case XGL_DESCRIPTOR_TYPE_SHADER_STORAGE_BUFFER_DYNAMIC: |
Chia-I Wu | 8d24b3b | 2015-03-26 13:14:16 +0800 | [diff] [blame] | 195 | surface_size = region->surface_desc_size; |
Chia-I Wu | f838506 | 2015-01-04 16:27:24 +0800 | [diff] [blame] | 196 | break; |
| 197 | default: |
| 198 | assert(!"unknown descriptor type"); |
| 199 | return XGL_ERROR_INVALID_VALUE; |
| 200 | break; |
| 201 | } |
| 202 | |
| 203 | intel_desc_offset_set(size, surface_size, sampler_size); |
| 204 | |
| 205 | return XGL_SUCCESS; |
| 206 | } |
| 207 | |
Chia-I Wu | 8d24b3b | 2015-03-26 13:14:16 +0800 | [diff] [blame] | 208 | XGL_RESULT intel_desc_region_alloc(struct intel_desc_region *region, |
| 209 | const XGL_DESCRIPTOR_POOL_CREATE_INFO *info, |
| 210 | struct intel_desc_offset *begin, |
| 211 | struct intel_desc_offset *end) |
Chia-I Wu | f838506 | 2015-01-04 16:27:24 +0800 | [diff] [blame] | 212 | { |
| 213 | uint32_t surface_size = 0, sampler_size = 0; |
| 214 | struct intel_desc_offset alloc; |
| 215 | uint32_t i; |
| 216 | |
| 217 | /* calculate sizes needed */ |
| 218 | for (i = 0; i < info->count; i++) { |
| 219 | const XGL_DESCRIPTOR_TYPE_COUNT *tc = &info->pTypeCount[i]; |
| 220 | struct intel_desc_offset size; |
| 221 | XGL_RESULT ret; |
| 222 | |
Chia-I Wu | 8d24b3b | 2015-03-26 13:14:16 +0800 | [diff] [blame] | 223 | ret = desc_region_get_desc_size(region, tc->type, &size); |
Chia-I Wu | f838506 | 2015-01-04 16:27:24 +0800 | [diff] [blame] | 224 | if (ret != XGL_SUCCESS) |
| 225 | return ret; |
| 226 | |
| 227 | surface_size += size.surface * tc->count; |
| 228 | sampler_size += size.sampler * tc->count; |
| 229 | } |
| 230 | |
| 231 | intel_desc_offset_set(&alloc, surface_size, sampler_size); |
| 232 | |
Chia-I Wu | 8d24b3b | 2015-03-26 13:14:16 +0800 | [diff] [blame] | 233 | *begin = region->cur; |
| 234 | intel_desc_offset_add(end, ®ion->cur, &alloc); |
Chia-I Wu | f838506 | 2015-01-04 16:27:24 +0800 | [diff] [blame] | 235 | |
Chia-I Wu | 8d24b3b | 2015-03-26 13:14:16 +0800 | [diff] [blame] | 236 | if (!intel_desc_offset_within(end, ®ion->size)) |
Chia-I Wu | f838506 | 2015-01-04 16:27:24 +0800 | [diff] [blame] | 237 | return XGL_ERROR_OUT_OF_MEMORY; |
| 238 | |
| 239 | /* increment the writer pointer */ |
Chia-I Wu | 8d24b3b | 2015-03-26 13:14:16 +0800 | [diff] [blame] | 240 | region->cur = *end; |
Chia-I Wu | f838506 | 2015-01-04 16:27:24 +0800 | [diff] [blame] | 241 | |
| 242 | return XGL_SUCCESS; |
| 243 | } |
| 244 | |
Chia-I Wu | 8d24b3b | 2015-03-26 13:14:16 +0800 | [diff] [blame] | 245 | static void desc_region_validate_begin_end(const struct intel_desc_region *region, |
| 246 | const struct intel_desc_offset *begin, |
| 247 | const struct intel_desc_offset *end) |
Chia-I Wu | f838506 | 2015-01-04 16:27:24 +0800 | [diff] [blame] | 248 | { |
Chia-I Wu | 8d24b3b | 2015-03-26 13:14:16 +0800 | [diff] [blame] | 249 | assert(begin->surface % region->surface_desc_size == 0 && |
| 250 | begin->sampler % region->sampler_desc_size == 0); |
| 251 | assert(end->surface % region->surface_desc_size == 0 && |
| 252 | end->sampler % region->sampler_desc_size == 0); |
| 253 | assert(intel_desc_offset_within(end, ®ion->size)); |
Chia-I Wu | f838506 | 2015-01-04 16:27:24 +0800 | [diff] [blame] | 254 | } |
| 255 | |
Chia-I Wu | 8d24b3b | 2015-03-26 13:14:16 +0800 | [diff] [blame] | 256 | void intel_desc_region_free(struct intel_desc_region *region, |
| 257 | const struct intel_desc_offset *begin, |
| 258 | const struct intel_desc_offset *end) |
Chia-I Wu | f838506 | 2015-01-04 16:27:24 +0800 | [diff] [blame] | 259 | { |
Chia-I Wu | 8d24b3b | 2015-03-26 13:14:16 +0800 | [diff] [blame] | 260 | desc_region_validate_begin_end(region, begin, end); |
Chia-I Wu | f838506 | 2015-01-04 16:27:24 +0800 | [diff] [blame] | 261 | |
| 262 | /* is it ok not to reclaim? */ |
| 263 | } |
| 264 | |
Chia-I Wu | 8d24b3b | 2015-03-26 13:14:16 +0800 | [diff] [blame] | 265 | XGL_RESULT intel_desc_region_begin_update(struct intel_desc_region *region, |
| 266 | XGL_DESCRIPTOR_UPDATE_MODE mode) |
Chia-I Wu | f838506 | 2015-01-04 16:27:24 +0800 | [diff] [blame] | 267 | { |
| 268 | /* no-op */ |
| 269 | return XGL_SUCCESS; |
| 270 | } |
| 271 | |
Chia-I Wu | 8d24b3b | 2015-03-26 13:14:16 +0800 | [diff] [blame] | 272 | XGL_RESULT intel_desc_region_end_update(struct intel_desc_region *region, |
| 273 | struct intel_cmd *cmd) |
Chia-I Wu | f838506 | 2015-01-04 16:27:24 +0800 | [diff] [blame] | 274 | { |
| 275 | /* No pipelined update. cmd_draw() will do the work. */ |
| 276 | return XGL_SUCCESS; |
| 277 | } |
| 278 | |
Chia-I Wu | 8d24b3b | 2015-03-26 13:14:16 +0800 | [diff] [blame] | 279 | void intel_desc_region_clear(struct intel_desc_region *region, |
| 280 | const struct intel_desc_offset *begin, |
| 281 | const struct intel_desc_offset *end) |
Chia-I Wu | f838506 | 2015-01-04 16:27:24 +0800 | [diff] [blame] | 282 | { |
| 283 | uint32_t i; |
| 284 | |
Chia-I Wu | 8d24b3b | 2015-03-26 13:14:16 +0800 | [diff] [blame] | 285 | desc_region_validate_begin_end(region, begin, end); |
Chia-I Wu | f838506 | 2015-01-04 16:27:24 +0800 | [diff] [blame] | 286 | |
Chia-I Wu | 8d24b3b | 2015-03-26 13:14:16 +0800 | [diff] [blame] | 287 | for (i = begin->surface; i < end->surface; i += region->surface_desc_size) { |
Chia-I Wu | f838506 | 2015-01-04 16:27:24 +0800 | [diff] [blame] | 288 | struct intel_desc_surface *desc = (struct intel_desc_surface *) |
Chia-I Wu | 8d24b3b | 2015-03-26 13:14:16 +0800 | [diff] [blame] | 289 | ((char *) region->surfaces + i); |
Chia-I Wu | f838506 | 2015-01-04 16:27:24 +0800 | [diff] [blame] | 290 | |
| 291 | desc->mem = NULL; |
| 292 | desc->type = INTEL_DESC_SURFACE_UNUSED; |
| 293 | desc->u.unused = NULL; |
| 294 | } |
| 295 | |
Chia-I Wu | 8d24b3b | 2015-03-26 13:14:16 +0800 | [diff] [blame] | 296 | for (i = begin->sampler; i < end->sampler; i += region->sampler_desc_size) { |
Chia-I Wu | f838506 | 2015-01-04 16:27:24 +0800 | [diff] [blame] | 297 | struct intel_desc_sampler *desc = (struct intel_desc_sampler *) |
Chia-I Wu | 8d24b3b | 2015-03-26 13:14:16 +0800 | [diff] [blame] | 298 | ((char *) region->samplers + i); |
Chia-I Wu | f838506 | 2015-01-04 16:27:24 +0800 | [diff] [blame] | 299 | |
| 300 | desc->sampler = NULL; |
| 301 | } |
| 302 | } |
| 303 | |
Chia-I Wu | 8d24b3b | 2015-03-26 13:14:16 +0800 | [diff] [blame] | 304 | void intel_desc_region_update(struct intel_desc_region *region, |
| 305 | const struct intel_desc_offset *begin, |
| 306 | const struct intel_desc_offset *end, |
| 307 | const struct intel_desc_surface *surfaces, |
| 308 | const struct intel_desc_sampler *samplers) |
Chia-I Wu | f838506 | 2015-01-04 16:27:24 +0800 | [diff] [blame] | 309 | { |
Chia-I Wu | 8d24b3b | 2015-03-26 13:14:16 +0800 | [diff] [blame] | 310 | desc_region_validate_begin_end(region, begin, end); |
Chia-I Wu | f838506 | 2015-01-04 16:27:24 +0800 | [diff] [blame] | 311 | |
| 312 | if (begin->surface < end->surface) { |
Chia-I Wu | 8d24b3b | 2015-03-26 13:14:16 +0800 | [diff] [blame] | 313 | memcpy((char *) region->surfaces + begin->surface, surfaces, |
Chia-I Wu | f838506 | 2015-01-04 16:27:24 +0800 | [diff] [blame] | 314 | end->surface - begin->surface); |
| 315 | } |
| 316 | |
| 317 | if (begin->sampler < end->sampler) { |
Chia-I Wu | 8d24b3b | 2015-03-26 13:14:16 +0800 | [diff] [blame] | 318 | memcpy((char *) region->samplers + begin->sampler, samplers, |
Chia-I Wu | f838506 | 2015-01-04 16:27:24 +0800 | [diff] [blame] | 319 | end->sampler - begin->sampler); |
| 320 | } |
| 321 | } |
| 322 | |
Chia-I Wu | 8d24b3b | 2015-03-26 13:14:16 +0800 | [diff] [blame] | 323 | void intel_desc_region_copy(struct intel_desc_region *region, |
| 324 | const struct intel_desc_offset *begin, |
| 325 | const struct intel_desc_offset *end, |
| 326 | const struct intel_desc_offset *src) |
Chia-I Wu | f838506 | 2015-01-04 16:27:24 +0800 | [diff] [blame] | 327 | { |
| 328 | struct intel_desc_offset src_end; |
| 329 | const struct intel_desc_surface *surfaces; |
| 330 | const struct intel_desc_sampler *samplers; |
| 331 | |
| 332 | /* no overlap */ |
| 333 | assert(intel_desc_offset_within(src, begin) || |
| 334 | intel_desc_offset_within(end, src)); |
| 335 | |
Chia-I Wu | 8d24b3b | 2015-03-26 13:14:16 +0800 | [diff] [blame] | 336 | /* no read past region */ |
Chia-I Wu | f838506 | 2015-01-04 16:27:24 +0800 | [diff] [blame] | 337 | intel_desc_offset_sub(&src_end, end, begin); |
| 338 | intel_desc_offset_add(&src_end, src, &src_end); |
Chia-I Wu | 8d24b3b | 2015-03-26 13:14:16 +0800 | [diff] [blame] | 339 | assert(intel_desc_offset_within(&src_end, ®ion->size)); |
Chia-I Wu | f838506 | 2015-01-04 16:27:24 +0800 | [diff] [blame] | 340 | |
| 341 | surfaces = (const struct intel_desc_surface *) |
Chia-I Wu | 8d24b3b | 2015-03-26 13:14:16 +0800 | [diff] [blame] | 342 | ((const char *) region->surfaces + src->surface); |
Tony Barbour | 379e0a7 | 2015-02-05 11:09:34 -0700 | [diff] [blame] | 343 | samplers = (const struct intel_desc_sampler *) |
Chia-I Wu | 8d24b3b | 2015-03-26 13:14:16 +0800 | [diff] [blame] | 344 | ((const char *) region->samplers + src->sampler); |
Chia-I Wu | f838506 | 2015-01-04 16:27:24 +0800 | [diff] [blame] | 345 | |
Chia-I Wu | 8d24b3b | 2015-03-26 13:14:16 +0800 | [diff] [blame] | 346 | intel_desc_region_update(region, begin, end, surfaces, samplers); |
Chia-I Wu | f838506 | 2015-01-04 16:27:24 +0800 | [diff] [blame] | 347 | } |
| 348 | |
Chia-I Wu | 8d24b3b | 2015-03-26 13:14:16 +0800 | [diff] [blame] | 349 | static void desc_pool_destroy(struct intel_obj *obj) |
Chia-I Wu | f838506 | 2015-01-04 16:27:24 +0800 | [diff] [blame] | 350 | { |
Chia-I Wu | 8d24b3b | 2015-03-26 13:14:16 +0800 | [diff] [blame] | 351 | struct intel_desc_pool *pool = intel_desc_pool_from_obj(obj); |
Chia-I Wu | f838506 | 2015-01-04 16:27:24 +0800 | [diff] [blame] | 352 | |
Chia-I Wu | 8d24b3b | 2015-03-26 13:14:16 +0800 | [diff] [blame] | 353 | intel_desc_pool_destroy(pool); |
Chia-I Wu | f838506 | 2015-01-04 16:27:24 +0800 | [diff] [blame] | 354 | } |
| 355 | |
Chia-I Wu | 8d24b3b | 2015-03-26 13:14:16 +0800 | [diff] [blame] | 356 | XGL_RESULT intel_desc_pool_create(struct intel_dev *dev, |
| 357 | XGL_DESCRIPTOR_POOL_USAGE usage, |
| 358 | uint32_t max_sets, |
| 359 | const XGL_DESCRIPTOR_POOL_CREATE_INFO *info, |
| 360 | struct intel_desc_pool **pool_ret) |
Chia-I Wu | f838506 | 2015-01-04 16:27:24 +0800 | [diff] [blame] | 361 | { |
Chia-I Wu | 8d24b3b | 2015-03-26 13:14:16 +0800 | [diff] [blame] | 362 | struct intel_desc_pool *pool; |
Chia-I Wu | f838506 | 2015-01-04 16:27:24 +0800 | [diff] [blame] | 363 | XGL_RESULT ret; |
| 364 | |
Chia-I Wu | 8d24b3b | 2015-03-26 13:14:16 +0800 | [diff] [blame] | 365 | pool = (struct intel_desc_pool *) intel_base_create(&dev->base.handle, |
| 366 | sizeof(*pool), dev->base.dbg, XGL_DBG_OBJECT_DESCRIPTOR_POOL, |
Chia-I Wu | 545c2e1 | 2015-02-22 13:19:54 +0800 | [diff] [blame] | 367 | info, 0); |
Chia-I Wu | 8d24b3b | 2015-03-26 13:14:16 +0800 | [diff] [blame] | 368 | if (!pool) |
Chia-I Wu | f838506 | 2015-01-04 16:27:24 +0800 | [diff] [blame] | 369 | return XGL_ERROR_OUT_OF_MEMORY; |
| 370 | |
Chia-I Wu | 8d24b3b | 2015-03-26 13:14:16 +0800 | [diff] [blame] | 371 | pool->dev = dev; |
Chia-I Wu | f838506 | 2015-01-04 16:27:24 +0800 | [diff] [blame] | 372 | |
Chia-I Wu | 8d24b3b | 2015-03-26 13:14:16 +0800 | [diff] [blame] | 373 | ret = intel_desc_region_alloc(dev->desc_region, info, |
| 374 | &pool->region_begin, &pool->region_end); |
Chia-I Wu | f838506 | 2015-01-04 16:27:24 +0800 | [diff] [blame] | 375 | if (ret != XGL_SUCCESS) { |
Chia-I Wu | 8d24b3b | 2015-03-26 13:14:16 +0800 | [diff] [blame] | 376 | intel_base_destroy(&pool->obj.base); |
Chia-I Wu | f838506 | 2015-01-04 16:27:24 +0800 | [diff] [blame] | 377 | return ret; |
| 378 | } |
| 379 | |
| 380 | /* point to head */ |
Chia-I Wu | 8d24b3b | 2015-03-26 13:14:16 +0800 | [diff] [blame] | 381 | pool->cur = pool->region_begin; |
Chia-I Wu | f838506 | 2015-01-04 16:27:24 +0800 | [diff] [blame] | 382 | |
Chia-I Wu | 8d24b3b | 2015-03-26 13:14:16 +0800 | [diff] [blame] | 383 | pool->obj.destroy = desc_pool_destroy; |
Chia-I Wu | f838506 | 2015-01-04 16:27:24 +0800 | [diff] [blame] | 384 | |
Chia-I Wu | 8d24b3b | 2015-03-26 13:14:16 +0800 | [diff] [blame] | 385 | *pool_ret = pool; |
Chia-I Wu | f838506 | 2015-01-04 16:27:24 +0800 | [diff] [blame] | 386 | |
| 387 | return XGL_SUCCESS; |
| 388 | } |
| 389 | |
Chia-I Wu | 8d24b3b | 2015-03-26 13:14:16 +0800 | [diff] [blame] | 390 | void intel_desc_pool_destroy(struct intel_desc_pool *pool) |
Chia-I Wu | f838506 | 2015-01-04 16:27:24 +0800 | [diff] [blame] | 391 | { |
Chia-I Wu | 8d24b3b | 2015-03-26 13:14:16 +0800 | [diff] [blame] | 392 | intel_desc_region_free(pool->dev->desc_region, |
| 393 | &pool->region_begin, &pool->region_end); |
| 394 | intel_base_destroy(&pool->obj.base); |
Chia-I Wu | f838506 | 2015-01-04 16:27:24 +0800 | [diff] [blame] | 395 | } |
| 396 | |
Chia-I Wu | 8d24b3b | 2015-03-26 13:14:16 +0800 | [diff] [blame] | 397 | XGL_RESULT intel_desc_pool_alloc(struct intel_desc_pool *pool, |
| 398 | const struct intel_desc_layout *layout, |
| 399 | struct intel_desc_offset *begin, |
| 400 | struct intel_desc_offset *end) |
Chia-I Wu | f838506 | 2015-01-04 16:27:24 +0800 | [diff] [blame] | 401 | { |
Chia-I Wu | 8d24b3b | 2015-03-26 13:14:16 +0800 | [diff] [blame] | 402 | *begin = pool->cur; |
| 403 | intel_desc_offset_add(end, &pool->cur, &layout->region_size); |
Chia-I Wu | f838506 | 2015-01-04 16:27:24 +0800 | [diff] [blame] | 404 | |
Chia-I Wu | 8d24b3b | 2015-03-26 13:14:16 +0800 | [diff] [blame] | 405 | if (!intel_desc_offset_within(end, &pool->region_end)) |
Chia-I Wu | f838506 | 2015-01-04 16:27:24 +0800 | [diff] [blame] | 406 | return XGL_ERROR_OUT_OF_MEMORY; |
| 407 | |
| 408 | /* increment the writer pointer */ |
Chia-I Wu | 8d24b3b | 2015-03-26 13:14:16 +0800 | [diff] [blame] | 409 | pool->cur = *end; |
Chia-I Wu | f838506 | 2015-01-04 16:27:24 +0800 | [diff] [blame] | 410 | |
| 411 | return XGL_SUCCESS; |
| 412 | } |
| 413 | |
Chia-I Wu | dee9561 | 2015-03-26 15:23:52 +0800 | [diff] [blame] | 414 | void intel_desc_pool_reset(struct intel_desc_pool *pool) |
Chia-I Wu | f838506 | 2015-01-04 16:27:24 +0800 | [diff] [blame] | 415 | { |
| 416 | /* reset to head */ |
Chia-I Wu | 8d24b3b | 2015-03-26 13:14:16 +0800 | [diff] [blame] | 417 | pool->cur = pool->region_begin; |
Chia-I Wu | f838506 | 2015-01-04 16:27:24 +0800 | [diff] [blame] | 418 | } |
| 419 | |
| 420 | static void desc_set_destroy(struct intel_obj *obj) |
| 421 | { |
| 422 | struct intel_desc_set *set = intel_desc_set_from_obj(obj); |
| 423 | |
| 424 | intel_desc_set_destroy(set); |
| 425 | } |
| 426 | |
| 427 | XGL_RESULT intel_desc_set_create(struct intel_dev *dev, |
Chia-I Wu | 8d24b3b | 2015-03-26 13:14:16 +0800 | [diff] [blame] | 428 | struct intel_desc_pool *pool, |
Chia-I Wu | f838506 | 2015-01-04 16:27:24 +0800 | [diff] [blame] | 429 | XGL_DESCRIPTOR_SET_USAGE usage, |
| 430 | const struct intel_desc_layout *layout, |
| 431 | struct intel_desc_set **set_ret) |
| 432 | { |
| 433 | struct intel_desc_set *set; |
| 434 | XGL_RESULT ret; |
| 435 | |
Chia-I Wu | 545c2e1 | 2015-02-22 13:19:54 +0800 | [diff] [blame] | 436 | set = (struct intel_desc_set *) intel_base_create(&dev->base.handle, |
| 437 | sizeof(*set), dev->base.dbg, XGL_DBG_OBJECT_DESCRIPTOR_SET, |
| 438 | NULL, 0); |
Chia-I Wu | f838506 | 2015-01-04 16:27:24 +0800 | [diff] [blame] | 439 | if (!set) |
| 440 | return XGL_ERROR_OUT_OF_MEMORY; |
| 441 | |
Chia-I Wu | 8d24b3b | 2015-03-26 13:14:16 +0800 | [diff] [blame] | 442 | set->region = dev->desc_region; |
| 443 | ret = intel_desc_pool_alloc(pool, layout, |
| 444 | &set->region_begin, &set->region_end); |
Chia-I Wu | f838506 | 2015-01-04 16:27:24 +0800 | [diff] [blame] | 445 | if (ret != XGL_SUCCESS) { |
| 446 | intel_base_destroy(&set->obj.base); |
| 447 | return ret; |
| 448 | } |
| 449 | |
| 450 | set->layout = layout; |
| 451 | |
| 452 | set->obj.destroy = desc_set_destroy; |
| 453 | |
| 454 | *set_ret = set; |
| 455 | |
| 456 | return XGL_SUCCESS; |
| 457 | } |
| 458 | |
| 459 | void intel_desc_set_destroy(struct intel_desc_set *set) |
| 460 | { |
| 461 | intel_base_destroy(&set->obj.base); |
| 462 | } |
| 463 | |
Chia-I Wu | f838506 | 2015-01-04 16:27:24 +0800 | [diff] [blame] | 464 | static bool desc_set_img_layout_read_only(XGL_IMAGE_LAYOUT layout) |
| 465 | { |
| 466 | switch (layout) { |
| 467 | case XGL_IMAGE_LAYOUT_DEPTH_STENCIL_READ_ONLY_OPTIMAL: |
| 468 | case XGL_IMAGE_LAYOUT_SHADER_READ_ONLY_OPTIMAL: |
| 469 | case XGL_IMAGE_LAYOUT_TRANSFER_SOURCE_OPTIMAL: |
| 470 | return true; |
| 471 | default: |
| 472 | return false; |
| 473 | } |
| 474 | } |
| 475 | |
| 476 | void intel_desc_set_update_samplers(struct intel_desc_set *set, |
| 477 | const XGL_UPDATE_SAMPLERS *update) |
| 478 | { |
Chia-I Wu | 7732cb2 | 2015-03-26 15:27:55 +0800 | [diff] [blame^] | 479 | struct intel_desc_iter iter; |
Chia-I Wu | f838506 | 2015-01-04 16:27:24 +0800 | [diff] [blame] | 480 | uint32_t i; |
| 481 | |
Chia-I Wu | 7732cb2 | 2015-03-26 15:27:55 +0800 | [diff] [blame^] | 482 | if (!desc_iter_init_for_update(&iter, set, XGL_DESCRIPTOR_TYPE_SAMPLER, |
| 483 | update->binding, update->arrayIndex)) |
Chia-I Wu | f838506 | 2015-01-04 16:27:24 +0800 | [diff] [blame] | 484 | return; |
| 485 | |
| 486 | for (i = 0; i < update->count; i++) { |
| 487 | const struct intel_sampler *sampler = |
| 488 | intel_sampler((XGL_SAMPLER) update->pSamplers[i]); |
| 489 | struct intel_desc_sampler desc; |
| 490 | |
Chia-I Wu | f838506 | 2015-01-04 16:27:24 +0800 | [diff] [blame] | 491 | desc.sampler = sampler; |
Chia-I Wu | 7732cb2 | 2015-03-26 15:27:55 +0800 | [diff] [blame^] | 492 | intel_desc_region_update(set->region, &iter.begin, &iter.end, |
| 493 | NULL, &desc); |
Chia-I Wu | f838506 | 2015-01-04 16:27:24 +0800 | [diff] [blame] | 494 | |
Chia-I Wu | 7732cb2 | 2015-03-26 15:27:55 +0800 | [diff] [blame^] | 495 | if (!intel_desc_iter_advance(&iter)) |
Chia-I Wu | f838506 | 2015-01-04 16:27:24 +0800 | [diff] [blame] | 496 | break; |
| 497 | } |
| 498 | } |
| 499 | |
| 500 | void intel_desc_set_update_sampler_textures(struct intel_desc_set *set, |
| 501 | const XGL_UPDATE_SAMPLER_TEXTURES *update) |
| 502 | { |
Chia-I Wu | 7732cb2 | 2015-03-26 15:27:55 +0800 | [diff] [blame^] | 503 | struct intel_desc_iter iter; |
| 504 | const struct intel_desc_layout_binding *binding; |
Chia-I Wu | f838506 | 2015-01-04 16:27:24 +0800 | [diff] [blame] | 505 | uint32_t i; |
| 506 | |
Chia-I Wu | 7732cb2 | 2015-03-26 15:27:55 +0800 | [diff] [blame^] | 507 | if (!desc_iter_init_for_update(&iter, set, XGL_DESCRIPTOR_TYPE_SAMPLER_TEXTURE, |
| 508 | update->binding, update->arrayIndex)) |
Chia-I Wu | f838506 | 2015-01-04 16:27:24 +0800 | [diff] [blame] | 509 | return; |
| 510 | |
Chia-I Wu | 7732cb2 | 2015-03-26 15:27:55 +0800 | [diff] [blame^] | 511 | binding = &set->layout->bindings[update->binding]; |
| 512 | |
| 513 | if (binding->immutable_sampler) { |
| 514 | struct intel_desc_offset end; |
| 515 | struct intel_desc_sampler sampler_desc; |
| 516 | |
| 517 | assert(!iter.increment.sampler); |
| 518 | intel_desc_offset_set(&end, iter.begin.surface, |
| 519 | iter.begin.sampler + set->region->sampler_desc_size); |
| 520 | |
| 521 | sampler_desc.sampler = binding->immutable_sampler; |
| 522 | intel_desc_region_update(set->region, &iter.begin, &end, |
| 523 | NULL, &sampler_desc); |
| 524 | } |
| 525 | |
Chia-I Wu | f838506 | 2015-01-04 16:27:24 +0800 | [diff] [blame] | 526 | for (i = 0; i < update->count; i++) { |
| 527 | const struct intel_sampler *sampler = |
Chia-I Wu | 7732cb2 | 2015-03-26 15:27:55 +0800 | [diff] [blame^] | 528 | intel_sampler(update->pSamplerImageViews[i].sampler); |
Chia-I Wu | f838506 | 2015-01-04 16:27:24 +0800 | [diff] [blame] | 529 | const XGL_IMAGE_VIEW_ATTACH_INFO *info = |
| 530 | update->pSamplerImageViews[i].pImageView; |
| 531 | const struct intel_img_view *view = intel_img_view(info->view); |
| 532 | struct intel_desc_surface view_desc; |
| 533 | struct intel_desc_sampler sampler_desc; |
| 534 | |
Chia-I Wu | f838506 | 2015-01-04 16:27:24 +0800 | [diff] [blame] | 535 | view_desc.mem = view->img->obj.mem; |
| 536 | view_desc.read_only = desc_set_img_layout_read_only(info->layout); |
| 537 | view_desc.type = INTEL_DESC_SURFACE_IMG; |
| 538 | view_desc.u.img = view; |
| 539 | |
| 540 | sampler_desc.sampler = sampler; |
| 541 | |
Chia-I Wu | 7732cb2 | 2015-03-26 15:27:55 +0800 | [diff] [blame^] | 542 | intel_desc_region_update(set->region, &iter.begin, &iter.end, |
| 543 | &view_desc, &sampler_desc); |
Chia-I Wu | f838506 | 2015-01-04 16:27:24 +0800 | [diff] [blame] | 544 | |
Chia-I Wu | 7732cb2 | 2015-03-26 15:27:55 +0800 | [diff] [blame^] | 545 | if (!intel_desc_iter_advance(&iter)) |
Chia-I Wu | f838506 | 2015-01-04 16:27:24 +0800 | [diff] [blame] | 546 | break; |
| 547 | } |
| 548 | } |
| 549 | |
| 550 | void intel_desc_set_update_images(struct intel_desc_set *set, |
| 551 | const XGL_UPDATE_IMAGES *update) |
| 552 | { |
Chia-I Wu | 7732cb2 | 2015-03-26 15:27:55 +0800 | [diff] [blame^] | 553 | struct intel_desc_iter iter; |
Chia-I Wu | f838506 | 2015-01-04 16:27:24 +0800 | [diff] [blame] | 554 | uint32_t i; |
| 555 | |
Chia-I Wu | 7732cb2 | 2015-03-26 15:27:55 +0800 | [diff] [blame^] | 556 | if (!desc_iter_init_for_update(&iter, set, update->descriptorType, |
| 557 | update->binding, update->arrayIndex)) |
Chia-I Wu | f838506 | 2015-01-04 16:27:24 +0800 | [diff] [blame] | 558 | return; |
| 559 | |
| 560 | for (i = 0; i < update->count; i++) { |
Chia-I Wu | 7732cb2 | 2015-03-26 15:27:55 +0800 | [diff] [blame^] | 561 | const XGL_IMAGE_VIEW_ATTACH_INFO *info = &update->pImageViews[i]; |
Chia-I Wu | f838506 | 2015-01-04 16:27:24 +0800 | [diff] [blame] | 562 | const struct intel_img_view *view = intel_img_view(info->view); |
| 563 | struct intel_desc_surface desc; |
| 564 | |
Chia-I Wu | f838506 | 2015-01-04 16:27:24 +0800 | [diff] [blame] | 565 | desc.mem = view->img->obj.mem; |
| 566 | desc.read_only = desc_set_img_layout_read_only(info->layout); |
| 567 | desc.type = INTEL_DESC_SURFACE_IMG; |
| 568 | desc.u.img = view; |
Chia-I Wu | 7732cb2 | 2015-03-26 15:27:55 +0800 | [diff] [blame^] | 569 | intel_desc_region_update(set->region, &iter.begin, &iter.end, |
| 570 | &desc, NULL); |
Chia-I Wu | f838506 | 2015-01-04 16:27:24 +0800 | [diff] [blame] | 571 | |
Chia-I Wu | 7732cb2 | 2015-03-26 15:27:55 +0800 | [diff] [blame^] | 572 | if (!intel_desc_iter_advance(&iter)) |
Chia-I Wu | f838506 | 2015-01-04 16:27:24 +0800 | [diff] [blame] | 573 | break; |
| 574 | } |
| 575 | } |
| 576 | |
| 577 | void intel_desc_set_update_buffers(struct intel_desc_set *set, |
| 578 | const XGL_UPDATE_BUFFERS *update) |
| 579 | { |
Chia-I Wu | 7732cb2 | 2015-03-26 15:27:55 +0800 | [diff] [blame^] | 580 | struct intel_desc_iter iter; |
Chia-I Wu | f838506 | 2015-01-04 16:27:24 +0800 | [diff] [blame] | 581 | uint32_t i; |
| 582 | |
Chia-I Wu | 7732cb2 | 2015-03-26 15:27:55 +0800 | [diff] [blame^] | 583 | if (!desc_iter_init_for_update(&iter, set, update->descriptorType, |
| 584 | update->binding, update->arrayIndex)) |
Chia-I Wu | f838506 | 2015-01-04 16:27:24 +0800 | [diff] [blame] | 585 | return; |
| 586 | |
| 587 | for (i = 0; i < update->count; i++) { |
Chia-I Wu | 7732cb2 | 2015-03-26 15:27:55 +0800 | [diff] [blame^] | 588 | const XGL_BUFFER_VIEW_ATTACH_INFO *info = &update->pBufferViews[i]; |
Chia-I Wu | f838506 | 2015-01-04 16:27:24 +0800 | [diff] [blame] | 589 | const struct intel_buf_view *view = intel_buf_view(info->view); |
| 590 | struct intel_desc_surface desc; |
| 591 | |
Chia-I Wu | f838506 | 2015-01-04 16:27:24 +0800 | [diff] [blame] | 592 | desc.mem = view->buf->obj.mem; |
| 593 | desc.read_only = false; |
| 594 | desc.type = INTEL_DESC_SURFACE_BUF; |
| 595 | desc.u.buf = view; |
Chia-I Wu | 7732cb2 | 2015-03-26 15:27:55 +0800 | [diff] [blame^] | 596 | intel_desc_region_update(set->region, &iter.begin, &iter.end, |
| 597 | &desc, NULL); |
Chia-I Wu | f838506 | 2015-01-04 16:27:24 +0800 | [diff] [blame] | 598 | |
Chia-I Wu | 7732cb2 | 2015-03-26 15:27:55 +0800 | [diff] [blame^] | 599 | if (!intel_desc_iter_advance(&iter)) |
Chia-I Wu | f838506 | 2015-01-04 16:27:24 +0800 | [diff] [blame] | 600 | break; |
| 601 | } |
| 602 | } |
| 603 | |
| 604 | void intel_desc_set_update_as_copy(struct intel_desc_set *set, |
| 605 | const XGL_UPDATE_AS_COPY *update) |
| 606 | { |
| 607 | const struct intel_desc_set *src_set = |
| 608 | intel_desc_set(update->descriptorSet); |
Chia-I Wu | 7732cb2 | 2015-03-26 15:27:55 +0800 | [diff] [blame^] | 609 | struct intel_desc_iter iter, src_iter; |
| 610 | struct intel_desc_offset begin, src_begin; |
Chia-I Wu | f838506 | 2015-01-04 16:27:24 +0800 | [diff] [blame] | 611 | uint32_t i; |
| 612 | |
| 613 | /* disallow combined sampler textures */ |
| 614 | if (update->descriptorType == XGL_DESCRIPTOR_TYPE_SAMPLER_TEXTURE) |
| 615 | return; |
| 616 | |
Chia-I Wu | 7732cb2 | 2015-03-26 15:27:55 +0800 | [diff] [blame^] | 617 | if (!desc_iter_init_for_update(&iter, set, update->descriptorType, |
| 618 | update->binding, update->arrayElement) || |
| 619 | !desc_iter_init_for_update(&src_iter, src_set, update->descriptorType, |
| 620 | update->binding, update->arrayElement)) |
Chia-I Wu | f838506 | 2015-01-04 16:27:24 +0800 | [diff] [blame] | 621 | return; |
| 622 | |
Chia-I Wu | 7732cb2 | 2015-03-26 15:27:55 +0800 | [diff] [blame^] | 623 | /* save the begin offsets */ |
| 624 | begin = iter.begin; |
| 625 | src_begin = src_iter.begin; |
Chia-I Wu | f838506 | 2015-01-04 16:27:24 +0800 | [diff] [blame] | 626 | |
Chia-I Wu | 7732cb2 | 2015-03-26 15:27:55 +0800 | [diff] [blame^] | 627 | /* advance to the end */ |
Chia-I Wu | f838506 | 2015-01-04 16:27:24 +0800 | [diff] [blame] | 628 | for (i = 0; i < update->count; i++) { |
Chia-I Wu | 7732cb2 | 2015-03-26 15:27:55 +0800 | [diff] [blame^] | 629 | if (!intel_desc_iter_advance(&iter) || |
| 630 | !intel_desc_iter_advance(&src_iter)) { |
| 631 | /* out of bound */ |
| 632 | return; |
| 633 | } |
Chia-I Wu | f838506 | 2015-01-04 16:27:24 +0800 | [diff] [blame] | 634 | } |
Chia-I Wu | f838506 | 2015-01-04 16:27:24 +0800 | [diff] [blame] | 635 | |
Chia-I Wu | 7732cb2 | 2015-03-26 15:27:55 +0800 | [diff] [blame^] | 636 | intel_desc_region_copy(set->region, &begin, &iter.end, &src_begin); |
Chia-I Wu | f838506 | 2015-01-04 16:27:24 +0800 | [diff] [blame] | 637 | } |
| 638 | |
Chia-I Wu | 2f0cba8 | 2015-02-12 10:15:42 -0700 | [diff] [blame] | 639 | static void desc_set_read(const struct intel_desc_set *set, |
| 640 | const struct intel_desc_offset *offset, |
| 641 | const struct intel_desc_surface **surface, |
| 642 | const struct intel_desc_sampler **sampler) |
| 643 | { |
| 644 | struct intel_desc_offset begin, end; |
| 645 | |
Chia-I Wu | 8d24b3b | 2015-03-26 13:14:16 +0800 | [diff] [blame] | 646 | intel_desc_offset_add(&begin, &set->region_begin, offset); |
Chia-I Wu | 2f0cba8 | 2015-02-12 10:15:42 -0700 | [diff] [blame] | 647 | intel_desc_offset_set(&end, 0, 0); |
| 648 | |
| 649 | if (surface) { |
| 650 | *surface = (const struct intel_desc_surface *) |
Chia-I Wu | 8d24b3b | 2015-03-26 13:14:16 +0800 | [diff] [blame] | 651 | ((const char *) set->region->surfaces + begin.surface); |
Chia-I Wu | 2f0cba8 | 2015-02-12 10:15:42 -0700 | [diff] [blame] | 652 | |
Chia-I Wu | 8d24b3b | 2015-03-26 13:14:16 +0800 | [diff] [blame] | 653 | end.surface = set->region->surface_desc_size; |
Chia-I Wu | 2f0cba8 | 2015-02-12 10:15:42 -0700 | [diff] [blame] | 654 | } |
| 655 | |
| 656 | if (sampler) { |
| 657 | *sampler = (const struct intel_desc_sampler *) |
Chia-I Wu | 8d24b3b | 2015-03-26 13:14:16 +0800 | [diff] [blame] | 658 | ((const char *) set->region->samplers + begin.sampler); |
Chia-I Wu | 2f0cba8 | 2015-02-12 10:15:42 -0700 | [diff] [blame] | 659 | |
Chia-I Wu | 8d24b3b | 2015-03-26 13:14:16 +0800 | [diff] [blame] | 660 | end.sampler = set->region->sampler_desc_size; |
Chia-I Wu | 2f0cba8 | 2015-02-12 10:15:42 -0700 | [diff] [blame] | 661 | } |
| 662 | |
| 663 | intel_desc_offset_add(&end, &begin, &end); |
Chia-I Wu | 8d24b3b | 2015-03-26 13:14:16 +0800 | [diff] [blame] | 664 | desc_region_validate_begin_end(set->region, &begin, &end); |
Chia-I Wu | 2f0cba8 | 2015-02-12 10:15:42 -0700 | [diff] [blame] | 665 | } |
| 666 | |
| 667 | void intel_desc_set_read_surface(const struct intel_desc_set *set, |
| 668 | const struct intel_desc_offset *offset, |
| 669 | XGL_PIPELINE_SHADER_STAGE stage, |
| 670 | const struct intel_mem **mem, |
| 671 | bool *read_only, |
| 672 | const uint32_t **cmd, |
| 673 | uint32_t *cmd_len) |
| 674 | { |
| 675 | const struct intel_desc_surface *desc; |
| 676 | |
| 677 | desc_set_read(set, offset, &desc, NULL); |
| 678 | |
| 679 | *mem = desc->mem; |
| 680 | *read_only = desc->read_only; |
| 681 | switch (desc->type) { |
| 682 | case INTEL_DESC_SURFACE_BUF: |
| 683 | *cmd = (stage == XGL_SHADER_STAGE_FRAGMENT) ? |
| 684 | desc->u.buf->fs_cmd : desc->u.buf->cmd; |
| 685 | *cmd_len = desc->u.buf->cmd_len; |
| 686 | break; |
| 687 | case INTEL_DESC_SURFACE_IMG: |
| 688 | *cmd = desc->u.img->cmd; |
| 689 | *cmd_len = desc->u.img->cmd_len; |
| 690 | break; |
| 691 | case INTEL_DESC_SURFACE_UNUSED: |
| 692 | default: |
| 693 | *cmd = NULL; |
| 694 | *cmd_len = 0; |
| 695 | break; |
| 696 | } |
| 697 | } |
| 698 | |
| 699 | void intel_desc_set_read_sampler(const struct intel_desc_set *set, |
| 700 | const struct intel_desc_offset *offset, |
| 701 | const struct intel_sampler **sampler) |
| 702 | { |
| 703 | const struct intel_desc_sampler *desc; |
| 704 | |
| 705 | desc_set_read(set, offset, NULL, &desc); |
| 706 | |
| 707 | *sampler = desc->sampler; |
| 708 | } |
| 709 | |
Chia-I Wu | f838506 | 2015-01-04 16:27:24 +0800 | [diff] [blame] | 710 | static void desc_layout_destroy(struct intel_obj *obj) |
| 711 | { |
| 712 | struct intel_desc_layout *layout = intel_desc_layout_from_obj(obj); |
| 713 | |
| 714 | intel_desc_layout_destroy(layout); |
| 715 | } |
| 716 | |
Chia-I Wu | fc9d913 | 2015-03-26 15:04:41 +0800 | [diff] [blame] | 717 | static XGL_RESULT desc_layout_init_bindings(struct intel_desc_layout *layout, |
| 718 | const struct intel_desc_region *region, |
| 719 | const XGL_DESCRIPTOR_SET_LAYOUT_CREATE_INFO *info) |
Chia-I Wu | f838506 | 2015-01-04 16:27:24 +0800 | [diff] [blame] | 720 | { |
| 721 | struct intel_desc_offset offset; |
Chia-I Wu | 7732cb2 | 2015-03-26 15:27:55 +0800 | [diff] [blame^] | 722 | uint32_t i; |
Chia-I Wu | f838506 | 2015-01-04 16:27:24 +0800 | [diff] [blame] | 723 | XGL_RESULT ret; |
| 724 | |
Chia-I Wu | 7732cb2 | 2015-03-26 15:27:55 +0800 | [diff] [blame^] | 725 | intel_desc_offset_set(&offset, 0, 0); |
Chia-I Wu | f838506 | 2015-01-04 16:27:24 +0800 | [diff] [blame] | 726 | |
Chia-I Wu | fc9d913 | 2015-03-26 15:04:41 +0800 | [diff] [blame] | 727 | /* allocate bindings */ |
| 728 | layout->bindings = intel_alloc(layout, sizeof(layout->bindings[0]) * |
| 729 | info->count, 0, XGL_SYSTEM_ALLOC_INTERNAL); |
| 730 | if (!layout->bindings) |
| 731 | return XGL_ERROR_OUT_OF_MEMORY; |
| 732 | |
| 733 | memset(layout->bindings, 0, sizeof(layout->bindings[0]) * info->count); |
| 734 | layout->binding_count = info->count; |
| 735 | |
| 736 | /* initialize bindings */ |
| 737 | for (i = 0; i < info->count; i++) { |
| 738 | const XGL_DESCRIPTOR_SET_LAYOUT_BINDING *lb = &info->pBinding[i]; |
| 739 | struct intel_desc_layout_binding *binding = &layout->bindings[i]; |
Chia-I Wu | f838506 | 2015-01-04 16:27:24 +0800 | [diff] [blame] | 740 | struct intel_desc_offset size; |
| 741 | |
Chia-I Wu | fc9d913 | 2015-03-26 15:04:41 +0800 | [diff] [blame] | 742 | switch (lb->descriptorType) { |
| 743 | case XGL_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC: |
| 744 | case XGL_DESCRIPTOR_TYPE_SHADER_STORAGE_BUFFER_DYNAMIC: |
Chia-I Wu | fc9d913 | 2015-03-26 15:04:41 +0800 | [diff] [blame] | 745 | layout->dynamic_desc_count += lb->count; |
| 746 | break; |
| 747 | default: |
| 748 | break; |
| 749 | } |
| 750 | |
Chia-I Wu | 7732cb2 | 2015-03-26 15:27:55 +0800 | [diff] [blame^] | 751 | /* lb->stageFlags does not gain us anything */ |
| 752 | binding->type = lb->descriptorType; |
| 753 | binding->array_size = lb->count; |
| 754 | binding->offset = offset; |
| 755 | |
Chia-I Wu | fc9d913 | 2015-03-26 15:04:41 +0800 | [diff] [blame] | 756 | ret = desc_region_get_desc_size(region, |
| 757 | lb->descriptorType, &size); |
Chia-I Wu | f838506 | 2015-01-04 16:27:24 +0800 | [diff] [blame] | 758 | if (ret != XGL_SUCCESS) |
| 759 | return ret; |
| 760 | |
Chia-I Wu | fc9d913 | 2015-03-26 15:04:41 +0800 | [diff] [blame] | 761 | if (lb->immutableSampler != XGL_NULL_HANDLE) { |
| 762 | binding->immutable_sampler = intel_sampler(lb->immutableSampler); |
Chia-I Wu | f838506 | 2015-01-04 16:27:24 +0800 | [diff] [blame] | 763 | /* do not increment sampler offset */ |
Chia-I Wu | fc9d913 | 2015-03-26 15:04:41 +0800 | [diff] [blame] | 764 | intel_desc_offset_set(&binding->increment, size.surface, 0); |
Chia-I Wu | f838506 | 2015-01-04 16:27:24 +0800 | [diff] [blame] | 765 | } else { |
Chia-I Wu | fc9d913 | 2015-03-26 15:04:41 +0800 | [diff] [blame] | 766 | binding->immutable_sampler = NULL; |
| 767 | binding->increment = size; |
Chia-I Wu | f838506 | 2015-01-04 16:27:24 +0800 | [diff] [blame] | 768 | } |
| 769 | |
Chia-I Wu | 7732cb2 | 2015-03-26 15:27:55 +0800 | [diff] [blame^] | 770 | /* increment offset */ |
Chia-I Wu | fc9d913 | 2015-03-26 15:04:41 +0800 | [diff] [blame] | 771 | intel_desc_offset_mad(&size, &binding->increment, &size, |
| 772 | lb->count - 1); |
Chia-I Wu | f838506 | 2015-01-04 16:27:24 +0800 | [diff] [blame] | 773 | intel_desc_offset_add(&offset, &offset, &size); |
Chia-I Wu | f838506 | 2015-01-04 16:27:24 +0800 | [diff] [blame] | 774 | } |
| 775 | |
Chia-I Wu | 8d24b3b | 2015-03-26 13:14:16 +0800 | [diff] [blame] | 776 | layout->region_size = offset; |
Chia-I Wu | f838506 | 2015-01-04 16:27:24 +0800 | [diff] [blame] | 777 | |
| 778 | return XGL_SUCCESS; |
| 779 | } |
| 780 | |
Chia-I Wu | f838506 | 2015-01-04 16:27:24 +0800 | [diff] [blame] | 781 | XGL_RESULT intel_desc_layout_create(struct intel_dev *dev, |
Chia-I Wu | f838506 | 2015-01-04 16:27:24 +0800 | [diff] [blame] | 782 | const XGL_DESCRIPTOR_SET_LAYOUT_CREATE_INFO *info, |
| 783 | struct intel_desc_layout **layout_ret) |
| 784 | { |
| 785 | struct intel_desc_layout *layout; |
| 786 | XGL_RESULT ret; |
| 787 | |
Chia-I Wu | 545c2e1 | 2015-02-22 13:19:54 +0800 | [diff] [blame] | 788 | layout = (struct intel_desc_layout *) intel_base_create(&dev->base.handle, |
| 789 | sizeof(*layout), dev->base.dbg, |
| 790 | XGL_DBG_OBJECT_DESCRIPTOR_SET_LAYOUT, info, 0); |
Chia-I Wu | f838506 | 2015-01-04 16:27:24 +0800 | [diff] [blame] | 791 | if (!layout) |
| 792 | return XGL_ERROR_OUT_OF_MEMORY; |
| 793 | |
Chia-I Wu | 7732cb2 | 2015-03-26 15:27:55 +0800 | [diff] [blame^] | 794 | ret = desc_layout_init_bindings(layout, dev->desc_region, info); |
Chia-I Wu | f838506 | 2015-01-04 16:27:24 +0800 | [diff] [blame] | 795 | if (ret != XGL_SUCCESS) { |
| 796 | intel_desc_layout_destroy(layout); |
| 797 | return ret; |
| 798 | } |
| 799 | |
| 800 | layout->obj.destroy = desc_layout_destroy; |
| 801 | |
| 802 | *layout_ret = layout; |
| 803 | |
| 804 | return XGL_SUCCESS; |
| 805 | } |
| 806 | |
| 807 | void intel_desc_layout_destroy(struct intel_desc_layout *layout) |
| 808 | { |
Chia-I Wu | fc9d913 | 2015-03-26 15:04:41 +0800 | [diff] [blame] | 809 | intel_free(layout, layout->bindings); |
Chia-I Wu | f838506 | 2015-01-04 16:27:24 +0800 | [diff] [blame] | 810 | intel_base_destroy(&layout->obj.base); |
| 811 | } |
| 812 | |
Chia-I Wu | 7732cb2 | 2015-03-26 15:27:55 +0800 | [diff] [blame^] | 813 | static void desc_layout_chain_destroy(struct intel_obj *obj) |
Chia-I Wu | f838506 | 2015-01-04 16:27:24 +0800 | [diff] [blame] | 814 | { |
Chia-I Wu | 7732cb2 | 2015-03-26 15:27:55 +0800 | [diff] [blame^] | 815 | struct intel_desc_layout_chain *chain = |
| 816 | intel_desc_layout_chain_from_obj(obj); |
Chia-I Wu | f838506 | 2015-01-04 16:27:24 +0800 | [diff] [blame] | 817 | |
Chia-I Wu | 7732cb2 | 2015-03-26 15:27:55 +0800 | [diff] [blame^] | 818 | intel_desc_layout_chain_destroy(chain); |
Chia-I Wu | f838506 | 2015-01-04 16:27:24 +0800 | [diff] [blame] | 819 | } |
| 820 | |
Chia-I Wu | 7732cb2 | 2015-03-26 15:27:55 +0800 | [diff] [blame^] | 821 | XGL_RESULT intel_desc_layout_chain_create(struct intel_dev *dev, |
| 822 | const XGL_DESCRIPTOR_SET_LAYOUT *layouts, |
| 823 | uint32_t count, |
| 824 | struct intel_desc_layout_chain **chain_ret) |
Chia-I Wu | f838506 | 2015-01-04 16:27:24 +0800 | [diff] [blame] | 825 | { |
Chia-I Wu | 7732cb2 | 2015-03-26 15:27:55 +0800 | [diff] [blame^] | 826 | struct intel_desc_layout_chain *chain; |
| 827 | uint32_t i; |
| 828 | |
| 829 | chain = (struct intel_desc_layout_chain *) |
| 830 | intel_base_create(&dev->base.handle, sizeof(*chain), dev->base.dbg, |
| 831 | XGL_DBG_OBJECT_DESCRIPTOR_SET_LAYOUT_CHAIN, NULL, 0); |
| 832 | if (!chain) |
| 833 | return XGL_ERROR_OUT_OF_MEMORY; |
| 834 | |
| 835 | chain->layouts = intel_alloc(chain, sizeof(chain->layouts[0]) * count, |
| 836 | 0, XGL_SYSTEM_ALLOC_INTERNAL); |
| 837 | if (!chain) { |
| 838 | intel_desc_layout_chain_destroy(chain); |
| 839 | return XGL_ERROR_OUT_OF_MEMORY; |
Chia-I Wu | f838506 | 2015-01-04 16:27:24 +0800 | [diff] [blame] | 840 | } |
| 841 | |
Chia-I Wu | 7732cb2 | 2015-03-26 15:27:55 +0800 | [diff] [blame^] | 842 | for (i = 0; i < count; i++) |
| 843 | chain->layouts[i] = intel_desc_layout(layouts[i]); |
Chia-I Wu | f838506 | 2015-01-04 16:27:24 +0800 | [diff] [blame] | 844 | |
Chia-I Wu | 7732cb2 | 2015-03-26 15:27:55 +0800 | [diff] [blame^] | 845 | chain->layout_count = count; |
Chia-I Wu | f838506 | 2015-01-04 16:27:24 +0800 | [diff] [blame] | 846 | |
Chia-I Wu | 7732cb2 | 2015-03-26 15:27:55 +0800 | [diff] [blame^] | 847 | chain->obj.destroy = desc_layout_chain_destroy; |
| 848 | |
| 849 | *chain_ret = chain; |
| 850 | |
| 851 | return XGL_SUCCESS; |
Chia-I Wu | f838506 | 2015-01-04 16:27:24 +0800 | [diff] [blame] | 852 | } |
| 853 | |
Chia-I Wu | 7732cb2 | 2015-03-26 15:27:55 +0800 | [diff] [blame^] | 854 | void intel_desc_layout_chain_destroy(struct intel_desc_layout_chain *chain) |
Chia-I Wu | f838506 | 2015-01-04 16:27:24 +0800 | [diff] [blame] | 855 | { |
Chia-I Wu | 7732cb2 | 2015-03-26 15:27:55 +0800 | [diff] [blame^] | 856 | if (chain->layouts) |
| 857 | intel_free(chain, chain->layouts); |
| 858 | intel_base_destroy(&chain->obj.base); |
Chia-I Wu | f838506 | 2015-01-04 16:27:24 +0800 | [diff] [blame] | 859 | } |
| 860 | |
Chia-I Wu | de26bdf | 2015-02-18 15:47:12 -0700 | [diff] [blame] | 861 | ICD_EXPORT XGL_RESULT XGLAPI xglCreateDescriptorSetLayout( |
Chia-I Wu | f838506 | 2015-01-04 16:27:24 +0800 | [diff] [blame] | 862 | XGL_DEVICE device, |
Chia-I Wu | fc9d913 | 2015-03-26 15:04:41 +0800 | [diff] [blame] | 863 | const XGL_DESCRIPTOR_SET_LAYOUT_CREATE_INFO* pCreateInfo, |
Chia-I Wu | f838506 | 2015-01-04 16:27:24 +0800 | [diff] [blame] | 864 | XGL_DESCRIPTOR_SET_LAYOUT* pSetLayout) |
| 865 | { |
| 866 | struct intel_dev *dev = intel_dev(device); |
Chia-I Wu | f838506 | 2015-01-04 16:27:24 +0800 | [diff] [blame] | 867 | |
Chia-I Wu | 7732cb2 | 2015-03-26 15:27:55 +0800 | [diff] [blame^] | 868 | return intel_desc_layout_create(dev, pCreateInfo, |
Chia-I Wu | f838506 | 2015-01-04 16:27:24 +0800 | [diff] [blame] | 869 | (struct intel_desc_layout **) pSetLayout); |
| 870 | } |
| 871 | |
Chia-I Wu | 7732cb2 | 2015-03-26 15:27:55 +0800 | [diff] [blame^] | 872 | ICD_EXPORT XGL_RESULT XGLAPI xglCreateDescriptorSetLayoutChain( |
| 873 | XGL_DEVICE device, |
| 874 | uint32_t setLayoutArrayCount, |
| 875 | const XGL_DESCRIPTOR_SET_LAYOUT* pSetLayoutArray, |
| 876 | XGL_DESCRIPTOR_SET_LAYOUT_CHAIN* pLayoutChain) |
| 877 | { |
| 878 | struct intel_dev *dev = intel_dev(device); |
| 879 | |
| 880 | return intel_desc_layout_chain_create(dev, |
| 881 | pSetLayoutArray, setLayoutArrayCount, |
| 882 | (struct intel_desc_layout_chain **) pLayoutChain); |
| 883 | } |
| 884 | |
Chia-I Wu | 8d24b3b | 2015-03-26 13:14:16 +0800 | [diff] [blame] | 885 | ICD_EXPORT XGL_RESULT XGLAPI xglBeginDescriptorPoolUpdate( |
Chia-I Wu | f838506 | 2015-01-04 16:27:24 +0800 | [diff] [blame] | 886 | XGL_DEVICE device, |
| 887 | XGL_DESCRIPTOR_UPDATE_MODE updateMode) |
| 888 | { |
| 889 | struct intel_dev *dev = intel_dev(device); |
Chia-I Wu | 8d24b3b | 2015-03-26 13:14:16 +0800 | [diff] [blame] | 890 | struct intel_desc_region *region = dev->desc_region; |
Chia-I Wu | f838506 | 2015-01-04 16:27:24 +0800 | [diff] [blame] | 891 | |
Chia-I Wu | 8d24b3b | 2015-03-26 13:14:16 +0800 | [diff] [blame] | 892 | return intel_desc_region_begin_update(region, updateMode); |
Chia-I Wu | f838506 | 2015-01-04 16:27:24 +0800 | [diff] [blame] | 893 | } |
| 894 | |
Chia-I Wu | 8d24b3b | 2015-03-26 13:14:16 +0800 | [diff] [blame] | 895 | ICD_EXPORT XGL_RESULT XGLAPI xglEndDescriptorPoolUpdate( |
Chia-I Wu | f838506 | 2015-01-04 16:27:24 +0800 | [diff] [blame] | 896 | XGL_DEVICE device, |
| 897 | XGL_CMD_BUFFER cmd_) |
| 898 | { |
| 899 | struct intel_dev *dev = intel_dev(device); |
Chia-I Wu | 8d24b3b | 2015-03-26 13:14:16 +0800 | [diff] [blame] | 900 | struct intel_desc_region *region = dev->desc_region; |
Chia-I Wu | f838506 | 2015-01-04 16:27:24 +0800 | [diff] [blame] | 901 | struct intel_cmd *cmd = intel_cmd(cmd_); |
| 902 | |
Chia-I Wu | 8d24b3b | 2015-03-26 13:14:16 +0800 | [diff] [blame] | 903 | return intel_desc_region_end_update(region, cmd); |
Chia-I Wu | f838506 | 2015-01-04 16:27:24 +0800 | [diff] [blame] | 904 | } |
| 905 | |
Chia-I Wu | 8d24b3b | 2015-03-26 13:14:16 +0800 | [diff] [blame] | 906 | ICD_EXPORT XGL_RESULT XGLAPI xglCreateDescriptorPool( |
Chia-I Wu | f838506 | 2015-01-04 16:27:24 +0800 | [diff] [blame] | 907 | XGL_DEVICE device, |
Chia-I Wu | 8d24b3b | 2015-03-26 13:14:16 +0800 | [diff] [blame] | 908 | XGL_DESCRIPTOR_POOL_USAGE poolUsage, |
Mark Lobodzinski | e2d07a5 | 2015-01-29 08:55:56 -0600 | [diff] [blame] | 909 | uint32_t maxSets, |
Chia-I Wu | 8d24b3b | 2015-03-26 13:14:16 +0800 | [diff] [blame] | 910 | const XGL_DESCRIPTOR_POOL_CREATE_INFO* pCreateInfo, |
| 911 | XGL_DESCRIPTOR_POOL* pDescriptorPool) |
Chia-I Wu | f838506 | 2015-01-04 16:27:24 +0800 | [diff] [blame] | 912 | { |
| 913 | struct intel_dev *dev = intel_dev(device); |
| 914 | |
Chia-I Wu | 8d24b3b | 2015-03-26 13:14:16 +0800 | [diff] [blame] | 915 | return intel_desc_pool_create(dev, poolUsage, maxSets, pCreateInfo, |
| 916 | (struct intel_desc_pool **) pDescriptorPool); |
Chia-I Wu | f838506 | 2015-01-04 16:27:24 +0800 | [diff] [blame] | 917 | } |
| 918 | |
Chia-I Wu | dee9561 | 2015-03-26 15:23:52 +0800 | [diff] [blame] | 919 | ICD_EXPORT XGL_RESULT XGLAPI xglResetDescriptorPool( |
Chia-I Wu | 8d24b3b | 2015-03-26 13:14:16 +0800 | [diff] [blame] | 920 | XGL_DESCRIPTOR_POOL descriptorPool) |
Chia-I Wu | f838506 | 2015-01-04 16:27:24 +0800 | [diff] [blame] | 921 | { |
Chia-I Wu | 8d24b3b | 2015-03-26 13:14:16 +0800 | [diff] [blame] | 922 | struct intel_desc_pool *pool = intel_desc_pool(descriptorPool); |
Chia-I Wu | f838506 | 2015-01-04 16:27:24 +0800 | [diff] [blame] | 923 | |
Chia-I Wu | dee9561 | 2015-03-26 15:23:52 +0800 | [diff] [blame] | 924 | intel_desc_pool_reset(pool); |
Chia-I Wu | f838506 | 2015-01-04 16:27:24 +0800 | [diff] [blame] | 925 | |
| 926 | return XGL_SUCCESS; |
| 927 | } |
| 928 | |
Chia-I Wu | de26bdf | 2015-02-18 15:47:12 -0700 | [diff] [blame] | 929 | ICD_EXPORT XGL_RESULT XGLAPI xglAllocDescriptorSets( |
Chia-I Wu | 8d24b3b | 2015-03-26 13:14:16 +0800 | [diff] [blame] | 930 | XGL_DESCRIPTOR_POOL descriptorPool, |
Chia-I Wu | f838506 | 2015-01-04 16:27:24 +0800 | [diff] [blame] | 931 | XGL_DESCRIPTOR_SET_USAGE setUsage, |
Mark Lobodzinski | e2d07a5 | 2015-01-29 08:55:56 -0600 | [diff] [blame] | 932 | uint32_t count, |
Chia-I Wu | f838506 | 2015-01-04 16:27:24 +0800 | [diff] [blame] | 933 | const XGL_DESCRIPTOR_SET_LAYOUT* pSetLayouts, |
| 934 | XGL_DESCRIPTOR_SET* pDescriptorSets, |
Mark Lobodzinski | e2d07a5 | 2015-01-29 08:55:56 -0600 | [diff] [blame] | 935 | uint32_t* pCount) |
Chia-I Wu | f838506 | 2015-01-04 16:27:24 +0800 | [diff] [blame] | 936 | { |
Chia-I Wu | 8d24b3b | 2015-03-26 13:14:16 +0800 | [diff] [blame] | 937 | struct intel_desc_pool *pool = intel_desc_pool(descriptorPool); |
| 938 | struct intel_dev *dev = pool->dev; |
Chia-I Wu | f838506 | 2015-01-04 16:27:24 +0800 | [diff] [blame] | 939 | XGL_RESULT ret = XGL_SUCCESS; |
| 940 | uint32_t i; |
| 941 | |
| 942 | for (i = 0; i < count; i++) { |
| 943 | const struct intel_desc_layout *layout = |
| 944 | intel_desc_layout((XGL_DESCRIPTOR_SET_LAYOUT) pSetLayouts[i]); |
| 945 | |
Chia-I Wu | 8d24b3b | 2015-03-26 13:14:16 +0800 | [diff] [blame] | 946 | ret = intel_desc_set_create(dev, pool, setUsage, layout, |
Chia-I Wu | f838506 | 2015-01-04 16:27:24 +0800 | [diff] [blame] | 947 | (struct intel_desc_set **) &pDescriptorSets[i]); |
| 948 | if (ret != XGL_SUCCESS) |
| 949 | break; |
| 950 | } |
| 951 | |
| 952 | if (pCount) |
| 953 | *pCount = i; |
| 954 | |
| 955 | return ret; |
| 956 | } |
| 957 | |
Chia-I Wu | de26bdf | 2015-02-18 15:47:12 -0700 | [diff] [blame] | 958 | ICD_EXPORT void XGLAPI xglClearDescriptorSets( |
Chia-I Wu | 8d24b3b | 2015-03-26 13:14:16 +0800 | [diff] [blame] | 959 | XGL_DESCRIPTOR_POOL descriptorPool, |
Mark Lobodzinski | e2d07a5 | 2015-01-29 08:55:56 -0600 | [diff] [blame] | 960 | uint32_t count, |
Chia-I Wu | f838506 | 2015-01-04 16:27:24 +0800 | [diff] [blame] | 961 | const XGL_DESCRIPTOR_SET* pDescriptorSets) |
| 962 | { |
| 963 | uint32_t i; |
| 964 | |
| 965 | for (i = 0; i < count; i++) { |
| 966 | struct intel_desc_set *set = |
| 967 | intel_desc_set((XGL_DESCRIPTOR_SET) pDescriptorSets[i]); |
| 968 | |
Chia-I Wu | 8d24b3b | 2015-03-26 13:14:16 +0800 | [diff] [blame] | 969 | intel_desc_region_clear(set->region, &set->region_begin, &set->region_end); |
Chia-I Wu | f838506 | 2015-01-04 16:27:24 +0800 | [diff] [blame] | 970 | } |
| 971 | } |
| 972 | |
Chia-I Wu | de26bdf | 2015-02-18 15:47:12 -0700 | [diff] [blame] | 973 | ICD_EXPORT void XGLAPI xglUpdateDescriptors( |
Chia-I Wu | f838506 | 2015-01-04 16:27:24 +0800 | [diff] [blame] | 974 | XGL_DESCRIPTOR_SET descriptorSet, |
Chia-I Wu | 7732cb2 | 2015-03-26 15:27:55 +0800 | [diff] [blame^] | 975 | uint32_t updateCount, |
| 976 | const void** ppUpdateArray) |
Chia-I Wu | f838506 | 2015-01-04 16:27:24 +0800 | [diff] [blame] | 977 | { |
| 978 | struct intel_desc_set *set = intel_desc_set(descriptorSet); |
Chia-I Wu | 7732cb2 | 2015-03-26 15:27:55 +0800 | [diff] [blame^] | 979 | uint32_t i; |
Chia-I Wu | f838506 | 2015-01-04 16:27:24 +0800 | [diff] [blame] | 980 | |
Chia-I Wu | 7732cb2 | 2015-03-26 15:27:55 +0800 | [diff] [blame^] | 981 | for (i = 0; i < updateCount; i++) { |
| 982 | const union { |
| 983 | struct { |
| 984 | XGL_STRUCTURE_TYPE sType; |
| 985 | const void* pNext; |
| 986 | } common; |
Chia-I Wu | f838506 | 2015-01-04 16:27:24 +0800 | [diff] [blame] | 987 | |
Chia-I Wu | 7732cb2 | 2015-03-26 15:27:55 +0800 | [diff] [blame^] | 988 | XGL_UPDATE_SAMPLERS samplers; |
| 989 | XGL_UPDATE_SAMPLER_TEXTURES sampler_textures; |
| 990 | XGL_UPDATE_IMAGES images; |
| 991 | XGL_UPDATE_BUFFERS buffers; |
| 992 | XGL_UPDATE_AS_COPY as_copy; |
| 993 | } *u = ppUpdateArray[i]; |
| 994 | |
Chia-I Wu | f838506 | 2015-01-04 16:27:24 +0800 | [diff] [blame] | 995 | switch (u->common.sType) { |
| 996 | case XGL_STRUCTURE_TYPE_UPDATE_SAMPLERS: |
| 997 | intel_desc_set_update_samplers(set, &u->samplers); |
| 998 | break; |
| 999 | case XGL_STRUCTURE_TYPE_UPDATE_SAMPLER_TEXTURES: |
| 1000 | intel_desc_set_update_sampler_textures(set, &u->sampler_textures); |
| 1001 | break; |
| 1002 | case XGL_STRUCTURE_TYPE_UPDATE_IMAGES: |
| 1003 | intel_desc_set_update_images(set, &u->images); |
| 1004 | break; |
| 1005 | case XGL_STRUCTURE_TYPE_UPDATE_BUFFERS: |
| 1006 | intel_desc_set_update_buffers(set, &u->buffers); |
| 1007 | break; |
| 1008 | case XGL_STRUCTURE_TYPE_UPDATE_AS_COPY: |
| 1009 | intel_desc_set_update_as_copy(set, &u->as_copy); |
| 1010 | break; |
| 1011 | default: |
| 1012 | assert(!"unknown descriptor update"); |
| 1013 | break; |
| 1014 | } |
Chia-I Wu | f838506 | 2015-01-04 16:27:24 +0800 | [diff] [blame] | 1015 | } |
| 1016 | } |