blob: 84114759f15f166f594392a0a3de534028634972 [file] [log] [blame]
Chia-I Wu4ea339e2014-08-08 21:56:26 +08001/*
2 * XGL
3 *
4 * Copyright (C) 2014 LunarG, Inc.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included
14 * in all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE.
Chia-I Wu44e42362014-09-02 08:32:09 +080023 *
24 * Authors:
25 * Chia-I Wu <olv@lunarg.com>
Chia-I Wu4ea339e2014-08-08 21:56:26 +080026 */
27
Chia-I Wue46da3e2014-08-08 21:52:48 +080028#include "kmd/winsys.h"
29#include "dev.h"
30#include "gpu.h"
31#include "img.h"
Chia-I Wu4ea339e2014-08-08 21:56:26 +080032
Chia-I Wu4ea339e2014-08-08 21:56:26 +080033/*
34 * From the Ivy Bridge PRM, volume 1 part 1, page 105:
35 *
36 * "In addition to restrictions on maximum height, width, and depth,
37 * surfaces are also restricted to a maximum size in bytes. This
38 * maximum is 2 GB for all products and all surface types."
39 */
Chia-I Wue46da3e2014-08-08 21:52:48 +080040static const size_t intel_max_resource_size = 1u << 31;
Chia-I Wu4ea339e2014-08-08 21:56:26 +080041
Chia-I Wufeb441f2014-08-08 21:27:38 +080042static void img_destroy(struct intel_obj *obj)
43{
44 struct intel_img *img = intel_img_from_obj(obj);
45
46 intel_img_destroy(img);
47}
48
49static XGL_RESULT img_get_info(struct intel_base *base, int type,
50 XGL_SIZE *size, XGL_VOID *data)
51{
52 struct intel_img *img = intel_img_from_base(base);
53 XGL_RESULT ret = XGL_SUCCESS;
54
55 switch (type) {
56 case XGL_INFO_TYPE_MEMORY_REQUIREMENTS:
57 {
58 XGL_MEMORY_REQUIREMENTS *mem_req = data;
59
Chia-I Wu9b752e12014-08-15 16:21:44 +080060 mem_req->size = img->total_size;
Chia-I Wufeb441f2014-08-08 21:27:38 +080061 mem_req->alignment = 4096;
62 mem_req->heapCount = 1;
63 mem_req->heaps[0] = 0;
64
65 *size = sizeof(*mem_req);
66 }
67 break;
68 default:
69 ret = intel_base_get_info(base, type, size, data);
70 break;
71 }
72
73 return ret;
74}
75
76XGL_RESULT intel_img_create(struct intel_dev *dev,
77 const XGL_IMAGE_CREATE_INFO *info,
Chia-I Wu794d12a2014-09-15 14:55:25 +080078 bool scanout,
Chia-I Wufeb441f2014-08-08 21:27:38 +080079 struct intel_img **img_ret)
80{
Chia-I Wufeb441f2014-08-08 21:27:38 +080081 struct intel_img *img;
Chia-I Wu37cba152014-08-15 16:03:10 +080082 struct intel_layout *layout;
Chia-I Wufeb441f2014-08-08 21:27:38 +080083
Courtney Goeltzenleuchterfb4fb532014-08-14 09:35:21 -060084 img = (struct intel_img *) intel_base_create(dev, sizeof(*img),
Chia-I Wufeb441f2014-08-08 21:27:38 +080085 dev->base.dbg, XGL_DBG_OBJECT_IMAGE, info, 0);
86 if (!img)
87 return XGL_ERROR_OUT_OF_MEMORY;
88
Chia-I Wu37cba152014-08-15 16:03:10 +080089 layout = &img->layout;
90
Chia-I Wueb2da592014-08-16 14:19:39 +080091 img->type = info->imageType;
Chia-I Wu73e326f2014-08-21 11:07:57 +080092 img->depth = info->extent.depth;
Chia-I Wueb2da592014-08-16 14:19:39 +080093 img->array_size = info->arraySize;
94 img->samples = info->samples;
Chia-I Wu794d12a2014-09-15 14:55:25 +080095 intel_layout_init(layout, dev, info, scanout);
Chia-I Wu37cba152014-08-15 16:03:10 +080096
97 if (layout->bo_stride > intel_max_resource_size / layout->bo_height) {
98 intel_dev_log(dev, XGL_DBG_MSG_ERROR, XGL_VALIDATION_LEVEL_0,
99 XGL_NULL_HANDLE, 0, 0, "image too big");
100 intel_img_destroy(img);
101 return XGL_ERROR_INVALID_MEMORY_SIZE;
102 }
Chia-I Wufeb441f2014-08-08 21:27:38 +0800103
Chia-I Wu9b752e12014-08-15 16:21:44 +0800104 img->total_size = img->layout.bo_stride * img->layout.bo_height;
105
Chia-I Wu457d0a62014-08-18 13:02:26 +0800106 if (layout->aux != INTEL_LAYOUT_AUX_NONE) {
Chia-I Wu9b752e12014-08-15 16:21:44 +0800107 img->aux_offset = u_align(img->total_size, 4096);
108 img->total_size = img->aux_offset +
109 layout->aux_stride * layout->aux_height;
110 }
111
112 if (layout->separate_stencil) {
113 XGL_IMAGE_CREATE_INFO s8_info;
114
115 img->s8_layout = icd_alloc(sizeof(*img->s8_layout), 0,
116 XGL_SYSTEM_ALLOC_INTERNAL);
117 if (!img->s8_layout) {
118 intel_img_destroy(img);
119 return XGL_ERROR_OUT_OF_MEMORY;
120 }
121
122 s8_info = *info;
123 s8_info.format.channelFormat = XGL_CH_FMT_R8;
124 assert(info->format.numericFormat == XGL_NUM_FMT_DS);
125
Chia-I Wu794d12a2014-09-15 14:55:25 +0800126 intel_layout_init(img->s8_layout, dev, &s8_info, scanout);
Chia-I Wu9b752e12014-08-15 16:21:44 +0800127
128 img->s8_offset = u_align(img->total_size, 4096);
129 img->total_size = img->s8_offset +
130 img->s8_layout->bo_stride * img->s8_layout->bo_height;
Chia-I Wufeb441f2014-08-08 21:27:38 +0800131 }
132
Chia-I Wufeb441f2014-08-08 21:27:38 +0800133 img->obj.destroy = img_destroy;
134 img->obj.base.get_info = img_get_info;
135
136 *img_ret = img;
137
138 return XGL_SUCCESS;
139}
140
141void intel_img_destroy(struct intel_img *img)
142{
Chia-I Wu9b752e12014-08-15 16:21:44 +0800143 if (img->s8_layout)
144 icd_free(img->s8_layout);
145
Chia-I Wufeb441f2014-08-08 21:27:38 +0800146 intel_base_destroy(&img->obj.base);
147}
148
Chia-I Wu251e7d92014-08-19 13:35:42 +0800149XGL_RESULT XGLAPI intelOpenPeerImage(
150 XGL_DEVICE device,
151 const XGL_PEER_IMAGE_OPEN_INFO* pOpenInfo,
152 XGL_IMAGE* pImage,
153 XGL_GPU_MEMORY* pMem)
154{
155 return XGL_ERROR_UNAVAILABLE;
156}
157
Chia-I Wufeb441f2014-08-08 21:27:38 +0800158XGL_RESULT XGLAPI intelCreateImage(
159 XGL_DEVICE device,
160 const XGL_IMAGE_CREATE_INFO* pCreateInfo,
161 XGL_IMAGE* pImage)
162{
163 struct intel_dev *dev = intel_dev(device);
164
Chia-I Wu794d12a2014-09-15 14:55:25 +0800165 return intel_img_create(dev, pCreateInfo, false,
166 (struct intel_img **) pImage);
Chia-I Wufeb441f2014-08-08 21:27:38 +0800167}
168
169XGL_RESULT XGLAPI intelGetImageSubresourceInfo(
170 XGL_IMAGE image,
171 const XGL_IMAGE_SUBRESOURCE* pSubresource,
172 XGL_SUBRESOURCE_INFO_TYPE infoType,
173 XGL_SIZE* pDataSize,
174 XGL_VOID* pData)
175{
176 const struct intel_img *img = intel_img(image);
177 XGL_RESULT ret = XGL_SUCCESS;
178
179 switch (infoType) {
180 case XGL_INFO_TYPE_SUBRESOURCE_LAYOUT:
181 {
182 XGL_SUBRESOURCE_LAYOUT *layout = (XGL_SUBRESOURCE_LAYOUT *) pData;
Chia-I Wu2b685d72014-08-14 13:45:37 +0800183 unsigned x, y;
184
185 intel_layout_get_slice_pos(&img->layout, pSubresource->mipLevel,
186 pSubresource->arraySlice, &x, &y);
187 intel_layout_pos_to_mem(&img->layout, x, y, &x, &y);
Chia-I Wufeb441f2014-08-08 21:27:38 +0800188
189 *pDataSize = sizeof(XGL_SUBRESOURCE_LAYOUT);
190
Chia-I Wu457d0a62014-08-18 13:02:26 +0800191 layout->offset = intel_layout_mem_to_linear(&img->layout, x, y);
Chia-I Wu2b685d72014-08-14 13:45:37 +0800192 layout->size = intel_layout_get_slice_size(&img->layout,
193 pSubresource->mipLevel);
194 layout->rowPitch = img->layout.bo_stride;
195 layout->depthPitch = intel_layout_get_slice_stride(&img->layout,
196 pSubresource->mipLevel);
Chia-I Wufeb441f2014-08-08 21:27:38 +0800197 }
198 break;
199 default:
200 ret = XGL_ERROR_INVALID_VALUE;
201 break;
202 }
203
204 return ret;
205}