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Chia-I Wub2755562014-08-20 13:38:52 +08001/*
2 * XGL
3 *
4 * Copyright (C) 2014 LunarG, Inc.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included
14 * in all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE.
23 */
24
Chia-I Wu9f039862014-08-20 15:39:56 +080025#include "genhw/genhw.h"
Chia-I Wub2755562014-08-20 13:38:52 +080026#include "dset.h"
Chia-I Wu7fae4e32014-08-21 11:39:44 +080027#include "img.h"
Chia-I Wub2755562014-08-20 13:38:52 +080028#include "mem.h"
Chia-I Wu018a3962014-08-21 10:37:52 +080029#include "pipeline.h"
Chia-I Wub2755562014-08-20 13:38:52 +080030#include "state.h"
31#include "view.h"
32#include "cmd_priv.h"
33
Chia-I Wu59c097e2014-08-21 10:51:07 +080034static int translate_primitive_topology(XGL_PRIMITIVE_TOPOLOGY topo)
35{
36 switch (topo) {
37 case XGL_TOPOLOGY_POINT_LIST: return GEN6_3DPRIM_POINTLIST;
38 case XGL_TOPOLOGY_LINE_LIST: return GEN6_3DPRIM_LINELIST;
39 case XGL_TOPOLOGY_LINE_STRIP: return GEN6_3DPRIM_LINESTRIP;
40 case XGL_TOPOLOGY_TRIANGLE_LIST: return GEN6_3DPRIM_TRILIST;
41 case XGL_TOPOLOGY_TRIANGLE_STRIP: return GEN6_3DPRIM_TRISTRIP;
42 case XGL_TOPOLOGY_RECT_LIST: return GEN6_3DPRIM_RECTLIST;
43 case XGL_TOPOLOGY_QUAD_LIST: return GEN6_3DPRIM_QUADLIST;
44 case XGL_TOPOLOGY_QUAD_STRIP: return GEN6_3DPRIM_QUADSTRIP;
45 case XGL_TOPOLOGY_LINE_LIST_ADJ: return GEN6_3DPRIM_LINELIST_ADJ;
46 case XGL_TOPOLOGY_LINE_STRIP_ADJ: return GEN6_3DPRIM_LINESTRIP_ADJ;
47 case XGL_TOPOLOGY_TRIANGLE_LIST_ADJ: return GEN6_3DPRIM_TRILIST_ADJ;
48 case XGL_TOPOLOGY_TRIANGLE_STRIP_ADJ: return GEN6_3DPRIM_TRISTRIP_ADJ;
49 case XGL_TOPOLOGY_PATCH: return GEN7_3DPRIM_PATCHLIST_1;
50 default:
51 assert(!"unknown primitive topology");
52 return GEN6_3DPRIM_POINTLIST;
53 }
54}
55
56static void gen6_3DPRIMITIVE(struct intel_cmd *cmd,
57 XGL_PRIMITIVE_TOPOLOGY topo,
58 bool indexed,
59 uint32_t vertex_count,
60 uint32_t vertex_start,
61 uint32_t instance_count,
62 uint32_t instance_start,
63 uint32_t vertex_base)
64{
65 const uint8_t cmd_len = 6;
66 uint32_t dw0;
67
68 CMD_ASSERT(cmd, 6, 6);
69
Chia-I Wub0b9f692014-08-21 11:33:29 +080070 dw0 = GEN_RENDER_CMD(3D, GEN6, 3DPRIMITIVE) |
Chia-I Wu59c097e2014-08-21 10:51:07 +080071 translate_primitive_topology(topo) << GEN6_3DPRIM_DW0_TYPE__SHIFT |
72 (cmd_len - 2);
73
74 if (indexed)
75 dw0 |= GEN6_3DPRIM_DW0_ACCESS_RANDOM;
76
77 cmd_reserve(cmd, cmd_len);
78 cmd_write(cmd, dw0);
79 cmd_write(cmd, vertex_count);
80 cmd_write(cmd, vertex_start);
81 cmd_write(cmd, instance_count);
82 cmd_write(cmd, instance_start);
83 cmd_write(cmd, vertex_base);
84}
85
86static void gen7_3DPRIMITIVE(struct intel_cmd *cmd,
87 XGL_PRIMITIVE_TOPOLOGY topo,
88 bool indexed,
89 uint32_t vertex_count,
90 uint32_t vertex_start,
91 uint32_t instance_count,
92 uint32_t instance_start,
93 uint32_t vertex_base)
94{
95 const uint8_t cmd_len = 7;
96 uint32_t dw0, dw1;
97
98 CMD_ASSERT(cmd, 7, 7.5);
99
Chia-I Wub0b9f692014-08-21 11:33:29 +0800100 dw0 = GEN_RENDER_CMD(3D, GEN6, 3DPRIMITIVE) | (cmd_len - 2);
Chia-I Wu59c097e2014-08-21 10:51:07 +0800101 dw1 = translate_primitive_topology(topo) << GEN7_3DPRIM_DW1_TYPE__SHIFT;
102
103 if (indexed)
104 dw1 |= GEN7_3DPRIM_DW1_ACCESS_RANDOM;
105
106 cmd_reserve(cmd, cmd_len);
107 cmd_write(cmd, dw0);
108 cmd_write(cmd, dw1);
109 cmd_write(cmd, vertex_count);
110 cmd_write(cmd, vertex_start);
111 cmd_write(cmd, instance_count);
112 cmd_write(cmd, instance_start);
113 cmd_write(cmd, vertex_base);
114}
115
116static void gen6_3DSTATE_INDEX_BUFFER(struct intel_cmd *cmd,
Chia-I Wu958d1b72014-08-21 11:28:11 +0800117 const struct intel_mem *mem,
Chia-I Wu59c097e2014-08-21 10:51:07 +0800118 XGL_GPU_SIZE offset,
119 XGL_INDEX_TYPE type,
120 bool enable_cut_index)
121{
122 const uint8_t cmd_len = 3;
123 uint32_t dw0, end_offset;
124 unsigned offset_align;
125
126 CMD_ASSERT(cmd, 6, 7.5);
127
Chia-I Wub0b9f692014-08-21 11:33:29 +0800128 dw0 = GEN_RENDER_CMD(3D, GEN6, 3DSTATE_INDEX_BUFFER) | (cmd_len - 2);
Chia-I Wu59c097e2014-08-21 10:51:07 +0800129
130 /* the bit is moved to 3DSTATE_VF */
131 if (cmd_gen(cmd) >= INTEL_GEN(7.5))
132 assert(!enable_cut_index);
133 if (enable_cut_index)
134 dw0 |= GEN6_IB_DW0_CUT_INDEX_ENABLE;
135
136 switch (type) {
137 case XGL_INDEX_8:
138 dw0 |= GEN6_IB_DW0_FORMAT_BYTE;
139 offset_align = 1;
140 break;
141 case XGL_INDEX_16:
142 dw0 |= GEN6_IB_DW0_FORMAT_WORD;
143 offset_align = 2;
144 break;
145 case XGL_INDEX_32:
146 dw0 |= GEN6_IB_DW0_FORMAT_DWORD;
147 offset_align = 4;
148 break;
149 default:
150 cmd->result = XGL_ERROR_INVALID_VALUE;
151 return;
152 break;
153 }
154
155 if (offset % offset_align) {
156 cmd->result = XGL_ERROR_INVALID_VALUE;
157 return;
158 }
159
160 /* aligned and inclusive */
161 end_offset = mem->size - (mem->size % offset_align) - 1;
162
163 cmd_reserve(cmd, cmd_len);
164 cmd_write(cmd, dw0);
165 cmd_write_r(cmd, offset, mem, INTEL_DOMAIN_VERTEX, 0);
166 cmd_write_r(cmd, end_offset, mem, INTEL_DOMAIN_VERTEX, 0);
167}
168
Chia-I Wu7fae4e32014-08-21 11:39:44 +0800169static void gen6_3DSTATE_DEPTH_BUFFER(struct intel_cmd *cmd,
170 const struct intel_ds_view *view)
171{
172 const uint8_t cmd_len = 7;
173 uint32_t dw0;
174
175 CMD_ASSERT(cmd, 6, 7.5);
176
177 dw0 = (cmd_gen(cmd) >= INTEL_GEN(7)) ?
178 GEN_RENDER_CMD(3D, GEN7, 3DSTATE_DEPTH_BUFFER) :
179 GEN_RENDER_CMD(3D, GEN6, 3DSTATE_DEPTH_BUFFER);
180 dw0 |= (cmd_len - 2);
181
182 cmd_reserve(cmd, cmd_len);
183 cmd_write(cmd, dw0);
184 cmd_write(cmd, view->cmd[0]);
185 cmd_write_r(cmd, view->cmd[1], view->img->obj.mem,
186 INTEL_DOMAIN_RENDER,
187 INTEL_DOMAIN_RENDER);
188 cmd_write(cmd, view->cmd[2]);
189 cmd_write(cmd, view->cmd[3]);
190 cmd_write(cmd, view->cmd[4]);
191 cmd_write(cmd, view->cmd[5]);
192}
193
194static void gen6_3DSTATE_STENCIL_BUFFER(struct intel_cmd *cmd,
195 const struct intel_ds_view *view)
196{
197 const uint8_t cmd_len = 3;
198 uint32_t dw0;
199
200 CMD_ASSERT(cmd, 6, 7.5);
201
202 dw0 = (cmd_gen(cmd) >= INTEL_GEN(7)) ?
203 GEN_RENDER_CMD(3D, GEN7, 3DSTATE_STENCIL_BUFFER) :
204 GEN_RENDER_CMD(3D, GEN6, 3DSTATE_STENCIL_BUFFER);
205 dw0 |= (cmd_len - 2);
206
207 cmd_reserve(cmd, cmd_len);
208 cmd_write(cmd, dw0);
209 cmd_write(cmd, view->cmd[6]);
210 cmd_write_r(cmd, view->cmd[7], view->img->obj.mem,
211 INTEL_DOMAIN_RENDER,
212 INTEL_DOMAIN_RENDER);
213}
214
215static void gen6_3DSTATE_HIER_DEPTH_BUFFER(struct intel_cmd *cmd,
216 const struct intel_ds_view *view)
217{
218 const uint8_t cmd_len = 3;
219 uint32_t dw0;
220
221 CMD_ASSERT(cmd, 6, 7.5);
222
223 dw0 = (cmd_gen(cmd) >= INTEL_GEN(7)) ?
224 GEN_RENDER_CMD(3D, GEN7, 3DSTATE_HIER_DEPTH_BUFFER) :
225 GEN_RENDER_CMD(3D, GEN6, 3DSTATE_HIER_DEPTH_BUFFER);
226 dw0 |= (cmd_len - 2);
227
228 cmd_reserve(cmd, cmd_len);
229 cmd_write(cmd, dw0);
230 cmd_write(cmd, view->cmd[8]);
231 cmd_write_r(cmd, view->cmd[9], view->img->obj.mem,
232 INTEL_DOMAIN_RENDER,
233 INTEL_DOMAIN_RENDER);
234}
235
Chia-I Wub2755562014-08-20 13:38:52 +0800236XGL_VOID XGLAPI intelCmdBindPipeline(
237 XGL_CMD_BUFFER cmdBuffer,
238 XGL_PIPELINE_BIND_POINT pipelineBindPoint,
239 XGL_PIPELINE pipeline)
240{
241 struct intel_cmd *cmd = intel_cmd(cmdBuffer);
242
243 switch (pipelineBindPoint) {
244 case XGL_PIPELINE_BIND_POINT_COMPUTE:
Chia-I Wu018a3962014-08-21 10:37:52 +0800245 cmd->bind.pipeline.compute = intel_pipeline(pipeline);
Chia-I Wub2755562014-08-20 13:38:52 +0800246 break;
247 case XGL_PIPELINE_BIND_POINT_GRAPHICS:
Chia-I Wu018a3962014-08-21 10:37:52 +0800248 cmd->bind.pipeline.graphics = intel_pipeline(pipeline);
Chia-I Wub2755562014-08-20 13:38:52 +0800249 break;
250 default:
251 break;
252 }
253}
254
255XGL_VOID XGLAPI intelCmdBindPipelineDelta(
256 XGL_CMD_BUFFER cmdBuffer,
257 XGL_PIPELINE_BIND_POINT pipelineBindPoint,
258 XGL_PIPELINE_DELTA delta)
259{
260 struct intel_cmd *cmd = intel_cmd(cmdBuffer);
261
262 switch (pipelineBindPoint) {
263 case XGL_PIPELINE_BIND_POINT_COMPUTE:
264 cmd->bind.pipeline.compute_delta = delta;
265 break;
266 case XGL_PIPELINE_BIND_POINT_GRAPHICS:
267 cmd->bind.pipeline.graphics_delta = delta;
268 break;
269 default:
270 break;
271 }
272}
273
274XGL_VOID XGLAPI intelCmdBindStateObject(
275 XGL_CMD_BUFFER cmdBuffer,
276 XGL_STATE_BIND_POINT stateBindPoint,
277 XGL_STATE_OBJECT state)
278{
279 struct intel_cmd *cmd = intel_cmd(cmdBuffer);
280
281 switch (stateBindPoint) {
282 case XGL_STATE_BIND_VIEWPORT:
283 cmd->bind.state.viewport =
284 intel_viewport_state((XGL_VIEWPORT_STATE_OBJECT) state);
285 break;
286 case XGL_STATE_BIND_RASTER:
287 cmd->bind.state.raster =
288 intel_raster_state((XGL_RASTER_STATE_OBJECT) state);
289 break;
290 case XGL_STATE_BIND_DEPTH_STENCIL:
291 cmd->bind.state.ds =
292 intel_ds_state((XGL_DEPTH_STENCIL_STATE_OBJECT) state);
293 break;
294 case XGL_STATE_BIND_COLOR_BLEND:
295 cmd->bind.state.blend =
296 intel_blend_state((XGL_COLOR_BLEND_STATE_OBJECT) state);
297 break;
298 case XGL_STATE_BIND_MSAA:
299 cmd->bind.state.msaa =
300 intel_msaa_state((XGL_MSAA_STATE_OBJECT) state);
301 break;
302 default:
303 break;
304 }
305}
306
307XGL_VOID XGLAPI intelCmdBindDescriptorSet(
308 XGL_CMD_BUFFER cmdBuffer,
309 XGL_PIPELINE_BIND_POINT pipelineBindPoint,
310 XGL_UINT index,
311 XGL_DESCRIPTOR_SET descriptorSet,
312 XGL_UINT slotOffset)
313{
314 struct intel_cmd *cmd = intel_cmd(cmdBuffer);
315 struct intel_dset *dset = intel_dset(descriptorSet);
316
317 assert(!index);
318
319 switch (pipelineBindPoint) {
320 case XGL_PIPELINE_BIND_POINT_COMPUTE:
321 cmd->bind.dset.compute = dset;
322 cmd->bind.dset.compute_offset = slotOffset;
323 break;
324 case XGL_PIPELINE_BIND_POINT_GRAPHICS:
325 cmd->bind.dset.graphics = dset;
326 cmd->bind.dset.graphics_offset = slotOffset;
327 break;
328 default:
329 break;
330 }
331}
332
333XGL_VOID XGLAPI intelCmdBindDynamicMemoryView(
334 XGL_CMD_BUFFER cmdBuffer,
335 XGL_PIPELINE_BIND_POINT pipelineBindPoint,
336 const XGL_MEMORY_VIEW_ATTACH_INFO* pMemView)
337{
338 struct intel_cmd *cmd = intel_cmd(cmdBuffer);
339
340 switch (pipelineBindPoint) {
341 case XGL_PIPELINE_BIND_POINT_COMPUTE:
342 intel_mem_view_init(&cmd->bind.mem_view.compute, cmd->dev, pMemView);
343 break;
344 case XGL_PIPELINE_BIND_POINT_GRAPHICS:
345 intel_mem_view_init(&cmd->bind.mem_view.graphics, cmd->dev, pMemView);
346 break;
347 default:
348 break;
349 }
350}
351
352XGL_VOID XGLAPI intelCmdBindIndexData(
353 XGL_CMD_BUFFER cmdBuffer,
354 XGL_GPU_MEMORY mem_,
355 XGL_GPU_SIZE offset,
356 XGL_INDEX_TYPE indexType)
357{
358 struct intel_cmd *cmd = intel_cmd(cmdBuffer);
359 struct intel_mem *mem = intel_mem(mem_);
360
Chia-I Wu9f039862014-08-20 15:39:56 +0800361 if (cmd_gen(cmd) >= INTEL_GEN(7.5)) {
362 gen6_3DSTATE_INDEX_BUFFER(cmd, mem, offset, indexType, false);
363 } else {
364 cmd->bind.index.mem = mem;
365 cmd->bind.index.offset = offset;
366 cmd->bind.index.type = indexType;
367 }
Chia-I Wub2755562014-08-20 13:38:52 +0800368}
369
370XGL_VOID XGLAPI intelCmdBindAttachments(
371 XGL_CMD_BUFFER cmdBuffer,
372 XGL_UINT colorAttachmentCount,
373 const XGL_COLOR_ATTACHMENT_BIND_INFO* pColorAttachments,
374 const XGL_DEPTH_STENCIL_BIND_INFO* pDepthStencilAttachment)
375{
376 struct intel_cmd *cmd = intel_cmd(cmdBuffer);
Chia-I Wu7fae4e32014-08-21 11:39:44 +0800377 const struct intel_ds_view *ds;
Chia-I Wub2755562014-08-20 13:38:52 +0800378 XGL_UINT i;
379
380 for (i = 0; i < colorAttachmentCount; i++) {
381 const XGL_COLOR_ATTACHMENT_BIND_INFO *att = &pColorAttachments[i];
382 struct intel_rt_view *rt = intel_rt_view(att->view);
383
384 cmd->bind.att.rt[i] = rt;
385 }
386
387 cmd->bind.att.rt_count = colorAttachmentCount;
388
389 if (pDepthStencilAttachment) {
Chia-I Wu7fae4e32014-08-21 11:39:44 +0800390 cmd->bind.att.ds = intel_ds_view(pDepthStencilAttachment->view);
391 ds = cmd->bind.att.ds;
392
Chia-I Wub2755562014-08-20 13:38:52 +0800393 } else {
Chia-I Wu7fae4e32014-08-21 11:39:44 +0800394 /* all zeros */
395 static const struct intel_ds_view null_ds;
396 ds = &null_ds;
Chia-I Wub2755562014-08-20 13:38:52 +0800397 }
Chia-I Wu7fae4e32014-08-21 11:39:44 +0800398
399 gen6_3DSTATE_DEPTH_BUFFER(cmd, ds);
400 gen6_3DSTATE_STENCIL_BUFFER(cmd, ds);
401 gen6_3DSTATE_HIER_DEPTH_BUFFER(cmd, ds);
Chia-I Wub2755562014-08-20 13:38:52 +0800402}
403
404XGL_VOID XGLAPI intelCmdDraw(
405 XGL_CMD_BUFFER cmdBuffer,
406 XGL_UINT firstVertex,
407 XGL_UINT vertexCount,
408 XGL_UINT firstInstance,
409 XGL_UINT instanceCount)
410{
Chia-I Wu59c097e2014-08-21 10:51:07 +0800411 struct intel_cmd *cmd = intel_cmd(cmdBuffer);
412 XGL_PRIMITIVE_TOPOLOGY topo;
413
414 /* TODO emit bounded states */
415 topo = XGL_TOPOLOGY_TRIANGLE_LIST;
416
417 if (cmd_gen(cmd) >= INTEL_GEN(7)) {
418 gen7_3DPRIMITIVE(cmd, topo, false, vertexCount, firstVertex,
419 instanceCount, firstInstance, 0);
420 } else {
421 gen6_3DPRIMITIVE(cmd, topo, false, vertexCount, firstVertex,
422 instanceCount, firstInstance, 0);
423 }
Chia-I Wub2755562014-08-20 13:38:52 +0800424}
425
426XGL_VOID XGLAPI intelCmdDrawIndexed(
427 XGL_CMD_BUFFER cmdBuffer,
428 XGL_UINT firstIndex,
429 XGL_UINT indexCount,
430 XGL_INT vertexOffset,
431 XGL_UINT firstInstance,
432 XGL_UINT instanceCount)
433{
Chia-I Wu59c097e2014-08-21 10:51:07 +0800434 struct intel_cmd *cmd = intel_cmd(cmdBuffer);
435 XGL_PRIMITIVE_TOPOLOGY topo;
436
437 /* TODO emit bounded states */
438 topo = XGL_TOPOLOGY_TRIANGLE_LIST;
439
440 if (cmd_gen(cmd) >= INTEL_GEN(7)) {
441 gen7_3DPRIMITIVE(cmd, topo, true, indexCount, firstIndex,
442 instanceCount, firstInstance, vertexOffset);
443 } else {
444 gen6_3DPRIMITIVE(cmd, topo, true, indexCount, firstIndex,
445 instanceCount, firstInstance, vertexOffset);
446 }
Chia-I Wub2755562014-08-20 13:38:52 +0800447}
448
449XGL_VOID XGLAPI intelCmdDrawIndirect(
450 XGL_CMD_BUFFER cmdBuffer,
451 XGL_GPU_MEMORY mem,
452 XGL_GPU_SIZE offset,
453 XGL_UINT32 count,
454 XGL_UINT32 stride)
455{
Chia-I Wu59c097e2014-08-21 10:51:07 +0800456 struct intel_cmd *cmd = intel_cmd(cmdBuffer);
457
458 cmd->result = XGL_ERROR_UNKNOWN;
Chia-I Wub2755562014-08-20 13:38:52 +0800459}
460
461XGL_VOID XGLAPI intelCmdDrawIndexedIndirect(
462 XGL_CMD_BUFFER cmdBuffer,
463 XGL_GPU_MEMORY mem,
464 XGL_GPU_SIZE offset,
465 XGL_UINT32 count,
466 XGL_UINT32 stride)
467{
Chia-I Wu59c097e2014-08-21 10:51:07 +0800468 struct intel_cmd *cmd = intel_cmd(cmdBuffer);
469
470 cmd->result = XGL_ERROR_UNKNOWN;
Chia-I Wub2755562014-08-20 13:38:52 +0800471}
472
473XGL_VOID XGLAPI intelCmdDispatch(
474 XGL_CMD_BUFFER cmdBuffer,
475 XGL_UINT x,
476 XGL_UINT y,
477 XGL_UINT z)
478{
Chia-I Wu59c097e2014-08-21 10:51:07 +0800479 struct intel_cmd *cmd = intel_cmd(cmdBuffer);
480
481 cmd->result = XGL_ERROR_UNKNOWN;
Chia-I Wub2755562014-08-20 13:38:52 +0800482}
483
484XGL_VOID XGLAPI intelCmdDispatchIndirect(
485 XGL_CMD_BUFFER cmdBuffer,
486 XGL_GPU_MEMORY mem,
487 XGL_GPU_SIZE offset)
488{
Chia-I Wu59c097e2014-08-21 10:51:07 +0800489 struct intel_cmd *cmd = intel_cmd(cmdBuffer);
490
491 cmd->result = XGL_ERROR_UNKNOWN;
Chia-I Wub2755562014-08-20 13:38:52 +0800492}