blob: 544013310d5203104b24d7f21d569509f17a0d89 [file] [log] [blame]
Chia-I Wuf8385062015-01-04 16:27:24 +08001/*
2 * XGL
3 *
4 * Copyright (C) 2015 LunarG, Inc.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included
14 * in all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE.
23 *
24 * Authors:
25 * Chia-I Wu <olv@lunarg.com>
26 */
27
28#include "buf.h"
29#include "cmd.h"
30#include "dev.h"
31#include "gpu.h"
32#include "img.h"
33#include "sampler.h"
34#include "view.h"
35#include "desc.h"
36
37enum intel_desc_surface_type {
38 INTEL_DESC_SURFACE_UNUSED,
39 INTEL_DESC_SURFACE_BUF,
40 INTEL_DESC_SURFACE_IMG,
41};
42
43struct intel_desc_surface {
44 const struct intel_mem *mem;
45 bool read_only;
46
47 enum intel_desc_surface_type type;
48 union {
49 const void *unused;
50 const struct intel_buf_view *buf;
51 const struct intel_img_view *img;
52 } u;
53};
54
55struct intel_desc_sampler {
56 const struct intel_sampler *sampler;
57};
58
Chia-I Wu7732cb22015-03-26 15:27:55 +080059bool intel_desc_iter_init_for_binding(struct intel_desc_iter *iter,
60 const struct intel_desc_layout *layout,
61 uint32_t binding_index, uint32_t array_base)
62{
63 const struct intel_desc_layout_binding *binding;
64
65 if (binding_index >= layout->binding_count ||
66 array_base >= layout->bindings[binding_index].array_size)
67 return false;
68
69 binding = &layout->bindings[binding_index];
70
71 iter->type = binding->type;
72 iter->increment = binding->increment;
73 iter->size = binding->array_size;
74
75 intel_desc_offset_mad(&iter->begin, &binding->increment,
76 &binding->offset, array_base);
77 intel_desc_offset_add(&iter->end, &iter->begin, &binding->increment);
78 iter->cur = array_base;
79
80 return true;
81}
82
83static bool desc_iter_init_for_update(struct intel_desc_iter *iter,
84 const struct intel_desc_set *set,
85 XGL_DESCRIPTOR_TYPE type,
86 uint32_t binding_index, uint32_t array_base)
87{
88 if (!intel_desc_iter_init_for_binding(iter, set->layout,
89 binding_index, array_base) || iter->type != type)
90 return false;
91
92 intel_desc_offset_add(&iter->begin, &iter->begin, &set->region_begin);
93 intel_desc_offset_add(&iter->end, &iter->end, &set->region_begin);
94
95 return true;
96}
97
98bool intel_desc_iter_advance(struct intel_desc_iter *iter)
99{
100 if (iter->cur >= iter->size)
101 return false;
102
103 iter->cur++;
104
105 iter->begin = iter->end;
106 intel_desc_offset_add(&iter->end, &iter->end, &iter->increment);
107
108 return true;
109}
110
Chia-I Wu8d24b3b2015-03-26 13:14:16 +0800111static bool desc_region_init_desc_sizes(struct intel_desc_region *region,
112 const struct intel_gpu *gpu)
Chia-I Wuf8385062015-01-04 16:27:24 +0800113{
Chia-I Wu8d24b3b2015-03-26 13:14:16 +0800114 region->surface_desc_size = sizeof(struct intel_desc_surface);
115 region->sampler_desc_size = sizeof(struct intel_desc_sampler);
Chia-I Wuf8385062015-01-04 16:27:24 +0800116
117 return true;
118}
119
Chia-I Wu8d24b3b2015-03-26 13:14:16 +0800120XGL_RESULT intel_desc_region_create(struct intel_dev *dev,
121 struct intel_desc_region **region_ret)
Chia-I Wuf8385062015-01-04 16:27:24 +0800122{
123 const uint32_t surface_count = 16384;
124 const uint32_t sampler_count = 16384;
Chia-I Wu8d24b3b2015-03-26 13:14:16 +0800125 struct intel_desc_region *region;
Chia-I Wuf8385062015-01-04 16:27:24 +0800126
Chia-I Wu8d24b3b2015-03-26 13:14:16 +0800127 region = intel_alloc(dev, sizeof(*region), 0, XGL_SYSTEM_ALLOC_INTERNAL);
128 if (!region)
Chia-I Wuf8385062015-01-04 16:27:24 +0800129 return XGL_ERROR_OUT_OF_MEMORY;
130
Chia-I Wu8d24b3b2015-03-26 13:14:16 +0800131 memset(region, 0, sizeof(*region));
Chia-I Wuf8385062015-01-04 16:27:24 +0800132
Chia-I Wu8d24b3b2015-03-26 13:14:16 +0800133 if (!desc_region_init_desc_sizes(region, dev->gpu)) {
134 intel_free(dev, region);
Chia-I Wuf8385062015-01-04 16:27:24 +0800135 return XGL_ERROR_UNKNOWN;
136 }
137
Chia-I Wu8d24b3b2015-03-26 13:14:16 +0800138 intel_desc_offset_set(&region->size,
139 region->surface_desc_size * surface_count,
140 region->sampler_desc_size * sampler_count);
Chia-I Wuf8385062015-01-04 16:27:24 +0800141
Chia-I Wu8d24b3b2015-03-26 13:14:16 +0800142 region->surfaces = intel_alloc(dev, region->size.surface,
Chia-I Wuf8385062015-01-04 16:27:24 +0800143 64, XGL_SYSTEM_ALLOC_INTERNAL);
Chia-I Wu8d24b3b2015-03-26 13:14:16 +0800144 if (!region->surfaces) {
145 intel_free(dev, region);
Chia-I Wuf8385062015-01-04 16:27:24 +0800146 return XGL_ERROR_OUT_OF_MEMORY;
147 }
148
Chia-I Wu8d24b3b2015-03-26 13:14:16 +0800149 region->samplers = intel_alloc(dev, region->size.sampler,
Chia-I Wuf8385062015-01-04 16:27:24 +0800150 64, XGL_SYSTEM_ALLOC_INTERNAL);
Chia-I Wu8d24b3b2015-03-26 13:14:16 +0800151 if (!region->samplers) {
152 intel_free(dev, region->surfaces);
153 intel_free(dev, region);
Chia-I Wuf8385062015-01-04 16:27:24 +0800154 return XGL_ERROR_OUT_OF_MEMORY;
155 }
156
Chia-I Wu8d24b3b2015-03-26 13:14:16 +0800157 *region_ret = region;
Chia-I Wuf8385062015-01-04 16:27:24 +0800158
159 return XGL_SUCCESS;
160}
161
Chia-I Wu8d24b3b2015-03-26 13:14:16 +0800162void intel_desc_region_destroy(struct intel_dev *dev,
163 struct intel_desc_region *region)
Chia-I Wuf8385062015-01-04 16:27:24 +0800164{
Chia-I Wu8d24b3b2015-03-26 13:14:16 +0800165 intel_free(dev, region->samplers);
166 intel_free(dev, region->surfaces);
167 intel_free(dev, region);
Chia-I Wuf8385062015-01-04 16:27:24 +0800168}
169
170/**
Chia-I Wu8d24b3b2015-03-26 13:14:16 +0800171 * Get the size of a descriptor in the region.
Chia-I Wuf8385062015-01-04 16:27:24 +0800172 */
Chia-I Wu8d24b3b2015-03-26 13:14:16 +0800173static XGL_RESULT desc_region_get_desc_size(const struct intel_desc_region *region,
Chia-I Wuf8385062015-01-04 16:27:24 +0800174 XGL_DESCRIPTOR_TYPE type,
175 struct intel_desc_offset *size)
176{
177 uint32_t surface_size = 0, sampler_size = 0;
178
179 switch (type) {
180 case XGL_DESCRIPTOR_TYPE_SAMPLER:
Chia-I Wu8d24b3b2015-03-26 13:14:16 +0800181 sampler_size = region->sampler_desc_size;
Chia-I Wuf8385062015-01-04 16:27:24 +0800182 break;
183 case XGL_DESCRIPTOR_TYPE_SAMPLER_TEXTURE:
Chia-I Wu8d24b3b2015-03-26 13:14:16 +0800184 surface_size = region->surface_desc_size;
185 sampler_size = region->sampler_desc_size;
Chia-I Wuf8385062015-01-04 16:27:24 +0800186 break;
187 case XGL_DESCRIPTOR_TYPE_TEXTURE:
188 case XGL_DESCRIPTOR_TYPE_TEXTURE_BUFFER:
189 case XGL_DESCRIPTOR_TYPE_IMAGE:
190 case XGL_DESCRIPTOR_TYPE_IMAGE_BUFFER:
191 case XGL_DESCRIPTOR_TYPE_UNIFORM_BUFFER:
192 case XGL_DESCRIPTOR_TYPE_SHADER_STORAGE_BUFFER:
Chia-I Wuf8385062015-01-04 16:27:24 +0800193 case XGL_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC:
194 case XGL_DESCRIPTOR_TYPE_SHADER_STORAGE_BUFFER_DYNAMIC:
Chia-I Wu8d24b3b2015-03-26 13:14:16 +0800195 surface_size = region->surface_desc_size;
Chia-I Wuf8385062015-01-04 16:27:24 +0800196 break;
197 default:
198 assert(!"unknown descriptor type");
199 return XGL_ERROR_INVALID_VALUE;
200 break;
201 }
202
203 intel_desc_offset_set(size, surface_size, sampler_size);
204
205 return XGL_SUCCESS;
206}
207
Chia-I Wu8d24b3b2015-03-26 13:14:16 +0800208XGL_RESULT intel_desc_region_alloc(struct intel_desc_region *region,
209 const XGL_DESCRIPTOR_POOL_CREATE_INFO *info,
210 struct intel_desc_offset *begin,
211 struct intel_desc_offset *end)
Chia-I Wuf8385062015-01-04 16:27:24 +0800212{
213 uint32_t surface_size = 0, sampler_size = 0;
214 struct intel_desc_offset alloc;
215 uint32_t i;
216
217 /* calculate sizes needed */
218 for (i = 0; i < info->count; i++) {
219 const XGL_DESCRIPTOR_TYPE_COUNT *tc = &info->pTypeCount[i];
220 struct intel_desc_offset size;
221 XGL_RESULT ret;
222
Chia-I Wu8d24b3b2015-03-26 13:14:16 +0800223 ret = desc_region_get_desc_size(region, tc->type, &size);
Chia-I Wuf8385062015-01-04 16:27:24 +0800224 if (ret != XGL_SUCCESS)
225 return ret;
226
227 surface_size += size.surface * tc->count;
228 sampler_size += size.sampler * tc->count;
229 }
230
231 intel_desc_offset_set(&alloc, surface_size, sampler_size);
232
Chia-I Wu8d24b3b2015-03-26 13:14:16 +0800233 *begin = region->cur;
234 intel_desc_offset_add(end, &region->cur, &alloc);
Chia-I Wuf8385062015-01-04 16:27:24 +0800235
Chia-I Wu8d24b3b2015-03-26 13:14:16 +0800236 if (!intel_desc_offset_within(end, &region->size))
Chia-I Wuf8385062015-01-04 16:27:24 +0800237 return XGL_ERROR_OUT_OF_MEMORY;
238
239 /* increment the writer pointer */
Chia-I Wu8d24b3b2015-03-26 13:14:16 +0800240 region->cur = *end;
Chia-I Wuf8385062015-01-04 16:27:24 +0800241
242 return XGL_SUCCESS;
243}
244
Chia-I Wu8d24b3b2015-03-26 13:14:16 +0800245static void desc_region_validate_begin_end(const struct intel_desc_region *region,
246 const struct intel_desc_offset *begin,
247 const struct intel_desc_offset *end)
Chia-I Wuf8385062015-01-04 16:27:24 +0800248{
Chia-I Wu8d24b3b2015-03-26 13:14:16 +0800249 assert(begin->surface % region->surface_desc_size == 0 &&
250 begin->sampler % region->sampler_desc_size == 0);
251 assert(end->surface % region->surface_desc_size == 0 &&
252 end->sampler % region->sampler_desc_size == 0);
253 assert(intel_desc_offset_within(end, &region->size));
Chia-I Wuf8385062015-01-04 16:27:24 +0800254}
255
Chia-I Wu8d24b3b2015-03-26 13:14:16 +0800256void intel_desc_region_free(struct intel_desc_region *region,
257 const struct intel_desc_offset *begin,
258 const struct intel_desc_offset *end)
Chia-I Wuf8385062015-01-04 16:27:24 +0800259{
Chia-I Wu8d24b3b2015-03-26 13:14:16 +0800260 desc_region_validate_begin_end(region, begin, end);
Chia-I Wuf8385062015-01-04 16:27:24 +0800261
262 /* is it ok not to reclaim? */
263}
264
Chia-I Wu8d24b3b2015-03-26 13:14:16 +0800265XGL_RESULT intel_desc_region_begin_update(struct intel_desc_region *region,
266 XGL_DESCRIPTOR_UPDATE_MODE mode)
Chia-I Wuf8385062015-01-04 16:27:24 +0800267{
268 /* no-op */
269 return XGL_SUCCESS;
270}
271
Chia-I Wu8d24b3b2015-03-26 13:14:16 +0800272XGL_RESULT intel_desc_region_end_update(struct intel_desc_region *region,
273 struct intel_cmd *cmd)
Chia-I Wuf8385062015-01-04 16:27:24 +0800274{
275 /* No pipelined update. cmd_draw() will do the work. */
276 return XGL_SUCCESS;
277}
278
Chia-I Wu8d24b3b2015-03-26 13:14:16 +0800279void intel_desc_region_clear(struct intel_desc_region *region,
280 const struct intel_desc_offset *begin,
281 const struct intel_desc_offset *end)
Chia-I Wuf8385062015-01-04 16:27:24 +0800282{
283 uint32_t i;
284
Chia-I Wu8d24b3b2015-03-26 13:14:16 +0800285 desc_region_validate_begin_end(region, begin, end);
Chia-I Wuf8385062015-01-04 16:27:24 +0800286
Chia-I Wu8d24b3b2015-03-26 13:14:16 +0800287 for (i = begin->surface; i < end->surface; i += region->surface_desc_size) {
Chia-I Wuf8385062015-01-04 16:27:24 +0800288 struct intel_desc_surface *desc = (struct intel_desc_surface *)
Chia-I Wu8d24b3b2015-03-26 13:14:16 +0800289 ((char *) region->surfaces + i);
Chia-I Wuf8385062015-01-04 16:27:24 +0800290
291 desc->mem = NULL;
292 desc->type = INTEL_DESC_SURFACE_UNUSED;
293 desc->u.unused = NULL;
294 }
295
Chia-I Wu8d24b3b2015-03-26 13:14:16 +0800296 for (i = begin->sampler; i < end->sampler; i += region->sampler_desc_size) {
Chia-I Wuf8385062015-01-04 16:27:24 +0800297 struct intel_desc_sampler *desc = (struct intel_desc_sampler *)
Chia-I Wu8d24b3b2015-03-26 13:14:16 +0800298 ((char *) region->samplers + i);
Chia-I Wuf8385062015-01-04 16:27:24 +0800299
300 desc->sampler = NULL;
301 }
302}
303
Chia-I Wu8d24b3b2015-03-26 13:14:16 +0800304void intel_desc_region_update(struct intel_desc_region *region,
305 const struct intel_desc_offset *begin,
306 const struct intel_desc_offset *end,
307 const struct intel_desc_surface *surfaces,
308 const struct intel_desc_sampler *samplers)
Chia-I Wuf8385062015-01-04 16:27:24 +0800309{
Chia-I Wu8d24b3b2015-03-26 13:14:16 +0800310 desc_region_validate_begin_end(region, begin, end);
Chia-I Wuf8385062015-01-04 16:27:24 +0800311
312 if (begin->surface < end->surface) {
Chia-I Wu8d24b3b2015-03-26 13:14:16 +0800313 memcpy((char *) region->surfaces + begin->surface, surfaces,
Chia-I Wuf8385062015-01-04 16:27:24 +0800314 end->surface - begin->surface);
315 }
316
317 if (begin->sampler < end->sampler) {
Chia-I Wu8d24b3b2015-03-26 13:14:16 +0800318 memcpy((char *) region->samplers + begin->sampler, samplers,
Chia-I Wuf8385062015-01-04 16:27:24 +0800319 end->sampler - begin->sampler);
320 }
321}
322
Chia-I Wu8d24b3b2015-03-26 13:14:16 +0800323void intel_desc_region_copy(struct intel_desc_region *region,
324 const struct intel_desc_offset *begin,
325 const struct intel_desc_offset *end,
326 const struct intel_desc_offset *src)
Chia-I Wuf8385062015-01-04 16:27:24 +0800327{
328 struct intel_desc_offset src_end;
329 const struct intel_desc_surface *surfaces;
330 const struct intel_desc_sampler *samplers;
331
332 /* no overlap */
333 assert(intel_desc_offset_within(src, begin) ||
334 intel_desc_offset_within(end, src));
335
Chia-I Wu8d24b3b2015-03-26 13:14:16 +0800336 /* no read past region */
Chia-I Wuf8385062015-01-04 16:27:24 +0800337 intel_desc_offset_sub(&src_end, end, begin);
338 intel_desc_offset_add(&src_end, src, &src_end);
Chia-I Wu8d24b3b2015-03-26 13:14:16 +0800339 assert(intel_desc_offset_within(&src_end, &region->size));
Chia-I Wuf8385062015-01-04 16:27:24 +0800340
341 surfaces = (const struct intel_desc_surface *)
Chia-I Wu8d24b3b2015-03-26 13:14:16 +0800342 ((const char *) region->surfaces + src->surface);
Tony Barbour379e0a72015-02-05 11:09:34 -0700343 samplers = (const struct intel_desc_sampler *)
Chia-I Wu8d24b3b2015-03-26 13:14:16 +0800344 ((const char *) region->samplers + src->sampler);
Chia-I Wuf8385062015-01-04 16:27:24 +0800345
Chia-I Wu8d24b3b2015-03-26 13:14:16 +0800346 intel_desc_region_update(region, begin, end, surfaces, samplers);
Chia-I Wuf8385062015-01-04 16:27:24 +0800347}
348
Chia-I Wu862c5572015-03-28 15:23:55 +0800349void intel_desc_region_read_surface(const struct intel_desc_region *region,
350 const struct intel_desc_offset *offset,
351 XGL_PIPELINE_SHADER_STAGE stage,
352 const struct intel_mem **mem,
353 bool *read_only,
354 const uint32_t **cmd,
355 uint32_t *cmd_len)
356{
357 const struct intel_desc_surface *desc;
358 struct intel_desc_offset end;
359
360 intel_desc_offset_set(&end,
361 offset->surface + region->surface_desc_size, offset->sampler);
362 desc_region_validate_begin_end(region, offset, &end);
363
364 desc = (const struct intel_desc_surface *)
365 ((const char *) region->surfaces + offset->surface);
366
367 *mem = desc->mem;
368 *read_only = desc->read_only;
369 switch (desc->type) {
370 case INTEL_DESC_SURFACE_BUF:
371 *cmd = (stage == XGL_SHADER_STAGE_FRAGMENT) ?
372 desc->u.buf->fs_cmd : desc->u.buf->cmd;
373 *cmd_len = desc->u.buf->cmd_len;
374 break;
375 case INTEL_DESC_SURFACE_IMG:
376 *cmd = desc->u.img->cmd;
377 *cmd_len = desc->u.img->cmd_len;
378 break;
379 case INTEL_DESC_SURFACE_UNUSED:
380 default:
381 *cmd = NULL;
382 *cmd_len = 0;
383 break;
384 }
385}
386
387void intel_desc_region_read_sampler(const struct intel_desc_region *region,
388 const struct intel_desc_offset *offset,
389 const struct intel_sampler **sampler)
390{
391 const struct intel_desc_sampler *desc;
392 struct intel_desc_offset end;
393
394 intel_desc_offset_set(&end,
395 offset->surface, offset->sampler + region->sampler_desc_size);
396 desc_region_validate_begin_end(region, offset, &end);
397
398 desc = (const struct intel_desc_sampler *)
399 ((const char *) region->samplers + offset->sampler);
400
401 *sampler = desc->sampler;
402}
403
Chia-I Wu8d24b3b2015-03-26 13:14:16 +0800404static void desc_pool_destroy(struct intel_obj *obj)
Chia-I Wuf8385062015-01-04 16:27:24 +0800405{
Chia-I Wu8d24b3b2015-03-26 13:14:16 +0800406 struct intel_desc_pool *pool = intel_desc_pool_from_obj(obj);
Chia-I Wuf8385062015-01-04 16:27:24 +0800407
Chia-I Wu8d24b3b2015-03-26 13:14:16 +0800408 intel_desc_pool_destroy(pool);
Chia-I Wuf8385062015-01-04 16:27:24 +0800409}
410
Chia-I Wu8d24b3b2015-03-26 13:14:16 +0800411XGL_RESULT intel_desc_pool_create(struct intel_dev *dev,
412 XGL_DESCRIPTOR_POOL_USAGE usage,
413 uint32_t max_sets,
414 const XGL_DESCRIPTOR_POOL_CREATE_INFO *info,
415 struct intel_desc_pool **pool_ret)
Chia-I Wuf8385062015-01-04 16:27:24 +0800416{
Chia-I Wu8d24b3b2015-03-26 13:14:16 +0800417 struct intel_desc_pool *pool;
Chia-I Wuf8385062015-01-04 16:27:24 +0800418 XGL_RESULT ret;
419
Chia-I Wu8d24b3b2015-03-26 13:14:16 +0800420 pool = (struct intel_desc_pool *) intel_base_create(&dev->base.handle,
421 sizeof(*pool), dev->base.dbg, XGL_DBG_OBJECT_DESCRIPTOR_POOL,
Chia-I Wu545c2e12015-02-22 13:19:54 +0800422 info, 0);
Chia-I Wu8d24b3b2015-03-26 13:14:16 +0800423 if (!pool)
Chia-I Wuf8385062015-01-04 16:27:24 +0800424 return XGL_ERROR_OUT_OF_MEMORY;
425
Chia-I Wu8d24b3b2015-03-26 13:14:16 +0800426 pool->dev = dev;
Chia-I Wuf8385062015-01-04 16:27:24 +0800427
Chia-I Wu8d24b3b2015-03-26 13:14:16 +0800428 ret = intel_desc_region_alloc(dev->desc_region, info,
429 &pool->region_begin, &pool->region_end);
Chia-I Wuf8385062015-01-04 16:27:24 +0800430 if (ret != XGL_SUCCESS) {
Chia-I Wu8d24b3b2015-03-26 13:14:16 +0800431 intel_base_destroy(&pool->obj.base);
Chia-I Wuf8385062015-01-04 16:27:24 +0800432 return ret;
433 }
434
435 /* point to head */
Chia-I Wu8d24b3b2015-03-26 13:14:16 +0800436 pool->cur = pool->region_begin;
Chia-I Wuf8385062015-01-04 16:27:24 +0800437
Chia-I Wu8d24b3b2015-03-26 13:14:16 +0800438 pool->obj.destroy = desc_pool_destroy;
Chia-I Wuf8385062015-01-04 16:27:24 +0800439
Chia-I Wu8d24b3b2015-03-26 13:14:16 +0800440 *pool_ret = pool;
Chia-I Wuf8385062015-01-04 16:27:24 +0800441
442 return XGL_SUCCESS;
443}
444
Chia-I Wu8d24b3b2015-03-26 13:14:16 +0800445void intel_desc_pool_destroy(struct intel_desc_pool *pool)
Chia-I Wuf8385062015-01-04 16:27:24 +0800446{
Chia-I Wu8d24b3b2015-03-26 13:14:16 +0800447 intel_desc_region_free(pool->dev->desc_region,
448 &pool->region_begin, &pool->region_end);
449 intel_base_destroy(&pool->obj.base);
Chia-I Wuf8385062015-01-04 16:27:24 +0800450}
451
Chia-I Wu8d24b3b2015-03-26 13:14:16 +0800452XGL_RESULT intel_desc_pool_alloc(struct intel_desc_pool *pool,
453 const struct intel_desc_layout *layout,
454 struct intel_desc_offset *begin,
455 struct intel_desc_offset *end)
Chia-I Wuf8385062015-01-04 16:27:24 +0800456{
Chia-I Wu8d24b3b2015-03-26 13:14:16 +0800457 *begin = pool->cur;
458 intel_desc_offset_add(end, &pool->cur, &layout->region_size);
Chia-I Wuf8385062015-01-04 16:27:24 +0800459
Chia-I Wu8d24b3b2015-03-26 13:14:16 +0800460 if (!intel_desc_offset_within(end, &pool->region_end))
Chia-I Wuf8385062015-01-04 16:27:24 +0800461 return XGL_ERROR_OUT_OF_MEMORY;
462
463 /* increment the writer pointer */
Chia-I Wu8d24b3b2015-03-26 13:14:16 +0800464 pool->cur = *end;
Chia-I Wuf8385062015-01-04 16:27:24 +0800465
466 return XGL_SUCCESS;
467}
468
Chia-I Wudee95612015-03-26 15:23:52 +0800469void intel_desc_pool_reset(struct intel_desc_pool *pool)
Chia-I Wuf8385062015-01-04 16:27:24 +0800470{
471 /* reset to head */
Chia-I Wu8d24b3b2015-03-26 13:14:16 +0800472 pool->cur = pool->region_begin;
Chia-I Wuf8385062015-01-04 16:27:24 +0800473}
474
475static void desc_set_destroy(struct intel_obj *obj)
476{
477 struct intel_desc_set *set = intel_desc_set_from_obj(obj);
478
479 intel_desc_set_destroy(set);
480}
481
482XGL_RESULT intel_desc_set_create(struct intel_dev *dev,
Chia-I Wu8d24b3b2015-03-26 13:14:16 +0800483 struct intel_desc_pool *pool,
Chia-I Wuf8385062015-01-04 16:27:24 +0800484 XGL_DESCRIPTOR_SET_USAGE usage,
485 const struct intel_desc_layout *layout,
486 struct intel_desc_set **set_ret)
487{
488 struct intel_desc_set *set;
489 XGL_RESULT ret;
490
Chia-I Wu545c2e12015-02-22 13:19:54 +0800491 set = (struct intel_desc_set *) intel_base_create(&dev->base.handle,
492 sizeof(*set), dev->base.dbg, XGL_DBG_OBJECT_DESCRIPTOR_SET,
493 NULL, 0);
Chia-I Wuf8385062015-01-04 16:27:24 +0800494 if (!set)
495 return XGL_ERROR_OUT_OF_MEMORY;
496
Chia-I Wu8d24b3b2015-03-26 13:14:16 +0800497 set->region = dev->desc_region;
498 ret = intel_desc_pool_alloc(pool, layout,
499 &set->region_begin, &set->region_end);
Chia-I Wuf8385062015-01-04 16:27:24 +0800500 if (ret != XGL_SUCCESS) {
501 intel_base_destroy(&set->obj.base);
502 return ret;
503 }
504
505 set->layout = layout;
506
507 set->obj.destroy = desc_set_destroy;
508
509 *set_ret = set;
510
511 return XGL_SUCCESS;
512}
513
514void intel_desc_set_destroy(struct intel_desc_set *set)
515{
516 intel_base_destroy(&set->obj.base);
517}
518
Chia-I Wuf8385062015-01-04 16:27:24 +0800519static bool desc_set_img_layout_read_only(XGL_IMAGE_LAYOUT layout)
520{
521 switch (layout) {
522 case XGL_IMAGE_LAYOUT_DEPTH_STENCIL_READ_ONLY_OPTIMAL:
523 case XGL_IMAGE_LAYOUT_SHADER_READ_ONLY_OPTIMAL:
524 case XGL_IMAGE_LAYOUT_TRANSFER_SOURCE_OPTIMAL:
525 return true;
526 default:
527 return false;
528 }
529}
530
531void intel_desc_set_update_samplers(struct intel_desc_set *set,
532 const XGL_UPDATE_SAMPLERS *update)
533{
Chia-I Wu7732cb22015-03-26 15:27:55 +0800534 struct intel_desc_iter iter;
Chia-I Wuf8385062015-01-04 16:27:24 +0800535 uint32_t i;
536
Chia-I Wu7732cb22015-03-26 15:27:55 +0800537 if (!desc_iter_init_for_update(&iter, set, XGL_DESCRIPTOR_TYPE_SAMPLER,
538 update->binding, update->arrayIndex))
Chia-I Wuf8385062015-01-04 16:27:24 +0800539 return;
540
541 for (i = 0; i < update->count; i++) {
542 const struct intel_sampler *sampler =
543 intel_sampler((XGL_SAMPLER) update->pSamplers[i]);
544 struct intel_desc_sampler desc;
545
Chia-I Wuf8385062015-01-04 16:27:24 +0800546 desc.sampler = sampler;
Chia-I Wu7732cb22015-03-26 15:27:55 +0800547 intel_desc_region_update(set->region, &iter.begin, &iter.end,
548 NULL, &desc);
Chia-I Wuf8385062015-01-04 16:27:24 +0800549
Chia-I Wu7732cb22015-03-26 15:27:55 +0800550 if (!intel_desc_iter_advance(&iter))
Chia-I Wuf8385062015-01-04 16:27:24 +0800551 break;
552 }
553}
554
555void intel_desc_set_update_sampler_textures(struct intel_desc_set *set,
556 const XGL_UPDATE_SAMPLER_TEXTURES *update)
557{
Chia-I Wu7732cb22015-03-26 15:27:55 +0800558 struct intel_desc_iter iter;
559 const struct intel_desc_layout_binding *binding;
Chia-I Wuf8385062015-01-04 16:27:24 +0800560 uint32_t i;
561
Chia-I Wu7732cb22015-03-26 15:27:55 +0800562 if (!desc_iter_init_for_update(&iter, set, XGL_DESCRIPTOR_TYPE_SAMPLER_TEXTURE,
563 update->binding, update->arrayIndex))
Chia-I Wuf8385062015-01-04 16:27:24 +0800564 return;
565
Chia-I Wu7732cb22015-03-26 15:27:55 +0800566 binding = &set->layout->bindings[update->binding];
567
Chia-I Wu310eece2015-03-27 12:56:09 +0800568 if (binding->shared_immutable_sampler) {
Chia-I Wu7732cb22015-03-26 15:27:55 +0800569 struct intel_desc_offset end;
570 struct intel_desc_sampler sampler_desc;
571
572 assert(!iter.increment.sampler);
573 intel_desc_offset_set(&end, iter.begin.surface,
574 iter.begin.sampler + set->region->sampler_desc_size);
575
Chia-I Wu310eece2015-03-27 12:56:09 +0800576 sampler_desc.sampler = binding->shared_immutable_sampler;
Chia-I Wu7732cb22015-03-26 15:27:55 +0800577 intel_desc_region_update(set->region, &iter.begin, &end,
578 NULL, &sampler_desc);
579 }
580
Chia-I Wuf8385062015-01-04 16:27:24 +0800581 for (i = 0; i < update->count; i++) {
Chia-I Wu310eece2015-03-27 12:56:09 +0800582 const struct intel_sampler *sampler = (binding->immutable_samplers) ?
583 binding->immutable_samplers[update->arrayIndex + i] :
Chia-I Wu7732cb22015-03-26 15:27:55 +0800584 intel_sampler(update->pSamplerImageViews[i].sampler);
Chia-I Wuf8385062015-01-04 16:27:24 +0800585 const XGL_IMAGE_VIEW_ATTACH_INFO *info =
586 update->pSamplerImageViews[i].pImageView;
587 const struct intel_img_view *view = intel_img_view(info->view);
588 struct intel_desc_surface view_desc;
589 struct intel_desc_sampler sampler_desc;
590
Chia-I Wuf8385062015-01-04 16:27:24 +0800591 view_desc.mem = view->img->obj.mem;
592 view_desc.read_only = desc_set_img_layout_read_only(info->layout);
593 view_desc.type = INTEL_DESC_SURFACE_IMG;
594 view_desc.u.img = view;
595
596 sampler_desc.sampler = sampler;
597
Chia-I Wu7732cb22015-03-26 15:27:55 +0800598 intel_desc_region_update(set->region, &iter.begin, &iter.end,
599 &view_desc, &sampler_desc);
Chia-I Wuf8385062015-01-04 16:27:24 +0800600
Chia-I Wu7732cb22015-03-26 15:27:55 +0800601 if (!intel_desc_iter_advance(&iter))
Chia-I Wuf8385062015-01-04 16:27:24 +0800602 break;
603 }
604}
605
606void intel_desc_set_update_images(struct intel_desc_set *set,
607 const XGL_UPDATE_IMAGES *update)
608{
Chia-I Wu7732cb22015-03-26 15:27:55 +0800609 struct intel_desc_iter iter;
Chia-I Wuf8385062015-01-04 16:27:24 +0800610 uint32_t i;
611
Chia-I Wu7732cb22015-03-26 15:27:55 +0800612 if (!desc_iter_init_for_update(&iter, set, update->descriptorType,
613 update->binding, update->arrayIndex))
Chia-I Wuf8385062015-01-04 16:27:24 +0800614 return;
615
616 for (i = 0; i < update->count; i++) {
Chia-I Wu7732cb22015-03-26 15:27:55 +0800617 const XGL_IMAGE_VIEW_ATTACH_INFO *info = &update->pImageViews[i];
Chia-I Wuf8385062015-01-04 16:27:24 +0800618 const struct intel_img_view *view = intel_img_view(info->view);
619 struct intel_desc_surface desc;
620
Chia-I Wuf8385062015-01-04 16:27:24 +0800621 desc.mem = view->img->obj.mem;
622 desc.read_only = desc_set_img_layout_read_only(info->layout);
623 desc.type = INTEL_DESC_SURFACE_IMG;
624 desc.u.img = view;
Chia-I Wu7732cb22015-03-26 15:27:55 +0800625 intel_desc_region_update(set->region, &iter.begin, &iter.end,
626 &desc, NULL);
Chia-I Wuf8385062015-01-04 16:27:24 +0800627
Chia-I Wu7732cb22015-03-26 15:27:55 +0800628 if (!intel_desc_iter_advance(&iter))
Chia-I Wuf8385062015-01-04 16:27:24 +0800629 break;
630 }
631}
632
633void intel_desc_set_update_buffers(struct intel_desc_set *set,
634 const XGL_UPDATE_BUFFERS *update)
635{
Chia-I Wu7732cb22015-03-26 15:27:55 +0800636 struct intel_desc_iter iter;
Chia-I Wuf8385062015-01-04 16:27:24 +0800637 uint32_t i;
638
Chia-I Wu7732cb22015-03-26 15:27:55 +0800639 if (!desc_iter_init_for_update(&iter, set, update->descriptorType,
640 update->binding, update->arrayIndex))
Chia-I Wuf8385062015-01-04 16:27:24 +0800641 return;
642
643 for (i = 0; i < update->count; i++) {
Chia-I Wu7732cb22015-03-26 15:27:55 +0800644 const XGL_BUFFER_VIEW_ATTACH_INFO *info = &update->pBufferViews[i];
Chia-I Wuf8385062015-01-04 16:27:24 +0800645 const struct intel_buf_view *view = intel_buf_view(info->view);
646 struct intel_desc_surface desc;
647
Chia-I Wuf8385062015-01-04 16:27:24 +0800648 desc.mem = view->buf->obj.mem;
649 desc.read_only = false;
650 desc.type = INTEL_DESC_SURFACE_BUF;
651 desc.u.buf = view;
Chia-I Wu7732cb22015-03-26 15:27:55 +0800652 intel_desc_region_update(set->region, &iter.begin, &iter.end,
653 &desc, NULL);
Chia-I Wuf8385062015-01-04 16:27:24 +0800654
Chia-I Wu7732cb22015-03-26 15:27:55 +0800655 if (!intel_desc_iter_advance(&iter))
Chia-I Wuf8385062015-01-04 16:27:24 +0800656 break;
657 }
658}
659
660void intel_desc_set_update_as_copy(struct intel_desc_set *set,
661 const XGL_UPDATE_AS_COPY *update)
662{
663 const struct intel_desc_set *src_set =
664 intel_desc_set(update->descriptorSet);
Chia-I Wu7732cb22015-03-26 15:27:55 +0800665 struct intel_desc_iter iter, src_iter;
666 struct intel_desc_offset begin, src_begin;
Chia-I Wuf8385062015-01-04 16:27:24 +0800667 uint32_t i;
668
669 /* disallow combined sampler textures */
670 if (update->descriptorType == XGL_DESCRIPTOR_TYPE_SAMPLER_TEXTURE)
671 return;
672
Chia-I Wu7732cb22015-03-26 15:27:55 +0800673 if (!desc_iter_init_for_update(&iter, set, update->descriptorType,
674 update->binding, update->arrayElement) ||
675 !desc_iter_init_for_update(&src_iter, src_set, update->descriptorType,
676 update->binding, update->arrayElement))
Chia-I Wuf8385062015-01-04 16:27:24 +0800677 return;
678
Chia-I Wu7732cb22015-03-26 15:27:55 +0800679 /* save the begin offsets */
680 begin = iter.begin;
681 src_begin = src_iter.begin;
Chia-I Wuf8385062015-01-04 16:27:24 +0800682
Chia-I Wu7732cb22015-03-26 15:27:55 +0800683 /* advance to the end */
Chia-I Wuf8385062015-01-04 16:27:24 +0800684 for (i = 0; i < update->count; i++) {
Chia-I Wu7732cb22015-03-26 15:27:55 +0800685 if (!intel_desc_iter_advance(&iter) ||
686 !intel_desc_iter_advance(&src_iter)) {
687 /* out of bound */
688 return;
689 }
Chia-I Wuf8385062015-01-04 16:27:24 +0800690 }
Chia-I Wuf8385062015-01-04 16:27:24 +0800691
Chia-I Wu7732cb22015-03-26 15:27:55 +0800692 intel_desc_region_copy(set->region, &begin, &iter.end, &src_begin);
Chia-I Wuf8385062015-01-04 16:27:24 +0800693}
694
695static void desc_layout_destroy(struct intel_obj *obj)
696{
697 struct intel_desc_layout *layout = intel_desc_layout_from_obj(obj);
698
699 intel_desc_layout_destroy(layout);
700}
701
Chia-I Wufc9d9132015-03-26 15:04:41 +0800702static XGL_RESULT desc_layout_init_bindings(struct intel_desc_layout *layout,
703 const struct intel_desc_region *region,
704 const XGL_DESCRIPTOR_SET_LAYOUT_CREATE_INFO *info)
Chia-I Wuf8385062015-01-04 16:27:24 +0800705{
706 struct intel_desc_offset offset;
Chia-I Wu7732cb22015-03-26 15:27:55 +0800707 uint32_t i;
Chia-I Wuf8385062015-01-04 16:27:24 +0800708 XGL_RESULT ret;
709
Chia-I Wu7732cb22015-03-26 15:27:55 +0800710 intel_desc_offset_set(&offset, 0, 0);
Chia-I Wuf8385062015-01-04 16:27:24 +0800711
Chia-I Wufc9d9132015-03-26 15:04:41 +0800712 /* allocate bindings */
713 layout->bindings = intel_alloc(layout, sizeof(layout->bindings[0]) *
714 info->count, 0, XGL_SYSTEM_ALLOC_INTERNAL);
715 if (!layout->bindings)
716 return XGL_ERROR_OUT_OF_MEMORY;
717
718 memset(layout->bindings, 0, sizeof(layout->bindings[0]) * info->count);
719 layout->binding_count = info->count;
720
721 /* initialize bindings */
722 for (i = 0; i < info->count; i++) {
723 const XGL_DESCRIPTOR_SET_LAYOUT_BINDING *lb = &info->pBinding[i];
724 struct intel_desc_layout_binding *binding = &layout->bindings[i];
Chia-I Wuf8385062015-01-04 16:27:24 +0800725 struct intel_desc_offset size;
726
Chia-I Wufc9d9132015-03-26 15:04:41 +0800727 switch (lb->descriptorType) {
728 case XGL_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC:
729 case XGL_DESCRIPTOR_TYPE_SHADER_STORAGE_BUFFER_DYNAMIC:
Chia-I Wufc9d9132015-03-26 15:04:41 +0800730 layout->dynamic_desc_count += lb->count;
731 break;
732 default:
733 break;
734 }
735
Chia-I Wu7732cb22015-03-26 15:27:55 +0800736 /* lb->stageFlags does not gain us anything */
737 binding->type = lb->descriptorType;
738 binding->array_size = lb->count;
739 binding->offset = offset;
740
Chia-I Wufc9d9132015-03-26 15:04:41 +0800741 ret = desc_region_get_desc_size(region,
742 lb->descriptorType, &size);
Chia-I Wuf8385062015-01-04 16:27:24 +0800743 if (ret != XGL_SUCCESS)
744 return ret;
745
Chia-I Wu310eece2015-03-27 12:56:09 +0800746 binding->increment = size;
747
748 /* copy immutable samplers */
749 if (lb->pImmutableSamplers) {
750 bool shared = true;
751 uint32_t j;
752
753 for (j = 1; j < lb->count; j++) {
754 if (lb->pImmutableSamplers[j] != lb->pImmutableSamplers[0]) {
755 shared = false;
756 break;
757 }
758 }
759
760 if (shared) {
761 binding->shared_immutable_sampler =
762 intel_sampler((XGL_SAMPLER) lb->pImmutableSamplers[0]);
763 /* set sampler offset increment to 0 */
764 intel_desc_offset_set(&binding->increment,
765 binding->increment.surface, 0);
766 } else {
767 binding->immutable_samplers = intel_alloc(layout,
768 sizeof(binding->immutable_samplers[0]) * lb->count,
769 0, XGL_SYSTEM_ALLOC_INTERNAL);
770 if (!binding->immutable_samplers)
771 return XGL_ERROR_OUT_OF_MEMORY;
772
773 for (j = 0; j < lb->count; j++) {
774 binding->immutable_samplers[j] =
775 intel_sampler((XGL_SAMPLER) lb->pImmutableSamplers[j]);
776 }
777 }
Chia-I Wuf8385062015-01-04 16:27:24 +0800778 }
779
Chia-I Wu7732cb22015-03-26 15:27:55 +0800780 /* increment offset */
Chia-I Wufc9d9132015-03-26 15:04:41 +0800781 intel_desc_offset_mad(&size, &binding->increment, &size,
782 lb->count - 1);
Chia-I Wuf8385062015-01-04 16:27:24 +0800783 intel_desc_offset_add(&offset, &offset, &size);
Chia-I Wuf8385062015-01-04 16:27:24 +0800784 }
785
Chia-I Wu8d24b3b2015-03-26 13:14:16 +0800786 layout->region_size = offset;
Chia-I Wuf8385062015-01-04 16:27:24 +0800787
788 return XGL_SUCCESS;
789}
790
Chia-I Wuf8385062015-01-04 16:27:24 +0800791XGL_RESULT intel_desc_layout_create(struct intel_dev *dev,
Chia-I Wuf8385062015-01-04 16:27:24 +0800792 const XGL_DESCRIPTOR_SET_LAYOUT_CREATE_INFO *info,
793 struct intel_desc_layout **layout_ret)
794{
795 struct intel_desc_layout *layout;
796 XGL_RESULT ret;
797
Chia-I Wu545c2e12015-02-22 13:19:54 +0800798 layout = (struct intel_desc_layout *) intel_base_create(&dev->base.handle,
799 sizeof(*layout), dev->base.dbg,
800 XGL_DBG_OBJECT_DESCRIPTOR_SET_LAYOUT, info, 0);
Chia-I Wuf8385062015-01-04 16:27:24 +0800801 if (!layout)
802 return XGL_ERROR_OUT_OF_MEMORY;
803
Chia-I Wu7732cb22015-03-26 15:27:55 +0800804 ret = desc_layout_init_bindings(layout, dev->desc_region, info);
Chia-I Wuf8385062015-01-04 16:27:24 +0800805 if (ret != XGL_SUCCESS) {
806 intel_desc_layout_destroy(layout);
807 return ret;
808 }
809
810 layout->obj.destroy = desc_layout_destroy;
811
812 *layout_ret = layout;
813
814 return XGL_SUCCESS;
815}
816
817void intel_desc_layout_destroy(struct intel_desc_layout *layout)
818{
Chia-I Wu310eece2015-03-27 12:56:09 +0800819 uint32_t i;
820
821 for (i = 0; i < layout->binding_count; i++) {
822 struct intel_desc_layout_binding *binding = &layout->bindings[i];
823
824 if (binding->immutable_samplers)
825 intel_free(layout, binding->immutable_samplers);
826 }
Chia-I Wufc9d9132015-03-26 15:04:41 +0800827 intel_free(layout, layout->bindings);
Chia-I Wuf8385062015-01-04 16:27:24 +0800828 intel_base_destroy(&layout->obj.base);
829}
830
Chia-I Wu7732cb22015-03-26 15:27:55 +0800831static void desc_layout_chain_destroy(struct intel_obj *obj)
Chia-I Wuf8385062015-01-04 16:27:24 +0800832{
Chia-I Wu7732cb22015-03-26 15:27:55 +0800833 struct intel_desc_layout_chain *chain =
834 intel_desc_layout_chain_from_obj(obj);
Chia-I Wuf8385062015-01-04 16:27:24 +0800835
Chia-I Wu7732cb22015-03-26 15:27:55 +0800836 intel_desc_layout_chain_destroy(chain);
Chia-I Wuf8385062015-01-04 16:27:24 +0800837}
838
Chia-I Wu7732cb22015-03-26 15:27:55 +0800839XGL_RESULT intel_desc_layout_chain_create(struct intel_dev *dev,
840 const XGL_DESCRIPTOR_SET_LAYOUT *layouts,
841 uint32_t count,
842 struct intel_desc_layout_chain **chain_ret)
Chia-I Wuf8385062015-01-04 16:27:24 +0800843{
Chia-I Wu7732cb22015-03-26 15:27:55 +0800844 struct intel_desc_layout_chain *chain;
845 uint32_t i;
846
847 chain = (struct intel_desc_layout_chain *)
848 intel_base_create(&dev->base.handle, sizeof(*chain), dev->base.dbg,
849 XGL_DBG_OBJECT_DESCRIPTOR_SET_LAYOUT_CHAIN, NULL, 0);
850 if (!chain)
851 return XGL_ERROR_OUT_OF_MEMORY;
852
853 chain->layouts = intel_alloc(chain, sizeof(chain->layouts[0]) * count,
854 0, XGL_SYSTEM_ALLOC_INTERNAL);
855 if (!chain) {
856 intel_desc_layout_chain_destroy(chain);
857 return XGL_ERROR_OUT_OF_MEMORY;
Chia-I Wuf8385062015-01-04 16:27:24 +0800858 }
859
Chia-I Wu862c5572015-03-28 15:23:55 +0800860 chain->dynamic_desc_indices = intel_alloc(chain,
861 sizeof(chain->dynamic_desc_indices[0]) * count,
862 0, XGL_SYSTEM_ALLOC_INTERNAL);
863 if (!chain->dynamic_desc_indices) {
864 intel_desc_layout_chain_destroy(chain);
865 return XGL_ERROR_OUT_OF_MEMORY;
866 }
867
868 for (i = 0; i < count; i++) {
Chia-I Wu7732cb22015-03-26 15:27:55 +0800869 chain->layouts[i] = intel_desc_layout(layouts[i]);
Chia-I Wu862c5572015-03-28 15:23:55 +0800870 chain->dynamic_desc_indices[i] = chain->total_dynamic_desc_count;
871
872 chain->total_dynamic_desc_count +=
873 chain->layouts[i]->dynamic_desc_count;
874 }
Chia-I Wuf8385062015-01-04 16:27:24 +0800875
Chia-I Wu7732cb22015-03-26 15:27:55 +0800876 chain->layout_count = count;
Chia-I Wuf8385062015-01-04 16:27:24 +0800877
Chia-I Wu7732cb22015-03-26 15:27:55 +0800878 chain->obj.destroy = desc_layout_chain_destroy;
879
880 *chain_ret = chain;
881
882 return XGL_SUCCESS;
Chia-I Wuf8385062015-01-04 16:27:24 +0800883}
884
Chia-I Wu7732cb22015-03-26 15:27:55 +0800885void intel_desc_layout_chain_destroy(struct intel_desc_layout_chain *chain)
Chia-I Wuf8385062015-01-04 16:27:24 +0800886{
Chia-I Wu862c5572015-03-28 15:23:55 +0800887 if (chain->dynamic_desc_indices)
888 intel_free(chain, chain->dynamic_desc_indices);
Chia-I Wu7732cb22015-03-26 15:27:55 +0800889 if (chain->layouts)
890 intel_free(chain, chain->layouts);
891 intel_base_destroy(&chain->obj.base);
Chia-I Wuf8385062015-01-04 16:27:24 +0800892}
893
Chia-I Wude26bdf2015-02-18 15:47:12 -0700894ICD_EXPORT XGL_RESULT XGLAPI xglCreateDescriptorSetLayout(
Chia-I Wuf8385062015-01-04 16:27:24 +0800895 XGL_DEVICE device,
Chia-I Wufc9d9132015-03-26 15:04:41 +0800896 const XGL_DESCRIPTOR_SET_LAYOUT_CREATE_INFO* pCreateInfo,
Chia-I Wuf8385062015-01-04 16:27:24 +0800897 XGL_DESCRIPTOR_SET_LAYOUT* pSetLayout)
898{
899 struct intel_dev *dev = intel_dev(device);
Chia-I Wuf8385062015-01-04 16:27:24 +0800900
Chia-I Wu7732cb22015-03-26 15:27:55 +0800901 return intel_desc_layout_create(dev, pCreateInfo,
Chia-I Wuf8385062015-01-04 16:27:24 +0800902 (struct intel_desc_layout **) pSetLayout);
903}
904
Chia-I Wu7732cb22015-03-26 15:27:55 +0800905ICD_EXPORT XGL_RESULT XGLAPI xglCreateDescriptorSetLayoutChain(
906 XGL_DEVICE device,
907 uint32_t setLayoutArrayCount,
908 const XGL_DESCRIPTOR_SET_LAYOUT* pSetLayoutArray,
909 XGL_DESCRIPTOR_SET_LAYOUT_CHAIN* pLayoutChain)
910{
911 struct intel_dev *dev = intel_dev(device);
912
913 return intel_desc_layout_chain_create(dev,
914 pSetLayoutArray, setLayoutArrayCount,
915 (struct intel_desc_layout_chain **) pLayoutChain);
916}
917
Chia-I Wu8d24b3b2015-03-26 13:14:16 +0800918ICD_EXPORT XGL_RESULT XGLAPI xglBeginDescriptorPoolUpdate(
Chia-I Wuf8385062015-01-04 16:27:24 +0800919 XGL_DEVICE device,
920 XGL_DESCRIPTOR_UPDATE_MODE updateMode)
921{
922 struct intel_dev *dev = intel_dev(device);
Chia-I Wu8d24b3b2015-03-26 13:14:16 +0800923 struct intel_desc_region *region = dev->desc_region;
Chia-I Wuf8385062015-01-04 16:27:24 +0800924
Chia-I Wu8d24b3b2015-03-26 13:14:16 +0800925 return intel_desc_region_begin_update(region, updateMode);
Chia-I Wuf8385062015-01-04 16:27:24 +0800926}
927
Chia-I Wu8d24b3b2015-03-26 13:14:16 +0800928ICD_EXPORT XGL_RESULT XGLAPI xglEndDescriptorPoolUpdate(
Chia-I Wuf8385062015-01-04 16:27:24 +0800929 XGL_DEVICE device,
930 XGL_CMD_BUFFER cmd_)
931{
932 struct intel_dev *dev = intel_dev(device);
Chia-I Wu8d24b3b2015-03-26 13:14:16 +0800933 struct intel_desc_region *region = dev->desc_region;
Chia-I Wuf8385062015-01-04 16:27:24 +0800934 struct intel_cmd *cmd = intel_cmd(cmd_);
935
Chia-I Wu8d24b3b2015-03-26 13:14:16 +0800936 return intel_desc_region_end_update(region, cmd);
Chia-I Wuf8385062015-01-04 16:27:24 +0800937}
938
Chia-I Wu8d24b3b2015-03-26 13:14:16 +0800939ICD_EXPORT XGL_RESULT XGLAPI xglCreateDescriptorPool(
Chia-I Wuf8385062015-01-04 16:27:24 +0800940 XGL_DEVICE device,
Chia-I Wu8d24b3b2015-03-26 13:14:16 +0800941 XGL_DESCRIPTOR_POOL_USAGE poolUsage,
Mark Lobodzinskie2d07a52015-01-29 08:55:56 -0600942 uint32_t maxSets,
Chia-I Wu8d24b3b2015-03-26 13:14:16 +0800943 const XGL_DESCRIPTOR_POOL_CREATE_INFO* pCreateInfo,
944 XGL_DESCRIPTOR_POOL* pDescriptorPool)
Chia-I Wuf8385062015-01-04 16:27:24 +0800945{
946 struct intel_dev *dev = intel_dev(device);
947
Chia-I Wu8d24b3b2015-03-26 13:14:16 +0800948 return intel_desc_pool_create(dev, poolUsage, maxSets, pCreateInfo,
949 (struct intel_desc_pool **) pDescriptorPool);
Chia-I Wuf8385062015-01-04 16:27:24 +0800950}
951
Chia-I Wudee95612015-03-26 15:23:52 +0800952ICD_EXPORT XGL_RESULT XGLAPI xglResetDescriptorPool(
Chia-I Wu8d24b3b2015-03-26 13:14:16 +0800953 XGL_DESCRIPTOR_POOL descriptorPool)
Chia-I Wuf8385062015-01-04 16:27:24 +0800954{
Chia-I Wu8d24b3b2015-03-26 13:14:16 +0800955 struct intel_desc_pool *pool = intel_desc_pool(descriptorPool);
Chia-I Wuf8385062015-01-04 16:27:24 +0800956
Chia-I Wudee95612015-03-26 15:23:52 +0800957 intel_desc_pool_reset(pool);
Chia-I Wuf8385062015-01-04 16:27:24 +0800958
959 return XGL_SUCCESS;
960}
961
Chia-I Wude26bdf2015-02-18 15:47:12 -0700962ICD_EXPORT XGL_RESULT XGLAPI xglAllocDescriptorSets(
Chia-I Wu8d24b3b2015-03-26 13:14:16 +0800963 XGL_DESCRIPTOR_POOL descriptorPool,
Chia-I Wuf8385062015-01-04 16:27:24 +0800964 XGL_DESCRIPTOR_SET_USAGE setUsage,
Mark Lobodzinskie2d07a52015-01-29 08:55:56 -0600965 uint32_t count,
Chia-I Wuf8385062015-01-04 16:27:24 +0800966 const XGL_DESCRIPTOR_SET_LAYOUT* pSetLayouts,
967 XGL_DESCRIPTOR_SET* pDescriptorSets,
Mark Lobodzinskie2d07a52015-01-29 08:55:56 -0600968 uint32_t* pCount)
Chia-I Wuf8385062015-01-04 16:27:24 +0800969{
Chia-I Wu8d24b3b2015-03-26 13:14:16 +0800970 struct intel_desc_pool *pool = intel_desc_pool(descriptorPool);
971 struct intel_dev *dev = pool->dev;
Chia-I Wuf8385062015-01-04 16:27:24 +0800972 XGL_RESULT ret = XGL_SUCCESS;
973 uint32_t i;
974
975 for (i = 0; i < count; i++) {
976 const struct intel_desc_layout *layout =
977 intel_desc_layout((XGL_DESCRIPTOR_SET_LAYOUT) pSetLayouts[i]);
978
Chia-I Wu8d24b3b2015-03-26 13:14:16 +0800979 ret = intel_desc_set_create(dev, pool, setUsage, layout,
Chia-I Wuf8385062015-01-04 16:27:24 +0800980 (struct intel_desc_set **) &pDescriptorSets[i]);
981 if (ret != XGL_SUCCESS)
982 break;
983 }
984
985 if (pCount)
986 *pCount = i;
987
988 return ret;
989}
990
Chia-I Wude26bdf2015-02-18 15:47:12 -0700991ICD_EXPORT void XGLAPI xglClearDescriptorSets(
Chia-I Wu8d24b3b2015-03-26 13:14:16 +0800992 XGL_DESCRIPTOR_POOL descriptorPool,
Mark Lobodzinskie2d07a52015-01-29 08:55:56 -0600993 uint32_t count,
Chia-I Wuf8385062015-01-04 16:27:24 +0800994 const XGL_DESCRIPTOR_SET* pDescriptorSets)
995{
996 uint32_t i;
997
998 for (i = 0; i < count; i++) {
999 struct intel_desc_set *set =
1000 intel_desc_set((XGL_DESCRIPTOR_SET) pDescriptorSets[i]);
1001
Chia-I Wu8d24b3b2015-03-26 13:14:16 +08001002 intel_desc_region_clear(set->region, &set->region_begin, &set->region_end);
Chia-I Wuf8385062015-01-04 16:27:24 +08001003 }
1004}
1005
Chia-I Wude26bdf2015-02-18 15:47:12 -07001006ICD_EXPORT void XGLAPI xglUpdateDescriptors(
Chia-I Wuf8385062015-01-04 16:27:24 +08001007 XGL_DESCRIPTOR_SET descriptorSet,
Chia-I Wu7732cb22015-03-26 15:27:55 +08001008 uint32_t updateCount,
1009 const void** ppUpdateArray)
Chia-I Wuf8385062015-01-04 16:27:24 +08001010{
1011 struct intel_desc_set *set = intel_desc_set(descriptorSet);
Chia-I Wu7732cb22015-03-26 15:27:55 +08001012 uint32_t i;
Chia-I Wuf8385062015-01-04 16:27:24 +08001013
Chia-I Wu7732cb22015-03-26 15:27:55 +08001014 for (i = 0; i < updateCount; i++) {
1015 const union {
1016 struct {
1017 XGL_STRUCTURE_TYPE sType;
1018 const void* pNext;
1019 } common;
Chia-I Wuf8385062015-01-04 16:27:24 +08001020
Chia-I Wu7732cb22015-03-26 15:27:55 +08001021 XGL_UPDATE_SAMPLERS samplers;
1022 XGL_UPDATE_SAMPLER_TEXTURES sampler_textures;
1023 XGL_UPDATE_IMAGES images;
1024 XGL_UPDATE_BUFFERS buffers;
1025 XGL_UPDATE_AS_COPY as_copy;
1026 } *u = ppUpdateArray[i];
1027
Chia-I Wuf8385062015-01-04 16:27:24 +08001028 switch (u->common.sType) {
1029 case XGL_STRUCTURE_TYPE_UPDATE_SAMPLERS:
1030 intel_desc_set_update_samplers(set, &u->samplers);
1031 break;
1032 case XGL_STRUCTURE_TYPE_UPDATE_SAMPLER_TEXTURES:
1033 intel_desc_set_update_sampler_textures(set, &u->sampler_textures);
1034 break;
1035 case XGL_STRUCTURE_TYPE_UPDATE_IMAGES:
1036 intel_desc_set_update_images(set, &u->images);
1037 break;
1038 case XGL_STRUCTURE_TYPE_UPDATE_BUFFERS:
1039 intel_desc_set_update_buffers(set, &u->buffers);
1040 break;
1041 case XGL_STRUCTURE_TYPE_UPDATE_AS_COPY:
1042 intel_desc_set_update_as_copy(set, &u->as_copy);
1043 break;
1044 default:
1045 assert(!"unknown descriptor update");
1046 break;
1047 }
Chia-I Wuf8385062015-01-04 16:27:24 +08001048 }
1049}