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Chia-I Wue09b5362014-08-07 09:25:14 +08001/*
2 * XGL
3 *
4 * Copyright (C) 2014 LunarG, Inc.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included
14 * in all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE.
Chia-I Wu44e42362014-09-02 08:32:09 +080023 *
24 * Authors:
25 * Chia-I Wu <olv@lunarg.com>
Chia-I Wue09b5362014-08-07 09:25:14 +080026 */
27
28#ifndef QUEUE_H
29#define QUEUE_H
30
Chia-I Wuc5438c22014-08-19 14:03:06 +080031#include "kmd/winsys.h"
Chia-I Wue09b5362014-08-07 09:25:14 +080032#include "intel.h"
Chia-I Wucdcff732014-08-19 14:44:15 +080033#include "gpu.h"
Chia-I Wue09b5362014-08-07 09:25:14 +080034#include "obj.h"
35
Chia-I Wuec841722014-08-25 22:36:01 +080036#define INTEL_QUEUE_ATOMIC_COUNTER_COUNT 1024
37
Chia-I Wue09b5362014-08-07 09:25:14 +080038struct intel_dev;
39
40struct intel_queue {
41 struct intel_base base;
42
43 struct intel_dev *dev;
Chia-I Wuc5438c22014-08-19 14:03:06 +080044 enum intel_ring_type ring;
Chia-I Wu34f45182014-08-19 14:02:59 +080045
Chia-I Wu63883292014-08-25 13:50:26 +080046 struct intel_bo *atomic_bo;
47 struct intel_bo *select_graphics_bo;
48 struct intel_bo *select_compute_bo;
Chia-I Wu3ad3c542014-08-25 11:09:17 +080049
Chia-I Wu046a7a92015-02-17 14:29:01 -070050 struct intel_bo *seqno_bo;
Chia-I Wu63883292014-08-25 13:50:26 +080051 int last_pipeline_select;
Chia-I Wue09b5362014-08-07 09:25:14 +080052};
53
54static inline struct intel_queue *intel_queue(XGL_QUEUE queue)
55{
56 return (struct intel_queue *) queue;
57}
58
Chia-I Wu9ae59c12014-08-07 10:08:49 +080059XGL_RESULT intel_queue_create(struct intel_dev *dev,
Chia-I Wucdcff732014-08-19 14:44:15 +080060 enum intel_gpu_engine_type engine,
Chia-I Wu9ae59c12014-08-07 10:08:49 +080061 struct intel_queue **queue_ret);
Chia-I Wue09b5362014-08-07 09:25:14 +080062void intel_queue_destroy(struct intel_queue *queue);
63
64XGL_RESULT intel_queue_wait(struct intel_queue *queue, int64_t timeout);
65
Chia-I Wue09b5362014-08-07 09:25:14 +080066#endif /* QUEUE_H */