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Chia-I Wue09b5362014-08-07 09:25:14 +08001/*
2 * XGL
3 *
4 * Copyright (C) 2014 LunarG, Inc.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included
14 * in all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE.
23 */
24
25#ifndef QUEUE_H
26#define QUEUE_H
27
Chia-I Wuc5438c22014-08-19 14:03:06 +080028#include "kmd/winsys.h"
Chia-I Wue09b5362014-08-07 09:25:14 +080029#include "intel.h"
Chia-I Wucdcff732014-08-19 14:44:15 +080030#include "gpu.h"
Chia-I Wue09b5362014-08-07 09:25:14 +080031#include "obj.h"
32
Chia-I Wuec841722014-08-25 22:36:01 +080033#define INTEL_QUEUE_ATOMIC_COUNTER_COUNT 1024
34
Chia-I Wu34f45182014-08-19 14:02:59 +080035struct intel_cmd;
Chia-I Wue09b5362014-08-07 09:25:14 +080036struct intel_dev;
37
38struct intel_queue {
39 struct intel_base base;
40
41 struct intel_dev *dev;
Chia-I Wuc5438c22014-08-19 14:03:06 +080042 enum intel_ring_type ring;
Chia-I Wu34f45182014-08-19 14:02:59 +080043
Chia-I Wu63883292014-08-25 13:50:26 +080044 struct intel_bo *atomic_bo;
45 struct intel_bo *select_graphics_bo;
46 struct intel_bo *select_compute_bo;
Chia-I Wu3ad3c542014-08-25 11:09:17 +080047
Chia-I Wu34f45182014-08-19 14:02:59 +080048 struct intel_cmd *last_submitted_cmd;
Chia-I Wu63883292014-08-25 13:50:26 +080049 int last_pipeline_select;
Chia-I Wue09b5362014-08-07 09:25:14 +080050};
51
52static inline struct intel_queue *intel_queue(XGL_QUEUE queue)
53{
54 return (struct intel_queue *) queue;
55}
56
Chia-I Wu9ae59c12014-08-07 10:08:49 +080057XGL_RESULT intel_queue_create(struct intel_dev *dev,
Chia-I Wucdcff732014-08-19 14:44:15 +080058 enum intel_gpu_engine_type engine,
Chia-I Wu9ae59c12014-08-07 10:08:49 +080059 struct intel_queue **queue_ret);
Chia-I Wue09b5362014-08-07 09:25:14 +080060void intel_queue_destroy(struct intel_queue *queue);
61
62XGL_RESULT intel_queue_wait(struct intel_queue *queue, int64_t timeout);
63
64XGL_RESULT XGLAPI intelQueueSetGlobalMemReferences(
65 XGL_QUEUE queue,
66 XGL_UINT memRefCount,
67 const XGL_MEMORY_REF* pMemRefs);
68
69XGL_RESULT XGLAPI intelQueueWaitIdle(
70 XGL_QUEUE queue);
71
Chia-I Wu251e7d92014-08-19 13:35:42 +080072XGL_RESULT XGLAPI intelQueueSubmit(
73 XGL_QUEUE queue,
74 XGL_UINT cmdBufferCount,
75 const XGL_CMD_BUFFER* pCmdBuffers,
76 XGL_UINT memRefCount,
77 const XGL_MEMORY_REF* pMemRefs,
78 XGL_FENCE fence);
79
80XGL_RESULT XGLAPI intelOpenSharedQueueSemaphore(
81 XGL_DEVICE device,
82 const XGL_QUEUE_SEMAPHORE_OPEN_INFO* pOpenInfo,
83 XGL_QUEUE_SEMAPHORE* pSemaphore);
84
85XGL_RESULT XGLAPI intelCreateQueueSemaphore(
86 XGL_DEVICE device,
87 const XGL_QUEUE_SEMAPHORE_CREATE_INFO* pCreateInfo,
88 XGL_QUEUE_SEMAPHORE* pSemaphore);
89
90XGL_RESULT XGLAPI intelSignalQueueSemaphore(
91 XGL_QUEUE queue,
92 XGL_QUEUE_SEMAPHORE semaphore);
93
94XGL_RESULT XGLAPI intelWaitQueueSemaphore(
95 XGL_QUEUE queue,
96 XGL_QUEUE_SEMAPHORE semaphore);
97
Chia-I Wue09b5362014-08-07 09:25:14 +080098#endif /* QUEUE_H */