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Chia-I Wu00a23b22014-08-20 15:28:08 +08001/*
2 * XGL
3 *
4 * Copyright (C) 2014 LunarG, Inc.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included
14 * in all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE.
23 */
24
25#ifndef CMD_PRIV_H
26#define CMD_PRIV_H
27
Chia-I Wue24c3292014-08-21 14:05:23 +080028#include "genhw/genhw.h"
Chia-I Wu32710d72014-08-20 16:05:22 +080029#include "dev.h"
30#include "gpu.h"
Chia-I Wu00a23b22014-08-20 15:28:08 +080031#include "cmd.h"
32
Chia-I Wu32710d72014-08-20 16:05:22 +080033#define CMD_ASSERT(cmd, min_gen, max_gen) \
34 INTEL_GPU_ASSERT((cmd)->dev->gpu, (min_gen), (max_gen))
35
Chia-I Wu958d1b72014-08-21 11:28:11 +080036struct intel_cmd_reloc {
Chia-I Wue24c3292014-08-21 14:05:23 +080037 struct intel_cmd_writer *writer;
Chia-I Wu958d1b72014-08-21 11:28:11 +080038 XGL_UINT pos;
39
40 uint32_t val;
Chia-I Wu9ee38722014-08-25 12:11:36 +080041 struct intel_bo *bo;
Chia-I Wu958d1b72014-08-21 11:28:11 +080042
43 /*
44 * With application state tracking promised by XGL, we should be able to
45 * set
46 *
47 * I915_EXEC_NO_RELOC
48 * I915_EXEC_HANDLE_LUT
49 * I915_EXEC_IS_PINNED
50 *
51 * once we figure them out.
52 */
53 uint16_t read_domains;
54 uint16_t write_domain;
55};
56
Chia-I Wu9f039862014-08-20 15:39:56 +080057static inline int cmd_gen(const struct intel_cmd *cmd)
58{
59 return intel_gpu_gen(cmd->dev->gpu);
60}
61
Chia-I Wucdff0592014-08-22 09:27:36 +080062static inline void cmd_reserve_reloc(struct intel_cmd *cmd,
63 XGL_UINT reloc_len)
64{
65 /* fail silently */
66 if (cmd->reloc_used + reloc_len > cmd->reloc_count) {
67 cmd->reloc_used = 0;
68 cmd->result = XGL_ERROR_TOO_MANY_MEMORY_REFERENCES;
69 }
70 assert(cmd->reloc_used + reloc_len <= cmd->reloc_count);
71}
72
Chia-I Wue24c3292014-08-21 14:05:23 +080073void cmd_writer_grow(struct intel_cmd *cmd,
74 struct intel_cmd_writer *writer);
Chia-I Wu00a23b22014-08-20 15:28:08 +080075
Chia-I Wu32710d72014-08-20 16:05:22 +080076/**
Chia-I Wubda55fd2014-08-25 12:46:10 +080077 * Add a reloc at \p pos. No error checking.
Chia-I Wucdff0592014-08-22 09:27:36 +080078 */
79static inline void cmd_writer_add_reloc(struct intel_cmd *cmd,
80 struct intel_cmd_writer *writer,
Chia-I Wubda55fd2014-08-25 12:46:10 +080081 XGL_UINT pos, uint32_t val,
Chia-I Wu9ee38722014-08-25 12:11:36 +080082 struct intel_bo *bo,
Chia-I Wucdff0592014-08-22 09:27:36 +080083 uint16_t read_domains,
84 uint16_t write_domain)
85{
86 struct intel_cmd_reloc *reloc = &cmd->relocs[cmd->reloc_used];
87
88 assert(cmd->reloc_used < cmd->reloc_count);
89
90 reloc->writer = writer;
Chia-I Wubda55fd2014-08-25 12:46:10 +080091 reloc->pos = pos;
Chia-I Wucdff0592014-08-22 09:27:36 +080092 reloc->val = val;
Chia-I Wu9ee38722014-08-25 12:11:36 +080093 reloc->bo = bo;
Chia-I Wucdff0592014-08-22 09:27:36 +080094 reloc->read_domains = read_domains;
95 reloc->write_domain = write_domain;
96
97 cmd->reloc_used++;
98}
99
100/**
101 * Reserve \p len DWords in the batch buffer for building a hardware command.
Chia-I Wue24c3292014-08-21 14:05:23 +0800102 */
103static inline void cmd_batch_reserve(struct intel_cmd *cmd, XGL_UINT len)
104{
105 struct intel_cmd_writer *writer = &cmd->batch;
106
107 if (writer->used + len > writer->size)
108 cmd_writer_grow(cmd, writer);
109 assert(writer->used + len <= writer->size);
110}
111
112/**
Chia-I Wucdff0592014-08-22 09:27:36 +0800113 * Reserve \p len DWords in the batch buffer and \p reloc_len relocs for
114 * building a hardware command.
115 */
116static inline void cmd_batch_reserve_reloc(struct intel_cmd *cmd,
117 XGL_UINT len, XGL_UINT reloc_len)
118{
119 cmd_reserve_reloc(cmd, reloc_len);
120 cmd_batch_reserve(cmd, len);
121}
122
123/**
124 * Add a DWord to the hardware command being built. No error checking.
Chia-I Wue24c3292014-08-21 14:05:23 +0800125 */
126static inline void cmd_batch_write(struct intel_cmd *cmd, uint32_t val)
127{
128 struct intel_cmd_writer *writer = &cmd->batch;
129
130 assert(writer->used < writer->size);
131 ((uint32_t *) writer->ptr_opaque)[writer->used++] = val;
132}
133
134/**
Chia-I Wucdff0592014-08-22 09:27:36 +0800135 * Add \p len DWords to the hardware command being built. No error checking.
136 */
137static inline void cmd_batch_write_n(struct intel_cmd *cmd,
138 const uint32_t *vals, XGL_UINT len)
139{
140 struct intel_cmd_writer *writer = &cmd->batch;
141
142 assert(writer->used + len <= writer->size);
143
144 memcpy((uint32_t *) writer->ptr_opaque + writer->used,
145 vals, sizeof(uint32_t) * len);
146 writer->used += len;
147}
148
149/**
150 * Add a reloc to the hardware command being built. No error checking.
Chia-I Wue24c3292014-08-21 14:05:23 +0800151 */
152static inline void cmd_batch_reloc(struct intel_cmd *cmd,
Chia-I Wu9ee38722014-08-25 12:11:36 +0800153 uint32_t val, struct intel_bo *bo,
Chia-I Wue24c3292014-08-21 14:05:23 +0800154 uint16_t read_domains,
155 uint16_t write_domain)
156{
157 struct intel_cmd_writer *writer = &cmd->batch;
158
Chia-I Wubda55fd2014-08-25 12:46:10 +0800159 cmd_writer_add_reloc(cmd, writer, writer->used, val,
Chia-I Wu9ee38722014-08-25 12:11:36 +0800160 bo, read_domains, write_domain);
Chia-I Wu5e25c272014-08-21 20:19:12 +0800161
Chia-I Wue24c3292014-08-21 14:05:23 +0800162 writer->used++;
163}
164
165/**
166 * End the batch buffer.
167 */
168static inline void cmd_batch_end(struct intel_cmd *cmd)
169{
170 if (cmd->batch.used & 1) {
171 cmd_batch_reserve(cmd, 1);
172 cmd_batch_write(cmd, GEN_MI_CMD(MI_BATCH_BUFFER_END));
173 } else {
174 cmd_batch_reserve(cmd, 2);
175 cmd_batch_write(cmd, GEN_MI_CMD(MI_BATCH_BUFFER_END));
176 cmd_batch_write(cmd, GEN_MI_CMD(MI_NOOP));
177 }
Chia-I Wu343b1372014-08-20 16:39:20 +0800178}
179
Chia-I Wu24565ee2014-08-21 20:24:31 +0800180/**
Chia-I Wucdff0592014-08-22 09:27:36 +0800181 * Reserve \p len DWords in the state buffer for building a hardware state.
182 * The current writer position is aligned to \p alignment first. Both the
183 * pointer to the reserved region and the aligned position are returned.
184 *
185 * Note that the returned pointer is only valid until the next reserve call.
Chia-I Wu24565ee2014-08-21 20:24:31 +0800186 */
187static inline uint32_t *cmd_state_reserve(struct intel_cmd *cmd, XGL_UINT len,
188 XGL_UINT alignment, XGL_UINT *pos)
189{
190 struct intel_cmd_writer *writer = &cmd->state;
191 XGL_UINT aligned;
192
193 assert(alignment && u_is_pow2(alignment));
194 aligned = u_align(writer->used, alignment);
195
196 if (aligned + len > writer->size)
197 cmd_writer_grow(cmd, writer);
198 assert(aligned + len <= writer->size);
199
200 writer->used = aligned;
201 *pos = aligned;
202
203 return &((uint32_t *) writer->ptr_opaque)[writer->used];
204}
205
206/**
Chia-I Wucdff0592014-08-22 09:27:36 +0800207 * Similar to \p cmd_state_reserve, except that \p reloc_len relocs are also
208 * reserved.
Chia-I Wu24565ee2014-08-21 20:24:31 +0800209 */
Chia-I Wucdff0592014-08-22 09:27:36 +0800210static inline uint32_t *cmd_state_reserve_reloc(struct intel_cmd *cmd,
211 XGL_UINT len,
212 XGL_UINT reloc_len,
213 XGL_UINT alignment,
214 XGL_UINT *pos)
Chia-I Wu24565ee2014-08-21 20:24:31 +0800215{
Chia-I Wucdff0592014-08-22 09:27:36 +0800216 cmd_reserve_reloc(cmd, reloc_len);
217 return cmd_state_reserve(cmd, len, alignment, pos);
Chia-I Wu24565ee2014-08-21 20:24:31 +0800218}
219
220/**
Chia-I Wubda55fd2014-08-25 12:46:10 +0800221 * Add a reloc at \p offset, relative to the current writer position. No
222 * error checking.
223 */
224static inline void cmd_state_reloc(struct intel_cmd *cmd,
225 XGL_INT offset, uint32_t val,
226 struct intel_bo *bo,
227 uint16_t read_domains,
228 uint16_t write_domain)
229{
230 struct intel_cmd_writer *writer = &cmd->state;
231
232 cmd_writer_add_reloc(cmd, writer, writer->used + offset, val,
233 bo, read_domains, write_domain);
234}
235
236/**
Chia-I Wucdff0592014-08-22 09:27:36 +0800237 * Advance the writer position of the state buffer. No error checking.
Chia-I Wu24565ee2014-08-21 20:24:31 +0800238 */
239static inline void cmd_state_advance(struct intel_cmd *cmd, XGL_UINT len)
240{
241 struct intel_cmd_writer *writer = &cmd->state;
242
243 assert(writer->used + len <= writer->size);
244 writer->used += len;
245}
246
247/**
Chia-I Wucdff0592014-08-22 09:27:36 +0800248 * A convenient function to copy a hardware state of \p len DWords into the
249 * state buffer. The position of the state is returned.
Chia-I Wu24565ee2014-08-21 20:24:31 +0800250 */
251static inline XGL_UINT cmd_state_copy(struct intel_cmd *cmd,
252 const uint32_t *vals, XGL_UINT len,
253 XGL_UINT alignment)
254{
255 uint32_t *dst;
256 XGL_UINT pos;
257
258 dst = cmd_state_reserve(cmd, len, alignment, &pos);
259 memcpy(dst, vals, sizeof(uint32_t) * len);
260 cmd_state_advance(cmd, len);
261
262 return pos;
263}
264
Chia-I Wu1cbc0052014-08-25 09:50:12 +0800265static inline XGL_UINT cmd_kernel_copy(struct intel_cmd *cmd,
266 const void *kernel, XGL_SIZE size)
267{
268 /*
269 * From the Sandy Bridge PRM, volume 4 part 2, page 112:
270 *
271 * "Due to prefetch of the instruction stream, the EUs may attempt to
272 * access up to 8 instructions (128 bytes) beyond the end of the
273 * kernel program - possibly into the next memory page. Although
274 * these instructions will not be executed, software must account for
275 * the prefetch in order to avoid invalid page access faults."
276 */
277 const XGL_UINT prefetch_len = 128 / sizeof(uint32_t);
278 /* kernels are aligned to 64-byte */
279 const XGL_UINT kernel_align = 64 / sizeof(uint32_t);
280 const XGL_UINT kernel_len = ((size + 3) & ~3) / sizeof(uint32_t);
281 struct intel_cmd_writer *writer = &cmd->kernel;
282 XGL_UINT kernel_pos;
283
284 kernel_pos = u_align(writer->used, kernel_align);
285 if (kernel_pos + kernel_len + prefetch_len > writer->size)
286 cmd_writer_grow(cmd, writer);
287 assert(kernel_pos + kernel_len + prefetch_len <= writer->size);
288
289 memcpy(&((uint32_t *) writer->ptr_opaque)[kernel_pos], kernel, size);
290 writer->used = kernel_pos + kernel_len;
291
292 return kernel_pos;
293}
294
Chia-I Wu00a23b22014-08-20 15:28:08 +0800295#endif /* CMD_PRIV_H */