Chia-I Wu | 4bc4701 | 2014-08-14 13:03:25 +0800 | [diff] [blame] | 1 | /* |
Courtney Goeltzenleuchter | 9cc421e | 2015-04-08 15:36:08 -0600 | [diff] [blame] | 2 | * Vulkan |
Chia-I Wu | 4bc4701 | 2014-08-14 13:03:25 +0800 | [diff] [blame] | 3 | * |
| 4 | * Copyright (C) 2014 LunarG, Inc. |
| 5 | * |
| 6 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 7 | * copy of this software and associated documentation files (the "Software"), |
| 8 | * to deal in the Software without restriction, including without limitation |
| 9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| 10 | * and/or sell copies of the Software, and to permit persons to whom the |
| 11 | * Software is furnished to do so, subject to the following conditions: |
| 12 | * |
| 13 | * The above copyright notice and this permission notice shall be included |
| 14 | * in all copies or substantial portions of the Software. |
| 15 | * |
| 16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
| 20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING |
| 21 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER |
| 22 | * DEALINGS IN THE SOFTWARE. |
| 23 | * |
| 24 | * Authors: |
Chia-I Wu | 44e4236 | 2014-09-02 08:32:09 +0800 | [diff] [blame] | 25 | * Chia-I Wu <olv@lunarg.com> |
Chia-I Wu | 4bc4701 | 2014-08-14 13:03:25 +0800 | [diff] [blame] | 26 | */ |
| 27 | |
Chia-I Wu | 8a8d8b6 | 2014-08-14 13:26:26 +0800 | [diff] [blame] | 28 | #ifndef LAYOUT_H |
| 29 | #define LAYOUT_H |
Chia-I Wu | 4bc4701 | 2014-08-14 13:03:25 +0800 | [diff] [blame] | 30 | |
Chia-I Wu | d1eb90c | 2015-03-07 06:01:45 +0800 | [diff] [blame] | 31 | #include "genhw/genhw.h" |
Chia-I Wu | 8a8d8b6 | 2014-08-14 13:26:26 +0800 | [diff] [blame] | 32 | #include "intel.h" |
Chia-I Wu | 4bc4701 | 2014-08-14 13:03:25 +0800 | [diff] [blame] | 33 | |
Chia-I Wu | 457d0a6 | 2014-08-18 13:02:26 +0800 | [diff] [blame] | 34 | #define INTEL_LAYOUT_MAX_LEVELS 16 |
| 35 | |
Chia-I Wu | cca7acf | 2014-08-27 10:37:43 +0800 | [diff] [blame] | 36 | struct intel_dev; |
| 37 | |
Chia-I Wu | 457d0a6 | 2014-08-18 13:02:26 +0800 | [diff] [blame] | 38 | enum intel_layout_walk_type { |
| 39 | /* |
| 40 | * Array layers of an LOD are packed together vertically. This maps to |
| 41 | * ARYSPC_LOD0 for non-mipmapped 2D textures, and is extended to support |
| 42 | * mipmapped stencil textures and HiZ on GEN6. |
| 43 | */ |
| 44 | INTEL_LAYOUT_WALK_LOD, |
| 45 | |
| 46 | /* |
| 47 | * LODs of an array layer are packed together. This maps to ARYSPC_FULL |
| 48 | * and is used for mipmapped 2D textures. |
| 49 | */ |
| 50 | INTEL_LAYOUT_WALK_LAYER, |
| 51 | |
| 52 | /* |
| 53 | * 3D slices of an LOD are packed together, horizontally with wrapping. |
| 54 | * Used for 3D textures. |
| 55 | */ |
| 56 | INTEL_LAYOUT_WALK_3D, |
| 57 | }; |
Chia-I Wu | 4bc4701 | 2014-08-14 13:03:25 +0800 | [diff] [blame] | 58 | |
Chia-I Wu | 8a8d8b6 | 2014-08-14 13:26:26 +0800 | [diff] [blame] | 59 | enum intel_layout_aux_type { |
| 60 | INTEL_LAYOUT_AUX_NONE, |
| 61 | INTEL_LAYOUT_AUX_HIZ, |
| 62 | INTEL_LAYOUT_AUX_MCS, |
Chia-I Wu | 4bc4701 | 2014-08-14 13:03:25 +0800 | [diff] [blame] | 63 | }; |
| 64 | |
Chia-I Wu | 457d0a6 | 2014-08-18 13:02:26 +0800 | [diff] [blame] | 65 | struct intel_layout_lod { |
| 66 | /* physical position */ |
| 67 | unsigned x; |
| 68 | unsigned y; |
| 69 | |
| 70 | /* |
| 71 | * Physical size of an LOD slice. There may be multiple slices when the |
| 72 | * walk type is not INTEL_LAYOUT_WALK_LAYER. |
| 73 | */ |
| 74 | unsigned slice_width; |
| 75 | unsigned slice_height; |
| 76 | }; |
| 77 | |
Chia-I Wu | 4bc4701 | 2014-08-14 13:03:25 +0800 | [diff] [blame] | 78 | /** |
| 79 | * Texture layout. |
| 80 | */ |
Chia-I Wu | 8a8d8b6 | 2014-08-14 13:26:26 +0800 | [diff] [blame] | 81 | struct intel_layout { |
Chia-I Wu | 457d0a6 | 2014-08-18 13:02:26 +0800 | [diff] [blame] | 82 | enum intel_layout_aux_type aux; |
| 83 | |
| 84 | /* physical width0, height0, and format */ |
| 85 | unsigned width0; |
| 86 | unsigned height0; |
Courtney Goeltzenleuchter | 382489d | 2015-04-10 08:34:15 -0600 | [diff] [blame] | 87 | VkFormat format; |
Chia-I Wu | 4bc4701 | 2014-08-14 13:03:25 +0800 | [diff] [blame] | 88 | bool separate_stencil; |
| 89 | |
| 90 | /* |
| 91 | * width, height, and size of pixel blocks, for conversion between 2D |
| 92 | * coordinates and memory offsets |
| 93 | */ |
| 94 | unsigned block_width; |
| 95 | unsigned block_height; |
| 96 | unsigned block_size; |
| 97 | |
Chia-I Wu | 457d0a6 | 2014-08-18 13:02:26 +0800 | [diff] [blame] | 98 | enum intel_layout_walk_type walk; |
Chia-I Wu | 4bc4701 | 2014-08-14 13:03:25 +0800 | [diff] [blame] | 99 | bool interleaved_samples; |
Chia-I Wu | 4bc4701 | 2014-08-14 13:03:25 +0800 | [diff] [blame] | 100 | |
| 101 | /* bitmask of valid tiling modes */ |
| 102 | unsigned valid_tilings; |
Chia-I Wu | d1eb90c | 2015-03-07 06:01:45 +0800 | [diff] [blame] | 103 | enum gen_surface_tiling tiling; |
Chia-I Wu | 4bc4701 | 2014-08-14 13:03:25 +0800 | [diff] [blame] | 104 | |
| 105 | /* mipmap alignments */ |
| 106 | unsigned align_i; |
| 107 | unsigned align_j; |
| 108 | |
Chia-I Wu | 457d0a6 | 2014-08-18 13:02:26 +0800 | [diff] [blame] | 109 | struct intel_layout_lod lods[INTEL_LAYOUT_MAX_LEVELS]; |
Chia-I Wu | 4bc4701 | 2014-08-14 13:03:25 +0800 | [diff] [blame] | 110 | |
Chia-I Wu | 457d0a6 | 2014-08-18 13:02:26 +0800 | [diff] [blame] | 111 | /* physical height of layers for INTEL_LAYOUT_WALK_LAYER */ |
Chia-I Wu | 4bc4701 | 2014-08-14 13:03:25 +0800 | [diff] [blame] | 112 | unsigned layer_height; |
| 113 | |
| 114 | /* distance in bytes between two pixel block rows */ |
| 115 | unsigned bo_stride; |
| 116 | /* number of pixel block rows */ |
| 117 | unsigned bo_height; |
| 118 | |
Chia-I Wu | 457d0a6 | 2014-08-18 13:02:26 +0800 | [diff] [blame] | 119 | /* bitmask of levels that can use aux */ |
| 120 | unsigned aux_enables; |
| 121 | unsigned aux_offsets[INTEL_LAYOUT_MAX_LEVELS]; |
Chia-I Wu | d1eb90c | 2015-03-07 06:01:45 +0800 | [diff] [blame] | 122 | unsigned aux_layer_height; |
Chia-I Wu | 4bc4701 | 2014-08-14 13:03:25 +0800 | [diff] [blame] | 123 | unsigned aux_stride; |
| 124 | unsigned aux_height; |
| 125 | }; |
| 126 | |
Chia-I Wu | 8a8d8b6 | 2014-08-14 13:26:26 +0800 | [diff] [blame] | 127 | void intel_layout_init(struct intel_layout *layout, |
Chia-I Wu | c94f3e5 | 2014-10-07 14:45:05 +0800 | [diff] [blame] | 128 | struct intel_dev *dev, |
Courtney Goeltzenleuchter | 382489d | 2015-04-10 08:34:15 -0600 | [diff] [blame] | 129 | const VkImageCreateInfo *info, |
Chia-I Wu | 794d12a | 2014-09-15 14:55:25 +0800 | [diff] [blame] | 130 | bool scanout); |
Chia-I Wu | 4bc4701 | 2014-08-14 13:03:25 +0800 | [diff] [blame] | 131 | |
Chia-I Wu | 4bc4701 | 2014-08-14 13:03:25 +0800 | [diff] [blame] | 132 | /** |
Chia-I Wu | 457d0a6 | 2014-08-18 13:02:26 +0800 | [diff] [blame] | 133 | * Convert from pixel position to 2D memory offset. |
Chia-I Wu | 4bc4701 | 2014-08-14 13:03:25 +0800 | [diff] [blame] | 134 | */ |
| 135 | static inline void |
Chia-I Wu | 8a8d8b6 | 2014-08-14 13:26:26 +0800 | [diff] [blame] | 136 | intel_layout_pos_to_mem(const struct intel_layout *layout, |
Chia-I Wu | 457d0a6 | 2014-08-18 13:02:26 +0800 | [diff] [blame] | 137 | unsigned pos_x, unsigned pos_y, |
Chia-I Wu | 8a8d8b6 | 2014-08-14 13:26:26 +0800 | [diff] [blame] | 138 | unsigned *mem_x, unsigned *mem_y) |
Chia-I Wu | 4bc4701 | 2014-08-14 13:03:25 +0800 | [diff] [blame] | 139 | { |
Chia-I Wu | 457d0a6 | 2014-08-18 13:02:26 +0800 | [diff] [blame] | 140 | assert(pos_x % layout->block_width == 0); |
| 141 | assert(pos_y % layout->block_height == 0); |
Chia-I Wu | 4bc4701 | 2014-08-14 13:03:25 +0800 | [diff] [blame] | 142 | |
Chia-I Wu | 457d0a6 | 2014-08-18 13:02:26 +0800 | [diff] [blame] | 143 | *mem_x = pos_x / layout->block_width * layout->block_size; |
| 144 | *mem_y = pos_y / layout->block_height; |
Chia-I Wu | 4bc4701 | 2014-08-14 13:03:25 +0800 | [diff] [blame] | 145 | } |
| 146 | |
| 147 | /** |
Chia-I Wu | 457d0a6 | 2014-08-18 13:02:26 +0800 | [diff] [blame] | 148 | * Convert from 2D memory offset to linear offset. |
Chia-I Wu | 4bc4701 | 2014-08-14 13:03:25 +0800 | [diff] [blame] | 149 | */ |
| 150 | static inline unsigned |
Chia-I Wu | 457d0a6 | 2014-08-18 13:02:26 +0800 | [diff] [blame] | 151 | intel_layout_mem_to_linear(const struct intel_layout *layout, |
| 152 | unsigned mem_x, unsigned mem_y) |
Chia-I Wu | 4bc4701 | 2014-08-14 13:03:25 +0800 | [diff] [blame] | 153 | { |
| 154 | return mem_y * layout->bo_stride + mem_x; |
| 155 | } |
| 156 | |
| 157 | /** |
Chia-I Wu | 457d0a6 | 2014-08-18 13:02:26 +0800 | [diff] [blame] | 158 | * Convert from 2D memory offset to raw offset. |
| 159 | */ |
| 160 | static inline unsigned |
| 161 | intel_layout_mem_to_raw(const struct intel_layout *layout, |
| 162 | unsigned mem_x, unsigned mem_y) |
| 163 | { |
Chia-I Wu | 08cd6e9 | 2015-02-11 13:44:50 -0700 | [diff] [blame] | 164 | unsigned tile_w U_ASSERT_ONLY; |
| 165 | unsigned tile_h; |
Chia-I Wu | 457d0a6 | 2014-08-18 13:02:26 +0800 | [diff] [blame] | 166 | |
| 167 | switch (layout->tiling) { |
Chia-I Wu | d1eb90c | 2015-03-07 06:01:45 +0800 | [diff] [blame] | 168 | case GEN6_TILING_NONE: |
| 169 | tile_w = 1; |
| 170 | tile_h = 1; |
Chia-I Wu | 457d0a6 | 2014-08-18 13:02:26 +0800 | [diff] [blame] | 171 | break; |
Chia-I Wu | d1eb90c | 2015-03-07 06:01:45 +0800 | [diff] [blame] | 172 | case GEN6_TILING_X: |
Chia-I Wu | 457d0a6 | 2014-08-18 13:02:26 +0800 | [diff] [blame] | 173 | tile_w = 512; |
| 174 | tile_h = 8; |
| 175 | break; |
Chia-I Wu | d1eb90c | 2015-03-07 06:01:45 +0800 | [diff] [blame] | 176 | case GEN6_TILING_Y: |
Chia-I Wu | 457d0a6 | 2014-08-18 13:02:26 +0800 | [diff] [blame] | 177 | tile_w = 128; |
| 178 | tile_h = 32; |
| 179 | break; |
Chia-I Wu | d1eb90c | 2015-03-07 06:01:45 +0800 | [diff] [blame] | 180 | case GEN8_TILING_W: |
| 181 | tile_w = 64; |
| 182 | tile_h = 64; |
| 183 | break; |
Chia-I Wu | 457d0a6 | 2014-08-18 13:02:26 +0800 | [diff] [blame] | 184 | default: |
| 185 | assert(!"unknown tiling"); |
| 186 | tile_w = 1; |
| 187 | tile_h = 1; |
| 188 | break; |
| 189 | } |
| 190 | |
| 191 | assert(mem_x % tile_w == 0); |
| 192 | assert(mem_y % tile_h == 0); |
| 193 | |
| 194 | return mem_y * layout->bo_stride + mem_x * tile_h; |
| 195 | } |
| 196 | |
| 197 | /** |
Chia-I Wu | 4bc4701 | 2014-08-14 13:03:25 +0800 | [diff] [blame] | 198 | * Return the stride, in bytes, between slices within a level. |
| 199 | */ |
| 200 | static inline unsigned |
Chia-I Wu | 457d0a6 | 2014-08-18 13:02:26 +0800 | [diff] [blame] | 201 | intel_layout_get_slice_stride(const struct intel_layout *layout, unsigned level) |
Chia-I Wu | 4bc4701 | 2014-08-14 13:03:25 +0800 | [diff] [blame] | 202 | { |
Chia-I Wu | 457d0a6 | 2014-08-18 13:02:26 +0800 | [diff] [blame] | 203 | unsigned h; |
Chia-I Wu | 4bc4701 | 2014-08-14 13:03:25 +0800 | [diff] [blame] | 204 | |
Chia-I Wu | 457d0a6 | 2014-08-18 13:02:26 +0800 | [diff] [blame] | 205 | switch (layout->walk) { |
| 206 | case INTEL_LAYOUT_WALK_LOD: |
| 207 | h = layout->lods[level].slice_height; |
| 208 | break; |
| 209 | case INTEL_LAYOUT_WALK_LAYER: |
| 210 | h = layout->layer_height; |
| 211 | break; |
| 212 | case INTEL_LAYOUT_WALK_3D: |
| 213 | if (level == 0) { |
| 214 | h = layout->lods[0].slice_height; |
| 215 | break; |
| 216 | } |
| 217 | /* fall through */ |
| 218 | default: |
| 219 | assert(!"no single stride to walk across slices"); |
| 220 | h = 0; |
| 221 | break; |
Chia-I Wu | 4bc4701 | 2014-08-14 13:03:25 +0800 | [diff] [blame] | 222 | } |
| 223 | |
Chia-I Wu | 457d0a6 | 2014-08-18 13:02:26 +0800 | [diff] [blame] | 224 | assert(h % layout->block_height == 0); |
Chia-I Wu | 4bc4701 | 2014-08-14 13:03:25 +0800 | [diff] [blame] | 225 | |
Chia-I Wu | 457d0a6 | 2014-08-18 13:02:26 +0800 | [diff] [blame] | 226 | return (h / layout->block_height) * layout->bo_stride; |
Chia-I Wu | 4bc4701 | 2014-08-14 13:03:25 +0800 | [diff] [blame] | 227 | } |
| 228 | |
| 229 | /** |
| 230 | * Return the physical size, in bytes, of a slice in a level. |
| 231 | */ |
| 232 | static inline unsigned |
Chia-I Wu | 8a8d8b6 | 2014-08-14 13:26:26 +0800 | [diff] [blame] | 233 | intel_layout_get_slice_size(const struct intel_layout *layout, unsigned level) |
Chia-I Wu | 4bc4701 | 2014-08-14 13:03:25 +0800 | [diff] [blame] | 234 | { |
Chia-I Wu | 457d0a6 | 2014-08-18 13:02:26 +0800 | [diff] [blame] | 235 | const unsigned w = layout->lods[level].slice_width; |
| 236 | const unsigned h = layout->lods[level].slice_height; |
Chia-I Wu | 4bc4701 | 2014-08-14 13:03:25 +0800 | [diff] [blame] | 237 | |
| 238 | assert(w % layout->block_width == 0); |
| 239 | assert(h % layout->block_height == 0); |
| 240 | |
| 241 | return (w / layout->block_width * layout->block_size) * |
| 242 | (h / layout->block_height); |
| 243 | } |
| 244 | |
| 245 | /** |
| 246 | * Return the pixel position of a slice. |
| 247 | */ |
| 248 | static inline void |
Chia-I Wu | 8a8d8b6 | 2014-08-14 13:26:26 +0800 | [diff] [blame] | 249 | intel_layout_get_slice_pos(const struct intel_layout *layout, |
| 250 | unsigned level, unsigned slice, |
| 251 | unsigned *x, unsigned *y) |
Chia-I Wu | 4bc4701 | 2014-08-14 13:03:25 +0800 | [diff] [blame] | 252 | { |
Chia-I Wu | 457d0a6 | 2014-08-18 13:02:26 +0800 | [diff] [blame] | 253 | switch (layout->walk) { |
| 254 | case INTEL_LAYOUT_WALK_LOD: |
| 255 | *x = layout->lods[level].x; |
| 256 | *y = layout->lods[level].y + layout->lods[level].slice_height * slice; |
| 257 | break; |
| 258 | case INTEL_LAYOUT_WALK_LAYER: |
| 259 | *x = layout->lods[level].x; |
| 260 | *y = layout->lods[level].y + layout->layer_height * slice; |
| 261 | break; |
| 262 | case INTEL_LAYOUT_WALK_3D: |
| 263 | { |
| 264 | /* slices are packed horizontally with wrapping */ |
| 265 | const unsigned sx = slice & ((1 << level) - 1); |
| 266 | const unsigned sy = slice >> level; |
Chia-I Wu | 4bc4701 | 2014-08-14 13:03:25 +0800 | [diff] [blame] | 267 | |
Chia-I Wu | 457d0a6 | 2014-08-18 13:02:26 +0800 | [diff] [blame] | 268 | *x = layout->lods[level].x + layout->lods[level].slice_width * sx; |
| 269 | *y = layout->lods[level].y + layout->lods[level].slice_height * sy; |
Chia-I Wu | 4bc4701 | 2014-08-14 13:03:25 +0800 | [diff] [blame] | 270 | |
Chia-I Wu | 457d0a6 | 2014-08-18 13:02:26 +0800 | [diff] [blame] | 271 | /* should not overlap with the next level */ |
| 272 | if (level + 1 < ARRAY_SIZE(layout->lods) && |
| 273 | layout->lods[level + 1].y) { |
| 274 | assert(*y + layout->lods[level].slice_height <= |
| 275 | layout->lods[level + 1].y); |
| 276 | } |
| 277 | break; |
Chia-I Wu | 4bc4701 | 2014-08-14 13:03:25 +0800 | [diff] [blame] | 278 | } |
Chia-I Wu | 457d0a6 | 2014-08-18 13:02:26 +0800 | [diff] [blame] | 279 | default: |
| 280 | assert(!"unknown layout walk type"); |
Chia-I Wu | 9a056dd | 2015-02-11 13:19:39 -0700 | [diff] [blame] | 281 | *x = 0; |
| 282 | *y = 0; |
Chia-I Wu | 457d0a6 | 2014-08-18 13:02:26 +0800 | [diff] [blame] | 283 | break; |
Chia-I Wu | 4bc4701 | 2014-08-14 13:03:25 +0800 | [diff] [blame] | 284 | } |
| 285 | |
| 286 | /* should not exceed the bo size */ |
Chia-I Wu | 457d0a6 | 2014-08-18 13:02:26 +0800 | [diff] [blame] | 287 | assert(*y + layout->lods[level].slice_height <= |
Chia-I Wu | 4bc4701 | 2014-08-14 13:03:25 +0800 | [diff] [blame] | 288 | layout->bo_height * layout->block_height); |
| 289 | } |
| 290 | |
Chia-I Wu | 63a5397 | 2014-12-04 12:51:54 +0800 | [diff] [blame] | 291 | unsigned |
| 292 | intel_layout_get_slice_tile_offset(const struct intel_layout *layout, |
| 293 | unsigned level, unsigned slice, |
| 294 | unsigned *x_offset, unsigned *y_offset); |
| 295 | |
Chia-I Wu | 8a8d8b6 | 2014-08-14 13:26:26 +0800 | [diff] [blame] | 296 | #endif /* LAYOUT_H */ |