blob: 93392fea5b1721d716f53810af89727eb6f5bea1 [file] [log] [blame]
Chia-I Wuc14d1562014-10-17 09:49:22 +08001/*
2 * XGL
3 *
4 * Copyright (C) 2014 LunarG, Inc.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included
14 * in all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE.
23 *
24 * Authors:
25 * Chia-I Wu <olv@lunarg.com>
26 */
27
28#include "img.h"
29#include "mem.h"
Chia-I Wu429a0aa2014-10-24 11:57:51 +080030#include "state.h"
Chia-I Wuc14d1562014-10-17 09:49:22 +080031#include "cmd_priv.h"
32
33static void cmd_meta_init_mem_view(struct intel_cmd *cmd,
34 XGL_GPU_MEMORY mem,
35 XGL_GPU_SIZE range,
36 XGL_FORMAT format,
37 XGL_MEMORY_STATE state,
38 struct intel_mem_view *view)
39{
40 XGL_MEMORY_VIEW_ATTACH_INFO info;
41
42 memset(&info, 0, sizeof(info));
43 info.sType = XGL_STRUCTURE_TYPE_MEMORY_VIEW_ATTACH_INFO;
44 info.mem = mem;
45 info.range = range;
46 info.stride = icd_format_get_size(format);
47 info.format = format;
48 info.state = state;
49
Chia-I Wubc7a30c2014-12-13 15:54:10 +080050 /*
51 * We do not rely on the hardware to avoid out-of-bound access. But we do
52 * not want the hardware to ignore the last element either.
53 */
54 if (info.range % info.stride)
55 info.range += info.stride - (info.range % info.stride);
56
Chia-I Wuc14d1562014-10-17 09:49:22 +080057 intel_mem_view_init(view, cmd->dev, &info);
58}
59
60static void cmd_meta_set_src_for_mem(struct intel_cmd *cmd,
61 const struct intel_mem *mem,
62 XGL_FORMAT format,
63 struct intel_cmd_meta *meta)
64{
65 struct intel_mem_view view;
66
67 cmd_meta_init_mem_view(cmd, (XGL_GPU_MEMORY) mem, mem->size, format,
68 XGL_MEMORY_STATE_GRAPHICS_SHADER_READ_ONLY, &view);
69
70 meta->src.valid = true;
71
72 memcpy(meta->src.surface, view.cmd, sizeof(view.cmd[0]) * view.cmd_len);
73 meta->src.surface_len = view.cmd_len;
74
75 meta->src.reloc_target = (intptr_t) mem->bo;
76 meta->src.reloc_offset = 0;
77 meta->src.reloc_flags = 0;
78}
79
80static void cmd_meta_set_dst_for_mem(struct intel_cmd *cmd,
81 const struct intel_mem *mem,
82 XGL_FORMAT format,
83 struct intel_cmd_meta *meta)
84{
85 struct intel_mem_view view;
86
87 cmd_meta_init_mem_view(cmd, (XGL_GPU_MEMORY) mem, mem->size, format,
88 XGL_MEMORY_STATE_GRAPHICS_SHADER_WRITE_ONLY, &view);
89
90 meta->dst.valid = true;
91
92 memcpy(meta->dst.surface, view.cmd, sizeof(view.cmd[0]) * view.cmd_len);
93 meta->dst.surface_len = view.cmd_len;
94
95 meta->dst.reloc_target = (intptr_t) mem->bo;
96 meta->dst.reloc_offset = 0;
Chia-I Wuc5e2ae32014-11-25 11:00:12 +080097 meta->dst.reloc_flags = INTEL_RELOC_WRITE;
Chia-I Wuc14d1562014-10-17 09:49:22 +080098}
99
100static void cmd_meta_set_src_for_img(struct intel_cmd *cmd,
101 const struct intel_img *img,
102 XGL_FORMAT format,
103 XGL_IMAGE_ASPECT aspect,
104 struct intel_cmd_meta *meta)
105{
106 XGL_IMAGE_VIEW_CREATE_INFO info;
107 struct intel_img_view *view;
108 XGL_RESULT ret;
109
110 memset(&info, 0, sizeof(info));
111 info.sType = XGL_STRUCTURE_TYPE_IMAGE_VIEW_CREATE_INFO;
112 info.image = (XGL_IMAGE) img;
113
114 switch (img->type) {
115 case XGL_IMAGE_1D:
116 info.viewType = XGL_IMAGE_VIEW_1D;
117 break;
118 case XGL_IMAGE_2D:
119 info.viewType = XGL_IMAGE_VIEW_2D;
120 break;
121 case XGL_IMAGE_3D:
122 info.viewType = XGL_IMAGE_VIEW_3D;
123 break;
124 default:
125 break;
126 }
127
128 info.format = format;
129 info.channels.r = XGL_CHANNEL_SWIZZLE_R;
130 info.channels.g = XGL_CHANNEL_SWIZZLE_G;
131 info.channels.b = XGL_CHANNEL_SWIZZLE_B;
132 info.channels.a = XGL_CHANNEL_SWIZZLE_A;
133 info.subresourceRange.aspect = aspect;
134 info.subresourceRange.baseMipLevel = 0;
135 info.subresourceRange.mipLevels = XGL_LAST_MIP_OR_SLICE;
136 info.subresourceRange.baseArraySlice = 0;
137 info.subresourceRange.arraySize = XGL_LAST_MIP_OR_SLICE;
138
139 ret = intel_img_view_create(cmd->dev, &info, &view);
140 if (ret != XGL_SUCCESS) {
141 cmd->result = ret;
142 return;
143 }
144
145 meta->src.valid = true;
146
147 memcpy(meta->src.surface, view->cmd,
148 sizeof(view->cmd[0]) * view->cmd_len);
149 meta->src.surface_len = view->cmd_len;
150
151 meta->src.reloc_target = (intptr_t) img->obj.mem->bo;
152 meta->src.reloc_offset = 0;
153 meta->src.reloc_flags = 0;
154
155 intel_img_view_destroy(view);
156}
157
Chia-I Wu83084ba2014-12-04 12:49:52 +0800158static void cmd_meta_adjust_compressed_dst(struct intel_cmd *cmd,
159 const struct intel_img *img,
160 struct intel_cmd_meta *meta)
161{
Chia-I Wu0d8c2ee2014-12-04 13:06:45 +0800162 XGL_INT w, h, layer;
163 unsigned x_offset, y_offset;
Chia-I Wu83084ba2014-12-04 12:49:52 +0800164
165 if (cmd_gen(cmd) >= INTEL_GEN(7)) {
166 w = GEN_EXTRACT(meta->dst.surface[2], GEN7_SURFACE_DW2_WIDTH);
167 h = GEN_EXTRACT(meta->dst.surface[2], GEN7_SURFACE_DW2_HEIGHT);
Chia-I Wu0d8c2ee2014-12-04 13:06:45 +0800168 layer = GEN_EXTRACT(meta->dst.surface[4],
169 GEN7_SURFACE_DW4_MIN_ARRAY_ELEMENT);
Chia-I Wu83084ba2014-12-04 12:49:52 +0800170 } else {
171 w = GEN_EXTRACT(meta->dst.surface[2], GEN6_SURFACE_DW2_WIDTH);
172 h = GEN_EXTRACT(meta->dst.surface[2], GEN6_SURFACE_DW2_HEIGHT);
Chia-I Wu0d8c2ee2014-12-04 13:06:45 +0800173 layer = GEN_EXTRACT(meta->dst.surface[4],
174 GEN6_SURFACE_DW4_MIN_ARRAY_ELEMENT);
Chia-I Wu83084ba2014-12-04 12:49:52 +0800175 }
176
177 /* note that the width/height fields have the real values minus 1 */
178 w = (w + img->layout.block_width) / img->layout.block_width - 1;
179 h = (h + img->layout.block_height) / img->layout.block_height - 1;
180
Chia-I Wu0d8c2ee2014-12-04 13:06:45 +0800181 /* adjust width and height */
Chia-I Wu83084ba2014-12-04 12:49:52 +0800182 if (cmd_gen(cmd) >= INTEL_GEN(7)) {
Chia-I Wu0d8c2ee2014-12-04 13:06:45 +0800183 meta->dst.surface[2] &= ~(GEN7_SURFACE_DW2_WIDTH__MASK |
184 GEN7_SURFACE_DW2_HEIGHT__MASK);
Chia-I Wu83084ba2014-12-04 12:49:52 +0800185 meta->dst.surface[2] |= GEN_SHIFT32(w, GEN7_SURFACE_DW2_WIDTH) |
186 GEN_SHIFT32(h, GEN7_SURFACE_DW2_HEIGHT);
187 } else {
Chia-I Wu0d8c2ee2014-12-04 13:06:45 +0800188 meta->dst.surface[2] &= ~(GEN6_SURFACE_DW2_WIDTH__MASK |
189 GEN6_SURFACE_DW2_HEIGHT__MASK);
Chia-I Wu83084ba2014-12-04 12:49:52 +0800190 meta->dst.surface[2] |= GEN_SHIFT32(w, GEN6_SURFACE_DW2_WIDTH) |
191 GEN_SHIFT32(h, GEN6_SURFACE_DW2_HEIGHT);
192 }
Chia-I Wu0d8c2ee2014-12-04 13:06:45 +0800193
194 if (!layer)
195 return;
196
197 meta->dst.reloc_offset = intel_layout_get_slice_tile_offset(&img->layout,
198 0, layer, &x_offset, &y_offset);
199
200 /*
201 * The lower 2 bits (or 1 bit for Y) are missing. This may be a problem
202 * for small images (16x16 or smaller). We will need to adjust the
203 * drawing rectangle instead.
204 */
205 x_offset = (x_offset / img->layout.block_width) >> 2;
206 y_offset = (y_offset / img->layout.block_height) >> 1;
207
208 /* adjust min array element and X/Y offsets */
209 if (cmd_gen(cmd) >= INTEL_GEN(7)) {
210 meta->dst.surface[4] &= ~GEN7_SURFACE_DW4_MIN_ARRAY_ELEMENT__MASK;
211 meta->dst.surface[5] |= GEN_SHIFT32(x_offset, GEN7_SURFACE_DW5_X_OFFSET) |
212 GEN_SHIFT32(y_offset, GEN7_SURFACE_DW5_Y_OFFSET);
213 } else {
214 meta->dst.surface[4] &= ~GEN6_SURFACE_DW4_MIN_ARRAY_ELEMENT__MASK;
215 meta->dst.surface[5] |= GEN_SHIFT32(x_offset, GEN6_SURFACE_DW5_X_OFFSET) |
216 GEN_SHIFT32(y_offset, GEN6_SURFACE_DW5_Y_OFFSET);
217 }
Chia-I Wu83084ba2014-12-04 12:49:52 +0800218}
219
Chia-I Wuc14d1562014-10-17 09:49:22 +0800220static void cmd_meta_set_dst_for_img(struct intel_cmd *cmd,
221 const struct intel_img *img,
222 XGL_FORMAT format,
223 XGL_UINT lod, XGL_UINT layer,
224 struct intel_cmd_meta *meta)
225{
226 XGL_COLOR_ATTACHMENT_VIEW_CREATE_INFO info;
227 struct intel_rt_view *rt;
228 XGL_RESULT ret;
229
230 memset(&info, 0, sizeof(info));
231 info.sType = XGL_STRUCTURE_TYPE_COLOR_ATTACHMENT_VIEW_CREATE_INFO;
232 info.image = (XGL_IMAGE) img;
233 info.format = format;
234 info.mipLevel = lod;
235 info.baseArraySlice = layer;
236 info.arraySize = 1;
237
238 ret = intel_rt_view_create(cmd->dev, &info, &rt);
239 if (ret != XGL_SUCCESS) {
240 cmd->result = ret;
241 return;
242 }
243
244 meta->dst.valid = true;
245
246 memcpy(meta->dst.surface, rt->cmd, sizeof(rt->cmd[0]) * rt->cmd_len);
247 meta->dst.surface_len = rt->cmd_len;
248
249 meta->dst.reloc_target = (intptr_t) img->obj.mem->bo;
250 meta->dst.reloc_offset = 0;
Chia-I Wuc5e2ae32014-11-25 11:00:12 +0800251 meta->dst.reloc_flags = INTEL_RELOC_WRITE;
Chia-I Wuc14d1562014-10-17 09:49:22 +0800252
Chia-I Wu83084ba2014-12-04 12:49:52 +0800253 if (icd_format_is_compressed(img->layout.format))
254 cmd_meta_adjust_compressed_dst(cmd, img, meta);
255
Chia-I Wuc14d1562014-10-17 09:49:22 +0800256 intel_rt_view_destroy(rt);
257}
258
259static void cmd_meta_set_src_for_writer(struct intel_cmd *cmd,
260 enum intel_cmd_writer_type writer,
261 XGL_GPU_SIZE size,
262 XGL_FORMAT format,
263 struct intel_cmd_meta *meta)
264{
265 struct intel_mem_view view;
266
267 cmd_meta_init_mem_view(cmd, XGL_NULL_HANDLE, size, format,
268 XGL_MEMORY_STATE_GRAPHICS_SHADER_READ_ONLY, &view);
269
270 meta->src.valid = true;
271
272 memcpy(meta->src.surface, view.cmd, sizeof(view.cmd[0]) * view.cmd_len);
273 meta->src.surface_len = view.cmd_len;
274
275 meta->src.reloc_target = (intptr_t) writer;
276 meta->src.reloc_offset = 0;
277 meta->src.reloc_flags = INTEL_CMD_RELOC_TARGET_IS_WRITER;
278}
279
Chia-I Wu429a0aa2014-10-24 11:57:51 +0800280static void cmd_meta_set_ds_view(struct intel_cmd *cmd,
281 const struct intel_img *img,
282 XGL_UINT lod, XGL_UINT layer,
283 struct intel_cmd_meta *meta)
Chia-I Wuc14d1562014-10-17 09:49:22 +0800284{
285 XGL_DEPTH_STENCIL_VIEW_CREATE_INFO info;
286 struct intel_ds_view *ds;
287 XGL_RESULT ret;
288
289 memset(&info, 0, sizeof(info));
290 info.sType = XGL_STRUCTURE_TYPE_DEPTH_STENCIL_VIEW_CREATE_INFO;
291 info.image = (XGL_IMAGE) img;
292 info.mipLevel = lod;
293 info.baseArraySlice = layer;
294 info.arraySize = 1;
295
296 ret = intel_ds_view_create(cmd->dev, &info, &ds);
297 if (ret != XGL_SUCCESS) {
298 cmd->result = ret;
299 return;
300 }
301
Chia-I Wu429a0aa2014-10-24 11:57:51 +0800302 meta->ds.view = ds;
303}
304
305static void cmd_meta_set_ds_state(struct intel_cmd *cmd,
306 XGL_IMAGE_ASPECT aspect,
307 XGL_UINT32 stencil_ref,
308 struct intel_cmd_meta *meta)
309{
310 XGL_DEPTH_STENCIL_STATE_CREATE_INFO info;
311 struct intel_ds_state *state;
312 XGL_RESULT ret;
313
314 memset(&info, 0, sizeof(info));
315 info.sType = XGL_STRUCTURE_TYPE_DEPTH_STENCIL_STATE_CREATE_INFO;
316
317 if (aspect == XGL_IMAGE_ASPECT_DEPTH) {
318 info.depthWriteEnable = XGL_TRUE;
319 }
320 else if (aspect == XGL_IMAGE_ASPECT_STENCIL) {
321 info.stencilTestEnable = XGL_TRUE;
322 info.stencilReadMask = 0xff;
323 info.stencilWriteMask = 0xff;
324 info.front.stencilFailOp = XGL_STENCIL_OP_KEEP;
325 info.front.stencilPassOp = XGL_STENCIL_OP_REPLACE;
326 info.front.stencilDepthFailOp = XGL_STENCIL_OP_KEEP;
327 info.front.stencilFunc = XGL_COMPARE_ALWAYS;
328 info.front.stencilRef = stencil_ref;
329 info.back = info.front;
330 }
331
332 ret = intel_ds_state_create(cmd->dev, &info, &state);
333 if (ret != XGL_SUCCESS) {
334 cmd->result = ret;
335 return;
336 }
337
338 meta->ds.state = state;
Chia-I Wuc14d1562014-10-17 09:49:22 +0800339}
340
341static enum intel_dev_meta_shader get_shader_id(const struct intel_dev *dev,
342 const struct intel_img *img,
343 bool copy_array)
344{
345 enum intel_dev_meta_shader shader_id;
346
347 switch (img->type) {
348 case XGL_IMAGE_1D:
349 shader_id = (copy_array) ?
350 INTEL_DEV_META_FS_COPY_1D_ARRAY : INTEL_DEV_META_FS_COPY_1D;
351 break;
352 case XGL_IMAGE_2D:
353 shader_id = (img->samples > 1) ? INTEL_DEV_META_FS_COPY_2D_MS :
354 (copy_array) ? INTEL_DEV_META_FS_COPY_2D_ARRAY :
355 INTEL_DEV_META_FS_COPY_2D;
356 break;
357 case XGL_IMAGE_3D:
358 default:
359 shader_id = INTEL_DEV_META_FS_COPY_2D_ARRAY;
360 break;
361 }
362
363 return shader_id;
364}
365
Chia-I Wuf3a27252014-11-24 15:27:01 +0800366static bool cmd_meta_mem_dword_aligned(const struct intel_cmd *cmd,
367 XGL_GPU_SIZE src_offset,
368 XGL_GPU_SIZE dst_offset,
369 XGL_GPU_SIZE size)
Chia-I Wuc14d1562014-10-17 09:49:22 +0800370{
Chia-I Wuf3a27252014-11-24 15:27:01 +0800371 return !((src_offset | dst_offset | size) & 0x3);
Chia-I Wuc14d1562014-10-17 09:49:22 +0800372}
373
374static XGL_FORMAT cmd_meta_img_raw_format(const struct intel_cmd *cmd,
375 XGL_FORMAT format)
376{
377 format.numericFormat = XGL_NUM_FMT_UINT;
378
Chia-I Wuffdde352014-12-20 15:12:16 +0800379 switch (icd_format_get_size(format)) {
380 case 1:
381 format.channelFormat = XGL_CH_FMT_R8;
382 break;
383 case 2:
384 format.channelFormat = XGL_CH_FMT_R16;
385 break;
386 case 4:
387 format.channelFormat = XGL_CH_FMT_R32;
388 break;
389 case 8:
390 format.channelFormat = XGL_CH_FMT_R32G32;
391 break;
392 case 16:
393 format.channelFormat = XGL_CH_FMT_R32G32B32A32;
394 break;
395 default:
396 assert(!"unsupported image format for raw blit op");
397 format.channelFormat = XGL_CH_FMT_UNDEFINED;
398 format.numericFormat = XGL_NUM_FMT_UNDEFINED;
399 break;
Chia-I Wuc14d1562014-10-17 09:49:22 +0800400 }
401
402 return format;
403}
404
405XGL_VOID XGLAPI intelCmdCopyMemory(
406 XGL_CMD_BUFFER cmdBuffer,
407 XGL_GPU_MEMORY srcMem,
408 XGL_GPU_MEMORY destMem,
409 XGL_UINT regionCount,
410 const XGL_MEMORY_COPY* pRegions)
411{
412 struct intel_cmd *cmd = intel_cmd(cmdBuffer);
413 struct intel_mem *src = intel_mem(srcMem);
414 struct intel_mem *dst = intel_mem(destMem);
415 struct intel_cmd_meta meta;
416 XGL_FORMAT format;
417 XGL_UINT i;
418
419 memset(&meta, 0, sizeof(meta));
Chia-I Wuf3a27252014-11-24 15:27:01 +0800420 meta.mode = INTEL_CMD_META_VS_POINTS;
Chia-I Wuc14d1562014-10-17 09:49:22 +0800421
Chia-I Wuc14d1562014-10-17 09:49:22 +0800422 meta.height = 1;
423 meta.samples = 1;
424
425 format.channelFormat = XGL_CH_FMT_UNDEFINED;
426 format.numericFormat = XGL_NUM_FMT_UINT;
427
428 for (i = 0; i < regionCount; i++) {
429 const XGL_MEMORY_COPY *region = &pRegions[i];
430 XGL_CHANNEL_FORMAT ch;
Chia-I Wuc14d1562014-10-17 09:49:22 +0800431
Chia-I Wuf3a27252014-11-24 15:27:01 +0800432 meta.src.x = region->srcOffset;
433 meta.dst.x = region->destOffset;
434 meta.width = region->copySize;
435
436 if (cmd_meta_mem_dword_aligned(cmd, region->srcOffset,
437 region->destOffset, region->copySize)) {
438 meta.shader_id = INTEL_DEV_META_VS_COPY_MEM;
439 meta.src.x /= 4;
440 meta.dst.x /= 4;
441 meta.width /= 4;
442
443 /*
444 * INTEL_DEV_META_VS_COPY_MEM is untyped but expects the stride to
445 * be 16
446 */
447 ch = XGL_CH_FMT_R32G32B32A32;
448 } else {
449 if (cmd_gen(cmd) == INTEL_GEN(6)) {
450 intel_dev_log(cmd->dev, XGL_DBG_MSG_ERROR,
451 XGL_VALIDATION_LEVEL_0, XGL_NULL_HANDLE, 0, 0,
452 "unaligned xglCmdCopyMemory unsupported");
453 cmd->result = XGL_ERROR_UNKNOWN;
454 continue;
455 }
456
457 meta.shader_id = INTEL_DEV_META_VS_COPY_MEM_UNALIGNED;
458
459 /*
460 * INTEL_DEV_META_VS_COPY_MEM_UNALIGNED is untyped but expects the
461 * stride to be 4
462 */
463 ch = XGL_CH_FMT_R8G8B8A8;
464 }
Chia-I Wuc14d1562014-10-17 09:49:22 +0800465
466 if (format.channelFormat != ch) {
467 format.channelFormat = ch;
468
469 cmd_meta_set_src_for_mem(cmd, src, format, &meta);
470 cmd_meta_set_dst_for_mem(cmd, dst, format, &meta);
471 }
472
Chia-I Wuc14d1562014-10-17 09:49:22 +0800473 cmd_draw_meta(cmd, &meta);
474 }
475}
476
477XGL_VOID XGLAPI intelCmdCopyImage(
478 XGL_CMD_BUFFER cmdBuffer,
479 XGL_IMAGE srcImage,
480 XGL_IMAGE destImage,
481 XGL_UINT regionCount,
482 const XGL_IMAGE_COPY* pRegions)
483{
484 struct intel_cmd *cmd = intel_cmd(cmdBuffer);
485 struct intel_img *src = intel_img(srcImage);
486 struct intel_img *dst = intel_img(destImage);
487 struct intel_cmd_meta meta;
488 XGL_FORMAT raw_format;
489 bool raw_copy;
490 XGL_UINT i;
491
492 if (src->type != dst->type) {
493 cmd->result = XGL_ERROR_UNKNOWN;
494 return;
495 }
496
497 if (icd_format_is_equal(src->layout.format, dst->layout.format)) {
498 raw_copy = true;
499 raw_format = cmd_meta_img_raw_format(cmd, src->layout.format);
500 } else if (icd_format_is_compressed(src->layout.format) ||
501 icd_format_is_compressed(dst->layout.format)) {
502 cmd->result = XGL_ERROR_UNKNOWN;
503 return;
504 }
505
506 memset(&meta, 0, sizeof(meta));
Chia-I Wu29e6f502014-11-24 14:27:29 +0800507 meta.mode = INTEL_CMD_META_FS_RECT;
Chia-I Wuc14d1562014-10-17 09:49:22 +0800508
509 cmd_meta_set_src_for_img(cmd, src,
510 (raw_copy) ? raw_format : src->layout.format,
511 XGL_IMAGE_ASPECT_COLOR, &meta);
512
513 meta.samples = dst->samples;
514
515 for (i = 0; i < regionCount; i++) {
516 const XGL_IMAGE_COPY *region = &pRegions[i];
517 XGL_UINT j;
518
519 meta.shader_id = get_shader_id(cmd->dev, src,
520 (region->extent.depth > 1));
521
522 meta.src.lod = region->srcSubresource.mipLevel;
523 meta.src.layer = region->srcSubresource.arraySlice +
524 region->srcOffset.z;
525 meta.src.x = region->srcOffset.x;
526 meta.src.y = region->srcOffset.y;
527
528 meta.dst.lod = region->destSubresource.mipLevel;
529 meta.dst.layer = region->destSubresource.arraySlice +
530 region->destOffset.z;
531 meta.dst.x = region->destOffset.x;
532 meta.dst.y = region->destOffset.y;
533
534 meta.width = region->extent.width;
535 meta.height = region->extent.height;
536
537 for (j = 0; j < region->extent.depth; j++) {
538 cmd_meta_set_dst_for_img(cmd, dst,
539 (raw_copy) ? raw_format : dst->layout.format,
540 meta.dst.lod, meta.dst.layer, &meta);
541
542 cmd_draw_meta(cmd, &meta);
543
544 meta.src.layer++;
545 meta.dst.layer++;
546 }
547 }
548}
549
550XGL_VOID XGLAPI intelCmdCopyMemoryToImage(
551 XGL_CMD_BUFFER cmdBuffer,
552 XGL_GPU_MEMORY srcMem,
553 XGL_IMAGE destImage,
554 XGL_UINT regionCount,
555 const XGL_MEMORY_IMAGE_COPY* pRegions)
556{
557 struct intel_cmd *cmd = intel_cmd(cmdBuffer);
558 struct intel_mem *mem = intel_mem(srcMem);
559 struct intel_img *img = intel_img(destImage);
560 struct intel_cmd_meta meta;
561 XGL_FORMAT format;
562 XGL_UINT i;
563
564 memset(&meta, 0, sizeof(meta));
Chia-I Wu29e6f502014-11-24 14:27:29 +0800565 meta.mode = INTEL_CMD_META_FS_RECT;
Chia-I Wuc14d1562014-10-17 09:49:22 +0800566
567 meta.shader_id = INTEL_DEV_META_FS_COPY_MEM_TO_IMG;
568 meta.samples = img->samples;
569
570 format = cmd_meta_img_raw_format(cmd, img->layout.format);
571 cmd_meta_set_src_for_mem(cmd, mem, format, &meta);
572
573 for (i = 0; i < regionCount; i++) {
574 const XGL_MEMORY_IMAGE_COPY *region = &pRegions[i];
575 XGL_UINT j;
576
577 meta.src.x = region->memOffset / icd_format_get_size(format);
578
579 meta.dst.lod = region->imageSubresource.mipLevel;
580 meta.dst.layer = region->imageSubresource.arraySlice +
581 region->imageOffset.z;
582 meta.dst.x = region->imageOffset.x;
583 meta.dst.y = region->imageOffset.y;
584
585 meta.width = region->imageExtent.width;
586 meta.height = region->imageExtent.height;
587
588 for (j = 0; j < region->imageExtent.depth; j++) {
589 cmd_meta_set_dst_for_img(cmd, img, format,
590 meta.dst.lod, meta.dst.layer, &meta);
591
592 cmd_draw_meta(cmd, &meta);
593
594 meta.src.x += meta.width * meta.height;
595 meta.dst.layer++;
596 }
597 }
598}
599
600XGL_VOID XGLAPI intelCmdCopyImageToMemory(
601 XGL_CMD_BUFFER cmdBuffer,
602 XGL_IMAGE srcImage,
603 XGL_GPU_MEMORY destMem,
604 XGL_UINT regionCount,
605 const XGL_MEMORY_IMAGE_COPY* pRegions)
606{
607 struct intel_cmd *cmd = intel_cmd(cmdBuffer);
608 struct intel_img *img = intel_img(srcImage);
609 struct intel_mem *mem = intel_mem(destMem);
610 struct intel_cmd_meta meta;
611 XGL_FORMAT format;
612 XGL_UINT i;
613
614 memset(&meta, 0, sizeof(meta));
Chia-I Wu29e6f502014-11-24 14:27:29 +0800615 meta.mode = INTEL_CMD_META_FS_RECT;
Chia-I Wuc14d1562014-10-17 09:49:22 +0800616
617 format = cmd_meta_img_raw_format(cmd, img->layout.format);
618 cmd_meta_set_src_for_img(cmd, img, format, XGL_IMAGE_ASPECT_COLOR, &meta);
619 cmd_meta_set_dst_for_mem(cmd, mem, format, &meta);
620
621 meta.height = 1;
622 meta.samples = 1;
623
624 for (i = 0; i < regionCount; i++) {
625 const XGL_MEMORY_IMAGE_COPY *region = &pRegions[i];
626 XGL_UINT j;
627
628 meta.shader_id = get_shader_id(cmd->dev, img,
629 (region->imageExtent.depth > 1));
630
631 meta.src.lod = region->imageSubresource.mipLevel;
632 meta.src.layer = region->imageSubresource.arraySlice +
633 region->imageOffset.z;
634 meta.src.x = region->imageOffset.x;
635 meta.src.y = region->imageOffset.y;
636
637 meta.dst.x = region->memOffset / icd_format_get_size(format);
638
639 meta.width = region->imageExtent.width * region->imageExtent.height;
640
641 for (j = 0; j < region->imageExtent.depth; j++) {
642 cmd_draw_meta(cmd, &meta);
643
644 meta.src.layer++;
645 meta.dst.x += meta.width;
646 }
647 }
648}
649
650XGL_VOID XGLAPI intelCmdCloneImageData(
651 XGL_CMD_BUFFER cmdBuffer,
652 XGL_IMAGE srcImage,
653 XGL_IMAGE_STATE srcImageState,
654 XGL_IMAGE destImage,
655 XGL_IMAGE_STATE destImageState)
656{
657 const struct intel_img *src = intel_img(srcImage);
658 XGL_IMAGE_COPY region;
659 XGL_UINT lv;
660
661 memset(&region, 0, sizeof(region));
662 region.srcSubresource.aspect = XGL_IMAGE_ASPECT_COLOR;
663 region.destSubresource.aspect = XGL_IMAGE_ASPECT_COLOR;
664
665 for (lv = 0; lv < src->mip_levels; lv++) {
666 region.srcSubresource.mipLevel = lv;
667 region.destSubresource.mipLevel = lv;
668
669 region.extent.width = u_minify(src->layout.width0, lv);
670 region.extent.height = u_minify(src->layout.height0, lv);
671 region.extent.depth = src->array_size;
672
673 intelCmdCopyImage(cmdBuffer, srcImage, destImage, 1, &region);
674 }
675}
676
677XGL_VOID XGLAPI intelCmdUpdateMemory(
678 XGL_CMD_BUFFER cmdBuffer,
679 XGL_GPU_MEMORY destMem,
680 XGL_GPU_SIZE destOffset,
681 XGL_GPU_SIZE dataSize,
682 const XGL_UINT32* pData)
683{
684 struct intel_cmd *cmd = intel_cmd(cmdBuffer);
685 struct intel_mem *dst = intel_mem(destMem);
686 struct intel_cmd_meta meta;
687 XGL_FORMAT format;
Chia-I Wuc14d1562014-10-17 09:49:22 +0800688 uint32_t *ptr;
689 uint32_t offset;
690
Chia-I Wuf3a27252014-11-24 15:27:01 +0800691 /* must be 4-byte aligned */
692 if ((destOffset | dataSize) & 3) {
693 cmd->result = XGL_ERROR_UNKNOWN;
694 return;
695 }
696
Chia-I Wuc14d1562014-10-17 09:49:22 +0800697 /* write to dynamic state writer first */
698 offset = cmd_state_pointer(cmd, INTEL_CMD_ITEM_BLOB, 32,
699 (dataSize + 3) / 4, &ptr);
700 memcpy(ptr, pData, dataSize);
701
Chia-I Wuc14d1562014-10-17 09:49:22 +0800702 memset(&meta, 0, sizeof(meta));
Chia-I Wuf3a27252014-11-24 15:27:01 +0800703 meta.mode = INTEL_CMD_META_VS_POINTS;
Chia-I Wuc14d1562014-10-17 09:49:22 +0800704
Chia-I Wuf3a27252014-11-24 15:27:01 +0800705 meta.shader_id = INTEL_DEV_META_VS_COPY_MEM;
706
707 meta.src.x = offset / 4;
708 meta.dst.x = destOffset / 4;
709 meta.width = dataSize / 4;
710 meta.height = 1;
711 meta.samples = 1;
712
713 /*
714 * INTEL_DEV_META_VS_COPY_MEM is untyped but expects the stride to be 16
715 */
716 format.channelFormat = XGL_CH_FMT_R32G32B32A32;
717 format.numericFormat = XGL_NUM_FMT_UINT;
Chia-I Wuc14d1562014-10-17 09:49:22 +0800718
719 cmd_meta_set_src_for_writer(cmd, INTEL_CMD_WRITER_STATE,
720 offset + dataSize, format, &meta);
721 cmd_meta_set_dst_for_mem(cmd, dst, format, &meta);
722
Chia-I Wuc14d1562014-10-17 09:49:22 +0800723 cmd_draw_meta(cmd, &meta);
724}
725
726XGL_VOID XGLAPI intelCmdFillMemory(
727 XGL_CMD_BUFFER cmdBuffer,
728 XGL_GPU_MEMORY destMem,
729 XGL_GPU_SIZE destOffset,
730 XGL_GPU_SIZE fillSize,
731 XGL_UINT32 data)
732{
733 struct intel_cmd *cmd = intel_cmd(cmdBuffer);
734 struct intel_mem *dst = intel_mem(destMem);
735 struct intel_cmd_meta meta;
736 XGL_FORMAT format;
Chia-I Wuc14d1562014-10-17 09:49:22 +0800737
738 /* must be 4-byte aligned */
739 if ((destOffset | fillSize) & 3) {
740 cmd->result = XGL_ERROR_UNKNOWN;
741 return;
742 }
743
744 memset(&meta, 0, sizeof(meta));
Chia-I Wuf3a27252014-11-24 15:27:01 +0800745 meta.mode = INTEL_CMD_META_VS_POINTS;
Chia-I Wuc14d1562014-10-17 09:49:22 +0800746
Chia-I Wuf3a27252014-11-24 15:27:01 +0800747 meta.shader_id = INTEL_DEV_META_VS_FILL_MEM;
Chia-I Wuc14d1562014-10-17 09:49:22 +0800748
749 meta.clear_val[0] = data;
Chia-I Wuc14d1562014-10-17 09:49:22 +0800750
Chia-I Wuf3a27252014-11-24 15:27:01 +0800751 meta.dst.x = destOffset / 4;
752 meta.width = fillSize / 4;
Chia-I Wuc14d1562014-10-17 09:49:22 +0800753 meta.height = 1;
754 meta.samples = 1;
755
Chia-I Wuf3a27252014-11-24 15:27:01 +0800756 /*
757 * INTEL_DEV_META_VS_FILL_MEM is untyped but expects the stride to be 16
758 */
759 format.channelFormat = XGL_CH_FMT_R32G32B32A32;
760 format.numericFormat = XGL_NUM_FMT_UINT;
761
762 cmd_meta_set_dst_for_mem(cmd, dst, format, &meta);
763
Chia-I Wuc14d1562014-10-17 09:49:22 +0800764 cmd_draw_meta(cmd, &meta);
765}
766
767static void cmd_meta_clear_image(struct intel_cmd *cmd,
768 struct intel_img *img,
769 XGL_FORMAT format,
770 struct intel_cmd_meta *meta,
771 const XGL_IMAGE_SUBRESOURCE_RANGE *range)
772{
773 XGL_UINT mip_levels, array_size;
774 XGL_UINT i, j;
775
776 if (range->baseMipLevel >= img->mip_levels ||
777 range->baseArraySlice >= img->array_size)
778 return;
779
780 mip_levels = img->mip_levels - range->baseMipLevel;
781 if (mip_levels > range->mipLevels)
782 mip_levels = range->mipLevels;
783
784 array_size = img->array_size - range->baseArraySlice;
785 if (array_size > range->arraySize)
786 array_size = range->arraySize;
787
Chia-I Wuc14d1562014-10-17 09:49:22 +0800788 for (i = 0; i < mip_levels; i++) {
Chia-I Wufaaed472014-10-28 14:17:43 +0800789 meta->dst.lod = range->baseMipLevel + i;
790 meta->dst.layer = range->baseArraySlice;
791
Chia-I Wuc14d1562014-10-17 09:49:22 +0800792 meta->width = u_minify(img->layout.width0, meta->dst.lod);
793 meta->height = u_minify(img->layout.height0, meta->dst.lod);
794
795 for (j = 0; j < array_size; j++) {
796 if (range->aspect == XGL_IMAGE_ASPECT_COLOR) {
797 cmd_meta_set_dst_for_img(cmd, img, format,
798 meta->dst.lod, meta->dst.layer, meta);
799
800 cmd_draw_meta(cmd, meta);
801 } else {
Chia-I Wu429a0aa2014-10-24 11:57:51 +0800802 cmd_meta_set_ds_view(cmd, img, meta->dst.lod,
Chia-I Wuc14d1562014-10-17 09:49:22 +0800803 meta->dst.layer, meta);
Chia-I Wu429a0aa2014-10-24 11:57:51 +0800804 cmd_meta_set_ds_state(cmd, range->aspect,
805 meta->clear_val[1], meta);
Chia-I Wuc14d1562014-10-17 09:49:22 +0800806
807 cmd_draw_meta(cmd, meta);
808
Chia-I Wu429a0aa2014-10-24 11:57:51 +0800809 intel_ds_view_destroy(meta->ds.view);
810 intel_ds_state_destroy(meta->ds.state);
Chia-I Wuc14d1562014-10-17 09:49:22 +0800811 }
812
813 meta->dst.layer++;
814 }
Chia-I Wuc14d1562014-10-17 09:49:22 +0800815 }
816}
817
818XGL_VOID XGLAPI intelCmdClearColorImage(
819 XGL_CMD_BUFFER cmdBuffer,
820 XGL_IMAGE image,
821 const XGL_FLOAT color[4],
822 XGL_UINT rangeCount,
823 const XGL_IMAGE_SUBRESOURCE_RANGE* pRanges)
824{
825 struct intel_cmd *cmd = intel_cmd(cmdBuffer);
826 struct intel_img *img = intel_img(image);
827 struct intel_cmd_meta meta;
828 XGL_UINT i;
829
830 memset(&meta, 0, sizeof(meta));
Chia-I Wu29e6f502014-11-24 14:27:29 +0800831 meta.mode = INTEL_CMD_META_FS_RECT;
Chia-I Wuc14d1562014-10-17 09:49:22 +0800832
833 meta.shader_id = INTEL_DEV_META_FS_CLEAR_COLOR;
834 meta.samples = img->samples;
835
836 meta.clear_val[0] = u_fui(color[0]);
837 meta.clear_val[1] = u_fui(color[1]);
838 meta.clear_val[2] = u_fui(color[2]);
839 meta.clear_val[3] = u_fui(color[3]);
840
841 for (i = 0; i < rangeCount; i++) {
842 cmd_meta_clear_image(cmd, img, img->layout.format,
843 &meta, &pRanges[i]);
844 }
845}
846
847XGL_VOID XGLAPI intelCmdClearColorImageRaw(
848 XGL_CMD_BUFFER cmdBuffer,
849 XGL_IMAGE image,
850 const XGL_UINT32 color[4],
851 XGL_UINT rangeCount,
852 const XGL_IMAGE_SUBRESOURCE_RANGE* pRanges)
853{
854 struct intel_cmd *cmd = intel_cmd(cmdBuffer);
855 struct intel_img *img = intel_img(image);
856 struct intel_cmd_meta meta;
857 XGL_FORMAT format;
858 XGL_UINT i;
859
860 memset(&meta, 0, sizeof(meta));
Chia-I Wu29e6f502014-11-24 14:27:29 +0800861 meta.mode = INTEL_CMD_META_FS_RECT;
Chia-I Wuc14d1562014-10-17 09:49:22 +0800862
863 meta.shader_id = INTEL_DEV_META_FS_CLEAR_COLOR;
864 meta.samples = img->samples;
865
Chia-I Wuffdde352014-12-20 15:12:16 +0800866 icd_format_get_raw_value(img->layout.format, color, meta.clear_val);
Chia-I Wuc14d1562014-10-17 09:49:22 +0800867 format = cmd_meta_img_raw_format(cmd, img->layout.format);
868
869 for (i = 0; i < rangeCount; i++)
870 cmd_meta_clear_image(cmd, img, format, &meta, &pRanges[i]);
871}
872
873XGL_VOID XGLAPI intelCmdClearDepthStencil(
874 XGL_CMD_BUFFER cmdBuffer,
875 XGL_IMAGE image,
876 XGL_FLOAT depth,
877 XGL_UINT32 stencil,
878 XGL_UINT rangeCount,
879 const XGL_IMAGE_SUBRESOURCE_RANGE* pRanges)
880{
881 struct intel_cmd *cmd = intel_cmd(cmdBuffer);
882 struct intel_img *img = intel_img(image);
883 struct intel_cmd_meta meta;
884 XGL_UINT i;
885
886 memset(&meta, 0, sizeof(meta));
Chia-I Wu29e6f502014-11-24 14:27:29 +0800887 meta.mode = INTEL_CMD_META_DEPTH_STENCIL_RECT;
Chia-I Wuc14d1562014-10-17 09:49:22 +0800888
889 meta.shader_id = INTEL_DEV_META_FS_CLEAR_DEPTH;
890 meta.samples = img->samples;
891
Chia-I Wu429a0aa2014-10-24 11:57:51 +0800892 meta.clear_val[0] = u_fui(depth);
893 meta.clear_val[1] = stencil;
894
Chia-I Wuc14d1562014-10-17 09:49:22 +0800895 for (i = 0; i < rangeCount; i++) {
896 const XGL_IMAGE_SUBRESOURCE_RANGE *range = &pRanges[i];
897
Chia-I Wuc14d1562014-10-17 09:49:22 +0800898 cmd_meta_clear_image(cmd, img, img->layout.format,
899 &meta, range);
900 }
901}
902
903XGL_VOID XGLAPI intelCmdResolveImage(
904 XGL_CMD_BUFFER cmdBuffer,
905 XGL_IMAGE srcImage,
906 XGL_IMAGE destImage,
907 XGL_UINT rectCount,
908 const XGL_IMAGE_RESOLVE* pRects)
909{
910 struct intel_cmd *cmd = intel_cmd(cmdBuffer);
911 struct intel_img *src = intel_img(srcImage);
912 struct intel_img *dst = intel_img(destImage);
913 struct intel_cmd_meta meta;
914 XGL_FORMAT format;
915 XGL_UINT i;
916
917 if (src->samples <= 1 || dst->samples > 1 ||
918 !icd_format_is_equal(src->layout.format, dst->layout.format)) {
919 cmd->result = XGL_ERROR_UNKNOWN;
920 return;
921 }
922
923 memset(&meta, 0, sizeof(meta));
Chia-I Wu29e6f502014-11-24 14:27:29 +0800924 meta.mode = INTEL_CMD_META_FS_RECT;
Chia-I Wuc14d1562014-10-17 09:49:22 +0800925
926 switch (src->samples) {
927 case 2:
928 default:
929 meta.shader_id = INTEL_DEV_META_FS_RESOLVE_2X;
930 break;
931 case 4:
932 meta.shader_id = INTEL_DEV_META_FS_RESOLVE_4X;
933 break;
934 case 8:
935 meta.shader_id = INTEL_DEV_META_FS_RESOLVE_8X;
936 break;
937 case 16:
938 meta.shader_id = INTEL_DEV_META_FS_RESOLVE_16X;
939 break;
940 }
941
942 meta.samples = 1;
943
944 format = cmd_meta_img_raw_format(cmd, src->layout.format);
945 cmd_meta_set_src_for_img(cmd, src, format, XGL_IMAGE_ASPECT_COLOR, &meta);
946
947 for (i = 0; i < rectCount; i++) {
948 const XGL_IMAGE_RESOLVE *rect = &pRects[i];
949
950 meta.src.lod = rect->srcSubresource.mipLevel;
951 meta.src.layer = rect->srcSubresource.arraySlice;
952 meta.src.x = rect->srcOffset.x;
953 meta.src.y = rect->srcOffset.y;
954
955 meta.dst.lod = rect->destSubresource.mipLevel;
956 meta.dst.layer = rect->destSubresource.arraySlice;
957 meta.dst.x = rect->destOffset.x;
958 meta.dst.y = rect->destOffset.y;
959
960 meta.width = rect->extent.width;
961 meta.height = rect->extent.height;
962
963 cmd_meta_set_dst_for_img(cmd, dst, format,
964 meta.dst.lod, meta.dst.layer, &meta);
965
966 cmd_draw_meta(cmd, &meta);
967 }
968}