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gerrit-public.fairphone.software / platform / prebuilts / sdk / f734ac8a54e1a2e2c61f1970428c486ee5546077 / . / renderscript / clang-include / avx512bwintrin.h
blob: d3c5a6c96446b3ef91e8371140370be706f2e191 [file] [log] [blame]
Stephen Hinesee4ca282014-12-02 17:05:12 -0800[diff] [blame]1/*===------------- avx512bwintrin.h - AVX512BW intrinsics ------------------===
2 *
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a copy
5 * of this software and associated documentation files (the "Software"), to deal
6 * in the Software without restriction, including without limitation the rights
7 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
8 * copies of the Software, and to permit persons to whom the Software is
9 * furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
17 * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
19 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
20 * THE SOFTWARE.
21 *
22 *===-----------------------------------------------------------------------===
23 */
Stephen Hinesb4d9c8b2015-03-30 16:04:04 -0700[diff] [blame]24#ifndef __IMMINTRIN_H
25#error "Never use <avx512bwintrin.h> directly; include <immintrin.h> instead."
26#endif
Stephen Hinesee4ca282014-12-02 17:05:12 -0800[diff] [blame]27
28#ifndef __AVX512BWINTRIN_H
29#define __AVX512BWINTRIN_H
30
31typedef unsigned int __mmask32;
32typedef unsigned long long __mmask64;
Stephen Hinesee4ca282014-12-02 17:05:12 -0800[diff] [blame]33
Pirama Arumuga Nainar4e74a022016-03-17 18:03:02 -0700[diff] [blame]34/* Define the default attributes for the functions in this file. */
35#define __DEFAULT_FN_ATTRS __attribute__((__always_inline__, __nodebug__, __target__("avx512bw")))
36
Pirama Arumuga Nainarbb4374f2016-10-20 16:43:03 -0700[diff] [blame]37static __inline __m512i __DEFAULT_FN_ATTRS
Pirama Arumuga Nainar4e74a022016-03-17 18:03:02 -0700[diff] [blame]38_mm512_setzero_qi(void) {
Pirama Arumuga Nainarbb4374f2016-10-20 16:43:03 -0700[diff] [blame]39 return (__m512i)(__v64qi){ 0, 0, 0, 0, 0, 0, 0, 0,
40 0, 0, 0, 0, 0, 0, 0, 0,
41 0, 0, 0, 0, 0, 0, 0, 0,
42 0, 0, 0, 0, 0, 0, 0, 0,
43 0, 0, 0, 0, 0, 0, 0, 0,
44 0, 0, 0, 0, 0, 0, 0, 0,
45 0, 0, 0, 0, 0, 0, 0, 0,
46 0, 0, 0, 0, 0, 0, 0, 0 };
Stephen Hines28c5e1e2015-08-13 18:18:46 -0700[diff] [blame]47}
48
Pirama Arumuga Nainarbb4374f2016-10-20 16:43:03 -0700[diff] [blame]49static __inline __m512i __DEFAULT_FN_ATTRS
Pirama Arumuga Nainar4e74a022016-03-17 18:03:02 -0700[diff] [blame]50_mm512_setzero_hi(void) {
Pirama Arumuga Nainarbb4374f2016-10-20 16:43:03 -0700[diff] [blame]51 return (__m512i)(__v32hi){ 0, 0, 0, 0, 0, 0, 0, 0,
52 0, 0, 0, 0, 0, 0, 0, 0,
53 0, 0, 0, 0, 0, 0, 0, 0,
54 0, 0, 0, 0, 0, 0, 0, 0 };
Stephen Hines28c5e1e2015-08-13 18:18:46 -0700[diff] [blame]55}
Stephen Hinesee4ca282014-12-02 17:05:12 -0800[diff] [blame]56
57/* Integer compare */
58
Pirama Arumuga Nainar4e74a022016-03-17 18:03:02 -0700[diff] [blame]59static __inline__ __mmask64 __DEFAULT_FN_ATTRS
Stephen Hinesee4ca282014-12-02 17:05:12 -0800[diff] [blame]60_mm512_cmpeq_epi8_mask(__m512i __a, __m512i __b) {
61 return (__mmask64)__builtin_ia32_pcmpeqb512_mask((__v64qi)__a, (__v64qi)__b,
62 (__mmask64)-1);
63}
64
Pirama Arumuga Nainar4e74a022016-03-17 18:03:02 -0700[diff] [blame]65static __inline__ __mmask64 __DEFAULT_FN_ATTRS
Stephen Hinesee4ca282014-12-02 17:05:12 -0800[diff] [blame]66_mm512_mask_cmpeq_epi8_mask(__mmask64 __u, __m512i __a, __m512i __b) {
67 return (__mmask64)__builtin_ia32_pcmpeqb512_mask((__v64qi)__a, (__v64qi)__b,
68 __u);
69}
70
Pirama Arumuga Nainar4e74a022016-03-17 18:03:02 -0700[diff] [blame]71static __inline__ __mmask64 __DEFAULT_FN_ATTRS
Stephen Hinesb4d9c8b2015-03-30 16:04:04 -0700[diff] [blame]72_mm512_cmpeq_epu8_mask(__m512i __a, __m512i __b) {
73 return (__mmask64)__builtin_ia32_ucmpb512_mask((__v64qi)__a, (__v64qi)__b, 0,
74 (__mmask64)-1);
75}
76
Pirama Arumuga Nainar4e74a022016-03-17 18:03:02 -0700[diff] [blame]77static __inline__ __mmask64 __DEFAULT_FN_ATTRS
Stephen Hinesb4d9c8b2015-03-30 16:04:04 -0700[diff] [blame]78_mm512_mask_cmpeq_epu8_mask(__mmask64 __u, __m512i __a, __m512i __b) {
79 return (__mmask64)__builtin_ia32_ucmpb512_mask((__v64qi)__a, (__v64qi)__b, 0,
80 __u);
81}
82
Pirama Arumuga Nainar4e74a022016-03-17 18:03:02 -0700[diff] [blame]83static __inline__ __mmask32 __DEFAULT_FN_ATTRS
Stephen Hinesee4ca282014-12-02 17:05:12 -0800[diff] [blame]84_mm512_cmpeq_epi16_mask(__m512i __a, __m512i __b) {
85 return (__mmask32)__builtin_ia32_pcmpeqw512_mask((__v32hi)__a, (__v32hi)__b,
86 (__mmask32)-1);
87}
88
Pirama Arumuga Nainar4e74a022016-03-17 18:03:02 -0700[diff] [blame]89static __inline__ __mmask32 __DEFAULT_FN_ATTRS
Stephen Hinesee4ca282014-12-02 17:05:12 -0800[diff] [blame]90_mm512_mask_cmpeq_epi16_mask(__mmask32 __u, __m512i __a, __m512i __b) {
91 return (__mmask32)__builtin_ia32_pcmpeqw512_mask((__v32hi)__a, (__v32hi)__b,
92 __u);
93}
94
Pirama Arumuga Nainar4e74a022016-03-17 18:03:02 -0700[diff] [blame]95static __inline__ __mmask32 __DEFAULT_FN_ATTRS
Stephen Hinesb4d9c8b2015-03-30 16:04:04 -0700[diff] [blame]96_mm512_cmpeq_epu16_mask(__m512i __a, __m512i __b) {
97 return (__mmask32)__builtin_ia32_ucmpw512_mask((__v32hi)__a, (__v32hi)__b, 0,
98 (__mmask32)-1);
99}
100
Pirama Arumuga Nainar4e74a022016-03-17 18:03:02 -0700[diff] [blame]101static __inline__ __mmask32 __DEFAULT_FN_ATTRS
Stephen Hinesb4d9c8b2015-03-30 16:04:04 -0700[diff] [blame]102_mm512_mask_cmpeq_epu16_mask(__mmask32 __u, __m512i __a, __m512i __b) {
103 return (__mmask32)__builtin_ia32_ucmpw512_mask((__v32hi)__a, (__v32hi)__b, 0,
104 __u);
105}
106
Pirama Arumuga Nainar4e74a022016-03-17 18:03:02 -0700[diff] [blame]107static __inline__ __mmask64 __DEFAULT_FN_ATTRS
Stephen Hinesb4d9c8b2015-03-30 16:04:04 -0700[diff] [blame]108_mm512_cmpge_epi8_mask(__m512i __a, __m512i __b) {
109 return (__mmask64)__builtin_ia32_cmpb512_mask((__v64qi)__a, (__v64qi)__b, 5,
110 (__mmask64)-1);
111}
112
Pirama Arumuga Nainar4e74a022016-03-17 18:03:02 -0700[diff] [blame]113static __inline__ __mmask64 __DEFAULT_FN_ATTRS
Stephen Hinesb4d9c8b2015-03-30 16:04:04 -0700[diff] [blame]114_mm512_mask_cmpge_epi8_mask(__mmask64 __u, __m512i __a, __m512i __b) {
115 return (__mmask64)__builtin_ia32_cmpb512_mask((__v64qi)__a, (__v64qi)__b, 5,
116 __u);
117}
118
Pirama Arumuga Nainar4e74a022016-03-17 18:03:02 -0700[diff] [blame]119static __inline__ __mmask64 __DEFAULT_FN_ATTRS
Stephen Hinesb4d9c8b2015-03-30 16:04:04 -0700[diff] [blame]120_mm512_cmpge_epu8_mask(__m512i __a, __m512i __b) {
121 return (__mmask64)__builtin_ia32_ucmpb512_mask((__v64qi)__a, (__v64qi)__b, 5,
122 (__mmask64)-1);
123}
124
Pirama Arumuga Nainar4e74a022016-03-17 18:03:02 -0700[diff] [blame]125static __inline__ __mmask64 __DEFAULT_FN_ATTRS
Stephen Hinesb4d9c8b2015-03-30 16:04:04 -0700[diff] [blame]126_mm512_mask_cmpge_epu8_mask(__mmask64 __u, __m512i __a, __m512i __b) {
127 return (__mmask64)__builtin_ia32_ucmpb512_mask((__v64qi)__a, (__v64qi)__b, 5,
128 __u);
129}
130
Pirama Arumuga Nainar4e74a022016-03-17 18:03:02 -0700[diff] [blame]131static __inline__ __mmask32 __DEFAULT_FN_ATTRS
Stephen Hinesb4d9c8b2015-03-30 16:04:04 -0700[diff] [blame]132_mm512_cmpge_epi16_mask(__m512i __a, __m512i __b) {
133 return (__mmask32)__builtin_ia32_cmpw512_mask((__v32hi)__a, (__v32hi)__b, 5,
134 (__mmask32)-1);
135}
136
Pirama Arumuga Nainar4e74a022016-03-17 18:03:02 -0700[diff] [blame]137static __inline__ __mmask32 __DEFAULT_FN_ATTRS
Stephen Hinesb4d9c8b2015-03-30 16:04:04 -0700[diff] [blame]138_mm512_mask_cmpge_epi16_mask(__mmask32 __u, __m512i __a, __m512i __b) {
139 return (__mmask32)__builtin_ia32_cmpw512_mask((__v32hi)__a, (__v32hi)__b, 5,
140 __u);
141}
142
Pirama Arumuga Nainar4e74a022016-03-17 18:03:02 -0700[diff] [blame]143static __inline__ __mmask32 __DEFAULT_FN_ATTRS
Stephen Hinesb4d9c8b2015-03-30 16:04:04 -0700[diff] [blame]144_mm512_cmpge_epu16_mask(__m512i __a, __m512i __b) {
145 return (__mmask32)__builtin_ia32_ucmpw512_mask((__v32hi)__a, (__v32hi)__b, 5,
146 (__mmask32)-1);
147}
148
Pirama Arumuga Nainar4e74a022016-03-17 18:03:02 -0700[diff] [blame]149static __inline__ __mmask32 __DEFAULT_FN_ATTRS
Stephen Hinesb4d9c8b2015-03-30 16:04:04 -0700[diff] [blame]150_mm512_mask_cmpge_epu16_mask(__mmask32 __u, __m512i __a, __m512i __b) {
151 return (__mmask32)__builtin_ia32_ucmpw512_mask((__v32hi)__a, (__v32hi)__b, 5,
152 __u);
153}
154
Pirama Arumuga Nainar4e74a022016-03-17 18:03:02 -0700[diff] [blame]155static __inline__ __mmask64 __DEFAULT_FN_ATTRS
Stephen Hinesb4d9c8b2015-03-30 16:04:04 -0700[diff] [blame]156_mm512_cmpgt_epi8_mask(__m512i __a, __m512i __b) {
157 return (__mmask64)__builtin_ia32_pcmpgtb512_mask((__v64qi)__a, (__v64qi)__b,
158 (__mmask64)-1);
159}
160
Pirama Arumuga Nainar4e74a022016-03-17 18:03:02 -0700[diff] [blame]161static __inline__ __mmask64 __DEFAULT_FN_ATTRS
Stephen Hinesb4d9c8b2015-03-30 16:04:04 -0700[diff] [blame]162_mm512_mask_cmpgt_epi8_mask(__mmask64 __u, __m512i __a, __m512i __b) {
163 return (__mmask64)__builtin_ia32_pcmpgtb512_mask((__v64qi)__a, (__v64qi)__b,
164 __u);
165}
166
Pirama Arumuga Nainar4e74a022016-03-17 18:03:02 -0700[diff] [blame]167static __inline__ __mmask64 __DEFAULT_FN_ATTRS
Stephen Hinesb4d9c8b2015-03-30 16:04:04 -0700[diff] [blame]168_mm512_cmpgt_epu8_mask(__m512i __a, __m512i __b) {
169 return (__mmask64)__builtin_ia32_ucmpb512_mask((__v64qi)__a, (__v64qi)__b, 6,
170 (__mmask64)-1);
171}
172
Pirama Arumuga Nainar4e74a022016-03-17 18:03:02 -0700[diff] [blame]173static __inline__ __mmask64 __DEFAULT_FN_ATTRS
Stephen Hinesb4d9c8b2015-03-30 16:04:04 -0700[diff] [blame]174_mm512_mask_cmpgt_epu8_mask(__mmask64 __u, __m512i __a, __m512i __b) {
175 return (__mmask64)__builtin_ia32_ucmpb512_mask((__v64qi)__a, (__v64qi)__b, 6,
176 __u);
177}
178
Pirama Arumuga Nainar4e74a022016-03-17 18:03:02 -0700[diff] [blame]179static __inline__ __mmask32 __DEFAULT_FN_ATTRS
Stephen Hinesb4d9c8b2015-03-30 16:04:04 -0700[diff] [blame]180_mm512_cmpgt_epi16_mask(__m512i __a, __m512i __b) {
181 return (__mmask32)__builtin_ia32_pcmpgtw512_mask((__v32hi)__a, (__v32hi)__b,
182 (__mmask32)-1);
183}
184
Pirama Arumuga Nainar4e74a022016-03-17 18:03:02 -0700[diff] [blame]185static __inline__ __mmask32 __DEFAULT_FN_ATTRS
Stephen Hinesb4d9c8b2015-03-30 16:04:04 -0700[diff] [blame]186_mm512_mask_cmpgt_epi16_mask(__mmask32 __u, __m512i __a, __m512i __b) {
187 return (__mmask32)__builtin_ia32_pcmpgtw512_mask((__v32hi)__a, (__v32hi)__b,
188 __u);
189}
190
Pirama Arumuga Nainar4e74a022016-03-17 18:03:02 -0700[diff] [blame]191static __inline__ __mmask32 __DEFAULT_FN_ATTRS
Stephen Hinesb4d9c8b2015-03-30 16:04:04 -0700[diff] [blame]192_mm512_cmpgt_epu16_mask(__m512i __a, __m512i __b) {
193 return (__mmask32)__builtin_ia32_ucmpw512_mask((__v32hi)__a, (__v32hi)__b, 6,
194 (__mmask32)-1);
195}
196
Pirama Arumuga Nainar4e74a022016-03-17 18:03:02 -0700[diff] [blame]197static __inline__ __mmask32 __DEFAULT_FN_ATTRS
Stephen Hinesb4d9c8b2015-03-30 16:04:04 -0700[diff] [blame]198_mm512_mask_cmpgt_epu16_mask(__mmask32 __u, __m512i __a, __m512i __b) {
199 return (__mmask32)__builtin_ia32_ucmpw512_mask((__v32hi)__a, (__v32hi)__b, 6,
200 __u);
201}
202
Pirama Arumuga Nainar4e74a022016-03-17 18:03:02 -0700[diff] [blame]203static __inline__ __mmask64 __DEFAULT_FN_ATTRS
Stephen Hinesb4d9c8b2015-03-30 16:04:04 -0700[diff] [blame]204_mm512_cmple_epi8_mask(__m512i __a, __m512i __b) {
205 return (__mmask64)__builtin_ia32_cmpb512_mask((__v64qi)__a, (__v64qi)__b, 2,
206 (__mmask64)-1);
207}
208
Pirama Arumuga Nainar4e74a022016-03-17 18:03:02 -0700[diff] [blame]209static __inline__ __mmask64 __DEFAULT_FN_ATTRS
Stephen Hinesb4d9c8b2015-03-30 16:04:04 -0700[diff] [blame]210_mm512_mask_cmple_epi8_mask(__mmask64 __u, __m512i __a, __m512i __b) {
211 return (__mmask64)__builtin_ia32_cmpb512_mask((__v64qi)__a, (__v64qi)__b, 2,
212 __u);
213}
214
Pirama Arumuga Nainar4e74a022016-03-17 18:03:02 -0700[diff] [blame]215static __inline__ __mmask64 __DEFAULT_FN_ATTRS
Stephen Hinesb4d9c8b2015-03-30 16:04:04 -0700[diff] [blame]216_mm512_cmple_epu8_mask(__m512i __a, __m512i __b) {
217 return (__mmask64)__builtin_ia32_ucmpb512_mask((__v64qi)__a, (__v64qi)__b, 2,
218 (__mmask64)-1);
219}
220
Pirama Arumuga Nainar4e74a022016-03-17 18:03:02 -0700[diff] [blame]221static __inline__ __mmask64 __DEFAULT_FN_ATTRS
Stephen Hinesb4d9c8b2015-03-30 16:04:04 -0700[diff] [blame]222_mm512_mask_cmple_epu8_mask(__mmask64 __u, __m512i __a, __m512i __b) {
223 return (__mmask64)__builtin_ia32_ucmpb512_mask((__v64qi)__a, (__v64qi)__b, 2,
224 __u);
225}
226
Pirama Arumuga Nainar4e74a022016-03-17 18:03:02 -0700[diff] [blame]227static __inline__ __mmask32 __DEFAULT_FN_ATTRS
Stephen Hinesb4d9c8b2015-03-30 16:04:04 -0700[diff] [blame]228_mm512_cmple_epi16_mask(__m512i __a, __m512i __b) {
229 return (__mmask32)__builtin_ia32_cmpw512_mask((__v32hi)__a, (__v32hi)__b, 2,
230 (__mmask32)-1);
231}
232
Pirama Arumuga Nainar4e74a022016-03-17 18:03:02 -0700[diff] [blame]233static __inline__ __mmask32 __DEFAULT_FN_ATTRS
Stephen Hinesb4d9c8b2015-03-30 16:04:04 -0700[diff] [blame]234_mm512_mask_cmple_epi16_mask(__mmask32 __u, __m512i __a, __m512i __b) {
235 return (__mmask32)__builtin_ia32_cmpw512_mask((__v32hi)__a, (__v32hi)__b, 2,
236 __u);
237}
238
Pirama Arumuga Nainar4e74a022016-03-17 18:03:02 -0700[diff] [blame]239static __inline__ __mmask32 __DEFAULT_FN_ATTRS
Stephen Hinesb4d9c8b2015-03-30 16:04:04 -0700[diff] [blame]240_mm512_cmple_epu16_mask(__m512i __a, __m512i __b) {
241 return (__mmask32)__builtin_ia32_ucmpw512_mask((__v32hi)__a, (__v32hi)__b, 2,
242 (__mmask32)-1);
243}
244
Pirama Arumuga Nainar4e74a022016-03-17 18:03:02 -0700[diff] [blame]245static __inline__ __mmask32 __DEFAULT_FN_ATTRS
Stephen Hinesb4d9c8b2015-03-30 16:04:04 -0700[diff] [blame]246_mm512_mask_cmple_epu16_mask(__mmask32 __u, __m512i __a, __m512i __b) {
247 return (__mmask32)__builtin_ia32_ucmpw512_mask((__v32hi)__a, (__v32hi)__b, 2,
248 __u);
249}
250
Pirama Arumuga Nainar4e74a022016-03-17 18:03:02 -0700[diff] [blame]251static __inline__ __mmask64 __DEFAULT_FN_ATTRS
Stephen Hinesb4d9c8b2015-03-30 16:04:04 -0700[diff] [blame]252_mm512_cmplt_epi8_mask(__m512i __a, __m512i __b) {
253 return (__mmask64)__builtin_ia32_cmpb512_mask((__v64qi)__a, (__v64qi)__b, 1,
254 (__mmask64)-1);
255}
256
Pirama Arumuga Nainar4e74a022016-03-17 18:03:02 -0700[diff] [blame]257static __inline__ __mmask64 __DEFAULT_FN_ATTRS
Stephen Hinesb4d9c8b2015-03-30 16:04:04 -0700[diff] [blame]258_mm512_mask_cmplt_epi8_mask(__mmask64 __u, __m512i __a, __m512i __b) {
259 return (__mmask64)__builtin_ia32_cmpb512_mask((__v64qi)__a, (__v64qi)__b, 1,
260 __u);
261}
262
Pirama Arumuga Nainar4e74a022016-03-17 18:03:02 -0700[diff] [blame]263static __inline__ __mmask64 __DEFAULT_FN_ATTRS
Stephen Hinesb4d9c8b2015-03-30 16:04:04 -0700[diff] [blame]264_mm512_cmplt_epu8_mask(__m512i __a, __m512i __b) {
265 return (__mmask64)__builtin_ia32_ucmpb512_mask((__v64qi)__a, (__v64qi)__b, 1,
266 (__mmask64)-1);
267}
268
Pirama Arumuga Nainar4e74a022016-03-17 18:03:02 -0700[diff] [blame]269static __inline__ __mmask64 __DEFAULT_FN_ATTRS
Stephen Hinesb4d9c8b2015-03-30 16:04:04 -0700[diff] [blame]270_mm512_mask_cmplt_epu8_mask(__mmask64 __u, __m512i __a, __m512i __b) {
271 return (__mmask64)__builtin_ia32_ucmpb512_mask((__v64qi)__a, (__v64qi)__b, 1,
272 __u);
273}
274
Pirama Arumuga Nainar4e74a022016-03-17 18:03:02 -0700[diff] [blame]275static __inline__ __mmask32 __DEFAULT_FN_ATTRS
Stephen Hinesb4d9c8b2015-03-30 16:04:04 -0700[diff] [blame]276_mm512_cmplt_epi16_mask(__m512i __a, __m512i __b) {
277 return (__mmask32)__builtin_ia32_cmpw512_mask((__v32hi)__a, (__v32hi)__b, 1,
278 (__mmask32)-1);
279}
280
Pirama Arumuga Nainar4e74a022016-03-17 18:03:02 -0700[diff] [blame]281static __inline__ __mmask32 __DEFAULT_FN_ATTRS
Stephen Hinesb4d9c8b2015-03-30 16:04:04 -0700[diff] [blame]282_mm512_mask_cmplt_epi16_mask(__mmask32 __u, __m512i __a, __m512i __b) {
283 return (__mmask32)__builtin_ia32_cmpw512_mask((__v32hi)__a, (__v32hi)__b, 1,
284 __u);
285}
286
Pirama Arumuga Nainar4e74a022016-03-17 18:03:02 -0700[diff] [blame]287static __inline__ __mmask32 __DEFAULT_FN_ATTRS
Stephen Hinesb4d9c8b2015-03-30 16:04:04 -0700[diff] [blame]288_mm512_cmplt_epu16_mask(__m512i __a, __m512i __b) {
289 return (__mmask32)__builtin_ia32_ucmpw512_mask((__v32hi)__a, (__v32hi)__b, 1,
290 (__mmask32)-1);
291}
292
Pirama Arumuga Nainar4e74a022016-03-17 18:03:02 -0700[diff] [blame]293static __inline__ __mmask32 __DEFAULT_FN_ATTRS
Stephen Hinesb4d9c8b2015-03-30 16:04:04 -0700[diff] [blame]294_mm512_mask_cmplt_epu16_mask(__mmask32 __u, __m512i __a, __m512i __b) {
295 return (__mmask32)__builtin_ia32_ucmpw512_mask((__v32hi)__a, (__v32hi)__b, 1,
296 __u);
297}
298
Pirama Arumuga Nainar4e74a022016-03-17 18:03:02 -0700[diff] [blame]299static __inline__ __mmask64 __DEFAULT_FN_ATTRS
Stephen Hinesb4d9c8b2015-03-30 16:04:04 -0700[diff] [blame]300_mm512_cmpneq_epi8_mask(__m512i __a, __m512i __b) {
301 return (__mmask64)__builtin_ia32_cmpb512_mask((__v64qi)__a, (__v64qi)__b, 4,
302 (__mmask64)-1);
303}
304
Pirama Arumuga Nainar4e74a022016-03-17 18:03:02 -0700[diff] [blame]305static __inline__ __mmask64 __DEFAULT_FN_ATTRS
Stephen Hinesb4d9c8b2015-03-30 16:04:04 -0700[diff] [blame]306_mm512_mask_cmpneq_epi8_mask(__mmask64 __u, __m512i __a, __m512i __b) {
307 return (__mmask64)__builtin_ia32_cmpb512_mask((__v64qi)__a, (__v64qi)__b, 4,
308 __u);
309}
310
Pirama Arumuga Nainar4e74a022016-03-17 18:03:02 -0700[diff] [blame]311static __inline__ __mmask64 __DEFAULT_FN_ATTRS
Stephen Hinesb4d9c8b2015-03-30 16:04:04 -0700[diff] [blame]312_mm512_cmpneq_epu8_mask(__m512i __a, __m512i __b) {
313 return (__mmask64)__builtin_ia32_ucmpb512_mask((__v64qi)__a, (__v64qi)__b, 4,
314 (__mmask64)-1);
315}
316
Pirama Arumuga Nainar4e74a022016-03-17 18:03:02 -0700[diff] [blame]317static __inline__ __mmask64 __DEFAULT_FN_ATTRS
Stephen Hinesb4d9c8b2015-03-30 16:04:04 -0700[diff] [blame]318_mm512_mask_cmpneq_epu8_mask(__mmask64 __u, __m512i __a, __m512i __b) {
319 return (__mmask64)__builtin_ia32_ucmpb512_mask((__v64qi)__a, (__v64qi)__b, 4,
320 __u);
321}
322
Pirama Arumuga Nainar4e74a022016-03-17 18:03:02 -0700[diff] [blame]323static __inline__ __mmask32 __DEFAULT_FN_ATTRS
Stephen Hinesb4d9c8b2015-03-30 16:04:04 -0700[diff] [blame]324_mm512_cmpneq_epi16_mask(__m512i __a, __m512i __b) {
325 return (__mmask32)__builtin_ia32_cmpw512_mask((__v32hi)__a, (__v32hi)__b, 4,
326 (__mmask32)-1);
327}
328
Pirama Arumuga Nainar4e74a022016-03-17 18:03:02 -0700[diff] [blame]329static __inline__ __mmask32 __DEFAULT_FN_ATTRS
Stephen Hinesb4d9c8b2015-03-30 16:04:04 -0700[diff] [blame]330_mm512_mask_cmpneq_epi16_mask(__mmask32 __u, __m512i __a, __m512i __b) {
331 return (__mmask32)__builtin_ia32_cmpw512_mask((__v32hi)__a, (__v32hi)__b, 4,
332 __u);
333}
334
Pirama Arumuga Nainar4e74a022016-03-17 18:03:02 -0700[diff] [blame]335static __inline__ __mmask32 __DEFAULT_FN_ATTRS
Stephen Hinesb4d9c8b2015-03-30 16:04:04 -0700[diff] [blame]336_mm512_cmpneq_epu16_mask(__m512i __a, __m512i __b) {
337 return (__mmask32)__builtin_ia32_ucmpw512_mask((__v32hi)__a, (__v32hi)__b, 4,
338 (__mmask32)-1);
339}
340
Pirama Arumuga Nainar4e74a022016-03-17 18:03:02 -0700[diff] [blame]341static __inline__ __mmask32 __DEFAULT_FN_ATTRS
Stephen Hinesb4d9c8b2015-03-30 16:04:04 -0700[diff] [blame]342_mm512_mask_cmpneq_epu16_mask(__mmask32 __u, __m512i __a, __m512i __b) {
343 return (__mmask32)__builtin_ia32_ucmpw512_mask((__v32hi)__a, (__v32hi)__b, 4,
344 __u);
345}
346
Pirama Arumuga Nainar4e74a022016-03-17 18:03:02 -0700[diff] [blame]347static __inline__ __m512i __DEFAULT_FN_ATTRS
Stephen Hines28c5e1e2015-08-13 18:18:46 -0700[diff] [blame]348_mm512_add_epi8 (__m512i __A, __m512i __B) {
Pirama Arumuga Nainarbb4374f2016-10-20 16:43:03 -0700[diff] [blame]349 return (__m512i) ((__v64qu) __A + (__v64qu) __B);
Stephen Hines28c5e1e2015-08-13 18:18:46 -0700[diff] [blame]350}
351
Pirama Arumuga Nainar4e74a022016-03-17 18:03:02 -0700[diff] [blame]352static __inline__ __m512i __DEFAULT_FN_ATTRS
Stephen Hines28c5e1e2015-08-13 18:18:46 -0700[diff] [blame]353_mm512_mask_add_epi8 (__m512i __W, __mmask64 __U, __m512i __A, __m512i __B) {
354 return (__m512i) __builtin_ia32_paddb512_mask ((__v64qi) __A,
355 (__v64qi) __B,
356 (__v64qi) __W,
357 (__mmask64) __U);
358}
359
Pirama Arumuga Nainar4e74a022016-03-17 18:03:02 -0700[diff] [blame]360static __inline__ __m512i __DEFAULT_FN_ATTRS
Stephen Hines28c5e1e2015-08-13 18:18:46 -0700[diff] [blame]361_mm512_maskz_add_epi8 (__mmask64 __U, __m512i __A, __m512i __B) {
362 return (__m512i) __builtin_ia32_paddb512_mask ((__v64qi) __A,
363 (__v64qi) __B,
Pirama Arumuga Nainar4e74a022016-03-17 18:03:02 -0700[diff] [blame]364 (__v64qi) _mm512_setzero_qi(),
Stephen Hines28c5e1e2015-08-13 18:18:46 -0700[diff] [blame]365 (__mmask64) __U);
366}
367
Pirama Arumuga Nainar4e74a022016-03-17 18:03:02 -0700[diff] [blame]368static __inline__ __m512i __DEFAULT_FN_ATTRS
Stephen Hines28c5e1e2015-08-13 18:18:46 -0700[diff] [blame]369_mm512_sub_epi8 (__m512i __A, __m512i __B) {
Pirama Arumuga Nainarbb4374f2016-10-20 16:43:03 -0700[diff] [blame]370 return (__m512i) ((__v64qu) __A - (__v64qu) __B);
Stephen Hines28c5e1e2015-08-13 18:18:46 -0700[diff] [blame]371}
372
Pirama Arumuga Nainar4e74a022016-03-17 18:03:02 -0700[diff] [blame]373static __inline__ __m512i __DEFAULT_FN_ATTRS
Stephen Hines28c5e1e2015-08-13 18:18:46 -0700[diff] [blame]374_mm512_mask_sub_epi8 (__m512i __W, __mmask64 __U, __m512i __A, __m512i __B) {
375 return (__m512i) __builtin_ia32_psubb512_mask ((__v64qi) __A,
376 (__v64qi) __B,
377 (__v64qi) __W,
378 (__mmask64) __U);
379}
380
Pirama Arumuga Nainar4e74a022016-03-17 18:03:02 -0700[diff] [blame]381static __inline__ __m512i __DEFAULT_FN_ATTRS
Stephen Hines28c5e1e2015-08-13 18:18:46 -0700[diff] [blame]382_mm512_maskz_sub_epi8 (__mmask64 __U, __m512i __A, __m512i __B) {
383 return (__m512i) __builtin_ia32_psubb512_mask ((__v64qi) __A,
384 (__v64qi) __B,
Pirama Arumuga Nainar4e74a022016-03-17 18:03:02 -0700[diff] [blame]385 (__v64qi) _mm512_setzero_qi(),
Stephen Hines28c5e1e2015-08-13 18:18:46 -0700[diff] [blame]386 (__mmask64) __U);
387}
388
Pirama Arumuga Nainar4e74a022016-03-17 18:03:02 -0700[diff] [blame]389static __inline__ __m512i __DEFAULT_FN_ATTRS
Stephen Hines28c5e1e2015-08-13 18:18:46 -0700[diff] [blame]390_mm512_add_epi16 (__m512i __A, __m512i __B) {
Pirama Arumuga Nainarbb4374f2016-10-20 16:43:03 -0700[diff] [blame]391 return (__m512i) ((__v32hu) __A + (__v32hu) __B);
Stephen Hines28c5e1e2015-08-13 18:18:46 -0700[diff] [blame]392}
393
Pirama Arumuga Nainar4e74a022016-03-17 18:03:02 -0700[diff] [blame]394static __inline__ __m512i __DEFAULT_FN_ATTRS
Stephen Hines28c5e1e2015-08-13 18:18:46 -0700[diff] [blame]395_mm512_mask_add_epi16 (__m512i __W, __mmask32 __U, __m512i __A, __m512i __B) {
396 return (__m512i) __builtin_ia32_paddw512_mask ((__v32hi) __A,
397 (__v32hi) __B,
398 (__v32hi) __W,
399 (__mmask32) __U);
400}
401
Pirama Arumuga Nainar4e74a022016-03-17 18:03:02 -0700[diff] [blame]402static __inline__ __m512i __DEFAULT_FN_ATTRS
Stephen Hines28c5e1e2015-08-13 18:18:46 -0700[diff] [blame]403_mm512_maskz_add_epi16 (__mmask32 __U, __m512i __A, __m512i __B) {
404 return (__m512i) __builtin_ia32_paddw512_mask ((__v32hi) __A,
405 (__v32hi) __B,
Pirama Arumuga Nainar4e74a022016-03-17 18:03:02 -0700[diff] [blame]406 (__v32hi) _mm512_setzero_hi(),
Stephen Hines28c5e1e2015-08-13 18:18:46 -0700[diff] [blame]407 (__mmask32) __U);
408}
409
Pirama Arumuga Nainar4e74a022016-03-17 18:03:02 -0700[diff] [blame]410static __inline__ __m512i __DEFAULT_FN_ATTRS
Stephen Hines28c5e1e2015-08-13 18:18:46 -0700[diff] [blame]411_mm512_sub_epi16 (__m512i __A, __m512i __B) {
Pirama Arumuga Nainarbb4374f2016-10-20 16:43:03 -0700[diff] [blame]412 return (__m512i) ((__v32hu) __A - (__v32hu) __B);
Stephen Hines28c5e1e2015-08-13 18:18:46 -0700[diff] [blame]413}
414
Pirama Arumuga Nainar4e74a022016-03-17 18:03:02 -0700[diff] [blame]415static __inline__ __m512i __DEFAULT_FN_ATTRS
Stephen Hines28c5e1e2015-08-13 18:18:46 -0700[diff] [blame]416_mm512_mask_sub_epi16 (__m512i __W, __mmask32 __U, __m512i __A, __m512i __B) {
417 return (__m512i) __builtin_ia32_psubw512_mask ((__v32hi) __A,
418 (__v32hi) __B,
419 (__v32hi) __W,
420 (__mmask32) __U);
421}
422
Pirama Arumuga Nainar4e74a022016-03-17 18:03:02 -0700[diff] [blame]423static __inline__ __m512i __DEFAULT_FN_ATTRS
Stephen Hines28c5e1e2015-08-13 18:18:46 -0700[diff] [blame]424_mm512_maskz_sub_epi16 (__mmask32 __U, __m512i __A, __m512i __B) {
425 return (__m512i) __builtin_ia32_psubw512_mask ((__v32hi) __A,
426 (__v32hi) __B,
Pirama Arumuga Nainar4e74a022016-03-17 18:03:02 -0700[diff] [blame]427 (__v32hi) _mm512_setzero_hi(),
Stephen Hines28c5e1e2015-08-13 18:18:46 -0700[diff] [blame]428 (__mmask32) __U);
429}
430
Pirama Arumuga Nainar4e74a022016-03-17 18:03:02 -0700[diff] [blame]431static __inline__ __m512i __DEFAULT_FN_ATTRS
Stephen Hines28c5e1e2015-08-13 18:18:46 -0700[diff] [blame]432_mm512_mullo_epi16 (__m512i __A, __m512i __B) {
Pirama Arumuga Nainarbb4374f2016-10-20 16:43:03 -0700[diff] [blame]433 return (__m512i) ((__v32hu) __A * (__v32hu) __B);
Stephen Hines28c5e1e2015-08-13 18:18:46 -0700[diff] [blame]434}
435
Pirama Arumuga Nainar4e74a022016-03-17 18:03:02 -0700[diff] [blame]436static __inline__ __m512i __DEFAULT_FN_ATTRS
Stephen Hines28c5e1e2015-08-13 18:18:46 -0700[diff] [blame]437_mm512_mask_mullo_epi16 (__m512i __W, __mmask32 __U, __m512i __A, __m512i __B) {
438 return (__m512i) __builtin_ia32_pmullw512_mask ((__v32hi) __A,
439 (__v32hi) __B,
440 (__v32hi) __W,
441 (__mmask32) __U);
442}
443
Pirama Arumuga Nainar4e74a022016-03-17 18:03:02 -0700[diff] [blame]444static __inline__ __m512i __DEFAULT_FN_ATTRS
Stephen Hines28c5e1e2015-08-13 18:18:46 -0700[diff] [blame]445_mm512_maskz_mullo_epi16 (__mmask32 __U, __m512i __A, __m512i __B) {
446 return (__m512i) __builtin_ia32_pmullw512_mask ((__v32hi) __A,
447 (__v32hi) __B,
Pirama Arumuga Nainar4e74a022016-03-17 18:03:02 -0700[diff] [blame]448 (__v32hi) _mm512_setzero_hi(),
Stephen Hines28c5e1e2015-08-13 18:18:46 -0700[diff] [blame]449 (__mmask32) __U);
450}
451
Pirama Arumuga Nainar4e74a022016-03-17 18:03:02 -0700[diff] [blame]452static __inline__ __m512i __DEFAULT_FN_ATTRS
453_mm512_mask_blend_epi8 (__mmask64 __U, __m512i __A, __m512i __W)
454{
Pirama Arumuga Nainarbb4374f2016-10-20 16:43:03 -0700[diff] [blame]455 return (__m512i) __builtin_ia32_selectb_512 ((__mmask64) __U,
Pirama Arumuga Nainar4e74a022016-03-17 18:03:02 -0700[diff] [blame]456 (__v64qi) __W,
Pirama Arumuga Nainarbb4374f2016-10-20 16:43:03 -0700[diff] [blame]457 (__v64qi) __A);
Pirama Arumuga Nainar4e74a022016-03-17 18:03:02 -0700[diff] [blame]458}
459
460static __inline__ __m512i __DEFAULT_FN_ATTRS
461_mm512_mask_blend_epi16 (__mmask32 __U, __m512i __A, __m512i __W)
462{
Pirama Arumuga Nainarbb4374f2016-10-20 16:43:03 -0700[diff] [blame]463 return (__m512i) __builtin_ia32_selectw_512 ((__mmask32) __U,
Pirama Arumuga Nainar4e74a022016-03-17 18:03:02 -0700[diff] [blame]464 (__v32hi) __W,
Pirama Arumuga Nainarbb4374f2016-10-20 16:43:03 -0700[diff] [blame]465 (__v32hi) __A);
Pirama Arumuga Nainar4e74a022016-03-17 18:03:02 -0700[diff] [blame]466}
467
468static __inline__ __m512i __DEFAULT_FN_ATTRS
469_mm512_abs_epi8 (__m512i __A)
470{
471 return (__m512i) __builtin_ia32_pabsb512_mask ((__v64qi) __A,
472 (__v64qi) _mm512_setzero_qi(),
473 (__mmask64) -1);
474}
475
476static __inline__ __m512i __DEFAULT_FN_ATTRS
477_mm512_mask_abs_epi8 (__m512i __W, __mmask64 __U, __m512i __A)
478{
479 return (__m512i) __builtin_ia32_pabsb512_mask ((__v64qi) __A,
480 (__v64qi) __W,
481 (__mmask64) __U);
482}
483
484static __inline__ __m512i __DEFAULT_FN_ATTRS
485_mm512_maskz_abs_epi8 (__mmask64 __U, __m512i __A)
486{
487 return (__m512i) __builtin_ia32_pabsb512_mask ((__v64qi) __A,
488 (__v64qi) _mm512_setzero_qi(),
489 (__mmask64) __U);
490}
491
492static __inline__ __m512i __DEFAULT_FN_ATTRS
493_mm512_abs_epi16 (__m512i __A)
494{
495 return (__m512i) __builtin_ia32_pabsw512_mask ((__v32hi) __A,
496 (__v32hi) _mm512_setzero_hi(),
497 (__mmask32) -1);
498}
499
500static __inline__ __m512i __DEFAULT_FN_ATTRS
501_mm512_mask_abs_epi16 (__m512i __W, __mmask32 __U, __m512i __A)
502{
503 return (__m512i) __builtin_ia32_pabsw512_mask ((__v32hi) __A,
504 (__v32hi) __W,
505 (__mmask32) __U);
506}
507
508static __inline__ __m512i __DEFAULT_FN_ATTRS
509_mm512_maskz_abs_epi16 (__mmask32 __U, __m512i __A)
510{
511 return (__m512i) __builtin_ia32_pabsw512_mask ((__v32hi) __A,
512 (__v32hi) _mm512_setzero_hi(),
513 (__mmask32) __U);
514}
515
516static __inline__ __m512i __DEFAULT_FN_ATTRS
517_mm512_packs_epi32 (__m512i __A, __m512i __B)
518{
519 return (__m512i) __builtin_ia32_packssdw512_mask ((__v16si) __A,
520 (__v16si) __B,
521 (__v32hi) _mm512_setzero_hi(),
522 (__mmask32) -1);
523}
524
525static __inline__ __m512i __DEFAULT_FN_ATTRS
526_mm512_maskz_packs_epi32 (__mmask32 __M, __m512i __A, __m512i __B)
527{
528 return (__m512i) __builtin_ia32_packssdw512_mask ((__v16si) __A,
529 (__v16si) __B,
530 (__v32hi) _mm512_setzero_hi(),
531 __M);
532}
533
534static __inline__ __m512i __DEFAULT_FN_ATTRS
535_mm512_mask_packs_epi32 (__m512i __W, __mmask32 __M, __m512i __A,
536 __m512i __B)
537{
538 return (__m512i) __builtin_ia32_packssdw512_mask ((__v16si) __A,
539 (__v16si) __B,
540 (__v32hi) __W,
541 __M);
542}
543
544static __inline__ __m512i __DEFAULT_FN_ATTRS
545_mm512_packs_epi16 (__m512i __A, __m512i __B)
546{
547 return (__m512i) __builtin_ia32_packsswb512_mask ((__v32hi) __A,
548 (__v32hi) __B,
549 (__v64qi) _mm512_setzero_qi(),
550 (__mmask64) -1);
551}
552
553static __inline__ __m512i __DEFAULT_FN_ATTRS
554_mm512_mask_packs_epi16 (__m512i __W, __mmask64 __M, __m512i __A,
555 __m512i __B)
556{
557 return (__m512i) __builtin_ia32_packsswb512_mask ((__v32hi) __A,
558 (__v32hi) __B,
559 (__v64qi) __W,
560 (__mmask64) __M);
561}
562
563static __inline__ __m512i __DEFAULT_FN_ATTRS
564_mm512_maskz_packs_epi16 (__mmask64 __M, __m512i __A, __m512i __B)
565{
566 return (__m512i) __builtin_ia32_packsswb512_mask ((__v32hi) __A,
567 (__v32hi) __B,
568 (__v64qi) _mm512_setzero_qi(),
569 __M);
570}
571
572static __inline__ __m512i __DEFAULT_FN_ATTRS
573_mm512_packus_epi32 (__m512i __A, __m512i __B)
574{
575 return (__m512i) __builtin_ia32_packusdw512_mask ((__v16si) __A,
576 (__v16si) __B,
577 (__v32hi) _mm512_setzero_hi(),
578 (__mmask32) -1);
579}
580
581static __inline__ __m512i __DEFAULT_FN_ATTRS
582_mm512_maskz_packus_epi32 (__mmask32 __M, __m512i __A, __m512i __B)
583{
584 return (__m512i) __builtin_ia32_packusdw512_mask ((__v16si) __A,
585 (__v16si) __B,
586 (__v32hi) _mm512_setzero_hi(),
587 __M);
588}
589
590static __inline__ __m512i __DEFAULT_FN_ATTRS
591_mm512_mask_packus_epi32 (__m512i __W, __mmask32 __M, __m512i __A,
592 __m512i __B)
593{
594 return (__m512i) __builtin_ia32_packusdw512_mask ((__v16si) __A,
595 (__v16si) __B,
596 (__v32hi) __W,
597 __M);
598}
599
600static __inline__ __m512i __DEFAULT_FN_ATTRS
601_mm512_packus_epi16 (__m512i __A, __m512i __B)
602{
603 return (__m512i) __builtin_ia32_packuswb512_mask ((__v32hi) __A,
604 (__v32hi) __B,
605 (__v64qi) _mm512_setzero_qi(),
606 (__mmask64) -1);
607}
608
609static __inline__ __m512i __DEFAULT_FN_ATTRS
610_mm512_mask_packus_epi16 (__m512i __W, __mmask64 __M, __m512i __A,
611 __m512i __B)
612{
613 return (__m512i) __builtin_ia32_packuswb512_mask ((__v32hi) __A,
614 (__v32hi) __B,
615 (__v64qi) __W,
616 (__mmask64) __M);
617}
618
619static __inline__ __m512i __DEFAULT_FN_ATTRS
620_mm512_maskz_packus_epi16 (__mmask64 __M, __m512i __A, __m512i __B)
621{
622 return (__m512i) __builtin_ia32_packuswb512_mask ((__v32hi) __A,
623 (__v32hi) __B,
624 (__v64qi) _mm512_setzero_qi(),
625 (__mmask64) __M);
626}
627
628static __inline__ __m512i __DEFAULT_FN_ATTRS
629_mm512_adds_epi8 (__m512i __A, __m512i __B)
630{
631 return (__m512i) __builtin_ia32_paddsb512_mask ((__v64qi) __A,
632 (__v64qi) __B,
633 (__v64qi) _mm512_setzero_qi(),
634 (__mmask64) -1);
635}
636
637static __inline__ __m512i __DEFAULT_FN_ATTRS
638_mm512_mask_adds_epi8 (__m512i __W, __mmask64 __U, __m512i __A,
639 __m512i __B)
640{
641 return (__m512i) __builtin_ia32_paddsb512_mask ((__v64qi) __A,
642 (__v64qi) __B,
643 (__v64qi) __W,
644 (__mmask64) __U);
645}
646
647static __inline__ __m512i __DEFAULT_FN_ATTRS
648_mm512_maskz_adds_epi8 (__mmask64 __U, __m512i __A, __m512i __B)
649{
650 return (__m512i) __builtin_ia32_paddsb512_mask ((__v64qi) __A,
651 (__v64qi) __B,
652 (__v64qi) _mm512_setzero_qi(),
653 (__mmask64) __U);
654}
655
656static __inline__ __m512i __DEFAULT_FN_ATTRS
657_mm512_adds_epi16 (__m512i __A, __m512i __B)
658{
659 return (__m512i) __builtin_ia32_paddsw512_mask ((__v32hi) __A,
660 (__v32hi) __B,
661 (__v32hi) _mm512_setzero_hi(),
662 (__mmask32) -1);
663}
664
665static __inline__ __m512i __DEFAULT_FN_ATTRS
666_mm512_mask_adds_epi16 (__m512i __W, __mmask32 __U, __m512i __A,
667 __m512i __B)
668{
669 return (__m512i) __builtin_ia32_paddsw512_mask ((__v32hi) __A,
670 (__v32hi) __B,
671 (__v32hi) __W,
672 (__mmask32) __U);
673}
674
675static __inline__ __m512i __DEFAULT_FN_ATTRS
676_mm512_maskz_adds_epi16 (__mmask32 __U, __m512i __A, __m512i __B)
677{
678 return (__m512i) __builtin_ia32_paddsw512_mask ((__v32hi) __A,
679 (__v32hi) __B,
680 (__v32hi) _mm512_setzero_hi(),
681 (__mmask32) __U);
682}
683
684static __inline__ __m512i __DEFAULT_FN_ATTRS
685_mm512_adds_epu8 (__m512i __A, __m512i __B)
686{
687 return (__m512i) __builtin_ia32_paddusb512_mask ((__v64qi) __A,
688 (__v64qi) __B,
689 (__v64qi) _mm512_setzero_qi(),
690 (__mmask64) -1);
691}
692
693static __inline__ __m512i __DEFAULT_FN_ATTRS
694_mm512_mask_adds_epu8 (__m512i __W, __mmask64 __U, __m512i __A,
695 __m512i __B)
696{
697 return (__m512i) __builtin_ia32_paddusb512_mask ((__v64qi) __A,
698 (__v64qi) __B,
699 (__v64qi) __W,
700 (__mmask64) __U);
701}
702
703static __inline__ __m512i __DEFAULT_FN_ATTRS
704_mm512_maskz_adds_epu8 (__mmask64 __U, __m512i __A, __m512i __B)
705{
706 return (__m512i) __builtin_ia32_paddusb512_mask ((__v64qi) __A,
707 (__v64qi) __B,
708 (__v64qi) _mm512_setzero_qi(),
709 (__mmask64) __U);
710}
711
712static __inline__ __m512i __DEFAULT_FN_ATTRS
713_mm512_adds_epu16 (__m512i __A, __m512i __B)
714{
715 return (__m512i) __builtin_ia32_paddusw512_mask ((__v32hi) __A,
716 (__v32hi) __B,
717 (__v32hi) _mm512_setzero_hi(),
718 (__mmask32) -1);
719}
720
721static __inline__ __m512i __DEFAULT_FN_ATTRS
722_mm512_mask_adds_epu16 (__m512i __W, __mmask32 __U, __m512i __A,
723 __m512i __B)
724{
725 return (__m512i) __builtin_ia32_paddusw512_mask ((__v32hi) __A,
726 (__v32hi) __B,
727 (__v32hi) __W,
728 (__mmask32) __U);
729}
730
731static __inline__ __m512i __DEFAULT_FN_ATTRS
732_mm512_maskz_adds_epu16 (__mmask32 __U, __m512i __A, __m512i __B)
733{
734 return (__m512i) __builtin_ia32_paddusw512_mask ((__v32hi) __A,
735 (__v32hi) __B,
736 (__v32hi) _mm512_setzero_hi(),
737 (__mmask32) __U);
738}
739
740static __inline__ __m512i __DEFAULT_FN_ATTRS
741_mm512_avg_epu8 (__m512i __A, __m512i __B)
742{
743 return (__m512i) __builtin_ia32_pavgb512_mask ((__v64qi) __A,
744 (__v64qi) __B,
745 (__v64qi) _mm512_setzero_qi(),
746 (__mmask64) -1);
747}
748
749static __inline__ __m512i __DEFAULT_FN_ATTRS
750_mm512_mask_avg_epu8 (__m512i __W, __mmask64 __U, __m512i __A,
751 __m512i __B)
752{
753 return (__m512i) __builtin_ia32_pavgb512_mask ((__v64qi) __A,
754 (__v64qi) __B,
755 (__v64qi) __W,
756 (__mmask64) __U);
757}
758
759static __inline__ __m512i __DEFAULT_FN_ATTRS
760_mm512_maskz_avg_epu8 (__mmask64 __U, __m512i __A, __m512i __B)
761{
762 return (__m512i) __builtin_ia32_pavgb512_mask ((__v64qi) __A,
763 (__v64qi) __B,
764 (__v64qi) _mm512_setzero_qi(),
765 (__mmask64) __U);
766}
767
768static __inline__ __m512i __DEFAULT_FN_ATTRS
769_mm512_avg_epu16 (__m512i __A, __m512i __B)
770{
771 return (__m512i) __builtin_ia32_pavgw512_mask ((__v32hi) __A,
772 (__v32hi) __B,
773 (__v32hi) _mm512_setzero_hi(),
774 (__mmask32) -1);
775}
776
777static __inline__ __m512i __DEFAULT_FN_ATTRS
778_mm512_mask_avg_epu16 (__m512i __W, __mmask32 __U, __m512i __A,
779 __m512i __B)
780{
781 return (__m512i) __builtin_ia32_pavgw512_mask ((__v32hi) __A,
782 (__v32hi) __B,
783 (__v32hi) __W,
784 (__mmask32) __U);
785}
786
787static __inline__ __m512i __DEFAULT_FN_ATTRS
788_mm512_maskz_avg_epu16 (__mmask32 __U, __m512i __A, __m512i __B)
789{
790 return (__m512i) __builtin_ia32_pavgw512_mask ((__v32hi) __A,
791 (__v32hi) __B,
792 (__v32hi) _mm512_setzero_hi(),
793 (__mmask32) __U);
794}
795
796static __inline__ __m512i __DEFAULT_FN_ATTRS
797_mm512_max_epi8 (__m512i __A, __m512i __B)
798{
799 return (__m512i) __builtin_ia32_pmaxsb512_mask ((__v64qi) __A,
800 (__v64qi) __B,
801 (__v64qi) _mm512_setzero_qi(),
802 (__mmask64) -1);
803}
804
805static __inline__ __m512i __DEFAULT_FN_ATTRS
806_mm512_maskz_max_epi8 (__mmask64 __M, __m512i __A, __m512i __B)
807{
808 return (__m512i) __builtin_ia32_pmaxsb512_mask ((__v64qi) __A,
809 (__v64qi) __B,
810 (__v64qi) _mm512_setzero_qi(),
811 (__mmask64) __M);
812}
813
814static __inline__ __m512i __DEFAULT_FN_ATTRS
815_mm512_mask_max_epi8 (__m512i __W, __mmask64 __M, __m512i __A,
816 __m512i __B)
817{
818 return (__m512i) __builtin_ia32_pmaxsb512_mask ((__v64qi) __A,
819 (__v64qi) __B,
820 (__v64qi) __W,
821 (__mmask64) __M);
822}
823
824static __inline__ __m512i __DEFAULT_FN_ATTRS
825_mm512_max_epi16 (__m512i __A, __m512i __B)
826{
827 return (__m512i) __builtin_ia32_pmaxsw512_mask ((__v32hi) __A,
828 (__v32hi) __B,
829 (__v32hi) _mm512_setzero_hi(),
830 (__mmask32) -1);
831}
832
833static __inline__ __m512i __DEFAULT_FN_ATTRS
834_mm512_maskz_max_epi16 (__mmask32 __M, __m512i __A, __m512i __B)
835{
836 return (__m512i) __builtin_ia32_pmaxsw512_mask ((__v32hi) __A,
837 (__v32hi) __B,
838 (__v32hi) _mm512_setzero_hi(),
839 (__mmask32) __M);
840}
841
842static __inline__ __m512i __DEFAULT_FN_ATTRS
843_mm512_mask_max_epi16 (__m512i __W, __mmask32 __M, __m512i __A,
844 __m512i __B)
845{
846 return (__m512i) __builtin_ia32_pmaxsw512_mask ((__v32hi) __A,
847 (__v32hi) __B,
848 (__v32hi) __W,
849 (__mmask32) __M);
850}
851
852static __inline__ __m512i __DEFAULT_FN_ATTRS
853_mm512_max_epu8 (__m512i __A, __m512i __B)
854{
855 return (__m512i) __builtin_ia32_pmaxub512_mask ((__v64qi) __A,
856 (__v64qi) __B,
857 (__v64qi) _mm512_setzero_qi(),
858 (__mmask64) -1);
859}
860
861static __inline__ __m512i __DEFAULT_FN_ATTRS
862_mm512_maskz_max_epu8 (__mmask64 __M, __m512i __A, __m512i __B)
863{
864 return (__m512i) __builtin_ia32_pmaxub512_mask ((__v64qi) __A,
865 (__v64qi) __B,
866 (__v64qi) _mm512_setzero_qi(),
867 (__mmask64) __M);
868}
869
870static __inline__ __m512i __DEFAULT_FN_ATTRS
871_mm512_mask_max_epu8 (__m512i __W, __mmask64 __M, __m512i __A,
872 __m512i __B)
873{
874 return (__m512i) __builtin_ia32_pmaxub512_mask ((__v64qi) __A,
875 (__v64qi) __B,
876 (__v64qi) __W,
877 (__mmask64) __M);
878}
879
880static __inline__ __m512i __DEFAULT_FN_ATTRS
881_mm512_max_epu16 (__m512i __A, __m512i __B)
882{
883 return (__m512i) __builtin_ia32_pmaxuw512_mask ((__v32hi) __A,
884 (__v32hi) __B,
885 (__v32hi) _mm512_setzero_hi(),
886 (__mmask32) -1);
887}
888
889static __inline__ __m512i __DEFAULT_FN_ATTRS
890_mm512_maskz_max_epu16 (__mmask32 __M, __m512i __A, __m512i __B)
891{
892 return (__m512i) __builtin_ia32_pmaxuw512_mask ((__v32hi) __A,
893 (__v32hi) __B,
894 (__v32hi) _mm512_setzero_hi(),
895 (__mmask32) __M);
896}
897
898static __inline__ __m512i __DEFAULT_FN_ATTRS
899_mm512_mask_max_epu16 (__m512i __W, __mmask32 __M, __m512i __A,
900 __m512i __B)
901{
902 return (__m512i) __builtin_ia32_pmaxuw512_mask ((__v32hi) __A,
903 (__v32hi) __B,
904 (__v32hi) __W,
905 (__mmask32) __M);
906}
907
908static __inline__ __m512i __DEFAULT_FN_ATTRS
909_mm512_min_epi8 (__m512i __A, __m512i __B)
910{
911 return (__m512i) __builtin_ia32_pminsb512_mask ((__v64qi) __A,
912 (__v64qi) __B,
913 (__v64qi) _mm512_setzero_qi(),
914 (__mmask64) -1);
915}
916
917static __inline__ __m512i __DEFAULT_FN_ATTRS
918_mm512_maskz_min_epi8 (__mmask64 __M, __m512i __A, __m512i __B)
919{
920 return (__m512i) __builtin_ia32_pminsb512_mask ((__v64qi) __A,
921 (__v64qi) __B,
922 (__v64qi) _mm512_setzero_qi(),
923 (__mmask64) __M);
924}
925
926static __inline__ __m512i __DEFAULT_FN_ATTRS
927_mm512_mask_min_epi8 (__m512i __W, __mmask64 __M, __m512i __A,
928 __m512i __B)
929{
930 return (__m512i) __builtin_ia32_pminsb512_mask ((__v64qi) __A,
931 (__v64qi) __B,
932 (__v64qi) __W,
933 (__mmask64) __M);
934}
935
936static __inline__ __m512i __DEFAULT_FN_ATTRS
937_mm512_min_epi16 (__m512i __A, __m512i __B)
938{
939 return (__m512i) __builtin_ia32_pminsw512_mask ((__v32hi) __A,
940 (__v32hi) __B,
941 (__v32hi) _mm512_setzero_hi(),
942 (__mmask32) -1);
943}
944
945static __inline__ __m512i __DEFAULT_FN_ATTRS
946_mm512_maskz_min_epi16 (__mmask32 __M, __m512i __A, __m512i __B)
947{
948 return (__m512i) __builtin_ia32_pminsw512_mask ((__v32hi) __A,
949 (__v32hi) __B,
950 (__v32hi) _mm512_setzero_hi(),
951 (__mmask32) __M);
952}
953
954static __inline__ __m512i __DEFAULT_FN_ATTRS
955_mm512_mask_min_epi16 (__m512i __W, __mmask32 __M, __m512i __A,
956 __m512i __B)
957{
958 return (__m512i) __builtin_ia32_pminsw512_mask ((__v32hi) __A,
959 (__v32hi) __B,
960 (__v32hi) __W,
961 (__mmask32) __M);
962}
963
964static __inline__ __m512i __DEFAULT_FN_ATTRS
965_mm512_min_epu8 (__m512i __A, __m512i __B)
966{
967 return (__m512i) __builtin_ia32_pminub512_mask ((__v64qi) __A,
968 (__v64qi) __B,
969 (__v64qi) _mm512_setzero_qi(),
970 (__mmask64) -1);
971}
972
973static __inline__ __m512i __DEFAULT_FN_ATTRS
974_mm512_maskz_min_epu8 (__mmask64 __M, __m512i __A, __m512i __B)
975{
976 return (__m512i) __builtin_ia32_pminub512_mask ((__v64qi) __A,
977 (__v64qi) __B,
978 (__v64qi) _mm512_setzero_qi(),
979 (__mmask64) __M);
980}
981
982static __inline__ __m512i __DEFAULT_FN_ATTRS
983_mm512_mask_min_epu8 (__m512i __W, __mmask64 __M, __m512i __A,
984 __m512i __B)
985{
986 return (__m512i) __builtin_ia32_pminub512_mask ((__v64qi) __A,
987 (__v64qi) __B,
988 (__v64qi) __W,
989 (__mmask64) __M);
990}
991
992static __inline__ __m512i __DEFAULT_FN_ATTRS
993_mm512_min_epu16 (__m512i __A, __m512i __B)
994{
995 return (__m512i) __builtin_ia32_pminuw512_mask ((__v32hi) __A,
996 (__v32hi) __B,
997 (__v32hi) _mm512_setzero_hi(),
998 (__mmask32) -1);
999}
1000
1001static __inline__ __m512i __DEFAULT_FN_ATTRS
1002_mm512_maskz_min_epu16 (__mmask32 __M, __m512i __A, __m512i __B)
1003{
1004 return (__m512i) __builtin_ia32_pminuw512_mask ((__v32hi) __A,
1005 (__v32hi) __B,
1006 (__v32hi) _mm512_setzero_hi(),
1007 (__mmask32) __M);
1008}
1009
1010static __inline__ __m512i __DEFAULT_FN_ATTRS
1011_mm512_mask_min_epu16 (__m512i __W, __mmask32 __M, __m512i __A,
1012 __m512i __B)
1013{
1014 return (__m512i) __builtin_ia32_pminuw512_mask ((__v32hi) __A,
1015 (__v32hi) __B,
1016 (__v32hi) __W,
1017 (__mmask32) __M);
1018}
1019
1020static __inline__ __m512i __DEFAULT_FN_ATTRS
1021_mm512_shuffle_epi8 (__m512i __A, __m512i __B)
1022{
1023 return (__m512i) __builtin_ia32_pshufb512_mask ((__v64qi) __A,
1024 (__v64qi) __B,
1025 (__v64qi) _mm512_setzero_qi(),
1026 (__mmask64) -1);
1027}
1028
1029static __inline__ __m512i __DEFAULT_FN_ATTRS
1030_mm512_mask_shuffle_epi8 (__m512i __W, __mmask64 __U, __m512i __A,
1031 __m512i __B)
1032{
1033 return (__m512i) __builtin_ia32_pshufb512_mask ((__v64qi) __A,
1034 (__v64qi) __B,
1035 (__v64qi) __W,
1036 (__mmask64) __U);
1037}
1038
1039static __inline__ __m512i __DEFAULT_FN_ATTRS
1040_mm512_maskz_shuffle_epi8 (__mmask64 __U, __m512i __A, __m512i __B)
1041{
1042 return (__m512i) __builtin_ia32_pshufb512_mask ((__v64qi) __A,
1043 (__v64qi) __B,
1044 (__v64qi) _mm512_setzero_qi(),
1045 (__mmask64) __U);
1046}
1047
1048static __inline__ __m512i __DEFAULT_FN_ATTRS
1049_mm512_subs_epi8 (__m512i __A, __m512i __B)
1050{
1051 return (__m512i) __builtin_ia32_psubsb512_mask ((__v64qi) __A,
1052 (__v64qi) __B,
1053 (__v64qi) _mm512_setzero_qi(),
1054 (__mmask64) -1);
1055}
1056
1057static __inline__ __m512i __DEFAULT_FN_ATTRS
1058_mm512_mask_subs_epi8 (__m512i __W, __mmask64 __U, __m512i __A,
1059 __m512i __B)
1060{
1061 return (__m512i) __builtin_ia32_psubsb512_mask ((__v64qi) __A,
1062 (__v64qi) __B,
1063 (__v64qi) __W,
1064 (__mmask64) __U);
1065}
1066
1067static __inline__ __m512i __DEFAULT_FN_ATTRS
1068_mm512_maskz_subs_epi8 (__mmask64 __U, __m512i __A, __m512i __B)
1069{
1070 return (__m512i) __builtin_ia32_psubsb512_mask ((__v64qi) __A,
1071 (__v64qi) __B,
1072 (__v64qi) _mm512_setzero_qi(),
1073 (__mmask64) __U);
1074}
1075
1076static __inline__ __m512i __DEFAULT_FN_ATTRS
1077_mm512_subs_epi16 (__m512i __A, __m512i __B)
1078{
1079 return (__m512i) __builtin_ia32_psubsw512_mask ((__v32hi) __A,
1080 (__v32hi) __B,
1081 (__v32hi) _mm512_setzero_hi(),
1082 (__mmask32) -1);
1083}
1084
1085static __inline__ __m512i __DEFAULT_FN_ATTRS
1086_mm512_mask_subs_epi16 (__m512i __W, __mmask32 __U, __m512i __A,
1087 __m512i __B)
1088{
1089 return (__m512i) __builtin_ia32_psubsw512_mask ((__v32hi) __A,
1090 (__v32hi) __B,
1091 (__v32hi) __W,
1092 (__mmask32) __U);
1093}
1094
1095static __inline__ __m512i __DEFAULT_FN_ATTRS
1096_mm512_maskz_subs_epi16 (__mmask32 __U, __m512i __A, __m512i __B)
1097{
1098 return (__m512i) __builtin_ia32_psubsw512_mask ((__v32hi) __A,
1099 (__v32hi) __B,
1100 (__v32hi) _mm512_setzero_hi(),
1101 (__mmask32) __U);
1102}
1103
1104static __inline__ __m512i __DEFAULT_FN_ATTRS
1105_mm512_subs_epu8 (__m512i __A, __m512i __B)
1106{
1107 return (__m512i) __builtin_ia32_psubusb512_mask ((__v64qi) __A,
1108 (__v64qi) __B,
1109 (__v64qi) _mm512_setzero_qi(),
1110 (__mmask64) -1);
1111}
1112
1113static __inline__ __m512i __DEFAULT_FN_ATTRS
1114_mm512_mask_subs_epu8 (__m512i __W, __mmask64 __U, __m512i __A,
1115 __m512i __B)
1116{
1117 return (__m512i) __builtin_ia32_psubusb512_mask ((__v64qi) __A,
1118 (__v64qi) __B,
1119 (__v64qi) __W,
1120 (__mmask64) __U);
1121}
1122
1123static __inline__ __m512i __DEFAULT_FN_ATTRS
1124_mm512_maskz_subs_epu8 (__mmask64 __U, __m512i __A, __m512i __B)
1125{
1126 return (__m512i) __builtin_ia32_psubusb512_mask ((__v64qi) __A,
1127 (__v64qi) __B,
1128 (__v64qi) _mm512_setzero_qi(),
1129 (__mmask64) __U);
1130}
1131
1132static __inline__ __m512i __DEFAULT_FN_ATTRS
1133_mm512_subs_epu16 (__m512i __A, __m512i __B)
1134{
1135 return (__m512i) __builtin_ia32_psubusw512_mask ((__v32hi) __A,
1136 (__v32hi) __B,
1137 (__v32hi) _mm512_setzero_hi(),
1138 (__mmask32) -1);
1139}
1140
1141static __inline__ __m512i __DEFAULT_FN_ATTRS
1142_mm512_mask_subs_epu16 (__m512i __W, __mmask32 __U, __m512i __A,
1143 __m512i __B)
1144{
1145 return (__m512i) __builtin_ia32_psubusw512_mask ((__v32hi) __A,
1146 (__v32hi) __B,
1147 (__v32hi) __W,
1148 (__mmask32) __U);
1149}
1150
1151static __inline__ __m512i __DEFAULT_FN_ATTRS
1152_mm512_maskz_subs_epu16 (__mmask32 __U, __m512i __A, __m512i __B)
1153{
1154 return (__m512i) __builtin_ia32_psubusw512_mask ((__v32hi) __A,
1155 (__v32hi) __B,
1156 (__v32hi) _mm512_setzero_hi(),
1157 (__mmask32) __U);
1158}
1159
1160static __inline__ __m512i __DEFAULT_FN_ATTRS
1161_mm512_mask2_permutex2var_epi16 (__m512i __A, __m512i __I,
1162 __mmask32 __U, __m512i __B)
1163{
1164 return (__m512i) __builtin_ia32_vpermi2varhi512_mask ((__v32hi) __A,
1165 (__v32hi) __I /* idx */ ,
1166 (__v32hi) __B,
1167 (__mmask32) __U);
1168}
1169
1170static __inline__ __m512i __DEFAULT_FN_ATTRS
1171_mm512_permutex2var_epi16 (__m512i __A, __m512i __I, __m512i __B)
1172{
1173 return (__m512i) __builtin_ia32_vpermt2varhi512_mask ((__v32hi) __I /* idx */,
1174 (__v32hi) __A,
1175 (__v32hi) __B,
1176 (__mmask32) -1);
1177}
1178
1179static __inline__ __m512i __DEFAULT_FN_ATTRS
1180_mm512_mask_permutex2var_epi16 (__m512i __A, __mmask32 __U,
1181 __m512i __I, __m512i __B)
1182{
1183 return (__m512i) __builtin_ia32_vpermt2varhi512_mask ((__v32hi) __I /* idx */,
1184 (__v32hi) __A,
1185 (__v32hi) __B,
1186 (__mmask32) __U);
1187}
1188
1189static __inline__ __m512i __DEFAULT_FN_ATTRS
1190_mm512_maskz_permutex2var_epi16 (__mmask32 __U, __m512i __A,
1191 __m512i __I, __m512i __B)
1192{
1193 return (__m512i) __builtin_ia32_vpermt2varhi512_maskz ((__v32hi) __I
1194 /* idx */ ,
1195 (__v32hi) __A,
1196 (__v32hi) __B,
1197 (__mmask32) __U);
1198}
1199
1200static __inline__ __m512i __DEFAULT_FN_ATTRS
1201_mm512_mulhrs_epi16 (__m512i __A, __m512i __B)
1202{
1203 return (__m512i) __builtin_ia32_pmulhrsw512_mask ((__v32hi) __A,
1204 (__v32hi) __B,
1205 (__v32hi) _mm512_setzero_hi(),
1206 (__mmask32) -1);
1207}
1208
1209static __inline__ __m512i __DEFAULT_FN_ATTRS
1210_mm512_mask_mulhrs_epi16 (__m512i __W, __mmask32 __U, __m512i __A,
1211 __m512i __B)
1212{
1213 return (__m512i) __builtin_ia32_pmulhrsw512_mask ((__v32hi) __A,
1214 (__v32hi) __B,
1215 (__v32hi) __W,
1216 (__mmask32) __U);
1217}
1218
1219static __inline__ __m512i __DEFAULT_FN_ATTRS
1220_mm512_maskz_mulhrs_epi16 (__mmask32 __U, __m512i __A, __m512i __B)
1221{
1222 return (__m512i) __builtin_ia32_pmulhrsw512_mask ((__v32hi) __A,
1223 (__v32hi) __B,
1224 (__v32hi) _mm512_setzero_hi(),
1225 (__mmask32) __U);
1226}
1227
1228static __inline__ __m512i __DEFAULT_FN_ATTRS
1229_mm512_mulhi_epi16 (__m512i __A, __m512i __B)
1230{
1231 return (__m512i) __builtin_ia32_pmulhw512_mask ((__v32hi) __A,
1232 (__v32hi) __B,
1233 (__v32hi) _mm512_setzero_hi(),
1234 (__mmask32) -1);
1235}
1236
1237static __inline__ __m512i __DEFAULT_FN_ATTRS
1238_mm512_mask_mulhi_epi16 (__m512i __W, __mmask32 __U, __m512i __A,
1239 __m512i __B)
1240{
1241 return (__m512i) __builtin_ia32_pmulhw512_mask ((__v32hi) __A,
1242 (__v32hi) __B,
1243 (__v32hi) __W,
1244 (__mmask32) __U);
1245}
1246
1247static __inline__ __m512i __DEFAULT_FN_ATTRS
1248_mm512_maskz_mulhi_epi16 (__mmask32 __U, __m512i __A, __m512i __B)
1249{
1250 return (__m512i) __builtin_ia32_pmulhw512_mask ((__v32hi) __A,
1251 (__v32hi) __B,
1252 (__v32hi) _mm512_setzero_hi(),
1253 (__mmask32) __U);
1254}
1255
1256static __inline__ __m512i __DEFAULT_FN_ATTRS
1257_mm512_mulhi_epu16 (__m512i __A, __m512i __B)
1258{
1259 return (__m512i) __builtin_ia32_pmulhuw512_mask ((__v32hi) __A,
1260 (__v32hi) __B,
1261 (__v32hi) _mm512_setzero_hi(),
1262 (__mmask32) -1);
1263}
1264
1265static __inline__ __m512i __DEFAULT_FN_ATTRS
1266_mm512_mask_mulhi_epu16 (__m512i __W, __mmask32 __U, __m512i __A,
1267 __m512i __B)
1268{
1269 return (__m512i) __builtin_ia32_pmulhuw512_mask ((__v32hi) __A,
1270 (__v32hi) __B,
1271 (__v32hi) __W,
1272 (__mmask32) __U);
1273}
1274
1275static __inline__ __m512i __DEFAULT_FN_ATTRS
1276_mm512_maskz_mulhi_epu16 (__mmask32 __U, __m512i __A, __m512i __B)
1277{
1278 return (__m512i) __builtin_ia32_pmulhuw512_mask ((__v32hi) __A,
1279 (__v32hi) __B,
1280 (__v32hi) _mm512_setzero_hi(),
1281 (__mmask32) __U);
1282}
1283
1284static __inline__ __m512i __DEFAULT_FN_ATTRS
1285_mm512_maddubs_epi16 (__m512i __X, __m512i __Y) {
1286 return (__m512i) __builtin_ia32_pmaddubsw512_mask ((__v64qi) __X,
1287 (__v64qi) __Y,
1288 (__v32hi) _mm512_setzero_hi(),
1289 (__mmask32) -1);
1290}
1291
1292static __inline__ __m512i __DEFAULT_FN_ATTRS
1293_mm512_mask_maddubs_epi16 (__m512i __W, __mmask32 __U, __m512i __X,
1294 __m512i __Y) {
1295 return (__m512i) __builtin_ia32_pmaddubsw512_mask ((__v64qi) __X,
1296 (__v64qi) __Y,
1297 (__v32hi) __W,
1298 (__mmask32) __U);
1299}
1300
1301static __inline__ __m512i __DEFAULT_FN_ATTRS
1302_mm512_maskz_maddubs_epi16 (__mmask32 __U, __m512i __X, __m512i __Y) {
1303 return (__m512i) __builtin_ia32_pmaddubsw512_mask ((__v64qi) __X,
1304 (__v64qi) __Y,
1305 (__v32hi) _mm512_setzero_hi(),
1306 (__mmask32) __U);
1307}
1308
1309static __inline__ __m512i __DEFAULT_FN_ATTRS
1310_mm512_madd_epi16 (__m512i __A, __m512i __B) {
1311 return (__m512i) __builtin_ia32_pmaddwd512_mask ((__v32hi) __A,
1312 (__v32hi) __B,
1313 (__v16si) _mm512_setzero_si512(),
1314 (__mmask16) -1);
1315}
1316
1317static __inline__ __m512i __DEFAULT_FN_ATTRS
1318_mm512_mask_madd_epi16 (__m512i __W, __mmask16 __U, __m512i __A,
1319 __m512i __B) {
1320 return (__m512i) __builtin_ia32_pmaddwd512_mask ((__v32hi) __A,
1321 (__v32hi) __B,
1322 (__v16si) __W,
1323 (__mmask16) __U);
1324}
1325
1326static __inline__ __m512i __DEFAULT_FN_ATTRS
1327_mm512_maskz_madd_epi16 (__mmask16 __U, __m512i __A, __m512i __B) {
1328 return (__m512i) __builtin_ia32_pmaddwd512_mask ((__v32hi) __A,
1329 (__v32hi) __B,
1330 (__v16si) _mm512_setzero_si512(),
1331 (__mmask16) __U);
1332}
1333
1334static __inline__ __m256i __DEFAULT_FN_ATTRS
1335_mm512_cvtsepi16_epi8 (__m512i __A) {
1336 return (__m256i) __builtin_ia32_pmovswb512_mask ((__v32hi) __A,
1337 (__v32qi)_mm256_setzero_si256(),
1338 (__mmask32) -1);
1339}
1340
1341static __inline__ __m256i __DEFAULT_FN_ATTRS
1342_mm512_mask_cvtsepi16_epi8 (__m256i __O, __mmask32 __M, __m512i __A) {
1343 return (__m256i) __builtin_ia32_pmovswb512_mask ((__v32hi) __A,
1344 (__v32qi)__O,
1345 __M);
1346}
1347
1348static __inline__ __m256i __DEFAULT_FN_ATTRS
1349_mm512_maskz_cvtsepi16_epi8 (__mmask32 __M, __m512i __A) {
1350 return (__m256i) __builtin_ia32_pmovswb512_mask ((__v32hi) __A,
1351 (__v32qi) _mm256_setzero_si256(),
1352 __M);
1353}
1354
1355static __inline__ __m256i __DEFAULT_FN_ATTRS
1356_mm512_cvtusepi16_epi8 (__m512i __A) {
1357 return (__m256i) __builtin_ia32_pmovuswb512_mask ((__v32hi) __A,
1358 (__v32qi) _mm256_setzero_si256(),
1359 (__mmask32) -1);
1360}
1361
1362static __inline__ __m256i __DEFAULT_FN_ATTRS
1363_mm512_mask_cvtusepi16_epi8 (__m256i __O, __mmask32 __M, __m512i __A) {
1364 return (__m256i) __builtin_ia32_pmovuswb512_mask ((__v32hi) __A,
1365 (__v32qi) __O,
1366 __M);
1367}
1368
1369static __inline__ __m256i __DEFAULT_FN_ATTRS
1370_mm512_maskz_cvtusepi16_epi8 (__mmask32 __M, __m512i __A) {
1371 return (__m256i) __builtin_ia32_pmovuswb512_mask ((__v32hi) __A,
1372 (__v32qi) _mm256_setzero_si256(),
1373 __M);
1374}
1375
1376static __inline__ __m256i __DEFAULT_FN_ATTRS
1377_mm512_cvtepi16_epi8 (__m512i __A) {
1378 return (__m256i) __builtin_ia32_pmovwb512_mask ((__v32hi) __A,
1379 (__v32qi) _mm256_setzero_si256(),
1380 (__mmask32) -1);
1381}
1382
1383static __inline__ __m256i __DEFAULT_FN_ATTRS
1384_mm512_mask_cvtepi16_epi8 (__m256i __O, __mmask32 __M, __m512i __A) {
1385 return (__m256i) __builtin_ia32_pmovwb512_mask ((__v32hi) __A,
1386 (__v32qi) __O,
1387 __M);
1388}
1389
1390static __inline__ __m256i __DEFAULT_FN_ATTRS
1391_mm512_maskz_cvtepi16_epi8 (__mmask32 __M, __m512i __A) {
1392 return (__m256i) __builtin_ia32_pmovwb512_mask ((__v32hi) __A,
1393 (__v32qi) _mm256_setzero_si256(),
1394 __M);
1395}
1396
Pirama Arumuga Nainarbb4374f2016-10-20 16:43:03 -0700[diff] [blame]1397static __inline__ void __DEFAULT_FN_ATTRS
1398_mm512_mask_cvtepi16_storeu_epi8 (void * __P, __mmask32 __M, __m512i __A)
1399{
1400 __builtin_ia32_pmovwb512mem_mask ((__v32qi *) __P, (__v32hi) __A, __M);
1401}
1402
1403static __inline__ void __DEFAULT_FN_ATTRS
1404_mm512_mask_cvtsepi16_storeu_epi8 (void * __P, __mmask32 __M, __m512i __A)
1405{
1406 __builtin_ia32_pmovswb512mem_mask ((__v32qi *) __P, (__v32hi) __A, __M);
1407}
1408
1409static __inline__ void __DEFAULT_FN_ATTRS
1410_mm512_mask_cvtusepi16_storeu_epi8 (void * __P, __mmask32 __M, __m512i __A)
1411{
1412 __builtin_ia32_pmovuswb512mem_mask ((__v32qi *) __P, (__v32hi) __A, __M);
Pirama Arumuga Nainar4e74a022016-03-17 18:03:02 -0700[diff] [blame]1413}
1414
1415static __inline__ __m512i __DEFAULT_FN_ATTRS
Pirama Arumuga Nainarbb4374f2016-10-20 16:43:03 -0700[diff] [blame]1416_mm512_unpackhi_epi8(__m512i __A, __m512i __B) {
1417 return (__m512i)__builtin_shufflevector((__v64qi)__A, (__v64qi)__B,
1418 8, 64+8, 9, 64+9,
1419 10, 64+10, 11, 64+11,
1420 12, 64+12, 13, 64+13,
1421 14, 64+14, 15, 64+15,
1422 24, 64+24, 25, 64+25,
1423 26, 64+26, 27, 64+27,
1424 28, 64+28, 29, 64+29,
1425 30, 64+30, 31, 64+31,
1426 40, 64+40, 41, 64+41,
1427 42, 64+42, 43, 64+43,
1428 44, 64+44, 45, 64+45,
1429 46, 64+46, 47, 64+47,
1430 56, 64+56, 57, 64+57,
1431 58, 64+58, 59, 64+59,
1432 60, 64+60, 61, 64+61,
1433 62, 64+62, 63, 64+63);
Pirama Arumuga Nainar4e74a022016-03-17 18:03:02 -0700[diff] [blame]1434}
1435
1436static __inline__ __m512i __DEFAULT_FN_ATTRS
Pirama Arumuga Nainarbb4374f2016-10-20 16:43:03 -0700[diff] [blame]1437_mm512_mask_unpackhi_epi8(__m512i __W, __mmask64 __U, __m512i __A, __m512i __B) {
1438 return (__m512i)__builtin_ia32_selectb_512((__mmask64)__U,
1439 (__v64qi)_mm512_unpackhi_epi8(__A, __B),
1440 (__v64qi)__W);
Pirama Arumuga Nainar4e74a022016-03-17 18:03:02 -0700[diff] [blame]1441}
1442
1443static __inline__ __m512i __DEFAULT_FN_ATTRS
Pirama Arumuga Nainarbb4374f2016-10-20 16:43:03 -0700[diff] [blame]1444_mm512_maskz_unpackhi_epi8(__mmask64 __U, __m512i __A, __m512i __B) {
1445 return (__m512i)__builtin_ia32_selectb_512((__mmask64)__U,
1446 (__v64qi)_mm512_unpackhi_epi8(__A, __B),
1447 (__v64qi)_mm512_setzero_qi());
Pirama Arumuga Nainar4e74a022016-03-17 18:03:02 -0700[diff] [blame]1448}
1449
1450static __inline__ __m512i __DEFAULT_FN_ATTRS
Pirama Arumuga Nainarbb4374f2016-10-20 16:43:03 -0700[diff] [blame]1451_mm512_unpackhi_epi16(__m512i __A, __m512i __B) {
1452 return (__m512i)__builtin_shufflevector((__v32hi)__A, (__v32hi)__B,
1453 4, 32+4, 5, 32+5,
1454 6, 32+6, 7, 32+7,
1455 12, 32+12, 13, 32+13,
1456 14, 32+14, 15, 32+15,
1457 20, 32+20, 21, 32+21,
1458 22, 32+22, 23, 32+23,
1459 28, 32+28, 29, 32+29,
1460 30, 32+30, 31, 32+31);
Pirama Arumuga Nainar4e74a022016-03-17 18:03:02 -0700[diff] [blame]1461}
1462
1463static __inline__ __m512i __DEFAULT_FN_ATTRS
Pirama Arumuga Nainarbb4374f2016-10-20 16:43:03 -0700[diff] [blame]1464_mm512_mask_unpackhi_epi16(__m512i __W, __mmask32 __U, __m512i __A, __m512i __B) {
1465 return (__m512i)__builtin_ia32_selectw_512((__mmask32)__U,
1466 (__v32hi)_mm512_unpackhi_epi16(__A, __B),
1467 (__v32hi)__W);
Pirama Arumuga Nainar4e74a022016-03-17 18:03:02 -0700[diff] [blame]1468}
1469
1470static __inline__ __m512i __DEFAULT_FN_ATTRS
Pirama Arumuga Nainarbb4374f2016-10-20 16:43:03 -0700[diff] [blame]1471_mm512_maskz_unpackhi_epi16(__mmask32 __U, __m512i __A, __m512i __B) {
1472 return (__m512i)__builtin_ia32_selectw_512((__mmask32)__U,
1473 (__v32hi)_mm512_unpackhi_epi16(__A, __B),
1474 (__v32hi)_mm512_setzero_hi());
Pirama Arumuga Nainar4e74a022016-03-17 18:03:02 -0700[diff] [blame]1475}
1476
1477static __inline__ __m512i __DEFAULT_FN_ATTRS
Pirama Arumuga Nainarbb4374f2016-10-20 16:43:03 -0700[diff] [blame]1478_mm512_unpacklo_epi8(__m512i __A, __m512i __B) {
1479 return (__m512i)__builtin_shufflevector((__v64qi)__A, (__v64qi)__B,
1480 0, 64+0, 1, 64+1,
1481 2, 64+2, 3, 64+3,
1482 4, 64+4, 5, 64+5,
1483 6, 64+6, 7, 64+7,
1484 16, 64+16, 17, 64+17,
1485 18, 64+18, 19, 64+19,
1486 20, 64+20, 21, 64+21,
1487 22, 64+22, 23, 64+23,
1488 32, 64+32, 33, 64+33,
1489 34, 64+34, 35, 64+35,
1490 36, 64+36, 37, 64+37,
1491 38, 64+38, 39, 64+39,
1492 48, 64+48, 49, 64+49,
1493 50, 64+50, 51, 64+51,
1494 52, 64+52, 53, 64+53,
1495 54, 64+54, 55, 64+55);
Pirama Arumuga Nainar4e74a022016-03-17 18:03:02 -0700[diff] [blame]1496}
1497
1498static __inline__ __m512i __DEFAULT_FN_ATTRS
Pirama Arumuga Nainarbb4374f2016-10-20 16:43:03 -0700[diff] [blame]1499_mm512_mask_unpacklo_epi8(__m512i __W, __mmask64 __U, __m512i __A, __m512i __B) {
1500 return (__m512i)__builtin_ia32_selectb_512((__mmask64)__U,
1501 (__v64qi)_mm512_unpacklo_epi8(__A, __B),
1502 (__v64qi)__W);
Pirama Arumuga Nainar4e74a022016-03-17 18:03:02 -0700[diff] [blame]1503}
1504
1505static __inline__ __m512i __DEFAULT_FN_ATTRS
Pirama Arumuga Nainarbb4374f2016-10-20 16:43:03 -0700[diff] [blame]1506_mm512_maskz_unpacklo_epi8(__mmask64 __U, __m512i __A, __m512i __B) {
1507 return (__m512i)__builtin_ia32_selectb_512((__mmask64)__U,
1508 (__v64qi)_mm512_unpacklo_epi8(__A, __B),
1509 (__v64qi)_mm512_setzero_qi());
Pirama Arumuga Nainar4e74a022016-03-17 18:03:02 -0700[diff] [blame]1510}
1511
1512static __inline__ __m512i __DEFAULT_FN_ATTRS
Pirama Arumuga Nainarbb4374f2016-10-20 16:43:03 -0700[diff] [blame]1513_mm512_unpacklo_epi16(__m512i __A, __m512i __B) {
1514 return (__m512i)__builtin_shufflevector((__v32hi)__A, (__v32hi)__B,
1515 0, 32+0, 1, 32+1,
1516 2, 32+2, 3, 32+3,
1517 8, 32+8, 9, 32+9,
1518 10, 32+10, 11, 32+11,
1519 16, 32+16, 17, 32+17,
1520 18, 32+18, 19, 32+19,
1521 24, 32+24, 25, 32+25,
1522 26, 32+26, 27, 32+27);
Pirama Arumuga Nainar4e74a022016-03-17 18:03:02 -0700[diff] [blame]1523}
1524
1525static __inline__ __m512i __DEFAULT_FN_ATTRS
Pirama Arumuga Nainarbb4374f2016-10-20 16:43:03 -0700[diff] [blame]1526_mm512_mask_unpacklo_epi16(__m512i __W, __mmask32 __U, __m512i __A, __m512i __B) {
1527 return (__m512i)__builtin_ia32_selectw_512((__mmask32)__U,
1528 (__v32hi)_mm512_unpacklo_epi16(__A, __B),
1529 (__v32hi)__W);
Pirama Arumuga Nainar4e74a022016-03-17 18:03:02 -0700[diff] [blame]1530}
1531
Pirama Arumuga Nainarbb4374f2016-10-20 16:43:03 -0700[diff] [blame]1532static __inline__ __m512i __DEFAULT_FN_ATTRS
1533_mm512_maskz_unpacklo_epi16(__mmask32 __U, __m512i __A, __m512i __B) {
1534 return (__m512i)__builtin_ia32_selectw_512((__mmask32)__U,
1535 (__v32hi)_mm512_unpacklo_epi16(__A, __B),
1536 (__v32hi)_mm512_setzero_hi());
1537}
1538
1539static __inline__ __m512i __DEFAULT_FN_ATTRS
1540_mm512_cvtepi8_epi16 (__m256i __A)
1541{
1542 return (__m512i) __builtin_ia32_pmovsxbw512_mask ((__v32qi) __A,
1543 (__v32hi)
1544 _mm512_setzero_hi (),
1545 (__mmask32) -1);
1546}
1547
1548static __inline__ __m512i __DEFAULT_FN_ATTRS
1549_mm512_mask_cvtepi8_epi16 (__m512i __W, __mmask32 __U, __m256i __A)
1550{
1551 return (__m512i) __builtin_ia32_pmovsxbw512_mask ((__v32qi) __A,
1552 (__v32hi) __W,
1553 (__mmask32) __U);
1554}
1555
1556static __inline__ __m512i __DEFAULT_FN_ATTRS
1557_mm512_maskz_cvtepi8_epi16 (__mmask32 __U, __m256i __A)
1558{
1559 return (__m512i) __builtin_ia32_pmovsxbw512_mask ((__v32qi) __A,
1560 (__v32hi)
1561 _mm512_setzero_hi(),
1562 (__mmask32) __U);
1563}
1564
1565static __inline__ __m512i __DEFAULT_FN_ATTRS
1566_mm512_cvtepu8_epi16 (__m256i __A)
1567{
1568 return (__m512i) __builtin_ia32_pmovzxbw512_mask ((__v32qi) __A,
1569 (__v32hi)
1570 _mm512_setzero_hi (),
1571 (__mmask32) -1);
1572}
1573
1574static __inline__ __m512i __DEFAULT_FN_ATTRS
1575_mm512_mask_cvtepu8_epi16 (__m512i __W, __mmask32 __U, __m256i __A)
1576{
1577 return (__m512i) __builtin_ia32_pmovzxbw512_mask ((__v32qi) __A,
1578 (__v32hi) __W,
1579 (__mmask32) __U);
1580}
1581
1582static __inline__ __m512i __DEFAULT_FN_ATTRS
1583_mm512_maskz_cvtepu8_epi16 (__mmask32 __U, __m256i __A)
1584{
1585 return (__m512i) __builtin_ia32_pmovzxbw512_mask ((__v32qi) __A,
1586 (__v32hi)
1587 _mm512_setzero_hi(),
1588 (__mmask32) __U);
1589}
1590
1591
Stephen Hinesb4d9c8b2015-03-30 16:04:04 -0700[diff] [blame]1592#define _mm512_cmp_epi8_mask(a, b, p) __extension__ ({ \
Pirama Arumuga Nainarbb4374f2016-10-20 16:43:03 -0700[diff] [blame]1593 (__mmask64)__builtin_ia32_cmpb512_mask((__v64qi)(__m512i)(a), \
1594 (__v64qi)(__m512i)(b), (int)(p), \
1595 (__mmask64)-1); })
Stephen Hinesb4d9c8b2015-03-30 16:04:04 -0700[diff] [blame]1596
1597#define _mm512_mask_cmp_epi8_mask(m, a, b, p) __extension__ ({ \
Pirama Arumuga Nainarbb4374f2016-10-20 16:43:03 -0700[diff] [blame]1598 (__mmask64)__builtin_ia32_cmpb512_mask((__v64qi)(__m512i)(a), \
1599 (__v64qi)(__m512i)(b), (int)(p), \
1600 (__mmask64)(m)); })
Stephen Hinesb4d9c8b2015-03-30 16:04:04 -0700[diff] [blame]1601
1602#define _mm512_cmp_epu8_mask(a, b, p) __extension__ ({ \
Pirama Arumuga Nainarbb4374f2016-10-20 16:43:03 -0700[diff] [blame]1603 (__mmask64)__builtin_ia32_ucmpb512_mask((__v64qi)(__m512i)(a), \
1604 (__v64qi)(__m512i)(b), (int)(p), \
1605 (__mmask64)-1); })
Stephen Hinesb4d9c8b2015-03-30 16:04:04 -0700[diff] [blame]1606
1607#define _mm512_mask_cmp_epu8_mask(m, a, b, p) __extension__ ({ \
Pirama Arumuga Nainarbb4374f2016-10-20 16:43:03 -0700[diff] [blame]1608 (__mmask64)__builtin_ia32_ucmpb512_mask((__v64qi)(__m512i)(a), \
1609 (__v64qi)(__m512i)(b), (int)(p), \
1610 (__mmask64)(m)); })
Stephen Hinesb4d9c8b2015-03-30 16:04:04 -0700[diff] [blame]1611
1612#define _mm512_cmp_epi16_mask(a, b, p) __extension__ ({ \
Pirama Arumuga Nainarbb4374f2016-10-20 16:43:03 -0700[diff] [blame]1613 (__mmask32)__builtin_ia32_cmpw512_mask((__v32hi)(__m512i)(a), \
1614 (__v32hi)(__m512i)(b), (int)(p), \
1615 (__mmask32)-1); })
Stephen Hinesb4d9c8b2015-03-30 16:04:04 -0700[diff] [blame]1616
1617#define _mm512_mask_cmp_epi16_mask(m, a, b, p) __extension__ ({ \
Pirama Arumuga Nainarbb4374f2016-10-20 16:43:03 -0700[diff] [blame]1618 (__mmask32)__builtin_ia32_cmpw512_mask((__v32hi)(__m512i)(a), \
1619 (__v32hi)(__m512i)(b), (int)(p), \
1620 (__mmask32)(m)); })
Stephen Hinesb4d9c8b2015-03-30 16:04:04 -0700[diff] [blame]1621
1622#define _mm512_cmp_epu16_mask(a, b, p) __extension__ ({ \
Pirama Arumuga Nainarbb4374f2016-10-20 16:43:03 -0700[diff] [blame]1623 (__mmask32)__builtin_ia32_ucmpw512_mask((__v32hi)(__m512i)(a), \
1624 (__v32hi)(__m512i)(b), (int)(p), \
1625 (__mmask32)-1); })
Stephen Hinesb4d9c8b2015-03-30 16:04:04 -0700[diff] [blame]1626
1627#define _mm512_mask_cmp_epu16_mask(m, a, b, p) __extension__ ({ \
Pirama Arumuga Nainarbb4374f2016-10-20 16:43:03 -0700[diff] [blame]1628 (__mmask32)__builtin_ia32_ucmpw512_mask((__v32hi)(__m512i)(a), \
1629 (__v32hi)(__m512i)(b), (int)(p), \
1630 (__mmask32)(m)); })
1631
1632#define _mm512_shufflehi_epi16(A, imm) __extension__ ({ \
1633 (__m512i)__builtin_shufflevector((__v32hi)(__m512i)(A), \
1634 (__v32hi)_mm512_undefined_epi32(), \
1635 0, 1, 2, 3, \
1636 4 + (((imm) >> 0) & 0x3), \
1637 4 + (((imm) >> 2) & 0x3), \
1638 4 + (((imm) >> 4) & 0x3), \
1639 4 + (((imm) >> 6) & 0x3), \
1640 8, 9, 10, 11, \
1641 12 + (((imm) >> 0) & 0x3), \
1642 12 + (((imm) >> 2) & 0x3), \
1643 12 + (((imm) >> 4) & 0x3), \
1644 12 + (((imm) >> 6) & 0x3), \
1645 16, 17, 18, 19, \
1646 20 + (((imm) >> 0) & 0x3), \
1647 20 + (((imm) >> 2) & 0x3), \
1648 20 + (((imm) >> 4) & 0x3), \
1649 20 + (((imm) >> 6) & 0x3), \
1650 24, 25, 26, 27, \
1651 28 + (((imm) >> 0) & 0x3), \
1652 28 + (((imm) >> 2) & 0x3), \
1653 28 + (((imm) >> 4) & 0x3), \
1654 28 + (((imm) >> 6) & 0x3)); })
1655
1656#define _mm512_mask_shufflehi_epi16(W, U, A, imm) __extension__ ({ \
1657 (__m512i)__builtin_ia32_selectw_512((__mmask32)(U), \
1658 (__v32hi)_mm512_shufflehi_epi16((A), \
1659 (imm)), \
1660 (__v32hi)(__m512i)(W)); })
1661
1662#define _mm512_maskz_shufflehi_epi16(U, A, imm) __extension__ ({ \
1663 (__m512i)__builtin_ia32_selectw_512((__mmask32)(U), \
1664 (__v32hi)_mm512_shufflehi_epi16((A), \
1665 (imm)), \
1666 (__v32hi)_mm512_setzero_hi()); })
1667
1668#define _mm512_shufflelo_epi16(A, imm) __extension__ ({ \
1669 (__m512i)__builtin_shufflevector((__v32hi)(__m512i)(A), \
1670 (__v32hi)_mm512_undefined_epi32(), \
1671 0 + (((imm) >> 0) & 0x3), \
1672 0 + (((imm) >> 2) & 0x3), \
1673 0 + (((imm) >> 4) & 0x3), \
1674 0 + (((imm) >> 6) & 0x3), \
1675 4, 5, 6, 7, \
1676 8 + (((imm) >> 0) & 0x3), \
1677 8 + (((imm) >> 2) & 0x3), \
1678 8 + (((imm) >> 4) & 0x3), \
1679 8 + (((imm) >> 6) & 0x3), \
1680 12, 13, 14, 15, \
1681 16 + (((imm) >> 0) & 0x3), \
1682 16 + (((imm) >> 2) & 0x3), \
1683 16 + (((imm) >> 4) & 0x3), \
1684 16 + (((imm) >> 6) & 0x3), \
1685 20, 21, 22, 23, \
1686 24 + (((imm) >> 0) & 0x3), \
1687 24 + (((imm) >> 2) & 0x3), \
1688 24 + (((imm) >> 4) & 0x3), \
1689 24 + (((imm) >> 6) & 0x3), \
1690 28, 29, 30, 31); })
1691
1692
1693#define _mm512_mask_shufflelo_epi16(W, U, A, imm) __extension__ ({ \
1694 (__m512i)__builtin_ia32_selectw_512((__mmask32)(U), \
1695 (__v32hi)_mm512_shufflelo_epi16((A), \
1696 (imm)), \
1697 (__v32hi)(__m512i)(W)); })
1698
1699
1700#define _mm512_maskz_shufflelo_epi16(U, A, imm) __extension__ ({ \
1701 (__m512i)__builtin_ia32_selectw_512((__mmask32)(U), \
1702 (__v32hi)_mm512_shufflelo_epi16((A), \
1703 (imm)), \
1704 (__v32hi)_mm512_setzero_hi()); })
1705
1706static __inline__ __m512i __DEFAULT_FN_ATTRS
1707_mm512_sllv_epi16 (__m512i __A, __m512i __B)
1708{
1709 return (__m512i) __builtin_ia32_psllv32hi_mask ((__v32hi) __A,
1710 (__v32hi) __B,
1711 (__v32hi)
1712 _mm512_setzero_hi (),
1713 (__mmask32) -1);
1714}
1715
1716static __inline__ __m512i __DEFAULT_FN_ATTRS
1717_mm512_mask_sllv_epi16 (__m512i __W, __mmask32 __U, __m512i __A,
1718 __m512i __B)
1719{
1720 return (__m512i) __builtin_ia32_psllv32hi_mask ((__v32hi) __A,
1721 (__v32hi) __B,
1722 (__v32hi) __W,
1723 (__mmask32) __U);
1724}
1725
1726static __inline__ __m512i __DEFAULT_FN_ATTRS
1727_mm512_maskz_sllv_epi16 (__mmask32 __U, __m512i __A, __m512i __B)
1728{
1729 return (__m512i) __builtin_ia32_psllv32hi_mask ((__v32hi) __A,
1730 (__v32hi) __B,
1731 (__v32hi)
1732 _mm512_setzero_hi (),
1733 (__mmask32) __U);
1734}
1735
1736static __inline__ __m512i __DEFAULT_FN_ATTRS
1737_mm512_sll_epi16 (__m512i __A, __m128i __B)
1738{
1739 return (__m512i) __builtin_ia32_psllw512_mask ((__v32hi) __A,
1740 (__v8hi) __B,
1741 (__v32hi)
1742 _mm512_setzero_hi (),
1743 (__mmask32) -1);
1744}
1745
1746static __inline__ __m512i __DEFAULT_FN_ATTRS
1747_mm512_mask_sll_epi16 (__m512i __W, __mmask32 __U, __m512i __A,
1748 __m128i __B)
1749{
1750 return (__m512i) __builtin_ia32_psllw512_mask ((__v32hi) __A,
1751 (__v8hi) __B,
1752 (__v32hi) __W,
1753 (__mmask32) __U);
1754}
1755
1756static __inline__ __m512i __DEFAULT_FN_ATTRS
1757_mm512_maskz_sll_epi16 (__mmask32 __U, __m512i __A, __m128i __B)
1758{
1759 return (__m512i) __builtin_ia32_psllw512_mask ((__v32hi) __A,
1760 (__v8hi) __B,
1761 (__v32hi)
1762 _mm512_setzero_hi (),
1763 (__mmask32) __U);
1764}
1765
1766#define _mm512_slli_epi16(A, B) __extension__ ({ \
1767 (__m512i)__builtin_ia32_psllwi512_mask((__v32hi)(__m512i)(A), (int)(B), \
1768 (__v32hi)_mm512_setzero_hi(), \
1769 (__mmask32)-1); })
1770
1771#define _mm512_mask_slli_epi16(W, U, A, B) __extension__ ({ \
1772 (__m512i)__builtin_ia32_psllwi512_mask((__v32hi)(__m512i)(A), (int)(B), \
1773 (__v32hi)(__m512i)(W), \
1774 (__mmask32)(U)); })
1775
1776#define _mm512_maskz_slli_epi16(U, A, B) __extension__ ({ \
1777 (__m512i)__builtin_ia32_psllwi512_mask((__v32hi)(__m512i)(A), (int)(B), \
1778 (__v32hi)_mm512_setzero_hi(), \
1779 (__mmask32)(U)); })
1780
1781#define _mm512_bslli_epi128(a, imm) __extension__ ({ \
1782 (__m512i)__builtin_shufflevector( \
1783 (__v64qi)_mm512_setzero_si512(), \
1784 (__v64qi)(__m512i)(a), \
1785 ((char)(imm)&0xF0) ? 0 : ((char)(imm)>0x0 ? 16 : 64) - (char)(imm), \
1786 ((char)(imm)&0xF0) ? 1 : ((char)(imm)>0x1 ? 17 : 65) - (char)(imm), \
1787 ((char)(imm)&0xF0) ? 2 : ((char)(imm)>0x2 ? 18 : 66) - (char)(imm), \
1788 ((char)(imm)&0xF0) ? 3 : ((char)(imm)>0x3 ? 19 : 67) - (char)(imm), \
1789 ((char)(imm)&0xF0) ? 4 : ((char)(imm)>0x4 ? 20 : 68) - (char)(imm), \
1790 ((char)(imm)&0xF0) ? 5 : ((char)(imm)>0x5 ? 21 : 69) - (char)(imm), \
1791 ((char)(imm)&0xF0) ? 6 : ((char)(imm)>0x6 ? 22 : 70) - (char)(imm), \
1792 ((char)(imm)&0xF0) ? 7 : ((char)(imm)>0x7 ? 23 : 71) - (char)(imm), \
1793 ((char)(imm)&0xF0) ? 8 : ((char)(imm)>0x8 ? 24 : 72) - (char)(imm), \
1794 ((char)(imm)&0xF0) ? 9 : ((char)(imm)>0x9 ? 25 : 73) - (char)(imm), \
1795 ((char)(imm)&0xF0) ? 10 : ((char)(imm)>0xA ? 26 : 74) - (char)(imm), \
1796 ((char)(imm)&0xF0) ? 11 : ((char)(imm)>0xB ? 27 : 75) - (char)(imm), \
1797 ((char)(imm)&0xF0) ? 12 : ((char)(imm)>0xC ? 28 : 76) - (char)(imm), \
1798 ((char)(imm)&0xF0) ? 13 : ((char)(imm)>0xD ? 29 : 77) - (char)(imm), \
1799 ((char)(imm)&0xF0) ? 14 : ((char)(imm)>0xE ? 30 : 78) - (char)(imm), \
1800 ((char)(imm)&0xF0) ? 15 : ((char)(imm)>0xF ? 31 : 79) - (char)(imm), \
1801 ((char)(imm)&0xF0) ? 16 : ((char)(imm)>0x0 ? 32 : 80) - (char)(imm), \
1802 ((char)(imm)&0xF0) ? 17 : ((char)(imm)>0x1 ? 33 : 81) - (char)(imm), \
1803 ((char)(imm)&0xF0) ? 18 : ((char)(imm)>0x2 ? 34 : 82) - (char)(imm), \
1804 ((char)(imm)&0xF0) ? 19 : ((char)(imm)>0x3 ? 35 : 83) - (char)(imm), \
1805 ((char)(imm)&0xF0) ? 20 : ((char)(imm)>0x4 ? 36 : 84) - (char)(imm), \
1806 ((char)(imm)&0xF0) ? 21 : ((char)(imm)>0x5 ? 37 : 85) - (char)(imm), \
1807 ((char)(imm)&0xF0) ? 22 : ((char)(imm)>0x6 ? 38 : 86) - (char)(imm), \
1808 ((char)(imm)&0xF0) ? 23 : ((char)(imm)>0x7 ? 39 : 87) - (char)(imm), \
1809 ((char)(imm)&0xF0) ? 24 : ((char)(imm)>0x8 ? 40 : 88) - (char)(imm), \
1810 ((char)(imm)&0xF0) ? 25 : ((char)(imm)>0x9 ? 41 : 89) - (char)(imm), \
1811 ((char)(imm)&0xF0) ? 26 : ((char)(imm)>0xA ? 42 : 90) - (char)(imm), \
1812 ((char)(imm)&0xF0) ? 27 : ((char)(imm)>0xB ? 43 : 91) - (char)(imm), \
1813 ((char)(imm)&0xF0) ? 28 : ((char)(imm)>0xC ? 44 : 92) - (char)(imm), \
1814 ((char)(imm)&0xF0) ? 29 : ((char)(imm)>0xD ? 45 : 93) - (char)(imm), \
1815 ((char)(imm)&0xF0) ? 30 : ((char)(imm)>0xE ? 46 : 94) - (char)(imm), \
1816 ((char)(imm)&0xF0) ? 31 : ((char)(imm)>0xF ? 47 : 95) - (char)(imm), \
1817 ((char)(imm)&0xF0) ? 32 : ((char)(imm)>0x0 ? 48 : 96) - (char)(imm), \
1818 ((char)(imm)&0xF0) ? 33 : ((char)(imm)>0x1 ? 49 : 97) - (char)(imm), \
1819 ((char)(imm)&0xF0) ? 34 : ((char)(imm)>0x2 ? 50 : 98) - (char)(imm), \
1820 ((char)(imm)&0xF0) ? 35 : ((char)(imm)>0x3 ? 51 : 99) - (char)(imm), \
1821 ((char)(imm)&0xF0) ? 36 : ((char)(imm)>0x4 ? 52 : 100) - (char)(imm), \
1822 ((char)(imm)&0xF0) ? 37 : ((char)(imm)>0x5 ? 53 : 101) - (char)(imm), \
1823 ((char)(imm)&0xF0) ? 38 : ((char)(imm)>0x6 ? 54 : 102) - (char)(imm), \
1824 ((char)(imm)&0xF0) ? 39 : ((char)(imm)>0x7 ? 55 : 103) - (char)(imm), \
1825 ((char)(imm)&0xF0) ? 40 : ((char)(imm)>0x8 ? 56 : 104) - (char)(imm), \
1826 ((char)(imm)&0xF0) ? 41 : ((char)(imm)>0x9 ? 57 : 105) - (char)(imm), \
1827 ((char)(imm)&0xF0) ? 42 : ((char)(imm)>0xA ? 58 : 106) - (char)(imm), \
1828 ((char)(imm)&0xF0) ? 43 : ((char)(imm)>0xB ? 59 : 107) - (char)(imm), \
1829 ((char)(imm)&0xF0) ? 44 : ((char)(imm)>0xC ? 60 : 108) - (char)(imm), \
1830 ((char)(imm)&0xF0) ? 45 : ((char)(imm)>0xD ? 61 : 109) - (char)(imm), \
1831 ((char)(imm)&0xF0) ? 46 : ((char)(imm)>0xE ? 62 : 110) - (char)(imm), \
1832 ((char)(imm)&0xF0) ? 47 : ((char)(imm)>0xF ? 63 : 111) - (char)(imm), \
1833 ((char)(imm)&0xF0) ? 48 : ((char)(imm)>0x0 ? 64 : 112) - (char)(imm), \
1834 ((char)(imm)&0xF0) ? 49 : ((char)(imm)>0x1 ? 65 : 113) - (char)(imm), \
1835 ((char)(imm)&0xF0) ? 50 : ((char)(imm)>0x2 ? 66 : 114) - (char)(imm), \
1836 ((char)(imm)&0xF0) ? 51 : ((char)(imm)>0x3 ? 67 : 115) - (char)(imm), \
1837 ((char)(imm)&0xF0) ? 52 : ((char)(imm)>0x4 ? 68 : 116) - (char)(imm), \
1838 ((char)(imm)&0xF0) ? 53 : ((char)(imm)>0x5 ? 69 : 117) - (char)(imm), \
1839 ((char)(imm)&0xF0) ? 54 : ((char)(imm)>0x6 ? 70 : 118) - (char)(imm), \
1840 ((char)(imm)&0xF0) ? 55 : ((char)(imm)>0x7 ? 71 : 119) - (char)(imm), \
1841 ((char)(imm)&0xF0) ? 56 : ((char)(imm)>0x8 ? 72 : 120) - (char)(imm), \
1842 ((char)(imm)&0xF0) ? 57 : ((char)(imm)>0x9 ? 73 : 121) - (char)(imm), \
1843 ((char)(imm)&0xF0) ? 58 : ((char)(imm)>0xA ? 74 : 122) - (char)(imm), \
1844 ((char)(imm)&0xF0) ? 59 : ((char)(imm)>0xB ? 75 : 123) - (char)(imm), \
1845 ((char)(imm)&0xF0) ? 60 : ((char)(imm)>0xC ? 76 : 124) - (char)(imm), \
1846 ((char)(imm)&0xF0) ? 61 : ((char)(imm)>0xD ? 77 : 125) - (char)(imm), \
1847 ((char)(imm)&0xF0) ? 62 : ((char)(imm)>0xE ? 78 : 126) - (char)(imm), \
1848 ((char)(imm)&0xF0) ? 63 : ((char)(imm)>0xF ? 79 : 127) - (char)(imm)); })
1849
1850static __inline__ __m512i __DEFAULT_FN_ATTRS
1851_mm512_srlv_epi16 (__m512i __A, __m512i __B)
1852{
1853 return (__m512i) __builtin_ia32_psrlv32hi_mask ((__v32hi) __A,
1854 (__v32hi) __B,
1855 (__v32hi)
1856 _mm512_setzero_hi (),
1857 (__mmask32) -1);
1858}
1859
1860static __inline__ __m512i __DEFAULT_FN_ATTRS
1861_mm512_mask_srlv_epi16 (__m512i __W, __mmask32 __U, __m512i __A,
1862 __m512i __B)
1863{
1864 return (__m512i) __builtin_ia32_psrlv32hi_mask ((__v32hi) __A,
1865 (__v32hi) __B,
1866 (__v32hi) __W,
1867 (__mmask32) __U);
1868}
1869
1870static __inline__ __m512i __DEFAULT_FN_ATTRS
1871_mm512_maskz_srlv_epi16 (__mmask32 __U, __m512i __A, __m512i __B)
1872{
1873 return (__m512i) __builtin_ia32_psrlv32hi_mask ((__v32hi) __A,
1874 (__v32hi) __B,
1875 (__v32hi)
1876 _mm512_setzero_hi (),
1877 (__mmask32) __U);
1878}
1879
1880static __inline__ __m512i __DEFAULT_FN_ATTRS
1881_mm512_srav_epi16 (__m512i __A, __m512i __B)
1882{
1883 return (__m512i) __builtin_ia32_psrav32hi_mask ((__v32hi) __A,
1884 (__v32hi) __B,
1885 (__v32hi)
1886 _mm512_setzero_hi (),
1887 (__mmask32) -1);
1888}
1889
1890static __inline__ __m512i __DEFAULT_FN_ATTRS
1891_mm512_mask_srav_epi16 (__m512i __W, __mmask32 __U, __m512i __A,
1892 __m512i __B)
1893{
1894 return (__m512i) __builtin_ia32_psrav32hi_mask ((__v32hi) __A,
1895 (__v32hi) __B,
1896 (__v32hi) __W,
1897 (__mmask32) __U);
1898}
1899
1900static __inline__ __m512i __DEFAULT_FN_ATTRS
1901_mm512_maskz_srav_epi16 (__mmask32 __U, __m512i __A, __m512i __B)
1902{
1903 return (__m512i) __builtin_ia32_psrav32hi_mask ((__v32hi) __A,
1904 (__v32hi) __B,
1905 (__v32hi)
1906 _mm512_setzero_hi (),
1907 (__mmask32) __U);
1908}
1909
1910static __inline__ __m512i __DEFAULT_FN_ATTRS
1911_mm512_sra_epi16 (__m512i __A, __m128i __B)
1912{
1913 return (__m512i) __builtin_ia32_psraw512_mask ((__v32hi) __A,
1914 (__v8hi) __B,
1915 (__v32hi)
1916 _mm512_setzero_hi (),
1917 (__mmask32) -1);
1918}
1919
1920static __inline__ __m512i __DEFAULT_FN_ATTRS
1921_mm512_mask_sra_epi16 (__m512i __W, __mmask32 __U, __m512i __A,
1922 __m128i __B)
1923{
1924 return (__m512i) __builtin_ia32_psraw512_mask ((__v32hi) __A,
1925 (__v8hi) __B,
1926 (__v32hi) __W,
1927 (__mmask32) __U);
1928}
1929
1930static __inline__ __m512i __DEFAULT_FN_ATTRS
1931_mm512_maskz_sra_epi16 (__mmask32 __U, __m512i __A, __m128i __B)
1932{
1933 return (__m512i) __builtin_ia32_psraw512_mask ((__v32hi) __A,
1934 (__v8hi) __B,
1935 (__v32hi)
1936 _mm512_setzero_hi (),
1937 (__mmask32) __U);
1938}
1939
1940#define _mm512_srai_epi16(A, B) __extension__ ({ \
1941 (__m512i)__builtin_ia32_psrawi512_mask((__v32hi)(__m512i)(A), (int)(B), \
1942 (__v32hi)_mm512_setzero_hi(), \
1943 (__mmask32)-1); })
1944
1945#define _mm512_mask_srai_epi16(W, U, A, B) __extension__ ({ \
1946 (__m512i)__builtin_ia32_psrawi512_mask((__v32hi)(__m512i)(A), (int)(B), \
1947 (__v32hi)(__m512i)(W), \
1948 (__mmask32)(U)); })
1949
1950#define _mm512_maskz_srai_epi16(U, A, B) __extension__ ({ \
1951 (__m512i)__builtin_ia32_psrawi512_mask((__v32hi)(__m512i)(A), (int)(B), \
1952 (__v32hi)_mm512_setzero_hi(), \
1953 (__mmask32)(U)); })
1954
1955
1956static __inline__ __m512i __DEFAULT_FN_ATTRS
1957_mm512_srl_epi16 (__m512i __A, __m128i __B)
1958{
1959 return (__m512i) __builtin_ia32_psrlw512_mask ((__v32hi) __A,
1960 (__v8hi) __B,
1961 (__v32hi)
1962 _mm512_setzero_hi (),
1963 (__mmask32) -1);
1964}
1965
1966static __inline__ __m512i __DEFAULT_FN_ATTRS
1967_mm512_mask_srl_epi16 (__m512i __W, __mmask32 __U, __m512i __A,
1968 __m128i __B)
1969{
1970 return (__m512i) __builtin_ia32_psrlw512_mask ((__v32hi) __A,
1971 (__v8hi) __B,
1972 (__v32hi) __W,
1973 (__mmask32) __U);
1974}
1975
1976static __inline__ __m512i __DEFAULT_FN_ATTRS
1977_mm512_maskz_srl_epi16 (__mmask32 __U, __m512i __A, __m128i __B)
1978{
1979 return (__m512i) __builtin_ia32_psrlw512_mask ((__v32hi) __A,
1980 (__v8hi) __B,
1981 (__v32hi)
1982 _mm512_setzero_hi (),
1983 (__mmask32) __U);
1984}
1985
1986#define _mm512_srli_epi16(A, imm) __extension__ ({ \
1987 (__m512i)__builtin_ia32_psrlwi512_mask((__v32hi)(__m512i)(A), (int)(imm), \
1988 (__v32hi)_mm512_setzero_hi(), \
1989 (__mmask32)-1); })
1990
1991#define _mm512_mask_srli_epi16(W, U, A, imm) __extension__ ({ \
1992 (__m512i)__builtin_ia32_psrlwi512_mask((__v32hi)(__m512i)(A), (int)(imm), \
1993 (__v32hi)(__m512i)(W), \
1994 (__mmask32)(U)); })
1995
1996#define _mm512_maskz_srli_epi16(U, A, imm) __extension__ ({ \
1997 (__m512i)__builtin_ia32_psrlwi512_mask((__v32hi)(__m512i)(A), (int)(imm), \
1998 (__v32hi)_mm512_setzero_hi(), \
1999 (__mmask32)(U)); })
2000
2001#define _mm512_bsrli_epi128(a, imm) __extension__ ({ \
2002 (__m512i)__builtin_shufflevector( \
2003 (__v64qi)(__m512i)(a), \
2004 (__v64qi)_mm512_setzero_si512(), \
2005 ((char)(imm)&0xF0) ? 64 : (char)(imm) + ((char)(imm)>0xF ? 48 : 0), \
2006 ((char)(imm)&0xF0) ? 65 : (char)(imm) + ((char)(imm)>0xE ? 49 : 1), \
2007 ((char)(imm)&0xF0) ? 66 : (char)(imm) + ((char)(imm)>0xD ? 50 : 2), \
2008 ((char)(imm)&0xF0) ? 67 : (char)(imm) + ((char)(imm)>0xC ? 51 : 3), \
2009 ((char)(imm)&0xF0) ? 68 : (char)(imm) + ((char)(imm)>0xB ? 52 : 4), \
2010 ((char)(imm)&0xF0) ? 69 : (char)(imm) + ((char)(imm)>0xA ? 53 : 5), \
2011 ((char)(imm)&0xF0) ? 70 : (char)(imm) + ((char)(imm)>0x9 ? 54 : 6), \
2012 ((char)(imm)&0xF0) ? 71 : (char)(imm) + ((char)(imm)>0x8 ? 55 : 7), \
2013 ((char)(imm)&0xF0) ? 72 : (char)(imm) + ((char)(imm)>0x7 ? 56 : 8), \
2014 ((char)(imm)&0xF0) ? 73 : (char)(imm) + ((char)(imm)>0x6 ? 57 : 9), \
2015 ((char)(imm)&0xF0) ? 74 : (char)(imm) + ((char)(imm)>0x5 ? 58 : 10), \
2016 ((char)(imm)&0xF0) ? 75 : (char)(imm) + ((char)(imm)>0x4 ? 59 : 11), \
2017 ((char)(imm)&0xF0) ? 76 : (char)(imm) + ((char)(imm)>0x3 ? 60 : 12), \
2018 ((char)(imm)&0xF0) ? 77 : (char)(imm) + ((char)(imm)>0x2 ? 61 : 13), \
2019 ((char)(imm)&0xF0) ? 78 : (char)(imm) + ((char)(imm)>0x1 ? 62 : 14), \
2020 ((char)(imm)&0xF0) ? 79 : (char)(imm) + ((char)(imm)>0x0 ? 63 : 15), \
2021 ((char)(imm)&0xF0) ? 80 : (char)(imm) + ((char)(imm)>0xF ? 64 : 16), \
2022 ((char)(imm)&0xF0) ? 81 : (char)(imm) + ((char)(imm)>0xE ? 65 : 17), \
2023 ((char)(imm)&0xF0) ? 82 : (char)(imm) + ((char)(imm)>0xD ? 66 : 18), \
2024 ((char)(imm)&0xF0) ? 83 : (char)(imm) + ((char)(imm)>0xC ? 67 : 19), \
2025 ((char)(imm)&0xF0) ? 84 : (char)(imm) + ((char)(imm)>0xB ? 68 : 20), \
2026 ((char)(imm)&0xF0) ? 85 : (char)(imm) + ((char)(imm)>0xA ? 69 : 21), \
2027 ((char)(imm)&0xF0) ? 86 : (char)(imm) + ((char)(imm)>0x9 ? 70 : 22), \
2028 ((char)(imm)&0xF0) ? 87 : (char)(imm) + ((char)(imm)>0x8 ? 71 : 23), \
2029 ((char)(imm)&0xF0) ? 88 : (char)(imm) + ((char)(imm)>0x7 ? 72 : 24), \
2030 ((char)(imm)&0xF0) ? 89 : (char)(imm) + ((char)(imm)>0x6 ? 73 : 25), \
2031 ((char)(imm)&0xF0) ? 90 : (char)(imm) + ((char)(imm)>0x5 ? 74 : 26), \
2032 ((char)(imm)&0xF0) ? 91 : (char)(imm) + ((char)(imm)>0x4 ? 75 : 27), \
2033 ((char)(imm)&0xF0) ? 92 : (char)(imm) + ((char)(imm)>0x3 ? 76 : 28), \
2034 ((char)(imm)&0xF0) ? 93 : (char)(imm) + ((char)(imm)>0x2 ? 77 : 29), \
2035 ((char)(imm)&0xF0) ? 94 : (char)(imm) + ((char)(imm)>0x1 ? 78 : 30), \
2036 ((char)(imm)&0xF0) ? 95 : (char)(imm) + ((char)(imm)>0x0 ? 79 : 31), \
2037 ((char)(imm)&0xF0) ? 96 : (char)(imm) + ((char)(imm)>0xF ? 80 : 32), \
2038 ((char)(imm)&0xF0) ? 97 : (char)(imm) + ((char)(imm)>0xE ? 81 : 33), \
2039 ((char)(imm)&0xF0) ? 98 : (char)(imm) + ((char)(imm)>0xD ? 82 : 34), \
2040 ((char)(imm)&0xF0) ? 99 : (char)(imm) + ((char)(imm)>0xC ? 83 : 35), \
2041 ((char)(imm)&0xF0) ? 100 : (char)(imm) + ((char)(imm)>0xB ? 84 : 36), \
2042 ((char)(imm)&0xF0) ? 101 : (char)(imm) + ((char)(imm)>0xA ? 85 : 37), \
2043 ((char)(imm)&0xF0) ? 102 : (char)(imm) + ((char)(imm)>0x9 ? 86 : 38), \
2044 ((char)(imm)&0xF0) ? 103 : (char)(imm) + ((char)(imm)>0x8 ? 87 : 39), \
2045 ((char)(imm)&0xF0) ? 104 : (char)(imm) + ((char)(imm)>0x7 ? 88 : 40), \
2046 ((char)(imm)&0xF0) ? 105 : (char)(imm) + ((char)(imm)>0x6 ? 89 : 41), \
2047 ((char)(imm)&0xF0) ? 106 : (char)(imm) + ((char)(imm)>0x5 ? 90 : 42), \
2048 ((char)(imm)&0xF0) ? 107 : (char)(imm) + ((char)(imm)>0x4 ? 91 : 43), \
2049 ((char)(imm)&0xF0) ? 108 : (char)(imm) + ((char)(imm)>0x3 ? 92 : 44), \
2050 ((char)(imm)&0xF0) ? 109 : (char)(imm) + ((char)(imm)>0x2 ? 93 : 45), \
2051 ((char)(imm)&0xF0) ? 110 : (char)(imm) + ((char)(imm)>0x1 ? 94 : 46), \
2052 ((char)(imm)&0xF0) ? 111 : (char)(imm) + ((char)(imm)>0x0 ? 95 : 47), \
2053 ((char)(imm)&0xF0) ? 112 : (char)(imm) + ((char)(imm)>0xF ? 96 : 48), \
2054 ((char)(imm)&0xF0) ? 113 : (char)(imm) + ((char)(imm)>0xE ? 97 : 49), \
2055 ((char)(imm)&0xF0) ? 114 : (char)(imm) + ((char)(imm)>0xD ? 98 : 50), \
2056 ((char)(imm)&0xF0) ? 115 : (char)(imm) + ((char)(imm)>0xC ? 99 : 51), \
2057 ((char)(imm)&0xF0) ? 116 : (char)(imm) + ((char)(imm)>0xB ? 100 : 52), \
2058 ((char)(imm)&0xF0) ? 117 : (char)(imm) + ((char)(imm)>0xA ? 101 : 53), \
2059 ((char)(imm)&0xF0) ? 118 : (char)(imm) + ((char)(imm)>0x9 ? 102 : 54), \
2060 ((char)(imm)&0xF0) ? 119 : (char)(imm) + ((char)(imm)>0x8 ? 103 : 55), \
2061 ((char)(imm)&0xF0) ? 120 : (char)(imm) + ((char)(imm)>0x7 ? 104 : 56), \
2062 ((char)(imm)&0xF0) ? 121 : (char)(imm) + ((char)(imm)>0x6 ? 105 : 57), \
2063 ((char)(imm)&0xF0) ? 122 : (char)(imm) + ((char)(imm)>0x5 ? 106 : 58), \
2064 ((char)(imm)&0xF0) ? 123 : (char)(imm) + ((char)(imm)>0x4 ? 107 : 59), \
2065 ((char)(imm)&0xF0) ? 124 : (char)(imm) + ((char)(imm)>0x3 ? 108 : 60), \
2066 ((char)(imm)&0xF0) ? 125 : (char)(imm) + ((char)(imm)>0x2 ? 109 : 61), \
2067 ((char)(imm)&0xF0) ? 126 : (char)(imm) + ((char)(imm)>0x1 ? 110 : 62), \
2068 ((char)(imm)&0xF0) ? 127 : (char)(imm) + ((char)(imm)>0x0 ? 111 : 63)); })
2069
2070static __inline__ __m512i __DEFAULT_FN_ATTRS
2071_mm512_mask_mov_epi16 (__m512i __W, __mmask32 __U, __m512i __A)
2072{
2073 return (__m512i) __builtin_ia32_selectw_512 ((__mmask32) __U,
2074 (__v32hi) __A,
2075 (__v32hi) __W);
2076}
2077
2078static __inline__ __m512i __DEFAULT_FN_ATTRS
2079_mm512_maskz_mov_epi16 (__mmask32 __U, __m512i __A)
2080{
2081 return (__m512i) __builtin_ia32_selectw_512 ((__mmask32) __U,
2082 (__v32hi) __A,
2083 (__v32hi) _mm512_setzero_hi ());
2084}
2085
2086static __inline__ __m512i __DEFAULT_FN_ATTRS
2087_mm512_mask_mov_epi8 (__m512i __W, __mmask64 __U, __m512i __A)
2088{
2089 return (__m512i) __builtin_ia32_selectb_512 ((__mmask64) __U,
2090 (__v64qi) __A,
2091 (__v64qi) __W);
2092}
2093
2094static __inline__ __m512i __DEFAULT_FN_ATTRS
2095_mm512_maskz_mov_epi8 (__mmask64 __U, __m512i __A)
2096{
2097 return (__m512i) __builtin_ia32_selectb_512 ((__mmask64) __U,
2098 (__v64qi) __A,
2099 (__v64qi) _mm512_setzero_hi ());
2100}
2101
2102static __inline__ __m512i __DEFAULT_FN_ATTRS
2103_mm512_mask_set1_epi8 (__m512i __O, __mmask64 __M, char __A)
2104{
2105 return (__m512i) __builtin_ia32_pbroadcastb512_gpr_mask (__A,
2106 (__v64qi) __O,
2107 __M);
2108}
2109
2110static __inline__ __m512i __DEFAULT_FN_ATTRS
2111_mm512_maskz_set1_epi8 (__mmask64 __M, char __A)
2112{
2113 return (__m512i) __builtin_ia32_pbroadcastb512_gpr_mask (__A,
2114 (__v64qi)
2115 _mm512_setzero_qi(),
2116 __M);
2117}
2118
2119static __inline__ __mmask64 __DEFAULT_FN_ATTRS
2120_mm512_kunpackd (__mmask64 __A, __mmask64 __B)
2121{
2122 return (__mmask64) __builtin_ia32_kunpckdi ((__mmask64) __A,
2123 (__mmask64) __B);
2124}
2125
2126static __inline__ __mmask32 __DEFAULT_FN_ATTRS
2127_mm512_kunpackw (__mmask32 __A, __mmask32 __B)
2128{
2129 return (__mmask32) __builtin_ia32_kunpcksi ((__mmask32) __A,
2130 (__mmask32) __B);
2131}
2132
2133static __inline__ __m512i __DEFAULT_FN_ATTRS
2134_mm512_mask_loadu_epi16 (__m512i __W, __mmask32 __U, void const *__P)
2135{
2136 return (__m512i) __builtin_ia32_loaddquhi512_mask ((__v32hi *) __P,
2137 (__v32hi) __W,
2138 (__mmask32) __U);
2139}
2140
2141static __inline__ __m512i __DEFAULT_FN_ATTRS
2142_mm512_maskz_loadu_epi16 (__mmask32 __U, void const *__P)
2143{
2144 return (__m512i) __builtin_ia32_loaddquhi512_mask ((__v32hi *) __P,
2145 (__v32hi)
2146 _mm512_setzero_hi (),
2147 (__mmask32) __U);
2148}
2149
2150static __inline__ __m512i __DEFAULT_FN_ATTRS
2151_mm512_mask_loadu_epi8 (__m512i __W, __mmask64 __U, void const *__P)
2152{
2153 return (__m512i) __builtin_ia32_loaddquqi512_mask ((__v64qi *) __P,
2154 (__v64qi) __W,
2155 (__mmask64) __U);
2156}
2157
2158static __inline__ __m512i __DEFAULT_FN_ATTRS
2159_mm512_maskz_loadu_epi8 (__mmask64 __U, void const *__P)
2160{
2161 return (__m512i) __builtin_ia32_loaddquqi512_mask ((__v64qi *) __P,
2162 (__v64qi)
2163 _mm512_setzero_hi (),
2164 (__mmask64) __U);
2165}
2166static __inline__ void __DEFAULT_FN_ATTRS
2167_mm512_mask_storeu_epi16 (void *__P, __mmask32 __U, __m512i __A)
2168{
2169 __builtin_ia32_storedquhi512_mask ((__v32hi *) __P,
2170 (__v32hi) __A,
2171 (__mmask32) __U);
2172}
2173
2174static __inline__ void __DEFAULT_FN_ATTRS
2175_mm512_mask_storeu_epi8 (void *__P, __mmask64 __U, __m512i __A)
2176{
2177 __builtin_ia32_storedquqi512_mask ((__v64qi *) __P,
2178 (__v64qi) __A,
2179 (__mmask64) __U);
2180}
2181
2182static __inline__ __mmask64 __DEFAULT_FN_ATTRS
2183_mm512_test_epi8_mask (__m512i __A, __m512i __B)
2184{
2185 return (__mmask64) __builtin_ia32_ptestmb512 ((__v64qi) __A,
2186 (__v64qi) __B,
2187 (__mmask64) -1);
2188}
2189
2190static __inline__ __mmask64 __DEFAULT_FN_ATTRS
2191_mm512_mask_test_epi8_mask (__mmask64 __U, __m512i __A, __m512i __B)
2192{
2193 return (__mmask64) __builtin_ia32_ptestmb512 ((__v64qi) __A,
2194 (__v64qi) __B, __U);
2195}
2196
2197static __inline__ __mmask32 __DEFAULT_FN_ATTRS
2198_mm512_test_epi16_mask (__m512i __A, __m512i __B)
2199{
2200 return (__mmask32) __builtin_ia32_ptestmw512 ((__v32hi) __A,
2201 (__v32hi) __B,
2202 (__mmask32) -1);
2203}
2204
2205static __inline__ __mmask32 __DEFAULT_FN_ATTRS
2206_mm512_mask_test_epi16_mask (__mmask32 __U, __m512i __A, __m512i __B)
2207{
2208 return (__mmask32) __builtin_ia32_ptestmw512 ((__v32hi) __A,
2209 (__v32hi) __B, __U);
2210}
2211
2212static __inline__ __mmask64 __DEFAULT_FN_ATTRS
2213_mm512_testn_epi8_mask (__m512i __A, __m512i __B)
2214{
2215 return (__mmask64) __builtin_ia32_ptestnmb512 ((__v64qi) __A,
2216 (__v64qi) __B,
2217 (__mmask64) -1);
2218}
2219
2220static __inline__ __mmask64 __DEFAULT_FN_ATTRS
2221_mm512_mask_testn_epi8_mask (__mmask64 __U, __m512i __A, __m512i __B)
2222{
2223 return (__mmask64) __builtin_ia32_ptestnmb512 ((__v64qi) __A,
2224 (__v64qi) __B, __U);
2225}
2226
2227static __inline__ __mmask32 __DEFAULT_FN_ATTRS
2228_mm512_testn_epi16_mask (__m512i __A, __m512i __B)
2229{
2230 return (__mmask32) __builtin_ia32_ptestnmw512 ((__v32hi) __A,
2231 (__v32hi) __B,
2232 (__mmask32) -1);
2233}
2234
2235static __inline__ __mmask32 __DEFAULT_FN_ATTRS
2236_mm512_mask_testn_epi16_mask (__mmask32 __U, __m512i __A, __m512i __B)
2237{
2238 return (__mmask32) __builtin_ia32_ptestnmw512 ((__v32hi) __A,
2239 (__v32hi) __B, __U);
2240}
2241
2242static __inline__ __mmask64 __DEFAULT_FN_ATTRS
2243_mm512_movepi8_mask (__m512i __A)
2244{
2245 return (__mmask64) __builtin_ia32_cvtb2mask512 ((__v64qi) __A);
2246}
2247
2248static __inline__ __mmask32 __DEFAULT_FN_ATTRS
2249_mm512_movepi16_mask (__m512i __A)
2250{
2251 return (__mmask32) __builtin_ia32_cvtw2mask512 ((__v32hi) __A);
2252}
2253
2254static __inline__ __m512i __DEFAULT_FN_ATTRS
2255_mm512_movm_epi8 (__mmask64 __A)
2256{
2257 return (__m512i) __builtin_ia32_cvtmask2b512 (__A);
2258}
2259
2260static __inline__ __m512i __DEFAULT_FN_ATTRS
2261_mm512_movm_epi16 (__mmask32 __A)
2262{
2263 return (__m512i) __builtin_ia32_cvtmask2w512 (__A);
2264}
2265
2266static __inline__ __m512i __DEFAULT_FN_ATTRS
2267_mm512_broadcastb_epi8 (__m128i __A)
2268{
2269 return (__m512i)__builtin_shufflevector((__v16qi) __A,
2270 (__v16qi)_mm_undefined_si128(),
2271 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2272 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2273 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2274 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0);
2275}
2276
2277static __inline__ __m512i __DEFAULT_FN_ATTRS
2278_mm512_mask_broadcastb_epi8 (__m512i __O, __mmask64 __M, __m128i __A)
2279{
2280 return (__m512i)__builtin_ia32_selectb_512(__M,
2281 (__v64qi) _mm512_broadcastb_epi8(__A),
2282 (__v64qi) __O);
2283}
2284
2285static __inline__ __m512i __DEFAULT_FN_ATTRS
2286_mm512_maskz_broadcastb_epi8 (__mmask64 __M, __m128i __A)
2287{
2288 return (__m512i)__builtin_ia32_selectb_512(__M,
2289 (__v64qi) _mm512_broadcastb_epi8(__A),
2290 (__v64qi) _mm512_setzero_si512());
2291}
2292
2293static __inline__ __m512i __DEFAULT_FN_ATTRS
2294_mm512_mask_set1_epi16 (__m512i __O, __mmask32 __M, short __A)
2295{
2296 return (__m512i) __builtin_ia32_pbroadcastw512_gpr_mask (__A,
2297 (__v32hi) __O,
2298 __M);
2299}
2300
2301static __inline__ __m512i __DEFAULT_FN_ATTRS
2302_mm512_maskz_set1_epi16 (__mmask32 __M, short __A)
2303{
2304 return (__m512i) __builtin_ia32_pbroadcastw512_gpr_mask (__A,
2305 (__v32hi) _mm512_setzero_hi(),
2306 __M);
2307}
2308
2309static __inline__ __m512i __DEFAULT_FN_ATTRS
2310_mm512_broadcastw_epi16 (__m128i __A)
2311{
2312 return (__m512i)__builtin_shufflevector((__v8hi) __A,
2313 (__v8hi)_mm_undefined_si128(),
2314 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2315 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0);
2316}
2317
2318static __inline__ __m512i __DEFAULT_FN_ATTRS
2319_mm512_mask_broadcastw_epi16 (__m512i __O, __mmask32 __M, __m128i __A)
2320{
2321 return (__m512i)__builtin_ia32_selectw_512(__M,
2322 (__v32hi) _mm512_broadcastw_epi16(__A),
2323 (__v32hi) __O);
2324}
2325
2326static __inline__ __m512i __DEFAULT_FN_ATTRS
2327_mm512_maskz_broadcastw_epi16 (__mmask32 __M, __m128i __A)
2328{
2329 return (__m512i)__builtin_ia32_selectw_512(__M,
2330 (__v32hi) _mm512_broadcastw_epi16(__A),
2331 (__v32hi) _mm512_setzero_si512());
2332}
2333
2334static __inline__ __m512i __DEFAULT_FN_ATTRS
2335_mm512_permutexvar_epi16 (__m512i __A, __m512i __B)
2336{
2337 return (__m512i) __builtin_ia32_permvarhi512_mask ((__v32hi) __B,
2338 (__v32hi) __A,
2339 (__v32hi) _mm512_undefined_epi32 (),
2340 (__mmask32) -1);
2341}
2342
2343static __inline__ __m512i __DEFAULT_FN_ATTRS
2344_mm512_maskz_permutexvar_epi16 (__mmask32 __M, __m512i __A,
2345 __m512i __B)
2346{
2347 return (__m512i) __builtin_ia32_permvarhi512_mask ((__v32hi) __B,
2348 (__v32hi) __A,
2349 (__v32hi) _mm512_setzero_hi(),
2350 (__mmask32) __M);
2351}
2352
2353static __inline__ __m512i __DEFAULT_FN_ATTRS
2354_mm512_mask_permutexvar_epi16 (__m512i __W, __mmask32 __M, __m512i __A,
2355 __m512i __B)
2356{
2357 return (__m512i) __builtin_ia32_permvarhi512_mask ((__v32hi) __B,
2358 (__v32hi) __A,
2359 (__v32hi) __W,
2360 (__mmask32) __M);
2361}
2362
2363#define _mm512_alignr_epi8(A, B, N) __extension__ ({\
2364 (__m512i)__builtin_ia32_palignr512_mask((__v64qi)(__m512i)(A), \
2365 (__v64qi)(__m512i)(B), (int)(N), \
2366 (__v64qi)_mm512_undefined_pd(), \
2367 (__mmask64)-1); })
2368
2369#define _mm512_mask_alignr_epi8(W, U, A, B, N) __extension__({\
2370 (__m512i)__builtin_ia32_palignr512_mask((__v64qi)(__m512i)(A), \
2371 (__v64qi)(__m512i)(B), (int)(N), \
2372 (__v64qi)(__m512i)(W), \
2373 (__mmask64)(U)); })
2374
2375#define _mm512_maskz_alignr_epi8(U, A, B, N) __extension__({\
2376 (__m512i)__builtin_ia32_palignr512_mask((__v64qi)(__m512i)(A), \
2377 (__v64qi)(__m512i)(B), (int)(N), \
2378 (__v64qi)_mm512_setzero_si512(), \
2379 (__mmask64)(U)); })
2380
2381#define _mm512_dbsad_epu8(A, B, imm) __extension__ ({\
2382 (__m512i)__builtin_ia32_dbpsadbw512_mask((__v64qi)(__m512i)(A), \
2383 (__v64qi)(__m512i)(B), (int)(imm), \
2384 (__v32hi)_mm512_undefined_epi32(), \
2385 (__mmask32)-1); })
2386
2387#define _mm512_mask_dbsad_epu8(W, U, A, B, imm) ({\
2388 (__m512i)__builtin_ia32_dbpsadbw512_mask((__v64qi)(__m512i)(A), \
2389 (__v64qi)(__m512i)(B), (int)(imm), \
2390 (__v32hi)(__m512i)(W), \
2391 (__mmask32)(U)); })
2392
2393#define _mm512_maskz_dbsad_epu8(U, A, B, imm) ({\
2394 (__m512i)__builtin_ia32_dbpsadbw512_mask((__v64qi)(__m512i)(A), \
2395 (__v64qi)(__m512i)(B), (int)(imm), \
2396 (__v32hi)_mm512_setzero_hi(), \
2397 (__mmask32)(U)); })
2398
2399static __inline__ __m512i __DEFAULT_FN_ATTRS
2400_mm512_sad_epu8 (__m512i __A, __m512i __B)
2401{
2402 return (__m512i) __builtin_ia32_psadbw512 ((__v64qi) __A,
2403 (__v64qi) __B);
2404}
2405
Stephen Hinesb4d9c8b2015-03-30 16:04:04 -0700[diff] [blame]2406
Pirama Arumuga Nainar4e74a022016-03-17 18:03:02 -0700[diff] [blame]2407
2408#undef __DEFAULT_FN_ATTRS
2409
Stephen Hinesee4ca282014-12-02 17:05:12 -0800[diff] [blame]2410#endif