Meng Wang | 61af684 | 2018-09-10 17:47:55 +0800 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0 |
Laxminath Kasam | 989fccf | 2018-06-15 16:53:31 +0530 | [diff] [blame] | 2 | /* Copyright (c) 2018, The Linux Foundation. All rights reserved. |
Laxminath Kasam | 989fccf | 2018-06-15 16:53:31 +0530 | [diff] [blame] | 3 | */ |
| 4 | |
| 5 | #include <linux/module.h> |
| 6 | #include <linux/init.h> |
| 7 | #include <linux/clk.h> |
| 8 | #include <linux/io.h> |
| 9 | #include <linux/platform_device.h> |
| 10 | #include <linux/regmap.h> |
| 11 | #include <sound/soc.h> |
| 12 | #include <sound/soc-dapm.h> |
| 13 | #include <sound/tlv.h> |
Laxminath Kasam | fb0d683 | 2018-09-22 01:49:52 +0530 | [diff] [blame] | 14 | #include <soc/swr-wcd.h> |
Laxminath Kasam | 989fccf | 2018-06-15 16:53:31 +0530 | [diff] [blame] | 15 | #include "bolero-cdc.h" |
| 16 | #include "bolero-cdc-registers.h" |
| 17 | #include "../msm-cdc-pinctrl.h" |
| 18 | |
| 19 | #define TX_MACRO_MAX_OFFSET 0x1000 |
| 20 | |
| 21 | #define NUM_DECIMATORS 8 |
| 22 | |
| 23 | #define TX_MACRO_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 |\ |
| 24 | SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_48000 |\ |
| 25 | SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_192000) |
| 26 | #define TX_MACRO_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\ |
| 27 | SNDRV_PCM_FMTBIT_S24_LE |\ |
| 28 | SNDRV_PCM_FMTBIT_S24_3LE) |
| 29 | |
| 30 | #define TX_HPF_CUT_OFF_FREQ_MASK 0x60 |
| 31 | #define CF_MIN_3DB_4HZ 0x0 |
| 32 | #define CF_MIN_3DB_75HZ 0x1 |
| 33 | #define CF_MIN_3DB_150HZ 0x2 |
| 34 | |
| 35 | #define TX_MACRO_DMIC_SAMPLE_RATE_UNDEFINED 0 |
| 36 | #define TX_MACRO_MCLK_FREQ 9600000 |
| 37 | #define TX_MACRO_TX_PATH_OFFSET 0x80 |
Laxminath Kasam | 497a651 | 2018-09-17 16:11:52 +0530 | [diff] [blame] | 38 | #define TX_MACRO_SWR_MIC_MUX_SEL_MASK 0xF |
| 39 | #define TX_MACRO_ADC_MUX_CFG_OFFSET 0x2 |
Laxminath Kasam | 989fccf | 2018-06-15 16:53:31 +0530 | [diff] [blame] | 40 | |
| 41 | #define TX_MACRO_TX_UNMUTE_DELAY_MS 40 |
| 42 | |
| 43 | static int tx_unmute_delay = TX_MACRO_TX_UNMUTE_DELAY_MS; |
| 44 | module_param(tx_unmute_delay, int, 0664); |
| 45 | MODULE_PARM_DESC(tx_unmute_delay, "delay to unmute the tx path"); |
| 46 | |
| 47 | static const DECLARE_TLV_DB_SCALE(digital_gain, 0, 1, 0); |
| 48 | |
| 49 | static int tx_macro_hw_params(struct snd_pcm_substream *substream, |
| 50 | struct snd_pcm_hw_params *params, |
| 51 | struct snd_soc_dai *dai); |
| 52 | static int tx_macro_get_channel_map(struct snd_soc_dai *dai, |
| 53 | unsigned int *tx_num, unsigned int *tx_slot, |
| 54 | unsigned int *rx_num, unsigned int *rx_slot); |
| 55 | |
| 56 | #define TX_MACRO_SWR_STRING_LEN 80 |
| 57 | #define TX_MACRO_CHILD_DEVICES_MAX 3 |
| 58 | |
| 59 | /* Hold instance to soundwire platform device */ |
| 60 | struct tx_macro_swr_ctrl_data { |
| 61 | struct platform_device *tx_swr_pdev; |
| 62 | }; |
| 63 | |
| 64 | struct tx_macro_swr_ctrl_platform_data { |
| 65 | void *handle; /* holds codec private data */ |
| 66 | int (*read)(void *handle, int reg); |
| 67 | int (*write)(void *handle, int reg, int val); |
| 68 | int (*bulk_write)(void *handle, u32 *reg, u32 *val, size_t len); |
| 69 | int (*clk)(void *handle, bool enable); |
| 70 | int (*handle_irq)(void *handle, |
| 71 | irqreturn_t (*swrm_irq_handler)(int irq, |
| 72 | void *data), |
| 73 | void *swrm_handle, |
| 74 | int action); |
| 75 | }; |
| 76 | |
| 77 | enum { |
Laxminath Kasam | 59c7a1d | 2018-08-09 16:11:17 +0530 | [diff] [blame] | 78 | TX_MACRO_AIF_INVALID = 0, |
| 79 | TX_MACRO_AIF1_CAP, |
Laxminath Kasam | 989fccf | 2018-06-15 16:53:31 +0530 | [diff] [blame] | 80 | TX_MACRO_AIF2_CAP, |
| 81 | TX_MACRO_MAX_DAIS |
| 82 | }; |
| 83 | |
| 84 | enum { |
| 85 | TX_MACRO_DEC0, |
| 86 | TX_MACRO_DEC1, |
| 87 | TX_MACRO_DEC2, |
| 88 | TX_MACRO_DEC3, |
| 89 | TX_MACRO_DEC4, |
| 90 | TX_MACRO_DEC5, |
| 91 | TX_MACRO_DEC6, |
| 92 | TX_MACRO_DEC7, |
| 93 | TX_MACRO_DEC_MAX, |
| 94 | }; |
| 95 | |
| 96 | enum { |
| 97 | TX_MACRO_CLK_DIV_2, |
| 98 | TX_MACRO_CLK_DIV_3, |
| 99 | TX_MACRO_CLK_DIV_4, |
| 100 | TX_MACRO_CLK_DIV_6, |
| 101 | TX_MACRO_CLK_DIV_8, |
| 102 | TX_MACRO_CLK_DIV_16, |
| 103 | }; |
| 104 | |
Laxminath Kasam | 497a651 | 2018-09-17 16:11:52 +0530 | [diff] [blame] | 105 | enum { |
| 106 | MSM_DMIC, |
| 107 | SWR_MIC, |
| 108 | ANC_FB_TUNE1 |
| 109 | }; |
| 110 | |
Laxminath Kasam | 989fccf | 2018-06-15 16:53:31 +0530 | [diff] [blame] | 111 | struct tx_mute_work { |
| 112 | struct tx_macro_priv *tx_priv; |
| 113 | u32 decimator; |
| 114 | struct delayed_work dwork; |
| 115 | }; |
| 116 | |
| 117 | struct hpf_work { |
| 118 | struct tx_macro_priv *tx_priv; |
| 119 | u8 decimator; |
| 120 | u8 hpf_cut_off_freq; |
| 121 | struct delayed_work dwork; |
| 122 | }; |
| 123 | |
| 124 | struct tx_macro_priv { |
| 125 | struct device *dev; |
| 126 | bool dec_active[NUM_DECIMATORS]; |
| 127 | int tx_mclk_users; |
| 128 | int swr_clk_users; |
| 129 | struct clk *tx_core_clk; |
| 130 | struct clk *tx_npl_clk; |
| 131 | struct mutex mclk_lock; |
| 132 | struct mutex swr_clk_lock; |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame^] | 133 | struct snd_soc_component *component; |
Laxminath Kasam | 989fccf | 2018-06-15 16:53:31 +0530 | [diff] [blame] | 134 | struct device_node *tx_swr_gpio_p; |
| 135 | struct tx_macro_swr_ctrl_data *swr_ctrl_data; |
| 136 | struct tx_macro_swr_ctrl_platform_data swr_plat_data; |
| 137 | struct work_struct tx_macro_add_child_devices_work; |
| 138 | struct hpf_work tx_hpf_work[NUM_DECIMATORS]; |
| 139 | struct tx_mute_work tx_mute_dwork[NUM_DECIMATORS]; |
| 140 | s32 dmic_0_1_clk_cnt; |
| 141 | s32 dmic_2_3_clk_cnt; |
| 142 | s32 dmic_4_5_clk_cnt; |
| 143 | s32 dmic_6_7_clk_cnt; |
| 144 | u16 dmic_clk_div; |
| 145 | unsigned long active_ch_mask[TX_MACRO_MAX_DAIS]; |
| 146 | unsigned long active_ch_cnt[TX_MACRO_MAX_DAIS]; |
| 147 | char __iomem *tx_io_base; |
| 148 | struct platform_device *pdev_child_devices |
| 149 | [TX_MACRO_CHILD_DEVICES_MAX]; |
| 150 | int child_count; |
| 151 | }; |
| 152 | |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame^] | 153 | static bool tx_macro_get_data(struct snd_soc_component *component, |
Laxminath Kasam | 989fccf | 2018-06-15 16:53:31 +0530 | [diff] [blame] | 154 | struct device **tx_dev, |
| 155 | struct tx_macro_priv **tx_priv, |
| 156 | const char *func_name) |
| 157 | { |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame^] | 158 | *tx_dev = bolero_get_device_ptr(component->dev, TX_MACRO); |
Laxminath Kasam | 989fccf | 2018-06-15 16:53:31 +0530 | [diff] [blame] | 159 | if (!(*tx_dev)) { |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame^] | 160 | dev_err(component->dev, |
Laxminath Kasam | 989fccf | 2018-06-15 16:53:31 +0530 | [diff] [blame] | 161 | "%s: null device for macro!\n", func_name); |
| 162 | return false; |
| 163 | } |
| 164 | |
| 165 | *tx_priv = dev_get_drvdata((*tx_dev)); |
| 166 | if (!(*tx_priv)) { |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame^] | 167 | dev_err(component->dev, |
Laxminath Kasam | 989fccf | 2018-06-15 16:53:31 +0530 | [diff] [blame] | 168 | "%s: priv is null for macro!\n", func_name); |
| 169 | return false; |
| 170 | } |
| 171 | |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame^] | 172 | if (!(*tx_priv)->component) { |
| 173 | dev_err(component->dev, |
| 174 | "%s: tx_priv->component not initialized!\n", func_name); |
Laxminath Kasam | 989fccf | 2018-06-15 16:53:31 +0530 | [diff] [blame] | 175 | return false; |
| 176 | } |
| 177 | |
| 178 | return true; |
| 179 | } |
| 180 | |
| 181 | static int tx_macro_mclk_enable(struct tx_macro_priv *tx_priv, |
| 182 | bool mclk_enable) |
| 183 | { |
| 184 | struct regmap *regmap = dev_get_regmap(tx_priv->dev->parent, NULL); |
| 185 | int ret = 0; |
| 186 | |
Tanya Dixit | 8530fb9 | 2018-09-14 16:01:25 +0530 | [diff] [blame] | 187 | if (regmap == NULL) { |
| 188 | dev_err(tx_priv->dev, "%s: regmap is NULL\n", __func__); |
| 189 | return -EINVAL; |
| 190 | } |
| 191 | |
Laxminath Kasam | b7f823c | 2018-08-02 13:23:11 +0530 | [diff] [blame] | 192 | dev_dbg(tx_priv->dev, "%s: mclk_enable = %u,clk_users= %d\n", |
| 193 | __func__, mclk_enable, tx_priv->tx_mclk_users); |
Laxminath Kasam | 989fccf | 2018-06-15 16:53:31 +0530 | [diff] [blame] | 194 | |
| 195 | mutex_lock(&tx_priv->mclk_lock); |
| 196 | if (mclk_enable) { |
| 197 | if (tx_priv->tx_mclk_users == 0) { |
| 198 | ret = bolero_request_clock(tx_priv->dev, |
| 199 | TX_MACRO, MCLK_MUX0, true); |
| 200 | if (ret < 0) { |
| 201 | dev_err(tx_priv->dev, |
| 202 | "%s: request clock enable failed\n", |
| 203 | __func__); |
| 204 | goto exit; |
| 205 | } |
| 206 | regcache_mark_dirty(regmap); |
| 207 | regcache_sync_region(regmap, |
| 208 | TX_START_OFFSET, |
| 209 | TX_MAX_OFFSET); |
| 210 | /* 9.6MHz MCLK, set value 0x00 if other frequency */ |
| 211 | regmap_update_bits(regmap, |
| 212 | BOLERO_CDC_TX_TOP_CSR_FREQ_MCLK, 0x01, 0x01); |
| 213 | regmap_update_bits(regmap, |
| 214 | BOLERO_CDC_TX_CLK_RST_CTRL_MCLK_CONTROL, |
| 215 | 0x01, 0x01); |
| 216 | regmap_update_bits(regmap, |
| 217 | BOLERO_CDC_TX_CLK_RST_CTRL_FS_CNT_CONTROL, |
| 218 | 0x01, 0x01); |
| 219 | } |
| 220 | tx_priv->tx_mclk_users++; |
| 221 | } else { |
| 222 | if (tx_priv->tx_mclk_users <= 0) { |
| 223 | dev_err(tx_priv->dev, "%s: clock already disabled\n", |
| 224 | __func__); |
| 225 | tx_priv->tx_mclk_users = 0; |
| 226 | goto exit; |
| 227 | } |
| 228 | tx_priv->tx_mclk_users--; |
| 229 | if (tx_priv->tx_mclk_users == 0) { |
| 230 | regmap_update_bits(regmap, |
| 231 | BOLERO_CDC_TX_CLK_RST_CTRL_FS_CNT_CONTROL, |
| 232 | 0x01, 0x00); |
| 233 | regmap_update_bits(regmap, |
| 234 | BOLERO_CDC_TX_CLK_RST_CTRL_MCLK_CONTROL, |
| 235 | 0x01, 0x00); |
| 236 | bolero_request_clock(tx_priv->dev, |
| 237 | TX_MACRO, MCLK_MUX0, false); |
| 238 | } |
| 239 | } |
| 240 | exit: |
| 241 | mutex_unlock(&tx_priv->mclk_lock); |
| 242 | return ret; |
| 243 | } |
| 244 | |
| 245 | static int tx_macro_mclk_event(struct snd_soc_dapm_widget *w, |
| 246 | struct snd_kcontrol *kcontrol, int event) |
| 247 | { |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame^] | 248 | struct snd_soc_component *component = |
| 249 | snd_soc_dapm_to_component(w->dapm); |
Laxminath Kasam | 989fccf | 2018-06-15 16:53:31 +0530 | [diff] [blame] | 250 | int ret = 0; |
| 251 | struct device *tx_dev = NULL; |
| 252 | struct tx_macro_priv *tx_priv = NULL; |
| 253 | |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame^] | 254 | if (!tx_macro_get_data(component, &tx_dev, &tx_priv, __func__)) |
Laxminath Kasam | 989fccf | 2018-06-15 16:53:31 +0530 | [diff] [blame] | 255 | return -EINVAL; |
| 256 | |
| 257 | dev_dbg(tx_dev, "%s: event = %d\n", __func__, event); |
| 258 | switch (event) { |
| 259 | case SND_SOC_DAPM_PRE_PMU: |
| 260 | ret = tx_macro_mclk_enable(tx_priv, 1); |
| 261 | break; |
| 262 | case SND_SOC_DAPM_POST_PMD: |
| 263 | ret = tx_macro_mclk_enable(tx_priv, 0); |
| 264 | break; |
| 265 | default: |
| 266 | dev_err(tx_priv->dev, |
| 267 | "%s: invalid DAPM event %d\n", __func__, event); |
| 268 | ret = -EINVAL; |
| 269 | } |
| 270 | return ret; |
| 271 | } |
| 272 | |
| 273 | static int tx_macro_mclk_ctrl(struct device *dev, bool enable) |
| 274 | { |
| 275 | struct tx_macro_priv *tx_priv = dev_get_drvdata(dev); |
| 276 | int ret = 0; |
| 277 | |
| 278 | if (enable) { |
| 279 | ret = clk_prepare_enable(tx_priv->tx_core_clk); |
| 280 | if (ret < 0) { |
| 281 | dev_err(dev, "%s:tx mclk enable failed\n", __func__); |
| 282 | goto exit; |
| 283 | } |
| 284 | ret = clk_prepare_enable(tx_priv->tx_npl_clk); |
| 285 | if (ret < 0) { |
| 286 | dev_err(dev, "%s:tx npl_clk enable failed\n", |
| 287 | __func__); |
| 288 | clk_disable_unprepare(tx_priv->tx_core_clk); |
| 289 | goto exit; |
| 290 | } |
| 291 | } else { |
| 292 | clk_disable_unprepare(tx_priv->tx_npl_clk); |
| 293 | clk_disable_unprepare(tx_priv->tx_core_clk); |
| 294 | } |
| 295 | |
| 296 | exit: |
| 297 | return ret; |
| 298 | } |
| 299 | |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame^] | 300 | static int tx_macro_event_handler(struct snd_soc_component *component, |
| 301 | u16 event, u32 data) |
Laxminath Kasam | fb0d683 | 2018-09-22 01:49:52 +0530 | [diff] [blame] | 302 | { |
| 303 | struct device *tx_dev = NULL; |
| 304 | struct tx_macro_priv *tx_priv = NULL; |
| 305 | |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame^] | 306 | if (!tx_macro_get_data(component, &tx_dev, &tx_priv, __func__)) |
Laxminath Kasam | fb0d683 | 2018-09-22 01:49:52 +0530 | [diff] [blame] | 307 | return -EINVAL; |
| 308 | |
| 309 | switch (event) { |
| 310 | case BOLERO_MACRO_EVT_SSR_DOWN: |
| 311 | swrm_wcd_notify( |
| 312 | tx_priv->swr_ctrl_data[0].tx_swr_pdev, |
| 313 | SWR_DEVICE_SSR_DOWN, NULL); |
| 314 | swrm_wcd_notify( |
| 315 | tx_priv->swr_ctrl_data[0].tx_swr_pdev, |
| 316 | SWR_DEVICE_DOWN, NULL); |
| 317 | break; |
| 318 | case BOLERO_MACRO_EVT_SSR_UP: |
| 319 | swrm_wcd_notify( |
| 320 | tx_priv->swr_ctrl_data[0].tx_swr_pdev, |
| 321 | SWR_DEVICE_SSR_UP, NULL); |
| 322 | break; |
| 323 | } |
| 324 | return 0; |
| 325 | } |
| 326 | |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame^] | 327 | static int tx_macro_reg_wake_irq(struct snd_soc_component *component, |
Aditya Bavanari | c4e9612 | 2018-11-14 14:46:38 +0530 | [diff] [blame] | 328 | u32 data) |
| 329 | { |
| 330 | struct device *tx_dev = NULL; |
| 331 | struct tx_macro_priv *tx_priv = NULL; |
| 332 | u32 ipc_wakeup = data; |
| 333 | int ret = 0; |
| 334 | |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame^] | 335 | if (!tx_macro_get_data(component, &tx_dev, &tx_priv, __func__)) |
Aditya Bavanari | c4e9612 | 2018-11-14 14:46:38 +0530 | [diff] [blame] | 336 | return -EINVAL; |
| 337 | |
| 338 | ret = swrm_wcd_notify( |
| 339 | tx_priv->swr_ctrl_data[0].tx_swr_pdev, |
| 340 | SWR_REGISTER_WAKE_IRQ, &ipc_wakeup); |
| 341 | |
| 342 | return ret; |
| 343 | } |
| 344 | |
Laxminath Kasam | 989fccf | 2018-06-15 16:53:31 +0530 | [diff] [blame] | 345 | static void tx_macro_tx_hpf_corner_freq_callback(struct work_struct *work) |
| 346 | { |
| 347 | struct delayed_work *hpf_delayed_work = NULL; |
| 348 | struct hpf_work *hpf_work = NULL; |
| 349 | struct tx_macro_priv *tx_priv = NULL; |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame^] | 350 | struct snd_soc_component *component = NULL; |
Laxminath Kasam | 9eb8022 | 2018-08-29 21:53:14 +0530 | [diff] [blame] | 351 | u16 dec_cfg_reg = 0, hpf_gate_reg = 0; |
Laxminath Kasam | 989fccf | 2018-06-15 16:53:31 +0530 | [diff] [blame] | 352 | u8 hpf_cut_off_freq = 0; |
Laxminath Kasam | 497a651 | 2018-09-17 16:11:52 +0530 | [diff] [blame] | 353 | u16 adc_mux_reg = 0, adc_n = 0, adc_reg = 0; |
Laxminath Kasam | 989fccf | 2018-06-15 16:53:31 +0530 | [diff] [blame] | 354 | |
| 355 | hpf_delayed_work = to_delayed_work(work); |
| 356 | hpf_work = container_of(hpf_delayed_work, struct hpf_work, dwork); |
| 357 | tx_priv = hpf_work->tx_priv; |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame^] | 358 | component = tx_priv->component; |
Laxminath Kasam | 989fccf | 2018-06-15 16:53:31 +0530 | [diff] [blame] | 359 | hpf_cut_off_freq = hpf_work->hpf_cut_off_freq; |
| 360 | |
| 361 | dec_cfg_reg = BOLERO_CDC_TX0_TX_PATH_CFG0 + |
| 362 | TX_MACRO_TX_PATH_OFFSET * hpf_work->decimator; |
Laxminath Kasam | 9eb8022 | 2018-08-29 21:53:14 +0530 | [diff] [blame] | 363 | hpf_gate_reg = BOLERO_CDC_TX0_TX_PATH_SEC2 + |
| 364 | TX_MACRO_TX_PATH_OFFSET * hpf_work->decimator; |
Laxminath Kasam | 989fccf | 2018-06-15 16:53:31 +0530 | [diff] [blame] | 365 | |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame^] | 366 | dev_dbg(component->dev, "%s: decimator %u hpf_cut_of_freq 0x%x\n", |
Laxminath Kasam | 989fccf | 2018-06-15 16:53:31 +0530 | [diff] [blame] | 367 | __func__, hpf_work->decimator, hpf_cut_off_freq); |
| 368 | |
Laxminath Kasam | 497a651 | 2018-09-17 16:11:52 +0530 | [diff] [blame] | 369 | adc_mux_reg = BOLERO_CDC_TX_INP_MUX_ADC_MUX0_CFG1 + |
| 370 | TX_MACRO_ADC_MUX_CFG_OFFSET * hpf_work->decimator; |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame^] | 371 | if (snd_soc_component_read32(component, adc_mux_reg) & SWR_MIC) { |
Laxminath Kasam | 497a651 | 2018-09-17 16:11:52 +0530 | [diff] [blame] | 372 | adc_reg = BOLERO_CDC_TX_INP_MUX_ADC_MUX0_CFG0 + |
| 373 | TX_MACRO_ADC_MUX_CFG_OFFSET * hpf_work->decimator; |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame^] | 374 | adc_n = snd_soc_component_read32(component, adc_reg) & |
Laxminath Kasam | 497a651 | 2018-09-17 16:11:52 +0530 | [diff] [blame] | 375 | TX_MACRO_SWR_MIC_MUX_SEL_MASK; |
| 376 | if (adc_n >= BOLERO_ADC_MAX) |
| 377 | goto tx_hpf_set; |
| 378 | /* analog mic clear TX hold */ |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame^] | 379 | bolero_clear_amic_tx_hold(component->dev, adc_n); |
Laxminath Kasam | 497a651 | 2018-09-17 16:11:52 +0530 | [diff] [blame] | 380 | } |
| 381 | tx_hpf_set: |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame^] | 382 | snd_soc_component_update_bits(component, |
| 383 | dec_cfg_reg, TX_HPF_CUT_OFF_FREQ_MASK, |
| 384 | hpf_cut_off_freq << 5); |
| 385 | snd_soc_component_update_bits(component, hpf_gate_reg, 0x03, 0x02); |
Laxminath Kasam | 9eb8022 | 2018-08-29 21:53:14 +0530 | [diff] [blame] | 386 | /* Minimum 1 clk cycle delay is required as per HW spec */ |
| 387 | usleep_range(1000, 1010); |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame^] | 388 | snd_soc_component_update_bits(component, hpf_gate_reg, 0x03, 0x01); |
Laxminath Kasam | 989fccf | 2018-06-15 16:53:31 +0530 | [diff] [blame] | 389 | } |
| 390 | |
| 391 | static void tx_macro_mute_update_callback(struct work_struct *work) |
| 392 | { |
| 393 | struct tx_mute_work *tx_mute_dwork = NULL; |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame^] | 394 | struct snd_soc_component *component = NULL; |
Laxminath Kasam | 989fccf | 2018-06-15 16:53:31 +0530 | [diff] [blame] | 395 | struct tx_macro_priv *tx_priv = NULL; |
| 396 | struct delayed_work *delayed_work = NULL; |
Xiaojun Sang | d155fdc | 2018-10-11 15:11:59 +0800 | [diff] [blame] | 397 | u16 tx_vol_ctl_reg = 0; |
Laxminath Kasam | 989fccf | 2018-06-15 16:53:31 +0530 | [diff] [blame] | 398 | u8 decimator = 0; |
| 399 | |
| 400 | delayed_work = to_delayed_work(work); |
| 401 | tx_mute_dwork = container_of(delayed_work, struct tx_mute_work, dwork); |
| 402 | tx_priv = tx_mute_dwork->tx_priv; |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame^] | 403 | component = tx_priv->component; |
Laxminath Kasam | 989fccf | 2018-06-15 16:53:31 +0530 | [diff] [blame] | 404 | decimator = tx_mute_dwork->decimator; |
| 405 | |
| 406 | tx_vol_ctl_reg = |
| 407 | BOLERO_CDC_TX0_TX_PATH_CTL + |
| 408 | TX_MACRO_TX_PATH_OFFSET * decimator; |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame^] | 409 | snd_soc_component_update_bits(component, tx_vol_ctl_reg, 0x10, 0x00); |
Laxminath Kasam | 989fccf | 2018-06-15 16:53:31 +0530 | [diff] [blame] | 410 | dev_dbg(tx_priv->dev, "%s: decimator %u unmute\n", |
| 411 | __func__, decimator); |
| 412 | } |
| 413 | |
| 414 | static int tx_macro_put_dec_enum(struct snd_kcontrol *kcontrol, |
| 415 | struct snd_ctl_elem_value *ucontrol) |
| 416 | { |
| 417 | struct snd_soc_dapm_widget *widget = |
| 418 | snd_soc_dapm_kcontrol_widget(kcontrol); |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame^] | 419 | struct snd_soc_component *component = |
| 420 | snd_soc_dapm_to_component(widget->dapm); |
Laxminath Kasam | 989fccf | 2018-06-15 16:53:31 +0530 | [diff] [blame] | 421 | struct soc_enum *e = (struct soc_enum *)kcontrol->private_value; |
| 422 | unsigned int val = 0; |
| 423 | u16 mic_sel_reg = 0; |
| 424 | |
| 425 | val = ucontrol->value.enumerated.item[0]; |
| 426 | if (val > e->items - 1) |
| 427 | return -EINVAL; |
| 428 | |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame^] | 429 | dev_dbg(component->dev, "%s: wname: %s, val: 0x%x\n", __func__, |
Laxminath Kasam | 989fccf | 2018-06-15 16:53:31 +0530 | [diff] [blame] | 430 | widget->name, val); |
| 431 | |
| 432 | switch (e->reg) { |
| 433 | case BOLERO_CDC_TX_INP_MUX_ADC_MUX0_CFG0: |
| 434 | mic_sel_reg = BOLERO_CDC_TX0_TX_PATH_CFG0; |
| 435 | break; |
| 436 | case BOLERO_CDC_TX_INP_MUX_ADC_MUX1_CFG0: |
| 437 | mic_sel_reg = BOLERO_CDC_TX1_TX_PATH_CFG0; |
| 438 | break; |
| 439 | case BOLERO_CDC_TX_INP_MUX_ADC_MUX2_CFG0: |
| 440 | mic_sel_reg = BOLERO_CDC_TX2_TX_PATH_CFG0; |
| 441 | break; |
| 442 | case BOLERO_CDC_TX_INP_MUX_ADC_MUX3_CFG0: |
| 443 | mic_sel_reg = BOLERO_CDC_TX3_TX_PATH_CFG0; |
| 444 | break; |
| 445 | case BOLERO_CDC_TX_INP_MUX_ADC_MUX4_CFG0: |
| 446 | mic_sel_reg = BOLERO_CDC_TX4_TX_PATH_CFG0; |
| 447 | break; |
| 448 | case BOLERO_CDC_TX_INP_MUX_ADC_MUX5_CFG0: |
| 449 | mic_sel_reg = BOLERO_CDC_TX5_TX_PATH_CFG0; |
| 450 | break; |
| 451 | case BOLERO_CDC_TX_INP_MUX_ADC_MUX6_CFG0: |
| 452 | mic_sel_reg = BOLERO_CDC_TX6_TX_PATH_CFG0; |
| 453 | break; |
| 454 | case BOLERO_CDC_TX_INP_MUX_ADC_MUX7_CFG0: |
| 455 | mic_sel_reg = BOLERO_CDC_TX7_TX_PATH_CFG0; |
| 456 | break; |
| 457 | default: |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame^] | 458 | dev_err(component->dev, "%s: e->reg: 0x%x not expected\n", |
Laxminath Kasam | 989fccf | 2018-06-15 16:53:31 +0530 | [diff] [blame] | 459 | __func__, e->reg); |
| 460 | return -EINVAL; |
| 461 | } |
Laxminath Kasam | 497a651 | 2018-09-17 16:11:52 +0530 | [diff] [blame] | 462 | if (strnstr(widget->name, "SMIC", strlen(widget->name))) { |
Laxminath Kasam | 989fccf | 2018-06-15 16:53:31 +0530 | [diff] [blame] | 463 | if (val != 0) { |
| 464 | if (val < 5) |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame^] | 465 | snd_soc_component_update_bits(component, |
| 466 | mic_sel_reg, |
Laxminath Kasam | 989fccf | 2018-06-15 16:53:31 +0530 | [diff] [blame] | 467 | 1 << 7, 0x0 << 7); |
| 468 | else |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame^] | 469 | snd_soc_component_update_bits(component, |
| 470 | mic_sel_reg, |
Laxminath Kasam | 989fccf | 2018-06-15 16:53:31 +0530 | [diff] [blame] | 471 | 1 << 7, 0x1 << 7); |
| 472 | } |
| 473 | } else { |
| 474 | /* DMIC selected */ |
| 475 | if (val != 0) |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame^] | 476 | snd_soc_component_update_bits(component, mic_sel_reg, |
| 477 | 1 << 7, 1 << 7); |
Laxminath Kasam | 989fccf | 2018-06-15 16:53:31 +0530 | [diff] [blame] | 478 | } |
| 479 | |
| 480 | return snd_soc_dapm_put_enum_double(kcontrol, ucontrol); |
| 481 | } |
| 482 | |
| 483 | static int tx_macro_tx_mixer_get(struct snd_kcontrol *kcontrol, |
| 484 | struct snd_ctl_elem_value *ucontrol) |
| 485 | { |
| 486 | struct snd_soc_dapm_widget *widget = |
| 487 | snd_soc_dapm_kcontrol_widget(kcontrol); |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame^] | 488 | struct snd_soc_component *component = |
| 489 | snd_soc_dapm_to_component(widget->dapm); |
Laxminath Kasam | 989fccf | 2018-06-15 16:53:31 +0530 | [diff] [blame] | 490 | struct soc_multi_mixer_control *mixer = |
| 491 | ((struct soc_multi_mixer_control *)kcontrol->private_value); |
| 492 | u32 dai_id = widget->shift; |
| 493 | u32 dec_id = mixer->shift; |
| 494 | struct device *tx_dev = NULL; |
| 495 | struct tx_macro_priv *tx_priv = NULL; |
| 496 | |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame^] | 497 | if (!tx_macro_get_data(component, &tx_dev, &tx_priv, __func__)) |
Laxminath Kasam | 989fccf | 2018-06-15 16:53:31 +0530 | [diff] [blame] | 498 | return -EINVAL; |
| 499 | |
| 500 | if (test_bit(dec_id, &tx_priv->active_ch_mask[dai_id])) |
| 501 | ucontrol->value.integer.value[0] = 1; |
| 502 | else |
| 503 | ucontrol->value.integer.value[0] = 0; |
| 504 | return 0; |
| 505 | } |
| 506 | |
| 507 | static int tx_macro_tx_mixer_put(struct snd_kcontrol *kcontrol, |
| 508 | struct snd_ctl_elem_value *ucontrol) |
| 509 | { |
| 510 | struct snd_soc_dapm_widget *widget = |
| 511 | snd_soc_dapm_kcontrol_widget(kcontrol); |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame^] | 512 | struct snd_soc_component *component = |
| 513 | snd_soc_dapm_to_component(widget->dapm); |
Laxminath Kasam | 989fccf | 2018-06-15 16:53:31 +0530 | [diff] [blame] | 514 | struct snd_soc_dapm_update *update = NULL; |
| 515 | struct soc_multi_mixer_control *mixer = |
| 516 | ((struct soc_multi_mixer_control *)kcontrol->private_value); |
| 517 | u32 dai_id = widget->shift; |
| 518 | u32 dec_id = mixer->shift; |
| 519 | u32 enable = ucontrol->value.integer.value[0]; |
| 520 | struct device *tx_dev = NULL; |
| 521 | struct tx_macro_priv *tx_priv = NULL; |
| 522 | |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame^] | 523 | if (!tx_macro_get_data(component, &tx_dev, &tx_priv, __func__)) |
Laxminath Kasam | 989fccf | 2018-06-15 16:53:31 +0530 | [diff] [blame] | 524 | return -EINVAL; |
| 525 | |
| 526 | if (enable) { |
| 527 | set_bit(dec_id, &tx_priv->active_ch_mask[dai_id]); |
| 528 | tx_priv->active_ch_cnt[dai_id]++; |
| 529 | } else { |
| 530 | tx_priv->active_ch_cnt[dai_id]--; |
| 531 | clear_bit(dec_id, &tx_priv->active_ch_mask[dai_id]); |
| 532 | } |
| 533 | snd_soc_dapm_mixer_update_power(widget->dapm, kcontrol, enable, update); |
| 534 | |
| 535 | return 0; |
| 536 | } |
| 537 | |
| 538 | static int tx_macro_enable_dmic(struct snd_soc_dapm_widget *w, |
| 539 | struct snd_kcontrol *kcontrol, int event) |
| 540 | { |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame^] | 541 | struct snd_soc_component *component = |
| 542 | snd_soc_dapm_to_component(w->dapm); |
Laxminath Kasam | 989fccf | 2018-06-15 16:53:31 +0530 | [diff] [blame] | 543 | u8 dmic_clk_en = 0x01; |
| 544 | u16 dmic_clk_reg = 0; |
| 545 | s32 *dmic_clk_cnt = NULL; |
| 546 | unsigned int dmic = 0; |
| 547 | int ret = 0; |
| 548 | char *wname = NULL; |
| 549 | struct device *tx_dev = NULL; |
| 550 | struct tx_macro_priv *tx_priv = NULL; |
| 551 | |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame^] | 552 | if (!tx_macro_get_data(component, &tx_dev, &tx_priv, __func__)) |
Laxminath Kasam | 989fccf | 2018-06-15 16:53:31 +0530 | [diff] [blame] | 553 | return -EINVAL; |
| 554 | |
| 555 | wname = strpbrk(w->name, "01234567"); |
| 556 | if (!wname) { |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame^] | 557 | dev_err(component->dev, "%s: widget not found\n", __func__); |
Laxminath Kasam | 989fccf | 2018-06-15 16:53:31 +0530 | [diff] [blame] | 558 | return -EINVAL; |
| 559 | } |
| 560 | |
| 561 | ret = kstrtouint(wname, 10, &dmic); |
| 562 | if (ret < 0) { |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame^] | 563 | dev_err(component->dev, "%s: Invalid DMIC line on the codec\n", |
Laxminath Kasam | 989fccf | 2018-06-15 16:53:31 +0530 | [diff] [blame] | 564 | __func__); |
| 565 | return -EINVAL; |
| 566 | } |
| 567 | |
| 568 | switch (dmic) { |
| 569 | case 0: |
| 570 | case 1: |
| 571 | dmic_clk_cnt = &(tx_priv->dmic_0_1_clk_cnt); |
| 572 | dmic_clk_reg = BOLERO_CDC_VA_TOP_CSR_DMIC0_CTL; |
| 573 | break; |
| 574 | case 2: |
| 575 | case 3: |
| 576 | dmic_clk_cnt = &(tx_priv->dmic_2_3_clk_cnt); |
| 577 | dmic_clk_reg = BOLERO_CDC_VA_TOP_CSR_DMIC1_CTL; |
| 578 | break; |
| 579 | case 4: |
| 580 | case 5: |
| 581 | dmic_clk_cnt = &(tx_priv->dmic_4_5_clk_cnt); |
| 582 | dmic_clk_reg = BOLERO_CDC_VA_TOP_CSR_DMIC2_CTL; |
| 583 | break; |
| 584 | case 6: |
| 585 | case 7: |
| 586 | dmic_clk_cnt = &(tx_priv->dmic_6_7_clk_cnt); |
| 587 | dmic_clk_reg = BOLERO_CDC_VA_TOP_CSR_DMIC3_CTL; |
| 588 | break; |
| 589 | default: |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame^] | 590 | dev_err(component->dev, "%s: Invalid DMIC Selection\n", |
Laxminath Kasam | 989fccf | 2018-06-15 16:53:31 +0530 | [diff] [blame] | 591 | __func__); |
| 592 | return -EINVAL; |
| 593 | } |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame^] | 594 | dev_dbg(component->dev, "%s: event %d DMIC%d dmic_clk_cnt %d\n", |
Laxminath Kasam | 989fccf | 2018-06-15 16:53:31 +0530 | [diff] [blame] | 595 | __func__, event, dmic, *dmic_clk_cnt); |
| 596 | |
| 597 | switch (event) { |
| 598 | case SND_SOC_DAPM_PRE_PMU: |
| 599 | (*dmic_clk_cnt)++; |
| 600 | if (*dmic_clk_cnt == 1) { |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame^] | 601 | snd_soc_component_update_bits(component, |
| 602 | BOLERO_CDC_VA_TOP_CSR_DMIC_CFG, |
Ramprasad Katkam | 9c2394a | 2018-08-23 13:13:48 +0530 | [diff] [blame] | 603 | 0x80, 0x00); |
| 604 | |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame^] | 605 | snd_soc_component_update_bits(component, dmic_clk_reg, |
Laxminath Kasam | 989fccf | 2018-06-15 16:53:31 +0530 | [diff] [blame] | 606 | 0x0E, tx_priv->dmic_clk_div << 0x1); |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame^] | 607 | snd_soc_component_update_bits(component, dmic_clk_reg, |
Laxminath Kasam | 989fccf | 2018-06-15 16:53:31 +0530 | [diff] [blame] | 608 | dmic_clk_en, dmic_clk_en); |
| 609 | } |
| 610 | break; |
| 611 | case SND_SOC_DAPM_POST_PMD: |
| 612 | (*dmic_clk_cnt)--; |
| 613 | if (*dmic_clk_cnt == 0) |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame^] | 614 | snd_soc_component_update_bits(component, dmic_clk_reg, |
Laxminath Kasam | 989fccf | 2018-06-15 16:53:31 +0530 | [diff] [blame] | 615 | dmic_clk_en, 0); |
| 616 | break; |
| 617 | } |
| 618 | |
| 619 | return 0; |
| 620 | } |
| 621 | |
| 622 | static int tx_macro_enable_dec(struct snd_soc_dapm_widget *w, |
| 623 | struct snd_kcontrol *kcontrol, int event) |
| 624 | { |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame^] | 625 | struct snd_soc_component *component = |
| 626 | snd_soc_dapm_to_component(w->dapm); |
Laxminath Kasam | 989fccf | 2018-06-15 16:53:31 +0530 | [diff] [blame] | 627 | unsigned int decimator = 0; |
| 628 | u16 tx_vol_ctl_reg = 0; |
| 629 | u16 dec_cfg_reg = 0; |
| 630 | u16 hpf_gate_reg = 0; |
| 631 | u16 tx_gain_ctl_reg = 0; |
| 632 | u8 hpf_cut_off_freq = 0; |
| 633 | struct device *tx_dev = NULL; |
| 634 | struct tx_macro_priv *tx_priv = NULL; |
| 635 | |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame^] | 636 | if (!tx_macro_get_data(component, &tx_dev, &tx_priv, __func__)) |
Laxminath Kasam | 989fccf | 2018-06-15 16:53:31 +0530 | [diff] [blame] | 637 | return -EINVAL; |
| 638 | |
| 639 | decimator = w->shift; |
| 640 | |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame^] | 641 | dev_dbg(component->dev, "%s(): widget = %s decimator = %u\n", __func__, |
Laxminath Kasam | 989fccf | 2018-06-15 16:53:31 +0530 | [diff] [blame] | 642 | w->name, decimator); |
| 643 | |
| 644 | tx_vol_ctl_reg = BOLERO_CDC_TX0_TX_PATH_CTL + |
| 645 | TX_MACRO_TX_PATH_OFFSET * decimator; |
| 646 | hpf_gate_reg = BOLERO_CDC_TX0_TX_PATH_SEC2 + |
| 647 | TX_MACRO_TX_PATH_OFFSET * decimator; |
| 648 | dec_cfg_reg = BOLERO_CDC_TX0_TX_PATH_CFG0 + |
| 649 | TX_MACRO_TX_PATH_OFFSET * decimator; |
| 650 | tx_gain_ctl_reg = BOLERO_CDC_TX0_TX_VOL_CTL + |
| 651 | TX_MACRO_TX_PATH_OFFSET * decimator; |
| 652 | |
| 653 | switch (event) { |
| 654 | case SND_SOC_DAPM_PRE_PMU: |
Laxminath Kasam | 9eb8022 | 2018-08-29 21:53:14 +0530 | [diff] [blame] | 655 | /* Enable TX PGA Mute */ |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame^] | 656 | snd_soc_component_update_bits(component, |
| 657 | tx_vol_ctl_reg, 0x10, 0x10); |
Laxminath Kasam | 9eb8022 | 2018-08-29 21:53:14 +0530 | [diff] [blame] | 658 | break; |
| 659 | case SND_SOC_DAPM_POST_PMU: |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame^] | 660 | snd_soc_component_update_bits(component, |
| 661 | tx_vol_ctl_reg, 0x20, 0x20); |
| 662 | snd_soc_component_update_bits(component, |
| 663 | hpf_gate_reg, 0x01, 0x00); |
Laxminath Kasam | 9eb8022 | 2018-08-29 21:53:14 +0530 | [diff] [blame] | 664 | |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame^] | 665 | hpf_cut_off_freq = ( |
| 666 | snd_soc_component_read32(component, dec_cfg_reg) & |
| 667 | TX_HPF_CUT_OFF_FREQ_MASK) >> 5; |
| 668 | |
Laxminath Kasam | 989fccf | 2018-06-15 16:53:31 +0530 | [diff] [blame] | 669 | tx_priv->tx_hpf_work[decimator].hpf_cut_off_freq = |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame^] | 670 | hpf_cut_off_freq; |
Laxminath Kasam | 989fccf | 2018-06-15 16:53:31 +0530 | [diff] [blame] | 671 | |
| 672 | if (hpf_cut_off_freq != CF_MIN_3DB_150HZ) |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame^] | 673 | snd_soc_component_update_bits(component, dec_cfg_reg, |
| 674 | TX_HPF_CUT_OFF_FREQ_MASK, |
| 675 | CF_MIN_3DB_150HZ << 5); |
| 676 | |
Laxminath Kasam | 989fccf | 2018-06-15 16:53:31 +0530 | [diff] [blame] | 677 | /* schedule work queue to Remove Mute */ |
| 678 | schedule_delayed_work(&tx_priv->tx_mute_dwork[decimator].dwork, |
| 679 | msecs_to_jiffies(tx_unmute_delay)); |
| 680 | if (tx_priv->tx_hpf_work[decimator].hpf_cut_off_freq != |
Laxminath Kasam | 9eb8022 | 2018-08-29 21:53:14 +0530 | [diff] [blame] | 681 | CF_MIN_3DB_150HZ) { |
Laxminath Kasam | 989fccf | 2018-06-15 16:53:31 +0530 | [diff] [blame] | 682 | schedule_delayed_work( |
| 683 | &tx_priv->tx_hpf_work[decimator].dwork, |
| 684 | msecs_to_jiffies(300)); |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame^] | 685 | snd_soc_component_update_bits(component, |
| 686 | hpf_gate_reg, 0x02, 0x02); |
Laxminath Kasam | 9eb8022 | 2018-08-29 21:53:14 +0530 | [diff] [blame] | 687 | /* |
| 688 | * Minimum 1 clk cycle delay is required as per HW spec |
| 689 | */ |
| 690 | usleep_range(1000, 1010); |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame^] | 691 | snd_soc_component_update_bits(component, |
| 692 | hpf_gate_reg, 0x02, 0x00); |
Laxminath Kasam | 9eb8022 | 2018-08-29 21:53:14 +0530 | [diff] [blame] | 693 | } |
Laxminath Kasam | 989fccf | 2018-06-15 16:53:31 +0530 | [diff] [blame] | 694 | /* apply gain after decimator is enabled */ |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame^] | 695 | snd_soc_component_write(component, tx_gain_ctl_reg, |
| 696 | snd_soc_component_read32(component, |
| 697 | tx_gain_ctl_reg)); |
Laxminath Kasam | 989fccf | 2018-06-15 16:53:31 +0530 | [diff] [blame] | 698 | break; |
| 699 | case SND_SOC_DAPM_PRE_PMD: |
| 700 | hpf_cut_off_freq = |
| 701 | tx_priv->tx_hpf_work[decimator].hpf_cut_off_freq; |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame^] | 702 | snd_soc_component_update_bits(component, |
| 703 | tx_vol_ctl_reg, 0x10, 0x10); |
Laxminath Kasam | 989fccf | 2018-06-15 16:53:31 +0530 | [diff] [blame] | 704 | if (cancel_delayed_work_sync( |
| 705 | &tx_priv->tx_hpf_work[decimator].dwork)) { |
| 706 | if (hpf_cut_off_freq != CF_MIN_3DB_150HZ) { |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame^] | 707 | snd_soc_component_update_bits( |
| 708 | component, dec_cfg_reg, |
| 709 | TX_HPF_CUT_OFF_FREQ_MASK, |
| 710 | hpf_cut_off_freq << 5); |
| 711 | snd_soc_component_update_bits(component, |
| 712 | hpf_gate_reg, |
Laxminath Kasam | 9eb8022 | 2018-08-29 21:53:14 +0530 | [diff] [blame] | 713 | 0x02, 0x02); |
| 714 | /* |
| 715 | * Minimum 1 clk cycle delay is required |
| 716 | * as per HW spec |
| 717 | */ |
| 718 | usleep_range(1000, 1010); |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame^] | 719 | snd_soc_component_update_bits(component, |
| 720 | hpf_gate_reg, |
Laxminath Kasam | 9eb8022 | 2018-08-29 21:53:14 +0530 | [diff] [blame] | 721 | 0x02, 0x00); |
Laxminath Kasam | 989fccf | 2018-06-15 16:53:31 +0530 | [diff] [blame] | 722 | } |
| 723 | } |
| 724 | cancel_delayed_work_sync( |
| 725 | &tx_priv->tx_mute_dwork[decimator].dwork); |
| 726 | break; |
| 727 | case SND_SOC_DAPM_POST_PMD: |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame^] | 728 | snd_soc_component_update_bits(component, tx_vol_ctl_reg, |
| 729 | 0x20, 0x00); |
| 730 | snd_soc_component_update_bits(component, tx_vol_ctl_reg, |
| 731 | 0x10, 0x00); |
Laxminath Kasam | 989fccf | 2018-06-15 16:53:31 +0530 | [diff] [blame] | 732 | break; |
| 733 | } |
| 734 | return 0; |
| 735 | } |
| 736 | |
| 737 | static int tx_macro_enable_micbias(struct snd_soc_dapm_widget *w, |
| 738 | struct snd_kcontrol *kcontrol, int event) |
| 739 | { |
| 740 | return 0; |
| 741 | } |
| 742 | |
| 743 | static int tx_macro_hw_params(struct snd_pcm_substream *substream, |
| 744 | struct snd_pcm_hw_params *params, |
| 745 | struct snd_soc_dai *dai) |
| 746 | { |
| 747 | int tx_fs_rate = -EINVAL; |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame^] | 748 | struct snd_soc_component *component = dai->component; |
Laxminath Kasam | 989fccf | 2018-06-15 16:53:31 +0530 | [diff] [blame] | 749 | u32 decimator = 0; |
Laxminath Kasam | b7f823c | 2018-08-02 13:23:11 +0530 | [diff] [blame] | 750 | u32 sample_rate = 0; |
Laxminath Kasam | 989fccf | 2018-06-15 16:53:31 +0530 | [diff] [blame] | 751 | u16 tx_fs_reg = 0; |
| 752 | struct device *tx_dev = NULL; |
| 753 | struct tx_macro_priv *tx_priv = NULL; |
| 754 | |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame^] | 755 | if (!tx_macro_get_data(component, &tx_dev, &tx_priv, __func__)) |
Laxminath Kasam | 989fccf | 2018-06-15 16:53:31 +0530 | [diff] [blame] | 756 | return -EINVAL; |
| 757 | |
| 758 | pr_debug("%s: dai_name = %s DAI-ID %x rate %d num_ch %d\n", __func__, |
| 759 | dai->name, dai->id, params_rate(params), |
| 760 | params_channels(params)); |
| 761 | |
| 762 | sample_rate = params_rate(params); |
| 763 | switch (sample_rate) { |
| 764 | case 8000: |
| 765 | tx_fs_rate = 0; |
| 766 | break; |
| 767 | case 16000: |
| 768 | tx_fs_rate = 1; |
| 769 | break; |
| 770 | case 32000: |
| 771 | tx_fs_rate = 3; |
| 772 | break; |
| 773 | case 48000: |
| 774 | tx_fs_rate = 4; |
| 775 | break; |
| 776 | case 96000: |
| 777 | tx_fs_rate = 5; |
| 778 | break; |
| 779 | case 192000: |
| 780 | tx_fs_rate = 6; |
| 781 | break; |
| 782 | case 384000: |
| 783 | tx_fs_rate = 7; |
| 784 | break; |
| 785 | default: |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame^] | 786 | dev_err(component->dev, "%s: Invalid TX sample rate: %d\n", |
Laxminath Kasam | 989fccf | 2018-06-15 16:53:31 +0530 | [diff] [blame] | 787 | __func__, params_rate(params)); |
| 788 | return -EINVAL; |
| 789 | } |
| 790 | for_each_set_bit(decimator, &tx_priv->active_ch_mask[dai->id], |
| 791 | TX_MACRO_DEC_MAX) { |
| 792 | if (decimator >= 0) { |
| 793 | tx_fs_reg = BOLERO_CDC_TX0_TX_PATH_CTL + |
| 794 | TX_MACRO_TX_PATH_OFFSET * decimator; |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame^] | 795 | dev_dbg(component->dev, "%s: set DEC%u rate to %u\n", |
Laxminath Kasam | 989fccf | 2018-06-15 16:53:31 +0530 | [diff] [blame] | 796 | __func__, decimator, sample_rate); |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame^] | 797 | snd_soc_component_update_bits(component, tx_fs_reg, |
| 798 | 0x0F, tx_fs_rate); |
Laxminath Kasam | 989fccf | 2018-06-15 16:53:31 +0530 | [diff] [blame] | 799 | } else { |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame^] | 800 | dev_err(component->dev, |
Laxminath Kasam | 989fccf | 2018-06-15 16:53:31 +0530 | [diff] [blame] | 801 | "%s: ERROR: Invalid decimator: %d\n", |
| 802 | __func__, decimator); |
| 803 | return -EINVAL; |
| 804 | } |
| 805 | } |
| 806 | return 0; |
| 807 | } |
| 808 | |
| 809 | static int tx_macro_get_channel_map(struct snd_soc_dai *dai, |
| 810 | unsigned int *tx_num, unsigned int *tx_slot, |
| 811 | unsigned int *rx_num, unsigned int *rx_slot) |
| 812 | { |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame^] | 813 | struct snd_soc_component *component = dai->component; |
Laxminath Kasam | 989fccf | 2018-06-15 16:53:31 +0530 | [diff] [blame] | 814 | struct device *tx_dev = NULL; |
| 815 | struct tx_macro_priv *tx_priv = NULL; |
| 816 | |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame^] | 817 | if (!tx_macro_get_data(component, &tx_dev, &tx_priv, __func__)) |
Laxminath Kasam | 989fccf | 2018-06-15 16:53:31 +0530 | [diff] [blame] | 818 | return -EINVAL; |
| 819 | |
| 820 | switch (dai->id) { |
| 821 | case TX_MACRO_AIF1_CAP: |
| 822 | case TX_MACRO_AIF2_CAP: |
| 823 | *tx_slot = tx_priv->active_ch_mask[dai->id]; |
| 824 | *tx_num = tx_priv->active_ch_cnt[dai->id]; |
| 825 | break; |
| 826 | default: |
| 827 | dev_err(tx_dev, "%s: Invalid AIF\n", __func__); |
| 828 | break; |
| 829 | } |
| 830 | return 0; |
| 831 | } |
| 832 | |
| 833 | static struct snd_soc_dai_ops tx_macro_dai_ops = { |
| 834 | .hw_params = tx_macro_hw_params, |
| 835 | .get_channel_map = tx_macro_get_channel_map, |
| 836 | }; |
| 837 | |
| 838 | static struct snd_soc_dai_driver tx_macro_dai[] = { |
| 839 | { |
| 840 | .name = "tx_macro_tx1", |
| 841 | .id = TX_MACRO_AIF1_CAP, |
| 842 | .capture = { |
| 843 | .stream_name = "TX_AIF1 Capture", |
| 844 | .rates = TX_MACRO_RATES, |
| 845 | .formats = TX_MACRO_FORMATS, |
| 846 | .rate_max = 192000, |
| 847 | .rate_min = 8000, |
| 848 | .channels_min = 1, |
| 849 | .channels_max = 8, |
| 850 | }, |
| 851 | .ops = &tx_macro_dai_ops, |
| 852 | }, |
| 853 | { |
| 854 | .name = "tx_macro_tx2", |
| 855 | .id = TX_MACRO_AIF2_CAP, |
| 856 | .capture = { |
| 857 | .stream_name = "TX_AIF2 Capture", |
| 858 | .rates = TX_MACRO_RATES, |
| 859 | .formats = TX_MACRO_FORMATS, |
| 860 | .rate_max = 192000, |
| 861 | .rate_min = 8000, |
| 862 | .channels_min = 1, |
| 863 | .channels_max = 8, |
| 864 | }, |
| 865 | .ops = &tx_macro_dai_ops, |
| 866 | }, |
| 867 | }; |
| 868 | |
| 869 | #define STRING(name) #name |
| 870 | #define TX_MACRO_DAPM_ENUM(name, reg, offset, text) \ |
| 871 | static SOC_ENUM_SINGLE_DECL(name##_enum, reg, offset, text); \ |
| 872 | static const struct snd_kcontrol_new name##_mux = \ |
| 873 | SOC_DAPM_ENUM(STRING(name), name##_enum) |
| 874 | |
| 875 | #define TX_MACRO_DAPM_ENUM_EXT(name, reg, offset, text, getname, putname) \ |
| 876 | static SOC_ENUM_SINGLE_DECL(name##_enum, reg, offset, text); \ |
| 877 | static const struct snd_kcontrol_new name##_mux = \ |
| 878 | SOC_DAPM_ENUM_EXT(STRING(name), name##_enum, getname, putname) |
| 879 | |
| 880 | #define TX_MACRO_DAPM_MUX(name, shift, kctl) \ |
| 881 | SND_SOC_DAPM_MUX(name, SND_SOC_NOPM, shift, 0, &kctl##_mux) |
| 882 | |
| 883 | static const char * const adc_mux_text[] = { |
| 884 | "MSM_DMIC", "SWR_MIC", "ANC_FB_TUNE1" |
| 885 | }; |
| 886 | |
| 887 | TX_MACRO_DAPM_ENUM(tx_dec0, BOLERO_CDC_TX_INP_MUX_ADC_MUX0_CFG1, |
| 888 | 0, adc_mux_text); |
| 889 | TX_MACRO_DAPM_ENUM(tx_dec1, BOLERO_CDC_TX_INP_MUX_ADC_MUX1_CFG1, |
| 890 | 0, adc_mux_text); |
| 891 | TX_MACRO_DAPM_ENUM(tx_dec2, BOLERO_CDC_TX_INP_MUX_ADC_MUX2_CFG1, |
| 892 | 0, adc_mux_text); |
| 893 | TX_MACRO_DAPM_ENUM(tx_dec3, BOLERO_CDC_TX_INP_MUX_ADC_MUX3_CFG1, |
| 894 | 0, adc_mux_text); |
| 895 | TX_MACRO_DAPM_ENUM(tx_dec4, BOLERO_CDC_TX_INP_MUX_ADC_MUX4_CFG1, |
| 896 | 0, adc_mux_text); |
| 897 | TX_MACRO_DAPM_ENUM(tx_dec5, BOLERO_CDC_TX_INP_MUX_ADC_MUX5_CFG1, |
| 898 | 0, adc_mux_text); |
| 899 | TX_MACRO_DAPM_ENUM(tx_dec6, BOLERO_CDC_TX_INP_MUX_ADC_MUX6_CFG1, |
| 900 | 0, adc_mux_text); |
| 901 | TX_MACRO_DAPM_ENUM(tx_dec7, BOLERO_CDC_TX_INP_MUX_ADC_MUX7_CFG1, |
| 902 | 0, adc_mux_text); |
| 903 | |
| 904 | |
| 905 | static const char * const dmic_mux_text[] = { |
| 906 | "ZERO", "DMIC0", "DMIC1", "DMIC2", "DMIC3", |
| 907 | "DMIC4", "DMIC5", "DMIC6", "DMIC7" |
| 908 | }; |
| 909 | |
| 910 | TX_MACRO_DAPM_ENUM_EXT(tx_dmic0, BOLERO_CDC_TX_INP_MUX_ADC_MUX0_CFG0, |
| 911 | 4, dmic_mux_text, snd_soc_dapm_get_enum_double, |
| 912 | tx_macro_put_dec_enum); |
| 913 | |
| 914 | TX_MACRO_DAPM_ENUM_EXT(tx_dmic1, BOLERO_CDC_TX_INP_MUX_ADC_MUX1_CFG0, |
| 915 | 4, dmic_mux_text, snd_soc_dapm_get_enum_double, |
| 916 | tx_macro_put_dec_enum); |
| 917 | |
| 918 | TX_MACRO_DAPM_ENUM_EXT(tx_dmic2, BOLERO_CDC_TX_INP_MUX_ADC_MUX2_CFG0, |
| 919 | 4, dmic_mux_text, snd_soc_dapm_get_enum_double, |
| 920 | tx_macro_put_dec_enum); |
| 921 | |
| 922 | TX_MACRO_DAPM_ENUM_EXT(tx_dmic3, BOLERO_CDC_TX_INP_MUX_ADC_MUX3_CFG0, |
| 923 | 4, dmic_mux_text, snd_soc_dapm_get_enum_double, |
| 924 | tx_macro_put_dec_enum); |
| 925 | |
| 926 | TX_MACRO_DAPM_ENUM_EXT(tx_dmic4, BOLERO_CDC_TX_INP_MUX_ADC_MUX4_CFG0, |
| 927 | 4, dmic_mux_text, snd_soc_dapm_get_enum_double, |
| 928 | tx_macro_put_dec_enum); |
| 929 | |
| 930 | TX_MACRO_DAPM_ENUM_EXT(tx_dmic5, BOLERO_CDC_TX_INP_MUX_ADC_MUX5_CFG0, |
| 931 | 4, dmic_mux_text, snd_soc_dapm_get_enum_double, |
| 932 | tx_macro_put_dec_enum); |
| 933 | |
| 934 | TX_MACRO_DAPM_ENUM_EXT(tx_dmic6, BOLERO_CDC_TX_INP_MUX_ADC_MUX6_CFG0, |
| 935 | 4, dmic_mux_text, snd_soc_dapm_get_enum_double, |
| 936 | tx_macro_put_dec_enum); |
| 937 | |
| 938 | TX_MACRO_DAPM_ENUM_EXT(tx_dmic7, BOLERO_CDC_TX_INP_MUX_ADC_MUX7_CFG0, |
| 939 | 4, dmic_mux_text, snd_soc_dapm_get_enum_double, |
| 940 | tx_macro_put_dec_enum); |
| 941 | |
| 942 | static const char * const smic_mux_text[] = { |
| 943 | "ZERO", "ADC0", "ADC1", "ADC2", "ADC3", |
| 944 | "SWR_DMIC0", "SWR_DMIC1", "SWR_DMIC2", "SWR_DMIC3", |
| 945 | "SWR_DMIC4", "SWR_DMIC5", "SWR_DMIC6", "SWR_DMIC7" |
| 946 | }; |
| 947 | |
| 948 | TX_MACRO_DAPM_ENUM_EXT(tx_smic0, BOLERO_CDC_TX_INP_MUX_ADC_MUX0_CFG0, |
| 949 | 0, smic_mux_text, snd_soc_dapm_get_enum_double, |
| 950 | tx_macro_put_dec_enum); |
| 951 | |
| 952 | TX_MACRO_DAPM_ENUM_EXT(tx_smic1, BOLERO_CDC_TX_INP_MUX_ADC_MUX1_CFG0, |
| 953 | 0, smic_mux_text, snd_soc_dapm_get_enum_double, |
| 954 | tx_macro_put_dec_enum); |
| 955 | |
| 956 | TX_MACRO_DAPM_ENUM_EXT(tx_smic2, BOLERO_CDC_TX_INP_MUX_ADC_MUX2_CFG0, |
| 957 | 0, smic_mux_text, snd_soc_dapm_get_enum_double, |
| 958 | tx_macro_put_dec_enum); |
| 959 | |
| 960 | TX_MACRO_DAPM_ENUM_EXT(tx_smic3, BOLERO_CDC_TX_INP_MUX_ADC_MUX3_CFG0, |
| 961 | 0, smic_mux_text, snd_soc_dapm_get_enum_double, |
| 962 | tx_macro_put_dec_enum); |
| 963 | |
| 964 | TX_MACRO_DAPM_ENUM_EXT(tx_smic4, BOLERO_CDC_TX_INP_MUX_ADC_MUX4_CFG0, |
| 965 | 0, smic_mux_text, snd_soc_dapm_get_enum_double, |
| 966 | tx_macro_put_dec_enum); |
| 967 | |
| 968 | TX_MACRO_DAPM_ENUM_EXT(tx_smic5, BOLERO_CDC_TX_INP_MUX_ADC_MUX5_CFG0, |
| 969 | 0, smic_mux_text, snd_soc_dapm_get_enum_double, |
| 970 | tx_macro_put_dec_enum); |
| 971 | |
| 972 | TX_MACRO_DAPM_ENUM_EXT(tx_smic6, BOLERO_CDC_TX_INP_MUX_ADC_MUX6_CFG0, |
| 973 | 0, smic_mux_text, snd_soc_dapm_get_enum_double, |
| 974 | tx_macro_put_dec_enum); |
| 975 | |
| 976 | TX_MACRO_DAPM_ENUM_EXT(tx_smic7, BOLERO_CDC_TX_INP_MUX_ADC_MUX7_CFG0, |
| 977 | 0, smic_mux_text, snd_soc_dapm_get_enum_double, |
| 978 | tx_macro_put_dec_enum); |
| 979 | |
| 980 | static const struct snd_kcontrol_new tx_aif1_cap_mixer[] = { |
| 981 | SOC_SINGLE_EXT("DEC0", SND_SOC_NOPM, TX_MACRO_DEC0, 1, 0, |
| 982 | tx_macro_tx_mixer_get, tx_macro_tx_mixer_put), |
| 983 | SOC_SINGLE_EXT("DEC1", SND_SOC_NOPM, TX_MACRO_DEC1, 1, 0, |
| 984 | tx_macro_tx_mixer_get, tx_macro_tx_mixer_put), |
| 985 | SOC_SINGLE_EXT("DEC2", SND_SOC_NOPM, TX_MACRO_DEC2, 1, 0, |
| 986 | tx_macro_tx_mixer_get, tx_macro_tx_mixer_put), |
| 987 | SOC_SINGLE_EXT("DEC3", SND_SOC_NOPM, TX_MACRO_DEC3, 1, 0, |
| 988 | tx_macro_tx_mixer_get, tx_macro_tx_mixer_put), |
| 989 | SOC_SINGLE_EXT("DEC4", SND_SOC_NOPM, TX_MACRO_DEC4, 1, 0, |
| 990 | tx_macro_tx_mixer_get, tx_macro_tx_mixer_put), |
| 991 | SOC_SINGLE_EXT("DEC5", SND_SOC_NOPM, TX_MACRO_DEC5, 1, 0, |
| 992 | tx_macro_tx_mixer_get, tx_macro_tx_mixer_put), |
| 993 | SOC_SINGLE_EXT("DEC6", SND_SOC_NOPM, TX_MACRO_DEC6, 1, 0, |
| 994 | tx_macro_tx_mixer_get, tx_macro_tx_mixer_put), |
| 995 | SOC_SINGLE_EXT("DEC7", SND_SOC_NOPM, TX_MACRO_DEC7, 1, 0, |
| 996 | tx_macro_tx_mixer_get, tx_macro_tx_mixer_put), |
| 997 | }; |
| 998 | |
| 999 | static const struct snd_kcontrol_new tx_aif2_cap_mixer[] = { |
| 1000 | SOC_SINGLE_EXT("DEC0", SND_SOC_NOPM, TX_MACRO_DEC0, 1, 0, |
| 1001 | tx_macro_tx_mixer_get, tx_macro_tx_mixer_put), |
| 1002 | SOC_SINGLE_EXT("DEC1", SND_SOC_NOPM, TX_MACRO_DEC1, 1, 0, |
| 1003 | tx_macro_tx_mixer_get, tx_macro_tx_mixer_put), |
| 1004 | SOC_SINGLE_EXT("DEC2", SND_SOC_NOPM, TX_MACRO_DEC2, 1, 0, |
| 1005 | tx_macro_tx_mixer_get, tx_macro_tx_mixer_put), |
| 1006 | SOC_SINGLE_EXT("DEC3", SND_SOC_NOPM, TX_MACRO_DEC3, 1, 0, |
| 1007 | tx_macro_tx_mixer_get, tx_macro_tx_mixer_put), |
| 1008 | SOC_SINGLE_EXT("DEC4", SND_SOC_NOPM, TX_MACRO_DEC4, 1, 0, |
| 1009 | tx_macro_tx_mixer_get, tx_macro_tx_mixer_put), |
| 1010 | SOC_SINGLE_EXT("DEC5", SND_SOC_NOPM, TX_MACRO_DEC5, 1, 0, |
| 1011 | tx_macro_tx_mixer_get, tx_macro_tx_mixer_put), |
| 1012 | SOC_SINGLE_EXT("DEC6", SND_SOC_NOPM, TX_MACRO_DEC6, 1, 0, |
| 1013 | tx_macro_tx_mixer_get, tx_macro_tx_mixer_put), |
| 1014 | SOC_SINGLE_EXT("DEC7", SND_SOC_NOPM, TX_MACRO_DEC7, 1, 0, |
| 1015 | tx_macro_tx_mixer_get, tx_macro_tx_mixer_put), |
| 1016 | }; |
| 1017 | |
| 1018 | static const struct snd_soc_dapm_widget tx_macro_dapm_widgets[] = { |
| 1019 | SND_SOC_DAPM_AIF_OUT("TX_AIF1 CAP", "TX_AIF1 Capture", 0, |
| 1020 | SND_SOC_NOPM, TX_MACRO_AIF1_CAP, 0), |
| 1021 | |
| 1022 | SND_SOC_DAPM_AIF_OUT("TX_AIF2 CAP", "TX_AIF2 Capture", 0, |
| 1023 | SND_SOC_NOPM, TX_MACRO_AIF2_CAP, 0), |
| 1024 | |
| 1025 | SND_SOC_DAPM_MIXER("TX_AIF1_CAP Mixer", SND_SOC_NOPM, TX_MACRO_AIF1_CAP, 0, |
| 1026 | tx_aif1_cap_mixer, ARRAY_SIZE(tx_aif1_cap_mixer)), |
| 1027 | |
| 1028 | SND_SOC_DAPM_MIXER("TX_AIF2_CAP Mixer", SND_SOC_NOPM, TX_MACRO_AIF2_CAP, 0, |
| 1029 | tx_aif2_cap_mixer, ARRAY_SIZE(tx_aif2_cap_mixer)), |
| 1030 | |
| 1031 | |
| 1032 | TX_MACRO_DAPM_MUX("TX DMIC MUX0", 0, tx_dmic0), |
| 1033 | TX_MACRO_DAPM_MUX("TX DMIC MUX1", 0, tx_dmic1), |
| 1034 | TX_MACRO_DAPM_MUX("TX DMIC MUX2", 0, tx_dmic2), |
| 1035 | TX_MACRO_DAPM_MUX("TX DMIC MUX3", 0, tx_dmic3), |
| 1036 | TX_MACRO_DAPM_MUX("TX DMIC MUX4", 0, tx_dmic4), |
| 1037 | TX_MACRO_DAPM_MUX("TX DMIC MUX5", 0, tx_dmic5), |
| 1038 | TX_MACRO_DAPM_MUX("TX DMIC MUX6", 0, tx_dmic6), |
| 1039 | TX_MACRO_DAPM_MUX("TX DMIC MUX7", 0, tx_dmic7), |
| 1040 | |
| 1041 | TX_MACRO_DAPM_MUX("TX SMIC MUX0", 0, tx_smic0), |
| 1042 | TX_MACRO_DAPM_MUX("TX SMIC MUX1", 0, tx_smic1), |
| 1043 | TX_MACRO_DAPM_MUX("TX SMIC MUX2", 0, tx_smic2), |
| 1044 | TX_MACRO_DAPM_MUX("TX SMIC MUX3", 0, tx_smic3), |
| 1045 | TX_MACRO_DAPM_MUX("TX SMIC MUX4", 0, tx_smic4), |
| 1046 | TX_MACRO_DAPM_MUX("TX SMIC MUX5", 0, tx_smic5), |
| 1047 | TX_MACRO_DAPM_MUX("TX SMIC MUX6", 0, tx_smic6), |
| 1048 | TX_MACRO_DAPM_MUX("TX SMIC MUX7", 0, tx_smic7), |
| 1049 | |
| 1050 | SND_SOC_DAPM_MICBIAS_E("TX MIC BIAS1", SND_SOC_NOPM, 0, 0, |
| 1051 | tx_macro_enable_micbias, |
| 1052 | SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), |
| 1053 | SND_SOC_DAPM_ADC_E("TX DMIC0", NULL, SND_SOC_NOPM, 0, 0, |
| 1054 | tx_macro_enable_dmic, SND_SOC_DAPM_PRE_PMU | |
| 1055 | SND_SOC_DAPM_POST_PMD), |
| 1056 | |
| 1057 | SND_SOC_DAPM_ADC_E("TX DMIC1", NULL, SND_SOC_NOPM, 0, 0, |
| 1058 | tx_macro_enable_dmic, SND_SOC_DAPM_PRE_PMU | |
| 1059 | SND_SOC_DAPM_POST_PMD), |
| 1060 | |
| 1061 | SND_SOC_DAPM_ADC_E("TX DMIC2", NULL, SND_SOC_NOPM, 0, 0, |
| 1062 | tx_macro_enable_dmic, SND_SOC_DAPM_PRE_PMU | |
| 1063 | SND_SOC_DAPM_POST_PMD), |
| 1064 | |
| 1065 | SND_SOC_DAPM_ADC_E("TX DMIC3", NULL, SND_SOC_NOPM, 0, 0, |
| 1066 | tx_macro_enable_dmic, SND_SOC_DAPM_PRE_PMU | |
| 1067 | SND_SOC_DAPM_POST_PMD), |
| 1068 | |
| 1069 | SND_SOC_DAPM_ADC_E("TX DMIC4", NULL, SND_SOC_NOPM, 0, 0, |
| 1070 | tx_macro_enable_dmic, SND_SOC_DAPM_PRE_PMU | |
| 1071 | SND_SOC_DAPM_POST_PMD), |
| 1072 | |
| 1073 | SND_SOC_DAPM_ADC_E("TX DMIC5", NULL, SND_SOC_NOPM, 0, 0, |
| 1074 | tx_macro_enable_dmic, SND_SOC_DAPM_PRE_PMU | |
| 1075 | SND_SOC_DAPM_POST_PMD), |
| 1076 | |
| 1077 | SND_SOC_DAPM_ADC_E("TX DMIC6", NULL, SND_SOC_NOPM, 0, 0, |
| 1078 | tx_macro_enable_dmic, SND_SOC_DAPM_PRE_PMU | |
| 1079 | SND_SOC_DAPM_POST_PMD), |
| 1080 | |
| 1081 | SND_SOC_DAPM_ADC_E("TX DMIC7", NULL, SND_SOC_NOPM, 0, 0, |
| 1082 | tx_macro_enable_dmic, SND_SOC_DAPM_PRE_PMU | |
| 1083 | SND_SOC_DAPM_POST_PMD), |
| 1084 | |
| 1085 | SND_SOC_DAPM_INPUT("TX SWR_ADC0"), |
| 1086 | SND_SOC_DAPM_INPUT("TX SWR_ADC1"), |
| 1087 | SND_SOC_DAPM_INPUT("TX SWR_ADC2"), |
| 1088 | SND_SOC_DAPM_INPUT("TX SWR_ADC3"), |
| 1089 | SND_SOC_DAPM_INPUT("TX SWR_DMIC0"), |
| 1090 | SND_SOC_DAPM_INPUT("TX SWR_DMIC1"), |
| 1091 | SND_SOC_DAPM_INPUT("TX SWR_DMIC2"), |
| 1092 | SND_SOC_DAPM_INPUT("TX SWR_DMIC3"), |
| 1093 | SND_SOC_DAPM_INPUT("TX SWR_DMIC4"), |
| 1094 | SND_SOC_DAPM_INPUT("TX SWR_DMIC5"), |
| 1095 | SND_SOC_DAPM_INPUT("TX SWR_DMIC6"), |
| 1096 | SND_SOC_DAPM_INPUT("TX SWR_DMIC7"), |
| 1097 | |
Ramprasad Katkam | f83acfb | 2018-08-11 23:28:57 +0530 | [diff] [blame] | 1098 | SND_SOC_DAPM_MUX_E("TX DEC0 MUX", SND_SOC_NOPM, |
Laxminath Kasam | 989fccf | 2018-06-15 16:53:31 +0530 | [diff] [blame] | 1099 | TX_MACRO_DEC0, 0, |
| 1100 | &tx_dec0_mux, tx_macro_enable_dec, |
| 1101 | SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | |
| 1102 | SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), |
| 1103 | |
Ramprasad Katkam | f83acfb | 2018-08-11 23:28:57 +0530 | [diff] [blame] | 1104 | SND_SOC_DAPM_MUX_E("TX DEC1 MUX", SND_SOC_NOPM, |
Laxminath Kasam | 989fccf | 2018-06-15 16:53:31 +0530 | [diff] [blame] | 1105 | TX_MACRO_DEC1, 0, |
| 1106 | &tx_dec1_mux, tx_macro_enable_dec, |
| 1107 | SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | |
| 1108 | SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), |
| 1109 | |
Ramprasad Katkam | f83acfb | 2018-08-11 23:28:57 +0530 | [diff] [blame] | 1110 | SND_SOC_DAPM_MUX_E("TX DEC2 MUX", SND_SOC_NOPM, |
Laxminath Kasam | 989fccf | 2018-06-15 16:53:31 +0530 | [diff] [blame] | 1111 | TX_MACRO_DEC2, 0, |
| 1112 | &tx_dec2_mux, tx_macro_enable_dec, |
| 1113 | SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | |
| 1114 | SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), |
| 1115 | |
Ramprasad Katkam | f83acfb | 2018-08-11 23:28:57 +0530 | [diff] [blame] | 1116 | SND_SOC_DAPM_MUX_E("TX DEC3 MUX", SND_SOC_NOPM, |
Laxminath Kasam | 989fccf | 2018-06-15 16:53:31 +0530 | [diff] [blame] | 1117 | TX_MACRO_DEC3, 0, |
| 1118 | &tx_dec3_mux, tx_macro_enable_dec, |
| 1119 | SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | |
| 1120 | SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), |
| 1121 | |
Ramprasad Katkam | f83acfb | 2018-08-11 23:28:57 +0530 | [diff] [blame] | 1122 | SND_SOC_DAPM_MUX_E("TX DEC4 MUX", SND_SOC_NOPM, |
Laxminath Kasam | 989fccf | 2018-06-15 16:53:31 +0530 | [diff] [blame] | 1123 | TX_MACRO_DEC4, 0, |
| 1124 | &tx_dec4_mux, tx_macro_enable_dec, |
| 1125 | SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | |
| 1126 | SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), |
| 1127 | |
Ramprasad Katkam | f83acfb | 2018-08-11 23:28:57 +0530 | [diff] [blame] | 1128 | SND_SOC_DAPM_MUX_E("TX DEC5 MUX", SND_SOC_NOPM, |
Laxminath Kasam | 989fccf | 2018-06-15 16:53:31 +0530 | [diff] [blame] | 1129 | TX_MACRO_DEC5, 0, |
| 1130 | &tx_dec5_mux, tx_macro_enable_dec, |
| 1131 | SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | |
| 1132 | SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), |
| 1133 | |
Ramprasad Katkam | f83acfb | 2018-08-11 23:28:57 +0530 | [diff] [blame] | 1134 | SND_SOC_DAPM_MUX_E("TX DEC6 MUX", SND_SOC_NOPM, |
Laxminath Kasam | 989fccf | 2018-06-15 16:53:31 +0530 | [diff] [blame] | 1135 | TX_MACRO_DEC6, 0, |
| 1136 | &tx_dec6_mux, tx_macro_enable_dec, |
| 1137 | SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | |
| 1138 | SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), |
| 1139 | |
Ramprasad Katkam | f83acfb | 2018-08-11 23:28:57 +0530 | [diff] [blame] | 1140 | SND_SOC_DAPM_MUX_E("TX DEC7 MUX", SND_SOC_NOPM, |
Laxminath Kasam | 989fccf | 2018-06-15 16:53:31 +0530 | [diff] [blame] | 1141 | TX_MACRO_DEC7, 0, |
| 1142 | &tx_dec7_mux, tx_macro_enable_dec, |
| 1143 | SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | |
| 1144 | SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), |
| 1145 | |
| 1146 | SND_SOC_DAPM_SUPPLY_S("TX_MCLK", 0, SND_SOC_NOPM, 0, 0, |
| 1147 | tx_macro_mclk_event, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), |
| 1148 | }; |
| 1149 | |
| 1150 | static const struct snd_soc_dapm_route tx_audio_map[] = { |
| 1151 | {"TX_AIF1 CAP", NULL, "TX_MCLK"}, |
| 1152 | {"TX_AIF2 CAP", NULL, "TX_MCLK"}, |
| 1153 | |
| 1154 | {"TX_AIF1 CAP", NULL, "TX_AIF1_CAP Mixer"}, |
| 1155 | {"TX_AIF2 CAP", NULL, "TX_AIF2_CAP Mixer"}, |
| 1156 | |
| 1157 | {"TX_AIF1_CAP Mixer", "DEC0", "TX DEC0 MUX"}, |
| 1158 | {"TX_AIF1_CAP Mixer", "DEC1", "TX DEC1 MUX"}, |
| 1159 | {"TX_AIF1_CAP Mixer", "DEC2", "TX DEC2 MUX"}, |
| 1160 | {"TX_AIF1_CAP Mixer", "DEC3", "TX DEC3 MUX"}, |
| 1161 | {"TX_AIF1_CAP Mixer", "DEC4", "TX DEC4 MUX"}, |
| 1162 | {"TX_AIF1_CAP Mixer", "DEC5", "TX DEC5 MUX"}, |
| 1163 | {"TX_AIF1_CAP Mixer", "DEC6", "TX DEC6 MUX"}, |
| 1164 | {"TX_AIF1_CAP Mixer", "DEC7", "TX DEC7 MUX"}, |
| 1165 | |
| 1166 | {"TX_AIF2_CAP Mixer", "DEC0", "TX DEC0 MUX"}, |
| 1167 | {"TX_AIF2_CAP Mixer", "DEC1", "TX DEC1 MUX"}, |
| 1168 | {"TX_AIF2_CAP Mixer", "DEC2", "TX DEC2 MUX"}, |
| 1169 | {"TX_AIF2_CAP Mixer", "DEC3", "TX DEC3 MUX"}, |
| 1170 | {"TX_AIF2_CAP Mixer", "DEC4", "TX DEC4 MUX"}, |
| 1171 | {"TX_AIF2_CAP Mixer", "DEC5", "TX DEC5 MUX"}, |
| 1172 | {"TX_AIF2_CAP Mixer", "DEC6", "TX DEC6 MUX"}, |
| 1173 | {"TX_AIF2_CAP Mixer", "DEC7", "TX DEC7 MUX"}, |
| 1174 | |
Laxminath Kasam | fc281ad | 2018-08-06 20:19:40 +0530 | [diff] [blame] | 1175 | {"TX DEC0 MUX", NULL, "TX_MCLK"}, |
| 1176 | {"TX DEC1 MUX", NULL, "TX_MCLK"}, |
| 1177 | {"TX DEC2 MUX", NULL, "TX_MCLK"}, |
| 1178 | {"TX DEC3 MUX", NULL, "TX_MCLK"}, |
| 1179 | {"TX DEC4 MUX", NULL, "TX_MCLK"}, |
| 1180 | {"TX DEC5 MUX", NULL, "TX_MCLK"}, |
| 1181 | {"TX DEC6 MUX", NULL, "TX_MCLK"}, |
| 1182 | {"TX DEC7 MUX", NULL, "TX_MCLK"}, |
| 1183 | |
Laxminath Kasam | 989fccf | 2018-06-15 16:53:31 +0530 | [diff] [blame] | 1184 | {"TX DEC0 MUX", "MSM_DMIC", "TX DMIC MUX0"}, |
| 1185 | {"TX DMIC MUX0", "DMIC0", "TX DMIC0"}, |
| 1186 | {"TX DMIC MUX0", "DMIC1", "TX DMIC1"}, |
| 1187 | {"TX DMIC MUX0", "DMIC2", "TX DMIC2"}, |
| 1188 | {"TX DMIC MUX0", "DMIC3", "TX DMIC3"}, |
| 1189 | {"TX DMIC MUX0", "DMIC4", "TX DMIC4"}, |
| 1190 | {"TX DMIC MUX0", "DMIC5", "TX DMIC5"}, |
| 1191 | {"TX DMIC MUX0", "DMIC6", "TX DMIC6"}, |
| 1192 | {"TX DMIC MUX0", "DMIC7", "TX DMIC7"}, |
| 1193 | |
| 1194 | {"TX DEC0 MUX", "SWR_MIC", "TX SMIC MUX0"}, |
| 1195 | {"TX SMIC MUX0", "ADC0", "TX SWR_ADC0"}, |
| 1196 | {"TX SMIC MUX0", "ADC1", "TX SWR_ADC1"}, |
| 1197 | {"TX SMIC MUX0", "ADC2", "TX SWR_ADC2"}, |
| 1198 | {"TX SMIC MUX0", "ADC3", "TX SWR_ADC3"}, |
| 1199 | {"TX SMIC MUX0", "SWR_DMIC0", "TX SWR_DMIC0"}, |
| 1200 | {"TX SMIC MUX0", "SWR_DMIC1", "TX SWR_DMIC1"}, |
| 1201 | {"TX SMIC MUX0", "SWR_DMIC2", "TX SWR_DMIC2"}, |
| 1202 | {"TX SMIC MUX0", "SWR_DMIC3", "TX SWR_DMIC3"}, |
| 1203 | {"TX SMIC MUX0", "SWR_DMIC4", "TX SWR_DMIC4"}, |
| 1204 | {"TX SMIC MUX0", "SWR_DMIC5", "TX SWR_DMIC5"}, |
| 1205 | {"TX SMIC MUX0", "SWR_DMIC6", "TX SWR_DMIC6"}, |
| 1206 | {"TX SMIC MUX0", "SWR_DMIC7", "TX SWR_DMIC7"}, |
| 1207 | |
| 1208 | {"TX DEC1 MUX", "MSM_DMIC", "TX DMIC MUX1"}, |
| 1209 | {"TX DMIC MUX1", "DMIC0", "TX DMIC0"}, |
| 1210 | {"TX DMIC MUX1", "DMIC1", "TX DMIC1"}, |
| 1211 | {"TX DMIC MUX1", "DMIC2", "TX DMIC2"}, |
| 1212 | {"TX DMIC MUX1", "DMIC3", "TX DMIC3"}, |
| 1213 | {"TX DMIC MUX1", "DMIC4", "TX DMIC4"}, |
| 1214 | {"TX DMIC MUX1", "DMIC5", "TX DMIC5"}, |
| 1215 | {"TX DMIC MUX1", "DMIC6", "TX DMIC6"}, |
| 1216 | {"TX DMIC MUX1", "DMIC7", "TX DMIC7"}, |
| 1217 | |
| 1218 | {"TX DEC1 MUX", "SWR_MIC", "TX SMIC MUX1"}, |
| 1219 | {"TX SMIC MUX1", "ADC0", "TX SWR_ADC0"}, |
| 1220 | {"TX SMIC MUX1", "ADC1", "TX SWR_ADC1"}, |
| 1221 | {"TX SMIC MUX1", "ADC2", "TX SWR_ADC2"}, |
| 1222 | {"TX SMIC MUX1", "ADC3", "TX SWR_ADC3"}, |
| 1223 | {"TX SMIC MUX1", "SWR_DMIC0", "TX SWR_DMIC0"}, |
| 1224 | {"TX SMIC MUX1", "SWR_DMIC1", "TX SWR_DMIC1"}, |
| 1225 | {"TX SMIC MUX1", "SWR_DMIC2", "TX SWR_DMIC2"}, |
| 1226 | {"TX SMIC MUX1", "SWR_DMIC3", "TX SWR_DMIC3"}, |
| 1227 | {"TX SMIC MUX1", "SWR_DMIC4", "TX SWR_DMIC4"}, |
| 1228 | {"TX SMIC MUX1", "SWR_DMIC5", "TX SWR_DMIC5"}, |
| 1229 | {"TX SMIC MUX1", "SWR_DMIC6", "TX SWR_DMIC6"}, |
| 1230 | {"TX SMIC MUX1", "SWR_DMIC7", "TX SWR_DMIC7"}, |
| 1231 | |
| 1232 | {"TX DEC2 MUX", "MSM_DMIC", "TX DMIC MUX2"}, |
| 1233 | {"TX DMIC MUX2", "DMIC0", "TX DMIC0"}, |
| 1234 | {"TX DMIC MUX2", "DMIC1", "TX DMIC1"}, |
| 1235 | {"TX DMIC MUX2", "DMIC2", "TX DMIC2"}, |
| 1236 | {"TX DMIC MUX2", "DMIC3", "TX DMIC3"}, |
| 1237 | {"TX DMIC MUX2", "DMIC4", "TX DMIC4"}, |
| 1238 | {"TX DMIC MUX2", "DMIC5", "TX DMIC5"}, |
| 1239 | {"TX DMIC MUX2", "DMIC6", "TX DMIC6"}, |
| 1240 | {"TX DMIC MUX2", "DMIC7", "TX DMIC7"}, |
| 1241 | |
| 1242 | {"TX DEC2 MUX", "SWR_MIC", "TX SMIC MUX2"}, |
| 1243 | {"TX SMIC MUX2", "ADC0", "TX SWR_ADC0"}, |
| 1244 | {"TX SMIC MUX2", "ADC1", "TX SWR_ADC1"}, |
| 1245 | {"TX SMIC MUX2", "ADC2", "TX SWR_ADC2"}, |
| 1246 | {"TX SMIC MUX2", "ADC3", "TX SWR_ADC3"}, |
| 1247 | {"TX SMIC MUX2", "SWR_DMIC0", "TX SWR_DMIC0"}, |
| 1248 | {"TX SMIC MUX2", "SWR_DMIC1", "TX SWR_DMIC1"}, |
| 1249 | {"TX SMIC MUX2", "SWR_DMIC2", "TX SWR_DMIC2"}, |
| 1250 | {"TX SMIC MUX2", "SWR_DMIC3", "TX SWR_DMIC3"}, |
| 1251 | {"TX SMIC MUX2", "SWR_DMIC4", "TX SWR_DMIC4"}, |
| 1252 | {"TX SMIC MUX2", "SWR_DMIC5", "TX SWR_DMIC5"}, |
| 1253 | {"TX SMIC MUX2", "SWR_DMIC6", "TX SWR_DMIC6"}, |
| 1254 | {"TX SMIC MUX2", "SWR_DMIC7", "TX SWR_DMIC7"}, |
| 1255 | |
| 1256 | {"TX DEC3 MUX", "MSM_DMIC", "TX DMIC MUX3"}, |
| 1257 | {"TX DMIC MUX3", "DMIC0", "TX DMIC0"}, |
| 1258 | {"TX DMIC MUX3", "DMIC1", "TX DMIC1"}, |
| 1259 | {"TX DMIC MUX3", "DMIC2", "TX DMIC2"}, |
| 1260 | {"TX DMIC MUX3", "DMIC3", "TX DMIC3"}, |
| 1261 | {"TX DMIC MUX3", "DMIC4", "TX DMIC4"}, |
| 1262 | {"TX DMIC MUX3", "DMIC5", "TX DMIC5"}, |
| 1263 | {"TX DMIC MUX3", "DMIC6", "TX DMIC6"}, |
| 1264 | {"TX DMIC MUX3", "DMIC7", "TX DMIC7"}, |
| 1265 | |
| 1266 | {"TX DEC3 MUX", "SWR_MIC", "TX SMIC MUX3"}, |
| 1267 | {"TX SMIC MUX3", "ADC0", "TX SWR_ADC0"}, |
| 1268 | {"TX SMIC MUX3", "ADC1", "TX SWR_ADC1"}, |
| 1269 | {"TX SMIC MUX3", "ADC2", "TX SWR_ADC2"}, |
| 1270 | {"TX SMIC MUX3", "ADC3", "TX SWR_ADC3"}, |
| 1271 | {"TX SMIC MUX3", "SWR_DMIC0", "TX SWR_DMIC0"}, |
| 1272 | {"TX SMIC MUX3", "SWR_DMIC1", "TX SWR_DMIC1"}, |
| 1273 | {"TX SMIC MUX3", "SWR_DMIC2", "TX SWR_DMIC2"}, |
| 1274 | {"TX SMIC MUX3", "SWR_DMIC3", "TX SWR_DMIC3"}, |
| 1275 | {"TX SMIC MUX3", "SWR_DMIC4", "TX SWR_DMIC4"}, |
| 1276 | {"TX SMIC MUX3", "SWR_DMIC5", "TX SWR_DMIC5"}, |
| 1277 | {"TX SMIC MUX3", "SWR_DMIC6", "TX SWR_DMIC6"}, |
| 1278 | {"TX SMIC MUX3", "SWR_DMIC7", "TX SWR_DMIC7"}, |
| 1279 | |
| 1280 | {"TX DEC4 MUX", "MSM_DMIC", "TX DMIC MUX4"}, |
| 1281 | {"TX DMIC MUX4", "DMIC0", "TX DMIC0"}, |
| 1282 | {"TX DMIC MUX4", "DMIC1", "TX DMIC1"}, |
| 1283 | {"TX DMIC MUX4", "DMIC2", "TX DMIC2"}, |
| 1284 | {"TX DMIC MUX4", "DMIC3", "TX DMIC3"}, |
| 1285 | {"TX DMIC MUX4", "DMIC4", "TX DMIC4"}, |
| 1286 | {"TX DMIC MUX4", "DMIC5", "TX DMIC5"}, |
| 1287 | {"TX DMIC MUX4", "DMIC6", "TX DMIC6"}, |
| 1288 | {"TX DMIC MUX4", "DMIC7", "TX DMIC7"}, |
| 1289 | |
| 1290 | {"TX DEC4 MUX", "SWR_MIC", "TX SMIC MUX4"}, |
| 1291 | {"TX SMIC MUX4", "ADC0", "TX SWR_ADC0"}, |
| 1292 | {"TX SMIC MUX4", "ADC1", "TX SWR_ADC1"}, |
| 1293 | {"TX SMIC MUX4", "ADC2", "TX SWR_ADC2"}, |
| 1294 | {"TX SMIC MUX4", "ADC3", "TX SWR_ADC3"}, |
| 1295 | {"TX SMIC MUX4", "SWR_DMIC0", "TX SWR_DMIC0"}, |
| 1296 | {"TX SMIC MUX4", "SWR_DMIC1", "TX SWR_DMIC1"}, |
| 1297 | {"TX SMIC MUX4", "SWR_DMIC2", "TX SWR_DMIC2"}, |
| 1298 | {"TX SMIC MUX4", "SWR_DMIC3", "TX SWR_DMIC3"}, |
| 1299 | {"TX SMIC MUX4", "SWR_DMIC4", "TX SWR_DMIC4"}, |
| 1300 | {"TX SMIC MUX4", "SWR_DMIC5", "TX SWR_DMIC5"}, |
| 1301 | {"TX SMIC MUX4", "SWR_DMIC6", "TX SWR_DMIC6"}, |
| 1302 | {"TX SMIC MUX4", "SWR_DMIC7", "TX SWR_DMIC7"}, |
| 1303 | |
| 1304 | {"TX DEC5 MUX", "MSM_DMIC", "TX DMIC MUX5"}, |
| 1305 | {"TX DMIC MUX5", "DMIC0", "TX DMIC0"}, |
| 1306 | {"TX DMIC MUX5", "DMIC1", "TX DMIC1"}, |
| 1307 | {"TX DMIC MUX5", "DMIC2", "TX DMIC2"}, |
| 1308 | {"TX DMIC MUX5", "DMIC3", "TX DMIC3"}, |
| 1309 | {"TX DMIC MUX5", "DMIC4", "TX DMIC4"}, |
| 1310 | {"TX DMIC MUX5", "DMIC5", "TX DMIC5"}, |
| 1311 | {"TX DMIC MUX5", "DMIC6", "TX DMIC6"}, |
| 1312 | {"TX DMIC MUX5", "DMIC7", "TX DMIC7"}, |
| 1313 | |
| 1314 | {"TX DEC5 MUX", "SWR_MIC", "TX SMIC MUX5"}, |
| 1315 | {"TX SMIC MUX5", "ADC0", "TX SWR_ADC0"}, |
| 1316 | {"TX SMIC MUX5", "ADC1", "TX SWR_ADC1"}, |
| 1317 | {"TX SMIC MUX5", "ADC2", "TX SWR_ADC2"}, |
| 1318 | {"TX SMIC MUX5", "ADC3", "TX SWR_ADC3"}, |
| 1319 | {"TX SMIC MUX5", "SWR_DMIC0", "TX SWR_DMIC0"}, |
| 1320 | {"TX SMIC MUX5", "SWR_DMIC1", "TX SWR_DMIC1"}, |
| 1321 | {"TX SMIC MUX5", "SWR_DMIC2", "TX SWR_DMIC2"}, |
| 1322 | {"TX SMIC MUX5", "SWR_DMIC3", "TX SWR_DMIC3"}, |
| 1323 | {"TX SMIC MUX5", "SWR_DMIC4", "TX SWR_DMIC4"}, |
| 1324 | {"TX SMIC MUX5", "SWR_DMIC5", "TX SWR_DMIC5"}, |
| 1325 | {"TX SMIC MUX5", "SWR_DMIC6", "TX SWR_DMIC6"}, |
| 1326 | {"TX SMIC MUX5", "SWR_DMIC7", "TX SWR_DMIC7"}, |
| 1327 | |
| 1328 | {"TX DEC6 MUX", "MSM_DMIC", "TX DMIC MUX6"}, |
| 1329 | {"TX DMIC MUX6", "DMIC0", "TX DMIC0"}, |
| 1330 | {"TX DMIC MUX6", "DMIC1", "TX DMIC1"}, |
| 1331 | {"TX DMIC MUX6", "DMIC2", "TX DMIC2"}, |
| 1332 | {"TX DMIC MUX6", "DMIC3", "TX DMIC3"}, |
| 1333 | {"TX DMIC MUX6", "DMIC4", "TX DMIC4"}, |
| 1334 | {"TX DMIC MUX6", "DMIC5", "TX DMIC5"}, |
| 1335 | {"TX DMIC MUX6", "DMIC6", "TX DMIC6"}, |
| 1336 | {"TX DMIC MUX6", "DMIC7", "TX DMIC7"}, |
| 1337 | |
| 1338 | {"TX DEC6 MUX", "SWR_MIC", "TX SMIC MUX6"}, |
| 1339 | {"TX SMIC MUX6", "ADC0", "TX SWR_ADC0"}, |
| 1340 | {"TX SMIC MUX6", "ADC1", "TX SWR_ADC1"}, |
| 1341 | {"TX SMIC MUX6", "ADC2", "TX SWR_ADC2"}, |
| 1342 | {"TX SMIC MUX6", "ADC3", "TX SWR_ADC3"}, |
| 1343 | {"TX SMIC MUX6", "SWR_DMIC0", "TX SWR_DMIC0"}, |
| 1344 | {"TX SMIC MUX6", "SWR_DMIC1", "TX SWR_DMIC1"}, |
| 1345 | {"TX SMIC MUX6", "SWR_DMIC2", "TX SWR_DMIC2"}, |
| 1346 | {"TX SMIC MUX6", "SWR_DMIC3", "TX SWR_DMIC3"}, |
| 1347 | {"TX SMIC MUX6", "SWR_DMIC4", "TX SWR_DMIC4"}, |
| 1348 | {"TX SMIC MUX6", "SWR_DMIC5", "TX SWR_DMIC5"}, |
| 1349 | {"TX SMIC MUX6", "SWR_DMIC6", "TX SWR_DMIC6"}, |
| 1350 | {"TX SMIC MUX6", "SWR_DMIC7", "TX SWR_DMIC7"}, |
| 1351 | |
| 1352 | {"TX DEC7 MUX", "MSM_DMIC", "TX DMIC MUX7"}, |
| 1353 | {"TX DMIC MUX7", "DMIC0", "TX DMIC0"}, |
| 1354 | {"TX DMIC MUX7", "DMIC1", "TX DMIC1"}, |
| 1355 | {"TX DMIC MUX7", "DMIC2", "TX DMIC2"}, |
| 1356 | {"TX DMIC MUX7", "DMIC3", "TX DMIC3"}, |
| 1357 | {"TX DMIC MUX7", "DMIC4", "TX DMIC4"}, |
| 1358 | {"TX DMIC MUX7", "DMIC5", "TX DMIC5"}, |
| 1359 | {"TX DMIC MUX7", "DMIC6", "TX DMIC6"}, |
| 1360 | {"TX DMIC MUX7", "DMIC7", "TX DMIC7"}, |
| 1361 | |
| 1362 | {"TX DEC7 MUX", "SWR_MIC", "TX SMIC MUX7"}, |
| 1363 | {"TX SMIC MUX7", "ADC0", "TX SWR_ADC0"}, |
| 1364 | {"TX SMIC MUX7", "ADC1", "TX SWR_ADC1"}, |
| 1365 | {"TX SMIC MUX7", "ADC2", "TX SWR_ADC2"}, |
| 1366 | {"TX SMIC MUX7", "ADC3", "TX SWR_ADC3"}, |
| 1367 | {"TX SMIC MUX7", "SWR_DMIC0", "TX SWR_DMIC0"}, |
| 1368 | {"TX SMIC MUX7", "SWR_DMIC1", "TX SWR_DMIC1"}, |
| 1369 | {"TX SMIC MUX7", "SWR_DMIC2", "TX SWR_DMIC2"}, |
| 1370 | {"TX SMIC MUX7", "SWR_DMIC3", "TX SWR_DMIC3"}, |
| 1371 | {"TX SMIC MUX7", "SWR_DMIC4", "TX SWR_DMIC4"}, |
| 1372 | {"TX SMIC MUX7", "SWR_DMIC5", "TX SWR_DMIC5"}, |
| 1373 | {"TX SMIC MUX7", "SWR_DMIC6", "TX SWR_DMIC6"}, |
| 1374 | {"TX SMIC MUX7", "SWR_DMIC7", "TX SWR_DMIC7"}, |
| 1375 | }; |
| 1376 | |
| 1377 | static const struct snd_kcontrol_new tx_macro_snd_controls[] = { |
| 1378 | SOC_SINGLE_SX_TLV("TX_DEC0 Volume", |
| 1379 | BOLERO_CDC_TX0_TX_VOL_CTL, |
| 1380 | 0, -84, 40, digital_gain), |
| 1381 | SOC_SINGLE_SX_TLV("TX_DEC1 Volume", |
| 1382 | BOLERO_CDC_TX1_TX_VOL_CTL, |
| 1383 | 0, -84, 40, digital_gain), |
| 1384 | SOC_SINGLE_SX_TLV("TX_DEC2 Volume", |
| 1385 | BOLERO_CDC_TX2_TX_VOL_CTL, |
| 1386 | 0, -84, 40, digital_gain), |
| 1387 | SOC_SINGLE_SX_TLV("TX_DEC3 Volume", |
| 1388 | BOLERO_CDC_TX3_TX_VOL_CTL, |
| 1389 | 0, -84, 40, digital_gain), |
| 1390 | SOC_SINGLE_SX_TLV("TX_DEC4 Volume", |
| 1391 | BOLERO_CDC_TX4_TX_VOL_CTL, |
| 1392 | 0, -84, 40, digital_gain), |
| 1393 | SOC_SINGLE_SX_TLV("TX_DEC5 Volume", |
| 1394 | BOLERO_CDC_TX5_TX_VOL_CTL, |
| 1395 | 0, -84, 40, digital_gain), |
| 1396 | SOC_SINGLE_SX_TLV("TX_DEC6 Volume", |
| 1397 | BOLERO_CDC_TX6_TX_VOL_CTL, |
| 1398 | 0, -84, 40, digital_gain), |
| 1399 | SOC_SINGLE_SX_TLV("TX_DEC7 Volume", |
| 1400 | BOLERO_CDC_TX7_TX_VOL_CTL, |
| 1401 | 0, -84, 40, digital_gain), |
| 1402 | }; |
| 1403 | |
| 1404 | static int tx_macro_swrm_clock(void *handle, bool enable) |
| 1405 | { |
| 1406 | struct tx_macro_priv *tx_priv = (struct tx_macro_priv *) handle; |
| 1407 | struct regmap *regmap = dev_get_regmap(tx_priv->dev->parent, NULL); |
| 1408 | int ret = 0; |
| 1409 | |
Tanya Dixit | 8530fb9 | 2018-09-14 16:01:25 +0530 | [diff] [blame] | 1410 | if (regmap == NULL) { |
| 1411 | dev_err(tx_priv->dev, "%s: regmap is NULL\n", __func__); |
| 1412 | return -EINVAL; |
| 1413 | } |
| 1414 | |
Laxminath Kasam | 989fccf | 2018-06-15 16:53:31 +0530 | [diff] [blame] | 1415 | mutex_lock(&tx_priv->swr_clk_lock); |
| 1416 | |
| 1417 | dev_dbg(tx_priv->dev, "%s: swrm clock %s\n", |
| 1418 | __func__, (enable ? "enable" : "disable")); |
| 1419 | if (enable) { |
| 1420 | if (tx_priv->swr_clk_users == 0) { |
| 1421 | ret = tx_macro_mclk_enable(tx_priv, 1); |
| 1422 | if (ret < 0) { |
| 1423 | dev_err(tx_priv->dev, |
| 1424 | "%s: request clock enable failed\n", |
| 1425 | __func__); |
| 1426 | goto exit; |
| 1427 | } |
| 1428 | regmap_update_bits(regmap, |
| 1429 | BOLERO_CDC_TX_CLK_RST_CTRL_SWR_CONTROL, |
| 1430 | 0x01, 0x01); |
| 1431 | regmap_update_bits(regmap, |
| 1432 | BOLERO_CDC_TX_CLK_RST_CTRL_SWR_CONTROL, |
| 1433 | 0x1C, 0x0C); |
| 1434 | msm_cdc_pinctrl_select_active_state( |
| 1435 | tx_priv->tx_swr_gpio_p); |
| 1436 | } |
| 1437 | tx_priv->swr_clk_users++; |
| 1438 | } else { |
| 1439 | if (tx_priv->swr_clk_users <= 0) { |
| 1440 | dev_err(tx_priv->dev, |
| 1441 | "tx swrm clock users already 0\n"); |
| 1442 | tx_priv->swr_clk_users = 0; |
| 1443 | goto exit; |
| 1444 | } |
| 1445 | tx_priv->swr_clk_users--; |
| 1446 | if (tx_priv->swr_clk_users == 0) { |
| 1447 | regmap_update_bits(regmap, |
| 1448 | BOLERO_CDC_TX_CLK_RST_CTRL_SWR_CONTROL, |
| 1449 | 0x01, 0x00); |
| 1450 | msm_cdc_pinctrl_select_sleep_state( |
| 1451 | tx_priv->tx_swr_gpio_p); |
| 1452 | tx_macro_mclk_enable(tx_priv, 0); |
| 1453 | } |
| 1454 | } |
| 1455 | dev_dbg(tx_priv->dev, "%s: swrm clock users %d\n", |
| 1456 | __func__, tx_priv->swr_clk_users); |
| 1457 | exit: |
| 1458 | mutex_unlock(&tx_priv->swr_clk_lock); |
| 1459 | return ret; |
| 1460 | } |
| 1461 | |
| 1462 | static int tx_macro_validate_dmic_sample_rate(u32 dmic_sample_rate, |
| 1463 | struct tx_macro_priv *tx_priv) |
| 1464 | { |
| 1465 | u32 div_factor = TX_MACRO_CLK_DIV_2; |
| 1466 | u32 mclk_rate = TX_MACRO_MCLK_FREQ; |
| 1467 | |
| 1468 | if (dmic_sample_rate == TX_MACRO_DMIC_SAMPLE_RATE_UNDEFINED || |
| 1469 | mclk_rate % dmic_sample_rate != 0) |
| 1470 | goto undefined_rate; |
| 1471 | |
| 1472 | div_factor = mclk_rate / dmic_sample_rate; |
| 1473 | |
| 1474 | switch (div_factor) { |
| 1475 | case 2: |
| 1476 | tx_priv->dmic_clk_div = TX_MACRO_CLK_DIV_2; |
| 1477 | break; |
| 1478 | case 3: |
| 1479 | tx_priv->dmic_clk_div = TX_MACRO_CLK_DIV_3; |
| 1480 | break; |
| 1481 | case 4: |
| 1482 | tx_priv->dmic_clk_div = TX_MACRO_CLK_DIV_4; |
| 1483 | break; |
| 1484 | case 6: |
| 1485 | tx_priv->dmic_clk_div = TX_MACRO_CLK_DIV_6; |
| 1486 | break; |
| 1487 | case 8: |
| 1488 | tx_priv->dmic_clk_div = TX_MACRO_CLK_DIV_8; |
| 1489 | break; |
| 1490 | case 16: |
| 1491 | tx_priv->dmic_clk_div = TX_MACRO_CLK_DIV_16; |
| 1492 | break; |
| 1493 | default: |
| 1494 | /* Any other DIV factor is invalid */ |
| 1495 | goto undefined_rate; |
| 1496 | } |
| 1497 | |
| 1498 | /* Valid dmic DIV factors */ |
| 1499 | dev_dbg(tx_priv->dev, "%s: DMIC_DIV = %u, mclk_rate = %u\n", |
| 1500 | __func__, div_factor, mclk_rate); |
| 1501 | |
| 1502 | return dmic_sample_rate; |
| 1503 | |
| 1504 | undefined_rate: |
| 1505 | dev_dbg(tx_priv->dev, "%s: Invalid rate %d, for mclk %d\n", |
| 1506 | __func__, dmic_sample_rate, mclk_rate); |
| 1507 | dmic_sample_rate = TX_MACRO_DMIC_SAMPLE_RATE_UNDEFINED; |
| 1508 | |
| 1509 | return dmic_sample_rate; |
| 1510 | } |
| 1511 | |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame^] | 1512 | static int tx_macro_init(struct snd_soc_component *component) |
Laxminath Kasam | 989fccf | 2018-06-15 16:53:31 +0530 | [diff] [blame] | 1513 | { |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame^] | 1514 | struct snd_soc_dapm_context *dapm = |
| 1515 | snd_soc_component_get_dapm(component); |
Laxminath Kasam | 989fccf | 2018-06-15 16:53:31 +0530 | [diff] [blame] | 1516 | int ret = 0, i = 0; |
| 1517 | struct device *tx_dev = NULL; |
| 1518 | struct tx_macro_priv *tx_priv = NULL; |
| 1519 | |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame^] | 1520 | tx_dev = bolero_get_device_ptr(component->dev, TX_MACRO); |
Laxminath Kasam | 989fccf | 2018-06-15 16:53:31 +0530 | [diff] [blame] | 1521 | if (!tx_dev) { |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame^] | 1522 | dev_err(component->dev, |
Laxminath Kasam | 989fccf | 2018-06-15 16:53:31 +0530 | [diff] [blame] | 1523 | "%s: null device for macro!\n", __func__); |
| 1524 | return -EINVAL; |
| 1525 | } |
| 1526 | tx_priv = dev_get_drvdata(tx_dev); |
| 1527 | if (!tx_priv) { |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame^] | 1528 | dev_err(component->dev, |
Laxminath Kasam | 989fccf | 2018-06-15 16:53:31 +0530 | [diff] [blame] | 1529 | "%s: priv is null for macro!\n", __func__); |
| 1530 | return -EINVAL; |
| 1531 | } |
| 1532 | ret = snd_soc_dapm_new_controls(dapm, tx_macro_dapm_widgets, |
| 1533 | ARRAY_SIZE(tx_macro_dapm_widgets)); |
| 1534 | if (ret < 0) { |
| 1535 | dev_err(tx_dev, "%s: Failed to add controls\n", __func__); |
| 1536 | return ret; |
| 1537 | } |
| 1538 | |
| 1539 | ret = snd_soc_dapm_add_routes(dapm, tx_audio_map, |
| 1540 | ARRAY_SIZE(tx_audio_map)); |
| 1541 | if (ret < 0) { |
| 1542 | dev_err(tx_dev, "%s: Failed to add routes\n", __func__); |
| 1543 | return ret; |
| 1544 | } |
| 1545 | |
| 1546 | ret = snd_soc_dapm_new_widgets(dapm->card); |
| 1547 | if (ret < 0) { |
| 1548 | dev_err(tx_dev, "%s: Failed to add widgets\n", __func__); |
| 1549 | return ret; |
| 1550 | } |
| 1551 | |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame^] | 1552 | ret = snd_soc_add_component_controls(component, tx_macro_snd_controls, |
Laxminath Kasam | 989fccf | 2018-06-15 16:53:31 +0530 | [diff] [blame] | 1553 | ARRAY_SIZE(tx_macro_snd_controls)); |
| 1554 | if (ret < 0) { |
| 1555 | dev_err(tx_dev, "%s: Failed to add snd_ctls\n", __func__); |
| 1556 | return ret; |
| 1557 | } |
Laxminath Kasam | 638b560 | 2018-09-24 13:19:52 +0530 | [diff] [blame] | 1558 | |
| 1559 | snd_soc_dapm_ignore_suspend(dapm, "TX_AIF1 Capture"); |
| 1560 | snd_soc_dapm_ignore_suspend(dapm, "TX_AIF2 Capture"); |
| 1561 | snd_soc_dapm_ignore_suspend(dapm, "TX SWR_ADC0"); |
| 1562 | snd_soc_dapm_ignore_suspend(dapm, "TX SWR_ADC1"); |
| 1563 | snd_soc_dapm_ignore_suspend(dapm, "TX SWR_ADC2"); |
| 1564 | snd_soc_dapm_ignore_suspend(dapm, "TX SWR_ADC3"); |
| 1565 | snd_soc_dapm_ignore_suspend(dapm, "TX SWR_MIC0"); |
| 1566 | snd_soc_dapm_ignore_suspend(dapm, "TX SWR_MIC1"); |
| 1567 | snd_soc_dapm_ignore_suspend(dapm, "TX SWR_MIC2"); |
| 1568 | snd_soc_dapm_ignore_suspend(dapm, "TX SWR_MIC3"); |
| 1569 | snd_soc_dapm_ignore_suspend(dapm, "TX SWR_MIC4"); |
| 1570 | snd_soc_dapm_ignore_suspend(dapm, "TX SWR_MIC5"); |
| 1571 | snd_soc_dapm_ignore_suspend(dapm, "TX SWR_MIC6"); |
| 1572 | snd_soc_dapm_ignore_suspend(dapm, "TX SWR_MIC7"); |
| 1573 | snd_soc_dapm_sync(dapm); |
| 1574 | |
Laxminath Kasam | 989fccf | 2018-06-15 16:53:31 +0530 | [diff] [blame] | 1575 | for (i = 0; i < NUM_DECIMATORS; i++) { |
| 1576 | tx_priv->tx_hpf_work[i].tx_priv = tx_priv; |
| 1577 | tx_priv->tx_hpf_work[i].decimator = i; |
| 1578 | INIT_DELAYED_WORK(&tx_priv->tx_hpf_work[i].dwork, |
| 1579 | tx_macro_tx_hpf_corner_freq_callback); |
| 1580 | } |
| 1581 | |
| 1582 | for (i = 0; i < NUM_DECIMATORS; i++) { |
| 1583 | tx_priv->tx_mute_dwork[i].tx_priv = tx_priv; |
| 1584 | tx_priv->tx_mute_dwork[i].decimator = i; |
| 1585 | INIT_DELAYED_WORK(&tx_priv->tx_mute_dwork[i].dwork, |
| 1586 | tx_macro_mute_update_callback); |
| 1587 | } |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame^] | 1588 | tx_priv->component = component; |
Laxminath Kasam | 989fccf | 2018-06-15 16:53:31 +0530 | [diff] [blame] | 1589 | |
| 1590 | return 0; |
| 1591 | } |
| 1592 | |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame^] | 1593 | static int tx_macro_deinit(struct snd_soc_component *component) |
Laxminath Kasam | 989fccf | 2018-06-15 16:53:31 +0530 | [diff] [blame] | 1594 | { |
| 1595 | struct device *tx_dev = NULL; |
| 1596 | struct tx_macro_priv *tx_priv = NULL; |
| 1597 | |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame^] | 1598 | if (!tx_macro_get_data(component, &tx_dev, &tx_priv, __func__)) |
Laxminath Kasam | 989fccf | 2018-06-15 16:53:31 +0530 | [diff] [blame] | 1599 | return -EINVAL; |
| 1600 | |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame^] | 1601 | tx_priv->component = NULL; |
Laxminath Kasam | 989fccf | 2018-06-15 16:53:31 +0530 | [diff] [blame] | 1602 | return 0; |
| 1603 | } |
| 1604 | |
| 1605 | static void tx_macro_add_child_devices(struct work_struct *work) |
| 1606 | { |
| 1607 | struct tx_macro_priv *tx_priv = NULL; |
| 1608 | struct platform_device *pdev = NULL; |
| 1609 | struct device_node *node = NULL; |
| 1610 | struct tx_macro_swr_ctrl_data *swr_ctrl_data = NULL, *temp = NULL; |
| 1611 | int ret = 0; |
| 1612 | u16 count = 0, ctrl_num = 0; |
| 1613 | struct tx_macro_swr_ctrl_platform_data *platdata = NULL; |
| 1614 | char plat_dev_name[TX_MACRO_SWR_STRING_LEN] = ""; |
| 1615 | bool tx_swr_master_node = false; |
| 1616 | |
| 1617 | tx_priv = container_of(work, struct tx_macro_priv, |
| 1618 | tx_macro_add_child_devices_work); |
| 1619 | if (!tx_priv) { |
| 1620 | pr_err("%s: Memory for tx_priv does not exist\n", |
| 1621 | __func__); |
| 1622 | return; |
| 1623 | } |
| 1624 | |
| 1625 | if (!tx_priv->dev) { |
| 1626 | pr_err("%s: tx dev does not exist\n", __func__); |
| 1627 | return; |
| 1628 | } |
| 1629 | |
| 1630 | if (!tx_priv->dev->of_node) { |
| 1631 | dev_err(tx_priv->dev, |
| 1632 | "%s: DT node for tx_priv does not exist\n", __func__); |
| 1633 | return; |
| 1634 | } |
| 1635 | |
| 1636 | platdata = &tx_priv->swr_plat_data; |
| 1637 | tx_priv->child_count = 0; |
| 1638 | |
| 1639 | for_each_available_child_of_node(tx_priv->dev->of_node, node) { |
| 1640 | tx_swr_master_node = false; |
| 1641 | if (strnstr(node->name, "tx_swr_master", |
| 1642 | strlen("tx_swr_master")) != NULL) |
| 1643 | tx_swr_master_node = true; |
| 1644 | |
| 1645 | if (tx_swr_master_node) |
| 1646 | strlcpy(plat_dev_name, "tx_swr_ctrl", |
| 1647 | (TX_MACRO_SWR_STRING_LEN - 1)); |
| 1648 | else |
| 1649 | strlcpy(plat_dev_name, node->name, |
| 1650 | (TX_MACRO_SWR_STRING_LEN - 1)); |
| 1651 | |
| 1652 | pdev = platform_device_alloc(plat_dev_name, -1); |
| 1653 | if (!pdev) { |
| 1654 | dev_err(tx_priv->dev, "%s: pdev memory alloc failed\n", |
| 1655 | __func__); |
| 1656 | ret = -ENOMEM; |
| 1657 | goto err; |
| 1658 | } |
| 1659 | pdev->dev.parent = tx_priv->dev; |
| 1660 | pdev->dev.of_node = node; |
| 1661 | |
| 1662 | if (tx_swr_master_node) { |
| 1663 | ret = platform_device_add_data(pdev, platdata, |
| 1664 | sizeof(*platdata)); |
| 1665 | if (ret) { |
| 1666 | dev_err(&pdev->dev, |
| 1667 | "%s: cannot add plat data ctrl:%d\n", |
| 1668 | __func__, ctrl_num); |
| 1669 | goto fail_pdev_add; |
| 1670 | } |
| 1671 | } |
| 1672 | |
| 1673 | ret = platform_device_add(pdev); |
| 1674 | if (ret) { |
| 1675 | dev_err(&pdev->dev, |
| 1676 | "%s: Cannot add platform device\n", |
| 1677 | __func__); |
| 1678 | goto fail_pdev_add; |
| 1679 | } |
| 1680 | |
| 1681 | if (tx_swr_master_node) { |
| 1682 | temp = krealloc(swr_ctrl_data, |
| 1683 | (ctrl_num + 1) * sizeof( |
| 1684 | struct tx_macro_swr_ctrl_data), |
| 1685 | GFP_KERNEL); |
| 1686 | if (!temp) { |
| 1687 | ret = -ENOMEM; |
| 1688 | goto fail_pdev_add; |
| 1689 | } |
| 1690 | swr_ctrl_data = temp; |
| 1691 | swr_ctrl_data[ctrl_num].tx_swr_pdev = pdev; |
| 1692 | ctrl_num++; |
| 1693 | dev_dbg(&pdev->dev, |
| 1694 | "%s: Added soundwire ctrl device(s)\n", |
| 1695 | __func__); |
| 1696 | tx_priv->swr_ctrl_data = swr_ctrl_data; |
| 1697 | } |
| 1698 | if (tx_priv->child_count < TX_MACRO_CHILD_DEVICES_MAX) |
| 1699 | tx_priv->pdev_child_devices[ |
| 1700 | tx_priv->child_count++] = pdev; |
| 1701 | else |
| 1702 | goto err; |
| 1703 | } |
| 1704 | return; |
| 1705 | fail_pdev_add: |
| 1706 | for (count = 0; count < tx_priv->child_count; count++) |
| 1707 | platform_device_put(tx_priv->pdev_child_devices[count]); |
| 1708 | err: |
| 1709 | return; |
| 1710 | } |
| 1711 | |
| 1712 | static void tx_macro_init_ops(struct macro_ops *ops, |
| 1713 | char __iomem *tx_io_base) |
| 1714 | { |
| 1715 | memset(ops, 0, sizeof(struct macro_ops)); |
| 1716 | ops->init = tx_macro_init; |
| 1717 | ops->exit = tx_macro_deinit; |
| 1718 | ops->io_base = tx_io_base; |
| 1719 | ops->dai_ptr = tx_macro_dai; |
| 1720 | ops->num_dais = ARRAY_SIZE(tx_macro_dai); |
| 1721 | ops->mclk_fn = tx_macro_mclk_ctrl; |
Laxminath Kasam | fb0d683 | 2018-09-22 01:49:52 +0530 | [diff] [blame] | 1722 | ops->event_handler = tx_macro_event_handler; |
Aditya Bavanari | c4e9612 | 2018-11-14 14:46:38 +0530 | [diff] [blame] | 1723 | ops->reg_wake_irq = tx_macro_reg_wake_irq; |
Laxminath Kasam | 989fccf | 2018-06-15 16:53:31 +0530 | [diff] [blame] | 1724 | } |
| 1725 | |
| 1726 | static int tx_macro_probe(struct platform_device *pdev) |
| 1727 | { |
| 1728 | struct macro_ops ops = {0}; |
| 1729 | struct tx_macro_priv *tx_priv = NULL; |
| 1730 | u32 tx_base_addr = 0, sample_rate = 0; |
| 1731 | char __iomem *tx_io_base = NULL; |
| 1732 | struct clk *tx_core_clk = NULL, *tx_npl_clk = NULL; |
| 1733 | int ret = 0; |
| 1734 | const char *dmic_sample_rate = "qcom,tx-dmic-sample-rate"; |
| 1735 | |
| 1736 | tx_priv = devm_kzalloc(&pdev->dev, sizeof(struct tx_macro_priv), |
| 1737 | GFP_KERNEL); |
| 1738 | if (!tx_priv) |
| 1739 | return -ENOMEM; |
| 1740 | platform_set_drvdata(pdev, tx_priv); |
| 1741 | |
| 1742 | tx_priv->dev = &pdev->dev; |
| 1743 | ret = of_property_read_u32(pdev->dev.of_node, "reg", |
| 1744 | &tx_base_addr); |
| 1745 | if (ret) { |
| 1746 | dev_err(&pdev->dev, "%s: could not find %s entry in dt\n", |
| 1747 | __func__, "reg"); |
| 1748 | return ret; |
| 1749 | } |
| 1750 | dev_set_drvdata(&pdev->dev, tx_priv); |
| 1751 | tx_priv->tx_swr_gpio_p = of_parse_phandle(pdev->dev.of_node, |
| 1752 | "qcom,tx-swr-gpios", 0); |
| 1753 | if (!tx_priv->tx_swr_gpio_p) { |
| 1754 | dev_err(&pdev->dev, "%s: swr_gpios handle not provided!\n", |
| 1755 | __func__); |
| 1756 | return -EINVAL; |
| 1757 | } |
| 1758 | tx_io_base = devm_ioremap(&pdev->dev, |
| 1759 | tx_base_addr, TX_MACRO_MAX_OFFSET); |
| 1760 | if (!tx_io_base) { |
| 1761 | dev_err(&pdev->dev, "%s: ioremap failed\n", __func__); |
| 1762 | return -ENOMEM; |
| 1763 | } |
| 1764 | tx_priv->tx_io_base = tx_io_base; |
| 1765 | ret = of_property_read_u32(pdev->dev.of_node, dmic_sample_rate, |
| 1766 | &sample_rate); |
| 1767 | if (ret) { |
| 1768 | dev_err(&pdev->dev, |
| 1769 | "%s: could not find sample_rate entry in dt\n", |
| 1770 | __func__); |
| 1771 | tx_priv->dmic_clk_div = TX_MACRO_CLK_DIV_2; |
| 1772 | } else { |
| 1773 | if (tx_macro_validate_dmic_sample_rate( |
| 1774 | sample_rate, tx_priv) == TX_MACRO_DMIC_SAMPLE_RATE_UNDEFINED) |
| 1775 | return -EINVAL; |
| 1776 | } |
| 1777 | |
| 1778 | INIT_WORK(&tx_priv->tx_macro_add_child_devices_work, |
| 1779 | tx_macro_add_child_devices); |
| 1780 | tx_priv->swr_plat_data.handle = (void *) tx_priv; |
| 1781 | tx_priv->swr_plat_data.read = NULL; |
| 1782 | tx_priv->swr_plat_data.write = NULL; |
| 1783 | tx_priv->swr_plat_data.bulk_write = NULL; |
| 1784 | tx_priv->swr_plat_data.clk = tx_macro_swrm_clock; |
| 1785 | tx_priv->swr_plat_data.handle_irq = NULL; |
| 1786 | /* Register MCLK for tx macro */ |
| 1787 | tx_core_clk = devm_clk_get(&pdev->dev, "tx_core_clk"); |
| 1788 | if (IS_ERR(tx_core_clk)) { |
| 1789 | ret = PTR_ERR(tx_core_clk); |
| 1790 | dev_err(&pdev->dev, "%s: clk get %s failed %d\n", |
| 1791 | __func__, "tx_core_clk", ret); |
| 1792 | return ret; |
| 1793 | } |
| 1794 | tx_priv->tx_core_clk = tx_core_clk; |
| 1795 | /* Register npl clk for soundwire */ |
| 1796 | tx_npl_clk = devm_clk_get(&pdev->dev, "tx_npl_clk"); |
| 1797 | if (IS_ERR(tx_npl_clk)) { |
| 1798 | ret = PTR_ERR(tx_npl_clk); |
| 1799 | dev_err(&pdev->dev, "%s: clk get %s failed %d\n", |
| 1800 | __func__, "tx_npl_clk", ret); |
| 1801 | return ret; |
| 1802 | } |
| 1803 | tx_priv->tx_npl_clk = tx_npl_clk; |
| 1804 | |
| 1805 | mutex_init(&tx_priv->mclk_lock); |
| 1806 | mutex_init(&tx_priv->swr_clk_lock); |
| 1807 | tx_macro_init_ops(&ops, tx_io_base); |
| 1808 | ret = bolero_register_macro(&pdev->dev, TX_MACRO, &ops); |
| 1809 | if (ret) { |
| 1810 | dev_err(&pdev->dev, |
| 1811 | "%s: register macro failed\n", __func__); |
| 1812 | goto err_reg_macro; |
| 1813 | } |
| 1814 | schedule_work(&tx_priv->tx_macro_add_child_devices_work); |
| 1815 | return 0; |
| 1816 | err_reg_macro: |
| 1817 | mutex_destroy(&tx_priv->mclk_lock); |
| 1818 | mutex_destroy(&tx_priv->swr_clk_lock); |
| 1819 | return ret; |
| 1820 | } |
| 1821 | |
| 1822 | static int tx_macro_remove(struct platform_device *pdev) |
| 1823 | { |
| 1824 | struct tx_macro_priv *tx_priv = NULL; |
| 1825 | u16 count = 0; |
| 1826 | |
| 1827 | tx_priv = platform_get_drvdata(pdev); |
| 1828 | |
| 1829 | if (!tx_priv) |
| 1830 | return -EINVAL; |
| 1831 | |
| 1832 | kfree(tx_priv->swr_ctrl_data); |
| 1833 | for (count = 0; count < tx_priv->child_count && |
| 1834 | count < TX_MACRO_CHILD_DEVICES_MAX; count++) |
| 1835 | platform_device_unregister(tx_priv->pdev_child_devices[count]); |
| 1836 | |
| 1837 | mutex_destroy(&tx_priv->mclk_lock); |
| 1838 | mutex_destroy(&tx_priv->swr_clk_lock); |
| 1839 | bolero_unregister_macro(&pdev->dev, TX_MACRO); |
| 1840 | return 0; |
| 1841 | } |
| 1842 | |
| 1843 | |
| 1844 | static const struct of_device_id tx_macro_dt_match[] = { |
| 1845 | {.compatible = "qcom,tx-macro"}, |
| 1846 | {} |
| 1847 | }; |
| 1848 | |
| 1849 | static struct platform_driver tx_macro_driver = { |
| 1850 | .driver = { |
| 1851 | .name = "tx_macro", |
| 1852 | .owner = THIS_MODULE, |
| 1853 | .of_match_table = tx_macro_dt_match, |
| 1854 | }, |
| 1855 | .probe = tx_macro_probe, |
| 1856 | .remove = tx_macro_remove, |
| 1857 | }; |
| 1858 | |
| 1859 | module_platform_driver(tx_macro_driver); |
| 1860 | |
| 1861 | MODULE_DESCRIPTION("TX macro driver"); |
| 1862 | MODULE_LICENSE("GPL v2"); |