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gerrit-public.fairphone.software / platform / vendor / opensource / audio-kernel / c4fbb03910b916d162cc1007aa790d3da11ee623 / . / asoc / sdm660-common.c
blob: abd85df3189cb79e3d6c61467653eec4df3006c6 [file] [log] [blame]
Soumya Managolibbeb8ee2019-03-18 17:05:29 +0530[diff] [blame]1/* Copyright (c) 2015-2019, The Linux Foundation. All rights reserved.
Asish Bhattacharya8e2277f2017-07-20 18:31:55 +0530[diff] [blame]2 *
3 * This program is free software; you can redistribute it and/or modify
4 * it under the terms of the GNU General Public License version 2 and
5 * only version 2 as published by the Free Software Foundation.
6 *
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
11 */
12
13#include <linux/input.h>
14#include <linux/of_gpio.h>
Asish Bhattacharya84f7f732017-07-25 16:29:27 +0530[diff] [blame]15#include <linux/module.h>
16#include <linux/platform_device.h>
17#include <linux/of_device.h>
Asish Bhattacharya8e2277f2017-07-20 18:31:55 +0530[diff] [blame]18#include <sound/pcm_params.h>
Laxminath Kasam605b42f2017-08-01 22:02:15 +0530[diff] [blame]19#include <dsp/q6afe-v2.h>
Meng Wangc444ff72017-10-18 10:52:07 +0800[diff] [blame]20#include <dsp/audio_notifier.h>
Laxminath Kasam605b42f2017-08-01 22:02:15 +0530[diff] [blame]21#include "msm-pcm-routing-v2.h"
Asish Bhattacharya8e2277f2017-07-20 18:31:55 +0530[diff] [blame]22#include "sdm660-common.h"
23#include "sdm660-internal.h"
24#include "sdm660-external.h"
Laxminath Kasam605b42f2017-08-01 22:02:15 +0530[diff] [blame]25#include "codecs/msm-cdc-pinctrl.h"
26#include "codecs/sdm660_cdc/msm-analog-cdc.h"
27#include "codecs/wsa881x.h"
Asish Bhattacharya8e2277f2017-07-20 18:31:55 +0530[diff] [blame]28
Revathi Uddaraju30feb0d2017-11-21 15:30:19 +0530[diff] [blame]29#define __CHIPSET__ "SDM660 "
30#define MSM_DAILINK_NAME(name) (__CHIPSET__#name)
31
Asish Bhattacharya8e2277f2017-07-20 18:31:55 +0530[diff] [blame]32#define DRV_NAME "sdm660-asoc-snd"
33
34#define MSM_INT_DIGITAL_CODEC "msm-dig-codec"
35#define PMIC_INT_ANALOG_CODEC "analog-codec"
36
37#define DEV_NAME_STR_LEN 32
38#define DEFAULT_MCLK_RATE 9600000
Revathi Uddaraju30feb0d2017-11-21 15:30:19 +0530[diff] [blame]39#define MSM_LL_QOS_VALUE 300 /* time in us to ensure LPM doesn't go in C3/C4 */
Asish Bhattacharya8e2277f2017-07-20 18:31:55 +0530[diff] [blame]40
Asish Bhattacharya8e2277f2017-07-20 18:31:55 +0530[diff] [blame]41enum {
42 DP_RX_IDX,
43 EXT_DISP_RX_IDX_MAX,
44};
45
Laxminath Kasam38070be2017-08-17 18:21:59 +0530[diff] [blame]46bool codec_reg_done;
47
Soumya Managolibbeb8ee2019-03-18 17:05:29 +0530[diff] [blame]48struct tdm_dai_data {
49 DECLARE_BITMAP(status_mask, 3);
50 u32 rate;
51 u32 channels;
52 u32 bitwidth;
53 u32 num_group_ports;
54 struct afe_clk_set clk_set; /* hold LPASS clock config. */
55 union afe_port_group_config group_cfg; /* hold tdm group config */
56 struct afe_tdm_port_config port_cfg; /* hold tdm config */
57};
58
59
Asish Bhattacharya8e2277f2017-07-20 18:31:55 +0530[diff] [blame]60/* TDM default config */
61static struct dev_config tdm_rx_cfg[TDM_INTERFACE_MAX][TDM_PORT_MAX] = {
62 { /* PRI TDM */
63 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_0 */
64 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_1 */
65 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_2 */
66 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_3 */
67 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_4 */
68 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_5 */
69 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_6 */
70 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_7 */
71 },
72 { /* SEC TDM */
73 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_0 */
74 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_1 */
75 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_2 */
76 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_3 */
77 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_4 */
78 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_5 */
79 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_6 */
80 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_7 */
81 },
82 { /* TERT TDM */
83 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_0 */
84 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_1 */
85 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_2 */
86 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_3 */
87 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_4 */
88 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_5 */
89 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_6 */
90 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_7 */
91 },
92 { /* QUAT TDM */
93 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_0 */
94 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_1 */
95 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_2 */
96 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_3 */
97 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_4 */
98 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_5 */
99 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_6 */
100 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_7 */
Rohit Kumard1754482017-09-10 22:57:39 +0530[diff] [blame]101 },
102 { /* QUIN TDM */
103 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_0 */
104 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_1 */
105 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_2 */
106 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_3 */
107 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_4 */
108 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_5 */
109 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_6 */
110 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_7 */
Asish Bhattacharya8e2277f2017-07-20 18:31:55 +0530[diff] [blame]111 }
112};
113
114/* TDM default config */
115static struct dev_config tdm_tx_cfg[TDM_INTERFACE_MAX][TDM_PORT_MAX] = {
116 { /* PRI TDM */
117 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_0 */
118 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_1 */
119 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_2 */
120 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_3 */
121 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_4 */
122 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_5 */
123 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_6 */
124 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_7 */
125 },
126 { /* SEC TDM */
127 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_0 */
128 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_1 */
129 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_2 */
130 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_3 */
131 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_4 */
132 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_5 */
133 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_6 */
134 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_7 */
135 },
136 { /* TERT TDM */
137 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_0 */
138 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_1 */
139 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_2 */
140 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_3 */
141 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_4 */
142 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_5 */
143 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_6 */
144 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_7 */
145 },
146 { /* QUAT TDM */
147 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_0 */
148 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_1 */
149 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_2 */
150 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_3 */
151 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_4 */
152 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_5 */
153 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_6 */
154 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_7 */
Rohit Kumard1754482017-09-10 22:57:39 +0530[diff] [blame]155 },
156 { /* QUIN TDM */
157 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_0 */
158 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_1 */
159 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_2 */
160 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_3 */
161 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_4 */
162 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_5 */
163 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_6 */
164 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_7 */
Asish Bhattacharya8e2277f2017-07-20 18:31:55 +0530[diff] [blame]165 }
166};
167
168/* Default configuration of external display BE */
169static struct dev_config ext_disp_rx_cfg[] = {
170 [DP_RX_IDX] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
171};
172static struct dev_config usb_rx_cfg = {
173 .sample_rate = SAMPLING_RATE_48KHZ,
174 .bit_format = SNDRV_PCM_FORMAT_S16_LE,
175 .channels = 2,
176};
177
178static struct dev_config usb_tx_cfg = {
179 .sample_rate = SAMPLING_RATE_48KHZ,
180 .bit_format = SNDRV_PCM_FORMAT_S16_LE,
181 .channels = 1,
182};
183
184enum {
Asish Bhattacharya8e2277f2017-07-20 18:31:55 +0530[diff] [blame]185 PRIM_AUX_PCM = 0,
186 SEC_AUX_PCM,
187 TERT_AUX_PCM,
188 QUAT_AUX_PCM,
Rohit Kumard1754482017-09-10 22:57:39 +0530[diff] [blame]189 QUIN_AUX_PCM,
Asish Bhattacharya8e2277f2017-07-20 18:31:55 +0530[diff] [blame]190 AUX_PCM_MAX,
191};
192
193enum {
194 PCM_I2S_SEL_PRIM = 0,
195 PCM_I2S_SEL_SEC,
196 PCM_I2S_SEL_TERT,
197 PCM_I2S_SEL_QUAT,
Rohit Kumard1754482017-09-10 22:57:39 +0530[diff] [blame]198 PCM_I2S_SEL_QUIN,
Asish Bhattacharya8e2277f2017-07-20 18:31:55 +0530[diff] [blame]199 PCM_I2S_SEL_MAX,
200};
201
202struct mi2s_conf {
203 struct mutex lock;
204 u32 ref_cnt;
205 u32 msm_is_mi2s_master;
206 u32 msm_is_ext_mclk;
207};
208
209static u32 mi2s_ebit_clk[MI2S_MAX] = {
210 Q6AFE_LPASS_CLK_ID_PRI_MI2S_EBIT,
211 Q6AFE_LPASS_CLK_ID_SEC_MI2S_EBIT,
212 Q6AFE_LPASS_CLK_ID_TER_MI2S_EBIT,
Rohit Kumar804f26b2017-10-02 10:35:21 +0530[diff] [blame]213 Q6AFE_LPASS_CLK_ID_QUAD_MI2S_EBIT,
214 Q6AFE_LPASS_CLK_ID_QUI_MI2S_EBIT
Asish Bhattacharya8e2277f2017-07-20 18:31:55 +0530[diff] [blame]215};
216
217struct msm_wsa881x_dev_info {
218 struct device_node *of_node;
219 u32 index;
220};
221static struct snd_soc_aux_dev *msm_aux_dev;
222static struct snd_soc_codec_conf *msm_codec_conf;
223
Asish Bhattacharya84f7f732017-07-25 16:29:27 +0530[diff] [blame]224static bool msm_swap_gnd_mic(struct snd_soc_codec *codec, bool active);
Asish Bhattacharya8e2277f2017-07-20 18:31:55 +0530[diff] [blame]225
226static struct wcd_mbhc_config mbhc_cfg = {
227 .read_fw_bin = false,
228 .calibration = NULL,
229 .detect_extn_cable = true,
230 .mono_stero_detection = false,
231 .swap_gnd_mic = NULL,
232 .hs_ext_micbias = true,
233 .key_code[0] = KEY_MEDIA,
234 .key_code[1] = KEY_VOICECOMMAND,
235 .key_code[2] = KEY_VOLUMEUP,
236 .key_code[3] = KEY_VOLUMEDOWN,
237 .key_code[4] = 0,
238 .key_code[5] = 0,
239 .key_code[6] = 0,
240 .key_code[7] = 0,
241 .linein_th = 5000,
242 .moisture_en = false,
243 .mbhc_micbias = 0,
244 .anc_micbias = 0,
245 .enable_anc_mic_detect = false,
246};
247
248static struct dev_config proxy_rx_cfg = {
249 .sample_rate = SAMPLING_RATE_48KHZ,
250 .bit_format = SNDRV_PCM_FORMAT_S16_LE,
251 .channels = 2,
252};
253
254/* Default configuration of MI2S channels */
255static struct dev_config mi2s_rx_cfg[] = {
256 [PRIM_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
257 [SEC_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
258 [TERT_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
259 [QUAT_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
Rohit Kumard1754482017-09-10 22:57:39 +0530[diff] [blame]260 [QUIN_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
Asish Bhattacharya8e2277f2017-07-20 18:31:55 +0530[diff] [blame]261};
262
263static struct dev_config mi2s_tx_cfg[] = {
264 [PRIM_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
265 [SEC_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
266 [TERT_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
267 [QUAT_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
Rohit Kumard1754482017-09-10 22:57:39 +0530[diff] [blame]268 [QUIN_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
Asish Bhattacharya8e2277f2017-07-20 18:31:55 +0530[diff] [blame]269};
270
271static struct dev_config aux_pcm_rx_cfg[] = {
272 [PRIM_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
273 [SEC_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
274 [TERT_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
275 [QUAT_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
Rohit Kumard1754482017-09-10 22:57:39 +0530[diff] [blame]276 [QUIN_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
Asish Bhattacharya8e2277f2017-07-20 18:31:55 +0530[diff] [blame]277};
278
279static struct dev_config aux_pcm_tx_cfg[] = {
280 [PRIM_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
281 [SEC_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
282 [TERT_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
283 [QUAT_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
Rohit Kumard1754482017-09-10 22:57:39 +0530[diff] [blame]284 [QUIN_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
Asish Bhattacharya8e2277f2017-07-20 18:31:55 +0530[diff] [blame]285};
286
287static char const *ch_text[] = {"Two", "Three", "Four", "Five",
288 "Six", "Seven", "Eight"};
289static const char *const auxpcm_rate_text[] = {"KHZ_8", "KHZ_16"};
290static char const *mi2s_rate_text[] = {"KHZ_8", "KHZ_16",
291 "KHZ_32", "KHZ_44P1", "KHZ_48",
292 "KHZ_96", "KHZ_192"};
293static const char *const mi2s_ch_text[] = {"One", "Two", "Three", "Four",
294 "Five", "Six", "Seven",
295 "Eight"};
296static char const *bit_format_text[] = {"S16_LE", "S24_LE", "S24_3LE",
297 "S32_LE"};
298static char const *mi2s_format_text[] = {"S16_LE", "S24_LE", "S24_3LE",
299 "S32_LE"};
300static char const *tdm_ch_text[] = {"One", "Two", "Three", "Four",
Dhanalakshmi Siddanid70a4f72019-11-27 15:35:41 +0530[diff] [blame]301 "Five", "Six", "Seven", "Eight",
302 "Nine", "Ten", "Eleven", "Twelve",
303 "Thirteen", "Fourteen", "Fifteen",
304 "Sixteen"};
Asish Bhattacharya8e2277f2017-07-20 18:31:55 +0530[diff] [blame]305static char const *tdm_bit_format_text[] = {"S16_LE", "S24_LE", "S32_LE"};
306static char const *tdm_sample_rate_text[] = {"KHZ_8", "KHZ_16", "KHZ_32",
307 "KHZ_44P1", "KHZ_48", "KHZ_96",
308 "KHZ_192", "KHZ_352P8", "KHZ_384"};
Dhanalakshmi Siddanid70a4f72019-11-27 15:35:41 +0530[diff] [blame]309static const char *const tdm_slot_num_text[] = {"One", "Two", "Four",
310 "Eight", "Sixteen", "ThirtyTwo"};
311static const char *const tdm_slot_width_text[] = {"16", "24", "32"};
Asish Bhattacharya8e2277f2017-07-20 18:31:55 +0530[diff] [blame]312static const char *const usb_ch_text[] = {"One", "Two", "Three", "Four",
313 "Five", "Six", "Seven",
314 "Eight"};
315static char const *usb_sample_rate_text[] = {"KHZ_8", "KHZ_11P025",
316 "KHZ_16", "KHZ_22P05",
317 "KHZ_32", "KHZ_44P1", "KHZ_48",
318 "KHZ_96", "KHZ_192", "KHZ_384"};
319static char const *ext_disp_bit_format_text[] = {"S16_LE", "S24_LE"};
320static char const *ext_disp_sample_rate_text[] = {"KHZ_48", "KHZ_96",
321 "KHZ_192"};
Revathi Uddaraju30feb0d2017-11-21 15:30:19 +0530[diff] [blame]322static const char *const qos_text[] = {"Disable", "Enable"};
Asish Bhattacharya8e2277f2017-07-20 18:31:55 +0530[diff] [blame]323
324static SOC_ENUM_SINGLE_EXT_DECL(ext_disp_rx_chs, ch_text);
325static SOC_ENUM_SINGLE_EXT_DECL(proxy_rx_chs, ch_text);
326static SOC_ENUM_SINGLE_EXT_DECL(prim_aux_pcm_rx_sample_rate, auxpcm_rate_text);
327static SOC_ENUM_SINGLE_EXT_DECL(sec_aux_pcm_rx_sample_rate, auxpcm_rate_text);
328static SOC_ENUM_SINGLE_EXT_DECL(tert_aux_pcm_rx_sample_rate, auxpcm_rate_text);
329static SOC_ENUM_SINGLE_EXT_DECL(quat_aux_pcm_rx_sample_rate, auxpcm_rate_text);
Rohit Kumard1754482017-09-10 22:57:39 +0530[diff] [blame]330static SOC_ENUM_SINGLE_EXT_DECL(quin_aux_pcm_rx_sample_rate, auxpcm_rate_text);
Asish Bhattacharya8e2277f2017-07-20 18:31:55 +0530[diff] [blame]331static SOC_ENUM_SINGLE_EXT_DECL(prim_aux_pcm_tx_sample_rate, auxpcm_rate_text);
332static SOC_ENUM_SINGLE_EXT_DECL(sec_aux_pcm_tx_sample_rate, auxpcm_rate_text);
333static SOC_ENUM_SINGLE_EXT_DECL(tert_aux_pcm_tx_sample_rate, auxpcm_rate_text);
334static SOC_ENUM_SINGLE_EXT_DECL(quat_aux_pcm_tx_sample_rate, auxpcm_rate_text);
Rohit Kumard1754482017-09-10 22:57:39 +0530[diff] [blame]335static SOC_ENUM_SINGLE_EXT_DECL(quin_aux_pcm_tx_sample_rate, auxpcm_rate_text);
Asish Bhattacharya8e2277f2017-07-20 18:31:55 +0530[diff] [blame]336static SOC_ENUM_SINGLE_EXT_DECL(prim_mi2s_rx_sample_rate, mi2s_rate_text);
337static SOC_ENUM_SINGLE_EXT_DECL(sec_mi2s_rx_sample_rate, mi2s_rate_text);
338static SOC_ENUM_SINGLE_EXT_DECL(tert_mi2s_rx_sample_rate, mi2s_rate_text);
339static SOC_ENUM_SINGLE_EXT_DECL(quat_mi2s_rx_sample_rate, mi2s_rate_text);
Rohit Kumard1754482017-09-10 22:57:39 +0530[diff] [blame]340static SOC_ENUM_SINGLE_EXT_DECL(quin_mi2s_rx_sample_rate, mi2s_rate_text);
Asish Bhattacharya8e2277f2017-07-20 18:31:55 +0530[diff] [blame]341static SOC_ENUM_SINGLE_EXT_DECL(prim_mi2s_tx_sample_rate, mi2s_rate_text);
342static SOC_ENUM_SINGLE_EXT_DECL(sec_mi2s_tx_sample_rate, mi2s_rate_text);
343static SOC_ENUM_SINGLE_EXT_DECL(tert_mi2s_tx_sample_rate, mi2s_rate_text);
344static SOC_ENUM_SINGLE_EXT_DECL(quat_mi2s_tx_sample_rate, mi2s_rate_text);
Rohit Kumard1754482017-09-10 22:57:39 +0530[diff] [blame]345static SOC_ENUM_SINGLE_EXT_DECL(quin_mi2s_tx_sample_rate, mi2s_rate_text);
Asish Bhattacharya8e2277f2017-07-20 18:31:55 +0530[diff] [blame]346static SOC_ENUM_SINGLE_EXT_DECL(prim_mi2s_rx_format, mi2s_format_text);
347static SOC_ENUM_SINGLE_EXT_DECL(sec_mi2s_rx_format, mi2s_format_text);
348static SOC_ENUM_SINGLE_EXT_DECL(tert_mi2s_rx_format, mi2s_format_text);
349static SOC_ENUM_SINGLE_EXT_DECL(quat_mi2s_rx_format, mi2s_format_text);
Rohit Kumard1754482017-09-10 22:57:39 +0530[diff] [blame]350static SOC_ENUM_SINGLE_EXT_DECL(quin_mi2s_rx_format, mi2s_format_text);
Asish Bhattacharya8e2277f2017-07-20 18:31:55 +0530[diff] [blame]351static SOC_ENUM_SINGLE_EXT_DECL(prim_mi2s_tx_format, mi2s_format_text);
352static SOC_ENUM_SINGLE_EXT_DECL(sec_mi2s_tx_format, mi2s_format_text);
353static SOC_ENUM_SINGLE_EXT_DECL(tert_mi2s_tx_format, mi2s_format_text);
354static SOC_ENUM_SINGLE_EXT_DECL(quat_mi2s_tx_format, mi2s_format_text);
Rohit Kumard1754482017-09-10 22:57:39 +0530[diff] [blame]355static SOC_ENUM_SINGLE_EXT_DECL(quin_mi2s_tx_format, mi2s_format_text);
Asish Bhattacharya8e2277f2017-07-20 18:31:55 +0530[diff] [blame]356static SOC_ENUM_SINGLE_EXT_DECL(prim_mi2s_rx_chs, mi2s_ch_text);
357static SOC_ENUM_SINGLE_EXT_DECL(prim_mi2s_tx_chs, mi2s_ch_text);
358static SOC_ENUM_SINGLE_EXT_DECL(sec_mi2s_rx_chs, mi2s_ch_text);
359static SOC_ENUM_SINGLE_EXT_DECL(sec_mi2s_tx_chs, mi2s_ch_text);
360static SOC_ENUM_SINGLE_EXT_DECL(tert_mi2s_rx_chs, mi2s_ch_text);
361static SOC_ENUM_SINGLE_EXT_DECL(tert_mi2s_tx_chs, mi2s_ch_text);
362static SOC_ENUM_SINGLE_EXT_DECL(quat_mi2s_rx_chs, mi2s_ch_text);
363static SOC_ENUM_SINGLE_EXT_DECL(quat_mi2s_tx_chs, mi2s_ch_text);
Rohit Kumard1754482017-09-10 22:57:39 +0530[diff] [blame]364static SOC_ENUM_SINGLE_EXT_DECL(quin_mi2s_rx_chs, mi2s_ch_text);
365static SOC_ENUM_SINGLE_EXT_DECL(quin_mi2s_tx_chs, mi2s_ch_text);
Asish Bhattacharya8e2277f2017-07-20 18:31:55 +0530[diff] [blame]366static SOC_ENUM_SINGLE_EXT_DECL(usb_rx_chs, usb_ch_text);
367static SOC_ENUM_SINGLE_EXT_DECL(usb_tx_chs, usb_ch_text);
368static SOC_ENUM_SINGLE_EXT_DECL(usb_rx_format, bit_format_text);
369static SOC_ENUM_SINGLE_EXT_DECL(usb_tx_format, bit_format_text);
370static SOC_ENUM_SINGLE_EXT_DECL(ext_disp_rx_format, ext_disp_bit_format_text);
371static SOC_ENUM_SINGLE_EXT_DECL(usb_rx_sample_rate, usb_sample_rate_text);
372static SOC_ENUM_SINGLE_EXT_DECL(usb_tx_sample_rate, usb_sample_rate_text);
373static SOC_ENUM_SINGLE_EXT_DECL(ext_disp_rx_sample_rate,
374 ext_disp_sample_rate_text);
375static SOC_ENUM_SINGLE_EXT_DECL(tdm_tx_chs, tdm_ch_text);
376static SOC_ENUM_SINGLE_EXT_DECL(tdm_tx_format, tdm_bit_format_text);
377static SOC_ENUM_SINGLE_EXT_DECL(tdm_tx_sample_rate, tdm_sample_rate_text);
378static SOC_ENUM_SINGLE_EXT_DECL(tdm_rx_chs, tdm_ch_text);
379static SOC_ENUM_SINGLE_EXT_DECL(tdm_rx_format, tdm_bit_format_text);
380static SOC_ENUM_SINGLE_EXT_DECL(tdm_rx_sample_rate, tdm_sample_rate_text);
Dhanalakshmi Siddanid70a4f72019-11-27 15:35:41 +0530[diff] [blame]381static SOC_ENUM_SINGLE_EXT_DECL(tdm_slot_num, tdm_slot_num_text);
382static SOC_ENUM_SINGLE_EXT_DECL(tdm_slot_width, tdm_slot_width_text);
Revathi Uddaraju30feb0d2017-11-21 15:30:19 +0530[diff] [blame]383static SOC_ENUM_SINGLE_EXT_DECL(qos_vote, qos_text);
384
385static int qos_vote_status;
Asish Bhattacharya8e2277f2017-07-20 18:31:55 +0530[diff] [blame]386
387static struct afe_clk_set mi2s_clk[MI2S_MAX] = {
388 {
389 AFE_API_VERSION_I2S_CONFIG,
390 Q6AFE_LPASS_CLK_ID_PRI_MI2S_IBIT,
391 Q6AFE_LPASS_IBIT_CLK_1_P536_MHZ,
392 Q6AFE_LPASS_CLK_ATTRIBUTE_COUPLE_NO,
393 Q6AFE_LPASS_CLK_ROOT_DEFAULT,
394 0,
395 },
396 {
397 AFE_API_VERSION_I2S_CONFIG,
398 Q6AFE_LPASS_CLK_ID_SEC_MI2S_IBIT,
399 Q6AFE_LPASS_IBIT_CLK_1_P536_MHZ,
400 Q6AFE_LPASS_CLK_ATTRIBUTE_COUPLE_NO,
401 Q6AFE_LPASS_CLK_ROOT_DEFAULT,
402 0,
403 },
404 {
405 AFE_API_VERSION_I2S_CONFIG,
406 Q6AFE_LPASS_CLK_ID_TER_MI2S_IBIT,
407 Q6AFE_LPASS_IBIT_CLK_1_P536_MHZ,
408 Q6AFE_LPASS_CLK_ATTRIBUTE_COUPLE_NO,
409 Q6AFE_LPASS_CLK_ROOT_DEFAULT,
410 0,
411 },
412 {
413 AFE_API_VERSION_I2S_CONFIG,
414 Q6AFE_LPASS_CLK_ID_QUAD_MI2S_IBIT,
415 Q6AFE_LPASS_IBIT_CLK_1_P536_MHZ,
416 Q6AFE_LPASS_CLK_ATTRIBUTE_COUPLE_NO,
417 Q6AFE_LPASS_CLK_ROOT_DEFAULT,
418 0,
Rohit Kumar804f26b2017-10-02 10:35:21 +0530[diff] [blame]419 },
420 {
421 AFE_API_VERSION_I2S_CONFIG,
422 Q6AFE_LPASS_CLK_ID_QUI_MI2S_IBIT,
423 Q6AFE_LPASS_IBIT_CLK_1_P536_MHZ,
424 Q6AFE_LPASS_CLK_ATTRIBUTE_COUPLE_NO,
425 Q6AFE_LPASS_CLK_ROOT_DEFAULT,
426 0,
Asish Bhattacharya8e2277f2017-07-20 18:31:55 +0530[diff] [blame]427 }
428};
429
430static struct afe_clk_set mi2s_mclk[MI2S_MAX] = {
431 {
432 AFE_API_VERSION_I2S_CONFIG,
433 Q6AFE_LPASS_CLK_ID_MCLK_3,
434 Q6AFE_LPASS_OSR_CLK_9_P600_MHZ,
435 Q6AFE_LPASS_CLK_ATTRIBUTE_COUPLE_NO,
436 Q6AFE_LPASS_CLK_ROOT_DEFAULT,
437 0,
438 },
439 {
440 AFE_API_VERSION_I2S_CONFIG,
Rohit Kumar804f26b2017-10-02 10:35:21 +0530[diff] [blame]441 Q6AFE_LPASS_CLK_ID_MCLK_2,
Asish Bhattacharya8e2277f2017-07-20 18:31:55 +0530[diff] [blame]442 Q6AFE_LPASS_OSR_CLK_9_P600_MHZ,
443 Q6AFE_LPASS_CLK_ATTRIBUTE_COUPLE_NO,
444 Q6AFE_LPASS_CLK_ROOT_DEFAULT,
445 0,
446 },
447 {
448 AFE_API_VERSION_I2S_CONFIG,
449 Q6AFE_LPASS_CLK_ID_MCLK_1,
450 Q6AFE_LPASS_OSR_CLK_9_P600_MHZ,
451 Q6AFE_LPASS_CLK_ATTRIBUTE_COUPLE_NO,
452 Q6AFE_LPASS_CLK_ROOT_DEFAULT,
453 0,
454 },
455 {
456 AFE_API_VERSION_I2S_CONFIG,
Rohit Kumar804f26b2017-10-02 10:35:21 +0530[diff] [blame]457 Q6AFE_LPASS_CLK_ID_MCLK_1,
458 Q6AFE_LPASS_OSR_CLK_9_P600_MHZ,
459 Q6AFE_LPASS_CLK_ATTRIBUTE_COUPLE_NO,
460 Q6AFE_LPASS_CLK_ROOT_DEFAULT,
461 0,
462 },
463 {
464 AFE_API_VERSION_I2S_CONFIG,
465 Q6AFE_LPASS_CLK_ID_QUI_MI2S_OSR,
Asish Bhattacharya8e2277f2017-07-20 18:31:55 +0530[diff] [blame]466 Q6AFE_LPASS_OSR_CLK_9_P600_MHZ,
467 Q6AFE_LPASS_CLK_ATTRIBUTE_COUPLE_NO,
468 Q6AFE_LPASS_CLK_ROOT_DEFAULT,
469 0,
470 }
471};
472
473static struct mi2s_conf mi2s_intf_conf[MI2S_MAX];
474
Dhanalakshmi Siddanid70a4f72019-11-27 15:35:41 +0530[diff] [blame]475/* TDM default slot config */
476struct tdm_slot_cfg {
477 u32 width;
478 u32 num;
479};
480
481static struct tdm_slot_cfg tdm_slot[TDM_INTERFACE_MAX] = {
482 /* PRI TDM */
483 {32, 8},
484 /* SEC TDM */
485 {32, 8},
486 /* TERT TDM */
487 {32, 8},
488 /* QUAT TDM */
489 {32, 8},
490 /* QUIN TDM */
491 {32, 8}
492};
493
494static unsigned int tdm_rx_slot_offset
495 [TDM_INTERFACE_MAX][TDM_PORT_MAX][TDM_SLOT_OFFSET_MAX] = {
496 {/* PRI TDM */
497 {0, 4, 8, 12, 16, 20, 24, 28,
498 32, 36, 40, 44, 48, 52, 56, 60, 0xFFFF},
499 {0xFFFF}, /* not used */
500 {0xFFFF}, /* not used */
501 {0xFFFF}, /* not used */
502 {0xFFFF}, /* not used */
503 {0xFFFF}, /* not used */
504 {0xFFFF}, /* not used */
505 {0xFFFF}, /* not used */
506 },
507 {/* SEC TDM */
508 {0, 4, 8, 12, 16, 20, 24, 28,
509 32, 36, 40, 44, 48, 52, 56, 60, 0xFFFF},
510 {0xFFFF}, /* not used */
511 {0xFFFF}, /* not used */
512 {0xFFFF}, /* not used */
513 {0xFFFF}, /* not used */
514 {0xFFFF}, /* not used */
515 {0xFFFF}, /* not used */
516 {0xFFFF}, /* not used */
517 },
518 {/* TERT TDM */
519 {0, 4, 8, 12, 16, 20, 24, 28,
520 32, 36, 40, 44, 48, 52, 56, 60, 0xFFFF},
521 {0xFFFF}, /* not used */
522 {0xFFFF}, /* not used */
523 {0xFFFF}, /* not used */
524 {0xFFFF}, /* not used */
525 {0xFFFF}, /* not used */
526 {0xFFFF}, /* not used */
527 {0xFFFF}, /* not used */
528 },
529 {/* QUAT TDM */
530 {0, 4, 8, 12, 16, 20, 24, 28,
531 32, 36, 40, 44, 48, 52, 56, 60, 0xFFFF},
532 {0xFFFF}, /* not used */
533 {0xFFFF}, /* not used */
534 {0xFFFF}, /* not used */
535 {0xFFFF}, /* not used */
536 {0xFFFF}, /* not used */
537 {0xFFFF}, /* not used */
538 },
539 {/* QUIN TDM */
540 {0, 4, 8, 12, 16, 20, 24, 28,
541 32, 36, 40, 44, 48, 52, 56, 60, 0xFFFF},
542 {0xFFFF}, /* not used */
543 {0xFFFF}, /* not used */
544 {0xFFFF}, /* not used */
545 {0xFFFF}, /* not used */
546 {0xFFFF}, /* not used */
547 {0xFFFF}, /* not used */
548 }
549};
550
551static unsigned int tdm_tx_slot_offset
552 [TDM_INTERFACE_MAX][TDM_PORT_MAX][TDM_SLOT_OFFSET_MAX] = {
553 {/* PRI TDM */
554 {0, 4, 8, 12, 16, 20, 24, 28,
555 32, 36, 40, 44, 48, 52, 56, 60, 0xFFFF},
556 {0xFFFF}, /* not used */
557 {0xFFFF}, /* not used */
558 {0xFFFF}, /* not used */
559 {0xFFFF}, /* not used */
560 {0xFFFF}, /* not used */
561 {0xFFFF}, /* not used */
562 {0xFFFF}, /* not used */
563 },
564 {/* SEC TDM */
565 {0, 4, 8, 12, 16, 20, 24, 28,
566 32, 36, 40, 44, 48, 52, 56, 60, 0xFFFF},
567 {0xFFFF}, /* not used */
568 {0xFFFF}, /* not used */
569 {0xFFFF}, /* not used */
570 {0xFFFF}, /* not used */
571 {0xFFFF}, /* not used */
572 {0xFFFF}, /* not used */
573 {0xFFFF}, /* not used */
574 },
575 {/* TERT TDM */
576 {0, 4, 8, 12, 16, 20, 24, 28,
577 32, 36, 40, 44, 48, 52, 56, 60, 0xFFFF},
578 {0xFFFF}, /* not used */
579 {0xFFFF}, /* not used */
580 {0xFFFF}, /* not used */
581 {0xFFFF}, /* not used */
582 {0xFFFF}, /* not used */
583 {0xFFFF}, /* not used */
584 {0xFFFF}, /* not used */
585 },
586 {/* QUAT TDM */
587 {0, 4, 8, 12, 16, 20, 24, 28,
588 32, 36, 40, 44, 48, 52, 56, 60, 0xFFFF},/*MIC ARR*/
589 {0xFFFF}, /* not used */
590 {0xFFFF}, /* not used */
591 {0xFFFF}, /* not used */
592 {0xFFFF}, /* not used */
593 {0xFFFF}, /* not used */
594 {0xFFFF}, /* not used */
595 {0xFFFF}, /* not used */
596 },
597 {/* QUIN TDM */
598 {0, 4, 8, 12, 16, 20, 24, 28,
599 32, 36, 40, 44, 48, 52, 56, 60, 0xFFFF},
600 {0xFFFF}, /* not used */
601 {0xFFFF}, /* not used */
602 {0xFFFF}, /* not used */
603 {0xFFFF}, /* not used */
604 {0xFFFF}, /* not used */
605 {0xFFFF}, /* not used */
606 }
607};
608static unsigned int tdm_param_set_slot_mask(int slots)
609{
610 unsigned int slot_mask = 0;
611 int i = 0;
612
613 if ((slots <= 0) || (slots > 32)) {
614 pr_err("%s: invalid slot number %d\n", __func__, slots);
615 return -EINVAL;
616 }
617
618 for (i = 0; i < slots ; i++)
619 slot_mask |= 1 << i;
620
621 return slot_mask;
622}
623
624int msm_tdm_snd_hw_params(struct snd_pcm_substream *substream,
625 struct snd_pcm_hw_params *params)
626{
627 struct snd_soc_pcm_runtime *rtd = substream->private_data;
628 struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
629 int ret = 0;
630 int channels, slot_width, slots, rate, format;
631 unsigned int slot_mask;
632 unsigned int *slot_offset;
633 int offset_channels = 0;
634 int i;
635 int clk_freq;
636
637 pr_debug("%s: dai id = 0x%x\n", __func__, cpu_dai->id);
638
639 channels = params_channels(params);
640 if (channels < 1 || channels > 32) {
641 pr_err("%s: invalid param channels %d\n",
642 __func__, channels);
643 return -EINVAL;
644 }
645
646 format = params_format(params);
647 if (format != SNDRV_PCM_FORMAT_S32_LE &&
648 format != SNDRV_PCM_FORMAT_S24_LE &&
649 format != SNDRV_PCM_FORMAT_S16_LE) {
650 /*
651 * up to 8 channels HW config should
652 * use 32 bit slot width for max support of
653 * stream bit width. (slot_width > bit_width)
654 */
655 pr_err("%s: invalid param format 0x%x\n",
656 __func__, format);
657 return -EINVAL;
658 }
659
660 switch (cpu_dai->id) {
661 case AFE_PORT_ID_PRIMARY_TDM_RX:
662 slots = tdm_slot[TDM_PRI].num;
663 slot_width = tdm_slot[TDM_PRI].width;
664 slot_offset = tdm_rx_slot_offset[TDM_PRI][TDM_0];
665 break;
666 case AFE_PORT_ID_PRIMARY_TDM_RX_1:
667 slots = tdm_slot[TDM_PRI].num;
668 slot_width = tdm_slot[TDM_PRI].width;
669 slot_offset = tdm_rx_slot_offset[TDM_PRI][TDM_1];
670 break;
671 case AFE_PORT_ID_PRIMARY_TDM_RX_2:
672 slots = tdm_slot[TDM_PRI].num;
673 slot_width = tdm_slot[TDM_PRI].width;
674 slot_offset = tdm_rx_slot_offset[TDM_PRI][TDM_2];
675 break;
676 case AFE_PORT_ID_PRIMARY_TDM_RX_3:
677 slots = tdm_slot[TDM_PRI].num;
678 slot_width = tdm_slot[TDM_PRI].width;
679 slot_offset = tdm_rx_slot_offset[TDM_PRI][TDM_3];
680 break;
681 case AFE_PORT_ID_PRIMARY_TDM_RX_4:
682 slots = tdm_slot[TDM_PRI].num;
683 slot_width = tdm_slot[TDM_PRI].width;
684 slot_offset = tdm_rx_slot_offset[TDM_PRI][TDM_4];
685 break;
686 case AFE_PORT_ID_PRIMARY_TDM_RX_5:
687 slots = tdm_slot[TDM_PRI].num;
688 slot_width = tdm_slot[TDM_PRI].width;
689 slot_offset = tdm_rx_slot_offset[TDM_PRI][TDM_5];
690 break;
691 case AFE_PORT_ID_PRIMARY_TDM_RX_6:
692 slots = tdm_slot[TDM_PRI].num;
693 slot_width = tdm_slot[TDM_PRI].width;
694 slot_offset = tdm_rx_slot_offset[TDM_PRI][TDM_6];
695 break;
696 case AFE_PORT_ID_PRIMARY_TDM_RX_7:
697 slots = tdm_slot[TDM_PRI].num;
698 slot_width = tdm_slot[TDM_PRI].width;
699 slot_offset = tdm_rx_slot_offset[TDM_PRI][TDM_7];
700 break;
701 case AFE_PORT_ID_PRIMARY_TDM_TX:
702 slots = tdm_slot[TDM_PRI].num;
703 slot_width = tdm_slot[TDM_PRI].width;
704 slot_offset = tdm_tx_slot_offset[TDM_PRI][TDM_0];
705 break;
706 case AFE_PORT_ID_PRIMARY_TDM_TX_1:
707 slots = tdm_slot[TDM_PRI].num;
708 slot_width = tdm_slot[TDM_PRI].width;
709 slot_offset = tdm_tx_slot_offset[TDM_PRI][TDM_1];
710 break;
711 case AFE_PORT_ID_PRIMARY_TDM_TX_2:
712 slots = tdm_slot[TDM_PRI].num;
713 slot_width = tdm_slot[TDM_PRI].width;
714 slot_offset = tdm_tx_slot_offset[TDM_PRI][TDM_2];
715 break;
716 case AFE_PORT_ID_PRIMARY_TDM_TX_3:
717 slots = tdm_slot[TDM_PRI].num;
718 slot_width = tdm_slot[TDM_PRI].width;
719 slot_offset = tdm_tx_slot_offset[TDM_PRI][TDM_3];
720 break;
721 case AFE_PORT_ID_PRIMARY_TDM_TX_4:
722 slots = tdm_slot[TDM_PRI].num;
723 slot_width = tdm_slot[TDM_PRI].width;
724 slot_offset = tdm_tx_slot_offset[TDM_PRI][TDM_4];
725 break;
726 case AFE_PORT_ID_PRIMARY_TDM_TX_5:
727 slots = tdm_slot[TDM_PRI].num;
728 slot_width = tdm_slot[TDM_PRI].width;
729 slot_offset = tdm_tx_slot_offset[TDM_PRI][TDM_5];
730 break;
731 case AFE_PORT_ID_PRIMARY_TDM_TX_6:
732 slots = tdm_slot[TDM_PRI].num;
733 slot_width = tdm_slot[TDM_PRI].width;
734 slot_offset = tdm_tx_slot_offset[TDM_PRI][TDM_6];
735 break;
736 case AFE_PORT_ID_PRIMARY_TDM_TX_7:
737 slots = tdm_slot[TDM_PRI].num;
738 slot_width = tdm_slot[TDM_PRI].width;
739 slot_offset = tdm_tx_slot_offset[TDM_PRI][TDM_7];
740 break;
741 case AFE_PORT_ID_SECONDARY_TDM_RX:
742 slots = tdm_slot[TDM_SEC].num;
743 slot_width = tdm_slot[TDM_SEC].width;
744 slot_offset = tdm_rx_slot_offset[TDM_SEC][TDM_0];
745 break;
746 case AFE_PORT_ID_SECONDARY_TDM_RX_1:
747 slots = tdm_slot[TDM_SEC].num;
748 slot_width = tdm_slot[TDM_SEC].width;
749 slot_offset = tdm_rx_slot_offset[TDM_SEC][TDM_1];
750 break;
751 case AFE_PORT_ID_SECONDARY_TDM_RX_2:
752 slots = tdm_slot[TDM_SEC].num;
753 slot_width = tdm_slot[TDM_SEC].width;
754 slot_offset = tdm_rx_slot_offset[TDM_SEC][TDM_2];
755 break;
756 case AFE_PORT_ID_SECONDARY_TDM_RX_3:
757 slots = tdm_slot[TDM_SEC].num;
758 slot_width = tdm_slot[TDM_SEC].width;
759 slot_offset = tdm_rx_slot_offset[TDM_SEC][TDM_3];
760 break;
761 case AFE_PORT_ID_SECONDARY_TDM_RX_4:
762 slots = tdm_slot[TDM_SEC].num;
763 slot_width = tdm_slot[TDM_SEC].width;
764 slot_offset = tdm_rx_slot_offset[TDM_SEC][TDM_4];
765 break;
766 case AFE_PORT_ID_SECONDARY_TDM_RX_5:
767 slots = tdm_slot[TDM_SEC].num;
768 slot_width = tdm_slot[TDM_SEC].width;
769 slot_offset = tdm_rx_slot_offset[TDM_SEC][TDM_5];
770 break;
771 case AFE_PORT_ID_SECONDARY_TDM_RX_6:
772 slots = tdm_slot[TDM_SEC].num;
773 slot_width = tdm_slot[TDM_SEC].width;
774 slot_offset = tdm_rx_slot_offset[TDM_SEC][TDM_6];
775 break;
776 case AFE_PORT_ID_SECONDARY_TDM_RX_7:
777 slots = tdm_slot[TDM_SEC].num;
778 slot_width = tdm_slot[TDM_SEC].width;
779 slot_offset = tdm_rx_slot_offset[TDM_SEC][TDM_7];
780 break;
781 case AFE_PORT_ID_SECONDARY_TDM_TX:
782 slots = tdm_slot[TDM_SEC].num;
783 slot_width = tdm_slot[TDM_SEC].width;
784 slot_offset = tdm_tx_slot_offset[TDM_SEC][TDM_0];
785 break;
786 case AFE_PORT_ID_SECONDARY_TDM_TX_1:
787 slots = tdm_slot[TDM_SEC].num;
788 slot_width = tdm_slot[TDM_SEC].width;
789 slot_offset = tdm_tx_slot_offset[TDM_SEC][TDM_1];
790 break;
791 case AFE_PORT_ID_SECONDARY_TDM_TX_2:
792 slots = tdm_slot[TDM_SEC].num;
793 slot_width = tdm_slot[TDM_SEC].width;
794 slot_offset = tdm_tx_slot_offset[TDM_SEC][TDM_2];
795 break;
796 case AFE_PORT_ID_SECONDARY_TDM_TX_3:
797 slots = tdm_slot[TDM_SEC].num;
798 slot_width = tdm_slot[TDM_SEC].width;
799 slot_offset = tdm_tx_slot_offset[TDM_SEC][TDM_3];
800 break;
801 case AFE_PORT_ID_SECONDARY_TDM_TX_4:
802 slots = tdm_slot[TDM_SEC].num;
803 slot_width = tdm_slot[TDM_SEC].width;
804 slot_offset = tdm_tx_slot_offset[TDM_SEC][TDM_4];
805 break;
806 case AFE_PORT_ID_SECONDARY_TDM_TX_5:
807 slots = tdm_slot[TDM_SEC].num;
808 slot_width = tdm_slot[TDM_SEC].width;
809 slot_offset = tdm_tx_slot_offset[TDM_SEC][TDM_5];
810 break;
811 case AFE_PORT_ID_SECONDARY_TDM_TX_6:
812 slots = tdm_slot[TDM_SEC].num;
813 slot_width = tdm_slot[TDM_SEC].width;
814 slot_offset = tdm_tx_slot_offset[TDM_SEC][TDM_6];
815 break;
816 case AFE_PORT_ID_SECONDARY_TDM_TX_7:
817 slots = tdm_slot[TDM_SEC].num;
818 slot_width = tdm_slot[TDM_SEC].width;
819 slot_offset = tdm_tx_slot_offset[TDM_SEC][TDM_7];
820 break;
821 case AFE_PORT_ID_TERTIARY_TDM_RX:
822 slots = tdm_slot[TDM_TERT].num;
823 slot_width = tdm_slot[TDM_TERT].width;
824 slot_offset = tdm_rx_slot_offset[TDM_TERT][TDM_0];
825 break;
826 case AFE_PORT_ID_TERTIARY_TDM_RX_1:
827 slots = tdm_slot[TDM_TERT].num;
828 slot_width = tdm_slot[TDM_TERT].width;
829 slot_offset = tdm_rx_slot_offset[TDM_TERT][TDM_1];
830 break;
831 case AFE_PORT_ID_TERTIARY_TDM_RX_2:
832 slots = tdm_slot[TDM_TERT].num;
833 slot_width = tdm_slot[TDM_TERT].width;
834 slot_offset = tdm_rx_slot_offset[TDM_TERT][TDM_2];
835 break;
836 case AFE_PORT_ID_TERTIARY_TDM_RX_3:
837 slots = tdm_slot[TDM_TERT].num;
838 slot_width = tdm_slot[TDM_TERT].width;
839 slot_offset = tdm_rx_slot_offset[TDM_TERT][TDM_3];
840 break;
841 case AFE_PORT_ID_TERTIARY_TDM_RX_4:
842 slots = tdm_slot[TDM_TERT].num;
843 slot_width = tdm_slot[TDM_TERT].width;
844 slot_offset = tdm_rx_slot_offset[TDM_TERT][TDM_4];
845 break;
846 case AFE_PORT_ID_TERTIARY_TDM_RX_5:
847 slots = tdm_slot[TDM_TERT].num;
848 slot_width = tdm_slot[TDM_TERT].width;
849 slot_offset = tdm_rx_slot_offset[TDM_TERT][TDM_5];
850 break;
851 case AFE_PORT_ID_TERTIARY_TDM_RX_6:
852 slots = tdm_slot[TDM_TERT].num;
853 slot_width = tdm_slot[TDM_TERT].width;
854 slot_offset = tdm_rx_slot_offset[TDM_TERT][TDM_6];
855 break;
856 case AFE_PORT_ID_TERTIARY_TDM_RX_7:
857 slots = tdm_slot[TDM_TERT].num;
858 slot_width = tdm_slot[TDM_TERT].width;
859 slot_offset = tdm_rx_slot_offset[TDM_TERT][TDM_7];
860 break;
861 case AFE_PORT_ID_TERTIARY_TDM_TX:
862 slots = tdm_slot[TDM_TERT].num;
863 slot_width = tdm_slot[TDM_TERT].width;
864 slot_offset = tdm_tx_slot_offset[TDM_TERT][TDM_0];
865 break;
866 case AFE_PORT_ID_TERTIARY_TDM_TX_1:
867 slots = tdm_slot[TDM_TERT].num;
868 slot_width = tdm_slot[TDM_TERT].width;
869 slot_offset = tdm_tx_slot_offset[TDM_TERT][TDM_1];
870 break;
871 case AFE_PORT_ID_TERTIARY_TDM_TX_2:
872 slots = tdm_slot[TDM_TERT].num;
873 slot_width = tdm_slot[TDM_TERT].width;
874 slot_offset = tdm_tx_slot_offset[TDM_TERT][TDM_2];
875 break;
876 case AFE_PORT_ID_TERTIARY_TDM_TX_3:
877 slots = tdm_slot[TDM_TERT].num;
878 slot_width = tdm_slot[TDM_TERT].width;
879 slot_offset = tdm_tx_slot_offset[TDM_TERT][TDM_3];
880 break;
881 case AFE_PORT_ID_TERTIARY_TDM_TX_4:
882 slots = tdm_slot[TDM_TERT].num;
883 slot_width = tdm_slot[TDM_TERT].width;
884 slot_offset = tdm_tx_slot_offset[TDM_TERT][TDM_4];
885 break;
886 case AFE_PORT_ID_TERTIARY_TDM_TX_5:
887 slots = tdm_slot[TDM_TERT].num;
888 slot_width = tdm_slot[TDM_TERT].width;
889 slot_offset = tdm_tx_slot_offset[TDM_TERT][TDM_5];
890 break;
891 case AFE_PORT_ID_TERTIARY_TDM_TX_6:
892 slots = tdm_slot[TDM_TERT].num;
893 slot_width = tdm_slot[TDM_TERT].width;
894 slot_offset = tdm_tx_slot_offset[TDM_TERT][TDM_6];
895 break;
896 case AFE_PORT_ID_TERTIARY_TDM_TX_7:
897 slots = tdm_slot[TDM_TERT].num;
898 slot_width = tdm_slot[TDM_TERT].width;
899 slot_offset = tdm_tx_slot_offset[TDM_TERT][TDM_7];
900 break;
901 case AFE_PORT_ID_QUATERNARY_TDM_RX:
902 slots = tdm_slot[TDM_QUAT].num;
903 slot_width = tdm_slot[TDM_QUAT].width;
904 slot_offset = tdm_rx_slot_offset[TDM_QUAT][TDM_0];
905 break;
906 case AFE_PORT_ID_QUATERNARY_TDM_RX_1:
907 slots = tdm_slot[TDM_QUAT].num;
908 slot_width = tdm_slot[TDM_QUAT].width;
909 slot_offset = tdm_rx_slot_offset[TDM_QUAT][TDM_1];
910 break;
911 case AFE_PORT_ID_QUATERNARY_TDM_RX_2:
912 slots = tdm_slot[TDM_QUAT].num;
913 slot_width = tdm_slot[TDM_QUAT].width;
914 slot_offset = tdm_rx_slot_offset[TDM_QUAT][TDM_2];
915 break;
916 case AFE_PORT_ID_QUATERNARY_TDM_RX_3:
917 slots = tdm_slot[TDM_QUAT].num;
918 slot_width = tdm_slot[TDM_QUAT].width;
919 slot_offset = tdm_rx_slot_offset[TDM_QUAT][TDM_3];
920 break;
921 case AFE_PORT_ID_QUATERNARY_TDM_RX_4:
922 slots = tdm_slot[TDM_QUAT].num;
923 slot_width = tdm_slot[TDM_QUAT].width;
924 slot_offset = tdm_rx_slot_offset[TDM_QUAT][TDM_4];
925 break;
926 case AFE_PORT_ID_QUATERNARY_TDM_RX_5:
927 slots = tdm_slot[TDM_QUAT].num;
928 slot_width = tdm_slot[TDM_QUAT].width;
929 slot_offset = tdm_rx_slot_offset[TDM_QUAT][TDM_5];
930 break;
931 case AFE_PORT_ID_QUATERNARY_TDM_RX_6:
932 slots = tdm_slot[TDM_QUAT].num;
933 slot_width = tdm_slot[TDM_QUAT].width;
934 slot_offset = tdm_rx_slot_offset[TDM_QUAT][TDM_6];
935 break;
936 case AFE_PORT_ID_QUATERNARY_TDM_RX_7:
937 slots = tdm_slot[TDM_QUAT].num;
938 slot_width = tdm_slot[TDM_QUAT].width;
939 slot_offset = tdm_rx_slot_offset[TDM_QUAT][TDM_7];
940 break;
941 case AFE_PORT_ID_QUATERNARY_TDM_TX:
942 slots = tdm_slot[TDM_QUAT].num;
943 slot_width = tdm_slot[TDM_QUAT].width;
944 slot_offset = tdm_tx_slot_offset[TDM_QUAT][TDM_0];
945 break;
946 case AFE_PORT_ID_QUATERNARY_TDM_TX_1:
947 slots = tdm_slot[TDM_QUAT].num;
948 slot_width = tdm_slot[TDM_QUAT].width;
949 slot_offset = tdm_tx_slot_offset[TDM_QUAT][TDM_1];
950 break;
951 case AFE_PORT_ID_QUATERNARY_TDM_TX_2:
952 slots = tdm_slot[TDM_QUAT].num;
953 slot_width = tdm_slot[TDM_QUAT].width;
954 slot_offset = tdm_tx_slot_offset[TDM_QUAT][TDM_2];
955 break;
956 case AFE_PORT_ID_QUATERNARY_TDM_TX_3:
957 slots = tdm_slot[TDM_QUAT].num;
958 slot_width = tdm_slot[TDM_QUAT].width;
959 slot_offset = tdm_tx_slot_offset[TDM_QUAT][TDM_3];
960 break;
961 case AFE_PORT_ID_QUATERNARY_TDM_TX_4:
962 slots = tdm_slot[TDM_QUAT].num;
963 slot_width = tdm_slot[TDM_QUAT].width;
964 slot_offset = tdm_tx_slot_offset[TDM_QUAT][TDM_4];
965 break;
966 case AFE_PORT_ID_QUATERNARY_TDM_TX_5:
967 slots = tdm_slot[TDM_QUAT].num;
968 slot_width = tdm_slot[TDM_QUAT].width;
969 slot_offset = tdm_tx_slot_offset[TDM_QUAT][TDM_5];
970 break;
971 case AFE_PORT_ID_QUATERNARY_TDM_TX_6:
972 slots = tdm_slot[TDM_QUAT].num;
973 slot_width = tdm_slot[TDM_QUAT].width;
974 slot_offset = tdm_tx_slot_offset[TDM_QUAT][TDM_6];
975 break;
976 case AFE_PORT_ID_QUATERNARY_TDM_TX_7:
977 slots = tdm_slot[TDM_QUAT].num;
978 slot_width = tdm_slot[TDM_QUAT].width;
979 slot_offset = tdm_tx_slot_offset[TDM_QUAT][TDM_7];
980 break;
981 case AFE_PORT_ID_QUINARY_TDM_RX:
982 slots = tdm_slot[TDM_QUIN].num;
983 slot_width = tdm_slot[TDM_QUIN].width;
984 slot_offset = tdm_rx_slot_offset[TDM_QUIN][TDM_0];
985 break;
986 case AFE_PORT_ID_QUINARY_TDM_RX_1:
987 slots = tdm_slot[TDM_QUIN].num;
988 slot_width = tdm_slot[TDM_QUIN].width;
989 slot_offset = tdm_rx_slot_offset[TDM_QUIN][TDM_1];
990 break;
991 case AFE_PORT_ID_QUINARY_TDM_RX_2:
992 slots = tdm_slot[TDM_QUIN].num;
993 slot_width = tdm_slot[TDM_QUIN].width;
994 slot_offset = tdm_rx_slot_offset[TDM_QUIN][TDM_2];
995 break;
996 case AFE_PORT_ID_QUINARY_TDM_RX_3:
997 slots = tdm_slot[TDM_QUIN].num;
998 slot_width = tdm_slot[TDM_QUIN].width;
999 slot_offset = tdm_rx_slot_offset[TDM_QUIN][TDM_3];
1000 break;
1001 case AFE_PORT_ID_QUINARY_TDM_RX_4:
1002 slots = tdm_slot[TDM_QUIN].num;
1003 slot_width = tdm_slot[TDM_QUIN].width;
1004 slot_offset = tdm_rx_slot_offset[TDM_QUIN][TDM_4];
1005 break;
1006 case AFE_PORT_ID_QUINARY_TDM_RX_5:
1007 slots = tdm_slot[TDM_QUIN].num;
1008 slot_width = tdm_slot[TDM_QUIN].width;
1009 slot_offset = tdm_rx_slot_offset[TDM_QUIN][TDM_5];
1010 break;
1011 case AFE_PORT_ID_QUINARY_TDM_RX_6:
1012 slots = tdm_slot[TDM_QUIN].num;
1013 slot_width = tdm_slot[TDM_QUIN].width;
1014 slot_offset = tdm_rx_slot_offset[TDM_QUIN][TDM_6];
1015 break;
1016 case AFE_PORT_ID_QUINARY_TDM_RX_7:
1017 slots = tdm_slot[TDM_QUIN].num;
1018 slot_width = tdm_slot[TDM_QUIN].width;
1019 slot_offset = tdm_rx_slot_offset[TDM_QUIN][TDM_7];
1020 break;
1021 case AFE_PORT_ID_QUINARY_TDM_TX:
1022 slots = tdm_slot[TDM_QUIN].num;
1023 slot_width = tdm_slot[TDM_QUIN].width;
1024 slot_offset = tdm_tx_slot_offset[TDM_QUIN][TDM_0];
1025 break;
1026 case AFE_PORT_ID_QUINARY_TDM_TX_1:
1027 slots = tdm_slot[TDM_QUIN].num;
1028 slot_width = tdm_slot[TDM_QUIN].width;
1029 slot_offset = tdm_tx_slot_offset[TDM_QUIN][TDM_1];
1030 break;
1031 case AFE_PORT_ID_QUINARY_TDM_TX_2:
1032 slots = tdm_slot[TDM_QUIN].num;
1033 slot_width = tdm_slot[TDM_QUIN].width;
1034 slot_offset = tdm_tx_slot_offset[TDM_QUIN][TDM_2];
1035 break;
1036 case AFE_PORT_ID_QUINARY_TDM_TX_3:
1037 slots = tdm_slot[TDM_QUIN].num;
1038 slot_width = tdm_slot[TDM_QUIN].width;
1039 slot_offset = tdm_tx_slot_offset[TDM_QUIN][TDM_3];
1040 break;
1041 case AFE_PORT_ID_QUINARY_TDM_TX_4:
1042 slots = tdm_slot[TDM_QUIN].num;
1043 slot_width = tdm_slot[TDM_QUIN].width;
1044 slot_offset = tdm_tx_slot_offset[TDM_QUIN][TDM_4];
1045 break;
1046 case AFE_PORT_ID_QUINARY_TDM_TX_5:
1047 slots = tdm_slot[TDM_QUIN].num;
1048 slot_width = tdm_slot[TDM_QUIN].width;
1049 slot_offset = tdm_tx_slot_offset[TDM_QUIN][TDM_5];
1050 break;
1051 case AFE_PORT_ID_QUINARY_TDM_TX_6:
1052 slots = tdm_slot[TDM_QUIN].num;
1053 slot_width = tdm_slot[TDM_QUIN].width;
1054 slot_offset = tdm_tx_slot_offset[TDM_QUIN][TDM_6];
1055 break;
1056 case AFE_PORT_ID_QUINARY_TDM_TX_7:
1057 slots = tdm_slot[TDM_QUIN].num;
1058 slot_width = tdm_slot[TDM_QUIN].width;
1059 slot_offset = tdm_tx_slot_offset[TDM_QUIN][TDM_7];
1060 break;
1061 default:
1062 pr_err("%s: dai id 0x%x not supported\n",
1063 __func__, cpu_dai->id);
1064 return -EINVAL;
1065 }
1066
1067 for (i = 0; i < TDM_SLOT_OFFSET_MAX; i++) {
1068 if (slot_offset[i] != AFE_SLOT_MAPPING_OFFSET_INVALID)
1069 offset_channels++;
1070 else
1071 break;
1072 }
1073
1074 if (offset_channels == 0) {
1075 pr_err("%s: slot offset not supported, offset_channels %d\n",
1076 __func__, offset_channels);
1077 return -EINVAL;
1078 }
1079
1080 if (channels > offset_channels) {
1081 pr_err("%s: channels %d exceed offset_channels %d\n",
1082 __func__, channels, offset_channels);
1083 return -EINVAL;
1084 }
1085
1086 slot_mask = tdm_param_set_slot_mask(slots);
1087 if (!slot_mask) {
1088 pr_err("%s: invalid slot_mask 0x%x\n",
1089 __func__, slot_mask);
1090 return -EINVAL;
1091 }
1092
1093 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
1094 pr_debug("%s: slot_width %d\n", __func__, slot_width);
1095 ret = snd_soc_dai_set_tdm_slot(cpu_dai, 0, slot_mask,
1096 slots, slot_width);
1097 if (ret < 0) {
1098 pr_err("%s: failed to set tdm slot, err:%d\n",
1099 __func__, ret);
1100 goto end;
1101 }
1102
1103 ret = snd_soc_dai_set_channel_map(cpu_dai, 0, NULL,
1104 channels, slot_offset);
1105 if (ret < 0) {
1106 pr_err("%s: failed to set channel map, err:%d\n",
1107 __func__, ret);
1108 goto end;
1109 }
1110 } else if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) {
1111 ret = snd_soc_dai_set_tdm_slot(cpu_dai, slot_mask, 0,
1112 slots, slot_width);
1113 if (ret < 0) {
1114 pr_err("%s: failed to set tdm slot, err:%d\n",
1115 __func__, ret);
1116 goto end;
1117 }
1118
1119 ret = snd_soc_dai_set_channel_map(cpu_dai, channels,
1120 slot_offset, 0, NULL);
1121 if (ret < 0) {
1122 pr_err("%s: failed to set channel map, err:%d\n",
1123 __func__, ret);
1124 goto end;
1125 }
1126 } else {
1127 ret = -EINVAL;
1128 pr_err("%s: invalid use case, err:%d\n",
1129 __func__, ret);
1130 goto end;
1131 }
1132
1133 rate = params_rate(params);
1134 clk_freq = rate * slot_width * slots;
1135 ret = snd_soc_dai_set_sysclk(cpu_dai, 0, clk_freq, SND_SOC_CLOCK_OUT);
1136 if (ret < 0) {
1137 pr_err("%s: failed to set tdm clk, err:%d\n",
1138 __func__, ret);
1139 }
1140
1141end:
1142 return ret;
1143}
1144EXPORT_SYMBOL(msm_tdm_snd_hw_params);
1145
Asish Bhattacharya8e2277f2017-07-20 18:31:55 +0530[diff] [blame]1146static int proxy_rx_ch_get(struct snd_kcontrol *kcontrol,
1147 struct snd_ctl_elem_value *ucontrol)
1148{
1149 pr_debug("%s: proxy_rx channels = %d\n",
1150 __func__, proxy_rx_cfg.channels);
1151 ucontrol->value.integer.value[0] = proxy_rx_cfg.channels - 2;
1152
1153 return 0;
1154}
1155
1156static int proxy_rx_ch_put(struct snd_kcontrol *kcontrol,
1157 struct snd_ctl_elem_value *ucontrol)
1158{
1159 proxy_rx_cfg.channels = ucontrol->value.integer.value[0] + 2;
1160 pr_debug("%s: proxy_rx channels = %d\n",
1161 __func__, proxy_rx_cfg.channels);
1162
1163 return 1;
1164}
1165
1166static int tdm_get_sample_rate(int value)
1167{
1168 int sample_rate = 0;
1169
1170 switch (value) {
1171 case 0:
1172 sample_rate = SAMPLING_RATE_8KHZ;
1173 break;
1174 case 1:
1175 sample_rate = SAMPLING_RATE_16KHZ;
1176 break;
1177 case 2:
1178 sample_rate = SAMPLING_RATE_32KHZ;
1179 break;
1180 case 3:
1181 sample_rate = SAMPLING_RATE_44P1KHZ;
1182 break;
1183 case 4:
1184 sample_rate = SAMPLING_RATE_48KHZ;
1185 break;
1186 case 5:
1187 sample_rate = SAMPLING_RATE_96KHZ;
1188 break;
1189 case 6:
1190 sample_rate = SAMPLING_RATE_192KHZ;
1191 break;
1192 case 7:
1193 sample_rate = SAMPLING_RATE_352P8KHZ;
1194 break;
1195 case 8:
1196 sample_rate = SAMPLING_RATE_384KHZ;
1197 break;
1198 default:
1199 sample_rate = SAMPLING_RATE_48KHZ;
1200 break;
1201 }
1202 return sample_rate;
1203}
1204
1205static int tdm_get_sample_rate_val(int sample_rate)
1206{
1207 int sample_rate_val = 0;
1208
1209 switch (sample_rate) {
1210 case SAMPLING_RATE_8KHZ:
1211 sample_rate_val = 0;
1212 break;
1213 case SAMPLING_RATE_16KHZ:
1214 sample_rate_val = 1;
1215 break;
1216 case SAMPLING_RATE_32KHZ:
1217 sample_rate_val = 2;
1218 break;
1219 case SAMPLING_RATE_44P1KHZ:
1220 sample_rate_val = 3;
1221 break;
1222 case SAMPLING_RATE_48KHZ:
1223 sample_rate_val = 4;
1224 break;
1225 case SAMPLING_RATE_96KHZ:
1226 sample_rate_val = 5;
1227 break;
1228 case SAMPLING_RATE_192KHZ:
1229 sample_rate_val = 6;
1230 break;
1231 case SAMPLING_RATE_352P8KHZ:
1232 sample_rate_val = 7;
1233 break;
1234 case SAMPLING_RATE_384KHZ:
1235 sample_rate_val = 8;
1236 break;
1237 default:
1238 sample_rate_val = 4;
1239 break;
1240 }
1241 return sample_rate_val;
1242}
1243
Dhanalakshmi Siddanid70a4f72019-11-27 15:35:41 +0530[diff] [blame]1244static int tdm_get_mode(struct snd_kcontrol *kcontrol)
1245{
1246 int mode;
1247
1248 if (strnstr(kcontrol->id.name, "PRI",
1249 sizeof(kcontrol->id.name))) {
1250 mode = TDM_PRI;
1251 } else if (strnstr(kcontrol->id.name, "SEC",
1252 sizeof(kcontrol->id.name))) {
1253 mode = TDM_SEC;
1254 } else if (strnstr(kcontrol->id.name, "TERT",
1255 sizeof(kcontrol->id.name))) {
1256 mode = TDM_TERT;
1257 } else if (strnstr(kcontrol->id.name, "QUAT",
1258 sizeof(kcontrol->id.name))) {
1259 mode = TDM_QUAT;
1260 } else if (strnstr(kcontrol->id.name, "QUIN",
1261 sizeof(kcontrol->id.name))) {
1262 mode = TDM_QUIN;
1263 } else {
1264 pr_err("%s: unsupported mode in: %s\n",
1265 __func__, kcontrol->id.name);
1266 mode = -EINVAL;
1267 }
1268
1269 return mode;
1270}
1271
1272static int tdm_get_channel(struct snd_kcontrol *kcontrol)
1273{
1274 int channel;
1275
1276 if (strnstr(kcontrol->id.name, "RX_0",
1277 sizeof(kcontrol->id.name)) ||
1278 strnstr(kcontrol->id.name, "TX_0",
1279 sizeof(kcontrol->id.name))) {
1280 channel = TDM_0;
1281 } else if (strnstr(kcontrol->id.name, "RX_1",
1282 sizeof(kcontrol->id.name)) ||
1283 strnstr(kcontrol->id.name, "TX_1",
1284 sizeof(kcontrol->id.name))) {
1285 channel = TDM_1;
1286 } else if (strnstr(kcontrol->id.name, "RX_2",
1287 sizeof(kcontrol->id.name)) ||
1288 strnstr(kcontrol->id.name, "TX_2",
1289 sizeof(kcontrol->id.name))) {
1290 channel = TDM_2;
1291 } else if (strnstr(kcontrol->id.name, "RX_3",
1292 sizeof(kcontrol->id.name)) ||
1293 strnstr(kcontrol->id.name, "TX_3",
1294 sizeof(kcontrol->id.name))) {
1295 channel = TDM_3;
1296 } else if (strnstr(kcontrol->id.name, "RX_4",
1297 sizeof(kcontrol->id.name)) ||
1298 strnstr(kcontrol->id.name, "TX_4",
1299 sizeof(kcontrol->id.name))) {
1300 channel = TDM_4;
1301 } else if (strnstr(kcontrol->id.name, "RX_5",
1302 sizeof(kcontrol->id.name)) ||
1303 strnstr(kcontrol->id.name, "TX_5",
1304 sizeof(kcontrol->id.name))) {
1305 channel = TDM_5;
1306 } else if (strnstr(kcontrol->id.name, "RX_6",
1307 sizeof(kcontrol->id.name)) ||
1308 strnstr(kcontrol->id.name, "TX_6",
1309 sizeof(kcontrol->id.name))) {
1310 channel = TDM_6;
1311 } else if (strnstr(kcontrol->id.name, "RX_7",
1312 sizeof(kcontrol->id.name)) ||
1313 strnstr(kcontrol->id.name, "TX_7",
1314 sizeof(kcontrol->id.name))) {
1315 channel = TDM_7;
1316 } else {
1317 pr_err("%s: unsupported channel in: %s\n",
1318 __func__, kcontrol->id.name);
1319 channel = -EINVAL;
1320 }
1321
1322 return channel;
1323}
1324
Asish Bhattacharya8e2277f2017-07-20 18:31:55 +0530[diff] [blame]1325static int tdm_get_port_idx(struct snd_kcontrol *kcontrol,
Dhanalakshmi Siddanid70a4f72019-11-27 15:35:41 +0530[diff] [blame]1326 struct tdm_port *port)
Asish Bhattacharya8e2277f2017-07-20 18:31:55 +0530[diff] [blame]1327{
1328 if (port) {
Dhanalakshmi Siddanid70a4f72019-11-27 15:35:41 +0530[diff] [blame]1329 port->mode = tdm_get_mode(kcontrol);
1330 if (port->mode < 0)
1331 return port->mode;
Asish Bhattacharya8e2277f2017-07-20 18:31:55 +0530[diff] [blame]1332
Dhanalakshmi Siddanid70a4f72019-11-27 15:35:41 +0530[diff] [blame]1333 port->channel = tdm_get_channel(kcontrol);
1334 if (port->channel < 0)
1335 return port->channel;
Asish Bhattacharya8e2277f2017-07-20 18:31:55 +0530[diff] [blame]1336 } else
1337 return -EINVAL;
Dhanalakshmi Siddanid70a4f72019-11-27 15:35:41 +0530[diff] [blame]1338
Asish Bhattacharya8e2277f2017-07-20 18:31:55 +0530[diff] [blame]1339 return 0;
1340}
1341
1342static int tdm_rx_sample_rate_get(struct snd_kcontrol *kcontrol,
1343 struct snd_ctl_elem_value *ucontrol)
1344{
1345 struct tdm_port port;
1346 int ret = tdm_get_port_idx(kcontrol, &port);
1347
1348 if (ret) {
1349 pr_err("%s: unsupported control: %s",
1350 __func__, kcontrol->id.name);
1351 } else {
1352 ucontrol->value.enumerated.item[0] = tdm_get_sample_rate_val(
1353 tdm_rx_cfg[port.mode][port.channel].sample_rate);
1354
1355 pr_debug("%s: tdm_rx_sample_rate = %d, item = %d\n", __func__,
1356 tdm_rx_cfg[port.mode][port.channel].sample_rate,
1357 ucontrol->value.enumerated.item[0]);
1358 }
1359 return ret;
1360}
1361
1362static int tdm_rx_sample_rate_put(struct snd_kcontrol *kcontrol,
1363 struct snd_ctl_elem_value *ucontrol)
1364{
1365 struct tdm_port port;
1366 int ret = tdm_get_port_idx(kcontrol, &port);
1367
1368 if (ret) {
1369 pr_err("%s: unsupported control: %s",
1370 __func__, kcontrol->id.name);
1371 } else {
1372 tdm_rx_cfg[port.mode][port.channel].sample_rate =
1373 tdm_get_sample_rate(ucontrol->value.enumerated.item[0]);
1374
1375 pr_debug("%s: tdm_rx_sample_rate = %d, item = %d\n", __func__,
1376 tdm_rx_cfg[port.mode][port.channel].sample_rate,
1377 ucontrol->value.enumerated.item[0]);
1378 }
1379 return ret;
1380}
1381
1382static int tdm_tx_sample_rate_get(struct snd_kcontrol *kcontrol,
1383 struct snd_ctl_elem_value *ucontrol)
1384{
1385 struct tdm_port port;
1386 int ret = tdm_get_port_idx(kcontrol, &port);
1387
1388 if (ret) {
1389 pr_err("%s: unsupported control: %s",
1390 __func__, kcontrol->id.name);
1391 } else {
1392 ucontrol->value.enumerated.item[0] = tdm_get_sample_rate_val(
1393 tdm_tx_cfg[port.mode][port.channel].sample_rate);
1394
1395 pr_debug("%s: tdm_tx_sample_rate = %d, item = %d\n", __func__,
1396 tdm_tx_cfg[port.mode][port.channel].sample_rate,
1397 ucontrol->value.enumerated.item[0]);
1398 }
1399 return ret;
1400}
1401
1402static int tdm_tx_sample_rate_put(struct snd_kcontrol *kcontrol,
1403 struct snd_ctl_elem_value *ucontrol)
1404{
1405 struct tdm_port port;
1406 int ret = tdm_get_port_idx(kcontrol, &port);
1407
1408 if (ret) {
1409 pr_err("%s: unsupported control: %s",
1410 __func__, kcontrol->id.name);
1411 } else {
1412 tdm_tx_cfg[port.mode][port.channel].sample_rate =
1413 tdm_get_sample_rate(ucontrol->value.enumerated.item[0]);
1414
1415 pr_debug("%s: tdm_tx_sample_rate = %d, item = %d\n", __func__,
1416 tdm_tx_cfg[port.mode][port.channel].sample_rate,
1417 ucontrol->value.enumerated.item[0]);
1418 }
1419 return ret;
1420}
1421
1422static int tdm_get_format(int value)
1423{
1424 int format = 0;
1425
1426 switch (value) {
1427 case 0:
1428 format = SNDRV_PCM_FORMAT_S16_LE;
1429 break;
1430 case 1:
1431 format = SNDRV_PCM_FORMAT_S24_LE;
1432 break;
1433 case 2:
1434 format = SNDRV_PCM_FORMAT_S32_LE;
1435 break;
1436 default:
1437 format = SNDRV_PCM_FORMAT_S16_LE;
1438 break;
1439 }
1440 return format;
1441}
1442
1443static int tdm_get_format_val(int format)
1444{
1445 int value = 0;
1446
1447 switch (format) {
1448 case SNDRV_PCM_FORMAT_S16_LE:
1449 value = 0;
1450 break;
1451 case SNDRV_PCM_FORMAT_S24_LE:
1452 value = 1;
1453 break;
1454 case SNDRV_PCM_FORMAT_S32_LE:
1455 value = 2;
1456 break;
1457 default:
1458 value = 0;
1459 break;
1460 }
1461 return value;
1462}
1463
1464static int mi2s_get_format(int value)
1465{
1466 int format = 0;
1467
1468 switch (value) {
1469 case 0:
1470 format = SNDRV_PCM_FORMAT_S16_LE;
1471 break;
1472 case 1:
1473 format = SNDRV_PCM_FORMAT_S24_LE;
1474 break;
1475 case 2:
1476 format = SNDRV_PCM_FORMAT_S24_3LE;
1477 break;
1478 case 3:
1479 format = SNDRV_PCM_FORMAT_S32_LE;
1480 break;
1481 default:
1482 format = SNDRV_PCM_FORMAT_S16_LE;
1483 break;
1484 }
1485 return format;
1486}
1487
1488static int mi2s_get_format_value(int format)
1489{
1490 int value = 0;
1491
1492 switch (format) {
1493 case SNDRV_PCM_FORMAT_S16_LE:
1494 value = 0;
1495 break;
1496 case SNDRV_PCM_FORMAT_S24_LE:
1497 value = 1;
1498 break;
1499 case SNDRV_PCM_FORMAT_S24_3LE:
1500 value = 2;
1501 break;
1502 case SNDRV_PCM_FORMAT_S32_LE:
1503 value = 3;
1504 break;
1505 default:
1506 value = 0;
1507 break;
1508 }
1509 return value;
1510}
1511
1512static int tdm_rx_format_get(struct snd_kcontrol *kcontrol,
1513 struct snd_ctl_elem_value *ucontrol)
1514{
1515 struct tdm_port port;
1516 int ret = tdm_get_port_idx(kcontrol, &port);
1517
1518 if (ret) {
1519 pr_err("%s: unsupported control: %s",
1520 __func__, kcontrol->id.name);
1521 } else {
1522 ucontrol->value.enumerated.item[0] = tdm_get_format_val(
1523 tdm_rx_cfg[port.mode][port.channel].bit_format);
1524
1525 pr_debug("%s: tdm_rx_bit_format = %d, item = %d\n", __func__,
1526 tdm_rx_cfg[port.mode][port.channel].bit_format,
1527 ucontrol->value.enumerated.item[0]);
1528 }
1529 return ret;
1530}
1531
1532static int tdm_rx_format_put(struct snd_kcontrol *kcontrol,
1533 struct snd_ctl_elem_value *ucontrol)
1534{
1535 struct tdm_port port;
1536 int ret = tdm_get_port_idx(kcontrol, &port);
1537
1538 if (ret) {
1539 pr_err("%s: unsupported control: %s",
1540 __func__, kcontrol->id.name);
1541 } else {
1542 tdm_rx_cfg[port.mode][port.channel].bit_format =
1543 tdm_get_format(ucontrol->value.enumerated.item[0]);
1544
1545 pr_debug("%s: tdm_rx_bit_format = %d, item = %d\n", __func__,
1546 tdm_rx_cfg[port.mode][port.channel].bit_format,
1547 ucontrol->value.enumerated.item[0]);
1548 }
1549 return ret;
1550}
1551
1552static int tdm_tx_format_get(struct snd_kcontrol *kcontrol,
1553 struct snd_ctl_elem_value *ucontrol)
1554{
1555 struct tdm_port port;
1556 int ret = tdm_get_port_idx(kcontrol, &port);
1557
1558 if (ret) {
1559 pr_err("%s: unsupported control: %s",
1560 __func__, kcontrol->id.name);
1561 } else {
1562 ucontrol->value.enumerated.item[0] = tdm_get_format_val(
1563 tdm_tx_cfg[port.mode][port.channel].bit_format);
1564
1565 pr_debug("%s: tdm_tx_bit_format = %d, item = %d\n", __func__,
1566 tdm_tx_cfg[port.mode][port.channel].bit_format,
1567 ucontrol->value.enumerated.item[0]);
1568 }
1569 return ret;
1570}
1571
1572static int tdm_tx_format_put(struct snd_kcontrol *kcontrol,
1573 struct snd_ctl_elem_value *ucontrol)
1574{
1575 struct tdm_port port;
1576 int ret = tdm_get_port_idx(kcontrol, &port);
1577
1578 if (ret) {
1579 pr_err("%s: unsupported control: %s",
1580 __func__, kcontrol->id.name);
1581 } else {
1582 tdm_tx_cfg[port.mode][port.channel].bit_format =
1583 tdm_get_format(ucontrol->value.enumerated.item[0]);
1584
1585 pr_debug("%s: tdm_tx_bit_format = %d, item = %d\n", __func__,
1586 tdm_tx_cfg[port.mode][port.channel].bit_format,
1587 ucontrol->value.enumerated.item[0]);
1588 }
1589 return ret;
1590}
1591
1592static int tdm_rx_ch_get(struct snd_kcontrol *kcontrol,
1593 struct snd_ctl_elem_value *ucontrol)
1594{
1595 struct tdm_port port;
1596 int ret = tdm_get_port_idx(kcontrol, &port);
1597
1598 if (ret) {
1599 pr_err("%s: unsupported control: %s",
1600 __func__, kcontrol->id.name);
1601 } else {
1602
1603 ucontrol->value.enumerated.item[0] =
1604 tdm_rx_cfg[port.mode][port.channel].channels - 1;
1605
1606 pr_debug("%s: tdm_rx_ch = %d, item = %d\n", __func__,
1607 tdm_rx_cfg[port.mode][port.channel].channels - 1,
1608 ucontrol->value.enumerated.item[0]);
1609 }
1610 return ret;
1611}
1612
1613static int tdm_rx_ch_put(struct snd_kcontrol *kcontrol,
1614 struct snd_ctl_elem_value *ucontrol)
1615{
1616 struct tdm_port port;
1617 int ret = tdm_get_port_idx(kcontrol, &port);
1618
1619 if (ret) {
1620 pr_err("%s: unsupported control: %s",
1621 __func__, kcontrol->id.name);
1622 } else {
1623 tdm_rx_cfg[port.mode][port.channel].channels =
1624 ucontrol->value.enumerated.item[0] + 1;
1625
1626 pr_debug("%s: tdm_rx_ch = %d, item = %d\n", __func__,
1627 tdm_rx_cfg[port.mode][port.channel].channels,
1628 ucontrol->value.enumerated.item[0] + 1);
1629 }
1630 return ret;
1631}
1632
1633static int tdm_tx_ch_get(struct snd_kcontrol *kcontrol,
1634 struct snd_ctl_elem_value *ucontrol)
1635{
1636 struct tdm_port port;
1637 int ret = tdm_get_port_idx(kcontrol, &port);
1638
1639 if (ret) {
1640 pr_err("%s: unsupported control: %s",
1641 __func__, kcontrol->id.name);
1642 } else {
1643 ucontrol->value.enumerated.item[0] =
1644 tdm_tx_cfg[port.mode][port.channel].channels - 1;
1645
1646 pr_debug("%s: tdm_tx_ch = %d, item = %d\n", __func__,
1647 tdm_tx_cfg[port.mode][port.channel].channels - 1,
1648 ucontrol->value.enumerated.item[0]);
1649 }
1650 return ret;
1651}
1652
1653static int tdm_tx_ch_put(struct snd_kcontrol *kcontrol,
1654 struct snd_ctl_elem_value *ucontrol)
1655{
1656 struct tdm_port port;
1657 int ret = tdm_get_port_idx(kcontrol, &port);
1658
1659 if (ret) {
1660 pr_err("%s: unsupported control: %s",
1661 __func__, kcontrol->id.name);
1662 } else {
1663 tdm_tx_cfg[port.mode][port.channel].channels =
1664 ucontrol->value.enumerated.item[0] + 1;
1665
1666 pr_debug("%s: tdm_tx_ch = %d, item = %d\n", __func__,
1667 tdm_tx_cfg[port.mode][port.channel].channels,
1668 ucontrol->value.enumerated.item[0] + 1);
1669 }
1670 return ret;
1671}
1672
Dhanalakshmi Siddanid70a4f72019-11-27 15:35:41 +0530[diff] [blame]1673static int tdm_get_slot_num_val(int slot_num)
1674{
1675 int slot_num_val;
1676
1677 switch (slot_num) {
1678 case 1:
1679 slot_num_val = 0;
1680 break;
1681 case 2:
1682 slot_num_val = 1;
1683 break;
1684 case 4:
1685 slot_num_val = 2;
1686 break;
1687 case 8:
1688 slot_num_val = 3;
1689 break;
1690 case 16:
1691 slot_num_val = 4;
1692 break;
1693 case 32:
1694 slot_num_val = 5;
1695 break;
1696 default:
1697 slot_num_val = 5;
1698 break;
1699 }
1700 return slot_num_val;
1701}
1702
1703static int tdm_slot_num_get(struct snd_kcontrol *kcontrol,
1704 struct snd_ctl_elem_value *ucontrol)
1705{
1706 int mode = tdm_get_mode(kcontrol);
1707
1708 if (mode < 0) {
1709 pr_err("%s: unsupported control: %s\n",
1710 __func__, kcontrol->id.name);
1711 return mode;
1712 }
1713
1714 ucontrol->value.enumerated.item[0] =
1715 tdm_get_slot_num_val(tdm_slot[mode].num);
1716
1717 pr_debug("%s: mode = %d, tdm_slot_num = %d, item = %d\n", __func__,
1718 mode, tdm_slot[mode].num,
1719 ucontrol->value.enumerated.item[0]);
1720
1721 return 0;
1722}
1723
1724static int tdm_get_slot_num(int value)
1725{
1726 int slot_num;
1727
1728 switch (value) {
1729 case 0:
1730 slot_num = 1;
1731 break;
1732 case 1:
1733 slot_num = 2;
1734 break;
1735 case 2:
1736 slot_num = 4;
1737 break;
1738 case 3:
1739 slot_num = 8;
1740 break;
1741 case 4:
1742 slot_num = 16;
1743 break;
1744 case 5:
1745 slot_num = 32;
1746 break;
1747 default:
1748 slot_num = 8;
1749 break;
1750 }
1751 return slot_num;
1752}
1753
1754static int tdm_slot_num_put(struct snd_kcontrol *kcontrol,
1755 struct snd_ctl_elem_value *ucontrol)
1756{
1757 int mode = tdm_get_mode(kcontrol);
1758
1759 if (mode < 0) {
1760 pr_err("%s: unsupported control: %s\n",
1761 __func__, kcontrol->id.name);
1762 return mode;
1763 }
1764
1765 tdm_slot[mode].num =
1766 tdm_get_slot_num(ucontrol->value.enumerated.item[0]);
1767
1768 pr_debug("%s: mode = %d, tdm_slot_num = %d, item = %d\n", __func__,
1769 mode, tdm_slot[mode].num,
1770 ucontrol->value.enumerated.item[0]);
1771
1772 return 0;
1773}
1774
1775static int tdm_get_slot_width_val(int slot_width)
1776{
1777 int slot_width_val;
1778
1779 switch (slot_width) {
1780 case 16:
1781 slot_width_val = 0;
1782 break;
1783 case 24:
1784 slot_width_val = 1;
1785 break;
1786 case 32:
1787 slot_width_val = 2;
1788 break;
1789 default:
1790 slot_width_val = 2;
1791 break;
1792 }
1793 return slot_width_val;
1794}
1795
1796static int tdm_slot_width_get(struct snd_kcontrol *kcontrol,
1797 struct snd_ctl_elem_value *ucontrol)
1798{
1799 int mode = tdm_get_mode(kcontrol);
1800
1801 if (mode < 0) {
1802 pr_err("%s: unsupported control: %s\n",
1803 __func__, kcontrol->id.name);
1804 return mode;
1805 }
1806
1807 ucontrol->value.enumerated.item[0] =
1808 tdm_get_slot_width_val(tdm_slot[mode].width);
1809
1810 pr_debug("%s: mode = %d, tdm_slot_width = %d, item = %d\n", __func__,
1811 mode, tdm_slot[mode].width,
1812 ucontrol->value.enumerated.item[0]);
1813
1814 return 0;
1815}
1816
1817static int tdm_get_slot_width(int value)
1818{
1819 int slot_width;
1820
1821 switch (value) {
1822 case 0:
1823 slot_width = 16;
1824 break;
1825 case 1:
1826 slot_width = 24;
1827 break;
1828 case 2:
1829 slot_width = 32;
1830 break;
1831 default:
1832 slot_width = 32;
1833 break;
1834 }
1835 return slot_width;
1836}
1837
1838static int tdm_slot_width_put(struct snd_kcontrol *kcontrol,
1839 struct snd_ctl_elem_value *ucontrol)
1840{
1841 int mode = tdm_get_mode(kcontrol);
1842
1843 if (mode < 0) {
1844 pr_err("%s: unsupported control: %s\n",
1845 __func__, kcontrol->id.name);
1846 return mode;
1847 }
1848
1849 tdm_slot[mode].width =
1850 tdm_get_slot_width(ucontrol->value.enumerated.item[0]);
1851
1852 pr_debug("%s: mode = %d, tdm_slot_width = %d, item = %d\n", __func__,
1853 mode, tdm_slot[mode].width,
1854 ucontrol->value.enumerated.item[0]);
1855
1856 return 0;
1857}
1858
1859static int tdm_rx_slot_mapping_get(struct snd_kcontrol *kcontrol,
1860 struct snd_ctl_elem_value *ucontrol)
1861{
1862 unsigned int *slot_offset;
1863 int i;
1864 struct tdm_port port;
1865 int ret = tdm_get_port_idx(kcontrol, &port);
1866
1867 if (ret) {
1868 pr_err("%s: unsupported control: %s\n",
1869 __func__, kcontrol->id.name);
1870 } else {
1871 if (port.mode < TDM_INTERFACE_MAX &&
1872 port.channel < TDM_PORT_MAX) {
1873 slot_offset =
1874 tdm_rx_slot_offset[port.mode][port.channel];
1875 pr_debug("%s: mode = %d, channel = %d\n",
1876 __func__, port.mode, port.channel);
1877 for (i = 0; i < TDM_SLOT_OFFSET_MAX; i++) {
1878 ucontrol->value.integer.value[i] =
1879 slot_offset[i];
1880 pr_debug("%s: offset %d, value %d\n",
1881 __func__, i, slot_offset[i]);
1882 }
1883 } else {
1884 pr_err("%s: unsupported mode/channel\n", __func__);
1885 }
1886 }
1887 return ret;
1888}
1889
1890static int tdm_rx_slot_mapping_put(struct snd_kcontrol *kcontrol,
1891 struct snd_ctl_elem_value *ucontrol)
1892{
1893 unsigned int *slot_offset;
1894 int i;
1895 struct tdm_port port;
1896 int ret = tdm_get_port_idx(kcontrol, &port);
1897
1898 if (ret) {
1899 pr_err("%s: unsupported control: %s\n",
1900 __func__, kcontrol->id.name);
1901 } else {
1902 if (port.mode < TDM_INTERFACE_MAX &&
1903 port.channel < TDM_PORT_MAX) {
1904 slot_offset =
1905 tdm_rx_slot_offset[port.mode][port.channel];
1906 pr_debug("%s: mode = %d, channel = %d\n",
1907 __func__, port.mode, port.channel);
1908 for (i = 0; i < TDM_SLOT_OFFSET_MAX; i++) {
1909 slot_offset[i] =
1910 ucontrol->value.integer.value[i];
1911 pr_debug("%s: offset %d, value %d\n",
1912 __func__, i, slot_offset[i]);
1913 }
1914 } else {
1915 pr_err("%s: unsupported mode/channel\n", __func__);
1916 }
1917 }
1918 return ret;
1919}
1920
1921static int tdm_tx_slot_mapping_get(struct snd_kcontrol *kcontrol,
1922 struct snd_ctl_elem_value *ucontrol)
1923{
1924 unsigned int *slot_offset;
1925 int i;
1926 struct tdm_port port;
1927 int ret = tdm_get_port_idx(kcontrol, &port);
1928
1929 if (ret) {
1930 pr_err("%s: unsupported control: %s\n",
1931 __func__, kcontrol->id.name);
1932 } else {
1933 if (port.mode < TDM_INTERFACE_MAX &&
1934 port.channel < TDM_PORT_MAX) {
1935 slot_offset =
1936 tdm_tx_slot_offset[port.mode][port.channel];
1937 pr_debug("%s: mode = %d, channel = %d\n",
1938 __func__, port.mode, port.channel);
1939 for (i = 0; i < TDM_SLOT_OFFSET_MAX; i++) {
1940 ucontrol->value.integer.value[i] =
1941 slot_offset[i];
1942 pr_debug("%s: offset %d, value %d\n",
1943 __func__, i, slot_offset[i]);
1944 }
1945 } else {
1946 pr_err("%s: unsupported mode/channel\n", __func__);
1947 }
1948 }
1949 return ret;
1950}
1951
1952static int tdm_tx_slot_mapping_put(struct snd_kcontrol *kcontrol,
1953 struct snd_ctl_elem_value *ucontrol)
1954{
1955 unsigned int *slot_offset;
1956 int i;
1957 struct tdm_port port;
1958 int ret = tdm_get_port_idx(kcontrol, &port);
1959
1960 if (ret) {
1961 pr_err("%s: unsupported control: %s\n",
1962 __func__, kcontrol->id.name);
1963 } else {
1964 if (port.mode < TDM_INTERFACE_MAX &&
1965 port.channel < TDM_PORT_MAX) {
1966 slot_offset =
1967 tdm_tx_slot_offset[port.mode][port.channel];
1968 pr_debug("%s: mode = %d, channel = %d\n",
1969 __func__, port.mode, port.channel);
1970 for (i = 0; i < TDM_SLOT_OFFSET_MAX; i++) {
1971 slot_offset[i] =
1972 ucontrol->value.integer.value[i];
1973 pr_debug("%s: offset %d, value %d\n",
1974 __func__, i, slot_offset[i]);
1975 }
1976 } else {
1977 pr_err("%s: unsupported mode/channel\n", __func__);
1978 }
1979 }
1980 return ret;
1981}
1982
Asish Bhattacharya8e2277f2017-07-20 18:31:55 +0530[diff] [blame]1983static int aux_pcm_get_sample_rate(int value)
1984{
1985 int sample_rate;
1986
1987 switch (value) {
1988 case 1:
1989 sample_rate = SAMPLING_RATE_16KHZ;
1990 break;
1991 case 0:
1992 default:
1993 sample_rate = SAMPLING_RATE_8KHZ;
1994 break;
1995 }
1996 return sample_rate;
1997}
1998
1999static int aux_pcm_get_sample_rate_val(int sample_rate)
2000{
2001 int sample_rate_val;
2002
2003 switch (sample_rate) {
2004 case SAMPLING_RATE_16KHZ:
2005 sample_rate_val = 1;
2006 break;
2007 case SAMPLING_RATE_8KHZ:
2008 default:
2009 sample_rate_val = 0;
2010 break;
2011 }
2012 return sample_rate_val;
2013}
2014
2015static int aux_pcm_get_port_idx(struct snd_kcontrol *kcontrol)
2016{
2017 int idx;
2018
2019 if (strnstr(kcontrol->id.name, "PRIM_AUX_PCM",
2020 sizeof("PRIM_AUX_PCM")))
2021 idx = PRIM_AUX_PCM;
2022 else if (strnstr(kcontrol->id.name, "SEC_AUX_PCM",
2023 sizeof("SEC_AUX_PCM")))
2024 idx = SEC_AUX_PCM;
2025 else if (strnstr(kcontrol->id.name, "TERT_AUX_PCM",
2026 sizeof("TERT_AUX_PCM")))
2027 idx = TERT_AUX_PCM;
2028 else if (strnstr(kcontrol->id.name, "QUAT_AUX_PCM",
2029 sizeof("QUAT_AUX_PCM")))
2030 idx = QUAT_AUX_PCM;
Rohit Kumard1754482017-09-10 22:57:39 +0530[diff] [blame]2031 else if (strnstr(kcontrol->id.name, "QUIN_AUX_PCM",
2032 sizeof("QUIN_AUX_PCM")))
2033 idx = QUIN_AUX_PCM;
Asish Bhattacharya8e2277f2017-07-20 18:31:55 +0530[diff] [blame]2034 else {
2035 pr_err("%s: unsupported port: %s",
2036 __func__, kcontrol->id.name);
2037 idx = -EINVAL;
2038 }
2039
2040 return idx;
2041}
2042
2043static int aux_pcm_rx_sample_rate_put(struct snd_kcontrol *kcontrol,
2044 struct snd_ctl_elem_value *ucontrol)
2045{
2046 int idx = aux_pcm_get_port_idx(kcontrol);
2047
2048 if (idx < 0)
2049 return idx;
2050
2051 aux_pcm_rx_cfg[idx].sample_rate =
2052 aux_pcm_get_sample_rate(ucontrol->value.enumerated.item[0]);
2053
2054 pr_debug("%s: idx[%d]_rx_sample_rate = %d, item = %d\n", __func__,
2055 idx, aux_pcm_rx_cfg[idx].sample_rate,
2056 ucontrol->value.enumerated.item[0]);
2057
2058 return 0;
2059}
2060
2061static int aux_pcm_rx_sample_rate_get(struct snd_kcontrol *kcontrol,
2062 struct snd_ctl_elem_value *ucontrol)
2063{
2064 int idx = aux_pcm_get_port_idx(kcontrol);
2065
2066 if (idx < 0)
2067 return idx;
2068
2069 ucontrol->value.enumerated.item[0] =
2070 aux_pcm_get_sample_rate_val(aux_pcm_rx_cfg[idx].sample_rate);
2071
2072 pr_debug("%s: idx[%d]_rx_sample_rate = %d, item = %d\n", __func__,
2073 idx, aux_pcm_rx_cfg[idx].sample_rate,
2074 ucontrol->value.enumerated.item[0]);
2075
2076 return 0;
2077}
2078
2079static int aux_pcm_tx_sample_rate_put(struct snd_kcontrol *kcontrol,
2080 struct snd_ctl_elem_value *ucontrol)
2081{
2082 int idx = aux_pcm_get_port_idx(kcontrol);
2083
2084 if (idx < 0)
2085 return idx;
2086
2087 aux_pcm_tx_cfg[idx].sample_rate =
2088 aux_pcm_get_sample_rate(ucontrol->value.enumerated.item[0]);
2089
2090 pr_debug("%s: idx[%d]_tx_sample_rate = %d, item = %d\n", __func__,
2091 idx, aux_pcm_tx_cfg[idx].sample_rate,
2092 ucontrol->value.enumerated.item[0]);
2093
2094 return 0;
2095}
2096
2097static int aux_pcm_tx_sample_rate_get(struct snd_kcontrol *kcontrol,
2098 struct snd_ctl_elem_value *ucontrol)
2099{
2100 int idx = aux_pcm_get_port_idx(kcontrol);
2101
2102 if (idx < 0)
2103 return idx;
2104
2105 ucontrol->value.enumerated.item[0] =
2106 aux_pcm_get_sample_rate_val(aux_pcm_tx_cfg[idx].sample_rate);
2107
2108 pr_debug("%s: idx[%d]_tx_sample_rate = %d, item = %d\n", __func__,
2109 idx, aux_pcm_tx_cfg[idx].sample_rate,
2110 ucontrol->value.enumerated.item[0]);
2111
2112 return 0;
2113}
2114
2115static int mi2s_get_port_idx(struct snd_kcontrol *kcontrol)
2116{
2117 int idx;
2118
2119 if (strnstr(kcontrol->id.name, "PRIM_MI2S_RX",
2120 sizeof("PRIM_MI2S_RX")))
2121 idx = PRIM_MI2S;
2122 else if (strnstr(kcontrol->id.name, "SEC_MI2S_RX",
2123 sizeof("SEC_MI2S_RX")))
2124 idx = SEC_MI2S;
2125 else if (strnstr(kcontrol->id.name, "TERT_MI2S_RX",
2126 sizeof("TERT_MI2S_RX")))
2127 idx = TERT_MI2S;
2128 else if (strnstr(kcontrol->id.name, "QUAT_MI2S_RX",
2129 sizeof("QUAT_MI2S_RX")))
2130 idx = QUAT_MI2S;
Rohit Kumard1754482017-09-10 22:57:39 +0530[diff] [blame]2131 else if (strnstr(kcontrol->id.name, "QUIN_MI2S_RX",
2132 sizeof("QUIN_MI2S_RX")))
2133 idx = QUIN_MI2S;
Asish Bhattacharya8e2277f2017-07-20 18:31:55 +0530[diff] [blame]2134 else if (strnstr(kcontrol->id.name, "PRIM_MI2S_TX",
2135 sizeof("PRIM_MI2S_TX")))
2136 idx = PRIM_MI2S;
2137 else if (strnstr(kcontrol->id.name, "SEC_MI2S_TX",
2138 sizeof("SEC_MI2S_TX")))
2139 idx = SEC_MI2S;
2140 else if (strnstr(kcontrol->id.name, "TERT_MI2S_TX",
2141 sizeof("TERT_MI2S_TX")))
2142 idx = TERT_MI2S;
2143 else if (strnstr(kcontrol->id.name, "QUAT_MI2S_TX",
2144 sizeof("QUAT_MI2S_TX")))
2145 idx = QUAT_MI2S;
Rohit Kumard1754482017-09-10 22:57:39 +0530[diff] [blame]2146 else if (strnstr(kcontrol->id.name, "QUIN_MI2S_TX",
2147 sizeof("QUIN_MI2S_TX")))
2148 idx = QUIN_MI2S;
Asish Bhattacharya8e2277f2017-07-20 18:31:55 +0530[diff] [blame]2149 else {
2150 pr_err("%s: unsupported channel: %s",
2151 __func__, kcontrol->id.name);
2152 idx = -EINVAL;
2153 }
2154
2155 return idx;
2156}
2157
2158static int mi2s_get_sample_rate_val(int sample_rate)
2159{
2160 int sample_rate_val;
2161
2162 switch (sample_rate) {
2163 case SAMPLING_RATE_8KHZ:
2164 sample_rate_val = 0;
2165 break;
2166 case SAMPLING_RATE_16KHZ:
2167 sample_rate_val = 1;
2168 break;
2169 case SAMPLING_RATE_32KHZ:
2170 sample_rate_val = 2;
2171 break;
2172 case SAMPLING_RATE_44P1KHZ:
2173 sample_rate_val = 3;
2174 break;
2175 case SAMPLING_RATE_48KHZ:
2176 sample_rate_val = 4;
2177 break;
2178 case SAMPLING_RATE_96KHZ:
2179 sample_rate_val = 5;
2180 break;
2181 case SAMPLING_RATE_192KHZ:
2182 sample_rate_val = 6;
2183 break;
2184 default:
2185 sample_rate_val = 4;
2186 break;
2187 }
2188 return sample_rate_val;
2189}
2190
2191static int mi2s_get_sample_rate(int value)
2192{
2193 int sample_rate;
2194
2195 switch (value) {
2196 case 0:
2197 sample_rate = SAMPLING_RATE_8KHZ;
2198 break;
2199 case 1:
2200 sample_rate = SAMPLING_RATE_16KHZ;
2201 break;
2202 case 2:
2203 sample_rate = SAMPLING_RATE_32KHZ;
2204 break;
2205 case 3:
2206 sample_rate = SAMPLING_RATE_44P1KHZ;
2207 break;
2208 case 4:
2209 sample_rate = SAMPLING_RATE_48KHZ;
2210 break;
2211 case 5:
2212 sample_rate = SAMPLING_RATE_96KHZ;
2213 break;
2214 case 6:
2215 sample_rate = SAMPLING_RATE_192KHZ;
2216 break;
2217 default:
2218 sample_rate = SAMPLING_RATE_48KHZ;
2219 break;
2220 }
2221 return sample_rate;
2222}
2223
2224static int mi2s_rx_sample_rate_put(struct snd_kcontrol *kcontrol,
2225 struct snd_ctl_elem_value *ucontrol)
2226{
2227 int idx = mi2s_get_port_idx(kcontrol);
2228
2229 if (idx < 0)
2230 return idx;
2231
2232 mi2s_rx_cfg[idx].sample_rate =
2233 mi2s_get_sample_rate(ucontrol->value.enumerated.item[0]);
2234
2235 pr_debug("%s: idx[%d]_rx_sample_rate = %d, item = %d\n", __func__,
2236 idx, mi2s_rx_cfg[idx].sample_rate,
2237 ucontrol->value.enumerated.item[0]);
2238
2239 return 0;
2240}
2241
2242static int mi2s_rx_sample_rate_get(struct snd_kcontrol *kcontrol,
2243 struct snd_ctl_elem_value *ucontrol)
2244{
2245 int idx = mi2s_get_port_idx(kcontrol);
2246
2247 if (idx < 0)
2248 return idx;
2249
2250 ucontrol->value.enumerated.item[0] =
2251 mi2s_get_sample_rate_val(mi2s_rx_cfg[idx].sample_rate);
2252
2253 pr_debug("%s: idx[%d]_rx_sample_rate = %d, item = %d\n", __func__,
2254 idx, mi2s_rx_cfg[idx].sample_rate,
2255 ucontrol->value.enumerated.item[0]);
2256
2257 return 0;
2258}
2259
2260static int mi2s_tx_sample_rate_put(struct snd_kcontrol *kcontrol,
2261 struct snd_ctl_elem_value *ucontrol)
2262{
2263 int idx = mi2s_get_port_idx(kcontrol);
2264
2265 if (idx < 0)
2266 return idx;
2267
2268 mi2s_tx_cfg[idx].sample_rate =
2269 mi2s_get_sample_rate(ucontrol->value.enumerated.item[0]);
2270
2271 pr_debug("%s: idx[%d]_tx_sample_rate = %d, item = %d\n", __func__,
2272 idx, mi2s_tx_cfg[idx].sample_rate,
2273 ucontrol->value.enumerated.item[0]);
2274
2275 return 0;
2276}
2277
2278static int mi2s_tx_sample_rate_get(struct snd_kcontrol *kcontrol,
2279 struct snd_ctl_elem_value *ucontrol)
2280{
2281 int idx = mi2s_get_port_idx(kcontrol);
2282
2283 if (idx < 0)
2284 return idx;
2285
2286 ucontrol->value.enumerated.item[0] =
2287 mi2s_get_sample_rate_val(mi2s_tx_cfg[idx].sample_rate);
2288
2289 pr_debug("%s: idx[%d]_tx_sample_rate = %d, item = %d\n", __func__,
2290 idx, mi2s_tx_cfg[idx].sample_rate,
2291 ucontrol->value.enumerated.item[0]);
2292
2293 return 0;
2294}
2295
2296static int mi2s_tx_format_put(struct snd_kcontrol *kcontrol,
2297 struct snd_ctl_elem_value *ucontrol)
2298{
2299 int idx = mi2s_get_port_idx(kcontrol);
2300
2301 if (idx < 0)
2302 return idx;
2303
2304 mi2s_tx_cfg[idx].bit_format =
2305 mi2s_get_format(ucontrol->value.enumerated.item[0]);
2306
2307 pr_debug("%s: idx[%d] _tx_format = %d, item = %d\n", __func__,
2308 idx, mi2s_tx_cfg[idx].bit_format,
2309 ucontrol->value.enumerated.item[0]);
2310
2311 return 0;
2312}
2313
2314static int mi2s_tx_format_get(struct snd_kcontrol *kcontrol,
2315 struct snd_ctl_elem_value *ucontrol)
2316{
2317 int idx = mi2s_get_port_idx(kcontrol);
2318
2319 if (idx < 0)
2320 return idx;
2321
2322 ucontrol->value.enumerated.item[0] =
2323 mi2s_get_format_value(mi2s_tx_cfg[idx].bit_format);
2324
2325 pr_debug("%s: idx[%d]_tx_format = %d, item = %d\n", __func__,
2326 idx, mi2s_tx_cfg[idx].bit_format,
2327 ucontrol->value.enumerated.item[0]);
2328
2329 return 0;
2330}
2331
2332static int mi2s_rx_format_put(struct snd_kcontrol *kcontrol,
2333 struct snd_ctl_elem_value *ucontrol)
2334{
2335 int idx = mi2s_get_port_idx(kcontrol);
2336
2337 if (idx < 0)
2338 return idx;
2339
2340 mi2s_rx_cfg[idx].bit_format =
2341 mi2s_get_format(ucontrol->value.enumerated.item[0]);
2342
2343 pr_debug("%s: idx[%d] _rx_format = %d, item = %d\n", __func__,
2344 idx, mi2s_rx_cfg[idx].bit_format,
2345 ucontrol->value.enumerated.item[0]);
2346
2347 return 0;
2348}
2349
2350static int mi2s_rx_format_get(struct snd_kcontrol *kcontrol,
2351 struct snd_ctl_elem_value *ucontrol)
2352{
2353 int idx = mi2s_get_port_idx(kcontrol);
2354
2355 if (idx < 0)
2356 return idx;
2357
2358 ucontrol->value.enumerated.item[0] =
2359 mi2s_get_format_value(mi2s_rx_cfg[idx].bit_format);
2360
2361 pr_debug("%s: idx[%d]_rx_format = %d, item = %d\n", __func__,
2362 idx, mi2s_rx_cfg[idx].bit_format,
2363 ucontrol->value.enumerated.item[0]);
2364
2365 return 0;
2366}
2367
2368static int msm_mi2s_rx_ch_get(struct snd_kcontrol *kcontrol,
2369 struct snd_ctl_elem_value *ucontrol)
2370{
2371 int idx = mi2s_get_port_idx(kcontrol);
2372
2373 if (idx < 0)
2374 return idx;
2375
2376 pr_debug("%s: msm_mi2s_[%d]_rx_ch = %d\n", __func__,
2377 idx, mi2s_rx_cfg[idx].channels);
2378 ucontrol->value.enumerated.item[0] = mi2s_rx_cfg[idx].channels - 1;
2379
2380 return 0;
2381}
2382
2383static int msm_mi2s_rx_ch_put(struct snd_kcontrol *kcontrol,
2384 struct snd_ctl_elem_value *ucontrol)
2385{
2386 int idx = mi2s_get_port_idx(kcontrol);
2387
2388 if (idx < 0)
2389 return idx;
2390
2391 mi2s_rx_cfg[idx].channels = ucontrol->value.enumerated.item[0] + 1;
2392 pr_debug("%s: msm_mi2s_[%d]_rx_ch = %d\n", __func__,
2393 idx, mi2s_rx_cfg[idx].channels);
2394
2395 return 1;
2396}
2397
2398static int msm_mi2s_tx_ch_get(struct snd_kcontrol *kcontrol,
2399 struct snd_ctl_elem_value *ucontrol)
2400{
2401 int idx = mi2s_get_port_idx(kcontrol);
2402
2403 if (idx < 0)
2404 return idx;
2405
2406 pr_debug("%s: msm_mi2s_[%d]_tx_ch = %d\n", __func__,
2407 idx, mi2s_tx_cfg[idx].channels);
2408 ucontrol->value.enumerated.item[0] = mi2s_tx_cfg[idx].channels - 1;
2409
2410 return 0;
2411}
2412
2413static int msm_mi2s_tx_ch_put(struct snd_kcontrol *kcontrol,
2414 struct snd_ctl_elem_value *ucontrol)
2415{
2416 int idx = mi2s_get_port_idx(kcontrol);
2417
2418 if (idx < 0)
2419 return idx;
2420
2421 mi2s_tx_cfg[idx].channels = ucontrol->value.enumerated.item[0] + 1;
2422 pr_debug("%s: msm_mi2s_[%d]_tx_ch = %d\n", __func__,
2423 idx, mi2s_tx_cfg[idx].channels);
2424
2425 return 1;
2426}
2427
2428static int usb_audio_rx_ch_get(struct snd_kcontrol *kcontrol,
2429 struct snd_ctl_elem_value *ucontrol)
2430{
2431 pr_debug("%s: usb_audio_rx_ch = %d\n", __func__,
2432 usb_rx_cfg.channels);
2433 ucontrol->value.integer.value[0] = usb_rx_cfg.channels - 1;
2434 return 0;
2435}
2436
2437static int usb_audio_rx_ch_put(struct snd_kcontrol *kcontrol,
2438 struct snd_ctl_elem_value *ucontrol)
2439{
2440 usb_rx_cfg.channels = ucontrol->value.integer.value[0] + 1;
2441
2442 pr_debug("%s: usb_audio_rx_ch = %d\n", __func__, usb_rx_cfg.channels);
2443 return 1;
2444}
2445
2446static int usb_audio_rx_sample_rate_get(struct snd_kcontrol *kcontrol,
2447 struct snd_ctl_elem_value *ucontrol)
2448{
2449 int sample_rate_val;
2450
2451 switch (usb_rx_cfg.sample_rate) {
2452 case SAMPLING_RATE_384KHZ:
2453 sample_rate_val = 9;
2454 break;
2455 case SAMPLING_RATE_192KHZ:
2456 sample_rate_val = 8;
2457 break;
2458 case SAMPLING_RATE_96KHZ:
2459 sample_rate_val = 7;
2460 break;
2461 case SAMPLING_RATE_48KHZ:
2462 sample_rate_val = 6;
2463 break;
2464 case SAMPLING_RATE_44P1KHZ:
2465 sample_rate_val = 5;
2466 break;
2467 case SAMPLING_RATE_32KHZ:
2468 sample_rate_val = 4;
2469 break;
2470 case SAMPLING_RATE_22P05KHZ:
2471 sample_rate_val = 3;
2472 break;
2473 case SAMPLING_RATE_16KHZ:
2474 sample_rate_val = 2;
2475 break;
2476 case SAMPLING_RATE_11P025KHZ:
2477 sample_rate_val = 1;
2478 break;
2479 case SAMPLING_RATE_8KHZ:
2480 default:
2481 sample_rate_val = 0;
2482 break;
2483 }
2484
2485 ucontrol->value.integer.value[0] = sample_rate_val;
2486 pr_debug("%s: usb_audio_rx_sample_rate = %d\n", __func__,
2487 usb_rx_cfg.sample_rate);
2488 return 0;
2489}
2490
2491static int usb_audio_rx_sample_rate_put(struct snd_kcontrol *kcontrol,
2492 struct snd_ctl_elem_value *ucontrol)
2493{
2494 switch (ucontrol->value.integer.value[0]) {
2495 case 9:
2496 usb_rx_cfg.sample_rate = SAMPLING_RATE_384KHZ;
2497 break;
2498 case 8:
2499 usb_rx_cfg.sample_rate = SAMPLING_RATE_192KHZ;
2500 break;
2501 case 7:
2502 usb_rx_cfg.sample_rate = SAMPLING_RATE_96KHZ;
2503 break;
2504 case 6:
2505 usb_rx_cfg.sample_rate = SAMPLING_RATE_48KHZ;
2506 break;
2507 case 5:
2508 usb_rx_cfg.sample_rate = SAMPLING_RATE_44P1KHZ;
2509 break;
2510 case 4:
2511 usb_rx_cfg.sample_rate = SAMPLING_RATE_32KHZ;
2512 break;
2513 case 3:
2514 usb_rx_cfg.sample_rate = SAMPLING_RATE_22P05KHZ;
2515 break;
2516 case 2:
2517 usb_rx_cfg.sample_rate = SAMPLING_RATE_16KHZ;
2518 break;
2519 case 1:
2520 usb_rx_cfg.sample_rate = SAMPLING_RATE_11P025KHZ;
2521 break;
2522 case 0:
2523 usb_rx_cfg.sample_rate = SAMPLING_RATE_8KHZ;
2524 break;
2525 default:
2526 usb_rx_cfg.sample_rate = SAMPLING_RATE_48KHZ;
2527 break;
2528 }
2529
2530 pr_debug("%s: control value = %ld, usb_audio_rx_sample_rate = %d\n",
2531 __func__, ucontrol->value.integer.value[0],
2532 usb_rx_cfg.sample_rate);
2533 return 0;
2534}
2535
2536static int usb_audio_rx_format_get(struct snd_kcontrol *kcontrol,
2537 struct snd_ctl_elem_value *ucontrol)
2538{
2539 switch (usb_rx_cfg.bit_format) {
2540 case SNDRV_PCM_FORMAT_S32_LE:
2541 ucontrol->value.integer.value[0] = 3;
2542 break;
2543 case SNDRV_PCM_FORMAT_S24_3LE:
2544 ucontrol->value.integer.value[0] = 2;
2545 break;
2546 case SNDRV_PCM_FORMAT_S24_LE:
2547 ucontrol->value.integer.value[0] = 1;
2548 break;
2549 case SNDRV_PCM_FORMAT_S16_LE:
2550 default:
2551 ucontrol->value.integer.value[0] = 0;
2552 break;
2553 }
2554
2555 pr_debug("%s: usb_audio_rx_format = %d, ucontrol value = %ld\n",
2556 __func__, usb_rx_cfg.bit_format,
2557 ucontrol->value.integer.value[0]);
2558 return 0;
2559}
2560
2561static int usb_audio_rx_format_put(struct snd_kcontrol *kcontrol,
2562 struct snd_ctl_elem_value *ucontrol)
2563{
2564 int rc = 0;
2565
2566 switch (ucontrol->value.integer.value[0]) {
2567 case 3:
2568 usb_rx_cfg.bit_format = SNDRV_PCM_FORMAT_S32_LE;
2569 break;
2570 case 2:
2571 usb_rx_cfg.bit_format = SNDRV_PCM_FORMAT_S24_3LE;
2572 break;
2573 case 1:
2574 usb_rx_cfg.bit_format = SNDRV_PCM_FORMAT_S24_LE;
2575 break;
2576 case 0:
2577 default:
2578 usb_rx_cfg.bit_format = SNDRV_PCM_FORMAT_S16_LE;
2579 break;
2580 }
2581 pr_debug("%s: usb_audio_rx_format = %d, ucontrol value = %ld\n",
2582 __func__, usb_rx_cfg.bit_format,
2583 ucontrol->value.integer.value[0]);
2584
2585 return rc;
2586}
2587
2588static int usb_audio_tx_ch_get(struct snd_kcontrol *kcontrol,
2589 struct snd_ctl_elem_value *ucontrol)
2590{
2591 pr_debug("%s: usb_audio_tx_ch = %d\n", __func__,
2592 usb_tx_cfg.channels);
2593 ucontrol->value.integer.value[0] = usb_tx_cfg.channels - 1;
2594 return 0;
2595}
2596
2597static int usb_audio_tx_ch_put(struct snd_kcontrol *kcontrol,
2598 struct snd_ctl_elem_value *ucontrol)
2599{
2600 usb_tx_cfg.channels = ucontrol->value.integer.value[0] + 1;
2601
2602 pr_debug("%s: usb_audio_tx_ch = %d\n", __func__, usb_tx_cfg.channels);
2603 return 1;
2604}
2605
2606static int usb_audio_tx_sample_rate_get(struct snd_kcontrol *kcontrol,
2607 struct snd_ctl_elem_value *ucontrol)
2608{
2609 int sample_rate_val;
2610
2611 switch (usb_tx_cfg.sample_rate) {
2612 case SAMPLING_RATE_384KHZ:
2613 sample_rate_val = 9;
2614 break;
2615 case SAMPLING_RATE_192KHZ:
2616 sample_rate_val = 8;
2617 break;
2618 case SAMPLING_RATE_96KHZ:
2619 sample_rate_val = 7;
2620 break;
2621 case SAMPLING_RATE_48KHZ:
2622 sample_rate_val = 6;
2623 break;
2624 case SAMPLING_RATE_44P1KHZ:
2625 sample_rate_val = 5;
2626 break;
2627 case SAMPLING_RATE_32KHZ:
2628 sample_rate_val = 4;
2629 break;
2630 case SAMPLING_RATE_22P05KHZ:
2631 sample_rate_val = 3;
2632 break;
2633 case SAMPLING_RATE_16KHZ:
2634 sample_rate_val = 2;
2635 break;
2636 case SAMPLING_RATE_11P025KHZ:
2637 sample_rate_val = 1;
2638 break;
2639 case SAMPLING_RATE_8KHZ:
2640 sample_rate_val = 0;
2641 break;
2642 default:
2643 sample_rate_val = 6;
2644 break;
2645 }
2646
2647 ucontrol->value.integer.value[0] = sample_rate_val;
2648 pr_debug("%s: usb_audio_tx_sample_rate = %d\n", __func__,
2649 usb_tx_cfg.sample_rate);
2650 return 0;
2651}
2652
2653static int usb_audio_tx_sample_rate_put(struct snd_kcontrol *kcontrol,
2654 struct snd_ctl_elem_value *ucontrol)
2655{
2656 switch (ucontrol->value.integer.value[0]) {
2657 case 9:
2658 usb_tx_cfg.sample_rate = SAMPLING_RATE_384KHZ;
2659 break;
2660 case 8:
2661 usb_tx_cfg.sample_rate = SAMPLING_RATE_192KHZ;
2662 break;
2663 case 7:
2664 usb_tx_cfg.sample_rate = SAMPLING_RATE_96KHZ;
2665 break;
2666 case 6:
2667 usb_tx_cfg.sample_rate = SAMPLING_RATE_48KHZ;
2668 break;
2669 case 5:
2670 usb_tx_cfg.sample_rate = SAMPLING_RATE_44P1KHZ;
2671 break;
2672 case 4:
2673 usb_tx_cfg.sample_rate = SAMPLING_RATE_32KHZ;
2674 break;
2675 case 3:
2676 usb_tx_cfg.sample_rate = SAMPLING_RATE_22P05KHZ;
2677 break;
2678 case 2:
2679 usb_tx_cfg.sample_rate = SAMPLING_RATE_16KHZ;
2680 break;
2681 case 1:
2682 usb_tx_cfg.sample_rate = SAMPLING_RATE_11P025KHZ;
2683 break;
2684 case 0:
2685 usb_tx_cfg.sample_rate = SAMPLING_RATE_8KHZ;
2686 break;
2687 default:
2688 usb_tx_cfg.sample_rate = SAMPLING_RATE_48KHZ;
2689 break;
2690 }
2691
2692 pr_debug("%s: control value = %ld, usb_audio_tx_sample_rate = %d\n",
2693 __func__, ucontrol->value.integer.value[0],
2694 usb_tx_cfg.sample_rate);
2695 return 0;
2696}
2697
2698static int usb_audio_tx_format_get(struct snd_kcontrol *kcontrol,
2699 struct snd_ctl_elem_value *ucontrol)
2700{
2701 switch (usb_tx_cfg.bit_format) {
2702 case SNDRV_PCM_FORMAT_S32_LE:
2703 ucontrol->value.integer.value[0] = 3;
2704 break;
2705 case SNDRV_PCM_FORMAT_S24_3LE:
2706 ucontrol->value.integer.value[0] = 2;
2707 break;
2708 case SNDRV_PCM_FORMAT_S24_LE:
2709 ucontrol->value.integer.value[0] = 1;
2710 break;
2711 case SNDRV_PCM_FORMAT_S16_LE:
2712 default:
2713 ucontrol->value.integer.value[0] = 0;
2714 break;
2715 }
2716
2717 pr_debug("%s: usb_audio_tx_format = %d, ucontrol value = %ld\n",
2718 __func__, usb_tx_cfg.bit_format,
2719 ucontrol->value.integer.value[0]);
2720 return 0;
2721}
2722
2723static int usb_audio_tx_format_put(struct snd_kcontrol *kcontrol,
2724 struct snd_ctl_elem_value *ucontrol)
2725{
2726 int rc = 0;
2727
2728 switch (ucontrol->value.integer.value[0]) {
2729 case 3:
2730 usb_tx_cfg.bit_format = SNDRV_PCM_FORMAT_S32_LE;
2731 break;
2732 case 2:
2733 usb_tx_cfg.bit_format = SNDRV_PCM_FORMAT_S24_3LE;
2734 break;
2735 case 1:
2736 usb_tx_cfg.bit_format = SNDRV_PCM_FORMAT_S24_LE;
2737 break;
2738 case 0:
2739 default:
2740 usb_tx_cfg.bit_format = SNDRV_PCM_FORMAT_S16_LE;
2741 break;
2742 }
2743 pr_debug("%s: usb_audio_tx_format = %d, ucontrol value = %ld\n",
2744 __func__, usb_tx_cfg.bit_format,
2745 ucontrol->value.integer.value[0]);
2746
2747 return rc;
2748}
2749
2750static int ext_disp_get_port_idx(struct snd_kcontrol *kcontrol)
2751{
2752 int idx;
2753
2754 if (strnstr(kcontrol->id.name, "Display Port RX",
2755 sizeof("Display Port RX")))
2756 idx = DP_RX_IDX;
2757 else {
2758 pr_err("%s: unsupported BE: %s",
2759 __func__, kcontrol->id.name);
2760 idx = -EINVAL;
2761 }
2762
2763 return idx;
2764}
2765
2766static int ext_disp_rx_format_get(struct snd_kcontrol *kcontrol,
2767 struct snd_ctl_elem_value *ucontrol)
2768{
2769 int idx = ext_disp_get_port_idx(kcontrol);
2770
2771 if (idx < 0)
2772 return idx;
2773
2774 switch (ext_disp_rx_cfg[idx].bit_format) {
2775 case SNDRV_PCM_FORMAT_S24_LE:
2776 ucontrol->value.integer.value[0] = 1;
2777 break;
2778
2779 case SNDRV_PCM_FORMAT_S16_LE:
2780 default:
2781 ucontrol->value.integer.value[0] = 0;
2782 break;
2783 }
2784
2785 pr_debug("%s: ext_disp_rx[%d].format = %d, ucontrol value = %ld\n",
2786 __func__, idx, ext_disp_rx_cfg[idx].bit_format,
2787 ucontrol->value.integer.value[0]);
2788 return 0;
2789}
2790
2791static int ext_disp_rx_format_put(struct snd_kcontrol *kcontrol,
2792 struct snd_ctl_elem_value *ucontrol)
2793{
2794 int idx = ext_disp_get_port_idx(kcontrol);
2795
2796 if (idx < 0)
2797 return idx;
2798
2799 switch (ucontrol->value.integer.value[0]) {
2800 case 1:
2801 ext_disp_rx_cfg[idx].bit_format = SNDRV_PCM_FORMAT_S24_LE;
2802 break;
2803 case 0:
2804 default:
2805 ext_disp_rx_cfg[idx].bit_format = SNDRV_PCM_FORMAT_S16_LE;
2806 break;
2807 }
2808 pr_debug("%s: ext_disp_rx[%d].format = %d, ucontrol value = %ld\n",
2809 __func__, idx, ext_disp_rx_cfg[idx].bit_format,
2810 ucontrol->value.integer.value[0]);
2811
2812 return 0;
2813}
2814
2815static int ext_disp_rx_ch_get(struct snd_kcontrol *kcontrol,
2816 struct snd_ctl_elem_value *ucontrol)
2817{
2818 int idx = ext_disp_get_port_idx(kcontrol);
2819
2820 if (idx < 0)
2821 return idx;
2822
2823 ucontrol->value.integer.value[0] =
2824 ext_disp_rx_cfg[idx].channels - 2;
2825
2826 pr_debug("%s: ext_disp_rx[%d].ch = %d\n", __func__,
2827 idx, ext_disp_rx_cfg[idx].channels);
2828
2829 return 0;
2830}
2831
2832static int ext_disp_rx_ch_put(struct snd_kcontrol *kcontrol,
2833 struct snd_ctl_elem_value *ucontrol)
2834{
2835 int idx = ext_disp_get_port_idx(kcontrol);
2836
2837 if (idx < 0)
2838 return idx;
2839
2840 ext_disp_rx_cfg[idx].channels =
2841 ucontrol->value.integer.value[0] + 2;
2842
2843 pr_debug("%s: ext_disp_rx[%d].ch = %d\n", __func__,
2844 idx, ext_disp_rx_cfg[idx].channels);
2845 return 1;
2846}
2847
2848static int ext_disp_rx_sample_rate_get(struct snd_kcontrol *kcontrol,
2849 struct snd_ctl_elem_value *ucontrol)
2850{
2851 int sample_rate_val;
2852 int idx = ext_disp_get_port_idx(kcontrol);
2853
2854 if (idx < 0)
2855 return idx;
2856
2857 switch (ext_disp_rx_cfg[idx].sample_rate) {
2858 case SAMPLING_RATE_192KHZ:
2859 sample_rate_val = 2;
2860 break;
2861
2862 case SAMPLING_RATE_96KHZ:
2863 sample_rate_val = 1;
2864 break;
2865
2866 case SAMPLING_RATE_48KHZ:
2867 default:
2868 sample_rate_val = 0;
2869 break;
2870 }
2871
2872 ucontrol->value.integer.value[0] = sample_rate_val;
2873 pr_debug("%s: ext_disp_rx[%d].sample_rate = %d\n", __func__,
2874 idx, ext_disp_rx_cfg[idx].sample_rate);
2875
2876 return 0;
2877}
2878
2879static int ext_disp_rx_sample_rate_put(struct snd_kcontrol *kcontrol,
2880 struct snd_ctl_elem_value *ucontrol)
2881{
2882 int idx = ext_disp_get_port_idx(kcontrol);
2883
2884 if (idx < 0)
2885 return idx;
2886
2887 switch (ucontrol->value.integer.value[0]) {
2888 case 2:
2889 ext_disp_rx_cfg[idx].sample_rate = SAMPLING_RATE_192KHZ;
2890 break;
2891 case 1:
2892 ext_disp_rx_cfg[idx].sample_rate = SAMPLING_RATE_96KHZ;
2893 break;
2894 case 0:
2895 default:
2896 ext_disp_rx_cfg[idx].sample_rate = SAMPLING_RATE_48KHZ;
2897 break;
2898 }
2899
2900 pr_debug("%s: control value = %ld, ext_disp_rx[%d].sample_rate = %d\n",
2901 __func__, ucontrol->value.integer.value[0], idx,
2902 ext_disp_rx_cfg[idx].sample_rate);
2903 return 0;
2904}
2905
Revathi Uddaraju30feb0d2017-11-21 15:30:19 +0530[diff] [blame]2906static int msm_qos_ctl_get(struct snd_kcontrol *kcontrol,
2907 struct snd_ctl_elem_value *ucontrol)
2908{
2909 ucontrol->value.enumerated.item[0] = qos_vote_status;
2910
2911 return 0;
2912}
2913
2914static int msm_qos_ctl_put(struct snd_kcontrol *kcontrol,
2915 struct snd_ctl_elem_value *ucontrol)
2916{
2917 struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
2918 struct snd_soc_card *card = codec->component.card;
2919 const char *fe_name = MSM_DAILINK_NAME(LowLatency);
2920 struct snd_soc_pcm_runtime *rtd;
2921 struct snd_pcm_substream *substream;
2922 s32 usecs;
2923
2924 rtd = snd_soc_get_pcm_runtime(card, fe_name);
2925 if (!rtd) {
2926 pr_err("%s: fail to get pcm runtime for %s\n",
2927 __func__, fe_name);
2928 return -EINVAL;
2929 }
2930
2931 substream = rtd->pcm->streams[SNDRV_PCM_STREAM_PLAYBACK].substream;
2932 if (!substream) {
2933 pr_err("%s: substream is null\n", __func__);
2934 return -EINVAL;
2935 }
2936
2937 qos_vote_status = ucontrol->value.enumerated.item[0];
2938 if (qos_vote_status) {
2939 if (pm_qos_request_active(&substream->latency_pm_qos_req))
2940 pm_qos_remove_request(&substream->latency_pm_qos_req);
2941 if (!substream->runtime) {
2942 pr_err("%s: runtime is null\n", __func__);
2943 return -EINVAL;
2944 }
2945 usecs = MSM_LL_QOS_VALUE;
2946 if (usecs >= 0)
2947 pm_qos_add_request(&substream->latency_pm_qos_req,
2948 PM_QOS_CPU_DMA_LATENCY, usecs);
2949 } else {
2950 if (pm_qos_request_active(&substream->latency_pm_qos_req))
2951 pm_qos_remove_request(&substream->latency_pm_qos_req);
2952 }
2953
2954 return 0;
2955}
2956
Asish Bhattacharya8e2277f2017-07-20 18:31:55 +0530[diff] [blame]2957const struct snd_kcontrol_new msm_common_snd_controls[] = {
2958 SOC_ENUM_EXT("PROXY_RX Channels", proxy_rx_chs,
2959 proxy_rx_ch_get, proxy_rx_ch_put),
2960 SOC_ENUM_EXT("PRIM_AUX_PCM_RX SampleRate", prim_aux_pcm_rx_sample_rate,
2961 aux_pcm_rx_sample_rate_get,
2962 aux_pcm_rx_sample_rate_put),
2963 SOC_ENUM_EXT("SEC_AUX_PCM_RX SampleRate", sec_aux_pcm_rx_sample_rate,
2964 aux_pcm_rx_sample_rate_get,
2965 aux_pcm_rx_sample_rate_put),
2966 SOC_ENUM_EXT("TERT_AUX_PCM_RX SampleRate", tert_aux_pcm_rx_sample_rate,
2967 aux_pcm_rx_sample_rate_get,
2968 aux_pcm_rx_sample_rate_put),
2969 SOC_ENUM_EXT("QUAT_AUX_PCM_RX SampleRate", quat_aux_pcm_rx_sample_rate,
2970 aux_pcm_rx_sample_rate_get,
2971 aux_pcm_rx_sample_rate_put),
Rohit Kumard1754482017-09-10 22:57:39 +0530[diff] [blame]2972 SOC_ENUM_EXT("QUIN_AUX_PCM_RX SampleRate", quin_aux_pcm_rx_sample_rate,
2973 aux_pcm_rx_sample_rate_get,
2974 aux_pcm_rx_sample_rate_put),
Asish Bhattacharya8e2277f2017-07-20 18:31:55 +0530[diff] [blame]2975 SOC_ENUM_EXT("PRIM_AUX_PCM_TX SampleRate", prim_aux_pcm_tx_sample_rate,
2976 aux_pcm_tx_sample_rate_get,
2977 aux_pcm_tx_sample_rate_put),
2978 SOC_ENUM_EXT("SEC_AUX_PCM_TX SampleRate", sec_aux_pcm_tx_sample_rate,
2979 aux_pcm_tx_sample_rate_get,
2980 aux_pcm_tx_sample_rate_put),
2981 SOC_ENUM_EXT("TERT_AUX_PCM_TX SampleRate", tert_aux_pcm_tx_sample_rate,
2982 aux_pcm_tx_sample_rate_get,
2983 aux_pcm_tx_sample_rate_put),
2984 SOC_ENUM_EXT("QUAT_AUX_PCM_TX SampleRate", quat_aux_pcm_tx_sample_rate,
2985 aux_pcm_tx_sample_rate_get,
2986 aux_pcm_tx_sample_rate_put),
Rohit Kumard1754482017-09-10 22:57:39 +0530[diff] [blame]2987 SOC_ENUM_EXT("QUIN_AUX_PCM_TX SampleRate", quin_aux_pcm_tx_sample_rate,
2988 aux_pcm_tx_sample_rate_get,
2989 aux_pcm_tx_sample_rate_put),
Asish Bhattacharya8e2277f2017-07-20 18:31:55 +0530[diff] [blame]2990 SOC_ENUM_EXT("PRIM_MI2S_RX SampleRate", prim_mi2s_rx_sample_rate,
2991 mi2s_rx_sample_rate_get,
2992 mi2s_rx_sample_rate_put),
2993 SOC_ENUM_EXT("SEC_MI2S_RX SampleRate", sec_mi2s_rx_sample_rate,
2994 mi2s_rx_sample_rate_get,
2995 mi2s_rx_sample_rate_put),
2996 SOC_ENUM_EXT("TERT_MI2S_RX SampleRate", tert_mi2s_rx_sample_rate,
2997 mi2s_rx_sample_rate_get,
2998 mi2s_rx_sample_rate_put),
2999 SOC_ENUM_EXT("QUAT_MI2S_RX SampleRate", quat_mi2s_rx_sample_rate,
3000 mi2s_rx_sample_rate_get,
3001 mi2s_rx_sample_rate_put),
Rohit Kumard1754482017-09-10 22:57:39 +0530[diff] [blame]3002 SOC_ENUM_EXT("QUIN_MI2S_RX SampleRate", quin_mi2s_rx_sample_rate,
3003 mi2s_rx_sample_rate_get,
3004 mi2s_rx_sample_rate_put),
Asish Bhattacharya8e2277f2017-07-20 18:31:55 +0530[diff] [blame]3005 SOC_ENUM_EXT("PRIM_MI2S_TX SampleRate", prim_mi2s_tx_sample_rate,
3006 mi2s_tx_sample_rate_get,
3007 mi2s_tx_sample_rate_put),
3008 SOC_ENUM_EXT("SEC_MI2S_TX SampleRate", sec_mi2s_tx_sample_rate,
3009 mi2s_tx_sample_rate_get,
3010 mi2s_tx_sample_rate_put),
3011 SOC_ENUM_EXT("TERT_MI2S_TX SampleRate", tert_mi2s_tx_sample_rate,
3012 mi2s_tx_sample_rate_get,
3013 mi2s_tx_sample_rate_put),
3014 SOC_ENUM_EXT("QUAT_MI2S_TX SampleRate", quat_mi2s_tx_sample_rate,
3015 mi2s_tx_sample_rate_get,
3016 mi2s_tx_sample_rate_put),
Rohit Kumard1754482017-09-10 22:57:39 +0530[diff] [blame]3017 SOC_ENUM_EXT("QUIN_MI2S_TX SampleRate", quin_mi2s_tx_sample_rate,
3018 mi2s_tx_sample_rate_get,
3019 mi2s_tx_sample_rate_put),
Asish Bhattacharya8e2277f2017-07-20 18:31:55 +0530[diff] [blame]3020 SOC_ENUM_EXT("PRIM_MI2S_RX Format", prim_mi2s_rx_format,
3021 mi2s_rx_format_get,
3022 mi2s_rx_format_put),
3023 SOC_ENUM_EXT("SEC_MI2S_RX Format", sec_mi2s_rx_format,
3024 mi2s_rx_format_get,
3025 mi2s_rx_format_put),
3026 SOC_ENUM_EXT("TERT_MI2S_RX Format", tert_mi2s_rx_format,
3027 mi2s_rx_format_get,
3028 mi2s_rx_format_put),
3029 SOC_ENUM_EXT("QUAT_MI2S_RX Format", quat_mi2s_rx_format,
3030 mi2s_rx_format_get,
3031 mi2s_rx_format_put),
Rohit Kumard1754482017-09-10 22:57:39 +0530[diff] [blame]3032 SOC_ENUM_EXT("QUIN_MI2S_RX Format", quin_mi2s_rx_format,
3033 mi2s_rx_format_get,
3034 mi2s_rx_format_put),
Asish Bhattacharya8e2277f2017-07-20 18:31:55 +0530[diff] [blame]3035 SOC_ENUM_EXT("PRIM_MI2S_TX Format", prim_mi2s_tx_format,
3036 mi2s_tx_format_get,
3037 mi2s_tx_format_put),
3038 SOC_ENUM_EXT("SEC_MI2S_TX Format", sec_mi2s_tx_format,
3039 mi2s_tx_format_get,
3040 mi2s_tx_format_put),
3041 SOC_ENUM_EXT("TERT_MI2S_TX Format", tert_mi2s_tx_format,
3042 mi2s_tx_format_get,
3043 mi2s_tx_format_put),
3044 SOC_ENUM_EXT("QUAT_MI2S_TX Format", quat_mi2s_tx_format,
3045 mi2s_tx_format_get,
3046 mi2s_tx_format_put),
Rohit Kumard1754482017-09-10 22:57:39 +0530[diff] [blame]3047 SOC_ENUM_EXT("QUIN_MI2S_TX Format", quin_mi2s_tx_format,
3048 mi2s_tx_format_get,
3049 mi2s_tx_format_put),
Asish Bhattacharya8e2277f2017-07-20 18:31:55 +0530[diff] [blame]3050 SOC_ENUM_EXT("PRIM_MI2S_RX Channels", prim_mi2s_rx_chs,
3051 msm_mi2s_rx_ch_get, msm_mi2s_rx_ch_put),
3052 SOC_ENUM_EXT("PRIM_MI2S_TX Channels", prim_mi2s_tx_chs,
3053 msm_mi2s_tx_ch_get, msm_mi2s_tx_ch_put),
3054 SOC_ENUM_EXT("SEC_MI2S_RX Channels", sec_mi2s_rx_chs,
3055 msm_mi2s_rx_ch_get, msm_mi2s_rx_ch_put),
3056 SOC_ENUM_EXT("SEC_MI2S_TX Channels", sec_mi2s_tx_chs,
3057 msm_mi2s_tx_ch_get, msm_mi2s_tx_ch_put),
3058 SOC_ENUM_EXT("TERT_MI2S_RX Channels", tert_mi2s_rx_chs,
3059 msm_mi2s_rx_ch_get, msm_mi2s_rx_ch_put),
3060 SOC_ENUM_EXT("TERT_MI2S_TX Channels", tert_mi2s_tx_chs,
3061 msm_mi2s_tx_ch_get, msm_mi2s_tx_ch_put),
3062 SOC_ENUM_EXT("QUAT_MI2S_RX Channels", quat_mi2s_rx_chs,
3063 msm_mi2s_rx_ch_get, msm_mi2s_rx_ch_put),
3064 SOC_ENUM_EXT("QUAT_MI2S_TX Channels", quat_mi2s_tx_chs,
3065 msm_mi2s_tx_ch_get, msm_mi2s_tx_ch_put),
Rohit Kumard1754482017-09-10 22:57:39 +0530[diff] [blame]3066 SOC_ENUM_EXT("QUIN_MI2S_RX Channels", quin_mi2s_rx_chs,
3067 msm_mi2s_rx_ch_get, msm_mi2s_rx_ch_put),
3068 SOC_ENUM_EXT("QUIN_MI2S_TX Channels", quin_mi2s_tx_chs,
3069 msm_mi2s_tx_ch_get, msm_mi2s_tx_ch_put),
Asish Bhattacharya8e2277f2017-07-20 18:31:55 +0530[diff] [blame]3070 SOC_ENUM_EXT("USB_AUDIO_RX Channels", usb_rx_chs,
3071 usb_audio_rx_ch_get, usb_audio_rx_ch_put),
3072 SOC_ENUM_EXT("USB_AUDIO_TX Channels", usb_tx_chs,
3073 usb_audio_tx_ch_get, usb_audio_tx_ch_put),
3074 SOC_ENUM_EXT("Display Port RX Channels", ext_disp_rx_chs,
3075 ext_disp_rx_ch_get, ext_disp_rx_ch_put),
3076 SOC_ENUM_EXT("USB_AUDIO_RX Format", usb_rx_format,
3077 usb_audio_rx_format_get, usb_audio_rx_format_put),
3078 SOC_ENUM_EXT("USB_AUDIO_TX Format", usb_tx_format,
3079 usb_audio_tx_format_get, usb_audio_tx_format_put),
3080 SOC_ENUM_EXT("Display Port RX Bit Format", ext_disp_rx_format,
3081 ext_disp_rx_format_get, ext_disp_rx_format_put),
3082 SOC_ENUM_EXT("USB_AUDIO_RX SampleRate", usb_rx_sample_rate,
3083 usb_audio_rx_sample_rate_get,
3084 usb_audio_rx_sample_rate_put),
3085 SOC_ENUM_EXT("USB_AUDIO_TX SampleRate", usb_tx_sample_rate,
3086 usb_audio_tx_sample_rate_get,
3087 usb_audio_tx_sample_rate_put),
3088 SOC_ENUM_EXT("Display Port RX SampleRate", ext_disp_rx_sample_rate,
3089 ext_disp_rx_sample_rate_get,
3090 ext_disp_rx_sample_rate_put),
3091 SOC_ENUM_EXT("PRI_TDM_RX_0 SampleRate", tdm_rx_sample_rate,
3092 tdm_rx_sample_rate_get,
3093 tdm_rx_sample_rate_put),
3094 SOC_ENUM_EXT("PRI_TDM_TX_0 SampleRate", tdm_tx_sample_rate,
3095 tdm_tx_sample_rate_get,
3096 tdm_tx_sample_rate_put),
3097 SOC_ENUM_EXT("PRI_TDM_RX_0 Format", tdm_rx_format,
3098 tdm_rx_format_get,
3099 tdm_rx_format_put),
3100 SOC_ENUM_EXT("PRI_TDM_TX_0 Format", tdm_tx_format,
3101 tdm_tx_format_get,
3102 tdm_tx_format_put),
3103 SOC_ENUM_EXT("PRI_TDM_RX_0 Channels", tdm_rx_chs,
3104 tdm_rx_ch_get,
3105 tdm_rx_ch_put),
3106 SOC_ENUM_EXT("PRI_TDM_TX_0 Channels", tdm_tx_chs,
3107 tdm_tx_ch_get,
3108 tdm_tx_ch_put),
3109 SOC_ENUM_EXT("SEC_TDM_RX_0 SampleRate", tdm_rx_sample_rate,
3110 tdm_rx_sample_rate_get,
3111 tdm_rx_sample_rate_put),
3112 SOC_ENUM_EXT("SEC_TDM_TX_0 SampleRate", tdm_tx_sample_rate,
3113 tdm_tx_sample_rate_get,
3114 tdm_tx_sample_rate_put),
3115 SOC_ENUM_EXT("SEC_TDM_RX_0 Format", tdm_rx_format,
3116 tdm_rx_format_get,
3117 tdm_rx_format_put),
3118 SOC_ENUM_EXT("SEC_TDM_TX_0 Format", tdm_tx_format,
3119 tdm_tx_format_get,
3120 tdm_tx_format_put),
3121 SOC_ENUM_EXT("SEC_TDM_RX_0 Channels", tdm_rx_chs,
3122 tdm_rx_ch_get,
3123 tdm_rx_ch_put),
3124 SOC_ENUM_EXT("SEC_TDM_TX_0 Channels", tdm_tx_chs,
3125 tdm_tx_ch_get,
3126 tdm_tx_ch_put),
3127 SOC_ENUM_EXT("TERT_TDM_RX_0 SampleRate", tdm_rx_sample_rate,
3128 tdm_rx_sample_rate_get,
3129 tdm_rx_sample_rate_put),
3130 SOC_ENUM_EXT("TERT_TDM_TX_0 SampleRate", tdm_tx_sample_rate,
3131 tdm_tx_sample_rate_get,
3132 tdm_tx_sample_rate_put),
3133 SOC_ENUM_EXT("TERT_TDM_RX_0 Format", tdm_rx_format,
3134 tdm_rx_format_get,
3135 tdm_rx_format_put),
3136 SOC_ENUM_EXT("TERT_TDM_TX_0 Format", tdm_tx_format,
3137 tdm_tx_format_get,
3138 tdm_tx_format_put),
3139 SOC_ENUM_EXT("TERT_TDM_RX_0 Channels", tdm_rx_chs,
3140 tdm_rx_ch_get,
3141 tdm_rx_ch_put),
3142 SOC_ENUM_EXT("TERT_TDM_TX_0 Channels", tdm_tx_chs,
3143 tdm_tx_ch_get,
3144 tdm_tx_ch_put),
3145 SOC_ENUM_EXT("QUAT_TDM_RX_0 SampleRate", tdm_rx_sample_rate,
3146 tdm_rx_sample_rate_get,
3147 tdm_rx_sample_rate_put),
3148 SOC_ENUM_EXT("QUAT_TDM_TX_0 SampleRate", tdm_tx_sample_rate,
3149 tdm_tx_sample_rate_get,
3150 tdm_tx_sample_rate_put),
3151 SOC_ENUM_EXT("QUAT_TDM_RX_0 Format", tdm_rx_format,
3152 tdm_rx_format_get,
3153 tdm_rx_format_put),
3154 SOC_ENUM_EXT("QUAT_TDM_TX_0 Format", tdm_tx_format,
3155 tdm_tx_format_get,
3156 tdm_tx_format_put),
3157 SOC_ENUM_EXT("QUAT_TDM_RX_0 Channels", tdm_rx_chs,
3158 tdm_rx_ch_get,
3159 tdm_rx_ch_put),
3160 SOC_ENUM_EXT("QUAT_TDM_TX_0 Channels", tdm_tx_chs,
3161 tdm_tx_ch_get,
3162 tdm_tx_ch_put),
Rohit Kumard1754482017-09-10 22:57:39 +0530[diff] [blame]3163 SOC_ENUM_EXT("QUIN_TDM_RX_0 SampleRate", tdm_rx_sample_rate,
3164 tdm_rx_sample_rate_get,
3165 tdm_rx_sample_rate_put),
3166 SOC_ENUM_EXT("QUIN_TDM_TX_0 SampleRate", tdm_tx_sample_rate,
3167 tdm_tx_sample_rate_get,
3168 tdm_tx_sample_rate_put),
3169 SOC_ENUM_EXT("QUIN_TDM_RX_0 Format", tdm_rx_format,
3170 tdm_rx_format_get,
3171 tdm_rx_format_put),
3172 SOC_ENUM_EXT("QUIN_TDM_TX_0 Format", tdm_tx_format,
3173 tdm_tx_format_get,
3174 tdm_tx_format_put),
3175 SOC_ENUM_EXT("QUIN_TDM_RX_0 Channels", tdm_rx_chs,
3176 tdm_rx_ch_get,
3177 tdm_rx_ch_put),
3178 SOC_ENUM_EXT("QUIN_TDM_TX_0 Channels", tdm_tx_chs,
3179 tdm_tx_ch_get,
3180 tdm_tx_ch_put),
Dhanalakshmi Siddanid70a4f72019-11-27 15:35:41 +0530[diff] [blame]3181 SOC_ENUM_EXT("PRI_TDM SlotNumber", tdm_slot_num,
3182 tdm_slot_num_get, tdm_slot_num_put),
3183 SOC_ENUM_EXT("PRI_TDM SlotWidth", tdm_slot_width,
3184 tdm_slot_width_get, tdm_slot_width_put),
3185 SOC_ENUM_EXT("SEC_TDM SlotNumber", tdm_slot_num,
3186 tdm_slot_num_get, tdm_slot_num_put),
3187 SOC_ENUM_EXT("SEC_TDM SlotWidth", tdm_slot_width,
3188 tdm_slot_width_get, tdm_slot_width_put),
3189 SOC_ENUM_EXT("TERT_TDM SlotNumber", tdm_slot_num,
3190 tdm_slot_num_get, tdm_slot_num_put),
3191 SOC_ENUM_EXT("TERT_TDM SlotWidth", tdm_slot_width,
3192 tdm_slot_width_get, tdm_slot_width_put),
3193 SOC_ENUM_EXT("QUAT_TDM SlotNumber", tdm_slot_num,
3194 tdm_slot_num_get, tdm_slot_num_put),
3195 SOC_ENUM_EXT("QUAT_TDM SlotWidth", tdm_slot_width,
3196 tdm_slot_width_get, tdm_slot_width_put),
3197 SOC_ENUM_EXT("QUIN_TDM SlotNumber", tdm_slot_num,
3198 tdm_slot_num_get, tdm_slot_num_put),
3199 SOC_ENUM_EXT("QUIN_TDM SlotWidth", tdm_slot_width,
3200 tdm_slot_width_get, tdm_slot_width_put),
3201 SOC_SINGLE_MULTI_EXT("PRI_TDM_RX_0 SlotMapping",
3202 SND_SOC_NOPM, 0, 0xFFFF, 0, TDM_SLOT_OFFSET_MAX,
3203 tdm_rx_slot_mapping_get, tdm_rx_slot_mapping_put),
3204 SOC_SINGLE_MULTI_EXT("PRI_TDM_RX_1 SlotMapping",
3205 SND_SOC_NOPM, 0, 0xFFFF, 0, TDM_SLOT_OFFSET_MAX,
3206 tdm_rx_slot_mapping_get, tdm_rx_slot_mapping_put),
3207 SOC_SINGLE_MULTI_EXT("PRI_TDM_RX_2 SlotMapping",
3208 SND_SOC_NOPM, 0, 0xFFFF, 0, TDM_SLOT_OFFSET_MAX,
3209 tdm_rx_slot_mapping_get, tdm_rx_slot_mapping_put),
3210 SOC_SINGLE_MULTI_EXT("PRI_TDM_RX_3 SlotMapping",
3211 SND_SOC_NOPM, 0, 0xFFFF, 0, TDM_SLOT_OFFSET_MAX,
3212 tdm_rx_slot_mapping_get, tdm_rx_slot_mapping_put),
3213 SOC_SINGLE_MULTI_EXT("PRI_TDM_RX_4 SlotMapping",
3214 SND_SOC_NOPM, 0, 0xFFFF, 0, TDM_SLOT_OFFSET_MAX,
3215 tdm_rx_slot_mapping_get, tdm_rx_slot_mapping_put),
3216 SOC_SINGLE_MULTI_EXT("PRI_TDM_RX_5 SlotMapping",
3217 SND_SOC_NOPM, 0, 0xFFFF, 0, TDM_SLOT_OFFSET_MAX,
3218 tdm_rx_slot_mapping_get, tdm_rx_slot_mapping_put),
3219 SOC_SINGLE_MULTI_EXT("PRI_TDM_RX_6 SlotMapping",
3220 SND_SOC_NOPM, 0, 0xFFFF, 0, TDM_SLOT_OFFSET_MAX,
3221 tdm_rx_slot_mapping_get, tdm_rx_slot_mapping_put),
3222 SOC_SINGLE_MULTI_EXT("PRI_TDM_RX_7 SlotMapping",
3223 SND_SOC_NOPM, 0, 0xFFFF, 0, TDM_SLOT_OFFSET_MAX,
3224 tdm_rx_slot_mapping_get, tdm_rx_slot_mapping_put),
3225 SOC_SINGLE_MULTI_EXT("PRI_TDM_TX_0 SlotMapping",
3226 SND_SOC_NOPM, 0, 0xFFFF, 0, TDM_SLOT_OFFSET_MAX,
3227 tdm_tx_slot_mapping_get, tdm_tx_slot_mapping_put),
3228 SOC_SINGLE_MULTI_EXT("PRI_TDM_TX_1 SlotMapping",
3229 SND_SOC_NOPM, 0, 0xFFFF, 0, TDM_SLOT_OFFSET_MAX,
3230 tdm_tx_slot_mapping_get, tdm_tx_slot_mapping_put),
3231 SOC_SINGLE_MULTI_EXT("PRI_TDM_TX_2 SlotMapping",
3232 SND_SOC_NOPM, 0, 0xFFFF, 0, TDM_SLOT_OFFSET_MAX,
3233 tdm_tx_slot_mapping_get, tdm_tx_slot_mapping_put),
3234 SOC_SINGLE_MULTI_EXT("PRI_TDM_TX_3 SlotMapping",
3235 SND_SOC_NOPM, 0, 0xFFFF, 0, TDM_SLOT_OFFSET_MAX,
3236 tdm_tx_slot_mapping_get, tdm_tx_slot_mapping_put),
3237 SOC_SINGLE_MULTI_EXT("PRI_TDM_TX_4 SlotMapping",
3238 SND_SOC_NOPM, 0, 0xFFFF, 0, TDM_SLOT_OFFSET_MAX,
3239 tdm_tx_slot_mapping_get, tdm_tx_slot_mapping_put),
3240 SOC_SINGLE_MULTI_EXT("PRI_TDM_TX_5 SlotMapping",
3241 SND_SOC_NOPM, 0, 0xFFFF, 0, TDM_SLOT_OFFSET_MAX,
3242 tdm_tx_slot_mapping_get, tdm_tx_slot_mapping_put),
3243 SOC_SINGLE_MULTI_EXT("PRI_TDM_TX_6 SlotMapping",
3244 SND_SOC_NOPM, 0, 0xFFFF, 0, TDM_SLOT_OFFSET_MAX,
3245 tdm_tx_slot_mapping_get, tdm_tx_slot_mapping_put),
3246 SOC_SINGLE_MULTI_EXT("PRI_TDM_TX_7 SlotMapping",
3247 SND_SOC_NOPM, 0, 0xFFFF, 0, TDM_SLOT_OFFSET_MAX,
3248 tdm_tx_slot_mapping_get, tdm_tx_slot_mapping_put),
3249 SOC_SINGLE_MULTI_EXT("SEC_TDM_RX_0 SlotMapping",
3250 SND_SOC_NOPM, 0, 0xFFFF, 0, TDM_SLOT_OFFSET_MAX,
3251 tdm_rx_slot_mapping_get, tdm_rx_slot_mapping_put),
3252 SOC_SINGLE_MULTI_EXT("SEC_TDM_RX_1 SlotMapping",
3253 SND_SOC_NOPM, 0, 0xFFFF, 0, TDM_SLOT_OFFSET_MAX,
3254 tdm_rx_slot_mapping_get, tdm_rx_slot_mapping_put),
3255 SOC_SINGLE_MULTI_EXT("SEC_TDM_RX_2 SlotMapping",
3256 SND_SOC_NOPM, 0, 0xFFFF, 0, TDM_SLOT_OFFSET_MAX,
3257 tdm_rx_slot_mapping_get, tdm_rx_slot_mapping_put),
3258 SOC_SINGLE_MULTI_EXT("SEC_TDM_RX_3 SlotMapping",
3259 SND_SOC_NOPM, 0, 0xFFFF, 0, TDM_SLOT_OFFSET_MAX,
3260 tdm_rx_slot_mapping_get, tdm_rx_slot_mapping_put),
3261 SOC_SINGLE_MULTI_EXT("SEC_TDM_RX_4 SlotMapping",
3262 SND_SOC_NOPM, 0, 0xFFFF, 0, TDM_SLOT_OFFSET_MAX,
3263 tdm_rx_slot_mapping_get, tdm_rx_slot_mapping_put),
3264 SOC_SINGLE_MULTI_EXT("SEC_TDM_RX_5 SlotMapping",
3265 SND_SOC_NOPM, 0, 0xFFFF, 0, TDM_SLOT_OFFSET_MAX,
3266 tdm_rx_slot_mapping_get, tdm_rx_slot_mapping_put),
3267 SOC_SINGLE_MULTI_EXT("SEC_TDM_RX_6 SlotMapping",
3268 SND_SOC_NOPM, 0, 0xFFFF, 0, TDM_SLOT_OFFSET_MAX,
3269 tdm_rx_slot_mapping_get, tdm_rx_slot_mapping_put),
3270 SOC_SINGLE_MULTI_EXT("SEC_TDM_RX_7 SlotMapping",
3271 SND_SOC_NOPM, 0, 0xFFFF, 0, TDM_SLOT_OFFSET_MAX,
3272 tdm_rx_slot_mapping_get, tdm_rx_slot_mapping_put),
3273 SOC_SINGLE_MULTI_EXT("SEC_TDM_TX_0 SlotMapping",
3274 SND_SOC_NOPM, 0, 0xFFFF, 0, TDM_SLOT_OFFSET_MAX,
3275 tdm_tx_slot_mapping_get, tdm_tx_slot_mapping_put),
3276 SOC_SINGLE_MULTI_EXT("SEC_TDM_TX_1 SlotMapping",
3277 SND_SOC_NOPM, 0, 0xFFFF, 0, TDM_SLOT_OFFSET_MAX,
3278 tdm_tx_slot_mapping_get, tdm_tx_slot_mapping_put),
3279 SOC_SINGLE_MULTI_EXT("SEC_TDM_TX_2 SlotMapping",
3280 SND_SOC_NOPM, 0, 0xFFFF, 0, TDM_SLOT_OFFSET_MAX,
3281 tdm_tx_slot_mapping_get, tdm_tx_slot_mapping_put),
3282 SOC_SINGLE_MULTI_EXT("SEC_TDM_TX_3 SlotMapping",
3283 SND_SOC_NOPM, 0, 0xFFFF, 0, TDM_SLOT_OFFSET_MAX,
3284 tdm_tx_slot_mapping_get, tdm_tx_slot_mapping_put),
3285 SOC_SINGLE_MULTI_EXT("SEC_TDM_TX_4 SlotMapping",
3286 SND_SOC_NOPM, 0, 0xFFFF, 0, TDM_SLOT_OFFSET_MAX,
3287 tdm_tx_slot_mapping_get, tdm_tx_slot_mapping_put),
3288 SOC_SINGLE_MULTI_EXT("SEC_TDM_TX_5 SlotMapping",
3289 SND_SOC_NOPM, 0, 0xFFFF, 0, TDM_SLOT_OFFSET_MAX,
3290 tdm_tx_slot_mapping_get, tdm_tx_slot_mapping_put),
3291 SOC_SINGLE_MULTI_EXT("SEC_TDM_TX_6 SlotMapping",
3292 SND_SOC_NOPM, 0, 0xFFFF, 0, TDM_SLOT_OFFSET_MAX,
3293 tdm_tx_slot_mapping_get, tdm_tx_slot_mapping_put),
3294 SOC_SINGLE_MULTI_EXT("SEC_TDM_TX_7 SlotMapping",
3295 SND_SOC_NOPM, 0, 0xFFFF, 0, TDM_SLOT_OFFSET_MAX,
3296 tdm_tx_slot_mapping_get, tdm_tx_slot_mapping_put),
3297 SOC_SINGLE_MULTI_EXT("TERT_TDM_RX_0 SlotMapping",
3298 SND_SOC_NOPM, 0, 0xFFFF, 0, TDM_SLOT_OFFSET_MAX,
3299 tdm_rx_slot_mapping_get, tdm_rx_slot_mapping_put),
3300 SOC_SINGLE_MULTI_EXT("TERT_TDM_RX_1 SlotMapping",
3301 SND_SOC_NOPM, 0, 0xFFFF, 0, TDM_SLOT_OFFSET_MAX,
3302 tdm_rx_slot_mapping_get, tdm_rx_slot_mapping_put),
3303 SOC_SINGLE_MULTI_EXT("TERT_TDM_RX_2 SlotMapping",
3304 SND_SOC_NOPM, 0, 0xFFFF, 0, TDM_SLOT_OFFSET_MAX,
3305 tdm_rx_slot_mapping_get, tdm_rx_slot_mapping_put),
3306 SOC_SINGLE_MULTI_EXT("TERT_TDM_RX_3 SlotMapping",
3307 SND_SOC_NOPM, 0, 0xFFFF, 0, TDM_SLOT_OFFSET_MAX,
3308 tdm_rx_slot_mapping_get, tdm_rx_slot_mapping_put),
3309 SOC_SINGLE_MULTI_EXT("TERT_TDM_RX_4 SlotMapping",
3310 SND_SOC_NOPM, 0, 0xFFFF, 0, TDM_SLOT_OFFSET_MAX,
3311 tdm_rx_slot_mapping_get, tdm_rx_slot_mapping_put),
3312 SOC_SINGLE_MULTI_EXT("TERT_TDM_RX_5 SlotMapping",
3313 SND_SOC_NOPM, 0, 0xFFFF, 0, TDM_SLOT_OFFSET_MAX,
3314 tdm_rx_slot_mapping_get, tdm_rx_slot_mapping_put),
3315 SOC_SINGLE_MULTI_EXT("TERT_TDM_RX_6 SlotMapping",
3316 SND_SOC_NOPM, 0, 0xFFFF, 0, TDM_SLOT_OFFSET_MAX,
3317 tdm_rx_slot_mapping_get, tdm_rx_slot_mapping_put),
3318 SOC_SINGLE_MULTI_EXT("TERT_TDM_RX_7 SlotMapping",
3319 SND_SOC_NOPM, 0, 0xFFFF, 0, TDM_SLOT_OFFSET_MAX,
3320 tdm_rx_slot_mapping_get, tdm_rx_slot_mapping_put),
3321 SOC_SINGLE_MULTI_EXT("TERT_TDM_TX_0 SlotMapping",
3322 SND_SOC_NOPM, 0, 0xFFFF, 0, TDM_SLOT_OFFSET_MAX,
3323 tdm_tx_slot_mapping_get, tdm_tx_slot_mapping_put),
3324 SOC_SINGLE_MULTI_EXT("TERT_TDM_TX_1 SlotMapping",
3325 SND_SOC_NOPM, 0, 0xFFFF, 0, TDM_SLOT_OFFSET_MAX,
3326 tdm_tx_slot_mapping_get, tdm_tx_slot_mapping_put),
3327 SOC_SINGLE_MULTI_EXT("TERT_TDM_TX_2 SlotMapping",
3328 SND_SOC_NOPM, 0, 0xFFFF, 0, TDM_SLOT_OFFSET_MAX,
3329 tdm_tx_slot_mapping_get, tdm_tx_slot_mapping_put),
3330 SOC_SINGLE_MULTI_EXT("TERT_TDM_TX_3 SlotMapping",
3331 SND_SOC_NOPM, 0, 0xFFFF, 0, TDM_SLOT_OFFSET_MAX,
3332 tdm_tx_slot_mapping_get, tdm_tx_slot_mapping_put),
3333 SOC_SINGLE_MULTI_EXT("TERT_TDM_TX_4 SlotMapping",
3334 SND_SOC_NOPM, 0, 0xFFFF, 0, TDM_SLOT_OFFSET_MAX,
3335 tdm_tx_slot_mapping_get, tdm_tx_slot_mapping_put),
3336 SOC_SINGLE_MULTI_EXT("TERT_TDM_TX_5 SlotMapping",
3337 SND_SOC_NOPM, 0, 0xFFFF, 0, TDM_SLOT_OFFSET_MAX,
3338 tdm_tx_slot_mapping_get, tdm_tx_slot_mapping_put),
3339 SOC_SINGLE_MULTI_EXT("TERT_TDM_TX_6 SlotMapping",
3340 SND_SOC_NOPM, 0, 0xFFFF, 0, TDM_SLOT_OFFSET_MAX,
3341 tdm_tx_slot_mapping_get, tdm_tx_slot_mapping_put),
3342 SOC_SINGLE_MULTI_EXT("TERT_TDM_TX_7 SlotMapping",
3343 SND_SOC_NOPM, 0, 0xFFFF, 0, TDM_SLOT_OFFSET_MAX,
3344 tdm_tx_slot_mapping_get, tdm_tx_slot_mapping_put),
3345 SOC_SINGLE_MULTI_EXT("QUAT_TDM_RX_0 SlotMapping",
3346 SND_SOC_NOPM, 0, 0xFFFF, 0, TDM_SLOT_OFFSET_MAX,
3347 tdm_rx_slot_mapping_get, tdm_rx_slot_mapping_put),
3348 SOC_SINGLE_MULTI_EXT("QUAT_TDM_RX_1 SlotMapping",
3349 SND_SOC_NOPM, 0, 0xFFFF, 0, TDM_SLOT_OFFSET_MAX,
3350 tdm_rx_slot_mapping_get, tdm_rx_slot_mapping_put),
3351 SOC_SINGLE_MULTI_EXT("QUAT_TDM_RX_2 SlotMapping",
3352 SND_SOC_NOPM, 0, 0xFFFF, 0, TDM_SLOT_OFFSET_MAX,
3353 tdm_rx_slot_mapping_get, tdm_rx_slot_mapping_put),
3354 SOC_SINGLE_MULTI_EXT("QUAT_TDM_RX_3 SlotMapping",
3355 SND_SOC_NOPM, 0, 0xFFFF, 0, TDM_SLOT_OFFSET_MAX,
3356 tdm_rx_slot_mapping_get, tdm_rx_slot_mapping_put),
3357 SOC_SINGLE_MULTI_EXT("QUAT_TDM_RX_4 SlotMapping",
3358 SND_SOC_NOPM, 0, 0xFFFF, 0, TDM_SLOT_OFFSET_MAX,
3359 tdm_rx_slot_mapping_get, tdm_rx_slot_mapping_put),
3360 SOC_SINGLE_MULTI_EXT("QUAT_TDM_RX_5 SlotMapping",
3361 SND_SOC_NOPM, 0, 0xFFFF, 0, TDM_SLOT_OFFSET_MAX,
3362 tdm_rx_slot_mapping_get, tdm_rx_slot_mapping_put),
3363 SOC_SINGLE_MULTI_EXT("QUAT_TDM_RX_6 SlotMapping",
3364 SND_SOC_NOPM, 0, 0xFFFF, 0, TDM_SLOT_OFFSET_MAX,
3365 tdm_rx_slot_mapping_get, tdm_rx_slot_mapping_put),
3366 SOC_SINGLE_MULTI_EXT("QUAT_TDM_RX_7 SlotMapping",
3367 SND_SOC_NOPM, 0, 0xFFFF, 0, TDM_SLOT_OFFSET_MAX,
3368 tdm_rx_slot_mapping_get, tdm_rx_slot_mapping_put),
3369 SOC_SINGLE_MULTI_EXT("QUAT_TDM_TX_0 SlotMapping",
3370 SND_SOC_NOPM, 0, 0xFFFF, 0, TDM_SLOT_OFFSET_MAX,
3371 tdm_tx_slot_mapping_get, tdm_tx_slot_mapping_put),
3372 SOC_SINGLE_MULTI_EXT("QUAT_TDM_TX_1 SlotMapping",
3373 SND_SOC_NOPM, 0, 0xFFFF, 0, TDM_SLOT_OFFSET_MAX,
3374 tdm_tx_slot_mapping_get, tdm_tx_slot_mapping_put),
3375 SOC_SINGLE_MULTI_EXT("QUAT_TDM_TX_2 SlotMapping",
3376 SND_SOC_NOPM, 0, 0xFFFF, 0, TDM_SLOT_OFFSET_MAX,
3377 tdm_tx_slot_mapping_get, tdm_tx_slot_mapping_put),
3378 SOC_SINGLE_MULTI_EXT("QUAT_TDM_TX_3 SlotMapping",
3379 SND_SOC_NOPM, 0, 0xFFFF, 0, TDM_SLOT_OFFSET_MAX,
3380 tdm_tx_slot_mapping_get, tdm_tx_slot_mapping_put),
3381 SOC_SINGLE_MULTI_EXT("QUAT_TDM_TX_4 SlotMapping",
3382 SND_SOC_NOPM, 0, 0xFFFF, 0, TDM_SLOT_OFFSET_MAX,
3383 tdm_tx_slot_mapping_get, tdm_tx_slot_mapping_put),
3384 SOC_SINGLE_MULTI_EXT("QUAT_TDM_TX_5 SlotMapping",
3385 SND_SOC_NOPM, 0, 0xFFFF, 0, TDM_SLOT_OFFSET_MAX,
3386 tdm_tx_slot_mapping_get, tdm_tx_slot_mapping_put),
3387 SOC_SINGLE_MULTI_EXT("QUAT_TDM_TX_6 SlotMapping",
3388 SND_SOC_NOPM, 0, 0xFFFF, 0, TDM_SLOT_OFFSET_MAX,
3389 tdm_tx_slot_mapping_get, tdm_tx_slot_mapping_put),
3390 SOC_SINGLE_MULTI_EXT("QUAT_TDM_TX_7 SlotMapping",
3391 SND_SOC_NOPM, 0, 0xFFFF, 0, TDM_SLOT_OFFSET_MAX,
3392 tdm_tx_slot_mapping_get, tdm_tx_slot_mapping_put),
3393 SOC_SINGLE_MULTI_EXT("QUIN_TDM_RX_0 SlotMapping",
3394 SND_SOC_NOPM, 0, 0xFFFF, 0, TDM_SLOT_OFFSET_MAX,
3395 tdm_rx_slot_mapping_get, tdm_rx_slot_mapping_put),
3396 SOC_SINGLE_MULTI_EXT("QUIN_TDM_RX_1 SlotMapping",
3397 SND_SOC_NOPM, 0, 0xFFFF, 0, TDM_SLOT_OFFSET_MAX,
3398 tdm_rx_slot_mapping_get, tdm_rx_slot_mapping_put),
3399 SOC_SINGLE_MULTI_EXT("QUIN_TDM_RX_2 SlotMapping",
3400 SND_SOC_NOPM, 0, 0xFFFF, 0, TDM_SLOT_OFFSET_MAX,
3401 tdm_rx_slot_mapping_get, tdm_rx_slot_mapping_put),
3402 SOC_SINGLE_MULTI_EXT("QUIN_TDM_RX_3 SlotMapping",
3403 SND_SOC_NOPM, 0, 0xFFFF, 0, TDM_SLOT_OFFSET_MAX,
3404 tdm_rx_slot_mapping_get, tdm_rx_slot_mapping_put),
3405 SOC_SINGLE_MULTI_EXT("QUIN_TDM_RX_4 SlotMapping",
3406 SND_SOC_NOPM, 0, 0xFFFF, 0, TDM_SLOT_OFFSET_MAX,
3407 tdm_rx_slot_mapping_get, tdm_rx_slot_mapping_put),
3408 SOC_SINGLE_MULTI_EXT("QUIN_TDM_RX_5 SlotMapping",
3409 SND_SOC_NOPM, 0, 0xFFFF, 0, TDM_SLOT_OFFSET_MAX,
3410 tdm_rx_slot_mapping_get, tdm_rx_slot_mapping_put),
3411 SOC_SINGLE_MULTI_EXT("QUIN_TDM_RX_6 SlotMapping",
3412 SND_SOC_NOPM, 0, 0xFFFF, 0, TDM_SLOT_OFFSET_MAX,
3413 tdm_rx_slot_mapping_get, tdm_rx_slot_mapping_put),
3414 SOC_SINGLE_MULTI_EXT("QUIN_TDM_RX_7 SlotMapping",
3415 SND_SOC_NOPM, 0, 0xFFFF, 0, TDM_SLOT_OFFSET_MAX,
3416 tdm_rx_slot_mapping_get, tdm_rx_slot_mapping_put),
3417 SOC_SINGLE_MULTI_EXT("QUIN_TDM_TX_0 SlotMapping",
3418 SND_SOC_NOPM, 0, 0xFFFF, 0, TDM_SLOT_OFFSET_MAX,
3419 tdm_tx_slot_mapping_get, tdm_tx_slot_mapping_put),
3420 SOC_SINGLE_MULTI_EXT("QUIN_TDM_TX_1 SlotMapping",
3421 SND_SOC_NOPM, 0, 0xFFFF, 0, TDM_SLOT_OFFSET_MAX,
3422 tdm_tx_slot_mapping_get, tdm_tx_slot_mapping_put),
3423 SOC_SINGLE_MULTI_EXT("QUIN_TDM_TX_2 SlotMapping",
3424 SND_SOC_NOPM, 0, 0xFFFF, 0, TDM_SLOT_OFFSET_MAX,
3425 tdm_tx_slot_mapping_get, tdm_tx_slot_mapping_put),
3426 SOC_SINGLE_MULTI_EXT("QUIN_TDM_TX_3 SlotMapping",
3427 SND_SOC_NOPM, 0, 0xFFFF, 0, TDM_SLOT_OFFSET_MAX,
3428 tdm_tx_slot_mapping_get, tdm_tx_slot_mapping_put),
3429 SOC_SINGLE_MULTI_EXT("QUIN_TDM_TX_4 SlotMapping",
3430 SND_SOC_NOPM, 0, 0xFFFF, 0, TDM_SLOT_OFFSET_MAX,
3431 tdm_tx_slot_mapping_get, tdm_tx_slot_mapping_put),
3432 SOC_SINGLE_MULTI_EXT("QUIN_TDM_TX_5 SlotMapping",
3433 SND_SOC_NOPM, 0, 0xFFFF, 0, TDM_SLOT_OFFSET_MAX,
3434 tdm_tx_slot_mapping_get, tdm_tx_slot_mapping_put),
3435 SOC_SINGLE_MULTI_EXT("QUIN_TDM_TX_6 SlotMapping",
3436 SND_SOC_NOPM, 0, 0xFFFF, 0, TDM_SLOT_OFFSET_MAX,
3437 tdm_tx_slot_mapping_get, tdm_tx_slot_mapping_put),
3438 SOC_SINGLE_MULTI_EXT("QUIN_TDM_TX_7 SlotMapping",
3439 SND_SOC_NOPM, 0, 0xFFFF, 0, TDM_SLOT_OFFSET_MAX,
3440 tdm_tx_slot_mapping_get, tdm_tx_slot_mapping_put),
Revathi Uddaraju30feb0d2017-11-21 15:30:19 +0530[diff] [blame]3441 SOC_ENUM_EXT("MultiMedia5_RX QOS Vote", qos_vote, msm_qos_ctl_get,
3442 msm_qos_ctl_put),
Asish Bhattacharya8e2277f2017-07-20 18:31:55 +0530[diff] [blame]3443};
3444
3445/**
3446 * msm_common_snd_controls_size - to return controls size
3447 *
3448 * Return: returns size of common controls array
3449 */
3450int msm_common_snd_controls_size(void)
3451{
3452 return ARRAY_SIZE(msm_common_snd_controls);
3453}
3454EXPORT_SYMBOL(msm_common_snd_controls_size);
3455
Laxminath Kasam38070be2017-08-17 18:21:59 +0530[diff] [blame]3456void msm_set_codec_reg_done(bool done)
3457{
3458 codec_reg_done = done;
3459}
3460EXPORT_SYMBOL(msm_set_codec_reg_done);
3461
Asish Bhattacharya8e2277f2017-07-20 18:31:55 +0530[diff] [blame]3462static inline int param_is_mask(int p)
3463{
3464 return (p >= SNDRV_PCM_HW_PARAM_FIRST_MASK) &&
3465 (p <= SNDRV_PCM_HW_PARAM_LAST_MASK);
3466}
3467
3468static inline struct snd_mask *param_to_mask(struct snd_pcm_hw_params *p,
3469 int n)
3470{
3471 return &(p->masks[n - SNDRV_PCM_HW_PARAM_FIRST_MASK]);
3472}
3473
3474static void param_set_mask(struct snd_pcm_hw_params *p, int n, unsigned int bit)
3475{
3476 if (bit >= SNDRV_MASK_MAX)
3477 return;
3478 if (param_is_mask(n)) {
3479 struct snd_mask *m = param_to_mask(p, n);
3480
3481 m->bits[0] = 0;
3482 m->bits[1] = 0;
3483 m->bits[bit >> 5] |= (1 << (bit & 31));
3484 }
3485}
3486
Dhanalakshmi Siddanid70a4f72019-11-27 15:35:41 +0530[diff] [blame]3487int msm_tdm_be_hw_params_fixup(struct snd_soc_pcm_runtime *rtd,
3488 struct snd_pcm_hw_params *params)
3489{
3490 struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
3491 struct snd_interval *rate = hw_param_interval(params,
3492 SNDRV_PCM_HW_PARAM_RATE);
3493 struct snd_interval *channels = hw_param_interval(params,
3494 SNDRV_PCM_HW_PARAM_CHANNELS);
3495 switch (cpu_dai->id) {
3496 case AFE_PORT_ID_PRIMARY_TDM_RX:
3497 channels->min = channels->max =
3498 tdm_rx_cfg[TDM_PRI][TDM_0].channels;
3499 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
3500 tdm_rx_cfg[TDM_PRI][TDM_0].bit_format);
3501 rate->min = rate->max =
3502 tdm_rx_cfg[TDM_PRI][TDM_0].sample_rate;
3503 break;
3504 case AFE_PORT_ID_PRIMARY_TDM_RX_1:
3505 channels->min = channels->max =
3506 tdm_rx_cfg[TDM_PRI][TDM_1].channels;
3507 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
3508 tdm_rx_cfg[TDM_PRI][TDM_1].bit_format);
3509 rate->min = rate->max =
3510 tdm_rx_cfg[TDM_PRI][TDM_1].sample_rate;
3511 break;
3512 case AFE_PORT_ID_PRIMARY_TDM_RX_2:
3513 channels->min = channels->max =
3514 tdm_rx_cfg[TDM_PRI][TDM_2].channels;
3515 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
3516 tdm_rx_cfg[TDM_PRI][TDM_2].bit_format);
3517 rate->min = rate->max =
3518 tdm_rx_cfg[TDM_PRI][TDM_2].sample_rate;
3519 break;
3520 case AFE_PORT_ID_PRIMARY_TDM_RX_3:
3521 channels->min = channels->max =
3522 tdm_rx_cfg[TDM_PRI][TDM_3].channels;
3523 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
3524 tdm_rx_cfg[TDM_PRI][TDM_3].bit_format);
3525 rate->min = rate->max =
3526 tdm_rx_cfg[TDM_PRI][TDM_3].sample_rate;
3527 break;
3528 case AFE_PORT_ID_PRIMARY_TDM_RX_4:
3529 channels->min = channels->max =
3530 tdm_rx_cfg[TDM_PRI][TDM_4].channels;
3531 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
3532 tdm_rx_cfg[TDM_PRI][TDM_4].bit_format);
3533 rate->min = rate->max =
3534 tdm_rx_cfg[TDM_PRI][TDM_4].sample_rate;
3535 break;
3536 case AFE_PORT_ID_PRIMARY_TDM_RX_5:
3537 channels->min = channels->max =
3538 tdm_rx_cfg[TDM_PRI][TDM_5].channels;
3539 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
3540 tdm_rx_cfg[TDM_PRI][TDM_5].bit_format);
3541 rate->min = rate->max =
3542 tdm_rx_cfg[TDM_PRI][TDM_5].sample_rate;
3543 break;
3544 case AFE_PORT_ID_PRIMARY_TDM_RX_6:
3545 channels->min = channels->max =
3546 tdm_rx_cfg[TDM_PRI][TDM_6].channels;
3547 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
3548 tdm_rx_cfg[TDM_PRI][TDM_6].bit_format);
3549 rate->min = rate->max =
3550 tdm_rx_cfg[TDM_PRI][TDM_6].sample_rate;
3551 break;
3552 case AFE_PORT_ID_PRIMARY_TDM_RX_7:
3553 channels->min = channels->max =
3554 tdm_rx_cfg[TDM_PRI][TDM_7].channels;
3555 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
3556 tdm_rx_cfg[TDM_PRI][TDM_7].bit_format);
3557 rate->min = rate->max =
3558 tdm_rx_cfg[TDM_PRI][TDM_7].sample_rate;
3559 break;
3560 case AFE_PORT_ID_PRIMARY_TDM_TX:
3561 channels->min = channels->max =
3562 tdm_tx_cfg[TDM_PRI][TDM_0].channels;
3563 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
3564 tdm_tx_cfg[TDM_PRI][TDM_0].bit_format);
3565 rate->min = rate->max =
3566 tdm_tx_cfg[TDM_PRI][TDM_0].sample_rate;
3567 break;
3568 case AFE_PORT_ID_PRIMARY_TDM_TX_1:
3569 channels->min = channels->max =
3570 tdm_tx_cfg[TDM_PRI][TDM_1].channels;
3571 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
3572 tdm_tx_cfg[TDM_PRI][TDM_1].bit_format);
3573 rate->min = rate->max =
3574 tdm_tx_cfg[TDM_PRI][TDM_1].sample_rate;
3575 break;
3576 case AFE_PORT_ID_PRIMARY_TDM_TX_2:
3577 channels->min = channels->max =
3578 tdm_tx_cfg[TDM_PRI][TDM_2].channels;
3579 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
3580 tdm_tx_cfg[TDM_PRI][TDM_2].bit_format);
3581 rate->min = rate->max =
3582 tdm_tx_cfg[TDM_PRI][TDM_2].sample_rate;
3583 break;
3584 case AFE_PORT_ID_PRIMARY_TDM_TX_3:
3585 channels->min = channels->max =
3586 tdm_tx_cfg[TDM_PRI][TDM_3].channels;
3587 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
3588 tdm_tx_cfg[TDM_PRI][TDM_3].bit_format);
3589 rate->min = rate->max =
3590 tdm_tx_cfg[TDM_PRI][TDM_3].sample_rate;
3591 break;
3592 case AFE_PORT_ID_PRIMARY_TDM_TX_4:
3593 channels->min = channels->max =
3594 tdm_tx_cfg[TDM_PRI][TDM_4].channels;
3595 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
3596 tdm_tx_cfg[TDM_PRI][TDM_4].bit_format);
3597 rate->min = rate->max =
3598 tdm_tx_cfg[TDM_PRI][TDM_4].sample_rate;
3599 break;
3600 case AFE_PORT_ID_PRIMARY_TDM_TX_5:
3601 channels->min = channels->max =
3602 tdm_tx_cfg[TDM_PRI][TDM_5].channels;
3603 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
3604 tdm_tx_cfg[TDM_PRI][TDM_5].bit_format);
3605 rate->min = rate->max =
3606 tdm_tx_cfg[TDM_PRI][TDM_5].sample_rate;
3607 break;
3608 case AFE_PORT_ID_PRIMARY_TDM_TX_6:
3609 channels->min = channels->max =
3610 tdm_tx_cfg[TDM_PRI][TDM_6].channels;
3611 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
3612 tdm_tx_cfg[TDM_PRI][TDM_6].bit_format);
3613 rate->min = rate->max =
3614 tdm_tx_cfg[TDM_PRI][TDM_6].sample_rate;
3615 break;
3616 case AFE_PORT_ID_PRIMARY_TDM_TX_7:
3617 channels->min = channels->max =
3618 tdm_tx_cfg[TDM_PRI][TDM_7].channels;
3619 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
3620 tdm_tx_cfg[TDM_PRI][TDM_7].bit_format);
3621 rate->min = rate->max =
3622 tdm_tx_cfg[TDM_PRI][TDM_7].sample_rate;
3623 break;
3624 case AFE_PORT_ID_SECONDARY_TDM_RX:
3625 channels->min = channels->max =
3626 tdm_rx_cfg[TDM_SEC][TDM_0].channels;
3627 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
3628 tdm_rx_cfg[TDM_SEC][TDM_0].bit_format);
3629 rate->min = rate->max =
3630 tdm_rx_cfg[TDM_SEC][TDM_0].sample_rate;
3631 break;
3632 case AFE_PORT_ID_SECONDARY_TDM_RX_1:
3633 channels->min = channels->max =
3634 tdm_rx_cfg[TDM_SEC][TDM_1].channels;
3635 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
3636 tdm_rx_cfg[TDM_SEC][TDM_1].bit_format);
3637 rate->min = rate->max =
3638 tdm_rx_cfg[TDM_SEC][TDM_1].sample_rate;
3639 break;
3640 case AFE_PORT_ID_SECONDARY_TDM_RX_2:
3641 channels->min = channels->max =
3642 tdm_rx_cfg[TDM_SEC][TDM_2].channels;
3643 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
3644 tdm_rx_cfg[TDM_SEC][TDM_2].bit_format);
3645 rate->min = rate->max =
3646 tdm_rx_cfg[TDM_SEC][TDM_2].sample_rate;
3647 break;
3648 case AFE_PORT_ID_SECONDARY_TDM_RX_3:
3649 channels->min = channels->max =
3650 tdm_rx_cfg[TDM_SEC][TDM_3].channels;
3651 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
3652 tdm_rx_cfg[TDM_SEC][TDM_3].bit_format);
3653 rate->min = rate->max =
3654 tdm_rx_cfg[TDM_SEC][TDM_3].sample_rate;
3655 break;
3656 case AFE_PORT_ID_SECONDARY_TDM_RX_4:
3657 channels->min = channels->max =
3658 tdm_rx_cfg[TDM_SEC][TDM_4].channels;
3659 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
3660 tdm_rx_cfg[TDM_SEC][TDM_4].bit_format);
3661 rate->min = rate->max =
3662 tdm_rx_cfg[TDM_SEC][TDM_4].sample_rate;
3663 break;
3664 case AFE_PORT_ID_SECONDARY_TDM_RX_5:
3665 channels->min = channels->max =
3666 tdm_rx_cfg[TDM_SEC][TDM_5].channels;
3667 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
3668 tdm_rx_cfg[TDM_SEC][TDM_5].bit_format);
3669 rate->min = rate->max =
3670 tdm_rx_cfg[TDM_SEC][TDM_5].sample_rate;
3671 break;
3672 case AFE_PORT_ID_SECONDARY_TDM_RX_6:
3673 channels->min = channels->max =
3674 tdm_rx_cfg[TDM_SEC][TDM_6].channels;
3675 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
3676 tdm_rx_cfg[TDM_SEC][TDM_6].bit_format);
3677 rate->min = rate->max =
3678 tdm_rx_cfg[TDM_SEC][TDM_6].sample_rate;
3679 break;
3680 case AFE_PORT_ID_SECONDARY_TDM_RX_7:
3681 channels->min = channels->max =
3682 tdm_rx_cfg[TDM_SEC][TDM_7].channels;
3683 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
3684 tdm_rx_cfg[TDM_SEC][TDM_7].bit_format);
3685 rate->min = rate->max =
3686 tdm_rx_cfg[TDM_SEC][TDM_7].sample_rate;
3687 break;
3688 case AFE_PORT_ID_SECONDARY_TDM_TX:
3689 channels->min = channels->max =
3690 tdm_tx_cfg[TDM_SEC][TDM_0].channels;
3691 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
3692 tdm_tx_cfg[TDM_SEC][TDM_0].bit_format);
3693 rate->min = rate->max =
3694 tdm_tx_cfg[TDM_SEC][TDM_0].sample_rate;
3695 break;
3696 case AFE_PORT_ID_SECONDARY_TDM_TX_1:
3697 channels->min = channels->max =
3698 tdm_tx_cfg[TDM_SEC][TDM_1].channels;
3699 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
3700 tdm_tx_cfg[TDM_SEC][TDM_1].bit_format);
3701 rate->min = rate->max =
3702 tdm_tx_cfg[TDM_SEC][TDM_1].sample_rate;
3703 break;
3704 case AFE_PORT_ID_SECONDARY_TDM_TX_2:
3705 channels->min = channels->max =
3706 tdm_tx_cfg[TDM_SEC][TDM_2].channels;
3707 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
3708 tdm_tx_cfg[TDM_SEC][TDM_2].bit_format);
3709 rate->min = rate->max =
3710 tdm_tx_cfg[TDM_SEC][TDM_2].sample_rate;
3711 break;
3712 case AFE_PORT_ID_SECONDARY_TDM_TX_3:
3713 channels->min = channels->max =
3714 tdm_tx_cfg[TDM_SEC][TDM_3].channels;
3715 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
3716 tdm_tx_cfg[TDM_SEC][TDM_3].bit_format);
3717 rate->min = rate->max =
3718 tdm_tx_cfg[TDM_SEC][TDM_3].sample_rate;
3719 break;
3720 case AFE_PORT_ID_SECONDARY_TDM_TX_4:
3721 channels->min = channels->max =
3722 tdm_tx_cfg[TDM_SEC][TDM_4].channels;
3723 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
3724 tdm_tx_cfg[TDM_SEC][TDM_4].bit_format);
3725 rate->min = rate->max =
3726 tdm_tx_cfg[TDM_SEC][TDM_4].sample_rate;
3727 break;
3728 case AFE_PORT_ID_SECONDARY_TDM_TX_5:
3729 channels->min = channels->max =
3730 tdm_tx_cfg[TDM_SEC][TDM_5].channels;
3731 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
3732 tdm_tx_cfg[TDM_SEC][TDM_5].bit_format);
3733 rate->min = rate->max =
3734 tdm_tx_cfg[TDM_SEC][TDM_5].sample_rate;
3735 break;
3736 case AFE_PORT_ID_SECONDARY_TDM_TX_6:
3737 channels->min = channels->max =
3738 tdm_tx_cfg[TDM_SEC][TDM_6].channels;
3739 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
3740 tdm_tx_cfg[TDM_SEC][TDM_6].bit_format);
3741 rate->min = rate->max =
3742 tdm_tx_cfg[TDM_SEC][TDM_6].sample_rate;
3743 break;
3744 case AFE_PORT_ID_SECONDARY_TDM_TX_7:
3745 channels->min = channels->max =
3746 tdm_tx_cfg[TDM_SEC][TDM_7].channels;
3747 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
3748 tdm_tx_cfg[TDM_SEC][TDM_7].bit_format);
3749 rate->min = rate->max =
3750 tdm_tx_cfg[TDM_SEC][TDM_7].sample_rate;
3751 break;
3752 case AFE_PORT_ID_TERTIARY_TDM_RX:
3753 channels->min = channels->max =
3754 tdm_rx_cfg[TDM_TERT][TDM_0].channels;
3755 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
3756 tdm_rx_cfg[TDM_TERT][TDM_0].bit_format);
3757 rate->min = rate->max =
3758 tdm_rx_cfg[TDM_TERT][TDM_0].sample_rate;
3759 break;
3760 case AFE_PORT_ID_TERTIARY_TDM_RX_1:
3761 channels->min = channels->max =
3762 tdm_rx_cfg[TDM_TERT][TDM_1].channels;
3763 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
3764 tdm_rx_cfg[TDM_TERT][TDM_1].bit_format);
3765 rate->min = rate->max =
3766 tdm_rx_cfg[TDM_TERT][TDM_1].sample_rate;
3767 break;
3768 case AFE_PORT_ID_TERTIARY_TDM_RX_2:
3769 channels->min = channels->max =
3770 tdm_rx_cfg[TDM_TERT][TDM_2].channels;
3771 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
3772 tdm_rx_cfg[TDM_TERT][TDM_2].bit_format);
3773 rate->min = rate->max =
3774 tdm_rx_cfg[TDM_TERT][TDM_2].sample_rate;
3775 break;
3776 case AFE_PORT_ID_TERTIARY_TDM_RX_3:
3777 channels->min = channels->max =
3778 tdm_rx_cfg[TDM_TERT][TDM_3].channels;
3779 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
3780 tdm_rx_cfg[TDM_TERT][TDM_3].bit_format);
3781 rate->min = rate->max =
3782 tdm_rx_cfg[TDM_TERT][TDM_3].sample_rate;
3783 break;
3784 case AFE_PORT_ID_TERTIARY_TDM_RX_4:
3785 channels->min = channels->max =
3786 tdm_rx_cfg[TDM_TERT][TDM_4].channels;
3787 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
3788 tdm_rx_cfg[TDM_TERT][TDM_4].bit_format);
3789 rate->min = rate->max =
3790 tdm_rx_cfg[TDM_TERT][TDM_4].sample_rate;
3791 break;
3792 case AFE_PORT_ID_TERTIARY_TDM_RX_5:
3793 channels->min = channels->max =
3794 tdm_rx_cfg[TDM_TERT][TDM_5].channels;
3795 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
3796 tdm_rx_cfg[TDM_TERT][TDM_5].bit_format);
3797 rate->min = rate->max =
3798 tdm_rx_cfg[TDM_TERT][TDM_5].sample_rate;
3799 break;
3800 case AFE_PORT_ID_TERTIARY_TDM_RX_6:
3801 channels->min = channels->max =
3802 tdm_rx_cfg[TDM_TERT][TDM_6].channels;
3803 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
3804 tdm_rx_cfg[TDM_TERT][TDM_6].bit_format);
3805 rate->min = rate->max =
3806 tdm_rx_cfg[TDM_TERT][TDM_6].sample_rate;
3807 break;
3808 case AFE_PORT_ID_TERTIARY_TDM_RX_7:
3809 channels->min = channels->max =
3810 tdm_rx_cfg[TDM_TERT][TDM_7].channels;
3811 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
3812 tdm_rx_cfg[TDM_TERT][TDM_7].bit_format);
3813 rate->min = rate->max =
3814 tdm_rx_cfg[TDM_TERT][TDM_7].sample_rate;
3815 break;
3816 case AFE_PORT_ID_TERTIARY_TDM_TX:
3817 channels->min = channels->max =
3818 tdm_tx_cfg[TDM_TERT][TDM_0].channels;
3819 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
3820 tdm_tx_cfg[TDM_TERT][TDM_0].bit_format);
3821 rate->min = rate->max =
3822 tdm_tx_cfg[TDM_TERT][TDM_0].sample_rate;
3823 break;
3824 case AFE_PORT_ID_TERTIARY_TDM_TX_1:
3825 channels->min = channels->max =
3826 tdm_tx_cfg[TDM_TERT][TDM_1].channels;
3827 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
3828 tdm_tx_cfg[TDM_TERT][TDM_1].bit_format);
3829 rate->min = rate->max =
3830 tdm_tx_cfg[TDM_TERT][TDM_1].sample_rate;
3831 break;
3832 case AFE_PORT_ID_TERTIARY_TDM_TX_2:
3833 channels->min = channels->max =
3834 tdm_tx_cfg[TDM_TERT][TDM_2].channels;
3835 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
3836 tdm_tx_cfg[TDM_TERT][TDM_2].bit_format);
3837 rate->min = rate->max =
3838 tdm_tx_cfg[TDM_TERT][TDM_2].sample_rate;
3839 break;
3840 case AFE_PORT_ID_TERTIARY_TDM_TX_3:
3841 channels->min = channels->max =
3842 tdm_tx_cfg[TDM_TERT][TDM_3].channels;
3843 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
3844 tdm_tx_cfg[TDM_TERT][TDM_3].bit_format);
3845 rate->min = rate->max =
3846 tdm_tx_cfg[TDM_TERT][TDM_3].sample_rate;
3847 break;
3848 case AFE_PORT_ID_TERTIARY_TDM_TX_4:
3849 channels->min = channels->max =
3850 tdm_tx_cfg[TDM_TERT][TDM_4].channels;
3851 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
3852 tdm_tx_cfg[TDM_TERT][TDM_4].bit_format);
3853 rate->min = rate->max =
3854 tdm_tx_cfg[TDM_TERT][TDM_4].sample_rate;
3855 break;
3856 case AFE_PORT_ID_TERTIARY_TDM_TX_5:
3857 channels->min = channels->max =
3858 tdm_tx_cfg[TDM_TERT][TDM_5].channels;
3859 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
3860 tdm_tx_cfg[TDM_TERT][TDM_5].bit_format);
3861 rate->min = rate->max =
3862 tdm_tx_cfg[TDM_TERT][TDM_5].sample_rate;
3863 break;
3864 case AFE_PORT_ID_TERTIARY_TDM_TX_6:
3865 channels->min = channels->max =
3866 tdm_tx_cfg[TDM_TERT][TDM_6].channels;
3867 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
3868 tdm_tx_cfg[TDM_TERT][TDM_6].bit_format);
3869 rate->min = rate->max =
3870 tdm_tx_cfg[TDM_TERT][TDM_6].sample_rate;
3871 break;
3872 case AFE_PORT_ID_TERTIARY_TDM_TX_7:
3873 channels->min = channels->max =
3874 tdm_tx_cfg[TDM_TERT][TDM_7].channels;
3875 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
3876 tdm_tx_cfg[TDM_TERT][TDM_7].bit_format);
3877 rate->min = rate->max =
3878 tdm_tx_cfg[TDM_TERT][TDM_7].sample_rate;
3879 break;
3880 case AFE_PORT_ID_QUATERNARY_TDM_RX:
3881 channels->min = channels->max =
3882 tdm_rx_cfg[TDM_QUAT][TDM_0].channels;
3883 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
3884 tdm_rx_cfg[TDM_QUAT][TDM_0].bit_format);
3885 rate->min = rate->max =
3886 tdm_rx_cfg[TDM_QUAT][TDM_0].sample_rate;
3887 break;
3888 case AFE_PORT_ID_QUATERNARY_TDM_RX_1:
3889 channels->min = channels->max =
3890 tdm_rx_cfg[TDM_QUAT][TDM_1].channels;
3891 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
3892 tdm_rx_cfg[TDM_QUAT][TDM_1].bit_format);
3893 rate->min = rate->max =
3894 tdm_rx_cfg[TDM_QUAT][TDM_1].sample_rate;
3895 break;
3896 case AFE_PORT_ID_QUATERNARY_TDM_RX_2:
3897 channels->min = channels->max =
3898 tdm_rx_cfg[TDM_QUAT][TDM_2].channels;
3899 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
3900 tdm_rx_cfg[TDM_QUAT][TDM_2].bit_format);
3901 rate->min = rate->max =
3902 tdm_rx_cfg[TDM_QUAT][TDM_2].sample_rate;
3903 break;
3904 case AFE_PORT_ID_QUATERNARY_TDM_RX_3:
3905 channels->min = channels->max =
3906 tdm_rx_cfg[TDM_QUAT][TDM_3].channels;
3907 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
3908 tdm_rx_cfg[TDM_QUAT][TDM_3].bit_format);
3909 rate->min = rate->max =
3910 tdm_rx_cfg[TDM_QUAT][TDM_3].sample_rate;
3911 break;
3912 case AFE_PORT_ID_QUATERNARY_TDM_RX_4:
3913 channels->min = channels->max =
3914 tdm_rx_cfg[TDM_QUAT][TDM_4].channels;
3915 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
3916 tdm_rx_cfg[TDM_QUAT][TDM_4].bit_format);
3917 rate->min = rate->max =
3918 tdm_rx_cfg[TDM_QUAT][TDM_4].sample_rate;
3919 break;
3920 case AFE_PORT_ID_QUATERNARY_TDM_RX_5:
3921 channels->min = channels->max =
3922 tdm_rx_cfg[TDM_QUAT][TDM_5].channels;
3923 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
3924 tdm_rx_cfg[TDM_QUAT][TDM_5].bit_format);
3925 rate->min = rate->max =
3926 tdm_rx_cfg[TDM_QUAT][TDM_5].sample_rate;
3927 break;
3928 case AFE_PORT_ID_QUATERNARY_TDM_RX_6:
3929 channels->min = channels->max =
3930 tdm_rx_cfg[TDM_QUAT][TDM_6].channels;
3931 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
3932 tdm_rx_cfg[TDM_QUAT][TDM_6].bit_format);
3933 rate->min = rate->max =
3934 tdm_rx_cfg[TDM_QUAT][TDM_6].sample_rate;
3935 break;
3936 case AFE_PORT_ID_QUATERNARY_TDM_RX_7:
3937 channels->min = channels->max =
3938 tdm_rx_cfg[TDM_QUAT][TDM_7].channels;
3939 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
3940 tdm_rx_cfg[TDM_QUAT][TDM_7].bit_format);
3941 rate->min = rate->max =
3942 tdm_rx_cfg[TDM_QUAT][TDM_7].sample_rate;
3943 break;
3944 case AFE_PORT_ID_QUATERNARY_TDM_TX:
3945 channels->min = channels->max =
3946 tdm_tx_cfg[TDM_QUAT][TDM_0].channels;
3947 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
3948 tdm_tx_cfg[TDM_QUAT][TDM_0].bit_format);
3949 rate->min = rate->max =
3950 tdm_tx_cfg[TDM_QUAT][TDM_0].sample_rate;
3951 break;
3952 case AFE_PORT_ID_QUATERNARY_TDM_TX_1:
3953 channels->min = channels->max =
3954 tdm_tx_cfg[TDM_QUAT][TDM_1].channels;
3955 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
3956 tdm_tx_cfg[TDM_QUAT][TDM_1].bit_format);
3957 rate->min = rate->max =
3958 tdm_tx_cfg[TDM_QUAT][TDM_1].sample_rate;
3959 break;
3960 case AFE_PORT_ID_QUATERNARY_TDM_TX_2:
3961 channels->min = channels->max =
3962 tdm_tx_cfg[TDM_QUAT][TDM_2].channels;
3963 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
3964 tdm_tx_cfg[TDM_QUAT][TDM_2].bit_format);
3965 rate->min = rate->max =
3966 tdm_tx_cfg[TDM_QUAT][TDM_2].sample_rate;
3967 break;
3968 case AFE_PORT_ID_QUATERNARY_TDM_TX_3:
3969 channels->min = channels->max =
3970 tdm_tx_cfg[TDM_QUAT][TDM_3].channels;
3971 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
3972 tdm_tx_cfg[TDM_QUAT][TDM_3].bit_format);
3973 rate->min = rate->max =
3974 tdm_tx_cfg[TDM_QUAT][TDM_3].sample_rate;
3975 break;
3976 case AFE_PORT_ID_QUATERNARY_TDM_TX_4:
3977 channels->min = channels->max =
3978 tdm_tx_cfg[TDM_QUAT][TDM_4].channels;
3979 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
3980 tdm_tx_cfg[TDM_QUAT][TDM_4].bit_format);
3981 rate->min = rate->max =
3982 tdm_tx_cfg[TDM_QUAT][TDM_4].sample_rate;
3983 break;
3984 case AFE_PORT_ID_QUATERNARY_TDM_TX_5:
3985 channels->min = channels->max =
3986 tdm_tx_cfg[TDM_QUAT][TDM_5].channels;
3987 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
3988 tdm_tx_cfg[TDM_QUAT][TDM_5].bit_format);
3989 rate->min = rate->max =
3990 tdm_tx_cfg[TDM_QUAT][TDM_5].sample_rate;
3991 break;
3992 case AFE_PORT_ID_QUATERNARY_TDM_TX_6:
3993 channels->min = channels->max =
3994 tdm_tx_cfg[TDM_QUAT][TDM_6].channels;
3995 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
3996 tdm_tx_cfg[TDM_QUAT][TDM_6].bit_format);
3997 rate->min = rate->max =
3998 tdm_tx_cfg[TDM_QUAT][TDM_6].sample_rate;
3999 break;
4000 case AFE_PORT_ID_QUATERNARY_TDM_TX_7:
4001 channels->min = channels->max =
4002 tdm_tx_cfg[TDM_QUAT][TDM_7].channels;
4003 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
4004 tdm_tx_cfg[TDM_QUAT][TDM_7].bit_format);
4005 rate->min = rate->max =
4006 tdm_tx_cfg[TDM_QUAT][TDM_7].sample_rate;
4007 break;
4008 case AFE_PORT_ID_QUINARY_TDM_RX:
4009 channels->min = channels->max =
4010 tdm_rx_cfg[TDM_QUIN][TDM_0].channels;
4011 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
4012 tdm_rx_cfg[TDM_QUIN][TDM_0].bit_format);
4013 rate->min = rate->max =
4014 tdm_rx_cfg[TDM_QUIN][TDM_0].sample_rate;
4015 break;
4016 case AFE_PORT_ID_QUINARY_TDM_RX_1:
4017 channels->min = channels->max =
4018 tdm_rx_cfg[TDM_QUIN][TDM_1].channels;
4019 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
4020 tdm_rx_cfg[TDM_QUIN][TDM_1].bit_format);
4021 rate->min = rate->max =
4022 tdm_rx_cfg[TDM_QUIN][TDM_1].sample_rate;
4023 break;
4024 case AFE_PORT_ID_QUINARY_TDM_RX_2:
4025 channels->min = channels->max =
4026 tdm_rx_cfg[TDM_QUIN][TDM_2].channels;
4027 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
4028 tdm_rx_cfg[TDM_QUIN][TDM_2].bit_format);
4029 rate->min = rate->max =
4030 tdm_rx_cfg[TDM_QUIN][TDM_2].sample_rate;
4031 break;
4032 case AFE_PORT_ID_QUINARY_TDM_RX_3:
4033 channels->min = channels->max =
4034 tdm_rx_cfg[TDM_QUIN][TDM_3].channels;
4035 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
4036 tdm_rx_cfg[TDM_QUIN][TDM_3].bit_format);
4037 rate->min = rate->max =
4038 tdm_rx_cfg[TDM_QUIN][TDM_3].sample_rate;
4039 break;
4040 case AFE_PORT_ID_QUINARY_TDM_RX_4:
4041 channels->min = channels->max =
4042 tdm_rx_cfg[TDM_QUIN][TDM_4].channels;
4043 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
4044 tdm_rx_cfg[TDM_QUIN][TDM_4].bit_format);
4045 rate->min = rate->max =
4046 tdm_rx_cfg[TDM_QUIN][TDM_4].sample_rate;
4047 break;
4048 case AFE_PORT_ID_QUINARY_TDM_RX_5:
4049 channels->min = channels->max =
4050 tdm_rx_cfg[TDM_QUIN][TDM_5].channels;
4051 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
4052 tdm_rx_cfg[TDM_QUIN][TDM_5].bit_format);
4053 rate->min = rate->max =
4054 tdm_rx_cfg[TDM_QUIN][TDM_5].sample_rate;
4055 break;
4056 case AFE_PORT_ID_QUINARY_TDM_RX_6:
4057 channels->min = channels->max =
4058 tdm_rx_cfg[TDM_QUIN][TDM_6].channels;
4059 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
4060 tdm_rx_cfg[TDM_QUIN][TDM_6].bit_format);
4061 rate->min = rate->max =
4062 tdm_rx_cfg[TDM_QUIN][TDM_6].sample_rate;
4063 break;
4064 case AFE_PORT_ID_QUINARY_TDM_RX_7:
4065 channels->min = channels->max =
4066 tdm_rx_cfg[TDM_QUIN][TDM_7].channels;
4067 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
4068 tdm_rx_cfg[TDM_QUIN][TDM_7].bit_format);
4069 rate->min = rate->max =
4070 tdm_rx_cfg[TDM_QUIN][TDM_7].sample_rate;
4071 break;
4072 case AFE_PORT_ID_QUINARY_TDM_TX:
4073 channels->min = channels->max =
4074 tdm_tx_cfg[TDM_QUIN][TDM_0].channels;
4075 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
4076 tdm_tx_cfg[TDM_QUIN][TDM_0].bit_format);
4077 rate->min = rate->max =
4078 tdm_tx_cfg[TDM_QUIN][TDM_0].sample_rate;
4079 break;
4080 case AFE_PORT_ID_QUINARY_TDM_TX_1:
4081 channels->min = channels->max =
4082 tdm_tx_cfg[TDM_QUIN][TDM_1].channels;
4083 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
4084 tdm_tx_cfg[TDM_QUIN][TDM_1].bit_format);
4085 rate->min = rate->max =
4086 tdm_tx_cfg[TDM_QUIN][TDM_1].sample_rate;
4087 break;
4088 case AFE_PORT_ID_QUINARY_TDM_TX_2:
4089 channels->min = channels->max =
4090 tdm_tx_cfg[TDM_QUIN][TDM_2].channels;
4091 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
4092 tdm_tx_cfg[TDM_QUIN][TDM_2].bit_format);
4093 rate->min = rate->max =
4094 tdm_tx_cfg[TDM_QUIN][TDM_2].sample_rate;
4095 break;
4096 case AFE_PORT_ID_QUINARY_TDM_TX_3:
4097 channels->min = channels->max =
4098 tdm_tx_cfg[TDM_QUIN][TDM_3].channels;
4099 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
4100 tdm_tx_cfg[TDM_QUIN][TDM_3].bit_format);
4101 rate->min = rate->max =
4102 tdm_tx_cfg[TDM_QUIN][TDM_3].sample_rate;
4103 break;
4104 case AFE_PORT_ID_QUINARY_TDM_TX_4:
4105 channels->min = channels->max =
4106 tdm_tx_cfg[TDM_QUIN][TDM_4].channels;
4107 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
4108 tdm_tx_cfg[TDM_QUIN][TDM_4].bit_format);
4109 rate->min = rate->max =
4110 tdm_tx_cfg[TDM_QUIN][TDM_4].sample_rate;
4111 break;
4112 case AFE_PORT_ID_QUINARY_TDM_TX_5:
4113 channels->min = channels->max =
4114 tdm_tx_cfg[TDM_QUIN][TDM_5].channels;
4115 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
4116 tdm_tx_cfg[TDM_QUIN][TDM_5].bit_format);
4117 rate->min = rate->max =
4118 tdm_tx_cfg[TDM_QUIN][TDM_5].sample_rate;
4119 break;
4120 case AFE_PORT_ID_QUINARY_TDM_TX_6:
4121 channels->min = channels->max =
4122 tdm_tx_cfg[TDM_QUIN][TDM_6].channels;
4123 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
4124 tdm_tx_cfg[TDM_QUIN][TDM_6].bit_format);
4125 rate->min = rate->max =
4126 tdm_tx_cfg[TDM_QUIN][TDM_6].sample_rate;
4127 break;
4128 case AFE_PORT_ID_QUINARY_TDM_TX_7:
4129 channels->min = channels->max =
4130 tdm_tx_cfg[TDM_QUIN][TDM_7].channels;
4131 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
4132 tdm_tx_cfg[TDM_QUIN][TDM_7].bit_format);
4133 rate->min = rate->max =
4134 tdm_tx_cfg[TDM_QUIN][TDM_7].sample_rate;
4135 break;
4136
4137 default:
4138 pr_err("%s: dai id 0x%x not supported\n",
4139 __func__, cpu_dai->id);
4140 return -EINVAL;
4141 }
4142
4143 pr_debug("%s: dai id = 0x%x channels = %d rate = %d format = 0x%x\n",
4144 __func__, cpu_dai->id, channels->max, rate->max,
4145 params_format(params));
4146
4147 return 0;
4148}
4149EXPORT_SYMBOL(msm_tdm_be_hw_params_fixup);
4150
Asish Bhattacharya84f7f732017-07-25 16:29:27 +0530[diff] [blame]4151static int msm_ext_disp_get_idx_from_beid(int32_t id)
Asish Bhattacharya8e2277f2017-07-20 18:31:55 +0530[diff] [blame]4152{
4153 int idx;
4154
Asish Bhattacharya84f7f732017-07-25 16:29:27 +0530[diff] [blame]4155 switch (id) {
Asish Bhattacharya8e2277f2017-07-20 18:31:55 +0530[diff] [blame]4156 case MSM_BACKEND_DAI_DISPLAY_PORT_RX:
4157 idx = DP_RX_IDX;
4158 break;
4159 default:
Asish Bhattacharya84f7f732017-07-25 16:29:27 +0530[diff] [blame]4160 pr_err("%s: Incorrect ext_disp id %d\n", __func__, id);
Asish Bhattacharya8e2277f2017-07-20 18:31:55 +0530[diff] [blame]4161 idx = -EINVAL;
4162 break;
4163 }
4164
4165 return idx;
4166}
4167
4168/**
4169 * msm_common_be_hw_params_fixup - updates settings of ALSA BE hw params.
4170 *
4171 * @rtd: runtime dailink instance
4172 * @params: HW params of associated backend dailink.
4173 *
4174 * Returns 0.
4175 */
4176int msm_common_be_hw_params_fixup(struct snd_soc_pcm_runtime *rtd,
4177 struct snd_pcm_hw_params *params)
4178{
4179 struct snd_soc_dai_link *dai_link = rtd->dai_link;
4180 struct snd_interval *rate = hw_param_interval(params,
4181 SNDRV_PCM_HW_PARAM_RATE);
4182 struct snd_interval *channels = hw_param_interval(params,
4183 SNDRV_PCM_HW_PARAM_CHANNELS);
4184 int rc = 0;
4185 int idx;
4186
4187 pr_debug("%s: format = %d, rate = %d\n",
4188 __func__, params_format(params), params_rate(params));
4189
Asish Bhattacharya84f7f732017-07-25 16:29:27 +0530[diff] [blame]4190 switch (dai_link->id) {
Asish Bhattacharya8e2277f2017-07-20 18:31:55 +0530[diff] [blame]4191 case MSM_BACKEND_DAI_USB_RX:
4192 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
4193 usb_rx_cfg.bit_format);
4194 rate->min = rate->max = usb_rx_cfg.sample_rate;
4195 channels->min = channels->max = usb_rx_cfg.channels;
4196 break;
4197
4198 case MSM_BACKEND_DAI_USB_TX:
4199 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
4200 usb_tx_cfg.bit_format);
4201 rate->min = rate->max = usb_tx_cfg.sample_rate;
4202 channels->min = channels->max = usb_tx_cfg.channels;
4203 break;
4204
4205 case MSM_BACKEND_DAI_DISPLAY_PORT_RX:
Asish Bhattacharya84f7f732017-07-25 16:29:27 +0530[diff] [blame]4206 idx = msm_ext_disp_get_idx_from_beid(dai_link->id);
4207 if (idx < 0) {
Asish Bhattacharya8e2277f2017-07-20 18:31:55 +0530[diff] [blame]4208 pr_err("%s: Incorrect ext disp idx %d\n",
4209 __func__, idx);
4210 rc = idx;
4211 break;
4212 }
4213
4214 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
4215 ext_disp_rx_cfg[idx].bit_format);
4216 rate->min = rate->max = ext_disp_rx_cfg[idx].sample_rate;
4217 channels->min = channels->max = ext_disp_rx_cfg[idx].channels;
4218 break;
4219
4220 case MSM_BACKEND_DAI_AFE_PCM_RX:
4221 channels->min = channels->max = proxy_rx_cfg.channels;
4222 rate->min = rate->max = SAMPLING_RATE_48KHZ;
4223 break;
4224
4225 case MSM_BACKEND_DAI_PRI_TDM_RX_0:
4226 channels->min = channels->max =
4227 tdm_rx_cfg[TDM_PRI][TDM_0].channels;
4228 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
4229 tdm_rx_cfg[TDM_PRI][TDM_0].bit_format);
4230 rate->min = rate->max = tdm_rx_cfg[TDM_PRI][TDM_0].sample_rate;
4231 break;
4232
4233 case MSM_BACKEND_DAI_PRI_TDM_TX_0:
4234 channels->min = channels->max =
4235 tdm_tx_cfg[TDM_PRI][TDM_0].channels;
4236 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
4237 tdm_tx_cfg[TDM_PRI][TDM_0].bit_format);
4238 rate->min = rate->max = tdm_tx_cfg[TDM_PRI][TDM_0].sample_rate;
4239 break;
4240
4241 case MSM_BACKEND_DAI_SEC_TDM_RX_0:
4242 channels->min = channels->max =
4243 tdm_rx_cfg[TDM_SEC][TDM_0].channels;
4244 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
4245 tdm_rx_cfg[TDM_SEC][TDM_0].bit_format);
4246 rate->min = rate->max = tdm_rx_cfg[TDM_SEC][TDM_0].sample_rate;
4247 break;
4248
4249 case MSM_BACKEND_DAI_SEC_TDM_TX_0:
4250 channels->min = channels->max =
4251 tdm_tx_cfg[TDM_SEC][TDM_0].channels;
4252 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
4253 tdm_tx_cfg[TDM_SEC][TDM_0].bit_format);
4254 rate->min = rate->max = tdm_tx_cfg[TDM_SEC][TDM_0].sample_rate;
4255 break;
4256
4257 case MSM_BACKEND_DAI_TERT_TDM_RX_0:
4258 channels->min = channels->max =
4259 tdm_rx_cfg[TDM_TERT][TDM_0].channels;
4260 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
4261 tdm_rx_cfg[TDM_TERT][TDM_0].bit_format);
4262 rate->min = rate->max = tdm_rx_cfg[TDM_TERT][TDM_0].sample_rate;
4263 break;
4264
4265 case MSM_BACKEND_DAI_TERT_TDM_TX_0:
4266 channels->min = channels->max =
4267 tdm_tx_cfg[TDM_TERT][TDM_0].channels;
4268 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
4269 tdm_tx_cfg[TDM_TERT][TDM_0].bit_format);
4270 rate->min = rate->max = tdm_tx_cfg[TDM_TERT][TDM_0].sample_rate;
4271 break;
4272
4273 case MSM_BACKEND_DAI_QUAT_TDM_RX_0:
4274 channels->min = channels->max =
4275 tdm_rx_cfg[TDM_QUAT][TDM_0].channels;
4276 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
4277 tdm_rx_cfg[TDM_QUAT][TDM_0].bit_format);
4278 rate->min = rate->max = tdm_rx_cfg[TDM_QUAT][TDM_0].sample_rate;
4279 break;
4280
4281 case MSM_BACKEND_DAI_QUAT_TDM_TX_0:
4282 channels->min = channels->max =
4283 tdm_tx_cfg[TDM_QUAT][TDM_0].channels;
4284 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
4285 tdm_tx_cfg[TDM_QUAT][TDM_0].bit_format);
4286 rate->min = rate->max = tdm_tx_cfg[TDM_QUAT][TDM_0].sample_rate;
4287 break;
4288
Rohit Kumard1754482017-09-10 22:57:39 +0530[diff] [blame]4289 case MSM_BACKEND_DAI_QUIN_TDM_RX_0:
4290 channels->min = channels->max =
4291 tdm_rx_cfg[TDM_QUIN][TDM_0].channels;
4292 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
4293 tdm_rx_cfg[TDM_QUIN][TDM_0].bit_format);
4294 rate->min = rate->max = tdm_rx_cfg[TDM_QUIN][TDM_0].sample_rate;
4295 break;
4296
4297 case MSM_BACKEND_DAI_QUIN_TDM_TX_0:
4298 channels->min = channels->max =
4299 tdm_tx_cfg[TDM_QUIN][TDM_0].channels;
4300 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
4301 tdm_tx_cfg[TDM_QUIN][TDM_0].bit_format);
4302 rate->min = rate->max = tdm_tx_cfg[TDM_QUIN][TDM_0].sample_rate;
4303 break;
4304
Asish Bhattacharya8e2277f2017-07-20 18:31:55 +0530[diff] [blame]4305 case MSM_BACKEND_DAI_AUXPCM_RX:
4306 rate->min = rate->max =
4307 aux_pcm_rx_cfg[PRIM_AUX_PCM].sample_rate;
4308 channels->min = channels->max =
4309 aux_pcm_rx_cfg[PRIM_AUX_PCM].channels;
4310 break;
4311
4312 case MSM_BACKEND_DAI_AUXPCM_TX:
4313 rate->min = rate->max =
4314 aux_pcm_tx_cfg[PRIM_AUX_PCM].sample_rate;
4315 channels->min = channels->max =
4316 aux_pcm_tx_cfg[PRIM_AUX_PCM].channels;
4317 break;
4318
4319 case MSM_BACKEND_DAI_SEC_AUXPCM_RX:
4320 rate->min = rate->max =
4321 aux_pcm_rx_cfg[SEC_AUX_PCM].sample_rate;
4322 channels->min = channels->max =
4323 aux_pcm_rx_cfg[SEC_AUX_PCM].channels;
4324 break;
4325
4326 case MSM_BACKEND_DAI_SEC_AUXPCM_TX:
4327 rate->min = rate->max =
4328 aux_pcm_tx_cfg[SEC_AUX_PCM].sample_rate;
4329 channels->min = channels->max =
4330 aux_pcm_tx_cfg[SEC_AUX_PCM].channels;
4331 break;
4332
4333 case MSM_BACKEND_DAI_TERT_AUXPCM_RX:
4334 rate->min = rate->max =
4335 aux_pcm_rx_cfg[TERT_AUX_PCM].sample_rate;
4336 channels->min = channels->max =
4337 aux_pcm_rx_cfg[TERT_AUX_PCM].channels;
4338 break;
4339
4340 case MSM_BACKEND_DAI_TERT_AUXPCM_TX:
4341 rate->min = rate->max =
4342 aux_pcm_tx_cfg[TERT_AUX_PCM].sample_rate;
4343 channels->min = channels->max =
4344 aux_pcm_tx_cfg[TERT_AUX_PCM].channels;
4345 break;
4346
4347 case MSM_BACKEND_DAI_QUAT_AUXPCM_RX:
4348 rate->min = rate->max =
4349 aux_pcm_rx_cfg[QUAT_AUX_PCM].sample_rate;
4350 channels->min = channels->max =
4351 aux_pcm_rx_cfg[QUAT_AUX_PCM].channels;
4352 break;
4353
4354 case MSM_BACKEND_DAI_QUAT_AUXPCM_TX:
4355 rate->min = rate->max =
4356 aux_pcm_tx_cfg[QUAT_AUX_PCM].sample_rate;
4357 channels->min = channels->max =
4358 aux_pcm_tx_cfg[QUAT_AUX_PCM].channels;
4359 break;
4360
Rohit Kumard1754482017-09-10 22:57:39 +0530[diff] [blame]4361 case MSM_BACKEND_DAI_QUIN_AUXPCM_RX:
4362 rate->min = rate->max =
4363 aux_pcm_rx_cfg[QUIN_AUX_PCM].sample_rate;
4364 channels->min = channels->max =
4365 aux_pcm_rx_cfg[QUIN_AUX_PCM].channels;
4366 break;
4367
4368 case MSM_BACKEND_DAI_QUIN_AUXPCM_TX:
4369 rate->min = rate->max =
4370 aux_pcm_tx_cfg[QUIN_AUX_PCM].sample_rate;
4371 channels->min = channels->max =
4372 aux_pcm_tx_cfg[QUIN_AUX_PCM].channels;
4373 break;
4374
Asish Bhattacharya8e2277f2017-07-20 18:31:55 +0530[diff] [blame]4375 case MSM_BACKEND_DAI_PRI_MI2S_RX:
4376 rate->min = rate->max = mi2s_rx_cfg[PRIM_MI2S].sample_rate;
4377 channels->min = channels->max =
4378 mi2s_rx_cfg[PRIM_MI2S].channels;
4379 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
4380 mi2s_rx_cfg[PRIM_MI2S].bit_format);
4381 break;
4382
4383 case MSM_BACKEND_DAI_PRI_MI2S_TX:
4384 rate->min = rate->max = mi2s_tx_cfg[PRIM_MI2S].sample_rate;
4385 channels->min = channels->max =
4386 mi2s_tx_cfg[PRIM_MI2S].channels;
4387 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
4388 mi2s_tx_cfg[PRIM_MI2S].bit_format);
4389 break;
4390
4391 case MSM_BACKEND_DAI_SECONDARY_MI2S_RX:
4392 rate->min = rate->max = mi2s_rx_cfg[SEC_MI2S].sample_rate;
4393 channels->min = channels->max =
4394 mi2s_rx_cfg[SEC_MI2S].channels;
4395 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
4396 mi2s_rx_cfg[SEC_MI2S].bit_format);
4397 break;
4398
4399 case MSM_BACKEND_DAI_SECONDARY_MI2S_TX:
4400 rate->min = rate->max = mi2s_tx_cfg[SEC_MI2S].sample_rate;
4401 channels->min = channels->max =
4402 mi2s_tx_cfg[SEC_MI2S].channels;
4403 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
4404 mi2s_tx_cfg[SEC_MI2S].bit_format);
4405 break;
4406
4407 case MSM_BACKEND_DAI_TERTIARY_MI2S_RX:
4408 rate->min = rate->max = mi2s_rx_cfg[TERT_MI2S].sample_rate;
4409 channels->min = channels->max =
4410 mi2s_rx_cfg[TERT_MI2S].channels;
4411 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
4412 mi2s_rx_cfg[TERT_MI2S].bit_format);
4413 break;
4414
4415 case MSM_BACKEND_DAI_TERTIARY_MI2S_TX:
4416 rate->min = rate->max = mi2s_tx_cfg[TERT_MI2S].sample_rate;
4417 channels->min = channels->max =
4418 mi2s_tx_cfg[TERT_MI2S].channels;
4419 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
4420 mi2s_tx_cfg[TERT_MI2S].bit_format);
4421 break;
4422
4423 case MSM_BACKEND_DAI_QUATERNARY_MI2S_RX:
4424 rate->min = rate->max = mi2s_rx_cfg[QUAT_MI2S].sample_rate;
4425 channels->min = channels->max =
4426 mi2s_rx_cfg[QUAT_MI2S].channels;
4427 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
4428 mi2s_rx_cfg[QUAT_MI2S].bit_format);
4429 break;
4430
4431 case MSM_BACKEND_DAI_QUATERNARY_MI2S_TX:
4432 rate->min = rate->max = mi2s_tx_cfg[QUAT_MI2S].sample_rate;
4433 channels->min = channels->max =
4434 mi2s_tx_cfg[QUAT_MI2S].channels;
4435 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
4436 mi2s_tx_cfg[QUAT_MI2S].bit_format);
4437 break;
4438
Rohit Kumard1754482017-09-10 22:57:39 +0530[diff] [blame]4439 case MSM_BACKEND_DAI_QUINARY_MI2S_RX:
4440 rate->min = rate->max = mi2s_rx_cfg[QUIN_MI2S].sample_rate;
4441 channels->min = channels->max =
4442 mi2s_rx_cfg[QUIN_MI2S].channels;
4443 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
4444 mi2s_rx_cfg[QUIN_MI2S].bit_format);
4445 break;
4446
4447 case MSM_BACKEND_DAI_QUINARY_MI2S_TX:
4448 rate->min = rate->max = mi2s_tx_cfg[QUIN_MI2S].sample_rate;
4449 channels->min = channels->max =
4450 mi2s_tx_cfg[QUIN_MI2S].channels;
4451 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
4452 mi2s_tx_cfg[QUIN_MI2S].bit_format);
4453 break;
4454
Asish Bhattacharya8e2277f2017-07-20 18:31:55 +0530[diff] [blame]4455 default:
4456 rate->min = rate->max = SAMPLING_RATE_48KHZ;
4457 break;
4458 }
4459 return rc;
4460}
4461EXPORT_SYMBOL(msm_common_be_hw_params_fixup);
4462
4463/**
4464 * msm_aux_pcm_snd_startup - startup ops of auxpcm.
4465 *
4466 * @substream: PCM stream pointer of associated backend dailink
4467 *
4468 * Returns 0 on success or -EINVAL on error.
4469 */
4470int msm_aux_pcm_snd_startup(struct snd_pcm_substream *substream)
4471{
4472 struct snd_soc_pcm_runtime *rtd = substream->private_data;
4473
4474 dev_dbg(rtd->card->dev,
4475 "%s: substream = %s stream = %d, dai name %s, dai ID %d\n",
4476 __func__, substream->name, substream->stream,
4477 rtd->cpu_dai->name, rtd->cpu_dai->id);
4478
4479 return 0;
4480}
4481EXPORT_SYMBOL(msm_aux_pcm_snd_startup);
4482
4483/**
4484 * msm_aux_pcm_snd_shutdown - shutdown ops of auxpcm.
4485 *
4486 * @substream: PCM stream pointer of associated backend dailink
4487 */
4488void msm_aux_pcm_snd_shutdown(struct snd_pcm_substream *substream)
4489{
4490 struct snd_soc_pcm_runtime *rtd = substream->private_data;
4491
4492 dev_dbg(rtd->card->dev,
4493 "%s: substream = %s stream = %d, dai name %s, dai ID %d\n",
4494 __func__,
4495 substream->name, substream->stream,
4496 rtd->cpu_dai->name, rtd->cpu_dai->id);
4497}
4498EXPORT_SYMBOL(msm_aux_pcm_snd_shutdown);
4499
Asish Bhattacharya84f7f732017-07-25 16:29:27 +0530[diff] [blame]4500static int msm_get_port_id(int id)
Asish Bhattacharya8e2277f2017-07-20 18:31:55 +0530[diff] [blame]4501{
4502 int afe_port_id;
4503
Asish Bhattacharya84f7f732017-07-25 16:29:27 +0530[diff] [blame]4504 switch (id) {
Asish Bhattacharya8e2277f2017-07-20 18:31:55 +0530[diff] [blame]4505 case MSM_BACKEND_DAI_PRI_MI2S_RX:
4506 afe_port_id = AFE_PORT_ID_PRIMARY_MI2S_RX;
4507 break;
4508 case MSM_BACKEND_DAI_PRI_MI2S_TX:
4509 afe_port_id = AFE_PORT_ID_PRIMARY_MI2S_TX;
4510 break;
4511 case MSM_BACKEND_DAI_SECONDARY_MI2S_RX:
4512 afe_port_id = AFE_PORT_ID_SECONDARY_MI2S_RX;
4513 break;
4514 case MSM_BACKEND_DAI_SECONDARY_MI2S_TX:
4515 afe_port_id = AFE_PORT_ID_SECONDARY_MI2S_TX;
4516 break;
4517 case MSM_BACKEND_DAI_TERTIARY_MI2S_RX:
4518 afe_port_id = AFE_PORT_ID_TERTIARY_MI2S_RX;
4519 break;
4520 case MSM_BACKEND_DAI_TERTIARY_MI2S_TX:
4521 afe_port_id = AFE_PORT_ID_TERTIARY_MI2S_TX;
4522 break;
4523 case MSM_BACKEND_DAI_QUATERNARY_MI2S_RX:
4524 afe_port_id = AFE_PORT_ID_QUATERNARY_MI2S_RX;
4525 break;
4526 case MSM_BACKEND_DAI_QUATERNARY_MI2S_TX:
4527 afe_port_id = AFE_PORT_ID_QUATERNARY_MI2S_TX;
4528 break;
Rohit Kumard1754482017-09-10 22:57:39 +0530[diff] [blame]4529 case MSM_BACKEND_DAI_QUINARY_MI2S_RX:
4530 afe_port_id = AFE_PORT_ID_QUINARY_MI2S_RX;
4531 break;
4532 case MSM_BACKEND_DAI_QUINARY_MI2S_TX:
4533 afe_port_id = AFE_PORT_ID_QUINARY_MI2S_TX;
4534 break;
Asish Bhattacharya8e2277f2017-07-20 18:31:55 +0530[diff] [blame]4535 default:
Asish Bhattacharya84f7f732017-07-25 16:29:27 +0530[diff] [blame]4536 pr_err("%s: Invalid id: %d\n", __func__, id);
Asish Bhattacharya8e2277f2017-07-20 18:31:55 +0530[diff] [blame]4537 afe_port_id = -EINVAL;
4538 }
4539
4540 return afe_port_id;
4541}
4542
4543static u32 get_mi2s_bits_per_sample(u32 bit_format)
4544{
4545 u32 bit_per_sample;
4546
4547 switch (bit_format) {
4548 case SNDRV_PCM_FORMAT_S32_LE:
4549 case SNDRV_PCM_FORMAT_S24_3LE:
4550 case SNDRV_PCM_FORMAT_S24_LE:
4551 bit_per_sample = 32;
4552 break;
4553 case SNDRV_PCM_FORMAT_S16_LE:
4554 default:
4555 bit_per_sample = 16;
4556 break;
4557 }
4558
4559 return bit_per_sample;
4560}
4561
4562static void update_mi2s_clk_val(int dai_id, int stream)
4563{
4564 u32 bit_per_sample;
4565
4566 if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
4567 bit_per_sample =
4568 get_mi2s_bits_per_sample(mi2s_rx_cfg[dai_id].bit_format);
4569 mi2s_clk[dai_id].clk_freq_in_hz =
4570 mi2s_rx_cfg[dai_id].sample_rate * 2 * bit_per_sample;
4571 } else {
4572 bit_per_sample =
4573 get_mi2s_bits_per_sample(mi2s_tx_cfg[dai_id].bit_format);
4574 mi2s_clk[dai_id].clk_freq_in_hz =
4575 mi2s_tx_cfg[dai_id].sample_rate * 2 * bit_per_sample;
4576 }
4577}
4578
4579static int msm_mi2s_set_sclk(struct snd_pcm_substream *substream, bool enable)
4580{
4581 int ret = 0;
4582 struct snd_soc_pcm_runtime *rtd = substream->private_data;
4583 struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
4584 int port_id = 0;
4585 int index = cpu_dai->id;
4586
Asish Bhattacharya84f7f732017-07-25 16:29:27 +0530[diff] [blame]4587 port_id = msm_get_port_id(rtd->dai_link->id);
Asish Bhattacharya8e2277f2017-07-20 18:31:55 +0530[diff] [blame]4588 if (port_id < 0) {
4589 dev_err(rtd->card->dev, "%s: Invalid port_id\n", __func__);
4590 ret = port_id;
4591 goto done;
4592 }
4593
4594 if (enable) {
4595 update_mi2s_clk_val(index, substream->stream);
4596 dev_dbg(rtd->card->dev, "%s: clock rate %ul\n", __func__,
4597 mi2s_clk[index].clk_freq_in_hz);
4598 }
4599
4600 mi2s_clk[index].enable = enable;
4601 ret = afe_set_lpass_clock_v2(port_id,
4602 &mi2s_clk[index]);
4603 if (ret < 0) {
4604 dev_err(rtd->card->dev,
4605 "%s: afe lpass clock failed for port 0x%x , err:%d\n",
4606 __func__, port_id, ret);
4607 goto done;
4608 }
4609
4610done:
4611 return ret;
4612}
4613
4614/**
4615 * msm_mi2s_snd_startup - startup ops of mi2s.
4616 *
4617 * @substream: PCM stream pointer of associated backend dailink
4618 *
4619 * Returns 0 on success or -EINVAL on error.
4620 */
4621int msm_mi2s_snd_startup(struct snd_pcm_substream *substream)
4622{
4623 int ret = 0;
4624 struct snd_soc_pcm_runtime *rtd = substream->private_data;
4625 struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
Asish Bhattacharya84f7f732017-07-25 16:29:27 +0530[diff] [blame]4626 int port_id = msm_get_port_id(rtd->dai_link->id);
Asish Bhattacharya8e2277f2017-07-20 18:31:55 +0530[diff] [blame]4627 int index = cpu_dai->id;
4628 unsigned int fmt = SND_SOC_DAIFMT_CBS_CFS;
Rohit Kumaraf88e4c2017-10-04 13:47:10 +0530[diff] [blame]4629 struct msm_asoc_mach_data *pdata =
4630 snd_soc_card_get_drvdata(rtd->card);
Asish Bhattacharya8e2277f2017-07-20 18:31:55 +0530[diff] [blame]4631
4632 dev_dbg(rtd->card->dev,
4633 "%s: substream = %s stream = %d, dai name %s, dai ID %d\n",
4634 __func__, substream->name, substream->stream,
4635 cpu_dai->name, cpu_dai->id);
4636
Rohit Kumard1754482017-09-10 22:57:39 +0530[diff] [blame]4637 if (index < PRIM_MI2S || index >= MI2S_MAX) {
Asish Bhattacharya8e2277f2017-07-20 18:31:55 +0530[diff] [blame]4638 ret = -EINVAL;
4639 dev_err(rtd->card->dev,
4640 "%s: CPU DAI id (%d) out of range\n",
4641 __func__, cpu_dai->id);
4642 goto done;
4643 }
4644 /*
4645 * Muxtex protection in case the same MI2S
4646 * interface using for both TX and RX so
4647 * that the same clock won't be enable twice.
4648 */
4649 mutex_lock(&mi2s_intf_conf[index].lock);
4650 if (++mi2s_intf_conf[index].ref_cnt == 1) {
4651 /* Check if msm needs to provide the clock to the interface */
4652 if (!mi2s_intf_conf[index].msm_is_mi2s_master) {
4653 mi2s_clk[index].clk_id = mi2s_ebit_clk[index];
4654 fmt = SND_SOC_DAIFMT_CBM_CFM;
4655 }
4656 ret = msm_mi2s_set_sclk(substream, true);
4657 if (ret < 0) {
4658 dev_err(rtd->card->dev,
4659 "%s: afe lpass clock failed to enable MI2S clock, err:%d\n",
4660 __func__, ret);
4661 goto clean_up;
4662 }
4663 ret = snd_soc_dai_set_fmt(cpu_dai, fmt);
4664 if (ret < 0) {
4665 dev_err(rtd->card->dev,
4666 "%s: set fmt cpu dai failed for MI2S (%d), err:%d\n",
4667 __func__, index, ret);
4668 goto clk_off;
4669 }
4670 if (mi2s_intf_conf[index].msm_is_ext_mclk) {
4671 mi2s_mclk[index].enable = 1;
4672 pr_debug("%s: Enabling mclk, clk_freq_in_hz = %u\n",
4673 __func__, mi2s_mclk[index].clk_freq_in_hz);
4674 ret = afe_set_lpass_clock_v2(port_id,
4675 &mi2s_mclk[index]);
4676 if (ret < 0) {
4677 pr_err("%s: afe lpass mclk failed, err:%d\n",
4678 __func__, ret);
4679 goto clk_off;
4680 }
4681 }
Rohit Kumaraf88e4c2017-10-04 13:47:10 +0530[diff] [blame]4682 if (pdata->mi2s_gpio_p[index])
4683 msm_cdc_pinctrl_select_active_state(
4684 pdata->mi2s_gpio_p[index]);
Asish Bhattacharya8e2277f2017-07-20 18:31:55 +0530[diff] [blame]4685 }
4686 mutex_unlock(&mi2s_intf_conf[index].lock);
4687 return 0;
4688clk_off:
4689 if (ret < 0)
4690 msm_mi2s_set_sclk(substream, false);
4691clean_up:
4692 if (ret < 0)
4693 mi2s_intf_conf[index].ref_cnt--;
4694 mutex_unlock(&mi2s_intf_conf[index].lock);
4695done:
4696 return ret;
4697}
4698EXPORT_SYMBOL(msm_mi2s_snd_startup);
4699
4700/**
4701 * msm_mi2s_snd_shutdown - shutdown ops of mi2s.
4702 *
4703 * @substream: PCM stream pointer of associated backend dailink
4704 */
4705void msm_mi2s_snd_shutdown(struct snd_pcm_substream *substream)
4706{
4707 int ret;
4708 struct snd_soc_pcm_runtime *rtd = substream->private_data;
Asish Bhattacharya84f7f732017-07-25 16:29:27 +0530[diff] [blame]4709 int port_id = msm_get_port_id(rtd->dai_link->id);
Asish Bhattacharya8e2277f2017-07-20 18:31:55 +0530[diff] [blame]4710 int index = rtd->cpu_dai->id;
Rohit Kumaraf88e4c2017-10-04 13:47:10 +0530[diff] [blame]4711 struct msm_asoc_mach_data *pdata =
4712 snd_soc_card_get_drvdata(rtd->card);
Asish Bhattacharya8e2277f2017-07-20 18:31:55 +0530[diff] [blame]4713
4714 pr_debug("%s(): substream = %s stream = %d\n", __func__,
4715 substream->name, substream->stream);
Rohit Kumard1754482017-09-10 22:57:39 +0530[diff] [blame]4716 if (index < PRIM_MI2S || index >= MI2S_MAX) {
Asish Bhattacharya8e2277f2017-07-20 18:31:55 +0530[diff] [blame]4717 pr_err("%s:invalid MI2S DAI(%d)\n", __func__, index);
4718 return;
4719 }
4720
4721 mutex_lock(&mi2s_intf_conf[index].lock);
4722 if (--mi2s_intf_conf[index].ref_cnt == 0) {
Rohit Kumaraf88e4c2017-10-04 13:47:10 +0530[diff] [blame]4723 if (pdata->mi2s_gpio_p[index])
4724 msm_cdc_pinctrl_select_sleep_state(
4725 pdata->mi2s_gpio_p[index]);
4726
Asish Bhattacharya8e2277f2017-07-20 18:31:55 +0530[diff] [blame]4727 ret = msm_mi2s_set_sclk(substream, false);
Aditya Bavanarib68d1022018-01-08 19:14:41 +0530[diff] [blame]4728 if (ret < 0)
Asish Bhattacharya8e2277f2017-07-20 18:31:55 +0530[diff] [blame]4729 pr_err("%s:clock disable failed for MI2S (%d); ret=%d\n",
4730 __func__, index, ret);
Aditya Bavanarib68d1022018-01-08 19:14:41 +0530[diff] [blame]4731
Asish Bhattacharya8e2277f2017-07-20 18:31:55 +0530[diff] [blame]4732 if (mi2s_intf_conf[index].msm_is_ext_mclk) {
4733 mi2s_mclk[index].enable = 0;
4734 pr_debug("%s: Disabling mclk, clk_freq_in_hz = %u\n",
4735 __func__, mi2s_mclk[index].clk_freq_in_hz);
4736 ret = afe_set_lpass_clock_v2(port_id,
4737 &mi2s_mclk[index]);
4738 if (ret < 0) {
4739 pr_err("%s: mclk disable failed for MCLK (%d); ret=%d\n",
4740 __func__, index, ret);
4741 }
4742 }
4743 }
4744 mutex_unlock(&mi2s_intf_conf[index].lock);
4745}
4746EXPORT_SYMBOL(msm_mi2s_snd_shutdown);
4747
Soumya Managolibbeb8ee2019-03-18 17:05:29 +0530[diff] [blame]4748static int msm_get_tdm_mode(u32 port_id)
4749{
4750 int tdm_mode;
4751
4752 switch (port_id) {
4753 case AFE_PORT_ID_PRIMARY_TDM_RX:
4754 case AFE_PORT_ID_PRIMARY_TDM_TX:
4755 tdm_mode = TDM_PRI;
Dhanalakshmi Siddanid70a4f72019-11-27 15:35:41 +0530[diff] [blame]4756 break;
Soumya Managolibbeb8ee2019-03-18 17:05:29 +0530[diff] [blame]4757 case AFE_PORT_ID_SECONDARY_TDM_RX:
4758 case AFE_PORT_ID_SECONDARY_TDM_TX:
4759 tdm_mode = TDM_SEC;
Dhanalakshmi Siddanid70a4f72019-11-27 15:35:41 +0530[diff] [blame]4760 break;
Soumya Managolibbeb8ee2019-03-18 17:05:29 +0530[diff] [blame]4761 case AFE_PORT_ID_TERTIARY_TDM_RX:
4762 case AFE_PORT_ID_TERTIARY_TDM_TX:
4763 tdm_mode = TDM_TERT;
Dhanalakshmi Siddanid70a4f72019-11-27 15:35:41 +0530[diff] [blame]4764 break;
Soumya Managolibbeb8ee2019-03-18 17:05:29 +0530[diff] [blame]4765 case AFE_PORT_ID_QUATERNARY_TDM_RX:
4766 case AFE_PORT_ID_QUATERNARY_TDM_TX:
4767 tdm_mode = TDM_QUAT;
Dhanalakshmi Siddanid70a4f72019-11-27 15:35:41 +0530[diff] [blame]4768 break;
Soumya Managolibbeb8ee2019-03-18 17:05:29 +0530[diff] [blame]4769 case AFE_PORT_ID_QUINARY_TDM_RX:
4770 case AFE_PORT_ID_QUINARY_TDM_TX:
4771 tdm_mode = TDM_QUIN;
Dhanalakshmi Siddanid70a4f72019-11-27 15:35:41 +0530[diff] [blame]4772 break;
Soumya Managolibbeb8ee2019-03-18 17:05:29 +0530[diff] [blame]4773 default:
4774 pr_err("%s: Invalid port id: %d\n", __func__, port_id);
4775 tdm_mode = -EINVAL;
4776 }
4777 return tdm_mode;
4778}
4779
4780int msm_tdm_snd_startup(struct snd_pcm_substream *substream)
4781{
4782 int ret = 0;
4783 struct snd_soc_pcm_runtime *rtd = substream->private_data;
4784 struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
4785 struct snd_soc_card *card = rtd->card;
4786 struct msm_asoc_mach_data *pdata = snd_soc_card_get_drvdata(card);
4787 struct tdm_dai_data *dai_data = dev_get_drvdata(cpu_dai->dev);
4788 int tdm_mode = msm_get_tdm_mode(cpu_dai->id);
4789
4790 if (tdm_mode < 0) {
4791 dev_err(rtd->card->dev, "%s: Invalid tdm_mode\n", __func__);
4792 return tdm_mode;
4793 }
4794 dai_data->clk_set.enable = true;
4795 ret = afe_set_lpass_clock_v2(cpu_dai->id, &dai_data->clk_set);
4796 if (ret < 0)
4797 pr_err("%s: afe lpass clock failed, err:%d\n",
4798 __func__, ret);
4799 /* currently only supporting TDM_RX_0 and TDM_TX_0 */
4800 if (pdata->mi2s_gpio_p[tdm_mode])
4801 ret = msm_cdc_pinctrl_select_active_state(
4802 pdata->mi2s_gpio_p[tdm_mode]);
4803 return ret;
4804}
4805EXPORT_SYMBOL(msm_tdm_snd_startup);
4806
4807void msm_tdm_snd_shutdown(struct snd_pcm_substream *substream)
4808{
4809 struct snd_soc_pcm_runtime *rtd = substream->private_data;
4810 struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
4811 struct snd_soc_card *card = rtd->card;
4812 struct msm_asoc_mach_data *pdata = snd_soc_card_get_drvdata(card);
4813 struct tdm_dai_data *dai_data = dev_get_drvdata(cpu_dai->dev);
4814 int tdm_mode = msm_get_tdm_mode(cpu_dai->id);
4815 int ret;
4816
4817 if (tdm_mode < 0) {
4818 dev_err(rtd->card->dev, "%s: Invalid tdm_mode\n", __func__);
4819 return;
4820 }
4821 dai_data->clk_set.enable = false;
4822 ret = afe_set_lpass_clock_v2(cpu_dai->id, &dai_data->clk_set);
4823 if (ret < 0)
4824 pr_err("%s: afe lpass clock failed, err:%d\n", __func__, ret);
4825
4826 /* currently only supporting TDM_RX_0 and TDM_TX_0 */
4827 if (pdata->mi2s_gpio_p[tdm_mode])
4828 msm_cdc_pinctrl_select_sleep_state(
4829 pdata->mi2s_gpio_p[tdm_mode]);
4830}
4831EXPORT_SYMBOL(msm_tdm_snd_shutdown);
4832
Asish Bhattacharya8e2277f2017-07-20 18:31:55 +0530[diff] [blame]4833/* Validate whether US EU switch is present or not */
4834static int msm_prepare_us_euro(struct snd_soc_card *card)
4835{
4836 struct msm_asoc_mach_data *pdata =
4837 snd_soc_card_get_drvdata(card);
4838 int ret = 0;
4839
4840 if (pdata->us_euro_gpio >= 0) {
4841 dev_dbg(card->dev, "%s: us_euro gpio request %d", __func__,
4842 pdata->us_euro_gpio);
4843 ret = gpio_request(pdata->us_euro_gpio, "TASHA_CODEC_US_EURO");
4844 if (ret) {
4845 dev_err(card->dev,
4846 "%s: Failed to request codec US/EURO gpio %d error %d\n",
4847 __func__, pdata->us_euro_gpio, ret);
4848 }
4849 }
4850
4851 return ret;
4852}
4853
Vatsal Bucha42dd4022017-12-07 14:35:59 +0530[diff] [blame]4854
4855static bool msm_usbc_swap_gnd_mic(struct snd_soc_codec *codec, bool active)
4856{
4857 int value = 0;
4858 bool ret = false;
4859 struct snd_soc_card *card = codec->component.card;
4860 struct msm_asoc_mach_data *pdata = snd_soc_card_get_drvdata(card);
4861 struct pinctrl_state *en2_pinctrl_active;
4862 struct pinctrl_state *en2_pinctrl_sleep;
4863
4864 if (!pdata->usbc_en2_gpio_p) {
4865 if (active) {
4866 /* if active and usbc_en2_gpio undefined, get pin */
4867 pdata->usbc_en2_gpio_p = devm_pinctrl_get(card->dev);
4868 if (IS_ERR_OR_NULL(pdata->usbc_en2_gpio_p)) {
4869 dev_err(card->dev,
4870 "%s: Can't get EN2 gpio pinctrl:%ld\n",
4871 __func__,
4872 PTR_ERR(pdata->usbc_en2_gpio_p));
4873 pdata->usbc_en2_gpio_p = NULL;
4874 return false;
4875 }
4876 } else {
4877 /* if not active and usbc_en2_gpio undefined, return */
4878 return false;
4879 }
4880 }
4881
4882 pdata->usbc_en2_gpio = of_get_named_gpio(card->dev->of_node,
4883 "qcom,usbc-analog-en2-gpio", 0);
4884 if (!gpio_is_valid(pdata->usbc_en2_gpio)) {
4885 dev_err(card->dev, "%s, property %s not in node %s\n",
4886 __func__, "qcom,usbc-analog-en2-gpio",
4887 card->dev->of_node->full_name);
4888 return false;
4889 }
4890
4891 en2_pinctrl_active = pinctrl_lookup_state(
4892 pdata->usbc_en2_gpio_p, "aud_active");
4893 if (IS_ERR_OR_NULL(en2_pinctrl_active)) {
4894 dev_err(card->dev,
4895 "%s: Cannot get aud_active pinctrl state:%ld\n",
4896 __func__, PTR_ERR(en2_pinctrl_active));
4897 ret = false;
4898 goto err_lookup_state;
4899 }
4900
4901 en2_pinctrl_sleep = pinctrl_lookup_state(
4902 pdata->usbc_en2_gpio_p, "aud_sleep");
4903 if (IS_ERR_OR_NULL(en2_pinctrl_sleep)) {
4904 dev_err(card->dev,
4905 "%s: Cannot get aud_sleep pinctrl state:%ld\n",
4906 __func__, PTR_ERR(en2_pinctrl_sleep));
4907 ret = false;
4908 goto err_lookup_state;
4909 }
4910
4911 /* if active and usbc_en2_gpio_p defined, swap using usbc_en2_gpio_p */
4912 if (active) {
4913 dev_dbg(codec->dev, "%s: enter\n", __func__);
4914 if (pdata->usbc_en2_gpio_p) {
4915 value = gpio_get_value_cansleep(pdata->usbc_en2_gpio);
4916 if (value)
4917 pinctrl_select_state(pdata->usbc_en2_gpio_p,
4918 en2_pinctrl_sleep);
4919 else
4920 pinctrl_select_state(pdata->usbc_en2_gpio_p,
4921 en2_pinctrl_active);
4922 } else if (pdata->usbc_en2_gpio >= 0) {
4923 value = gpio_get_value_cansleep(pdata->usbc_en2_gpio);
4924 gpio_set_value_cansleep(pdata->usbc_en2_gpio, !value);
4925 }
4926 pr_debug("%s: swap select switch %d to %d\n", __func__,
4927 value, !value);
4928 ret = true;
4929 } else {
4930 /* if not active, release usbc_en2_gpio_p pin */
4931 pinctrl_select_state(pdata->usbc_en2_gpio_p,
4932 en2_pinctrl_sleep);
4933 }
4934
4935err_lookup_state:
4936 devm_pinctrl_put(pdata->usbc_en2_gpio_p);
4937 pdata->usbc_en2_gpio_p = NULL;
4938 return ret;
4939}
4940
Asish Bhattacharya84f7f732017-07-25 16:29:27 +0530[diff] [blame]4941static bool msm_swap_gnd_mic(struct snd_soc_codec *codec, bool active)
Asish Bhattacharya8e2277f2017-07-20 18:31:55 +0530[diff] [blame]4942{
4943 struct snd_soc_card *card = codec->component.card;
4944 struct msm_asoc_mach_data *pdata =
4945 snd_soc_card_get_drvdata(card);
4946 int value = 0;
Vatsal Bucha42dd4022017-12-07 14:35:59 +0530[diff] [blame]4947 bool ret = 0;
Asish Bhattacharya8e2277f2017-07-20 18:31:55 +0530[diff] [blame]4948
Vatsal Bucha42dd4022017-12-07 14:35:59 +0530[diff] [blame]4949 if (!mbhc_cfg.enable_usbc_analog) {
4950 if (pdata->us_euro_gpio_p) {
4951 value = msm_cdc_pinctrl_get_state(
4952 pdata->us_euro_gpio_p);
4953 if (value)
4954 msm_cdc_pinctrl_select_sleep_state(
Asish Bhattacharya8e2277f2017-07-20 18:31:55 +0530[diff] [blame]4955 pdata->us_euro_gpio_p);
Vatsal Bucha42dd4022017-12-07 14:35:59 +0530[diff] [blame]4956 else
4957 msm_cdc_pinctrl_select_active_state(
Asish Bhattacharya8e2277f2017-07-20 18:31:55 +0530[diff] [blame]4958 pdata->us_euro_gpio_p);
Vatsal Bucha42dd4022017-12-07 14:35:59 +0530[diff] [blame]4959 } else if (pdata->us_euro_gpio >= 0) {
4960 value = gpio_get_value_cansleep(pdata->us_euro_gpio);
4961 gpio_set_value_cansleep(pdata->us_euro_gpio, !value);
4962 }
4963 pr_debug("%s: swap select switch %d to %d\n",
4964 __func__, value, !value);
4965 ret = true;
4966 } else {
4967 /* if usbc is defined, swap using usbc_en2 */
4968 ret = msm_usbc_swap_gnd_mic(codec, active);
Asish Bhattacharya8e2277f2017-07-20 18:31:55 +0530[diff] [blame]4969 }
Vatsal Bucha42dd4022017-12-07 14:35:59 +0530[diff] [blame]4970 return ret;
Asish Bhattacharya8e2277f2017-07-20 18:31:55 +0530[diff] [blame]4971}
4972
4973static int msm_populate_dai_link_component_of_node(
4974 struct msm_asoc_mach_data *pdata,
4975 struct snd_soc_card *card)
4976{
4977 int i, index, ret = 0;
4978 struct device *cdev = card->dev;
4979 struct snd_soc_dai_link *dai_link = card->dai_link;
4980 struct device_node *phandle;
4981
4982 if (!cdev) {
4983 pr_err("%s: Sound card device memory NULL\n", __func__);
4984 return -ENODEV;
4985 }
4986
4987 for (i = 0; i < card->num_links; i++) {
4988 if (dai_link[i].platform_of_node && dai_link[i].cpu_of_node)
4989 continue;
4990
4991 /* populate platform_of_node for snd card dai links */
4992 if (dai_link[i].platform_name &&
4993 !dai_link[i].platform_of_node) {
4994 index = of_property_match_string(cdev->of_node,
4995 "asoc-platform-names",
4996 dai_link[i].platform_name);
4997 if (index < 0) {
4998 pr_err("%s: No match found for platform name: %s\n",
4999 __func__, dai_link[i].platform_name);
5000 ret = index;
5001 goto cpu_dai;
5002 }
5003 phandle = of_parse_phandle(cdev->of_node,
5004 "asoc-platform",
5005 index);
5006 if (!phandle) {
5007 pr_err("%s: retrieving phandle for platform %s, index %d failed\n",
5008 __func__, dai_link[i].platform_name,
5009 index);
5010 ret = -ENODEV;
5011 goto err;
5012 }
5013 dai_link[i].platform_of_node = phandle;
5014 dai_link[i].platform_name = NULL;
5015 }
5016cpu_dai:
5017 /* populate cpu_of_node for snd card dai links */
5018 if (dai_link[i].cpu_dai_name && !dai_link[i].cpu_of_node) {
5019 index = of_property_match_string(cdev->of_node,
5020 "asoc-cpu-names",
5021 dai_link[i].cpu_dai_name);
5022 if (index < 0)
5023 goto codec_dai;
5024 phandle = of_parse_phandle(cdev->of_node, "asoc-cpu",
5025 index);
5026 if (!phandle) {
5027 pr_err("%s: retrieving phandle for cpu dai %s failed\n",
5028 __func__, dai_link[i].cpu_dai_name);
5029 ret = -ENODEV;
5030 goto err;
5031 }
5032 dai_link[i].cpu_of_node = phandle;
5033 dai_link[i].cpu_dai_name = NULL;
5034 }
5035codec_dai:
5036 /* populate codec_of_node for snd card dai links */
5037 if (dai_link[i].codec_name && !dai_link[i].codec_of_node) {
5038 index = of_property_match_string(cdev->of_node,
5039 "asoc-codec-names",
5040 dai_link[i].codec_name);
5041 if (index < 0)
5042 continue;
5043 phandle = of_parse_phandle(cdev->of_node, "asoc-codec",
5044 index);
5045 if (!phandle) {
5046 pr_err("%s: retrieving phandle for codec dai %s failed\n",
5047 __func__, dai_link[i].codec_name);
5048 ret = -ENODEV;
5049 goto err;
5050 }
5051 dai_link[i].codec_of_node = phandle;
5052 dai_link[i].codec_name = NULL;
5053 }
5054 if (pdata->snd_card_val == INT_SND_CARD) {
Asish Bhattacharya84f7f732017-07-25 16:29:27 +0530[diff] [blame]5055 if ((dai_link[i].id ==
Asish Bhattacharya8e2277f2017-07-20 18:31:55 +0530[diff] [blame]5056 MSM_BACKEND_DAI_INT0_MI2S_RX) ||
Asish Bhattacharya84f7f732017-07-25 16:29:27 +0530[diff] [blame]5057 (dai_link[i].id ==
Asish Bhattacharya8e2277f2017-07-20 18:31:55 +0530[diff] [blame]5058 MSM_BACKEND_DAI_INT1_MI2S_RX) ||
Asish Bhattacharya84f7f732017-07-25 16:29:27 +0530[diff] [blame]5059 (dai_link[i].id ==
Asish Bhattacharya8e2277f2017-07-20 18:31:55 +0530[diff] [blame]5060 MSM_BACKEND_DAI_INT2_MI2S_TX) ||
Asish Bhattacharya84f7f732017-07-25 16:29:27 +0530[diff] [blame]5061 (dai_link[i].id ==
Asish Bhattacharya8e2277f2017-07-20 18:31:55 +0530[diff] [blame]5062 MSM_BACKEND_DAI_INT3_MI2S_TX)) {
5063 index = of_property_match_string(cdev->of_node,
5064 "asoc-codec-names",
5065 MSM_INT_DIGITAL_CODEC);
5066 phandle = of_parse_phandle(cdev->of_node,
5067 "asoc-codec",
5068 index);
5069 dai_link[i].codecs[DIG_CDC].of_node = phandle;
5070 index = of_property_match_string(cdev->of_node,
5071 "asoc-codec-names",
5072 PMIC_INT_ANALOG_CODEC);
Viraja Kommaraju6521c6e2018-01-02 23:29:45 +0530[diff] [blame]5073 phandle = of_parse_phandle(
5074 cdev->of_node,
5075 "asoc-codec",
5076 index);
5077 dai_link[i].codecs[ANA_CDC].of_node =
5078 phandle;
5079 }
5080 }
5081 if (pdata->snd_card_val == INT_DIG_SND_CARD) {
5082 if ((dai_link[i].id ==
5083 MSM_BACKEND_DAI_INT0_MI2S_RX) ||
5084 (dai_link[i].id ==
5085 MSM_BACKEND_DAI_INT1_MI2S_RX) ||
5086 (dai_link[i].id ==
5087 MSM_BACKEND_DAI_INT2_MI2S_TX) ||
5088 (dai_link[i].id ==
5089 MSM_BACKEND_DAI_INT3_MI2S_TX)) {
5090 index = of_property_match_string(cdev->of_node,
5091 "asoc-codec-names",
5092 MSM_INT_DIGITAL_CODEC);
Asish Bhattacharya8e2277f2017-07-20 18:31:55 +0530[diff] [blame]5093 phandle = of_parse_phandle(cdev->of_node,
5094 "asoc-codec",
5095 index);
Viraja Kommaraju6521c6e2018-01-02 23:29:45 +0530[diff] [blame]5096 dai_link[i].codec_of_node = phandle;
Asish Bhattacharya8e2277f2017-07-20 18:31:55 +0530[diff] [blame]5097 }
5098 }
5099 }
5100err:
5101 return ret;
5102}
5103
5104static int msm_wsa881x_init(struct snd_soc_component *component)
5105{
5106 u8 spkleft_ports[WSA881X_MAX_SWR_PORTS] = {100, 101, 102, 106};
5107 u8 spkright_ports[WSA881X_MAX_SWR_PORTS] = {103, 104, 105, 107};
5108 unsigned int ch_rate[WSA881X_MAX_SWR_PORTS] = {2400, 600, 300, 1200};
5109 unsigned int ch_mask[WSA881X_MAX_SWR_PORTS] = {0x1, 0xF, 0x3, 0x3};
5110 struct snd_soc_codec *codec = snd_soc_component_to_codec(component);
5111 struct msm_asoc_mach_data *pdata;
5112 struct snd_soc_dapm_context *dapm =
5113 snd_soc_codec_get_dapm(codec);
5114
5115 if (!codec) {
5116 pr_err("%s codec is NULL\n", __func__);
5117 return -EINVAL;
5118 }
5119
5120 if (!strcmp(component->name_prefix, "SpkrLeft")) {
5121 dev_dbg(codec->dev, "%s: setting left ch map to codec %s\n",
5122 __func__, codec->component.name);
5123 wsa881x_set_channel_map(codec, &spkleft_ports[0],
5124 WSA881X_MAX_SWR_PORTS, &ch_mask[0],
5125 &ch_rate[0]);
5126 if (dapm->component) {
5127 snd_soc_dapm_ignore_suspend(dapm, "SpkrLeft IN");
5128 snd_soc_dapm_ignore_suspend(dapm, "SpkrLeft SPKR");
5129 }
5130 } else if (!strcmp(component->name_prefix, "SpkrRight")) {
5131 dev_dbg(codec->dev, "%s: setting right ch map to codec %s\n",
5132 __func__, codec->component.name);
5133 wsa881x_set_channel_map(codec, &spkright_ports[0],
5134 WSA881X_MAX_SWR_PORTS, &ch_mask[0],
5135 &ch_rate[0]);
5136 if (dapm->component) {
5137 snd_soc_dapm_ignore_suspend(dapm, "SpkrRight IN");
5138 snd_soc_dapm_ignore_suspend(dapm, "SpkrRight SPKR");
5139 }
5140 } else {
5141 dev_err(codec->dev, "%s: wrong codec name %s\n", __func__,
5142 codec->component.name);
5143 return -EINVAL;
5144 }
5145
5146
5147 pdata = snd_soc_card_get_drvdata(component->card);
5148 if (pdata && pdata->codec_root)
5149 wsa881x_codec_info_create_codec_entry(pdata->codec_root,
5150 codec);
5151 return 0;
5152}
5153
5154
5155static int msm_init_wsa_dev(struct platform_device *pdev,
5156 struct snd_soc_card *card)
5157{
5158 struct device_node *wsa_of_node;
5159 u32 wsa_max_devs;
5160 u32 wsa_dev_cnt;
5161 char *dev_name_str = NULL;
5162 struct msm_wsa881x_dev_info *wsa881x_dev_info;
5163 const char *wsa_auxdev_name_prefix[1];
5164 int found = 0;
5165 int i;
5166 int ret;
5167
5168 /* Get maximum WSA device count for this platform */
5169 ret = of_property_read_u32(pdev->dev.of_node,
5170 "qcom,wsa-max-devs", &wsa_max_devs);
5171 if (ret) {
5172 dev_dbg(&pdev->dev,
5173 "%s: wsa-max-devs property missing in DT %s, ret = %d\n",
5174 __func__, pdev->dev.of_node->full_name, ret);
5175 goto err_dt;
5176 }
5177 if (wsa_max_devs == 0) {
5178 dev_warn(&pdev->dev,
5179 "%s: Max WSA devices is 0 for this target?\n",
5180 __func__);
5181 goto err_dt;
5182 }
5183
5184 /* Get count of WSA device phandles for this platform */
5185 wsa_dev_cnt = of_count_phandle_with_args(pdev->dev.of_node,
5186 "qcom,wsa-devs", NULL);
5187 if (wsa_dev_cnt == -ENOENT) {
5188 dev_warn(&pdev->dev, "%s: No wsa device defined in DT.\n",
5189 __func__);
5190 goto err_dt;
5191 } else if (wsa_dev_cnt <= 0) {
5192 dev_err(&pdev->dev,
5193 "%s: Error reading wsa device from DT. wsa_dev_cnt = %d\n",
5194 __func__, wsa_dev_cnt);
5195 ret = -EINVAL;
5196 goto err_dt;
5197 }
5198
5199 /*
5200 * Expect total phandles count to be NOT less than maximum possible
5201 * WSA count. However, if it is less, then assign same value to
5202 * max count as well.
5203 */
5204 if (wsa_dev_cnt < wsa_max_devs) {
5205 dev_dbg(&pdev->dev,
5206 "%s: wsa_max_devs = %d cannot exceed wsa_dev_cnt = %d\n",
5207 __func__, wsa_max_devs, wsa_dev_cnt);
5208 wsa_max_devs = wsa_dev_cnt;
5209 }
5210
5211 /* Make sure prefix string passed for each WSA device */
5212 ret = of_property_count_strings(pdev->dev.of_node,
5213 "qcom,wsa-aux-dev-prefix");
5214 if (ret != wsa_dev_cnt) {
5215 dev_err(&pdev->dev,
5216 "%s: expecting %d wsa prefix. Defined only %d in DT\n",
5217 __func__, wsa_dev_cnt, ret);
5218 ret = -EINVAL;
5219 goto err_dt;
5220 }
5221
5222 /*
5223 * Alloc mem to store phandle and index info of WSA device, if already
5224 * registered with ALSA core
5225 */
5226 wsa881x_dev_info = devm_kcalloc(&pdev->dev, wsa_max_devs,
5227 sizeof(struct msm_wsa881x_dev_info),
5228 GFP_KERNEL);
5229 if (!wsa881x_dev_info) {
5230 ret = -ENOMEM;
5231 goto err_mem;
5232 }
5233
5234 /*
5235 * search and check whether all WSA devices are already
5236 * registered with ALSA core or not. If found a node, store
5237 * the node and the index in a local array of struct for later
5238 * use.
5239 */
5240 for (i = 0; i < wsa_dev_cnt; i++) {
5241 wsa_of_node = of_parse_phandle(pdev->dev.of_node,
5242 "qcom,wsa-devs", i);
5243 if (unlikely(!wsa_of_node)) {
5244 /* we should not be here */
5245 dev_err(&pdev->dev,
5246 "%s: wsa dev node is not present\n",
5247 __func__);
5248 ret = -EINVAL;
5249 goto err_dev_node;
5250 }
5251 if (soc_find_component(wsa_of_node, NULL)) {
5252 /* WSA device registered with ALSA core */
5253 wsa881x_dev_info[found].of_node = wsa_of_node;
5254 wsa881x_dev_info[found].index = i;
5255 found++;
5256 if (found == wsa_max_devs)
5257 break;
5258 }
5259 }
5260
5261 if (found < wsa_max_devs) {
5262 dev_dbg(&pdev->dev,
5263 "%s: failed to find %d components. Found only %d\n",
5264 __func__, wsa_max_devs, found);
5265 return -EPROBE_DEFER;
5266 }
5267 dev_info(&pdev->dev,
5268 "%s: found %d wsa881x devices registered with ALSA core\n",
5269 __func__, found);
5270
5271 card->num_aux_devs = wsa_max_devs;
5272 card->num_configs = wsa_max_devs;
5273
5274 /* Alloc array of AUX devs struct */
5275 msm_aux_dev = devm_kcalloc(&pdev->dev, card->num_aux_devs,
5276 sizeof(struct snd_soc_aux_dev),
5277 GFP_KERNEL);
5278 if (!msm_aux_dev) {
5279 ret = -ENOMEM;
5280 goto err_auxdev_mem;
5281 }
5282
5283 /* Alloc array of codec conf struct */
5284 msm_codec_conf = devm_kcalloc(&pdev->dev, card->num_aux_devs,
5285 sizeof(struct snd_soc_codec_conf),
5286 GFP_KERNEL);
5287 if (!msm_codec_conf) {
5288 ret = -ENOMEM;
5289 goto err_codec_conf;
5290 }
5291
5292 for (i = 0; i < card->num_aux_devs; i++) {
5293 dev_name_str = devm_kzalloc(&pdev->dev, DEV_NAME_STR_LEN,
5294 GFP_KERNEL);
5295 if (!dev_name_str) {
5296 ret = -ENOMEM;
5297 goto err_dev_str;
5298 }
5299
5300 ret = of_property_read_string_index(pdev->dev.of_node,
5301 "qcom,wsa-aux-dev-prefix",
5302 wsa881x_dev_info[i].index,
5303 wsa_auxdev_name_prefix);
5304 if (ret) {
5305 dev_err(&pdev->dev,
5306 "%s: failed to read wsa aux dev prefix, ret = %d\n",
5307 __func__, ret);
5308 ret = -EINVAL;
5309 goto err_dt_prop;
5310 }
5311
5312 snprintf(dev_name_str, strlen("wsa881x.%d"), "wsa881x.%d", i);
5313 msm_aux_dev[i].name = dev_name_str;
5314 msm_aux_dev[i].codec_name = NULL;
5315 msm_aux_dev[i].codec_of_node =
5316 wsa881x_dev_info[i].of_node;
5317 msm_aux_dev[i].init = msm_wsa881x_init;
5318 msm_codec_conf[i].dev_name = NULL;
5319 msm_codec_conf[i].name_prefix = wsa_auxdev_name_prefix[0];
5320 msm_codec_conf[i].of_node = wsa881x_dev_info[i].of_node;
5321 }
5322 card->codec_conf = msm_codec_conf;
5323 card->aux_dev = msm_aux_dev;
5324
5325 return 0;
5326
5327err_dt_prop:
5328 devm_kfree(&pdev->dev, dev_name_str);
5329err_dev_str:
5330 devm_kfree(&pdev->dev, msm_codec_conf);
5331err_codec_conf:
5332 devm_kfree(&pdev->dev, msm_aux_dev);
5333err_auxdev_mem:
5334err_dev_node:
5335 devm_kfree(&pdev->dev, wsa881x_dev_info);
5336err_mem:
5337err_dt:
5338 return ret;
5339}
5340
Asish Bhattacharya8e2277f2017-07-20 18:31:55 +0530[diff] [blame]5341static void i2s_auxpcm_init(struct platform_device *pdev)
5342{
5343 int count;
5344 u32 mi2s_master_slave[MI2S_MAX];
5345 u32 mi2s_ext_mclk[MI2S_MAX];
5346 int ret;
5347
5348 for (count = 0; count < MI2S_MAX; count++) {
5349 mutex_init(&mi2s_intf_conf[count].lock);
5350 mi2s_intf_conf[count].ref_cnt = 0;
5351 }
5352
5353 ret = of_property_read_u32_array(pdev->dev.of_node,
5354 "qcom,msm-mi2s-master",
5355 mi2s_master_slave, MI2S_MAX);
5356 if (ret) {
5357 dev_dbg(&pdev->dev, "%s: no qcom,msm-mi2s-master in DT node\n",
5358 __func__);
5359 } else {
5360 for (count = 0; count < MI2S_MAX; count++) {
5361 mi2s_intf_conf[count].msm_is_mi2s_master =
5362 mi2s_master_slave[count];
5363 }
5364 }
5365
5366 ret = of_property_read_u32_array(pdev->dev.of_node,
5367 "qcom,msm-mi2s-ext-mclk",
5368 mi2s_ext_mclk, MI2S_MAX);
5369 if (ret) {
5370 dev_dbg(&pdev->dev, "%s: no qcom,msm-mi2s-ext-mclk in DT node\n",
5371 __func__);
5372 } else {
5373 for (count = 0; count < MI2S_MAX; count++)
5374 mi2s_intf_conf[count].msm_is_ext_mclk =
5375 mi2s_ext_mclk[count];
5376 }
5377}
5378
5379static const struct of_device_id sdm660_asoc_machine_of_match[] = {
5380 { .compatible = "qcom,sdm660-asoc-snd",
5381 .data = "internal_codec"},
5382 { .compatible = "qcom,sdm660-asoc-snd-tasha",
5383 .data = "tasha_codec"},
5384 { .compatible = "qcom,sdm660-asoc-snd-tavil",
5385 .data = "tavil_codec"},
Laxminath Kasam38070be2017-08-17 18:21:59 +0530[diff] [blame]5386 { .compatible = "qcom,sdm670-asoc-snd",
5387 .data = "internal_codec"},
5388 { .compatible = "qcom,sdm670-asoc-snd-tasha",
5389 .data = "tasha_codec"},
5390 { .compatible = "qcom,sdm670-asoc-snd-tavil",
5391 .data = "tavil_codec"},
Viraja Kommaraju6521c6e2018-01-02 23:29:45 +0530[diff] [blame]5392 { .compatible = "qcom,qcs605-dig-asoc-snd",
5393 .data = "digital_codec"},
Meng Wangce5655b2018-07-06 10:47:38 +0800[diff] [blame]5394 { .compatible = "qcom,qcs605-asoc-snd-tavil",
5395 .data = "tavil_codec"},
Asish Bhattacharya8e2277f2017-07-20 18:31:55 +0530[diff] [blame]5396 {},
5397};
5398
5399static int msm_asoc_machine_probe(struct platform_device *pdev)
5400{
5401 struct snd_soc_card *card = NULL;
5402 struct msm_asoc_mach_data *pdata = NULL;
5403 const char *mclk = "qcom,msm-mclk-freq";
5404 int ret = -EINVAL, id;
5405 const struct of_device_id *match;
Vatsal Bucha42dd4022017-12-07 14:35:59 +0530[diff] [blame]5406 const char *usb_c_dt = "qcom,msm-mbhc-usbc-audio-supported";
Asish Bhattacharya8e2277f2017-07-20 18:31:55 +0530[diff] [blame]5407
5408 pdata = devm_kzalloc(&pdev->dev,
5409 sizeof(struct msm_asoc_mach_data),
5410 GFP_KERNEL);
5411 if (!pdata)
5412 return -ENOMEM;
5413
Laxminath Kasam38070be2017-08-17 18:21:59 +0530[diff] [blame]5414 msm_set_codec_reg_done(false);
Asish Bhattacharya8e2277f2017-07-20 18:31:55 +0530[diff] [blame]5415 match = of_match_node(sdm660_asoc_machine_of_match,
5416 pdev->dev.of_node);
5417 if (!match)
5418 goto err;
5419
5420 ret = of_property_read_u32(pdev->dev.of_node, mclk, &id);
5421 if (ret) {
5422 dev_err(&pdev->dev,
5423 "%s: missing %s in dt node\n", __func__, mclk);
5424 id = DEFAULT_MCLK_RATE;
5425 }
5426 pdata->mclk_freq = id;
5427
5428 if (!strcmp(match->data, "tasha_codec") ||
5429 !strcmp(match->data, "tavil_codec")) {
5430 if (!strcmp(match->data, "tasha_codec"))
5431 pdata->snd_card_val = EXT_SND_CARD_TASHA;
5432 else
5433 pdata->snd_card_val = EXT_SND_CARD_TAVIL;
5434 ret = msm_ext_cdc_init(pdev, pdata, &card, &mbhc_cfg);
5435 if (ret)
5436 goto err;
5437 } else if (!strcmp(match->data, "internal_codec")) {
5438 pdata->snd_card_val = INT_SND_CARD;
5439 ret = msm_int_cdc_init(pdev, pdata, &card, &mbhc_cfg);
5440 if (ret)
5441 goto err;
Viraja Kommaraju6521c6e2018-01-02 23:29:45 +0530[diff] [blame]5442 } else if (!strcmp(match->data, "digital_codec")) {
5443 pdata->snd_card_val = INT_DIG_SND_CARD;
5444 ret = msm_int_cdc_init(pdev, pdata, &card, NULL);
5445 if (ret)
5446 goto err;
Asish Bhattacharya8e2277f2017-07-20 18:31:55 +0530[diff] [blame]5447 } else {
5448 dev_err(&pdev->dev,
5449 "%s: Not a matching DT sound node\n", __func__);
5450 goto err;
5451 }
5452 if (!card)
5453 goto err;
5454
5455 if (pdata->snd_card_val == INT_SND_CARD) {
5456 /*reading the gpio configurations from dtsi file*/
5457 pdata->pdm_gpio_p = of_parse_phandle(pdev->dev.of_node,
5458 "qcom,cdc-pdm-gpios", 0);
5459 pdata->comp_gpio_p = of_parse_phandle(pdev->dev.of_node,
5460 "qcom,cdc-comp-gpios", 0);
5461 pdata->dmic_gpio_p = of_parse_phandle(pdev->dev.of_node,
5462 "qcom,cdc-dmic-gpios", 0);
5463 pdata->ext_spk_gpio_p = of_parse_phandle(pdev->dev.of_node,
5464 "qcom,cdc-ext-spk-gpios", 0);
5465 }
5466
Viraja Kommaraju6521c6e2018-01-02 23:29:45 +0530[diff] [blame]5467 if (pdata->snd_card_val == INT_DIG_SND_CARD) {
5468 /*reading the gpio configurations from dtsi file*/
5469 pdata->dmic_gpio_p = of_parse_phandle(pdev->dev.of_node,
5470 "qcom,cdc-dmic-gpios", 0);
5471 }
Rohit Kumaraf88e4c2017-10-04 13:47:10 +0530[diff] [blame]5472 pdata->mi2s_gpio_p[PRIM_MI2S] = of_parse_phandle(pdev->dev.of_node,
5473 "qcom,pri-mi2s-gpios", 0);
5474 pdata->mi2s_gpio_p[SEC_MI2S] = of_parse_phandle(pdev->dev.of_node,
5475 "qcom,sec-mi2s-gpios", 0);
5476 pdata->mi2s_gpio_p[TERT_MI2S] = of_parse_phandle(pdev->dev.of_node,
5477 "qcom,tert-mi2s-gpios", 0);
5478 pdata->mi2s_gpio_p[QUAT_MI2S] = of_parse_phandle(pdev->dev.of_node,
5479 "qcom,quat-mi2s-gpios", 0);
5480 pdata->mi2s_gpio_p[QUIN_MI2S] = of_parse_phandle(pdev->dev.of_node,
5481 "qcom,quin-mi2s-gpios", 0);
Asish Bhattacharya8e2277f2017-07-20 18:31:55 +0530[diff] [blame]5482 /*
5483 * Parse US-Euro gpio info from DT. Report no error if us-euro
5484 * entry is not found in DT file as some targets do not support
5485 * US-Euro detection
5486 */
5487 pdata->us_euro_gpio = of_get_named_gpio(pdev->dev.of_node,
5488 "qcom,us-euro-gpios", 0);
5489 if (!gpio_is_valid(pdata->us_euro_gpio))
5490 pdata->us_euro_gpio_p = of_parse_phandle(pdev->dev.of_node,
5491 "qcom,us-euro-gpios", 0);
5492 if (!gpio_is_valid(pdata->us_euro_gpio) && (!pdata->us_euro_gpio_p)) {
5493 dev_dbg(&pdev->dev, "property %s not detected in node %s",
5494 "qcom,us-euro-gpios", pdev->dev.of_node->full_name);
5495 } else {
5496 dev_dbg(&pdev->dev, "%s detected",
5497 "qcom,us-euro-gpios");
5498 mbhc_cfg.swap_gnd_mic = msm_swap_gnd_mic;
5499 }
5500
Vatsal Bucha42dd4022017-12-07 14:35:59 +0530[diff] [blame]5501 if (of_find_property(pdev->dev.of_node, usb_c_dt, NULL))
5502 mbhc_cfg.swap_gnd_mic = msm_swap_gnd_mic;
5503
Asish Bhattacharya8e2277f2017-07-20 18:31:55 +0530[diff] [blame]5504 ret = msm_prepare_us_euro(card);
5505 if (ret)
5506 dev_dbg(&pdev->dev, "msm_prepare_us_euro failed (%d)\n",
5507 ret);
5508
5509 i2s_auxpcm_init(pdev);
5510
5511 ret = snd_soc_of_parse_audio_routing(card, "qcom,audio-routing");
5512 if (ret)
5513 goto err;
5514
5515 ret = msm_populate_dai_link_component_of_node(pdata, card);
5516 if (ret) {
5517 ret = -EPROBE_DEFER;
5518 goto err;
5519 }
5520
5521 if (!of_property_read_bool(pdev->dev.of_node, "qcom,wsa-disable")) {
5522 ret = msm_init_wsa_dev(pdev, card);
5523 if (ret)
5524 goto err;
5525 }
5526
5527 ret = devm_snd_soc_register_card(&pdev->dev, card);
5528 if (ret == -EPROBE_DEFER) {
5529 if (codec_reg_done) {
5530 /*
5531 * return failure as EINVAL since other codec
5532 * registered sound card successfully.
5533 * This avoids any further probe calls.
5534 */
5535 ret = -EINVAL;
5536 }
5537 goto err;
5538 } else if (ret) {
5539 dev_err(&pdev->dev, "snd_soc_register_card failed (%d)\n",
5540 ret);
5541 goto err;
5542 }
Viraja Kommaraju6521c6e2018-01-02 23:29:45 +0530[diff] [blame]5543 if (pdata->snd_card_val > INT_MAX_SND_CARD)
Asish Bhattacharya8e2277f2017-07-20 18:31:55 +0530[diff] [blame]5544 msm_ext_register_audio_notifier(pdev);
5545
5546 return 0;
5547err:
5548 if (pdata->us_euro_gpio > 0) {
5549 dev_dbg(&pdev->dev, "%s free us_euro gpio %d\n",
5550 __func__, pdata->us_euro_gpio);
5551 pdata->us_euro_gpio = 0;
5552 }
5553 if (pdata->hph_en1_gpio > 0) {
5554 dev_dbg(&pdev->dev, "%s free hph_en1_gpio %d\n",
5555 __func__, pdata->hph_en1_gpio);
5556 gpio_free(pdata->hph_en1_gpio);
5557 pdata->hph_en1_gpio = 0;
5558 }
5559 if (pdata->hph_en0_gpio > 0) {
5560 dev_dbg(&pdev->dev, "%s free hph_en0_gpio %d\n",
5561 __func__, pdata->hph_en0_gpio);
5562 gpio_free(pdata->hph_en0_gpio);
5563 pdata->hph_en0_gpio = 0;
5564 }
Asish Bhattacharya8e2277f2017-07-20 18:31:55 +0530[diff] [blame]5565 devm_kfree(&pdev->dev, pdata);
5566 return ret;
5567}
5568
5569static int msm_asoc_machine_remove(struct platform_device *pdev)
5570{
5571 struct snd_soc_card *card = platform_get_drvdata(pdev);
5572 struct msm_asoc_mach_data *pdata = snd_soc_card_get_drvdata(card);
5573
Viraja Kommaraju6521c6e2018-01-02 23:29:45 +0530[diff] [blame]5574 if (pdata->snd_card_val <= INT_MAX_SND_CARD)
Asish Bhattacharya8e2277f2017-07-20 18:31:55 +0530[diff] [blame]5575 mutex_destroy(&pdata->cdc_int_mclk0_mutex);
Asish Bhattacharya8e2277f2017-07-20 18:31:55 +0530[diff] [blame]5576
Meng Wangc4ef3b52017-10-18 10:57:15 +0800[diff] [blame]5577 if (gpio_is_valid(pdata->us_euro_gpio)) {
5578 gpio_free(pdata->us_euro_gpio);
5579 pdata->us_euro_gpio = 0;
5580 }
5581 if (gpio_is_valid(pdata->hph_en1_gpio)) {
5582 gpio_free(pdata->hph_en1_gpio);
5583 pdata->hph_en1_gpio = 0;
5584 }
5585 if (gpio_is_valid(pdata->hph_en0_gpio)) {
5586 gpio_free(pdata->hph_en0_gpio);
5587 pdata->hph_en0_gpio = 0;
5588 }
Meng Wangc444ff72017-10-18 10:52:07 +0800[diff] [blame]5589
Viraja Kommaraju6521c6e2018-01-02 23:29:45 +0530[diff] [blame]5590 if (pdata->snd_card_val > INT_MAX_SND_CARD)
Meng Wangc444ff72017-10-18 10:52:07 +0800[diff] [blame]5591 audio_notifier_deregister("sdm660");
5592
Asish Bhattacharya8e2277f2017-07-20 18:31:55 +0530[diff] [blame]5593 snd_soc_unregister_card(card);
5594 return 0;
5595}
5596
5597static struct platform_driver sdm660_asoc_machine_driver = {
5598 .driver = {
5599 .name = DRV_NAME,
5600 .owner = THIS_MODULE,
5601 .pm = &snd_soc_pm_ops,
5602 .of_match_table = sdm660_asoc_machine_of_match,
5603 },
5604 .probe = msm_asoc_machine_probe,
5605 .remove = msm_asoc_machine_remove,
5606};
5607module_platform_driver(sdm660_asoc_machine_driver);
5608
5609MODULE_DESCRIPTION("ALSA SoC msm");
5610MODULE_LICENSE("GPL v2");
5611MODULE_ALIAS("platform:" DRV_NAME);
5612MODULE_DEVICE_TABLE(of, sdm660_asoc_machine_of_match);