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gerrit-public.fairphone.software / platform / vendor / opensource / audio-kernel / f53de7f9fb98f4236ab7aed20960a74702cb966e / . / asoc / sa6155.c
blob: 73217fa3f5eeca629152dd72895dfb7899302965 [file] [log] [blame]
Rahul Sharma02bee732018-12-20 18:48:34 +0530[diff] [blame]1/* Copyright (c) 2014-2019, The Linux Foundation. All rights reserved.
2 *
3 * This program is free software; you can redistribute it and/or modify
4 * it under the terms of the GNU General Public License version 2 and
5 * only version 2 as published by the Free Software Foundation.
6 *
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
11 */
12/*
13 * Copyright 2011, The Android Open Source Project
14
15 * Redistribution and use in source and binary forms, with or without
16 * modification, are permitted provided that the following conditions are met:
17 * Redistributions of source code must retain the above copyright
18 notice, this list of conditions and the following disclaimer.
19 * Redistributions in binary form must reproduce the above copyright
20 notice, this list of conditions and the following disclaimer in the
21 documentation and/or other materials provided with the distribution.
22 * Neither the name of The Android Open Source Project nor the names of
23 its contributors may be used to endorse or promote products derived
24 from this software without specific prior written permission.
25
26 * THIS SOFTWARE IS PROVIDED BY The Android Open Source Project ``AS IS'' AND
27 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
28 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
29 * ARE DISCLAIMED. IN NO EVENT SHALL The Android Open Source Project BE LIABLE
30 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
31 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
32 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
33 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
34 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
35 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
36 * DAMAGE.
37 */
38
39#include <linux/clk.h>
40#include <linux/delay.h>
41#include <linux/gpio.h>
42#include <linux/of_gpio.h>
43#include <linux/platform_device.h>
44#include <linux/slab.h>
45#include <linux/io.h>
46#include <linux/module.h>
47#include <linux/input.h>
48#include <linux/of_device.h>
49#include <linux/pm_qos.h>
50#include <sound/core.h>
51#include <sound/soc.h>
52#include <sound/soc-dapm.h>
53#include <sound/pcm.h>
54#include <sound/pcm_params.h>
55#include <sound/info.h>
56#include <dsp/audio_notifier.h>
57#include <dsp/q6afe-v2.h>
58#include <dsp/q6core.h>
59#include "device_event.h"
60#include "msm-pcm-routing-v2.h"
61
62#define DRV_NAME "sa6155-asoc-snd"
63
64#define __CHIPSET__ "SA6155 "
65#define MSM_DAILINK_NAME(name) (__CHIPSET__#name)
66
67#define DEV_NAME_STR_LEN 32
68
69#define SAMPLING_RATE_8KHZ 8000
70#define SAMPLING_RATE_11P025KHZ 11025
71#define SAMPLING_RATE_16KHZ 16000
72#define SAMPLING_RATE_22P05KHZ 22050
73#define SAMPLING_RATE_32KHZ 32000
74#define SAMPLING_RATE_44P1KHZ 44100
75#define SAMPLING_RATE_48KHZ 48000
76#define SAMPLING_RATE_88P2KHZ 88200
77#define SAMPLING_RATE_96KHZ 96000
78#define SAMPLING_RATE_176P4KHZ 176400
79#define SAMPLING_RATE_192KHZ 192000
80#define SAMPLING_RATE_352P8KHZ 352800
81#define SAMPLING_RATE_384KHZ 384000
82
83#define ADSP_STATE_READY_TIMEOUT_MS 3000
84#define MSM_LL_QOS_VALUE 300 /* time in us to ensure LPM doesn't go in C3/C4 */
85
86enum {
87 PRIM_MI2S = 0,
88 SEC_MI2S,
89 TERT_MI2S,
90 QUAT_MI2S,
91 QUIN_MI2S,
92 MI2S_MAX,
93};
94
95enum {
96 PRIM_AUX_PCM = 0,
97 SEC_AUX_PCM,
98 TERT_AUX_PCM,
99 QUAT_AUX_PCM,
100 QUIN_AUX_PCM,
101 AUX_PCM_MAX,
102};
103
104struct mi2s_conf {
105 struct mutex lock;
106 u32 ref_cnt;
107 u32 msm_is_mi2s_master;
108};
109
110static u32 mi2s_ebit_clk[MI2S_MAX] = {
111 Q6AFE_LPASS_CLK_ID_PRI_MI2S_EBIT,
112 Q6AFE_LPASS_CLK_ID_SEC_MI2S_EBIT,
113 Q6AFE_LPASS_CLK_ID_TER_MI2S_EBIT,
114 Q6AFE_LPASS_CLK_ID_QUAD_MI2S_EBIT,
115 Q6AFE_LPASS_CLK_ID_QUI_MI2S_EBIT
116};
117
118struct dev_config {
119 u32 sample_rate;
120 u32 bit_format;
121 u32 channels;
122};
123
124enum {
125 DP_RX_IDX = 0,
126 EXT_DISP_RX_IDX_MAX,
127};
128
129enum pinctrl_pin_state {
130 STATE_DISABLE = 0, /* All pins are in sleep state */
131 STATE_MI2S_ACTIVE, /* I2S = active, TDM = sleep */
132 STATE_TDM_ACTIVE, /* I2S = sleep, TDM = active */
133};
134
135struct msm_pinctrl_info {
136 struct pinctrl *pinctrl;
137 struct pinctrl_state *mi2s_disable;
138 struct pinctrl_state *tdm_disable;
139 struct pinctrl_state *mi2s_active;
140 struct pinctrl_state *tdm_active;
141 enum pinctrl_pin_state curr_state;
142};
143
144struct msm_asoc_mach_data {
145 struct msm_pinctrl_info pinctrl_info;
146};
147
148static const char *const pin_states[] = {"sleep", "i2s-active",
149 "tdm-active"};
150
151enum {
152 TDM_0 = 0,
153 TDM_1,
154 TDM_2,
155 TDM_3,
156 TDM_4,
157 TDM_5,
158 TDM_6,
159 TDM_7,
160 TDM_PORT_MAX,
161};
162
163enum {
164 TDM_PRI = 0,
165 TDM_SEC,
166 TDM_TERT,
167 TDM_QUAT,
168 TDM_QUIN,
169 TDM_INTERFACE_MAX,
170};
171
172struct tdm_port {
173 u32 mode;
174 u32 channel;
175};
176
177/* TDM default config */
178static struct dev_config tdm_rx_cfg[TDM_INTERFACE_MAX][TDM_PORT_MAX] = {
179 { /* PRI TDM */
180 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2}, /* RX_0 */
181 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2}, /* RX_1 */
182 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2}, /* RX_2 */
183 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2}, /* RX_3 */
184 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_4 */
185 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_5 */
186 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_6 */
187 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_7 */
188 },
189 { /* SEC TDM */
190 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2}, /* RX_0 */
191 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2}, /* RX_1 */
192 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2}, /* RX_2 */
193 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2}, /* RX_3 */
194 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_4 */
195 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_5 */
196 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_6 */
197 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_7 */
198 },
199 { /* TERT TDM */
200 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 6}, /* RX_0 */
201 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_1 */
202 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_2 */
203 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_3 */
204 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_4 */
205 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_5 */
206 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_6 */
207 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_7 */
208 },
209 { /* QUAT TDM */
210 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_0 */
211 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_1 */
212 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_2 */
213 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_3 */
214 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_4 */
215 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_5 */
216 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_6 */
217 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_7 */
218 },
219 { /* QUIN TDM */
220 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_0 */
221 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_1 */
222 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_2 */
223 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_3 */
224 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_4 */
225 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_5 */
226 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_6 */
227 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_7 */
228 }
229};
230
231/* TDM default config */
232static struct dev_config tdm_tx_cfg[TDM_INTERFACE_MAX][TDM_PORT_MAX] = {
233 { /* PRI TDM */
234 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2}, /* TX_0 */
235 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2}, /* TX_1 */
236 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2}, /* TX_2 */
237 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2}, /* TX_3 */
238 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_4 */
239 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_5 */
240 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_6 */
241 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_7 */
242 },
243 { /* SEC TDM */
244 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 6}, /* TX_0 */
245 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_1 */
246 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_2 */
247 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_3 */
248 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_4 */
249 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_5 */
250 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_6 */
251 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_7 */
252 },
253 { /* TERT TDM */
254 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 4}, /* TX_0 */
255 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2}, /* TX_1 */
256 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2}, /* TX_2 */
257 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_3 */
258 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_4 */
259 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_5 */
260 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_6 */
261 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_7 */
262 },
263 { /* QUAT TDM */
264 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_0 */
265 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_1 */
266 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_2 */
267 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_3 */
268 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_4 */
269 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_5 */
270 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_6 */
271 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_7 */
272 },
273 { /* QUIN TDM */
274 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_0 */
275 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_1 */
276 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_2 */
277 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_3 */
278 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_4 */
279 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_5 */
280 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_6 */
281 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_7 */
282 }
283};
284
285/* Default configuration of external display BE */
286static struct dev_config ext_disp_rx_cfg[] = {
287 [DP_RX_IDX] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
288};
289
290static struct dev_config usb_rx_cfg = {
291 .sample_rate = SAMPLING_RATE_48KHZ,
292 .bit_format = SNDRV_PCM_FORMAT_S16_LE,
293 .channels = 2,
294};
295
296static struct dev_config usb_tx_cfg = {
297 .sample_rate = SAMPLING_RATE_48KHZ,
298 .bit_format = SNDRV_PCM_FORMAT_S16_LE,
299 .channels = 1,
300};
301
302static struct dev_config proxy_rx_cfg = {
303 .sample_rate = SAMPLING_RATE_48KHZ,
304 .bit_format = SNDRV_PCM_FORMAT_S16_LE,
305 .channels = 2,
306};
307
308/* Default configuration of MI2S channels */
309static struct dev_config mi2s_rx_cfg[] = {
310 [PRIM_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
311 [SEC_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
312 [TERT_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
313 [QUAT_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
314 [QUIN_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
315};
316
317static struct dev_config mi2s_tx_cfg[] = {
318 [PRIM_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
319 [SEC_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
320 [TERT_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
321 [QUAT_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
322 [QUIN_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
323};
324
325static struct dev_config aux_pcm_rx_cfg[] = {
326 [PRIM_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
327 [SEC_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
328 [TERT_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
329 [QUAT_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
330 [QUIN_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
331};
332
333static struct dev_config aux_pcm_tx_cfg[] = {
334 [PRIM_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
335 [SEC_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
336 [TERT_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
337 [QUAT_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
338 [QUIN_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
339};
340
341/* TDM default slot config */
342struct tdm_slot_cfg {
343 u32 width;
344 u32 num;
345};
346
347static struct tdm_slot_cfg tdm_slot[TDM_INTERFACE_MAX] = {
348 /* PRI TDM */
349 {32, 8},
350 /* SEC TDM */
351 {32, 8},
352 /* TERT TDM */
353 {32, 8},
354 /* QUAT TDM */
355 {32, 8},
356 /* QUIN TDM */
357 {32, 8}
358};
359
360/*****************************************************************************
361* TO BE UPDATED: Codec/Platform specific tdm slot table
362*****************************************************************************/
363static struct tdm_slot_cfg tdm_slot_custom[TDM_INTERFACE_MAX] = {
364 /* PRI TDM */
365 {16, 16},
366 /* SEC TDM */
367 {16, 16},
368 /* TERT TDM */
369 {16, 16},
370 /* QUAT TDM */
371 {16, 16},
372 /* QUIN TDM */
373 {16, 16}
374};
375
376
377/* TDM default slot offset config */
378#define TDM_SLOT_OFFSET_MAX 32
379
380static unsigned int tdm_rx_slot_offset
381 [TDM_INTERFACE_MAX][TDM_PORT_MAX][TDM_SLOT_OFFSET_MAX] = {
382 {/* PRI TDM */
383 {0, 4, 0xFFFF},
384 {8, 12, 0xFFFF},
385 {16, 20, 0xFFFF},
386 {24, 28, 0xFFFF},
387 {0xFFFF}, /* not used */
388 {0xFFFF}, /* not used */
389 {0xFFFF}, /* not used */
390 {0xFFFF}, /* not used */
391 },
392 {/* SEC TDM */
393 {0, 4, 0xFFFF},
394 {8, 12, 0xFFFF},
395 {16, 20, 0xFFFF},
396 {24, 28, 0xFFFF},
397 {0xFFFF}, /* not used */
398 {0xFFFF}, /* not used */
399 {0xFFFF}, /* not used */
400 {0xFFFF}, /* not used */
401 },
402 {/* TERT TDM */
403 {0, 4, 8, 12, 16, 20, 0xFFFF},
404 {24, 0xFFFF},
405 {28, 0xFFFF},
406 {0xFFFF}, /* not used */
407 {0xFFFF}, /* not used */
408 {0xFFFF}, /* not used */
409 {0xFFFF}, /* not used */
410 {0xFFFF}, /* not used */
411 },
412 {/* QUAT TDM */
Rahul Sharma51181d02019-04-12 17:03:01 +0530[diff] [blame]413 {0, 4, 8, 12, 16, 20, 24, 28, 0xFFFF},/*AMP OUT*/
Rahul Sharma02bee732018-12-20 18:48:34 +0530[diff] [blame]414 {0xFFFF}, /* not used */
415 {0xFFFF}, /* not used */
416 {0xFFFF}, /* not used */
417 {0xFFFF}, /* not used */
418 {0xFFFF}, /* not used */
419 {0xFFFF}, /* not used */
420 {0xFFFF}, /* not used */
421 },
422 {/* QUIN TDM */
Rahul Sharma51181d02019-04-12 17:03:01 +0530[diff] [blame]423 {0, 4, 0xFFFF}, /* not used */
424 {8, 12, 0xFFFF}, /* not used */
425 {16, 20, 0xFFFF}, /* not used */
426 {24, 28, 0xFFFF}, /* not used */
Rahul Sharma02bee732018-12-20 18:48:34 +0530[diff] [blame]427 {0xFFFF}, /* not used */
428 {0xFFFF}, /* not used */
429 {0xFFFF}, /* not used */
430 {0xFFFF}, /* not used */
431 }
432};
433
434static unsigned int tdm_tx_slot_offset
435 [TDM_INTERFACE_MAX][TDM_PORT_MAX][TDM_SLOT_OFFSET_MAX] = {
436 {/* PRI TDM */
437 {0, 4, 0xFFFF},
438 {8, 12, 0xFFFF},
439 {16, 20, 0xFFFF},
440 {24, 28, 0xFFFF},
441 {0xFFFF}, /* not used */
442 {0xFFFF}, /* not used */
443 {0xFFFF}, /* not used */
444 {0xFFFF}, /* not used */
445 },
446 {/* SEC TDM */
447 {0, 4, 8, 12, 16, 20, 0xFFFF},
448 {24, 0xFFFF},
449 {28, 0xFFFF},
450 {0xFFFF}, /* not used */
451 {0xFFFF}, /* not used */
452 {0xFFFF}, /* not used */
453 {0xFFFF}, /* not used */
454 {0xFFFF}, /* not used */
455 },
456 {/* TERT TDM */
457 {0, 4, 8, 12, 0xFFFF},
458 {16, 20, 0xFFFF},
459 {24, 28, 0xFFFF},
460 {0xFFFF}, /* not used */
461 {0xFFFF}, /* not used */
462 {0xFFFF}, /* not used */
463 {0xFFFF}, /* not used */
464 {0xFFFF}, /* not used */
465 },
466 {/* QUAT TDM */
Rahul Sharma51181d02019-04-12 17:03:01 +0530[diff] [blame]467 {0, 4, 8, 12, 16, 20, 24, 28,
468 32, 36, 40, 44, 48, 52, 56, 60, 0xFFFF},/*MIC ARR*/
Rahul Sharma02bee732018-12-20 18:48:34 +0530[diff] [blame]469 {0xFFFF}, /* not used */
470 {0xFFFF}, /* not used */
471 {0xFFFF}, /* not used */
472 {0xFFFF}, /* not used */
473 {0xFFFF}, /* not used */
474 {0xFFFF}, /* not used */
475 {0xFFFF}, /* not used */
476 },
477 {/* QUIN TDM */
Rahul Sharma51181d02019-04-12 17:03:01 +0530[diff] [blame]478 {0, 4, 8, 12, 16, 20, 0xFFFF}, /* not used */
Rahul Sharma02bee732018-12-20 18:48:34 +0530[diff] [blame]479 {0xFFFF}, /* not used */
480 {0xFFFF}, /* not used */
481 {0xFFFF}, /* not used */
482 {0xFFFF}, /* not used */
483 {0xFFFF}, /* not used */
484 {0xFFFF}, /* not used */
485 {0xFFFF}, /* not used */
486 }
487};
488
489/*****************************************************************************
490* NOTE:
491* Each entry represents the slot offset array of one backend tdm device
492* valid offset represents the starting offset in byte for the channel
493* use 0xFFFF for end or unused slot offset entry.
494*****************************************************************************/
495static unsigned int tdm_rx_slot_offset_custom
496 [TDM_INTERFACE_MAX][TDM_PORT_MAX][TDM_SLOT_OFFSET_MAX] = {
497 {/* PRI TDM */
498 {0xFFFF}, /* not used */
499 {0xFFFF}, /* not used */
500 {0xFFFF}, /* not used */
501 {0xFFFF}, /* not used */
502 {0xFFFF}, /* not used */
503 {0xFFFF}, /* not used */
504 {0xFFFF}, /* not used */
505 {0xFFFF}, /* not used */
506 },
507 {/* SEC TDM */
508 {0, 2, 0xFFFF},
509 {4, 0xFFFF},
510 {6, 0xFFFF},
511 {8, 0xFFFF},
512 {10, 0xFFFF},
513 {12, 14, 16, 18, 20, 22, 24, 26, 0xFFFF},
514 {28, 30, 0xFFFF},
515 {0xFFFF}, /* not used */
516 },
517 {/* TERT TDM */
518 {0, 2, 0xFFFF},
519 {4, 6, 8, 10, 12, 14, 16, 18, 0xFFFF},
520 {20, 22, 24, 26, 28, 30, 0xFFFF},
521 {0xFFFF}, /* not used */
522 {0xFFFF}, /* not used */
523 {0xFFFF}, /* not used */
524 {0xFFFF}, /* not used */
525 {0xFFFF}, /* not used */
526 },
527 {/* QUAT TDM */
528 {0xFFFF}, /* not used */
529 {0xFFFF}, /* not used */
530 {0xFFFF}, /* not used */
531 {0xFFFF}, /* not used */
532 {0xFFFF}, /* not used */
533 {0xFFFF}, /* not used */
534 {0xFFFF}, /* not used */
535 {0xFFFF}, /* not used */
536 },
537 {/* QUIN TDM */
538 {0xFFFF}, /* not used */
539 {0xFFFF}, /* not used */
540 {0xFFFF}, /* not used */
541 {0xFFFF}, /* not used */
542 {0xFFFF}, /* not used */
543 {0xFFFF}, /* not used */
544 {0xFFFF}, /* not used */
545 {0xFFFF}, /* not used */
546 }
547};
548
549static unsigned int tdm_tx_slot_offset_custom
550 [TDM_INTERFACE_MAX][TDM_PORT_MAX][TDM_SLOT_OFFSET_MAX] = {
551 {/* PRI TDM */
552 {0xFFFF}, /* not used */
553 {0xFFFF}, /* not used */
554 {0xFFFF}, /* not used */
555 {0xFFFF}, /* not used */
556 {0xFFFF}, /* not used */
557 {0xFFFF}, /* not used */
558 {0xFFFF}, /* not used */
559 {0xFFFF}, /* not used */
560 },
561 {/* SEC TDM */
562 {0, 2, 0xFFFF},
563 {4, 6, 8, 10, 12, 14, 16, 18, 0xFFFF},
564 {20, 22, 24, 26, 28, 30, 0xFFFF},
565 {0xFFFF}, /* not used */
566 {0xFFFF}, /* not used */
567 {0xFFFF}, /* not used */
568 {0xFFFF}, /* not used */
569 {0xFFFF}, /* not used */
570 },
571 {/* TERT TDM */
572 {0, 2, 4, 6, 8, 10, 12, 0xFFFF},
573 {14, 16, 0xFFFF},
574 {18, 20, 22, 24, 26, 28, 30, 0xFFFF},
575 {0xFFFF}, /* not used */
576 {0xFFFF}, /* not used */
577 {0xFFFF}, /* not used */
578 {0xFFFF}, /* not used */
579 {0xFFFF}, /* not used */
580 },
581 {/* QUAT TDM */
582 {0xFFFF}, /* not used */
583 {0xFFFF}, /* not used */
584 {0xFFFF}, /* not used */
585 {0xFFFF}, /* not used */
586 {0xFFFF}, /* not used */
587 {0xFFFF}, /* not used */
588 {0xFFFF}, /* not used */
589 {0xFFFF}, /* not used */
590 },
591 {/* QUIN TDM */
592 {0xFFFF}, /* not used */
593 {0xFFFF}, /* not used */
594 {0xFFFF}, /* not used */
595 {0xFFFF}, /* not used */
596 {0xFFFF}, /* not used */
597 {0xFFFF}, /* not used */
598 {0xFFFF}, /* not used */
599 {0xFFFF}, /* not used */
600 }
601};
602
603
604static char const *bit_format_text[] = {"S16_LE", "S24_LE", "S24_3LE",
605 "S32_LE"};
606static char const *ext_disp_bit_format_text[] = {"S16_LE", "S24_LE",
607 "S24_3LE"};
608static const char *const usb_ch_text[] = {"One", "Two", "Three", "Four",
609 "Five", "Six", "Seven",
610 "Eight"};
611static char const *ch_text[] = {"Two", "Three", "Four", "Five",
612 "Six", "Seven", "Eight"};
613static char const *usb_sample_rate_text[] = {"KHZ_8", "KHZ_11P025",
614 "KHZ_16", "KHZ_22P05",
615 "KHZ_32", "KHZ_44P1", "KHZ_48",
616 "KHZ_88P2", "KHZ_96", "KHZ_176P4",
617 "KHZ_192", "KHZ_352P8", "KHZ_384"};
618static char const *ext_disp_sample_rate_text[] = {"KHZ_48", "KHZ_96",
619 "KHZ_192", "KHZ_32", "KHZ_44P1",
620 "KHZ_88P2", "KHZ_176P4"};
621static char const *tdm_ch_text[] = {
622 "One", "Two", "Three", "Four",
623 "Five", "Six", "Seven", "Eight",
624 "Nine", "Ten", "Eleven", "Twelve",
625 "Thirteen", "Fourteen", "Fifteen", "Sixteen",
626 "Seventeen", "Eighteen", "Nineteen", "Twenty",
627 "TwentyOne", "TwentyTwo", "TwentyThree", "TwentyFour",
628 "TwentyFive", "TwentySix", "TwentySeven", "TwentyEight",
629 "TwentyNine", "Thirty", "ThirtyOne", "ThirtyTwo"};
630static char const *tdm_bit_format_text[] = {"S16_LE", "S24_LE", "S32_LE"};
631static char const *tdm_sample_rate_text[] = {"KHZ_8", "KHZ_16", "KHZ_32",
632 "KHZ_48", "KHZ_176P4",
633 "KHZ_352P8"};
634static const char *const tdm_slot_num_text[] = {"One", "Two", "Four",
635 "Eight", "Sixteen", "ThirtyTwo"};
636static const char *const tdm_slot_width_text[] = {"16", "24", "32"};
637static const char *const auxpcm_rate_text[] = {"KHZ_8", "KHZ_16"};
638static char const *mi2s_rate_text[] = {"KHZ_8", "KHZ_11P025", "KHZ_16",
639 "KHZ_22P05", "KHZ_32", "KHZ_44P1",
640 "KHZ_48", "KHZ_96", "KHZ_192"};
641static const char *const mi2s_ch_text[] = {"One", "Two", "Three", "Four",
642 "Five", "Six", "Seven",
643 "Eight"};
644static const char *const qos_text[] = {"Disable", "Enable"};
645
646static SOC_ENUM_SINGLE_EXT_DECL(usb_rx_chs, usb_ch_text);
647static SOC_ENUM_SINGLE_EXT_DECL(usb_tx_chs, usb_ch_text);
648static SOC_ENUM_SINGLE_EXT_DECL(ext_disp_rx_chs, ch_text);
649static SOC_ENUM_SINGLE_EXT_DECL(proxy_rx_chs, ch_text);
650static SOC_ENUM_SINGLE_EXT_DECL(usb_rx_format, bit_format_text);
651static SOC_ENUM_SINGLE_EXT_DECL(usb_tx_format, bit_format_text);
652static SOC_ENUM_SINGLE_EXT_DECL(ext_disp_rx_format, ext_disp_bit_format_text);
653static SOC_ENUM_SINGLE_EXT_DECL(usb_rx_sample_rate, usb_sample_rate_text);
654static SOC_ENUM_SINGLE_EXT_DECL(usb_tx_sample_rate, usb_sample_rate_text);
655static SOC_ENUM_SINGLE_EXT_DECL(ext_disp_rx_sample_rate,
656 ext_disp_sample_rate_text);
657static SOC_ENUM_SINGLE_EXT_DECL(tdm_tx_chs, tdm_ch_text);
658static SOC_ENUM_SINGLE_EXT_DECL(tdm_tx_format, tdm_bit_format_text);
659static SOC_ENUM_SINGLE_EXT_DECL(tdm_tx_sample_rate, tdm_sample_rate_text);
660static SOC_ENUM_SINGLE_EXT_DECL(tdm_rx_chs, tdm_ch_text);
661static SOC_ENUM_SINGLE_EXT_DECL(tdm_rx_format, tdm_bit_format_text);
662static SOC_ENUM_SINGLE_EXT_DECL(tdm_rx_sample_rate, tdm_sample_rate_text);
663static SOC_ENUM_SINGLE_EXT_DECL(tdm_slot_num, tdm_slot_num_text);
664static SOC_ENUM_SINGLE_EXT_DECL(tdm_slot_width, tdm_slot_width_text);
665static SOC_ENUM_SINGLE_EXT_DECL(prim_aux_pcm_rx_sample_rate, auxpcm_rate_text);
666static SOC_ENUM_SINGLE_EXT_DECL(sec_aux_pcm_rx_sample_rate, auxpcm_rate_text);
667static SOC_ENUM_SINGLE_EXT_DECL(tert_aux_pcm_rx_sample_rate, auxpcm_rate_text);
668static SOC_ENUM_SINGLE_EXT_DECL(quat_aux_pcm_rx_sample_rate, auxpcm_rate_text);
669static SOC_ENUM_SINGLE_EXT_DECL(quin_aux_pcm_rx_sample_rate, auxpcm_rate_text);
670static SOC_ENUM_SINGLE_EXT_DECL(prim_aux_pcm_tx_sample_rate, auxpcm_rate_text);
671static SOC_ENUM_SINGLE_EXT_DECL(sec_aux_pcm_tx_sample_rate, auxpcm_rate_text);
672static SOC_ENUM_SINGLE_EXT_DECL(tert_aux_pcm_tx_sample_rate, auxpcm_rate_text);
673static SOC_ENUM_SINGLE_EXT_DECL(quat_aux_pcm_tx_sample_rate, auxpcm_rate_text);
674static SOC_ENUM_SINGLE_EXT_DECL(quin_aux_pcm_tx_sample_rate, auxpcm_rate_text);
675static SOC_ENUM_SINGLE_EXT_DECL(prim_mi2s_rx_sample_rate, mi2s_rate_text);
676static SOC_ENUM_SINGLE_EXT_DECL(sec_mi2s_rx_sample_rate, mi2s_rate_text);
677static SOC_ENUM_SINGLE_EXT_DECL(tert_mi2s_rx_sample_rate, mi2s_rate_text);
678static SOC_ENUM_SINGLE_EXT_DECL(quat_mi2s_rx_sample_rate, mi2s_rate_text);
679static SOC_ENUM_SINGLE_EXT_DECL(quin_mi2s_rx_sample_rate, mi2s_rate_text);
680static SOC_ENUM_SINGLE_EXT_DECL(prim_mi2s_tx_sample_rate, mi2s_rate_text);
681static SOC_ENUM_SINGLE_EXT_DECL(sec_mi2s_tx_sample_rate, mi2s_rate_text);
682static SOC_ENUM_SINGLE_EXT_DECL(tert_mi2s_tx_sample_rate, mi2s_rate_text);
683static SOC_ENUM_SINGLE_EXT_DECL(quat_mi2s_tx_sample_rate, mi2s_rate_text);
684static SOC_ENUM_SINGLE_EXT_DECL(quin_mi2s_tx_sample_rate, mi2s_rate_text);
685static SOC_ENUM_SINGLE_EXT_DECL(prim_mi2s_rx_chs, mi2s_ch_text);
686static SOC_ENUM_SINGLE_EXT_DECL(prim_mi2s_tx_chs, mi2s_ch_text);
687static SOC_ENUM_SINGLE_EXT_DECL(sec_mi2s_rx_chs, mi2s_ch_text);
688static SOC_ENUM_SINGLE_EXT_DECL(sec_mi2s_tx_chs, mi2s_ch_text);
689static SOC_ENUM_SINGLE_EXT_DECL(tert_mi2s_rx_chs, mi2s_ch_text);
690static SOC_ENUM_SINGLE_EXT_DECL(tert_mi2s_tx_chs, mi2s_ch_text);
691static SOC_ENUM_SINGLE_EXT_DECL(quat_mi2s_rx_chs, mi2s_ch_text);
692static SOC_ENUM_SINGLE_EXT_DECL(quat_mi2s_tx_chs, mi2s_ch_text);
693static SOC_ENUM_SINGLE_EXT_DECL(quin_mi2s_rx_chs, mi2s_ch_text);
694static SOC_ENUM_SINGLE_EXT_DECL(quin_mi2s_tx_chs, mi2s_ch_text);
695static SOC_ENUM_SINGLE_EXT_DECL(mi2s_rx_format, bit_format_text);
696static SOC_ENUM_SINGLE_EXT_DECL(mi2s_tx_format, bit_format_text);
697static SOC_ENUM_SINGLE_EXT_DECL(aux_pcm_rx_format, bit_format_text);
698static SOC_ENUM_SINGLE_EXT_DECL(aux_pcm_tx_format, bit_format_text);
699
700static bool is_initial_boot = true;
701
702static struct afe_clk_set mi2s_clk[MI2S_MAX] = {
703 {
704 AFE_API_VERSION_I2S_CONFIG,
705 Q6AFE_LPASS_CLK_ID_PRI_MI2S_IBIT,
706 Q6AFE_LPASS_IBIT_CLK_1_P536_MHZ,
707 Q6AFE_LPASS_CLK_ATTRIBUTE_COUPLE_NO,
708 Q6AFE_LPASS_CLK_ROOT_DEFAULT,
709 0,
710 },
711 {
712 AFE_API_VERSION_I2S_CONFIG,
713 Q6AFE_LPASS_CLK_ID_SEC_MI2S_IBIT,
714 Q6AFE_LPASS_IBIT_CLK_1_P536_MHZ,
715 Q6AFE_LPASS_CLK_ATTRIBUTE_COUPLE_NO,
716 Q6AFE_LPASS_CLK_ROOT_DEFAULT,
717 0,
718 },
719 {
720 AFE_API_VERSION_I2S_CONFIG,
721 Q6AFE_LPASS_CLK_ID_TER_MI2S_IBIT,
722 Q6AFE_LPASS_IBIT_CLK_1_P536_MHZ,
723 Q6AFE_LPASS_CLK_ATTRIBUTE_COUPLE_NO,
724 Q6AFE_LPASS_CLK_ROOT_DEFAULT,
725 0,
726 },
727 {
728 AFE_API_VERSION_I2S_CONFIG,
729 Q6AFE_LPASS_CLK_ID_QUAD_MI2S_IBIT,
730 Q6AFE_LPASS_IBIT_CLK_1_P536_MHZ,
731 Q6AFE_LPASS_CLK_ATTRIBUTE_COUPLE_NO,
732 Q6AFE_LPASS_CLK_ROOT_DEFAULT,
733 0,
734 },
735 {
736 AFE_API_VERSION_I2S_CONFIG,
737 Q6AFE_LPASS_CLK_ID_QUI_MI2S_IBIT,
738 Q6AFE_LPASS_IBIT_CLK_1_P536_MHZ,
739 Q6AFE_LPASS_CLK_ATTRIBUTE_COUPLE_NO,
740 Q6AFE_LPASS_CLK_ROOT_DEFAULT,
741 0,
742 }
743
744};
745
746static struct mi2s_conf mi2s_intf_conf[MI2S_MAX];
747
748static int usb_audio_rx_ch_get(struct snd_kcontrol *kcontrol,
749 struct snd_ctl_elem_value *ucontrol)
750{
751 pr_debug("%s: usb_audio_rx_ch = %d\n", __func__,
752 usb_rx_cfg.channels);
753 ucontrol->value.integer.value[0] = usb_rx_cfg.channels - 1;
754 return 0;
755}
756
757static int usb_audio_rx_ch_put(struct snd_kcontrol *kcontrol,
758 struct snd_ctl_elem_value *ucontrol)
759{
760 usb_rx_cfg.channels = ucontrol->value.integer.value[0] + 1;
761
762 pr_debug("%s: usb_audio_rx_ch = %d\n", __func__, usb_rx_cfg.channels);
763 return 1;
764}
765
766static int usb_audio_rx_sample_rate_get(struct snd_kcontrol *kcontrol,
767 struct snd_ctl_elem_value *ucontrol)
768{
769 int sample_rate_val;
770
771 switch (usb_rx_cfg.sample_rate) {
772 case SAMPLING_RATE_384KHZ:
773 sample_rate_val = 12;
774 break;
775 case SAMPLING_RATE_352P8KHZ:
776 sample_rate_val = 11;
777 break;
778 case SAMPLING_RATE_192KHZ:
779 sample_rate_val = 10;
780 break;
781 case SAMPLING_RATE_176P4KHZ:
782 sample_rate_val = 9;
783 break;
784 case SAMPLING_RATE_96KHZ:
785 sample_rate_val = 8;
786 break;
787 case SAMPLING_RATE_88P2KHZ:
788 sample_rate_val = 7;
789 break;
790 case SAMPLING_RATE_48KHZ:
791 sample_rate_val = 6;
792 break;
793 case SAMPLING_RATE_44P1KHZ:
794 sample_rate_val = 5;
795 break;
796 case SAMPLING_RATE_32KHZ:
797 sample_rate_val = 4;
798 break;
799 case SAMPLING_RATE_22P05KHZ:
800 sample_rate_val = 3;
801 break;
802 case SAMPLING_RATE_16KHZ:
803 sample_rate_val = 2;
804 break;
805 case SAMPLING_RATE_11P025KHZ:
806 sample_rate_val = 1;
807 break;
808 case SAMPLING_RATE_8KHZ:
809 default:
810 sample_rate_val = 0;
811 break;
812 }
813
814 ucontrol->value.integer.value[0] = sample_rate_val;
815 pr_debug("%s: usb_audio_rx_sample_rate = %d\n", __func__,
816 usb_rx_cfg.sample_rate);
817 return 0;
818}
819
820static int usb_audio_rx_sample_rate_put(struct snd_kcontrol *kcontrol,
821 struct snd_ctl_elem_value *ucontrol)
822{
823 switch (ucontrol->value.integer.value[0]) {
824 case 12:
825 usb_rx_cfg.sample_rate = SAMPLING_RATE_384KHZ;
826 break;
827 case 11:
828 usb_rx_cfg.sample_rate = SAMPLING_RATE_352P8KHZ;
829 break;
830 case 10:
831 usb_rx_cfg.sample_rate = SAMPLING_RATE_192KHZ;
832 break;
833 case 9:
834 usb_rx_cfg.sample_rate = SAMPLING_RATE_176P4KHZ;
835 break;
836 case 8:
837 usb_rx_cfg.sample_rate = SAMPLING_RATE_96KHZ;
838 break;
839 case 7:
840 usb_rx_cfg.sample_rate = SAMPLING_RATE_88P2KHZ;
841 break;
842 case 6:
843 usb_rx_cfg.sample_rate = SAMPLING_RATE_48KHZ;
844 break;
845 case 5:
846 usb_rx_cfg.sample_rate = SAMPLING_RATE_44P1KHZ;
847 break;
848 case 4:
849 usb_rx_cfg.sample_rate = SAMPLING_RATE_32KHZ;
850 break;
851 case 3:
852 usb_rx_cfg.sample_rate = SAMPLING_RATE_22P05KHZ;
853 break;
854 case 2:
855 usb_rx_cfg.sample_rate = SAMPLING_RATE_16KHZ;
856 break;
857 case 1:
858 usb_rx_cfg.sample_rate = SAMPLING_RATE_11P025KHZ;
859 break;
860 case 0:
861 usb_rx_cfg.sample_rate = SAMPLING_RATE_8KHZ;
862 break;
863 default:
864 usb_rx_cfg.sample_rate = SAMPLING_RATE_48KHZ;
865 break;
866 }
867
868 pr_debug("%s: control value = %ld, usb_audio_rx_sample_rate = %d\n",
869 __func__, ucontrol->value.integer.value[0],
870 usb_rx_cfg.sample_rate);
871 return 0;
872}
873
874static int usb_audio_rx_format_get(struct snd_kcontrol *kcontrol,
875 struct snd_ctl_elem_value *ucontrol)
876{
877 switch (usb_rx_cfg.bit_format) {
878 case SNDRV_PCM_FORMAT_S32_LE:
879 ucontrol->value.integer.value[0] = 3;
880 break;
881 case SNDRV_PCM_FORMAT_S24_3LE:
882 ucontrol->value.integer.value[0] = 2;
883 break;
884 case SNDRV_PCM_FORMAT_S24_LE:
885 ucontrol->value.integer.value[0] = 1;
886 break;
887 case SNDRV_PCM_FORMAT_S16_LE:
888 default:
889 ucontrol->value.integer.value[0] = 0;
890 break;
891 }
892
893 pr_debug("%s: usb_audio_rx_format = %d, ucontrol value = %ld\n",
894 __func__, usb_rx_cfg.bit_format,
895 ucontrol->value.integer.value[0]);
896 return 0;
897}
898
899static int usb_audio_rx_format_put(struct snd_kcontrol *kcontrol,
900 struct snd_ctl_elem_value *ucontrol)
901{
902 int rc = 0;
903
904 switch (ucontrol->value.integer.value[0]) {
905 case 3:
906 usb_rx_cfg.bit_format = SNDRV_PCM_FORMAT_S32_LE;
907 break;
908 case 2:
909 usb_rx_cfg.bit_format = SNDRV_PCM_FORMAT_S24_3LE;
910 break;
911 case 1:
912 usb_rx_cfg.bit_format = SNDRV_PCM_FORMAT_S24_LE;
913 break;
914 case 0:
915 default:
916 usb_rx_cfg.bit_format = SNDRV_PCM_FORMAT_S16_LE;
917 break;
918 }
919 pr_debug("%s: usb_audio_rx_format = %d, ucontrol value = %ld\n",
920 __func__, usb_rx_cfg.bit_format,
921 ucontrol->value.integer.value[0]);
922
923 return rc;
924}
925
926static int usb_audio_tx_ch_get(struct snd_kcontrol *kcontrol,
927 struct snd_ctl_elem_value *ucontrol)
928{
929 pr_debug("%s: usb_audio_tx_ch = %d\n", __func__,
930 usb_tx_cfg.channels);
931 ucontrol->value.integer.value[0] = usb_tx_cfg.channels - 1;
932 return 0;
933}
934
935static int usb_audio_tx_ch_put(struct snd_kcontrol *kcontrol,
936 struct snd_ctl_elem_value *ucontrol)
937{
938 usb_tx_cfg.channels = ucontrol->value.integer.value[0] + 1;
939
940 pr_debug("%s: usb_audio_tx_ch = %d\n", __func__, usb_tx_cfg.channels);
941 return 1;
942}
943
944static int usb_audio_tx_sample_rate_get(struct snd_kcontrol *kcontrol,
945 struct snd_ctl_elem_value *ucontrol)
946{
947 int sample_rate_val;
948
949 switch (usb_tx_cfg.sample_rate) {
950 case SAMPLING_RATE_384KHZ:
951 sample_rate_val = 12;
952 break;
953 case SAMPLING_RATE_352P8KHZ:
954 sample_rate_val = 11;
955 break;
956 case SAMPLING_RATE_192KHZ:
957 sample_rate_val = 10;
958 break;
959 case SAMPLING_RATE_176P4KHZ:
960 sample_rate_val = 9;
961 break;
962 case SAMPLING_RATE_96KHZ:
963 sample_rate_val = 8;
964 break;
965 case SAMPLING_RATE_88P2KHZ:
966 sample_rate_val = 7;
967 break;
968 case SAMPLING_RATE_48KHZ:
969 sample_rate_val = 6;
970 break;
971 case SAMPLING_RATE_44P1KHZ:
972 sample_rate_val = 5;
973 break;
974 case SAMPLING_RATE_32KHZ:
975 sample_rate_val = 4;
976 break;
977 case SAMPLING_RATE_22P05KHZ:
978 sample_rate_val = 3;
979 break;
980 case SAMPLING_RATE_16KHZ:
981 sample_rate_val = 2;
982 break;
983 case SAMPLING_RATE_11P025KHZ:
984 sample_rate_val = 1;
985 break;
986 case SAMPLING_RATE_8KHZ:
987 sample_rate_val = 0;
988 break;
989 default:
990 sample_rate_val = 6;
991 break;
992 }
993
994 ucontrol->value.integer.value[0] = sample_rate_val;
995 pr_debug("%s: usb_audio_tx_sample_rate = %d\n", __func__,
996 usb_tx_cfg.sample_rate);
997 return 0;
998}
999
1000static int usb_audio_tx_sample_rate_put(struct snd_kcontrol *kcontrol,
1001 struct snd_ctl_elem_value *ucontrol)
1002{
1003 switch (ucontrol->value.integer.value[0]) {
1004 case 12:
1005 usb_tx_cfg.sample_rate = SAMPLING_RATE_384KHZ;
1006 break;
1007 case 11:
1008 usb_tx_cfg.sample_rate = SAMPLING_RATE_352P8KHZ;
1009 break;
1010 case 10:
1011 usb_tx_cfg.sample_rate = SAMPLING_RATE_192KHZ;
1012 break;
1013 case 9:
1014 usb_tx_cfg.sample_rate = SAMPLING_RATE_176P4KHZ;
1015 break;
1016 case 8:
1017 usb_tx_cfg.sample_rate = SAMPLING_RATE_96KHZ;
1018 break;
1019 case 7:
1020 usb_tx_cfg.sample_rate = SAMPLING_RATE_88P2KHZ;
1021 break;
1022 case 6:
1023 usb_tx_cfg.sample_rate = SAMPLING_RATE_48KHZ;
1024 break;
1025 case 5:
1026 usb_tx_cfg.sample_rate = SAMPLING_RATE_44P1KHZ;
1027 break;
1028 case 4:
1029 usb_tx_cfg.sample_rate = SAMPLING_RATE_32KHZ;
1030 break;
1031 case 3:
1032 usb_tx_cfg.sample_rate = SAMPLING_RATE_22P05KHZ;
1033 break;
1034 case 2:
1035 usb_tx_cfg.sample_rate = SAMPLING_RATE_16KHZ;
1036 break;
1037 case 1:
1038 usb_tx_cfg.sample_rate = SAMPLING_RATE_11P025KHZ;
1039 break;
1040 case 0:
1041 usb_tx_cfg.sample_rate = SAMPLING_RATE_8KHZ;
1042 break;
1043 default:
1044 usb_tx_cfg.sample_rate = SAMPLING_RATE_48KHZ;
1045 break;
1046 }
1047
1048 pr_debug("%s: control value = %ld, usb_audio_tx_sample_rate = %d\n",
1049 __func__, ucontrol->value.integer.value[0],
1050 usb_tx_cfg.sample_rate);
1051 return 0;
1052}
1053
1054static int usb_audio_tx_format_get(struct snd_kcontrol *kcontrol,
1055 struct snd_ctl_elem_value *ucontrol)
1056{
1057 switch (usb_tx_cfg.bit_format) {
1058 case SNDRV_PCM_FORMAT_S32_LE:
1059 ucontrol->value.integer.value[0] = 3;
1060 break;
1061 case SNDRV_PCM_FORMAT_S24_3LE:
1062 ucontrol->value.integer.value[0] = 2;
1063 break;
1064 case SNDRV_PCM_FORMAT_S24_LE:
1065 ucontrol->value.integer.value[0] = 1;
1066 break;
1067 case SNDRV_PCM_FORMAT_S16_LE:
1068 default:
1069 ucontrol->value.integer.value[0] = 0;
1070 break;
1071 }
1072
1073 pr_debug("%s: usb_audio_tx_format = %d, ucontrol value = %ld\n",
1074 __func__, usb_tx_cfg.bit_format,
1075 ucontrol->value.integer.value[0]);
1076 return 0;
1077}
1078
1079static int usb_audio_tx_format_put(struct snd_kcontrol *kcontrol,
1080 struct snd_ctl_elem_value *ucontrol)
1081{
1082 int rc = 0;
1083
1084 switch (ucontrol->value.integer.value[0]) {
1085 case 3:
1086 usb_tx_cfg.bit_format = SNDRV_PCM_FORMAT_S32_LE;
1087 break;
1088 case 2:
1089 usb_tx_cfg.bit_format = SNDRV_PCM_FORMAT_S24_3LE;
1090 break;
1091 case 1:
1092 usb_tx_cfg.bit_format = SNDRV_PCM_FORMAT_S24_LE;
1093 break;
1094 case 0:
1095 default:
1096 usb_tx_cfg.bit_format = SNDRV_PCM_FORMAT_S16_LE;
1097 break;
1098 }
1099 pr_debug("%s: usb_audio_tx_format = %d, ucontrol value = %ld\n",
1100 __func__, usb_tx_cfg.bit_format,
1101 ucontrol->value.integer.value[0]);
1102
1103 return rc;
1104}
1105
1106static int ext_disp_get_port_idx(struct snd_kcontrol *kcontrol)
1107{
1108 int idx = 0;
1109
1110 if (strnstr(kcontrol->id.name, "Display Port RX",
1111 sizeof("Display Port RX"))) {
1112 idx = DP_RX_IDX;
1113 } else {
1114 pr_err("%s: unsupported BE: %s\n",
1115 __func__, kcontrol->id.name);
1116 idx = -EINVAL;
1117 }
1118
1119 return idx;
1120}
1121
1122static int ext_disp_rx_format_get(struct snd_kcontrol *kcontrol,
1123 struct snd_ctl_elem_value *ucontrol)
1124{
1125 int idx = ext_disp_get_port_idx(kcontrol);
1126
1127 if (idx < 0)
1128 return idx;
1129
1130 switch (ext_disp_rx_cfg[idx].bit_format) {
1131 case SNDRV_PCM_FORMAT_S24_3LE:
1132 ucontrol->value.integer.value[0] = 2;
1133 break;
1134 case SNDRV_PCM_FORMAT_S24_LE:
1135 ucontrol->value.integer.value[0] = 1;
1136 break;
1137 case SNDRV_PCM_FORMAT_S16_LE:
1138 default:
1139 ucontrol->value.integer.value[0] = 0;
1140 break;
1141 }
1142
1143 pr_debug("%s: ext_disp_rx[%d].format = %d, ucontrol value = %ld\n",
1144 __func__, idx, ext_disp_rx_cfg[idx].bit_format,
1145 ucontrol->value.integer.value[0]);
1146 return 0;
1147}
1148
1149static int ext_disp_rx_format_put(struct snd_kcontrol *kcontrol,
1150 struct snd_ctl_elem_value *ucontrol)
1151{
1152 int idx = ext_disp_get_port_idx(kcontrol);
1153
1154 if (idx < 0)
1155 return idx;
1156
1157 switch (ucontrol->value.integer.value[0]) {
1158 case 2:
1159 ext_disp_rx_cfg[idx].bit_format = SNDRV_PCM_FORMAT_S24_3LE;
1160 break;
1161 case 1:
1162 ext_disp_rx_cfg[idx].bit_format = SNDRV_PCM_FORMAT_S24_LE;
1163 break;
1164 case 0:
1165 default:
1166 ext_disp_rx_cfg[idx].bit_format = SNDRV_PCM_FORMAT_S16_LE;
1167 break;
1168 }
1169 pr_debug("%s: ext_disp_rx[%d].format = %d, ucontrol value = %ld\n",
1170 __func__, idx, ext_disp_rx_cfg[idx].bit_format,
1171 ucontrol->value.integer.value[0]);
1172
1173 return 0;
1174}
1175
1176static int ext_disp_rx_ch_get(struct snd_kcontrol *kcontrol,
1177 struct snd_ctl_elem_value *ucontrol)
1178{
1179 int idx = ext_disp_get_port_idx(kcontrol);
1180
1181 if (idx < 0)
1182 return idx;
1183
1184 ucontrol->value.integer.value[0] =
1185 ext_disp_rx_cfg[idx].channels - 2;
1186
1187 pr_debug("%s: ext_disp_rx[%d].ch = %d\n", __func__,
1188 idx, ext_disp_rx_cfg[idx].channels);
1189
1190 return 0;
1191}
1192
1193static int ext_disp_rx_ch_put(struct snd_kcontrol *kcontrol,
1194 struct snd_ctl_elem_value *ucontrol)
1195{
1196 int idx = ext_disp_get_port_idx(kcontrol);
1197
1198 if (idx < 0)
1199 return idx;
1200
1201 ext_disp_rx_cfg[idx].channels =
1202 ucontrol->value.integer.value[0] + 2;
1203
1204 pr_debug("%s: ext_disp_rx[%d].ch = %d\n", __func__,
1205 idx, ext_disp_rx_cfg[idx].channels);
1206 return 1;
1207}
1208
1209static int ext_disp_rx_sample_rate_get(struct snd_kcontrol *kcontrol,
1210 struct snd_ctl_elem_value *ucontrol)
1211{
1212 int sample_rate_val;
1213 int idx = ext_disp_get_port_idx(kcontrol);
1214
1215 if (idx < 0)
1216 return idx;
1217
1218 switch (ext_disp_rx_cfg[idx].sample_rate) {
1219 case SAMPLING_RATE_176P4KHZ:
1220 sample_rate_val = 6;
1221 break;
1222
1223 case SAMPLING_RATE_88P2KHZ:
1224 sample_rate_val = 5;
1225 break;
1226
1227 case SAMPLING_RATE_44P1KHZ:
1228 sample_rate_val = 4;
1229 break;
1230
1231 case SAMPLING_RATE_32KHZ:
1232 sample_rate_val = 3;
1233 break;
1234
1235 case SAMPLING_RATE_192KHZ:
1236 sample_rate_val = 2;
1237 break;
1238
1239 case SAMPLING_RATE_96KHZ:
1240 sample_rate_val = 1;
1241 break;
1242
1243 case SAMPLING_RATE_48KHZ:
1244 default:
1245 sample_rate_val = 0;
1246 break;
1247 }
1248
1249 ucontrol->value.integer.value[0] = sample_rate_val;
1250 pr_debug("%s: ext_disp_rx[%d].sample_rate = %d\n", __func__,
1251 idx, ext_disp_rx_cfg[idx].sample_rate);
1252
1253 return 0;
1254}
1255
1256static int ext_disp_rx_sample_rate_put(struct snd_kcontrol *kcontrol,
1257 struct snd_ctl_elem_value *ucontrol)
1258{
1259 int idx = ext_disp_get_port_idx(kcontrol);
1260
1261 if (idx < 0)
1262 return idx;
1263
1264 switch (ucontrol->value.integer.value[0]) {
1265 case 6:
1266 ext_disp_rx_cfg[idx].sample_rate = SAMPLING_RATE_176P4KHZ;
1267 break;
1268 case 5:
1269 ext_disp_rx_cfg[idx].sample_rate = SAMPLING_RATE_88P2KHZ;
1270 break;
1271 case 4:
1272 ext_disp_rx_cfg[idx].sample_rate = SAMPLING_RATE_44P1KHZ;
1273 break;
1274 case 3:
1275 ext_disp_rx_cfg[idx].sample_rate = SAMPLING_RATE_32KHZ;
1276 break;
1277 case 2:
1278 ext_disp_rx_cfg[idx].sample_rate = SAMPLING_RATE_192KHZ;
1279 break;
1280 case 1:
1281 ext_disp_rx_cfg[idx].sample_rate = SAMPLING_RATE_96KHZ;
1282 break;
1283 case 0:
1284 default:
1285 ext_disp_rx_cfg[idx].sample_rate = SAMPLING_RATE_48KHZ;
1286 break;
1287 }
1288
1289 pr_debug("%s: control value = %ld, ext_disp_rx[%d].sample_rate = %d\n",
1290 __func__, ucontrol->value.integer.value[0], idx,
1291 ext_disp_rx_cfg[idx].sample_rate);
1292 return 0;
1293}
1294
1295static int proxy_rx_ch_get(struct snd_kcontrol *kcontrol,
1296 struct snd_ctl_elem_value *ucontrol)
1297{
1298 pr_debug("%s: proxy_rx channels = %d\n",
1299 __func__, proxy_rx_cfg.channels);
1300 ucontrol->value.integer.value[0] = proxy_rx_cfg.channels - 2;
1301
1302 return 0;
1303}
1304
1305static int proxy_rx_ch_put(struct snd_kcontrol *kcontrol,
1306 struct snd_ctl_elem_value *ucontrol)
1307{
1308 proxy_rx_cfg.channels = ucontrol->value.integer.value[0] + 2;
1309 pr_debug("%s: proxy_rx channels = %d\n",
1310 __func__, proxy_rx_cfg.channels);
1311
1312 return 1;
1313}
1314
1315static int tdm_get_sample_rate(int value)
1316{
1317 int sample_rate = 0;
1318
1319 switch (value) {
1320 case 0:
1321 sample_rate = SAMPLING_RATE_8KHZ;
1322 break;
1323 case 1:
1324 sample_rate = SAMPLING_RATE_16KHZ;
1325 break;
1326 case 2:
1327 sample_rate = SAMPLING_RATE_32KHZ;
1328 break;
1329 case 3:
1330 sample_rate = SAMPLING_RATE_48KHZ;
1331 break;
1332 case 4:
1333 sample_rate = SAMPLING_RATE_176P4KHZ;
1334 break;
1335 case 5:
1336 sample_rate = SAMPLING_RATE_352P8KHZ;
1337 break;
1338 default:
1339 sample_rate = SAMPLING_RATE_48KHZ;
1340 break;
1341 }
1342 return sample_rate;
1343}
1344
1345static int aux_pcm_get_sample_rate(int value)
1346{
1347 int sample_rate;
1348
1349 switch (value) {
1350 case 1:
1351 sample_rate = SAMPLING_RATE_16KHZ;
1352 break;
1353 case 0:
1354 default:
1355 sample_rate = SAMPLING_RATE_8KHZ;
1356 break;
1357 }
1358 return sample_rate;
1359}
1360
1361static int tdm_get_sample_rate_val(int sample_rate)
1362{
1363 int sample_rate_val = 0;
1364
1365 switch (sample_rate) {
1366 case SAMPLING_RATE_8KHZ:
1367 sample_rate_val = 0;
1368 break;
1369 case SAMPLING_RATE_16KHZ:
1370 sample_rate_val = 1;
1371 break;
1372 case SAMPLING_RATE_32KHZ:
1373 sample_rate_val = 2;
1374 break;
1375 case SAMPLING_RATE_48KHZ:
1376 sample_rate_val = 3;
1377 break;
1378 case SAMPLING_RATE_176P4KHZ:
1379 sample_rate_val = 4;
1380 break;
1381 case SAMPLING_RATE_352P8KHZ:
1382 sample_rate_val = 5;
1383 break;
1384 default:
1385 sample_rate_val = 3;
1386 break;
1387 }
1388 return sample_rate_val;
1389}
1390
1391static int aux_pcm_get_sample_rate_val(int sample_rate)
1392{
1393 int sample_rate_val = 0;
1394
1395 switch (sample_rate) {
1396 case SAMPLING_RATE_16KHZ:
1397 sample_rate_val = 1;
1398 break;
1399 case SAMPLING_RATE_8KHZ:
1400 default:
1401 sample_rate_val = 0;
1402 break;
1403 }
1404 return sample_rate_val;
1405}
1406
1407static int tdm_get_mode(struct snd_kcontrol *kcontrol)
1408{
1409 int mode = TDM_PRI;
1410
1411 if (strnstr(kcontrol->id.name, "PRI",
1412 sizeof(kcontrol->id.name))) {
1413 mode = TDM_PRI;
1414 } else if (strnstr(kcontrol->id.name, "SEC",
1415 sizeof(kcontrol->id.name))) {
1416 mode = TDM_SEC;
1417 } else if (strnstr(kcontrol->id.name, "TERT",
1418 sizeof(kcontrol->id.name))) {
1419 mode = TDM_TERT;
1420 } else if (strnstr(kcontrol->id.name, "QUAT",
1421 sizeof(kcontrol->id.name))) {
1422 mode = TDM_QUAT;
1423 } else if (strnstr(kcontrol->id.name, "QUIN",
1424 sizeof(kcontrol->id.name))) {
1425 mode = TDM_QUIN;
1426 } else {
1427 pr_err("%s: unsupported mode in: %s",
1428 __func__, kcontrol->id.name);
1429 mode = -EINVAL;
1430 }
1431
1432 return mode;
1433}
1434
1435static int tdm_get_channel(struct snd_kcontrol *kcontrol)
1436{
1437 int channel = TDM_0;
1438
1439 if (strnstr(kcontrol->id.name, "RX_0",
1440 sizeof(kcontrol->id.name)) ||
1441 strnstr(kcontrol->id.name, "TX_0",
1442 sizeof(kcontrol->id.name))) {
1443 channel = TDM_0;
1444 } else if (strnstr(kcontrol->id.name, "RX_1",
1445 sizeof(kcontrol->id.name)) ||
1446 strnstr(kcontrol->id.name, "TX_1",
1447 sizeof(kcontrol->id.name))) {
1448 channel = TDM_1;
1449 } else if (strnstr(kcontrol->id.name, "RX_2",
1450 sizeof(kcontrol->id.name)) ||
1451 strnstr(kcontrol->id.name, "TX_2",
1452 sizeof(kcontrol->id.name))) {
1453 channel = TDM_2;
1454 } else if (strnstr(kcontrol->id.name, "RX_3",
1455 sizeof(kcontrol->id.name)) ||
1456 strnstr(kcontrol->id.name, "TX_3",
1457 sizeof(kcontrol->id.name))) {
1458 channel = TDM_3;
1459 } else if (strnstr(kcontrol->id.name, "RX_4",
1460 sizeof(kcontrol->id.name)) ||
1461 strnstr(kcontrol->id.name, "TX_4",
1462 sizeof(kcontrol->id.name))) {
1463 channel = TDM_4;
1464 } else if (strnstr(kcontrol->id.name, "RX_5",
1465 sizeof(kcontrol->id.name)) ||
1466 strnstr(kcontrol->id.name, "TX_5",
1467 sizeof(kcontrol->id.name))) {
1468 channel = TDM_5;
1469 } else if (strnstr(kcontrol->id.name, "RX_6",
1470 sizeof(kcontrol->id.name)) ||
1471 strnstr(kcontrol->id.name, "TX_6",
1472 sizeof(kcontrol->id.name))) {
1473 channel = TDM_6;
1474 } else if (strnstr(kcontrol->id.name, "RX_7",
1475 sizeof(kcontrol->id.name)) ||
1476 strnstr(kcontrol->id.name, "TX_7",
1477 sizeof(kcontrol->id.name))) {
1478 channel = TDM_7;
1479 } else {
1480 pr_err("%s: unsupported channel in: %s",
1481 __func__, kcontrol->id.name);
1482 channel = -EINVAL;
1483 }
1484
1485 return channel;
1486}
1487
1488static int tdm_get_port_idx(struct snd_kcontrol *kcontrol,
1489 struct tdm_port *port)
1490{
1491 if (port) {
1492 port->mode = tdm_get_mode(kcontrol);
1493 if (port->mode < 0)
1494 return port->mode;
1495
1496 port->channel = tdm_get_channel(kcontrol);
1497 if (port->channel < 0)
1498 return port->channel;
1499 } else {
1500 return -EINVAL;
1501 }
1502 return 0;
1503}
1504
1505static int tdm_rx_sample_rate_get(struct snd_kcontrol *kcontrol,
1506 struct snd_ctl_elem_value *ucontrol)
1507{
1508 struct tdm_port port;
1509 int ret = tdm_get_port_idx(kcontrol, &port);
1510
1511 if (ret) {
1512 pr_err("%s: unsupported control: %s\n",
1513 __func__, kcontrol->id.name);
1514 } else {
1515 ucontrol->value.enumerated.item[0] = tdm_get_sample_rate_val(
1516 tdm_rx_cfg[port.mode][port.channel].sample_rate);
1517
1518 pr_debug("%s: tdm_rx_sample_rate = %d, item = %d\n", __func__,
1519 tdm_rx_cfg[port.mode][port.channel].sample_rate,
1520 ucontrol->value.enumerated.item[0]);
1521 }
1522 return ret;
1523}
1524
1525static int tdm_rx_sample_rate_put(struct snd_kcontrol *kcontrol,
1526 struct snd_ctl_elem_value *ucontrol)
1527{
1528 struct tdm_port port;
1529 int ret = tdm_get_port_idx(kcontrol, &port);
1530
1531 if (ret) {
1532 pr_err("%s: unsupported control: %s\n",
1533 __func__, kcontrol->id.name);
1534 } else {
1535 tdm_rx_cfg[port.mode][port.channel].sample_rate =
1536 tdm_get_sample_rate(ucontrol->value.enumerated.item[0]);
1537
1538 pr_debug("%s: tdm_rx_sample_rate = %d, item = %d\n", __func__,
1539 tdm_rx_cfg[port.mode][port.channel].sample_rate,
1540 ucontrol->value.enumerated.item[0]);
1541 }
1542 return ret;
1543}
1544
1545static int tdm_tx_sample_rate_get(struct snd_kcontrol *kcontrol,
1546 struct snd_ctl_elem_value *ucontrol)
1547{
1548 struct tdm_port port;
1549 int ret = tdm_get_port_idx(kcontrol, &port);
1550
1551 if (ret) {
1552 pr_err("%s: unsupported control: %s",
1553 __func__, kcontrol->id.name);
1554 } else {
1555 ucontrol->value.enumerated.item[0] = tdm_get_sample_rate_val(
1556 tdm_tx_cfg[port.mode][port.channel].sample_rate);
1557
1558 pr_debug("%s: tdm_tx_sample_rate = %d, item = %d\n", __func__,
1559 tdm_tx_cfg[port.mode][port.channel].sample_rate,
1560 ucontrol->value.enumerated.item[0]);
1561 }
1562 return ret;
1563}
1564
1565static int tdm_tx_sample_rate_put(struct snd_kcontrol *kcontrol,
1566 struct snd_ctl_elem_value *ucontrol)
1567{
1568 struct tdm_port port;
1569 int ret = tdm_get_port_idx(kcontrol, &port);
1570
1571 if (ret) {
1572 pr_err("%s: unsupported control: %s\n",
1573 __func__, kcontrol->id.name);
1574 } else {
1575 tdm_tx_cfg[port.mode][port.channel].sample_rate =
1576 tdm_get_sample_rate(ucontrol->value.enumerated.item[0]);
1577
1578 pr_debug("%s: tdm_tx_sample_rate = %d, item = %d\n", __func__,
1579 tdm_tx_cfg[port.mode][port.channel].sample_rate,
1580 ucontrol->value.enumerated.item[0]);
1581 }
1582 return ret;
1583}
1584
1585static int tdm_get_format(int value)
1586{
1587 int format = 0;
1588
1589 switch (value) {
1590 case 0:
1591 format = SNDRV_PCM_FORMAT_S16_LE;
1592 break;
1593 case 1:
1594 format = SNDRV_PCM_FORMAT_S24_LE;
1595 break;
1596 case 2:
1597 format = SNDRV_PCM_FORMAT_S32_LE;
1598 break;
1599 default:
1600 format = SNDRV_PCM_FORMAT_S16_LE;
1601 break;
1602 }
1603 return format;
1604}
1605
1606static int tdm_get_format_val(int format)
1607{
1608 int value = 0;
1609
1610 switch (format) {
1611 case SNDRV_PCM_FORMAT_S16_LE:
1612 value = 0;
1613 break;
1614 case SNDRV_PCM_FORMAT_S24_LE:
1615 value = 1;
1616 break;
1617 case SNDRV_PCM_FORMAT_S32_LE:
1618 value = 2;
1619 break;
1620 default:
1621 value = 0;
1622 break;
1623 }
1624 return value;
1625}
1626
1627static int tdm_rx_format_get(struct snd_kcontrol *kcontrol,
1628 struct snd_ctl_elem_value *ucontrol)
1629{
1630 struct tdm_port port;
1631 int ret = tdm_get_port_idx(kcontrol, &port);
1632
1633 if (ret) {
1634 pr_err("%s: unsupported control: %s\n",
1635 __func__, kcontrol->id.name);
1636 } else {
1637 ucontrol->value.enumerated.item[0] = tdm_get_format_val(
1638 tdm_rx_cfg[port.mode][port.channel].bit_format);
1639
1640 pr_debug("%s: tdm_rx_bit_format = %d, item = %d\n", __func__,
1641 tdm_rx_cfg[port.mode][port.channel].bit_format,
1642 ucontrol->value.enumerated.item[0]);
1643 }
1644 return ret;
1645}
1646
1647static int tdm_rx_format_put(struct snd_kcontrol *kcontrol,
1648 struct snd_ctl_elem_value *ucontrol)
1649{
1650 struct tdm_port port;
1651 int ret = tdm_get_port_idx(kcontrol, &port);
1652
1653 if (ret) {
1654 pr_err("%s: unsupported control: %s\n",
1655 __func__, kcontrol->id.name);
1656 } else {
1657 tdm_rx_cfg[port.mode][port.channel].bit_format =
1658 tdm_get_format(ucontrol->value.enumerated.item[0]);
1659
1660 pr_debug("%s: tdm_rx_bit_format = %d, item = %d\n", __func__,
1661 tdm_rx_cfg[port.mode][port.channel].bit_format,
1662 ucontrol->value.enumerated.item[0]);
1663 }
1664 return ret;
1665}
1666
1667static int tdm_tx_format_get(struct snd_kcontrol *kcontrol,
1668 struct snd_ctl_elem_value *ucontrol)
1669{
1670 struct tdm_port port;
1671 int ret = tdm_get_port_idx(kcontrol, &port);
1672
1673 if (ret) {
1674 pr_err("%s: unsupported control: %s\n",
1675 __func__, kcontrol->id.name);
1676 } else {
1677 ucontrol->value.enumerated.item[0] = tdm_get_format_val(
1678 tdm_tx_cfg[port.mode][port.channel].bit_format);
1679
1680 pr_debug("%s: tdm_tx_bit_format = %d, item = %d\n", __func__,
1681 tdm_tx_cfg[port.mode][port.channel].bit_format,
1682 ucontrol->value.enumerated.item[0]);
1683 }
1684 return ret;
1685}
1686
1687static int tdm_tx_format_put(struct snd_kcontrol *kcontrol,
1688 struct snd_ctl_elem_value *ucontrol)
1689{
1690 struct tdm_port port;
1691 int ret = tdm_get_port_idx(kcontrol, &port);
1692
1693 if (ret) {
1694 pr_err("%s: unsupported control: %s\n",
1695 __func__, kcontrol->id.name);
1696 } else {
1697 tdm_tx_cfg[port.mode][port.channel].bit_format =
1698 tdm_get_format(ucontrol->value.enumerated.item[0]);
1699
1700 pr_debug("%s: tdm_tx_bit_format = %d, item = %d\n", __func__,
1701 tdm_tx_cfg[port.mode][port.channel].bit_format,
1702 ucontrol->value.enumerated.item[0]);
1703 }
1704 return ret;
1705}
1706
1707static int tdm_rx_ch_get(struct snd_kcontrol *kcontrol,
1708 struct snd_ctl_elem_value *ucontrol)
1709{
1710 struct tdm_port port;
1711 int ret = tdm_get_port_idx(kcontrol, &port);
1712
1713 if (ret) {
1714 pr_err("%s: unsupported control: %s\n",
1715 __func__, kcontrol->id.name);
1716 } else {
1717
1718 ucontrol->value.enumerated.item[0] =
1719 tdm_rx_cfg[port.mode][port.channel].channels - 1;
1720
1721 pr_debug("%s: tdm_rx_ch = %d, item = %d\n", __func__,
1722 tdm_rx_cfg[port.mode][port.channel].channels - 1,
1723 ucontrol->value.enumerated.item[0]);
1724 }
1725 return ret;
1726}
1727
1728static int tdm_rx_ch_put(struct snd_kcontrol *kcontrol,
1729 struct snd_ctl_elem_value *ucontrol)
1730{
1731 struct tdm_port port;
1732 int ret = tdm_get_port_idx(kcontrol, &port);
1733
1734 if (ret) {
1735 pr_err("%s: unsupported control: %s\n",
1736 __func__, kcontrol->id.name);
1737 } else {
1738 tdm_rx_cfg[port.mode][port.channel].channels =
1739 ucontrol->value.enumerated.item[0] + 1;
1740
1741 pr_debug("%s: tdm_rx_ch = %d, item = %d\n", __func__,
1742 tdm_rx_cfg[port.mode][port.channel].channels,
1743 ucontrol->value.enumerated.item[0] + 1);
1744 }
1745 return ret;
1746}
1747
1748static int tdm_tx_ch_get(struct snd_kcontrol *kcontrol,
1749 struct snd_ctl_elem_value *ucontrol)
1750{
1751 struct tdm_port port;
1752 int ret = tdm_get_port_idx(kcontrol, &port);
1753
1754 if (ret) {
1755 pr_err("%s: unsupported control: %s\n",
1756 __func__, kcontrol->id.name);
1757 } else {
1758 ucontrol->value.enumerated.item[0] =
1759 tdm_tx_cfg[port.mode][port.channel].channels - 1;
1760
1761 pr_debug("%s: tdm_tx_ch = %d, item = %d\n", __func__,
1762 tdm_tx_cfg[port.mode][port.channel].channels - 1,
1763 ucontrol->value.enumerated.item[0]);
1764 }
1765 return ret;
1766}
1767
1768static int tdm_tx_ch_put(struct snd_kcontrol *kcontrol,
1769 struct snd_ctl_elem_value *ucontrol)
1770{
1771 struct tdm_port port;
1772 int ret = tdm_get_port_idx(kcontrol, &port);
1773
1774 if (ret) {
1775 pr_err("%s: unsupported control: %s\n",
1776 __func__, kcontrol->id.name);
1777 } else {
1778 tdm_tx_cfg[port.mode][port.channel].channels =
1779 ucontrol->value.enumerated.item[0] + 1;
1780
1781 pr_debug("%s: tdm_tx_ch = %d, item = %d\n", __func__,
1782 tdm_tx_cfg[port.mode][port.channel].channels,
1783 ucontrol->value.enumerated.item[0] + 1);
1784 }
1785 return ret;
1786}
1787
1788static int tdm_get_slot_num_val(int slot_num)
1789{
1790 int slot_num_val = 0;
1791
1792 switch (slot_num) {
1793 case 1:
1794 slot_num_val = 0;
1795 break;
1796 case 2:
1797 slot_num_val = 1;
1798 break;
1799 case 4:
1800 slot_num_val = 2;
1801 break;
1802 case 8:
1803 slot_num_val = 3;
1804 break;
1805 case 16:
1806 slot_num_val = 4;
1807 break;
1808 case 32:
1809 slot_num_val = 5;
1810 break;
1811 default:
1812 slot_num_val = 5;
1813 break;
1814 }
1815 return slot_num_val;
1816}
1817
1818static int tdm_slot_num_get(struct snd_kcontrol *kcontrol,
1819 struct snd_ctl_elem_value *ucontrol)
1820{
1821 int mode = tdm_get_mode(kcontrol);
1822
1823 if (mode < 0) {
1824 pr_err("%s: unsupported control: %s\n",
1825 __func__, kcontrol->id.name);
1826 return mode;
1827 }
1828
1829 ucontrol->value.enumerated.item[0] =
1830 tdm_get_slot_num_val(tdm_slot[mode].num);
1831
1832 pr_debug("%s: mode = %d, tdm_slot_num = %d, item = %d\n", __func__,
1833 mode, tdm_slot[mode].num,
1834 ucontrol->value.enumerated.item[0]);
1835
1836 return 0;
1837}
1838
1839static int tdm_get_slot_num(int value)
1840{
1841 int slot_num = 0;
1842
1843 switch (value) {
1844 case 0:
1845 slot_num = 1;
1846 break;
1847 case 1:
1848 slot_num = 2;
1849 break;
1850 case 2:
1851 slot_num = 4;
1852 break;
1853 case 3:
1854 slot_num = 8;
1855 break;
1856 case 4:
1857 slot_num = 16;
1858 break;
1859 case 5:
1860 slot_num = 32;
1861 break;
1862 default:
1863 slot_num = 8;
1864 break;
1865 }
1866 return slot_num;
1867}
1868
1869static int tdm_slot_num_put(struct snd_kcontrol *kcontrol,
1870 struct snd_ctl_elem_value *ucontrol)
1871{
1872 int mode = tdm_get_mode(kcontrol);
1873
1874 if (mode < 0) {
1875 pr_err("%s: unsupported control: %s\n",
1876 __func__, kcontrol->id.name);
1877 return mode;
1878 }
1879
1880 tdm_slot[mode].num =
1881 tdm_get_slot_num(ucontrol->value.enumerated.item[0]);
1882
1883 pr_debug("%s: mode = %d, tdm_slot_num = %d, item = %d\n", __func__,
1884 mode, tdm_slot[mode].num,
1885 ucontrol->value.enumerated.item[0]);
1886
1887 return 0;
1888}
1889
1890static int tdm_get_slot_width_val(int slot_width)
1891{
1892 int slot_width_val = 2;
1893
1894 switch (slot_width) {
1895 case 16:
1896 slot_width_val = 0;
1897 break;
1898 case 24:
1899 slot_width_val = 1;
1900 break;
1901 case 32:
1902 slot_width_val = 2;
1903 break;
1904 default:
1905 slot_width_val = 2;
1906 break;
1907 }
1908 return slot_width_val;
1909}
1910
1911static int tdm_slot_width_get(struct snd_kcontrol *kcontrol,
1912 struct snd_ctl_elem_value *ucontrol)
1913{
1914 int mode = tdm_get_mode(kcontrol);
1915
1916 if (mode < 0) {
1917 pr_err("%s: unsupported control: %s\n",
1918 __func__, kcontrol->id.name);
1919 return mode;
1920 }
1921
1922 ucontrol->value.enumerated.item[0] =
1923 tdm_get_slot_width_val(tdm_slot[mode].width);
1924
1925 pr_debug("%s: mode = %d, tdm_slot_width = %d, item = %d\n", __func__,
1926 mode, tdm_slot[mode].width,
1927 ucontrol->value.enumerated.item[0]);
1928
1929 return 0;
1930}
1931
1932static int tdm_get_slot_width(int value)
1933{
1934 int slot_width = 32;
1935
1936 switch (value) {
1937 case 0:
1938 slot_width = 16;
1939 break;
1940 case 1:
1941 slot_width = 24;
1942 break;
1943 case 2:
1944 slot_width = 32;
1945 break;
1946 default:
1947 slot_width = 32;
1948 break;
1949 }
1950 return slot_width;
1951}
1952
1953static int tdm_slot_width_put(struct snd_kcontrol *kcontrol,
1954 struct snd_ctl_elem_value *ucontrol)
1955{
1956 int mode = tdm_get_mode(kcontrol);
1957
1958 if (mode < 0) {
1959 pr_err("%s: unsupported control: %s\n",
1960 __func__, kcontrol->id.name);
1961 return mode;
1962 }
1963
1964 tdm_slot[mode].width =
1965 tdm_get_slot_width(ucontrol->value.enumerated.item[0]);
1966
1967 pr_debug("%s: mode = %d, tdm_slot_width = %d, item = %d\n", __func__,
1968 mode, tdm_slot[mode].width,
1969 ucontrol->value.enumerated.item[0]);
1970
1971 return 0;
1972}
1973
1974static int tdm_rx_slot_mapping_get(struct snd_kcontrol *kcontrol,
1975 struct snd_ctl_elem_value *ucontrol)
1976{
1977 unsigned int *slot_offset;
1978 int i;
1979 struct tdm_port port;
1980 int ret = tdm_get_port_idx(kcontrol, &port);
1981
1982 if (ret) {
1983 pr_err("%s: unsupported control: %s\n",
1984 __func__, kcontrol->id.name);
1985 } else {
1986 slot_offset = tdm_rx_slot_offset[port.mode][port.channel];
1987 pr_debug("%s: mode = %d, channel = %d\n",
1988 __func__, port.mode, port.channel);
1989 for (i = 0; i < TDM_SLOT_OFFSET_MAX; i++) {
1990 ucontrol->value.integer.value[i] = slot_offset[i];
1991 pr_debug("%s: offset %d, value %d\n",
1992 __func__, i, slot_offset[i]);
1993 }
1994 }
1995 return ret;
1996}
1997
1998static int tdm_rx_slot_mapping_put(struct snd_kcontrol *kcontrol,
1999 struct snd_ctl_elem_value *ucontrol)
2000{
2001 unsigned int *slot_offset;
2002 int i;
2003 struct tdm_port port;
2004 int ret = tdm_get_port_idx(kcontrol, &port);
2005
2006 if (ret) {
2007 pr_err("%s: unsupported control: %s\n",
2008 __func__, kcontrol->id.name);
2009 } else {
2010 slot_offset = tdm_rx_slot_offset[port.mode][port.channel];
2011 pr_debug("%s: mode = %d, channel = %d\n",
2012 __func__, port.mode, port.channel);
2013 for (i = 0; i < TDM_SLOT_OFFSET_MAX; i++) {
2014 slot_offset[i] = ucontrol->value.integer.value[i];
2015 pr_debug("%s: offset %d, value %d\n",
2016 __func__, i, slot_offset[i]);
2017 }
2018 }
2019 return ret;
2020}
2021
2022static int tdm_tx_slot_mapping_get(struct snd_kcontrol *kcontrol,
2023 struct snd_ctl_elem_value *ucontrol)
2024{
2025 unsigned int *slot_offset;
2026 int i;
2027 struct tdm_port port;
2028 int ret = tdm_get_port_idx(kcontrol, &port);
2029
2030 if (ret) {
2031 pr_err("%s: unsupported control: %s\n",
2032 __func__, kcontrol->id.name);
2033 } else {
2034 slot_offset = tdm_tx_slot_offset[port.mode][port.channel];
2035 pr_debug("%s: mode = %d, channel = %d\n",
2036 __func__, port.mode, port.channel);
2037 for (i = 0; i < TDM_SLOT_OFFSET_MAX; i++) {
2038 ucontrol->value.integer.value[i] = slot_offset[i];
2039 pr_debug("%s: offset %d, value %d\n",
2040 __func__, i, slot_offset[i]);
2041 }
2042 }
2043 return ret;
2044}
2045
2046static int tdm_tx_slot_mapping_put(struct snd_kcontrol *kcontrol,
2047 struct snd_ctl_elem_value *ucontrol)
2048{
2049 unsigned int *slot_offset;
2050 int i;
2051 struct tdm_port port;
2052 int ret = tdm_get_port_idx(kcontrol, &port);
2053
2054 if (ret) {
2055 pr_err("%s: unsupported control: %s\n",
2056 __func__, kcontrol->id.name);
2057 } else {
2058 slot_offset = tdm_tx_slot_offset[port.mode][port.channel];
2059 pr_debug("%s: mode = %d, channel = %d\n",
2060 __func__, port.mode, port.channel);
2061 for (i = 0; i < TDM_SLOT_OFFSET_MAX; i++) {
2062 slot_offset[i] = ucontrol->value.integer.value[i];
2063 pr_debug("%s: offset %d, value %d\n",
2064 __func__, i, slot_offset[i]);
2065 }
2066 }
2067 return ret;
2068}
2069
2070static int aux_pcm_get_port_idx(struct snd_kcontrol *kcontrol)
2071{
2072 int idx;
2073
2074 if (strnstr(kcontrol->id.name, "PRIM_AUX_PCM",
2075 sizeof("PRIM_AUX_PCM")))
2076 idx = PRIM_AUX_PCM;
2077 else if (strnstr(kcontrol->id.name, "SEC_AUX_PCM",
2078 sizeof("SEC_AUX_PCM")))
2079 idx = SEC_AUX_PCM;
2080 else if (strnstr(kcontrol->id.name, "TERT_AUX_PCM",
2081 sizeof("TERT_AUX_PCM")))
2082 idx = TERT_AUX_PCM;
2083 else if (strnstr(kcontrol->id.name, "QUAT_AUX_PCM",
2084 sizeof("QUAT_AUX_PCM")))
2085 idx = QUAT_AUX_PCM;
2086 else if (strnstr(kcontrol->id.name, "QUIN_AUX_PCM",
2087 sizeof("QUIN_AUX_PCM")))
2088 idx = QUIN_AUX_PCM;
2089 else {
2090 pr_err("%s: unsupported port: %s\n",
2091 __func__, kcontrol->id.name);
2092 idx = -EINVAL;
2093 }
2094
2095 return idx;
2096}
2097
2098static int aux_pcm_rx_sample_rate_put(struct snd_kcontrol *kcontrol,
2099 struct snd_ctl_elem_value *ucontrol)
2100{
2101 int idx = aux_pcm_get_port_idx(kcontrol);
2102
2103 if (idx < 0)
2104 return idx;
2105
2106 aux_pcm_rx_cfg[idx].sample_rate =
2107 aux_pcm_get_sample_rate(ucontrol->value.enumerated.item[0]);
2108
2109 pr_debug("%s: idx[%d]_rx_sample_rate = %d, item = %d\n", __func__,
2110 idx, aux_pcm_rx_cfg[idx].sample_rate,
2111 ucontrol->value.enumerated.item[0]);
2112
2113 return 0;
2114}
2115
2116static int aux_pcm_rx_sample_rate_get(struct snd_kcontrol *kcontrol,
2117 struct snd_ctl_elem_value *ucontrol)
2118{
2119 int idx = aux_pcm_get_port_idx(kcontrol);
2120
2121 if (idx < 0)
2122 return idx;
2123
2124 ucontrol->value.enumerated.item[0] =
2125 aux_pcm_get_sample_rate_val(aux_pcm_rx_cfg[idx].sample_rate);
2126
2127 pr_debug("%s: idx[%d]_rx_sample_rate = %d, item = %d\n", __func__,
2128 idx, aux_pcm_rx_cfg[idx].sample_rate,
2129 ucontrol->value.enumerated.item[0]);
2130
2131 return 0;
2132}
2133
2134static int aux_pcm_tx_sample_rate_put(struct snd_kcontrol *kcontrol,
2135 struct snd_ctl_elem_value *ucontrol)
2136{
2137 int idx = aux_pcm_get_port_idx(kcontrol);
2138
2139 if (idx < 0)
2140 return idx;
2141
2142 aux_pcm_tx_cfg[idx].sample_rate =
2143 aux_pcm_get_sample_rate(ucontrol->value.enumerated.item[0]);
2144
2145 pr_debug("%s: idx[%d]_tx_sample_rate = %d, item = %d\n", __func__,
2146 idx, aux_pcm_tx_cfg[idx].sample_rate,
2147 ucontrol->value.enumerated.item[0]);
2148
2149 return 0;
2150}
2151
2152static int aux_pcm_tx_sample_rate_get(struct snd_kcontrol *kcontrol,
2153 struct snd_ctl_elem_value *ucontrol)
2154{
2155 int idx = aux_pcm_get_port_idx(kcontrol);
2156
2157 if (idx < 0)
2158 return idx;
2159
2160 ucontrol->value.enumerated.item[0] =
2161 aux_pcm_get_sample_rate_val(aux_pcm_tx_cfg[idx].sample_rate);
2162
2163 pr_debug("%s: idx[%d]_tx_sample_rate = %d, item = %d\n", __func__,
2164 idx, aux_pcm_tx_cfg[idx].sample_rate,
2165 ucontrol->value.enumerated.item[0]);
2166
2167 return 0;
2168}
2169
2170static int mi2s_get_port_idx(struct snd_kcontrol *kcontrol)
2171{
2172 int idx;
2173
2174 if (strnstr(kcontrol->id.name, "PRIM_MI2S_RX",
2175 sizeof("PRIM_MI2S_RX")))
2176 idx = PRIM_MI2S;
2177 else if (strnstr(kcontrol->id.name, "SEC_MI2S_RX",
2178 sizeof("SEC_MI2S_RX")))
2179 idx = SEC_MI2S;
2180 else if (strnstr(kcontrol->id.name, "TERT_MI2S_RX",
2181 sizeof("TERT_MI2S_RX")))
2182 idx = TERT_MI2S;
2183 else if (strnstr(kcontrol->id.name, "QUAT_MI2S_RX",
2184 sizeof("QUAT_MI2S_RX")))
2185 idx = QUAT_MI2S;
2186 else if (strnstr(kcontrol->id.name, "QUIN_MI2S_RX",
2187 sizeof("QUIN_MI2S_RX")))
2188 idx = QUIN_MI2S;
2189 else if (strnstr(kcontrol->id.name, "PRIM_MI2S_TX",
2190 sizeof("PRIM_MI2S_TX")))
2191 idx = PRIM_MI2S;
2192 else if (strnstr(kcontrol->id.name, "SEC_MI2S_TX",
2193 sizeof("SEC_MI2S_TX")))
2194 idx = SEC_MI2S;
2195 else if (strnstr(kcontrol->id.name, "TERT_MI2S_TX",
2196 sizeof("TERT_MI2S_TX")))
2197 idx = TERT_MI2S;
2198 else if (strnstr(kcontrol->id.name, "QUAT_MI2S_TX",
2199 sizeof("QUAT_MI2S_TX")))
2200 idx = QUAT_MI2S;
2201 else if (strnstr(kcontrol->id.name, "QUIN_MI2S_TX",
2202 sizeof("QUIN_MI2S_TX")))
2203 idx = QUIN_MI2S;
2204 else {
2205 pr_err("%s: unsupported channel: %s\n",
2206 __func__, kcontrol->id.name);
2207 idx = -EINVAL;
2208 }
2209
2210 return idx;
2211}
2212
2213static int mi2s_get_sample_rate_val(int sample_rate)
2214{
2215 int sample_rate_val;
2216
2217 switch (sample_rate) {
2218 case SAMPLING_RATE_8KHZ:
2219 sample_rate_val = 0;
2220 break;
2221 case SAMPLING_RATE_11P025KHZ:
2222 sample_rate_val = 1;
2223 break;
2224 case SAMPLING_RATE_16KHZ:
2225 sample_rate_val = 2;
2226 break;
2227 case SAMPLING_RATE_22P05KHZ:
2228 sample_rate_val = 3;
2229 break;
2230 case SAMPLING_RATE_32KHZ:
2231 sample_rate_val = 4;
2232 break;
2233 case SAMPLING_RATE_44P1KHZ:
2234 sample_rate_val = 5;
2235 break;
2236 case SAMPLING_RATE_48KHZ:
2237 sample_rate_val = 6;
2238 break;
2239 case SAMPLING_RATE_96KHZ:
2240 sample_rate_val = 7;
2241 break;
2242 case SAMPLING_RATE_192KHZ:
2243 sample_rate_val = 8;
2244 break;
2245 default:
2246 sample_rate_val = 6;
2247 break;
2248 }
2249 return sample_rate_val;
2250}
2251
2252static int mi2s_get_sample_rate(int value)
2253{
2254 int sample_rate;
2255
2256 switch (value) {
2257 case 0:
2258 sample_rate = SAMPLING_RATE_8KHZ;
2259 break;
2260 case 1:
2261 sample_rate = SAMPLING_RATE_11P025KHZ;
2262 break;
2263 case 2:
2264 sample_rate = SAMPLING_RATE_16KHZ;
2265 break;
2266 case 3:
2267 sample_rate = SAMPLING_RATE_22P05KHZ;
2268 break;
2269 case 4:
2270 sample_rate = SAMPLING_RATE_32KHZ;
2271 break;
2272 case 5:
2273 sample_rate = SAMPLING_RATE_44P1KHZ;
2274 break;
2275 case 6:
2276 sample_rate = SAMPLING_RATE_48KHZ;
2277 break;
2278 case 7:
2279 sample_rate = SAMPLING_RATE_96KHZ;
2280 break;
2281 case 8:
2282 sample_rate = SAMPLING_RATE_192KHZ;
2283 break;
2284 default:
2285 sample_rate = SAMPLING_RATE_48KHZ;
2286 break;
2287 }
2288 return sample_rate;
2289}
2290
2291static int mi2s_auxpcm_get_format(int value)
2292{
2293 int format;
2294
2295 switch (value) {
2296 case 0:
2297 format = SNDRV_PCM_FORMAT_S16_LE;
2298 break;
2299 case 1:
2300 format = SNDRV_PCM_FORMAT_S24_LE;
2301 break;
2302 case 2:
2303 format = SNDRV_PCM_FORMAT_S24_3LE;
2304 break;
2305 case 3:
2306 format = SNDRV_PCM_FORMAT_S32_LE;
2307 break;
2308 default:
2309 format = SNDRV_PCM_FORMAT_S16_LE;
2310 break;
2311 }
2312 return format;
2313}
2314
2315static int mi2s_auxpcm_get_format_value(int format)
2316{
2317 int value;
2318
2319 switch (format) {
2320 case SNDRV_PCM_FORMAT_S16_LE:
2321 value = 0;
2322 break;
2323 case SNDRV_PCM_FORMAT_S24_LE:
2324 value = 1;
2325 break;
2326 case SNDRV_PCM_FORMAT_S24_3LE:
2327 value = 2;
2328 break;
2329 case SNDRV_PCM_FORMAT_S32_LE:
2330 value = 3;
2331 break;
2332 default:
2333 value = 0;
2334 break;
2335 }
2336 return value;
2337}
2338
2339static int mi2s_rx_sample_rate_put(struct snd_kcontrol *kcontrol,
2340 struct snd_ctl_elem_value *ucontrol)
2341{
2342 int idx = mi2s_get_port_idx(kcontrol);
2343
2344 if (idx < 0)
2345 return idx;
2346
2347 mi2s_rx_cfg[idx].sample_rate =
2348 mi2s_get_sample_rate(ucontrol->value.enumerated.item[0]);
2349
2350 pr_debug("%s: idx[%d]_rx_sample_rate = %d, item = %d\n", __func__,
2351 idx, mi2s_rx_cfg[idx].sample_rate,
2352 ucontrol->value.enumerated.item[0]);
2353
2354 return 0;
2355}
2356
2357static int mi2s_rx_sample_rate_get(struct snd_kcontrol *kcontrol,
2358 struct snd_ctl_elem_value *ucontrol)
2359{
2360 int idx = mi2s_get_port_idx(kcontrol);
2361
2362 if (idx < 0)
2363 return idx;
2364
2365 ucontrol->value.enumerated.item[0] =
2366 mi2s_get_sample_rate_val(mi2s_rx_cfg[idx].sample_rate);
2367
2368 pr_debug("%s: idx[%d]_rx_sample_rate = %d, item = %d\n", __func__,
2369 idx, mi2s_rx_cfg[idx].sample_rate,
2370 ucontrol->value.enumerated.item[0]);
2371
2372 return 0;
2373}
2374
2375static int mi2s_tx_sample_rate_put(struct snd_kcontrol *kcontrol,
2376 struct snd_ctl_elem_value *ucontrol)
2377{
2378 int idx = mi2s_get_port_idx(kcontrol);
2379
2380 if (idx < 0)
2381 return idx;
2382
2383 mi2s_tx_cfg[idx].sample_rate =
2384 mi2s_get_sample_rate(ucontrol->value.enumerated.item[0]);
2385
2386 pr_debug("%s: idx[%d]_tx_sample_rate = %d, item = %d\n", __func__,
2387 idx, mi2s_tx_cfg[idx].sample_rate,
2388 ucontrol->value.enumerated.item[0]);
2389
2390 return 0;
2391}
2392
2393static int mi2s_tx_sample_rate_get(struct snd_kcontrol *kcontrol,
2394 struct snd_ctl_elem_value *ucontrol)
2395{
2396 int idx = mi2s_get_port_idx(kcontrol);
2397
2398 if (idx < 0)
2399 return idx;
2400
2401 ucontrol->value.enumerated.item[0] =
2402 mi2s_get_sample_rate_val(mi2s_tx_cfg[idx].sample_rate);
2403
2404 pr_debug("%s: idx[%d]_tx_sample_rate = %d, item = %d\n", __func__,
2405 idx, mi2s_tx_cfg[idx].sample_rate,
2406 ucontrol->value.enumerated.item[0]);
2407
2408 return 0;
2409}
2410
2411static int msm_mi2s_rx_ch_get(struct snd_kcontrol *kcontrol,
2412 struct snd_ctl_elem_value *ucontrol)
2413{
2414 int idx = mi2s_get_port_idx(kcontrol);
2415
2416 if (idx < 0)
2417 return idx;
2418
2419 pr_debug("%s: msm_mi2s_[%d]_rx_ch = %d\n", __func__,
2420 idx, mi2s_rx_cfg[idx].channels);
2421 ucontrol->value.enumerated.item[0] = mi2s_rx_cfg[idx].channels - 1;
2422
2423 return 0;
2424}
2425
2426static int msm_mi2s_rx_ch_put(struct snd_kcontrol *kcontrol,
2427 struct snd_ctl_elem_value *ucontrol)
2428{
2429 int idx = mi2s_get_port_idx(kcontrol);
2430
2431 if (idx < 0)
2432 return idx;
2433
2434 mi2s_rx_cfg[idx].channels = ucontrol->value.enumerated.item[0] + 1;
2435 pr_debug("%s: msm_mi2s_[%d]_rx_ch = %d\n", __func__,
2436 idx, mi2s_rx_cfg[idx].channels);
2437
2438 return 1;
2439}
2440
2441static int msm_mi2s_tx_ch_get(struct snd_kcontrol *kcontrol,
2442 struct snd_ctl_elem_value *ucontrol)
2443{
2444 int idx = mi2s_get_port_idx(kcontrol);
2445
2446 if (idx < 0)
2447 return idx;
2448
2449 pr_debug("%s: msm_mi2s_[%d]_tx_ch = %d\n", __func__,
2450 idx, mi2s_tx_cfg[idx].channels);
2451 ucontrol->value.enumerated.item[0] = mi2s_tx_cfg[idx].channels - 1;
2452
2453 return 0;
2454}
2455
2456static int msm_mi2s_tx_ch_put(struct snd_kcontrol *kcontrol,
2457 struct snd_ctl_elem_value *ucontrol)
2458{
2459 int idx = mi2s_get_port_idx(kcontrol);
2460
2461 if (idx < 0)
2462 return idx;
2463
2464 mi2s_tx_cfg[idx].channels = ucontrol->value.enumerated.item[0] + 1;
2465 pr_debug("%s: msm_mi2s_[%d]_tx_ch = %d\n", __func__,
2466 idx, mi2s_tx_cfg[idx].channels);
2467
2468 return 1;
2469}
2470
2471static int msm_mi2s_rx_format_get(struct snd_kcontrol *kcontrol,
2472 struct snd_ctl_elem_value *ucontrol)
2473{
2474 int idx = mi2s_get_port_idx(kcontrol);
2475
2476 if (idx < 0)
2477 return idx;
2478
2479 ucontrol->value.enumerated.item[0] =
2480 mi2s_auxpcm_get_format_value(mi2s_rx_cfg[idx].bit_format);
2481
2482 pr_debug("%s: idx[%d]_rx_format = %d, item = %d\n", __func__,
2483 idx, mi2s_rx_cfg[idx].bit_format,
2484 ucontrol->value.enumerated.item[0]);
2485
2486 return 0;
2487}
2488
2489static int msm_mi2s_rx_format_put(struct snd_kcontrol *kcontrol,
2490 struct snd_ctl_elem_value *ucontrol)
2491{
2492 int idx = mi2s_get_port_idx(kcontrol);
2493
2494 if (idx < 0)
2495 return idx;
2496
2497 mi2s_rx_cfg[idx].bit_format =
2498 mi2s_auxpcm_get_format(ucontrol->value.enumerated.item[0]);
2499
2500 pr_debug("%s: idx[%d]_rx_format = %d, item = %d\n", __func__,
2501 idx, mi2s_rx_cfg[idx].bit_format,
2502 ucontrol->value.enumerated.item[0]);
2503
2504 return 0;
2505}
2506
2507static int msm_mi2s_tx_format_get(struct snd_kcontrol *kcontrol,
2508 struct snd_ctl_elem_value *ucontrol)
2509{
2510 int idx = mi2s_get_port_idx(kcontrol);
2511
2512 if (idx < 0)
2513 return idx;
2514
2515 ucontrol->value.enumerated.item[0] =
2516 mi2s_auxpcm_get_format_value(mi2s_tx_cfg[idx].bit_format);
2517
2518 pr_debug("%s: idx[%d]_tx_format = %d, item = %d\n", __func__,
2519 idx, mi2s_tx_cfg[idx].bit_format,
2520 ucontrol->value.enumerated.item[0]);
2521
2522 return 0;
2523}
2524
2525static int msm_mi2s_tx_format_put(struct snd_kcontrol *kcontrol,
2526 struct snd_ctl_elem_value *ucontrol)
2527{
2528 int idx = mi2s_get_port_idx(kcontrol);
2529
2530 if (idx < 0)
2531 return idx;
2532
2533 mi2s_tx_cfg[idx].bit_format =
2534 mi2s_auxpcm_get_format(ucontrol->value.enumerated.item[0]);
2535
2536 pr_debug("%s: idx[%d]_tx_format = %d, item = %d\n", __func__,
2537 idx, mi2s_tx_cfg[idx].bit_format,
2538 ucontrol->value.enumerated.item[0]);
2539
2540 return 0;
2541}
2542
2543static int msm_aux_pcm_rx_format_get(struct snd_kcontrol *kcontrol,
2544 struct snd_ctl_elem_value *ucontrol)
2545{
2546 int idx = aux_pcm_get_port_idx(kcontrol);
2547
2548 if (idx < 0)
2549 return idx;
2550
2551 ucontrol->value.enumerated.item[0] =
2552 mi2s_auxpcm_get_format_value(aux_pcm_rx_cfg[idx].bit_format);
2553
2554 pr_debug("%s: idx[%d]_rx_format = %d, item = %d\n", __func__,
2555 idx, aux_pcm_rx_cfg[idx].bit_format,
2556 ucontrol->value.enumerated.item[0]);
2557
2558 return 0;
2559}
2560
2561static int msm_aux_pcm_rx_format_put(struct snd_kcontrol *kcontrol,
2562 struct snd_ctl_elem_value *ucontrol)
2563{
2564 int idx = aux_pcm_get_port_idx(kcontrol);
2565
2566 if (idx < 0)
2567 return idx;
2568
2569 aux_pcm_rx_cfg[idx].bit_format =
2570 mi2s_auxpcm_get_format(ucontrol->value.enumerated.item[0]);
2571
2572 pr_debug("%s: idx[%d]_rx_format = %d, item = %d\n", __func__,
2573 idx, aux_pcm_rx_cfg[idx].bit_format,
2574 ucontrol->value.enumerated.item[0]);
2575
2576 return 0;
2577}
2578
2579static int msm_aux_pcm_tx_format_get(struct snd_kcontrol *kcontrol,
2580 struct snd_ctl_elem_value *ucontrol)
2581{
2582 int idx = aux_pcm_get_port_idx(kcontrol);
2583
2584 if (idx < 0)
2585 return idx;
2586
2587 ucontrol->value.enumerated.item[0] =
2588 mi2s_auxpcm_get_format_value(aux_pcm_tx_cfg[idx].bit_format);
2589
2590 pr_debug("%s: idx[%d]_tx_format = %d, item = %d\n", __func__,
2591 idx, aux_pcm_tx_cfg[idx].bit_format,
2592 ucontrol->value.enumerated.item[0]);
2593
2594 return 0;
2595}
2596
2597static int msm_aux_pcm_tx_format_put(struct snd_kcontrol *kcontrol,
2598 struct snd_ctl_elem_value *ucontrol)
2599{
2600 int idx = aux_pcm_get_port_idx(kcontrol);
2601
2602 if (idx < 0)
2603 return idx;
2604
2605 aux_pcm_tx_cfg[idx].bit_format =
2606 mi2s_auxpcm_get_format(ucontrol->value.enumerated.item[0]);
2607
2608 pr_debug("%s: idx[%d]_tx_format = %d, item = %d\n", __func__,
2609 idx, aux_pcm_tx_cfg[idx].bit_format,
2610 ucontrol->value.enumerated.item[0]);
2611
2612 return 0;
2613}
2614
2615static const struct snd_kcontrol_new msm_snd_controls[] = {
2616 SOC_ENUM_EXT("USB_AUDIO_RX Channels", usb_rx_chs,
2617 usb_audio_rx_ch_get, usb_audio_rx_ch_put),
2618 SOC_ENUM_EXT("USB_AUDIO_TX Channels", usb_tx_chs,
2619 usb_audio_tx_ch_get, usb_audio_tx_ch_put),
2620 SOC_ENUM_EXT("Display Port RX Channels", ext_disp_rx_chs,
2621 ext_disp_rx_ch_get, ext_disp_rx_ch_put),
2622 SOC_ENUM_EXT("PROXY_RX Channels", proxy_rx_chs,
2623 proxy_rx_ch_get, proxy_rx_ch_put),
2624 SOC_ENUM_EXT("USB_AUDIO_RX Format", usb_rx_format,
2625 usb_audio_rx_format_get, usb_audio_rx_format_put),
2626 SOC_ENUM_EXT("USB_AUDIO_TX Format", usb_tx_format,
2627 usb_audio_tx_format_get, usb_audio_tx_format_put),
2628 SOC_ENUM_EXT("Display Port RX Bit Format", ext_disp_rx_format,
2629 ext_disp_rx_format_get, ext_disp_rx_format_put),
2630 SOC_ENUM_EXT("USB_AUDIO_RX SampleRate", usb_rx_sample_rate,
2631 usb_audio_rx_sample_rate_get,
2632 usb_audio_rx_sample_rate_put),
2633 SOC_ENUM_EXT("USB_AUDIO_TX SampleRate", usb_tx_sample_rate,
2634 usb_audio_tx_sample_rate_get,
2635 usb_audio_tx_sample_rate_put),
2636 SOC_ENUM_EXT("Display Port RX SampleRate", ext_disp_rx_sample_rate,
2637 ext_disp_rx_sample_rate_get,
2638 ext_disp_rx_sample_rate_put),
2639 SOC_ENUM_EXT("PRI_TDM_RX_0 SampleRate", tdm_rx_sample_rate,
2640 tdm_rx_sample_rate_get,
2641 tdm_rx_sample_rate_put),
2642 SOC_ENUM_EXT("PRI_TDM_RX_1 SampleRate", tdm_rx_sample_rate,
2643 tdm_rx_sample_rate_get,
2644 tdm_rx_sample_rate_put),
2645 SOC_ENUM_EXT("PRI_TDM_RX_2 SampleRate", tdm_rx_sample_rate,
2646 tdm_rx_sample_rate_get,
2647 tdm_rx_sample_rate_put),
2648 SOC_ENUM_EXT("PRI_TDM_RX_3 SampleRate", tdm_rx_sample_rate,
2649 tdm_rx_sample_rate_get,
2650 tdm_rx_sample_rate_put),
2651 SOC_ENUM_EXT("PRI_TDM_TX_0 SampleRate", tdm_tx_sample_rate,
2652 tdm_tx_sample_rate_get,
2653 tdm_tx_sample_rate_put),
2654 SOC_ENUM_EXT("PRI_TDM_TX_1 SampleRate", tdm_tx_sample_rate,
2655 tdm_tx_sample_rate_get,
2656 tdm_tx_sample_rate_put),
2657 SOC_ENUM_EXT("PRI_TDM_TX_2 SampleRate", tdm_tx_sample_rate,
2658 tdm_tx_sample_rate_get,
2659 tdm_tx_sample_rate_put),
2660 SOC_ENUM_EXT("PRI_TDM_TX_3 SampleRate", tdm_tx_sample_rate,
2661 tdm_tx_sample_rate_get,
2662 tdm_tx_sample_rate_put),
2663 SOC_ENUM_EXT("PRI_TDM_RX_0 Format", tdm_rx_format,
2664 tdm_rx_format_get,
2665 tdm_rx_format_put),
2666 SOC_ENUM_EXT("PRI_TDM_RX_1 Format", tdm_rx_format,
2667 tdm_rx_format_get,
2668 tdm_rx_format_put),
2669 SOC_ENUM_EXT("PRI_TDM_RX_2 Format", tdm_rx_format,
2670 tdm_rx_format_get,
2671 tdm_rx_format_put),
2672 SOC_ENUM_EXT("PRI_TDM_RX_3 Format", tdm_rx_format,
2673 tdm_rx_format_get,
2674 tdm_rx_format_put),
2675 SOC_ENUM_EXT("PRI_TDM_TX_0 Format", tdm_tx_format,
2676 tdm_tx_format_get,
2677 tdm_tx_format_put),
2678 SOC_ENUM_EXT("PRI_TDM_TX_1 Format", tdm_tx_format,
2679 tdm_tx_format_get,
2680 tdm_tx_format_put),
2681 SOC_ENUM_EXT("PRI_TDM_TX_2 Format", tdm_tx_format,
2682 tdm_tx_format_get,
2683 tdm_tx_format_put),
2684 SOC_ENUM_EXT("PRI_TDM_TX_3 Format", tdm_tx_format,
2685 tdm_tx_format_get,
2686 tdm_tx_format_put),
2687 SOC_ENUM_EXT("PRI_TDM_RX_0 Channels", tdm_rx_chs,
2688 tdm_rx_ch_get,
2689 tdm_rx_ch_put),
2690 SOC_ENUM_EXT("PRI_TDM_RX_1 Channels", tdm_rx_chs,
2691 tdm_rx_ch_get,
2692 tdm_rx_ch_put),
2693 SOC_ENUM_EXT("PRI_TDM_RX_2 Channels", tdm_rx_chs,
2694 tdm_rx_ch_get,
2695 tdm_rx_ch_put),
2696 SOC_ENUM_EXT("PRI_TDM_RX_3 Channels", tdm_rx_chs,
2697 tdm_rx_ch_get,
2698 tdm_rx_ch_put),
2699 SOC_ENUM_EXT("PRI_TDM_TX_0 Channels", tdm_tx_chs,
2700 tdm_tx_ch_get,
2701 tdm_tx_ch_put),
2702 SOC_ENUM_EXT("PRI_TDM_TX_1 Channels", tdm_tx_chs,
2703 tdm_tx_ch_get,
2704 tdm_tx_ch_put),
2705 SOC_ENUM_EXT("PRI_TDM_TX_2 Channels", tdm_tx_chs,
2706 tdm_tx_ch_get,
2707 tdm_tx_ch_put),
2708 SOC_ENUM_EXT("PRI_TDM_TX_3 Channels", tdm_tx_chs,
2709 tdm_tx_ch_get,
2710 tdm_tx_ch_put),
2711 SOC_ENUM_EXT("SEC_TDM_RX_0 SampleRate", tdm_rx_sample_rate,
2712 tdm_rx_sample_rate_get,
2713 tdm_rx_sample_rate_put),
2714 SOC_ENUM_EXT("SEC_TDM_RX_1 SampleRate", tdm_rx_sample_rate,
2715 tdm_rx_sample_rate_get,
2716 tdm_rx_sample_rate_put),
2717 SOC_ENUM_EXT("SEC_TDM_RX_2 SampleRate", tdm_rx_sample_rate,
2718 tdm_rx_sample_rate_get,
2719 tdm_rx_sample_rate_put),
2720 SOC_ENUM_EXT("SEC_TDM_RX_3 SampleRate", tdm_rx_sample_rate,
2721 tdm_rx_sample_rate_get,
2722 tdm_rx_sample_rate_put),
2723 SOC_ENUM_EXT("SEC_TDM_TX_0 SampleRate", tdm_tx_sample_rate,
2724 tdm_tx_sample_rate_get,
2725 tdm_tx_sample_rate_put),
2726 SOC_ENUM_EXT("SEC_TDM_TX_1 SampleRate", tdm_tx_sample_rate,
2727 tdm_tx_sample_rate_get,
2728 tdm_tx_sample_rate_put),
2729 SOC_ENUM_EXT("SEC_TDM_TX_2 SampleRate", tdm_tx_sample_rate,
2730 tdm_tx_sample_rate_get,
2731 tdm_tx_sample_rate_put),
2732 SOC_ENUM_EXT("SEC_TDM_TX_3 SampleRate", tdm_tx_sample_rate,
2733 tdm_tx_sample_rate_get,
2734 tdm_tx_sample_rate_put),
2735 SOC_ENUM_EXT("SEC_TDM_RX_0 Format", tdm_rx_format,
2736 tdm_rx_format_get,
2737 tdm_rx_format_put),
2738 SOC_ENUM_EXT("SEC_TDM_RX_1 Format", tdm_rx_format,
2739 tdm_rx_format_get,
2740 tdm_rx_format_put),
2741 SOC_ENUM_EXT("SEC_TDM_RX_2 Format", tdm_rx_format,
2742 tdm_rx_format_get,
2743 tdm_rx_format_put),
2744 SOC_ENUM_EXT("SEC_TDM_RX_3 Format", tdm_rx_format,
2745 tdm_rx_format_get,
2746 tdm_rx_format_put),
2747 SOC_ENUM_EXT("SEC_TDM_TX_0 Format", tdm_tx_format,
2748 tdm_tx_format_get,
2749 tdm_tx_format_put),
2750 SOC_ENUM_EXT("SEC_TDM_TX_1 Format", tdm_tx_format,
2751 tdm_tx_format_get,
2752 tdm_tx_format_put),
2753 SOC_ENUM_EXT("SEC_TDM_TX_2 Format", tdm_tx_format,
2754 tdm_tx_format_get,
2755 tdm_tx_format_put),
2756 SOC_ENUM_EXT("SEC_TDM_TX_3 Format", tdm_tx_format,
2757 tdm_tx_format_get,
2758 tdm_tx_format_put),
2759 SOC_ENUM_EXT("SEC_TDM_RX_0 Channels", tdm_rx_chs,
2760 tdm_rx_ch_get,
2761 tdm_rx_ch_put),
2762 SOC_ENUM_EXT("SEC_TDM_RX_1 Channels", tdm_rx_chs,
2763 tdm_rx_ch_get,
2764 tdm_rx_ch_put),
2765 SOC_ENUM_EXT("SEC_TDM_RX_2 Channels", tdm_rx_chs,
2766 tdm_rx_ch_get,
2767 tdm_rx_ch_put),
2768 SOC_ENUM_EXT("SEC_TDM_RX_3 Channels", tdm_rx_chs,
2769 tdm_rx_ch_get,
2770 tdm_rx_ch_put),
2771 SOC_ENUM_EXT("SEC_TDM_TX_0 Channels", tdm_tx_chs,
2772 tdm_tx_ch_get,
2773 tdm_tx_ch_put),
2774 SOC_ENUM_EXT("SEC_TDM_TX_1 Channels", tdm_tx_chs,
2775 tdm_tx_ch_get,
2776 tdm_tx_ch_put),
2777 SOC_ENUM_EXT("SEC_TDM_TX_2 Channels", tdm_tx_chs,
2778 tdm_tx_ch_get,
2779 tdm_tx_ch_put),
2780 SOC_ENUM_EXT("SEC_TDM_TX_3 Channels", tdm_tx_chs,
2781 tdm_tx_ch_get,
2782 tdm_tx_ch_put),
2783 SOC_ENUM_EXT("TERT_TDM_RX_0 SampleRate", tdm_rx_sample_rate,
2784 tdm_rx_sample_rate_get,
2785 tdm_rx_sample_rate_put),
2786 SOC_ENUM_EXT("TERT_TDM_RX_1 SampleRate", tdm_rx_sample_rate,
2787 tdm_rx_sample_rate_get,
2788 tdm_rx_sample_rate_put),
2789 SOC_ENUM_EXT("TERT_TDM_RX_2 SampleRate", tdm_rx_sample_rate,
2790 tdm_rx_sample_rate_get,
2791 tdm_rx_sample_rate_put),
2792 SOC_ENUM_EXT("TERT_TDM_RX_3 SampleRate", tdm_rx_sample_rate,
2793 tdm_rx_sample_rate_get,
2794 tdm_rx_sample_rate_put),
2795 SOC_ENUM_EXT("TERT_TDM_RX_4 SampleRate", tdm_rx_sample_rate,
2796 tdm_rx_sample_rate_get,
2797 tdm_rx_sample_rate_put),
2798 SOC_ENUM_EXT("TERT_TDM_TX_0 SampleRate", tdm_tx_sample_rate,
2799 tdm_tx_sample_rate_get,
2800 tdm_tx_sample_rate_put),
2801 SOC_ENUM_EXT("TERT_TDM_TX_1 SampleRate", tdm_tx_sample_rate,
2802 tdm_tx_sample_rate_get,
2803 tdm_tx_sample_rate_put),
2804 SOC_ENUM_EXT("TERT_TDM_TX_2 SampleRate", tdm_tx_sample_rate,
2805 tdm_tx_sample_rate_get,
2806 tdm_tx_sample_rate_put),
2807 SOC_ENUM_EXT("TERT_TDM_TX_3 SampleRate", tdm_tx_sample_rate,
2808 tdm_tx_sample_rate_get,
2809 tdm_tx_sample_rate_put),
2810 SOC_ENUM_EXT("TERT_TDM_RX_0 Format", tdm_rx_format,
2811 tdm_rx_format_get,
2812 tdm_rx_format_put),
2813 SOC_ENUM_EXT("TERT_TDM_RX_1 Format", tdm_rx_format,
2814 tdm_rx_format_get,
2815 tdm_rx_format_put),
2816 SOC_ENUM_EXT("TERT_TDM_RX_2 Format", tdm_rx_format,
2817 tdm_rx_format_get,
2818 tdm_rx_format_put),
2819 SOC_ENUM_EXT("TERT_TDM_RX_3 Format", tdm_rx_format,
2820 tdm_rx_format_get,
2821 tdm_rx_format_put),
2822 SOC_ENUM_EXT("TERT_TDM_RX_4 Format", tdm_rx_format,
2823 tdm_rx_format_get,
2824 tdm_rx_format_put),
2825 SOC_ENUM_EXT("TERT_TDM_TX_0 Format", tdm_tx_format,
2826 tdm_tx_format_get,
2827 tdm_tx_format_put),
2828 SOC_ENUM_EXT("TERT_TDM_TX_1 Format", tdm_tx_format,
2829 tdm_tx_format_get,
2830 tdm_tx_format_put),
2831 SOC_ENUM_EXT("TERT_TDM_TX_2 Format", tdm_tx_format,
2832 tdm_tx_format_get,
2833 tdm_tx_format_put),
2834 SOC_ENUM_EXT("TERT_TDM_TX_3 Format", tdm_tx_format,
2835 tdm_tx_format_get,
2836 tdm_tx_format_put),
2837 SOC_ENUM_EXT("TERT_TDM_RX_0 Channels", tdm_rx_chs,
2838 tdm_rx_ch_get,
2839 tdm_rx_ch_put),
2840 SOC_ENUM_EXT("TERT_TDM_RX_1 Channels", tdm_rx_chs,
2841 tdm_rx_ch_get,
2842 tdm_rx_ch_put),
2843 SOC_ENUM_EXT("TERT_TDM_RX_2 Channels", tdm_rx_chs,
2844 tdm_rx_ch_get,
2845 tdm_rx_ch_put),
2846 SOC_ENUM_EXT("TERT_TDM_RX_3 Channels", tdm_rx_chs,
2847 tdm_rx_ch_get,
2848 tdm_rx_ch_put),
2849 SOC_ENUM_EXT("TERT_TDM_RX_4 Channels", tdm_rx_chs,
2850 tdm_rx_ch_get,
2851 tdm_rx_ch_put),
2852 SOC_ENUM_EXT("TERT_TDM_TX_0 Channels", tdm_tx_chs,
2853 tdm_tx_ch_get,
2854 tdm_tx_ch_put),
2855 SOC_ENUM_EXT("TERT_TDM_TX_1 Channels", tdm_tx_chs,
2856 tdm_tx_ch_get,
2857 tdm_tx_ch_put),
2858 SOC_ENUM_EXT("TERT_TDM_TX_2 Channels", tdm_tx_chs,
2859 tdm_tx_ch_get,
2860 tdm_tx_ch_put),
2861 SOC_ENUM_EXT("TERT_TDM_TX_3 Channels", tdm_tx_chs,
2862 tdm_tx_ch_get,
2863 tdm_tx_ch_put),
2864 SOC_ENUM_EXT("QUAT_TDM_RX_0 SampleRate", tdm_rx_sample_rate,
2865 tdm_rx_sample_rate_get,
2866 tdm_rx_sample_rate_put),
2867 SOC_ENUM_EXT("QUAT_TDM_RX_1 SampleRate", tdm_rx_sample_rate,
2868 tdm_rx_sample_rate_get,
2869 tdm_rx_sample_rate_put),
2870 SOC_ENUM_EXT("QUAT_TDM_RX_2 SampleRate", tdm_rx_sample_rate,
2871 tdm_rx_sample_rate_get,
2872 tdm_rx_sample_rate_put),
2873 SOC_ENUM_EXT("QUAT_TDM_RX_3 SampleRate", tdm_rx_sample_rate,
2874 tdm_rx_sample_rate_get,
2875 tdm_rx_sample_rate_put),
2876 SOC_ENUM_EXT("QUAT_TDM_TX_0 SampleRate", tdm_tx_sample_rate,
2877 tdm_tx_sample_rate_get,
2878 tdm_tx_sample_rate_put),
2879 SOC_ENUM_EXT("QUAT_TDM_TX_1 SampleRate", tdm_tx_sample_rate,
2880 tdm_tx_sample_rate_get,
2881 tdm_tx_sample_rate_put),
2882 SOC_ENUM_EXT("QUAT_TDM_TX_2 SampleRate", tdm_tx_sample_rate,
2883 tdm_tx_sample_rate_get,
2884 tdm_tx_sample_rate_put),
2885 SOC_ENUM_EXT("QUAT_TDM_TX_3 SampleRate", tdm_tx_sample_rate,
2886 tdm_tx_sample_rate_get,
2887 tdm_tx_sample_rate_put),
2888 SOC_ENUM_EXT("QUAT_TDM_RX_0 Format", tdm_rx_format,
2889 tdm_rx_format_get,
2890 tdm_rx_format_put),
2891 SOC_ENUM_EXT("QUAT_TDM_RX_1 Format", tdm_rx_format,
2892 tdm_rx_format_get,
2893 tdm_rx_format_put),
2894 SOC_ENUM_EXT("QUAT_TDM_RX_2 Format", tdm_rx_format,
2895 tdm_rx_format_get,
2896 tdm_rx_format_put),
2897 SOC_ENUM_EXT("QUAT_TDM_RX_3 Format", tdm_rx_format,
2898 tdm_rx_format_get,
2899 tdm_rx_format_put),
2900 SOC_ENUM_EXT("QUAT_TDM_TX_0 Format", tdm_tx_format,
2901 tdm_tx_format_get,
2902 tdm_tx_format_put),
2903 SOC_ENUM_EXT("QUAT_TDM_TX_1 Format", tdm_tx_format,
2904 tdm_tx_format_get,
2905 tdm_tx_format_put),
2906 SOC_ENUM_EXT("QUAT_TDM_TX_2 Format", tdm_tx_format,
2907 tdm_tx_format_get,
2908 tdm_tx_format_put),
2909 SOC_ENUM_EXT("QUAT_TDM_TX_3 Format", tdm_tx_format,
2910 tdm_tx_format_get,
2911 tdm_tx_format_put),
2912 SOC_ENUM_EXT("QUAT_TDM_RX_0 Channels", tdm_rx_chs,
2913 tdm_rx_ch_get,
2914 tdm_rx_ch_put),
2915 SOC_ENUM_EXT("QUAT_TDM_RX_1 Channels", tdm_rx_chs,
2916 tdm_rx_ch_get,
2917 tdm_rx_ch_put),
2918 SOC_ENUM_EXT("QUAT_TDM_RX_2 Channels", tdm_rx_chs,
2919 tdm_rx_ch_get,
2920 tdm_rx_ch_put),
2921 SOC_ENUM_EXT("QUAT_TDM_RX_3 Channels", tdm_rx_chs,
2922 tdm_rx_ch_get,
2923 tdm_rx_ch_put),
2924 SOC_ENUM_EXT("QUAT_TDM_TX_0 Channels", tdm_tx_chs,
2925 tdm_tx_ch_get,
2926 tdm_tx_ch_put),
2927 SOC_ENUM_EXT("QUAT_TDM_TX_1 Channels", tdm_tx_chs,
2928 tdm_tx_ch_get,
2929 tdm_tx_ch_put),
2930 SOC_ENUM_EXT("QUAT_TDM_TX_2 Channels", tdm_tx_chs,
2931 tdm_tx_ch_get,
2932 tdm_tx_ch_put),
2933 SOC_ENUM_EXT("QUAT_TDM_TX_3 Channels", tdm_tx_chs,
2934 tdm_tx_ch_get,
2935 tdm_tx_ch_put),
2936 SOC_ENUM_EXT("QUIN_TDM_RX_0 SampleRate", tdm_rx_sample_rate,
2937 tdm_rx_sample_rate_get,
2938 tdm_rx_sample_rate_put),
2939 SOC_ENUM_EXT("QUIN_TDM_RX_1 SampleRate", tdm_rx_sample_rate,
2940 tdm_rx_sample_rate_get,
2941 tdm_rx_sample_rate_put),
2942 SOC_ENUM_EXT("QUIN_TDM_RX_2 SampleRate", tdm_rx_sample_rate,
2943 tdm_rx_sample_rate_get,
2944 tdm_rx_sample_rate_put),
2945 SOC_ENUM_EXT("QUIN_TDM_RX_3 SampleRate", tdm_rx_sample_rate,
2946 tdm_rx_sample_rate_get,
2947 tdm_rx_sample_rate_put),
2948 SOC_ENUM_EXT("QUIN_TDM_TX_0 SampleRate", tdm_tx_sample_rate,
2949 tdm_tx_sample_rate_get,
2950 tdm_tx_sample_rate_put),
2951 SOC_ENUM_EXT("QUIN_TDM_TX_1 SampleRate", tdm_tx_sample_rate,
2952 tdm_tx_sample_rate_get,
2953 tdm_tx_sample_rate_put),
2954 SOC_ENUM_EXT("QUIN_TDM_TX_2 SampleRate", tdm_tx_sample_rate,
2955 tdm_tx_sample_rate_get,
2956 tdm_tx_sample_rate_put),
2957 SOC_ENUM_EXT("QUIN_TDM_TX_3 SampleRate", tdm_tx_sample_rate,
2958 tdm_tx_sample_rate_get,
2959 tdm_tx_sample_rate_put),
2960 SOC_ENUM_EXT("QUIN_TDM_RX_0 Format", tdm_rx_format,
2961 tdm_rx_format_get,
2962 tdm_rx_format_put),
2963 SOC_ENUM_EXT("QUIN_TDM_RX_1 Format", tdm_rx_format,
2964 tdm_rx_format_get,
2965 tdm_rx_format_put),
2966 SOC_ENUM_EXT("QUIN_TDM_RX_2 Format", tdm_rx_format,
2967 tdm_rx_format_get,
2968 tdm_rx_format_put),
2969 SOC_ENUM_EXT("QUIN_TDM_RX_3 Format", tdm_rx_format,
2970 tdm_rx_format_get,
2971 tdm_rx_format_put),
2972 SOC_ENUM_EXT("QUIN_TDM_TX_0 Format", tdm_tx_format,
2973 tdm_tx_format_get,
2974 tdm_tx_format_put),
2975 SOC_ENUM_EXT("QUIN_TDM_TX_1 Format", tdm_tx_format,
2976 tdm_tx_format_get,
2977 tdm_tx_format_put),
2978 SOC_ENUM_EXT("QUIN_TDM_TX_2 Format", tdm_tx_format,
2979 tdm_tx_format_get,
2980 tdm_tx_format_put),
2981 SOC_ENUM_EXT("QUIN_TDM_TX_3 Format", tdm_tx_format,
2982 tdm_tx_format_get,
2983 tdm_tx_format_put),
2984 SOC_ENUM_EXT("QUIN_TDM_RX_0 Channels", tdm_rx_chs,
2985 tdm_rx_ch_get,
2986 tdm_rx_ch_put),
2987 SOC_ENUM_EXT("QUIN_TDM_RX_1 Channels", tdm_rx_chs,
2988 tdm_rx_ch_get,
2989 tdm_rx_ch_put),
2990 SOC_ENUM_EXT("QUIN_TDM_RX_2 Channels", tdm_rx_chs,
2991 tdm_rx_ch_get,
2992 tdm_rx_ch_put),
2993 SOC_ENUM_EXT("QUIN_TDM_RX_3 Channels", tdm_rx_chs,
2994 tdm_rx_ch_get,
2995 tdm_rx_ch_put),
2996 SOC_ENUM_EXT("QUIN_TDM_TX_0 Channels", tdm_tx_chs,
2997 tdm_tx_ch_get,
2998 tdm_tx_ch_put),
2999 SOC_ENUM_EXT("QUIN_TDM_TX_1 Channels", tdm_tx_chs,
3000 tdm_tx_ch_get,
3001 tdm_tx_ch_put),
3002 SOC_ENUM_EXT("QUIN_TDM_TX_2 Channels", tdm_tx_chs,
3003 tdm_tx_ch_get,
3004 tdm_tx_ch_put),
3005 SOC_ENUM_EXT("QUIN_TDM_TX_3 Channels", tdm_tx_chs,
3006 tdm_tx_ch_get,
3007 tdm_tx_ch_put),
3008 SOC_ENUM_EXT("PRI_TDM SlotNumber", tdm_slot_num,
3009 tdm_slot_num_get, tdm_slot_num_put),
3010 SOC_ENUM_EXT("PRI_TDM SlotWidth", tdm_slot_width,
3011 tdm_slot_width_get, tdm_slot_width_put),
3012 SOC_ENUM_EXT("SEC_TDM SlotNumber", tdm_slot_num,
3013 tdm_slot_num_get, tdm_slot_num_put),
3014 SOC_ENUM_EXT("SEC_TDM SlotWidth", tdm_slot_width,
3015 tdm_slot_width_get, tdm_slot_width_put),
3016 SOC_ENUM_EXT("TERT_TDM SlotNumber", tdm_slot_num,
3017 tdm_slot_num_get, tdm_slot_num_put),
3018 SOC_ENUM_EXT("TERT_TDM SlotWidth", tdm_slot_width,
3019 tdm_slot_width_get, tdm_slot_width_put),
3020 SOC_ENUM_EXT("QUAT_TDM SlotNumber", tdm_slot_num,
3021 tdm_slot_num_get, tdm_slot_num_put),
3022 SOC_ENUM_EXT("QUAT_TDM SlotWidth", tdm_slot_width,
3023 tdm_slot_width_get, tdm_slot_width_put),
3024 SOC_ENUM_EXT("QUIN_TDM SlotNumber", tdm_slot_num,
3025 tdm_slot_num_get, tdm_slot_num_put),
3026 SOC_ENUM_EXT("QUIN_TDM SlotWidth", tdm_slot_width,
3027 tdm_slot_width_get, tdm_slot_width_put),
3028 SOC_SINGLE_MULTI_EXT("PRI_TDM_RX_0 SlotMapping",
3029 SND_SOC_NOPM, 0, 0xFFFF, 0, TDM_SLOT_OFFSET_MAX,
3030 tdm_rx_slot_mapping_get, tdm_rx_slot_mapping_put),
3031 SOC_SINGLE_MULTI_EXT("PRI_TDM_RX_1 SlotMapping",
3032 SND_SOC_NOPM, 0, 0xFFFF, 0, TDM_SLOT_OFFSET_MAX,
3033 tdm_rx_slot_mapping_get, tdm_rx_slot_mapping_put),
3034 SOC_SINGLE_MULTI_EXT("PRI_TDM_RX_2 SlotMapping",
3035 SND_SOC_NOPM, 0, 0xFFFF, 0, TDM_SLOT_OFFSET_MAX,
3036 tdm_rx_slot_mapping_get, tdm_rx_slot_mapping_put),
3037 SOC_SINGLE_MULTI_EXT("PRI_TDM_RX_3 SlotMapping",
3038 SND_SOC_NOPM, 0, 0xFFFF, 0, TDM_SLOT_OFFSET_MAX,
3039 tdm_rx_slot_mapping_get, tdm_rx_slot_mapping_put),
3040 SOC_SINGLE_MULTI_EXT("PRI_TDM_TX_0 SlotMapping",
3041 SND_SOC_NOPM, 0, 0xFFFF, 0, TDM_SLOT_OFFSET_MAX,
3042 tdm_tx_slot_mapping_get, tdm_tx_slot_mapping_put),
3043 SOC_SINGLE_MULTI_EXT("PRI_TDM_TX_1 SlotMapping",
3044 SND_SOC_NOPM, 0, 0xFFFF, 0, TDM_SLOT_OFFSET_MAX,
3045 tdm_tx_slot_mapping_get, tdm_tx_slot_mapping_put),
3046 SOC_SINGLE_MULTI_EXT("PRI_TDM_TX_2 SlotMapping",
3047 SND_SOC_NOPM, 0, 0xFFFF, 0, TDM_SLOT_OFFSET_MAX,
3048 tdm_tx_slot_mapping_get, tdm_tx_slot_mapping_put),
3049 SOC_SINGLE_MULTI_EXT("PRI_TDM_TX_3 SlotMapping",
3050 SND_SOC_NOPM, 0, 0xFFFF, 0, TDM_SLOT_OFFSET_MAX,
3051 tdm_tx_slot_mapping_get, tdm_tx_slot_mapping_put),
3052 SOC_SINGLE_MULTI_EXT("SEC_TDM_RX_0 SlotMapping",
3053 SND_SOC_NOPM, 0, 0xFFFF, 0, TDM_SLOT_OFFSET_MAX,
3054 tdm_rx_slot_mapping_get, tdm_rx_slot_mapping_put),
3055 SOC_SINGLE_MULTI_EXT("SEC_TDM_RX_1 SlotMapping",
3056 SND_SOC_NOPM, 0, 0xFFFF, 0, TDM_SLOT_OFFSET_MAX,
3057 tdm_rx_slot_mapping_get, tdm_rx_slot_mapping_put),
3058 SOC_SINGLE_MULTI_EXT("SEC_TDM_RX_2 SlotMapping",
3059 SND_SOC_NOPM, 0, 0xFFFF, 0, TDM_SLOT_OFFSET_MAX,
3060 tdm_rx_slot_mapping_get, tdm_rx_slot_mapping_put),
3061 SOC_SINGLE_MULTI_EXT("SEC_TDM_RX_3 SlotMapping",
3062 SND_SOC_NOPM, 0, 0xFFFF, 0, TDM_SLOT_OFFSET_MAX,
3063 tdm_rx_slot_mapping_get, tdm_rx_slot_mapping_put),
3064 SOC_SINGLE_MULTI_EXT("SEC_TDM_TX_0 SlotMapping",
3065 SND_SOC_NOPM, 0, 0xFFFF, 0, TDM_SLOT_OFFSET_MAX,
3066 tdm_tx_slot_mapping_get, tdm_tx_slot_mapping_put),
3067 SOC_SINGLE_MULTI_EXT("SEC_TDM_TX_1 SlotMapping",
3068 SND_SOC_NOPM, 0, 0xFFFF, 0, TDM_SLOT_OFFSET_MAX,
3069 tdm_tx_slot_mapping_get, tdm_tx_slot_mapping_put),
3070 SOC_SINGLE_MULTI_EXT("SEC_TDM_TX_2 SlotMapping",
3071 SND_SOC_NOPM, 0, 0xFFFF, 0, TDM_SLOT_OFFSET_MAX,
3072 tdm_tx_slot_mapping_get, tdm_tx_slot_mapping_put),
3073 SOC_SINGLE_MULTI_EXT("SEC_TDM_TX_3 SlotMapping",
3074 SND_SOC_NOPM, 0, 0xFFFF, 0, TDM_SLOT_OFFSET_MAX,
3075 tdm_tx_slot_mapping_get, tdm_tx_slot_mapping_put),
3076 SOC_SINGLE_MULTI_EXT("TERT_TDM_RX_0 SlotMapping",
3077 SND_SOC_NOPM, 0, 0xFFFF, 0, TDM_SLOT_OFFSET_MAX,
3078 tdm_rx_slot_mapping_get, tdm_rx_slot_mapping_put),
3079 SOC_SINGLE_MULTI_EXT("TERT_TDM_RX_1 SlotMapping",
3080 SND_SOC_NOPM, 0, 0xFFFF, 0, TDM_SLOT_OFFSET_MAX,
3081 tdm_rx_slot_mapping_get, tdm_rx_slot_mapping_put),
3082 SOC_SINGLE_MULTI_EXT("TERT_TDM_RX_2 SlotMapping",
3083 SND_SOC_NOPM, 0, 0xFFFF, 0, TDM_SLOT_OFFSET_MAX,
3084 tdm_rx_slot_mapping_get, tdm_rx_slot_mapping_put),
3085 SOC_SINGLE_MULTI_EXT("TERT_TDM_RX_3 SlotMapping",
3086 SND_SOC_NOPM, 0, 0xFFFF, 0, TDM_SLOT_OFFSET_MAX,
3087 tdm_rx_slot_mapping_get, tdm_rx_slot_mapping_put),
3088 SOC_SINGLE_MULTI_EXT("TERT_TDM_RX_4 SlotMapping",
3089 SND_SOC_NOPM, 0, 0xFFFF, 0, TDM_SLOT_OFFSET_MAX,
3090 tdm_rx_slot_mapping_get, tdm_rx_slot_mapping_put),
3091 SOC_SINGLE_MULTI_EXT("TERT_TDM_TX_0 SlotMapping",
3092 SND_SOC_NOPM, 0, 0xFFFF, 0, TDM_SLOT_OFFSET_MAX,
3093 tdm_tx_slot_mapping_get, tdm_tx_slot_mapping_put),
3094 SOC_SINGLE_MULTI_EXT("TERT_TDM_TX_1 SlotMapping",
3095 SND_SOC_NOPM, 0, 0xFFFF, 0, TDM_SLOT_OFFSET_MAX,
3096 tdm_tx_slot_mapping_get, tdm_tx_slot_mapping_put),
3097 SOC_SINGLE_MULTI_EXT("TERT_TDM_TX_2 SlotMapping",
3098 SND_SOC_NOPM, 0, 0xFFFF, 0, TDM_SLOT_OFFSET_MAX,
3099 tdm_tx_slot_mapping_get, tdm_tx_slot_mapping_put),
3100 SOC_SINGLE_MULTI_EXT("TERT_TDM_TX_3 SlotMapping",
3101 SND_SOC_NOPM, 0, 0xFFFF, 0, TDM_SLOT_OFFSET_MAX,
3102 tdm_tx_slot_mapping_get, tdm_tx_slot_mapping_put),
3103 SOC_SINGLE_MULTI_EXT("QUAT_TDM_RX_0 SlotMapping",
3104 SND_SOC_NOPM, 0, 0xFFFF, 0, TDM_SLOT_OFFSET_MAX,
3105 tdm_rx_slot_mapping_get, tdm_rx_slot_mapping_put),
3106 SOC_SINGLE_MULTI_EXT("QUAT_TDM_RX_1 SlotMapping",
3107 SND_SOC_NOPM, 0, 0xFFFF, 0, TDM_SLOT_OFFSET_MAX,
3108 tdm_rx_slot_mapping_get, tdm_rx_slot_mapping_put),
3109 SOC_SINGLE_MULTI_EXT("QUAT_TDM_RX_2 SlotMapping",
3110 SND_SOC_NOPM, 0, 0xFFFF, 0, TDM_SLOT_OFFSET_MAX,
3111 tdm_rx_slot_mapping_get, tdm_rx_slot_mapping_put),
3112 SOC_SINGLE_MULTI_EXT("QUAT_TDM_RX_3 SlotMapping",
3113 SND_SOC_NOPM, 0, 0xFFFF, 0, TDM_SLOT_OFFSET_MAX,
3114 tdm_rx_slot_mapping_get, tdm_rx_slot_mapping_put),
3115 SOC_SINGLE_MULTI_EXT("QUAT_TDM_TX_0 SlotMapping",
3116 SND_SOC_NOPM, 0, 0xFFFF, 0, TDM_SLOT_OFFSET_MAX,
3117 tdm_tx_slot_mapping_get, tdm_tx_slot_mapping_put),
3118 SOC_SINGLE_MULTI_EXT("QUAT_TDM_TX_1 SlotMapping",
3119 SND_SOC_NOPM, 0, 0xFFFF, 0, TDM_SLOT_OFFSET_MAX,
3120 tdm_tx_slot_mapping_get, tdm_tx_slot_mapping_put),
3121 SOC_SINGLE_MULTI_EXT("QUAT_TDM_TX_2 SlotMapping",
3122 SND_SOC_NOPM, 0, 0xFFFF, 0, TDM_SLOT_OFFSET_MAX,
3123 tdm_tx_slot_mapping_get, tdm_tx_slot_mapping_put),
3124 SOC_SINGLE_MULTI_EXT("QUAT_TDM_TX_3 SlotMapping",
3125 SND_SOC_NOPM, 0, 0xFFFF, 0, TDM_SLOT_OFFSET_MAX,
3126 tdm_tx_slot_mapping_get, tdm_tx_slot_mapping_put),
3127 SOC_SINGLE_MULTI_EXT("QUIN_TDM_RX_0 SlotMapping",
3128 SND_SOC_NOPM, 0, 0xFFFF, 0, TDM_SLOT_OFFSET_MAX,
3129 tdm_rx_slot_mapping_get, tdm_rx_slot_mapping_put),
3130 SOC_SINGLE_MULTI_EXT("QUIN_TDM_RX_1 SlotMapping",
3131 SND_SOC_NOPM, 0, 0xFFFF, 0, TDM_SLOT_OFFSET_MAX,
3132 tdm_rx_slot_mapping_get, tdm_rx_slot_mapping_put),
3133 SOC_SINGLE_MULTI_EXT("QUIN_TDM_RX_2 SlotMapping",
3134 SND_SOC_NOPM, 0, 0xFFFF, 0, TDM_SLOT_OFFSET_MAX,
3135 tdm_rx_slot_mapping_get, tdm_rx_slot_mapping_put),
3136 SOC_SINGLE_MULTI_EXT("QUIN_TDM_RX_3 SlotMapping",
3137 SND_SOC_NOPM, 0, 0xFFFF, 0, TDM_SLOT_OFFSET_MAX,
3138 tdm_rx_slot_mapping_get, tdm_rx_slot_mapping_put),
3139 SOC_SINGLE_MULTI_EXT("QUIN_TDM_TX_0 SlotMapping",
3140 SND_SOC_NOPM, 0, 0xFFFF, 0, TDM_SLOT_OFFSET_MAX,
3141 tdm_tx_slot_mapping_get, tdm_tx_slot_mapping_put),
3142 SOC_SINGLE_MULTI_EXT("QUIN_TDM_TX_1 SlotMapping",
3143 SND_SOC_NOPM, 0, 0xFFFF, 0, TDM_SLOT_OFFSET_MAX,
3144 tdm_tx_slot_mapping_get, tdm_tx_slot_mapping_put),
3145 SOC_SINGLE_MULTI_EXT("QUIN_TDM_TX_2 SlotMapping",
3146 SND_SOC_NOPM, 0, 0xFFFF, 0, TDM_SLOT_OFFSET_MAX,
3147 tdm_tx_slot_mapping_get, tdm_tx_slot_mapping_put),
3148 SOC_SINGLE_MULTI_EXT("QUIN_TDM_TX_3 SlotMapping",
3149 SND_SOC_NOPM, 0, 0xFFFF, 0, TDM_SLOT_OFFSET_MAX,
3150 tdm_tx_slot_mapping_get, tdm_tx_slot_mapping_put),
3151 SOC_ENUM_EXT("PRIM_AUX_PCM_RX SampleRate", prim_aux_pcm_rx_sample_rate,
3152 aux_pcm_rx_sample_rate_get,
3153 aux_pcm_rx_sample_rate_put),
3154 SOC_ENUM_EXT("SEC_AUX_PCM_RX SampleRate", sec_aux_pcm_rx_sample_rate,
3155 aux_pcm_rx_sample_rate_get,
3156 aux_pcm_rx_sample_rate_put),
3157 SOC_ENUM_EXT("TERT_AUX_PCM_RX SampleRate", tert_aux_pcm_rx_sample_rate,
3158 aux_pcm_rx_sample_rate_get,
3159 aux_pcm_rx_sample_rate_put),
3160 SOC_ENUM_EXT("QUAT_AUX_PCM_RX SampleRate", quat_aux_pcm_rx_sample_rate,
3161 aux_pcm_rx_sample_rate_get,
3162 aux_pcm_rx_sample_rate_put),
3163 SOC_ENUM_EXT("QUIN_AUX_PCM_RX SampleRate", quin_aux_pcm_rx_sample_rate,
3164 aux_pcm_rx_sample_rate_get,
3165 aux_pcm_rx_sample_rate_put),
3166 SOC_ENUM_EXT("PRIM_AUX_PCM_TX SampleRate", prim_aux_pcm_tx_sample_rate,
3167 aux_pcm_tx_sample_rate_get,
3168 aux_pcm_tx_sample_rate_put),
3169 SOC_ENUM_EXT("SEC_AUX_PCM_TX SampleRate", sec_aux_pcm_tx_sample_rate,
3170 aux_pcm_tx_sample_rate_get,
3171 aux_pcm_tx_sample_rate_put),
3172 SOC_ENUM_EXT("TERT_AUX_PCM_TX SampleRate", tert_aux_pcm_tx_sample_rate,
3173 aux_pcm_tx_sample_rate_get,
3174 aux_pcm_tx_sample_rate_put),
3175 SOC_ENUM_EXT("QUAT_AUX_PCM_TX SampleRate", quat_aux_pcm_tx_sample_rate,
3176 aux_pcm_tx_sample_rate_get,
3177 aux_pcm_tx_sample_rate_put),
3178 SOC_ENUM_EXT("QUIN_AUX_PCM_TX SampleRate", quin_aux_pcm_tx_sample_rate,
3179 aux_pcm_tx_sample_rate_get,
3180 aux_pcm_tx_sample_rate_put),
3181 SOC_ENUM_EXT("PRIM_MI2S_RX SampleRate", prim_mi2s_rx_sample_rate,
3182 mi2s_rx_sample_rate_get,
3183 mi2s_rx_sample_rate_put),
3184 SOC_ENUM_EXT("SEC_MI2S_RX SampleRate", sec_mi2s_rx_sample_rate,
3185 mi2s_rx_sample_rate_get,
3186 mi2s_rx_sample_rate_put),
3187 SOC_ENUM_EXT("TERT_MI2S_RX SampleRate", tert_mi2s_rx_sample_rate,
3188 mi2s_rx_sample_rate_get,
3189 mi2s_rx_sample_rate_put),
3190 SOC_ENUM_EXT("QUAT_MI2S_RX SampleRate", quat_mi2s_rx_sample_rate,
3191 mi2s_rx_sample_rate_get,
3192 mi2s_rx_sample_rate_put),
3193 SOC_ENUM_EXT("QUIN_MI2S_RX SampleRate", quin_mi2s_rx_sample_rate,
3194 mi2s_rx_sample_rate_get,
3195 mi2s_rx_sample_rate_put),
3196 SOC_ENUM_EXT("PRIM_MI2S_TX SampleRate", prim_mi2s_tx_sample_rate,
3197 mi2s_tx_sample_rate_get,
3198 mi2s_tx_sample_rate_put),
3199 SOC_ENUM_EXT("SEC_MI2S_TX SampleRate", sec_mi2s_tx_sample_rate,
3200 mi2s_tx_sample_rate_get,
3201 mi2s_tx_sample_rate_put),
3202 SOC_ENUM_EXT("TERT_MI2S_TX SampleRate", tert_mi2s_tx_sample_rate,
3203 mi2s_tx_sample_rate_get,
3204 mi2s_tx_sample_rate_put),
3205 SOC_ENUM_EXT("QUAT_MI2S_TX SampleRate", quat_mi2s_tx_sample_rate,
3206 mi2s_tx_sample_rate_get,
3207 mi2s_tx_sample_rate_put),
3208 SOC_ENUM_EXT("QUIN_MI2S_TX SampleRate", quin_mi2s_tx_sample_rate,
3209 mi2s_tx_sample_rate_get,
3210 mi2s_tx_sample_rate_put),
3211 SOC_ENUM_EXT("PRIM_MI2S_RX Channels", prim_mi2s_rx_chs,
3212 msm_mi2s_rx_ch_get, msm_mi2s_rx_ch_put),
3213 SOC_ENUM_EXT("PRIM_MI2S_TX Channels", prim_mi2s_tx_chs,
3214 msm_mi2s_tx_ch_get, msm_mi2s_tx_ch_put),
3215 SOC_ENUM_EXT("SEC_MI2S_RX Channels", sec_mi2s_rx_chs,
3216 msm_mi2s_rx_ch_get, msm_mi2s_rx_ch_put),
3217 SOC_ENUM_EXT("SEC_MI2S_TX Channels", sec_mi2s_tx_chs,
3218 msm_mi2s_tx_ch_get, msm_mi2s_tx_ch_put),
3219 SOC_ENUM_EXT("TERT_MI2S_RX Channels", tert_mi2s_rx_chs,
3220 msm_mi2s_rx_ch_get, msm_mi2s_rx_ch_put),
3221 SOC_ENUM_EXT("TERT_MI2S_TX Channels", tert_mi2s_tx_chs,
3222 msm_mi2s_tx_ch_get, msm_mi2s_tx_ch_put),
3223 SOC_ENUM_EXT("QUAT_MI2S_RX Channels", quat_mi2s_rx_chs,
3224 msm_mi2s_rx_ch_get, msm_mi2s_rx_ch_put),
3225 SOC_ENUM_EXT("QUAT_MI2S_TX Channels", quat_mi2s_tx_chs,
3226 msm_mi2s_tx_ch_get, msm_mi2s_tx_ch_put),
3227 SOC_ENUM_EXT("QUIN_MI2S_RX Channels", quin_mi2s_rx_chs,
3228 msm_mi2s_rx_ch_get, msm_mi2s_rx_ch_put),
3229 SOC_ENUM_EXT("QUIN_MI2S_TX Channels", quin_mi2s_tx_chs,
3230 msm_mi2s_tx_ch_get, msm_mi2s_tx_ch_put),
3231 SOC_ENUM_EXT("PRIM_MI2S_RX Format", mi2s_rx_format,
3232 msm_mi2s_rx_format_get, msm_mi2s_rx_format_put),
3233 SOC_ENUM_EXT("PRIM_MI2S_TX Format", mi2s_tx_format,
3234 msm_mi2s_tx_format_get, msm_mi2s_tx_format_put),
3235 SOC_ENUM_EXT("SEC_MI2S_RX Format", mi2s_rx_format,
3236 msm_mi2s_rx_format_get, msm_mi2s_rx_format_put),
3237 SOC_ENUM_EXT("SEC_MI2S_TX Format", mi2s_tx_format,
3238 msm_mi2s_tx_format_get, msm_mi2s_tx_format_put),
3239 SOC_ENUM_EXT("TERT_MI2S_RX Format", mi2s_rx_format,
3240 msm_mi2s_rx_format_get, msm_mi2s_rx_format_put),
3241 SOC_ENUM_EXT("TERT_MI2S_TX Format", mi2s_tx_format,
3242 msm_mi2s_tx_format_get, msm_mi2s_tx_format_put),
3243 SOC_ENUM_EXT("QUAT_MI2S_RX Format", mi2s_rx_format,
3244 msm_mi2s_rx_format_get, msm_mi2s_rx_format_put),
3245 SOC_ENUM_EXT("QUAT_MI2S_TX Format", mi2s_tx_format,
3246 msm_mi2s_tx_format_get, msm_mi2s_tx_format_put),
3247 SOC_ENUM_EXT("QUIN_MI2S_RX Format", mi2s_rx_format,
3248 msm_mi2s_rx_format_get, msm_mi2s_rx_format_put),
3249 SOC_ENUM_EXT("QUIN_MI2S_TX Format", mi2s_tx_format,
3250 msm_mi2s_tx_format_get, msm_mi2s_tx_format_put),
3251 SOC_ENUM_EXT("PRIM_AUX_PCM_RX Format", aux_pcm_rx_format,
3252 msm_aux_pcm_rx_format_get, msm_aux_pcm_rx_format_put),
3253 SOC_ENUM_EXT("PRIM_AUX_PCM_TX Format", aux_pcm_tx_format,
3254 msm_aux_pcm_tx_format_get, msm_aux_pcm_tx_format_put),
3255 SOC_ENUM_EXT("SEC_AUX_PCM_RX Format", aux_pcm_rx_format,
3256 msm_aux_pcm_rx_format_get, msm_aux_pcm_rx_format_put),
3257 SOC_ENUM_EXT("SEC_AUX_PCM_TX Format", aux_pcm_tx_format,
3258 msm_aux_pcm_tx_format_get, msm_aux_pcm_tx_format_put),
3259 SOC_ENUM_EXT("TERT_AUX_PCM_RX Format", aux_pcm_rx_format,
3260 msm_aux_pcm_rx_format_get, msm_aux_pcm_rx_format_put),
3261 SOC_ENUM_EXT("TERT_AUX_PCM_TX Format", aux_pcm_tx_format,
3262 msm_aux_pcm_tx_format_get, msm_aux_pcm_tx_format_put),
3263 SOC_ENUM_EXT("QUAT_AUX_PCM_RX Format", aux_pcm_rx_format,
3264 msm_aux_pcm_rx_format_get, msm_aux_pcm_rx_format_put),
3265 SOC_ENUM_EXT("QUAT_AUX_PCM_TX Format", aux_pcm_tx_format,
3266 msm_aux_pcm_tx_format_get, msm_aux_pcm_tx_format_put),
3267 SOC_ENUM_EXT("QUIN_AUX_PCM_RX Format", aux_pcm_rx_format,
3268 msm_aux_pcm_rx_format_get, msm_aux_pcm_rx_format_put),
3269 SOC_ENUM_EXT("QUIN_AUX_PCM_TX Format", aux_pcm_tx_format,
3270 msm_aux_pcm_tx_format_get, msm_aux_pcm_tx_format_put),
3271};
3272
3273static inline int param_is_mask(int p)
3274{
3275 return (p >= SNDRV_PCM_HW_PARAM_FIRST_MASK) &&
3276 (p <= SNDRV_PCM_HW_PARAM_LAST_MASK);
3277}
3278
3279static inline struct snd_mask *param_to_mask(struct snd_pcm_hw_params *p,
3280 int n)
3281{
3282 return &(p->masks[n - SNDRV_PCM_HW_PARAM_FIRST_MASK]);
3283}
3284
3285static void param_set_mask(struct snd_pcm_hw_params *p, int n,
3286 unsigned int bit)
3287{
3288 if (bit >= SNDRV_MASK_MAX)
3289 return;
3290 if (param_is_mask(n)) {
3291 struct snd_mask *m = param_to_mask(p, n);
3292
3293 m->bits[0] = 0;
3294 m->bits[1] = 0;
3295 m->bits[bit >> 5] |= (1 << (bit & 31));
3296 }
3297}
3298
3299static int msm_ext_disp_get_idx_from_beid(int32_t be_id)
3300{
3301 int idx;
3302
3303 switch (be_id) {
3304 case MSM_BACKEND_DAI_DISPLAY_PORT_RX:
3305 idx = DP_RX_IDX;
3306 break;
3307 default:
3308 pr_err("%s: Incorrect ext_disp BE id %d\n", __func__, be_id);
3309 idx = -EINVAL;
3310 break;
3311 }
3312
3313 return idx;
3314}
3315
3316static int msm_be_hw_params_fixup(struct snd_soc_pcm_runtime *rtd,
3317 struct snd_pcm_hw_params *params)
3318{
3319 struct snd_soc_dai_link *dai_link = rtd->dai_link;
3320 struct snd_interval *rate = hw_param_interval(params,
3321 SNDRV_PCM_HW_PARAM_RATE);
3322 struct snd_interval *channels = hw_param_interval(params,
3323 SNDRV_PCM_HW_PARAM_CHANNELS);
3324 int rc = 0;
3325 int idx;
3326
3327 pr_debug("%s: format = %d, rate = %d\n",
3328 __func__, params_format(params), params_rate(params));
3329
3330 switch (dai_link->id) {
3331 case MSM_BACKEND_DAI_USB_RX:
3332 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
3333 usb_rx_cfg.bit_format);
3334 rate->min = rate->max = usb_rx_cfg.sample_rate;
3335 channels->min = channels->max = usb_rx_cfg.channels;
3336 break;
3337
3338 case MSM_BACKEND_DAI_USB_TX:
3339 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
3340 usb_tx_cfg.bit_format);
3341 rate->min = rate->max = usb_tx_cfg.sample_rate;
3342 channels->min = channels->max = usb_tx_cfg.channels;
3343 break;
3344
3345 case MSM_BACKEND_DAI_DISPLAY_PORT_RX:
3346 idx = msm_ext_disp_get_idx_from_beid(dai_link->id);
3347 if (idx < 0) {
3348 pr_err("%s: Incorrect ext disp idx %d\n",
3349 __func__, idx);
3350 rc = idx;
3351 goto done;
3352 }
3353
3354 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
3355 ext_disp_rx_cfg[idx].bit_format);
3356 rate->min = rate->max = ext_disp_rx_cfg[idx].sample_rate;
3357 channels->min = channels->max = ext_disp_rx_cfg[idx].channels;
3358 break;
3359
3360 case MSM_BACKEND_DAI_AFE_PCM_RX:
3361 channels->min = channels->max = proxy_rx_cfg.channels;
3362 rate->min = rate->max = SAMPLING_RATE_48KHZ;
3363 break;
3364
3365 case MSM_BACKEND_DAI_PRI_TDM_RX_0:
3366 channels->min = channels->max =
3367 tdm_rx_cfg[TDM_PRI][TDM_0].channels;
3368 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
3369 tdm_rx_cfg[TDM_PRI][TDM_0].bit_format);
3370 rate->min = rate->max = tdm_rx_cfg[TDM_PRI][TDM_0].sample_rate;
3371 break;
3372
3373 case MSM_BACKEND_DAI_PRI_TDM_TX_0:
3374 channels->min = channels->max =
3375 tdm_tx_cfg[TDM_PRI][TDM_0].channels;
3376 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
3377 tdm_tx_cfg[TDM_PRI][TDM_0].bit_format);
3378 rate->min = rate->max = tdm_tx_cfg[TDM_PRI][TDM_0].sample_rate;
3379 break;
3380
3381 case MSM_BACKEND_DAI_SEC_TDM_RX_0:
3382 channels->min = channels->max =
3383 tdm_rx_cfg[TDM_SEC][TDM_0].channels;
3384 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
3385 tdm_rx_cfg[TDM_SEC][TDM_0].bit_format);
3386 rate->min = rate->max = tdm_rx_cfg[TDM_SEC][TDM_0].sample_rate;
3387 break;
3388
3389 case MSM_BACKEND_DAI_SEC_TDM_TX_0:
3390 channels->min = channels->max =
3391 tdm_tx_cfg[TDM_SEC][TDM_0].channels;
3392 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
3393 tdm_tx_cfg[TDM_SEC][TDM_0].bit_format);
3394 rate->min = rate->max = tdm_tx_cfg[TDM_SEC][TDM_0].sample_rate;
3395 break;
3396
3397 case MSM_BACKEND_DAI_TERT_TDM_RX_0:
3398 channels->min = channels->max =
3399 tdm_rx_cfg[TDM_TERT][TDM_0].channels;
3400 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
3401 tdm_rx_cfg[TDM_TERT][TDM_0].bit_format);
3402 rate->min = rate->max = tdm_rx_cfg[TDM_TERT][TDM_0].sample_rate;
3403 break;
3404
3405 case MSM_BACKEND_DAI_TERT_TDM_TX_0:
3406 channels->min = channels->max =
3407 tdm_tx_cfg[TDM_TERT][TDM_0].channels;
3408 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
3409 tdm_tx_cfg[TDM_TERT][TDM_0].bit_format);
3410 rate->min = rate->max = tdm_tx_cfg[TDM_TERT][TDM_0].sample_rate;
3411 break;
3412
3413 case MSM_BACKEND_DAI_QUAT_TDM_RX_0:
3414 channels->min = channels->max =
3415 tdm_rx_cfg[TDM_QUAT][TDM_0].channels;
3416 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
3417 tdm_rx_cfg[TDM_QUAT][TDM_0].bit_format);
3418 rate->min = rate->max = tdm_rx_cfg[TDM_QUAT][TDM_0].sample_rate;
3419 break;
3420
3421 case MSM_BACKEND_DAI_QUAT_TDM_TX_0:
3422 channels->min = channels->max =
3423 tdm_tx_cfg[TDM_QUAT][TDM_0].channels;
3424 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
3425 tdm_tx_cfg[TDM_QUAT][TDM_0].bit_format);
3426 rate->min = rate->max = tdm_tx_cfg[TDM_QUAT][TDM_0].sample_rate;
3427 break;
3428
3429 case MSM_BACKEND_DAI_QUIN_TDM_RX_0:
3430 channels->min = channels->max =
3431 tdm_rx_cfg[TDM_QUIN][TDM_0].channels;
3432 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
3433 tdm_rx_cfg[TDM_QUIN][TDM_0].bit_format);
3434 rate->min = rate->max = tdm_rx_cfg[TDM_QUIN][TDM_0].sample_rate;
3435 break;
3436
3437 case MSM_BACKEND_DAI_QUIN_TDM_TX_0:
3438 channels->min = channels->max =
3439 tdm_tx_cfg[TDM_QUIN][TDM_0].channels;
3440 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
3441 tdm_tx_cfg[TDM_QUIN][TDM_0].bit_format);
3442 rate->min = rate->max = tdm_tx_cfg[TDM_QUIN][TDM_0].sample_rate;
3443 break;
3444
3445
3446 case MSM_BACKEND_DAI_AUXPCM_RX:
3447 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
3448 aux_pcm_rx_cfg[PRIM_AUX_PCM].bit_format);
3449 rate->min = rate->max =
3450 aux_pcm_rx_cfg[PRIM_AUX_PCM].sample_rate;
3451 channels->min = channels->max =
3452 aux_pcm_rx_cfg[PRIM_AUX_PCM].channels;
3453 break;
3454
3455 case MSM_BACKEND_DAI_AUXPCM_TX:
3456 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
3457 aux_pcm_tx_cfg[PRIM_AUX_PCM].bit_format);
3458 rate->min = rate->max =
3459 aux_pcm_tx_cfg[PRIM_AUX_PCM].sample_rate;
3460 channels->min = channels->max =
3461 aux_pcm_tx_cfg[PRIM_AUX_PCM].channels;
3462 break;
3463
3464 case MSM_BACKEND_DAI_SEC_AUXPCM_RX:
3465 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
3466 aux_pcm_rx_cfg[SEC_AUX_PCM].bit_format);
3467 rate->min = rate->max =
3468 aux_pcm_rx_cfg[SEC_AUX_PCM].sample_rate;
3469 channels->min = channels->max =
3470 aux_pcm_rx_cfg[SEC_AUX_PCM].channels;
3471 break;
3472
3473 case MSM_BACKEND_DAI_SEC_AUXPCM_TX:
3474 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
3475 aux_pcm_tx_cfg[SEC_AUX_PCM].bit_format);
3476 rate->min = rate->max =
3477 aux_pcm_tx_cfg[SEC_AUX_PCM].sample_rate;
3478 channels->min = channels->max =
3479 aux_pcm_tx_cfg[SEC_AUX_PCM].channels;
3480 break;
3481
3482 case MSM_BACKEND_DAI_TERT_AUXPCM_RX:
3483 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
3484 aux_pcm_rx_cfg[TERT_AUX_PCM].bit_format);
3485 rate->min = rate->max =
3486 aux_pcm_rx_cfg[TERT_AUX_PCM].sample_rate;
3487 channels->min = channels->max =
3488 aux_pcm_rx_cfg[TERT_AUX_PCM].channels;
3489 break;
3490
3491 case MSM_BACKEND_DAI_TERT_AUXPCM_TX:
3492 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
3493 aux_pcm_tx_cfg[TERT_AUX_PCM].bit_format);
3494 rate->min = rate->max =
3495 aux_pcm_tx_cfg[TERT_AUX_PCM].sample_rate;
3496 channels->min = channels->max =
3497 aux_pcm_tx_cfg[TERT_AUX_PCM].channels;
3498 break;
3499
3500 case MSM_BACKEND_DAI_QUAT_AUXPCM_RX:
3501 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
3502 aux_pcm_rx_cfg[QUAT_AUX_PCM].bit_format);
3503 rate->min = rate->max =
3504 aux_pcm_rx_cfg[QUAT_AUX_PCM].sample_rate;
3505 channels->min = channels->max =
3506 aux_pcm_rx_cfg[QUAT_AUX_PCM].channels;
3507 break;
3508
3509 case MSM_BACKEND_DAI_QUAT_AUXPCM_TX:
3510 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
3511 aux_pcm_tx_cfg[QUAT_AUX_PCM].bit_format);
3512 rate->min = rate->max =
3513 aux_pcm_tx_cfg[QUAT_AUX_PCM].sample_rate;
3514 channels->min = channels->max =
3515 aux_pcm_tx_cfg[QUAT_AUX_PCM].channels;
3516 break;
3517
3518 case MSM_BACKEND_DAI_QUIN_AUXPCM_RX:
3519 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
3520 aux_pcm_rx_cfg[QUIN_AUX_PCM].bit_format);
3521 rate->min = rate->max =
3522 aux_pcm_rx_cfg[QUIN_AUX_PCM].sample_rate;
3523 channels->min = channels->max =
3524 aux_pcm_rx_cfg[QUIN_AUX_PCM].channels;
3525 break;
3526
3527 case MSM_BACKEND_DAI_QUIN_AUXPCM_TX:
3528 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
3529 aux_pcm_tx_cfg[QUIN_AUX_PCM].bit_format);
3530 rate->min = rate->max =
3531 aux_pcm_tx_cfg[QUIN_AUX_PCM].sample_rate;
3532 channels->min = channels->max =
3533 aux_pcm_tx_cfg[QUIN_AUX_PCM].channels;
3534 break;
3535
3536 case MSM_BACKEND_DAI_PRI_MI2S_RX:
3537 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
3538 mi2s_rx_cfg[PRIM_MI2S].bit_format);
3539 rate->min = rate->max = mi2s_rx_cfg[PRIM_MI2S].sample_rate;
3540 channels->min = channels->max =
3541 mi2s_rx_cfg[PRIM_MI2S].channels;
3542 break;
3543
3544 case MSM_BACKEND_DAI_PRI_MI2S_TX:
3545 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
3546 mi2s_tx_cfg[PRIM_MI2S].bit_format);
3547 rate->min = rate->max = mi2s_tx_cfg[PRIM_MI2S].sample_rate;
3548 channels->min = channels->max =
3549 mi2s_tx_cfg[PRIM_MI2S].channels;
3550 break;
3551
3552 case MSM_BACKEND_DAI_SECONDARY_MI2S_RX:
3553 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
3554 mi2s_rx_cfg[SEC_MI2S].bit_format);
3555 rate->min = rate->max = mi2s_rx_cfg[SEC_MI2S].sample_rate;
3556 channels->min = channels->max =
3557 mi2s_rx_cfg[SEC_MI2S].channels;
3558 break;
3559
3560 case MSM_BACKEND_DAI_SECONDARY_MI2S_TX:
3561 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
3562 mi2s_tx_cfg[SEC_MI2S].bit_format);
3563 rate->min = rate->max = mi2s_tx_cfg[SEC_MI2S].sample_rate;
3564 channels->min = channels->max =
3565 mi2s_tx_cfg[SEC_MI2S].channels;
3566 break;
3567
3568 case MSM_BACKEND_DAI_TERTIARY_MI2S_RX:
3569 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
3570 mi2s_rx_cfg[TERT_MI2S].bit_format);
3571 rate->min = rate->max = mi2s_rx_cfg[TERT_MI2S].sample_rate;
3572 channels->min = channels->max =
3573 mi2s_rx_cfg[TERT_MI2S].channels;
3574 break;
3575
3576 case MSM_BACKEND_DAI_TERTIARY_MI2S_TX:
3577 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
3578 mi2s_tx_cfg[TERT_MI2S].bit_format);
3579 rate->min = rate->max = mi2s_tx_cfg[TERT_MI2S].sample_rate;
3580 channels->min = channels->max =
3581 mi2s_tx_cfg[TERT_MI2S].channels;
3582 break;
3583
3584 case MSM_BACKEND_DAI_QUATERNARY_MI2S_RX:
3585 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
3586 mi2s_rx_cfg[QUAT_MI2S].bit_format);
3587 rate->min = rate->max = mi2s_rx_cfg[QUAT_MI2S].sample_rate;
3588 channels->min = channels->max =
3589 mi2s_rx_cfg[QUAT_MI2S].channels;
3590 break;
3591
3592 case MSM_BACKEND_DAI_QUATERNARY_MI2S_TX:
3593 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
3594 mi2s_tx_cfg[QUAT_MI2S].bit_format);
3595 rate->min = rate->max = mi2s_tx_cfg[QUAT_MI2S].sample_rate;
3596 channels->min = channels->max =
3597 mi2s_tx_cfg[QUAT_MI2S].channels;
3598 break;
3599
3600 case MSM_BACKEND_DAI_QUINARY_MI2S_RX:
3601 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
3602 mi2s_rx_cfg[QUIN_MI2S].bit_format);
3603 rate->min = rate->max = mi2s_rx_cfg[QUIN_MI2S].sample_rate;
3604 channels->min = channels->max =
3605 mi2s_rx_cfg[QUIN_MI2S].channels;
3606 break;
3607
3608 case MSM_BACKEND_DAI_QUINARY_MI2S_TX:
3609 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
3610 mi2s_tx_cfg[QUIN_MI2S].bit_format);
3611 rate->min = rate->max = mi2s_tx_cfg[QUIN_MI2S].sample_rate;
3612 channels->min = channels->max =
3613 mi2s_tx_cfg[QUIN_MI2S].channels;
3614 break;
3615
3616 default:
3617 rate->min = rate->max = SAMPLING_RATE_48KHZ;
3618 break;
3619 }
3620
3621done:
3622 return rc;
3623}
3624
3625static int msm_get_port_id(int be_id)
3626{
3627 int afe_port_id;
3628
3629 switch (be_id) {
3630 case MSM_BACKEND_DAI_PRI_MI2S_RX:
3631 afe_port_id = AFE_PORT_ID_PRIMARY_MI2S_RX;
3632 break;
3633 case MSM_BACKEND_DAI_PRI_MI2S_TX:
3634 afe_port_id = AFE_PORT_ID_PRIMARY_MI2S_TX;
3635 break;
3636 case MSM_BACKEND_DAI_SECONDARY_MI2S_RX:
3637 afe_port_id = AFE_PORT_ID_SECONDARY_MI2S_RX;
3638 break;
3639 case MSM_BACKEND_DAI_SECONDARY_MI2S_TX:
3640 afe_port_id = AFE_PORT_ID_SECONDARY_MI2S_TX;
3641 break;
3642 case MSM_BACKEND_DAI_TERTIARY_MI2S_RX:
3643 afe_port_id = AFE_PORT_ID_TERTIARY_MI2S_RX;
3644 break;
3645 case MSM_BACKEND_DAI_TERTIARY_MI2S_TX:
3646 afe_port_id = AFE_PORT_ID_TERTIARY_MI2S_TX;
3647 break;
3648 case MSM_BACKEND_DAI_QUATERNARY_MI2S_RX:
3649 afe_port_id = AFE_PORT_ID_QUATERNARY_MI2S_RX;
3650 break;
3651 case MSM_BACKEND_DAI_QUATERNARY_MI2S_TX:
3652 afe_port_id = AFE_PORT_ID_QUATERNARY_MI2S_TX;
3653 break;
3654 case MSM_BACKEND_DAI_QUINARY_MI2S_RX:
3655 afe_port_id = AFE_PORT_ID_QUINARY_MI2S_RX;
3656 break;
3657 case MSM_BACKEND_DAI_QUINARY_MI2S_TX:
3658 afe_port_id = AFE_PORT_ID_QUINARY_MI2S_TX;
3659 break;
3660 default:
3661 pr_err("%s: Invalid BE id: %d\n", __func__, be_id);
3662 afe_port_id = -EINVAL;
3663 }
3664
3665 return afe_port_id;
3666}
3667
3668static u32 get_mi2s_bits_per_sample(u32 bit_format)
3669{
3670 u32 bit_per_sample;
3671
3672 switch (bit_format) {
3673 case SNDRV_PCM_FORMAT_S32_LE:
3674 case SNDRV_PCM_FORMAT_S24_3LE:
3675 case SNDRV_PCM_FORMAT_S24_LE:
3676 bit_per_sample = 32;
3677 break;
3678 case SNDRV_PCM_FORMAT_S16_LE:
3679 default:
3680 bit_per_sample = 16;
3681 break;
3682 }
3683
3684 return bit_per_sample;
3685}
3686
3687static void update_mi2s_clk_val(int dai_id, int stream)
3688{
3689 u32 bit_per_sample;
3690
3691 if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
3692 bit_per_sample =
3693 get_mi2s_bits_per_sample(mi2s_rx_cfg[dai_id].bit_format);
3694 mi2s_clk[dai_id].clk_freq_in_hz =
3695 mi2s_rx_cfg[dai_id].sample_rate * 2 * bit_per_sample;
3696 } else {
3697 bit_per_sample =
3698 get_mi2s_bits_per_sample(mi2s_tx_cfg[dai_id].bit_format);
3699 mi2s_clk[dai_id].clk_freq_in_hz =
3700 mi2s_tx_cfg[dai_id].sample_rate * 2 * bit_per_sample;
3701 }
3702}
3703
3704static int msm_mi2s_set_sclk(struct snd_pcm_substream *substream, bool enable)
3705{
3706 int ret = 0;
3707 struct snd_soc_pcm_runtime *rtd = substream->private_data;
3708 struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
3709 int port_id = 0;
3710 int index = cpu_dai->id;
3711
3712 port_id = msm_get_port_id(rtd->dai_link->id);
3713 if (port_id < 0) {
3714 dev_err(rtd->card->dev, "%s: Invalid port_id\n", __func__);
3715 ret = port_id;
3716 goto err;
3717 }
3718
3719 if (enable) {
3720 update_mi2s_clk_val(index, substream->stream);
3721 dev_dbg(rtd->card->dev, "%s: clock rate %ul\n", __func__,
3722 mi2s_clk[index].clk_freq_in_hz);
3723 }
3724
3725 mi2s_clk[index].enable = enable;
3726 ret = afe_set_lpass_clock_v2(port_id,
3727 &mi2s_clk[index]);
3728 if (ret < 0) {
3729 dev_err(rtd->card->dev,
3730 "%s: afe lpass clock failed for port 0x%x , err:%d\n",
3731 __func__, port_id, ret);
3732 goto err;
3733 }
3734
3735err:
3736 return ret;
3737}
3738
3739#ifdef ENABLE_PINCTRL
3740static int msm_set_pinctrl(struct msm_pinctrl_info *pinctrl_info,
3741 enum pinctrl_pin_state new_state)
3742{
3743 int ret = 0;
3744 int curr_state = 0;
3745
3746 if (pinctrl_info == NULL) {
3747 pr_err("%s: pinctrl_info is NULL\n", __func__);
3748 ret = -EINVAL;
3749 goto err;
3750 }
3751
3752 if (pinctrl_info->pinctrl == NULL) {
3753 pr_err("%s: pinctrl_info->pinctrl is NULL\n", __func__);
3754 ret = -EINVAL;
3755 goto err;
3756 }
3757
3758 curr_state = pinctrl_info->curr_state;
3759 pinctrl_info->curr_state = new_state;
3760 pr_debug("%s: curr_state = %s new_state = %s\n", __func__,
3761 pin_states[curr_state], pin_states[pinctrl_info->curr_state]);
3762
3763 if (curr_state == pinctrl_info->curr_state) {
3764 pr_debug("%s: Already in same state\n", __func__);
3765 goto err;
3766 }
3767
3768 if (curr_state != STATE_DISABLE &&
3769 pinctrl_info->curr_state != STATE_DISABLE) {
3770 pr_debug("%s: state already active cannot switch\n", __func__);
3771 ret = -EIO;
3772 goto err;
3773 }
3774
3775 switch (pinctrl_info->curr_state) {
3776 case STATE_MI2S_ACTIVE:
3777 ret = pinctrl_select_state(pinctrl_info->pinctrl,
3778 pinctrl_info->mi2s_active);
3779 if (ret) {
3780 pr_err("%s: MI2S state select failed with %d\n",
3781 __func__, ret);
3782 ret = -EIO;
3783 goto err;
3784 }
3785 break;
3786 case STATE_TDM_ACTIVE:
3787 ret = pinctrl_select_state(pinctrl_info->pinctrl,
3788 pinctrl_info->tdm_active);
3789 if (ret) {
3790 pr_err("%s: TDM state select failed with %d\n",
3791 __func__, ret);
3792 ret = -EIO;
3793 goto err;
3794 }
3795 break;
3796 case STATE_DISABLE:
3797 if (curr_state == STATE_MI2S_ACTIVE) {
3798 ret = pinctrl_select_state(pinctrl_info->pinctrl,
3799 pinctrl_info->mi2s_disable);
3800 } else {
3801 ret = pinctrl_select_state(pinctrl_info->pinctrl,
3802 pinctrl_info->tdm_disable);
3803 }
3804 if (ret) {
3805 pr_err("%s: state disable failed with %d\n",
3806 __func__, ret);
3807 ret = -EIO;
3808 goto err;
3809 }
3810 break;
3811 default:
3812 pr_err("%s: TLMM pin state is invalid\n", __func__);
3813 return -EINVAL;
3814 }
3815
3816err:
3817 return ret;
3818}
3819
3820static void msm_release_pinctrl(struct platform_device *pdev)
3821{
3822 struct snd_soc_card *card = platform_get_drvdata(pdev);
3823 struct msm_asoc_mach_data *pdata = snd_soc_card_get_drvdata(card);
3824 struct msm_pinctrl_info *pinctrl_info = &pdata->pinctrl_info;
3825
3826 if (pinctrl_info->pinctrl) {
3827 devm_pinctrl_put(pinctrl_info->pinctrl);
3828 pinctrl_info->pinctrl = NULL;
3829 }
3830}
3831
3832static int msm_get_pinctrl(struct platform_device *pdev)
3833{
3834 struct snd_soc_card *card = platform_get_drvdata(pdev);
3835 struct msm_asoc_mach_data *pdata = snd_soc_card_get_drvdata(card);
3836 struct msm_pinctrl_info *pinctrl_info = NULL;
3837 struct pinctrl *pinctrl;
3838 int ret = 0;
3839
3840 pinctrl_info = &pdata->pinctrl_info;
3841
3842 if (pinctrl_info == NULL) {
3843 pr_err("%s: pinctrl_info is NULL\n", __func__);
3844 return -EINVAL;
3845 }
3846
3847 pinctrl = devm_pinctrl_get(&pdev->dev);
3848 if (IS_ERR_OR_NULL(pinctrl)) {
3849 pr_err("%s: Unable to get pinctrl handle\n", __func__);
3850 return -EINVAL;
3851 }
3852 pinctrl_info->pinctrl = pinctrl;
3853
3854 /* get all the states handles from Device Tree */
3855 pinctrl_info->mi2s_disable = pinctrl_lookup_state(pinctrl,
3856 "quat_mi2s_disable");
3857 if (IS_ERR(pinctrl_info->mi2s_disable)) {
3858 pr_err("%s: could not get mi2s_disable pinstate\n", __func__);
3859 goto err;
3860 }
3861 pinctrl_info->mi2s_active = pinctrl_lookup_state(pinctrl,
3862 "quat_mi2s_enable");
3863 if (IS_ERR(pinctrl_info->mi2s_active)) {
3864 pr_err("%s: could not get mi2s_active pinstate\n", __func__);
3865 goto err;
3866 }
3867 pinctrl_info->tdm_disable = pinctrl_lookup_state(pinctrl,
3868 "quat_tdm_disable");
3869 if (IS_ERR(pinctrl_info->tdm_disable)) {
3870 pr_err("%s: could not get tdm_disable pinstate\n", __func__);
3871 goto err;
3872 }
3873 pinctrl_info->tdm_active = pinctrl_lookup_state(pinctrl,
3874 "quat_tdm_enable");
3875 if (IS_ERR(pinctrl_info->tdm_active)) {
3876 pr_err("%s: could not get tdm_active pinstate\n",
3877 __func__);
3878 goto err;
3879 }
3880 /* Reset the TLMM pins to a default state */
3881 ret = pinctrl_select_state(pinctrl_info->pinctrl,
3882 pinctrl_info->mi2s_disable);
3883 if (ret != 0) {
3884 pr_err("%s: Disable TLMM pins failed with %d\n",
3885 __func__, ret);
3886 ret = -EIO;
3887 goto err;
3888 }
3889 pinctrl_info->curr_state = STATE_DISABLE;
3890
3891 return 0;
3892
3893err:
3894 devm_pinctrl_put(pinctrl);
3895 pinctrl_info->pinctrl = NULL;
3896 return -EINVAL;
3897}
3898#else
3899static int msm_set_pinctrl(struct msm_pinctrl_info *pinctrl_info,
3900 enum pinctrl_pin_state new_state)
3901{
3902 return 0;
3903}
3904
3905static void msm_release_pinctrl(struct platform_device *pdev)
3906{
3907 return;
3908}
3909
3910static int msm_get_pinctrl(struct platform_device *pdev)
3911{
3912 return 0;
3913}
3914#endif
3915
3916static int msm_tdm_be_hw_params_fixup(struct snd_soc_pcm_runtime *rtd,
3917 struct snd_pcm_hw_params *params)
3918{
3919 struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
3920 struct snd_interval *rate = hw_param_interval(params,
3921 SNDRV_PCM_HW_PARAM_RATE);
3922 struct snd_interval *channels = hw_param_interval(params,
3923 SNDRV_PCM_HW_PARAM_CHANNELS);
3924
3925 switch (cpu_dai->id) {
3926 case AFE_PORT_ID_PRIMARY_TDM_RX:
3927 channels->min = channels->max =
3928 tdm_rx_cfg[TDM_PRI][TDM_0].channels;
3929 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
3930 tdm_rx_cfg[TDM_PRI][TDM_0].bit_format);
3931 rate->min = rate->max =
3932 tdm_rx_cfg[TDM_PRI][TDM_0].sample_rate;
3933 break;
3934 case AFE_PORT_ID_PRIMARY_TDM_RX_1:
3935 channels->min = channels->max =
3936 tdm_rx_cfg[TDM_PRI][TDM_1].channels;
3937 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
3938 tdm_rx_cfg[TDM_PRI][TDM_1].bit_format);
3939 rate->min = rate->max =
3940 tdm_rx_cfg[TDM_PRI][TDM_1].sample_rate;
3941 break;
3942 case AFE_PORT_ID_PRIMARY_TDM_RX_2:
3943 channels->min = channels->max =
3944 tdm_rx_cfg[TDM_PRI][TDM_2].channels;
3945 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
3946 tdm_rx_cfg[TDM_PRI][TDM_2].bit_format);
3947 rate->min = rate->max =
3948 tdm_rx_cfg[TDM_PRI][TDM_2].sample_rate;
3949 break;
3950 case AFE_PORT_ID_PRIMARY_TDM_RX_3:
3951 channels->min = channels->max =
3952 tdm_rx_cfg[TDM_PRI][TDM_3].channels;
3953 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
3954 tdm_rx_cfg[TDM_PRI][TDM_3].bit_format);
3955 rate->min = rate->max =
3956 tdm_rx_cfg[TDM_PRI][TDM_3].sample_rate;
3957 break;
3958 case AFE_PORT_ID_PRIMARY_TDM_TX:
3959 channels->min = channels->max =
3960 tdm_tx_cfg[TDM_PRI][TDM_0].channels;
3961 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
3962 tdm_tx_cfg[TDM_PRI][TDM_0].bit_format);
3963 rate->min = rate->max =
3964 tdm_tx_cfg[TDM_PRI][TDM_0].sample_rate;
3965 break;
3966 case AFE_PORT_ID_PRIMARY_TDM_TX_1:
3967 channels->min = channels->max =
3968 tdm_tx_cfg[TDM_PRI][TDM_1].channels;
3969 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
3970 tdm_tx_cfg[TDM_PRI][TDM_1].bit_format);
3971 rate->min = rate->max =
3972 tdm_tx_cfg[TDM_PRI][TDM_1].sample_rate;
3973 break;
3974 case AFE_PORT_ID_PRIMARY_TDM_TX_2:
3975 channels->min = channels->max =
3976 tdm_tx_cfg[TDM_PRI][TDM_2].channels;
3977 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
3978 tdm_tx_cfg[TDM_PRI][TDM_2].bit_format);
3979 rate->min = rate->max =
3980 tdm_tx_cfg[TDM_PRI][TDM_2].sample_rate;
3981 break;
3982 case AFE_PORT_ID_PRIMARY_TDM_TX_3:
3983 channels->min = channels->max =
3984 tdm_tx_cfg[TDM_PRI][TDM_3].channels;
3985 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
3986 tdm_tx_cfg[TDM_PRI][TDM_3].bit_format);
3987 rate->min = rate->max =
3988 tdm_tx_cfg[TDM_PRI][TDM_3].sample_rate;
3989 break;
3990 case AFE_PORT_ID_SECONDARY_TDM_RX:
3991 channels->min = channels->max =
3992 tdm_rx_cfg[TDM_SEC][TDM_0].channels;
3993 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
3994 tdm_rx_cfg[TDM_SEC][TDM_0].bit_format);
3995 rate->min = rate->max =
3996 tdm_rx_cfg[TDM_SEC][TDM_0].sample_rate;
3997 break;
3998 case AFE_PORT_ID_SECONDARY_TDM_RX_1:
3999 channels->min = channels->max =
4000 tdm_rx_cfg[TDM_SEC][TDM_1].channels;
4001 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
4002 tdm_rx_cfg[TDM_SEC][TDM_1].bit_format);
4003 rate->min = rate->max =
4004 tdm_rx_cfg[TDM_SEC][TDM_1].sample_rate;
4005 break;
4006 case AFE_PORT_ID_SECONDARY_TDM_RX_2:
4007 channels->min = channels->max =
4008 tdm_rx_cfg[TDM_SEC][TDM_2].channels;
4009 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
4010 tdm_rx_cfg[TDM_SEC][TDM_2].bit_format);
4011 rate->min = rate->max =
4012 tdm_rx_cfg[TDM_SEC][TDM_2].sample_rate;
4013 break;
4014 case AFE_PORT_ID_SECONDARY_TDM_RX_3:
4015 channels->min = channels->max =
4016 tdm_rx_cfg[TDM_SEC][TDM_3].channels;
4017 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
4018 tdm_rx_cfg[TDM_SEC][TDM_3].bit_format);
4019 rate->min = rate->max =
4020 tdm_rx_cfg[TDM_SEC][TDM_3].sample_rate;
4021 break;
4022 case AFE_PORT_ID_SECONDARY_TDM_TX:
4023 channels->min = channels->max =
4024 tdm_tx_cfg[TDM_SEC][TDM_0].channels;
4025 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
4026 tdm_tx_cfg[TDM_SEC][TDM_0].bit_format);
4027 rate->min = rate->max =
4028 tdm_tx_cfg[TDM_SEC][TDM_0].sample_rate;
4029 break;
4030 case AFE_PORT_ID_SECONDARY_TDM_TX_1:
4031 channels->min = channels->max =
4032 tdm_tx_cfg[TDM_SEC][TDM_1].channels;
4033 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
4034 tdm_tx_cfg[TDM_SEC][TDM_1].bit_format);
4035 rate->min = rate->max =
4036 tdm_tx_cfg[TDM_SEC][TDM_1].sample_rate;
4037 break;
4038 case AFE_PORT_ID_SECONDARY_TDM_TX_2:
4039 channels->min = channels->max =
4040 tdm_tx_cfg[TDM_SEC][TDM_2].channels;
4041 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
4042 tdm_tx_cfg[TDM_SEC][TDM_2].bit_format);
4043 rate->min = rate->max =
4044 tdm_tx_cfg[TDM_SEC][TDM_2].sample_rate;
4045 break;
4046 case AFE_PORT_ID_SECONDARY_TDM_TX_3:
4047 channels->min = channels->max =
4048 tdm_tx_cfg[TDM_SEC][TDM_3].channels;
4049 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
4050 tdm_tx_cfg[TDM_SEC][TDM_3].bit_format);
4051 rate->min = rate->max =
4052 tdm_tx_cfg[TDM_SEC][TDM_3].sample_rate;
4053 break;
4054 case AFE_PORT_ID_TERTIARY_TDM_RX:
4055 channels->min = channels->max =
4056 tdm_rx_cfg[TDM_TERT][TDM_0].channels;
4057 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
4058 tdm_rx_cfg[TDM_TERT][TDM_0].bit_format);
4059 rate->min = rate->max =
4060 tdm_rx_cfg[TDM_TERT][TDM_0].sample_rate;
4061 break;
4062 case AFE_PORT_ID_TERTIARY_TDM_RX_1:
4063 channels->min = channels->max =
4064 tdm_rx_cfg[TDM_TERT][TDM_1].channels;
4065 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
4066 tdm_rx_cfg[TDM_TERT][TDM_1].bit_format);
4067 rate->min = rate->max =
4068 tdm_rx_cfg[TDM_TERT][TDM_1].sample_rate;
4069 break;
4070 case AFE_PORT_ID_TERTIARY_TDM_RX_2:
4071 channels->min = channels->max =
4072 tdm_rx_cfg[TDM_TERT][TDM_2].channels;
4073 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
4074 tdm_rx_cfg[TDM_TERT][TDM_2].bit_format);
4075 rate->min = rate->max =
4076 tdm_rx_cfg[TDM_TERT][TDM_2].sample_rate;
4077 break;
4078 case AFE_PORT_ID_TERTIARY_TDM_RX_3:
4079 channels->min = channels->max =
4080 tdm_rx_cfg[TDM_TERT][TDM_3].channels;
4081 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
4082 tdm_rx_cfg[TDM_TERT][TDM_3].bit_format);
4083 rate->min = rate->max =
4084 tdm_rx_cfg[TDM_TERT][TDM_3].sample_rate;
4085 break;
4086 case AFE_PORT_ID_TERTIARY_TDM_RX_4:
4087 channels->min = channels->max =
4088 tdm_rx_cfg[TDM_TERT][TDM_4].channels;
4089 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
4090 tdm_rx_cfg[TDM_TERT][TDM_4].bit_format);
4091 rate->min = rate->max =
4092 tdm_rx_cfg[TDM_TERT][TDM_4].sample_rate;
4093 break;
4094 case AFE_PORT_ID_TERTIARY_TDM_TX:
4095 channels->min = channels->max =
4096 tdm_tx_cfg[TDM_TERT][TDM_0].channels;
4097 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
4098 tdm_tx_cfg[TDM_TERT][TDM_0].bit_format);
4099 rate->min = rate->max =
4100 tdm_tx_cfg[TDM_TERT][TDM_0].sample_rate;
4101 break;
4102 case AFE_PORT_ID_TERTIARY_TDM_TX_1:
4103 channels->min = channels->max =
4104 tdm_tx_cfg[TDM_TERT][TDM_1].channels;
4105 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
4106 tdm_tx_cfg[TDM_TERT][TDM_1].bit_format);
4107 rate->min = rate->max =
4108 tdm_tx_cfg[TDM_TERT][TDM_1].sample_rate;
4109 break;
4110 case AFE_PORT_ID_TERTIARY_TDM_TX_2:
4111 channels->min = channels->max =
4112 tdm_tx_cfg[TDM_TERT][TDM_2].channels;
4113 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
4114 tdm_tx_cfg[TDM_TERT][TDM_2].bit_format);
4115 rate->min = rate->max =
4116 tdm_tx_cfg[TDM_TERT][TDM_2].sample_rate;
4117 break;
4118 case AFE_PORT_ID_TERTIARY_TDM_TX_3:
4119 channels->min = channels->max =
4120 tdm_tx_cfg[TDM_TERT][TDM_3].channels;
4121 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
4122 tdm_tx_cfg[TDM_TERT][TDM_3].bit_format);
4123 rate->min = rate->max =
4124 tdm_tx_cfg[TDM_TERT][TDM_3].sample_rate;
4125 break;
4126 case AFE_PORT_ID_QUATERNARY_TDM_RX:
4127 channels->min = channels->max =
4128 tdm_rx_cfg[TDM_QUAT][TDM_0].channels;
4129 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
4130 tdm_rx_cfg[TDM_QUAT][TDM_0].bit_format);
4131 rate->min = rate->max =
4132 tdm_rx_cfg[TDM_QUAT][TDM_0].sample_rate;
4133 break;
4134 case AFE_PORT_ID_QUATERNARY_TDM_RX_1:
4135 channels->min = channels->max =
4136 tdm_rx_cfg[TDM_QUAT][TDM_1].channels;
4137 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
4138 tdm_rx_cfg[TDM_QUAT][TDM_1].bit_format);
4139 rate->min = rate->max =
4140 tdm_rx_cfg[TDM_QUAT][TDM_1].sample_rate;
4141 break;
4142 case AFE_PORT_ID_QUATERNARY_TDM_RX_2:
4143 channels->min = channels->max =
4144 tdm_rx_cfg[TDM_QUAT][TDM_2].channels;
4145 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
4146 tdm_rx_cfg[TDM_QUAT][TDM_2].bit_format);
4147 rate->min = rate->max =
4148 tdm_rx_cfg[TDM_QUAT][TDM_2].sample_rate;
4149 break;
4150 case AFE_PORT_ID_QUATERNARY_TDM_RX_3:
4151 channels->min = channels->max =
4152 tdm_rx_cfg[TDM_QUAT][TDM_3].channels;
4153 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
4154 tdm_rx_cfg[TDM_QUAT][TDM_3].bit_format);
4155 rate->min = rate->max =
4156 tdm_rx_cfg[TDM_QUAT][TDM_3].sample_rate;
4157 break;
4158 case AFE_PORT_ID_QUATERNARY_TDM_TX:
4159 channels->min = channels->max =
4160 tdm_tx_cfg[TDM_QUAT][TDM_0].channels;
4161 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
4162 tdm_tx_cfg[TDM_QUAT][TDM_0].bit_format);
4163 rate->min = rate->max =
4164 tdm_tx_cfg[TDM_QUAT][TDM_0].sample_rate;
4165 break;
4166 case AFE_PORT_ID_QUATERNARY_TDM_TX_1:
4167 channels->min = channels->max =
4168 tdm_tx_cfg[TDM_QUAT][TDM_1].channels;
4169 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
4170 tdm_tx_cfg[TDM_QUAT][TDM_1].bit_format);
4171 rate->min = rate->max =
4172 tdm_tx_cfg[TDM_QUAT][TDM_1].sample_rate;
4173 break;
4174 case AFE_PORT_ID_QUATERNARY_TDM_TX_2:
4175 channels->min = channels->max =
4176 tdm_tx_cfg[TDM_QUAT][TDM_2].channels;
4177 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
4178 tdm_tx_cfg[TDM_QUAT][TDM_2].bit_format);
4179 rate->min = rate->max =
4180 tdm_tx_cfg[TDM_QUAT][TDM_2].sample_rate;
4181 break;
4182 case AFE_PORT_ID_QUATERNARY_TDM_TX_3:
4183 channels->min = channels->max =
4184 tdm_tx_cfg[TDM_QUAT][TDM_3].channels;
4185 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
4186 tdm_tx_cfg[TDM_QUAT][TDM_3].bit_format);
4187 rate->min = rate->max =
4188 tdm_tx_cfg[TDM_QUAT][TDM_3].sample_rate;
4189 break;
4190 case AFE_PORT_ID_QUINARY_TDM_RX:
4191 channels->min = channels->max =
4192 tdm_rx_cfg[TDM_QUIN][TDM_0].channels;
4193 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
4194 tdm_rx_cfg[TDM_QUIN][TDM_0].bit_format);
4195 rate->min = rate->max =
4196 tdm_rx_cfg[TDM_QUIN][TDM_0].sample_rate;
4197 break;
4198 case AFE_PORT_ID_QUINARY_TDM_RX_1:
4199 channels->min = channels->max =
4200 tdm_rx_cfg[TDM_QUIN][TDM_1].channels;
4201 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
4202 tdm_rx_cfg[TDM_QUIN][TDM_1].bit_format);
4203 rate->min = rate->max =
4204 tdm_rx_cfg[TDM_QUIN][TDM_1].sample_rate;
4205 break;
4206 case AFE_PORT_ID_QUINARY_TDM_RX_2:
4207 channels->min = channels->max =
4208 tdm_rx_cfg[TDM_QUIN][TDM_2].channels;
4209 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
4210 tdm_rx_cfg[TDM_QUIN][TDM_2].bit_format);
4211 rate->min = rate->max =
4212 tdm_rx_cfg[TDM_QUIN][TDM_2].sample_rate;
4213 break;
4214 case AFE_PORT_ID_QUINARY_TDM_RX_3:
4215 channels->min = channels->max =
4216 tdm_rx_cfg[TDM_QUIN][TDM_3].channels;
4217 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
4218 tdm_rx_cfg[TDM_QUIN][TDM_3].bit_format);
4219 rate->min = rate->max =
4220 tdm_rx_cfg[TDM_QUIN][TDM_3].sample_rate;
4221 break;
4222 case AFE_PORT_ID_QUINARY_TDM_TX:
4223 channels->min = channels->max =
4224 tdm_tx_cfg[TDM_QUIN][TDM_0].channels;
4225 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
4226 tdm_tx_cfg[TDM_QUIN][TDM_0].bit_format);
4227 rate->min = rate->max =
4228 tdm_tx_cfg[TDM_QUIN][TDM_0].sample_rate;
4229 break;
4230 case AFE_PORT_ID_QUINARY_TDM_TX_1:
4231 channels->min = channels->max =
4232 tdm_tx_cfg[TDM_QUIN][TDM_1].channels;
4233 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
4234 tdm_tx_cfg[TDM_QUIN][TDM_1].bit_format);
4235 rate->min = rate->max =
4236 tdm_tx_cfg[TDM_QUIN][TDM_1].sample_rate;
4237 break;
4238 case AFE_PORT_ID_QUINARY_TDM_TX_2:
4239 channels->min = channels->max =
4240 tdm_tx_cfg[TDM_QUIN][TDM_2].channels;
4241 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
4242 tdm_tx_cfg[TDM_QUIN][TDM_2].bit_format);
4243 rate->min = rate->max =
4244 tdm_tx_cfg[TDM_QUIN][TDM_2].sample_rate;
4245 break;
4246 case AFE_PORT_ID_QUINARY_TDM_TX_3:
4247 channels->min = channels->max =
4248 tdm_tx_cfg[TDM_QUIN][TDM_3].channels;
4249 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
4250 tdm_tx_cfg[TDM_QUIN][TDM_3].bit_format);
4251 rate->min = rate->max =
4252 tdm_tx_cfg[TDM_QUIN][TDM_3].sample_rate;
4253 break;
4254 default:
4255 pr_err("%s: dai id 0x%x not supported\n",
4256 __func__, cpu_dai->id);
4257 return -EINVAL;
4258 }
4259
4260 pr_debug("%s: dai id = 0x%x channels = %d rate = %d format = 0x%x\n",
4261 __func__, cpu_dai->id, channels->max, rate->max,
4262 params_format(params));
4263
4264 return 0;
4265}
4266
4267static unsigned int tdm_param_set_slot_mask(int slots)
4268{
4269 unsigned int slot_mask = 0;
4270 int i = 0;
4271
4272 if ((slots <= 0) || (slots > 32)) {
4273 pr_err("%s: invalid slot number %d\n", __func__, slots);
4274 return -EINVAL;
4275 }
4276
4277 for (i = 0; i < slots ; i++)
4278 slot_mask |= 1 << i;
4279 return slot_mask;
4280}
4281
4282static int sa6155_tdm_snd_hw_params(struct snd_pcm_substream *substream,
4283 struct snd_pcm_hw_params *params)
4284{
4285 struct snd_soc_pcm_runtime *rtd = substream->private_data;
4286 struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
4287 int ret = 0;
4288 int channels, slot_width, slots, rate, format;
4289 unsigned int slot_mask;
4290 unsigned int *slot_offset;
4291 int offset_channels = 0;
4292 int i;
4293 int clk_freq;
4294
4295 pr_debug("%s: dai id = 0x%x\n", __func__, cpu_dai->id);
4296
4297 channels = params_channels(params);
4298 if (channels < 1 || channels > 32) {
4299 pr_err("%s: invalid param channels %d\n",
4300 __func__, channels);
4301 return -EINVAL;
4302 }
4303
4304 format = params_format(params);
4305 if (format != SNDRV_PCM_FORMAT_S32_LE &&
4306 format != SNDRV_PCM_FORMAT_S24_LE &&
4307 format != SNDRV_PCM_FORMAT_S16_LE) {
4308 /*
4309 * Up to 8 channel HW configuration should
4310 * use 32 bit slot width for max support of
4311 * stream bit width. (slot_width > bit_width)
4312 */
4313 pr_err("%s: invalid param format 0x%x\n",
4314 __func__, format);
4315 return -EINVAL;
4316 }
4317
4318 switch (cpu_dai->id) {
4319 case AFE_PORT_ID_PRIMARY_TDM_RX:
4320 slots = tdm_slot[TDM_PRI].num;
4321 slot_width = tdm_slot[TDM_PRI].width;
4322 slot_offset = tdm_rx_slot_offset[TDM_PRI][TDM_0];
4323 break;
4324 case AFE_PORT_ID_PRIMARY_TDM_RX_1:
4325 slots = tdm_slot[TDM_PRI].num;
4326 slot_width = tdm_slot[TDM_PRI].width;
4327 slot_offset = tdm_rx_slot_offset[TDM_PRI][TDM_1];
4328 break;
4329 case AFE_PORT_ID_PRIMARY_TDM_RX_2:
4330 slots = tdm_slot[TDM_PRI].num;
4331 slot_width = tdm_slot[TDM_PRI].width;
4332 slot_offset = tdm_rx_slot_offset[TDM_PRI][TDM_2];
4333 break;
4334 case AFE_PORT_ID_PRIMARY_TDM_RX_3:
4335 slots = tdm_slot[TDM_PRI].num;
4336 slot_width = tdm_slot[TDM_PRI].width;
4337 slot_offset = tdm_rx_slot_offset[TDM_PRI][TDM_3];
4338 break;
4339 case AFE_PORT_ID_PRIMARY_TDM_TX:
4340 slots = tdm_slot[TDM_PRI].num;
4341 slot_width = tdm_slot[TDM_PRI].width;
4342 slot_offset = tdm_tx_slot_offset[TDM_PRI][TDM_0];
4343 break;
4344 case AFE_PORT_ID_PRIMARY_TDM_TX_1:
4345 slots = tdm_slot[TDM_PRI].num;
4346 slot_width = tdm_slot[TDM_PRI].width;
4347 slot_offset = tdm_tx_slot_offset[TDM_PRI][TDM_1];
4348 break;
4349 case AFE_PORT_ID_PRIMARY_TDM_TX_2:
4350 slots = tdm_slot[TDM_PRI].num;
4351 slot_width = tdm_slot[TDM_PRI].width;
4352 slot_offset = tdm_tx_slot_offset[TDM_PRI][TDM_2];
4353 break;
4354 case AFE_PORT_ID_PRIMARY_TDM_TX_3:
4355 slots = tdm_slot[TDM_PRI].num;
4356 slot_width = tdm_slot[TDM_PRI].width;
4357 slot_offset = tdm_tx_slot_offset[TDM_PRI][TDM_3];
4358 break;
4359 case AFE_PORT_ID_SECONDARY_TDM_RX:
4360 slots = tdm_slot[TDM_SEC].num;
4361 slot_width = tdm_slot[TDM_SEC].width;
4362 slot_offset = tdm_rx_slot_offset[TDM_SEC][TDM_0];
4363 break;
4364 case AFE_PORT_ID_SECONDARY_TDM_RX_1:
4365 slots = tdm_slot[TDM_SEC].num;
4366 slot_width = tdm_slot[TDM_SEC].width;
4367 slot_offset = tdm_rx_slot_offset[TDM_SEC][TDM_1];
4368 break;
4369 case AFE_PORT_ID_SECONDARY_TDM_RX_2:
4370 slots = tdm_slot[TDM_SEC].num;
4371 slot_width = tdm_slot[TDM_SEC].width;
4372 slot_offset = tdm_rx_slot_offset[TDM_SEC][TDM_2];
4373 break;
4374 case AFE_PORT_ID_SECONDARY_TDM_RX_3:
4375 slots = tdm_slot[TDM_SEC].num;
4376 slot_width = tdm_slot[TDM_SEC].width;
4377 slot_offset = tdm_rx_slot_offset[TDM_SEC][TDM_3];
4378 break;
4379 case AFE_PORT_ID_SECONDARY_TDM_TX:
4380 slots = tdm_slot[TDM_SEC].num;
4381 slot_width = tdm_slot[TDM_SEC].width;
4382 slot_offset = tdm_tx_slot_offset[TDM_SEC][TDM_0];
4383 break;
4384 case AFE_PORT_ID_SECONDARY_TDM_TX_1:
4385 slots = tdm_slot[TDM_SEC].num;
4386 slot_width = tdm_slot[TDM_SEC].width;
4387 slot_offset = tdm_tx_slot_offset[TDM_SEC][TDM_1];
4388 break;
4389 case AFE_PORT_ID_SECONDARY_TDM_TX_2:
4390 slots = tdm_slot[TDM_SEC].num;
4391 slot_width = tdm_slot[TDM_SEC].width;
4392 slot_offset = tdm_tx_slot_offset[TDM_SEC][TDM_2];
4393 break;
4394 case AFE_PORT_ID_SECONDARY_TDM_TX_3:
4395 slots = tdm_slot[TDM_SEC].num;
4396 slot_width = tdm_slot[TDM_SEC].width;
4397 slot_offset = tdm_tx_slot_offset[TDM_SEC][TDM_3];
4398 break;
4399 case AFE_PORT_ID_TERTIARY_TDM_RX:
4400 slots = tdm_slot[TDM_TERT].num;
4401 slot_width = tdm_slot[TDM_TERT].width;
4402 slot_offset = tdm_rx_slot_offset[TDM_TERT][TDM_0];
4403 break;
4404 case AFE_PORT_ID_TERTIARY_TDM_RX_1:
4405 slots = tdm_slot[TDM_TERT].num;
4406 slot_width = tdm_slot[TDM_TERT].width;
4407 slot_offset = tdm_rx_slot_offset[TDM_TERT][TDM_1];
4408 break;
4409 case AFE_PORT_ID_TERTIARY_TDM_RX_2:
4410 slots = tdm_slot[TDM_TERT].num;
4411 slot_width = tdm_slot[TDM_TERT].width;
4412 slot_offset = tdm_rx_slot_offset[TDM_TERT][TDM_2];
4413 break;
4414 case AFE_PORT_ID_TERTIARY_TDM_RX_3:
4415 slots = tdm_slot[TDM_TERT].num;
4416 slot_width = tdm_slot[TDM_TERT].width;
4417 slot_offset = tdm_rx_slot_offset[TDM_TERT][TDM_3];
4418 break;
4419 case AFE_PORT_ID_TERTIARY_TDM_RX_4:
4420 slots = tdm_slot[TDM_TERT].num;
4421 slot_width = tdm_slot[TDM_TERT].width;
4422 slot_offset = tdm_rx_slot_offset[TDM_TERT][TDM_4];
4423 break;
4424 case AFE_PORT_ID_TERTIARY_TDM_TX:
4425 slots = tdm_slot[TDM_TERT].num;
4426 slot_width = tdm_slot[TDM_TERT].width;
4427 slot_offset = tdm_tx_slot_offset[TDM_TERT][TDM_0];
4428 break;
4429 case AFE_PORT_ID_TERTIARY_TDM_TX_1:
4430 slots = tdm_slot[TDM_TERT].num;
4431 slot_width = tdm_slot[TDM_TERT].width;
4432 slot_offset = tdm_tx_slot_offset[TDM_TERT][TDM_1];
4433 break;
4434 case AFE_PORT_ID_TERTIARY_TDM_TX_2:
4435 slots = tdm_slot[TDM_TERT].num;
4436 slot_width = tdm_slot[TDM_TERT].width;
4437 slot_offset = tdm_tx_slot_offset[TDM_TERT][TDM_2];
4438 break;
4439 case AFE_PORT_ID_TERTIARY_TDM_TX_3:
4440 slots = tdm_slot[TDM_TERT].num;
4441 slot_width = tdm_slot[TDM_TERT].width;
4442 slot_offset = tdm_tx_slot_offset[TDM_TERT][TDM_3];
4443 break;
4444 case AFE_PORT_ID_QUATERNARY_TDM_RX:
4445 slots = tdm_slot[TDM_QUAT].num;
4446 slot_width = tdm_slot[TDM_QUAT].width;
4447 slot_offset = tdm_rx_slot_offset[TDM_QUAT][TDM_0];
4448 break;
4449 case AFE_PORT_ID_QUATERNARY_TDM_RX_1:
4450 slots = tdm_slot[TDM_QUAT].num;
4451 slot_width = tdm_slot[TDM_QUAT].width;
4452 slot_offset = tdm_rx_slot_offset[TDM_QUAT][TDM_1];
4453 break;
4454 case AFE_PORT_ID_QUATERNARY_TDM_RX_2:
4455 slots = tdm_slot[TDM_QUAT].num;
4456 slot_width = tdm_slot[TDM_QUAT].width;
4457 slot_offset = tdm_rx_slot_offset[TDM_QUAT][TDM_2];
4458 break;
4459 case AFE_PORT_ID_QUATERNARY_TDM_RX_3:
4460 slots = tdm_slot[TDM_QUAT].num;
4461 slot_width = tdm_slot[TDM_QUAT].width;
4462 slot_offset = tdm_rx_slot_offset[TDM_QUAT][TDM_3];
4463 break;
4464 case AFE_PORT_ID_QUATERNARY_TDM_TX:
4465 slots = tdm_slot[TDM_QUAT].num;
4466 slot_width = tdm_slot[TDM_QUAT].width;
4467 slot_offset = tdm_tx_slot_offset[TDM_QUAT][TDM_0];
4468 break;
4469 case AFE_PORT_ID_QUATERNARY_TDM_TX_1:
4470 slots = tdm_slot[TDM_QUAT].num;
4471 slot_width = tdm_slot[TDM_QUAT].width;
4472 slot_offset = tdm_tx_slot_offset[TDM_QUAT][TDM_1];
4473 break;
4474 case AFE_PORT_ID_QUATERNARY_TDM_TX_2:
4475 slots = tdm_slot[TDM_QUAT].num;
4476 slot_width = tdm_slot[TDM_QUAT].width;
4477 slot_offset = tdm_tx_slot_offset[TDM_QUAT][TDM_2];
4478 break;
4479 case AFE_PORT_ID_QUATERNARY_TDM_TX_3:
4480 slots = tdm_slot[TDM_QUAT].num;
4481 slot_width = tdm_slot[TDM_QUAT].width;
4482 slot_offset = tdm_tx_slot_offset[TDM_QUAT][TDM_3];
4483 break;
4484 case AFE_PORT_ID_QUINARY_TDM_RX:
4485 slots = tdm_slot[TDM_QUIN].num;
4486 slot_width = tdm_slot[TDM_QUIN].width;
4487 slot_offset = tdm_rx_slot_offset[TDM_QUIN][TDM_0];
4488 break;
4489 case AFE_PORT_ID_QUINARY_TDM_RX_1:
4490 slots = tdm_slot[TDM_QUIN].num;
4491 slot_width = tdm_slot[TDM_QUIN].width;
4492 slot_offset = tdm_rx_slot_offset[TDM_QUIN][TDM_1];
4493 break;
4494 case AFE_PORT_ID_QUINARY_TDM_RX_2:
4495 slots = tdm_slot[TDM_QUIN].num;
4496 slot_width = tdm_slot[TDM_QUIN].width;
4497 slot_offset = tdm_rx_slot_offset[TDM_QUIN][TDM_2];
4498 break;
4499 case AFE_PORT_ID_QUINARY_TDM_RX_3:
4500 slots = tdm_slot[TDM_QUIN].num;
4501 slot_width = tdm_slot[TDM_QUIN].width;
4502 slot_offset = tdm_rx_slot_offset[TDM_QUIN][TDM_3];
4503 break;
4504 case AFE_PORT_ID_QUINARY_TDM_TX:
4505 slots = tdm_slot[TDM_QUIN].num;
4506 slot_width = tdm_slot[TDM_QUIN].width;
4507 slot_offset = tdm_tx_slot_offset[TDM_QUIN][TDM_0];
4508 break;
4509 case AFE_PORT_ID_QUINARY_TDM_TX_1:
4510 slots = tdm_slot[TDM_QUIN].num;
4511 slot_width = tdm_slot[TDM_QUIN].width;
4512 slot_offset = tdm_tx_slot_offset[TDM_QUIN][TDM_1];
4513 break;
4514 case AFE_PORT_ID_QUINARY_TDM_TX_2:
4515 slots = tdm_slot[TDM_QUIN].num;
4516 slot_width = tdm_slot[TDM_QUIN].width;
4517 slot_offset = tdm_tx_slot_offset[TDM_QUIN][TDM_2];
4518 break;
4519 case AFE_PORT_ID_QUINARY_TDM_TX_3:
4520 slots = tdm_slot[TDM_QUIN].num;
4521 slot_width = tdm_slot[TDM_QUIN].width;
4522 slot_offset = tdm_tx_slot_offset[TDM_QUIN][TDM_3];
4523 break;
4524 default:
4525 pr_err("%s: dai id 0x%x not supported\n",
4526 __func__, cpu_dai->id);
4527 return -EINVAL;
4528 }
4529
4530 for (i = 0; i < TDM_SLOT_OFFSET_MAX; i++) {
4531 if (slot_offset[i] != AFE_SLOT_MAPPING_OFFSET_INVALID)
4532 offset_channels++;
4533 else
4534 break;
4535 }
4536
4537 if (offset_channels == 0) {
4538 pr_err("%s: invalid offset_channels %d\n",
4539 __func__, offset_channels);
4540 return -EINVAL;
4541 }
4542
4543 if (channels > offset_channels) {
4544 pr_err("%s: channels %d exceed offset_channels %d\n",
4545 __func__, channels, offset_channels);
4546 return -EINVAL;
4547 }
4548
4549 slot_mask = tdm_param_set_slot_mask(slots);
4550 if (!slot_mask) {
4551 pr_err("%s: invalid slot_mask 0x%x\n",
4552 __func__, slot_mask);
4553 return -EINVAL;
4554 }
4555
4556 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
4557 ret = snd_soc_dai_set_tdm_slot(cpu_dai, 0, slot_mask,
4558 slots, slot_width);
4559 if (ret < 0) {
4560 pr_err("%s: failed to set tdm slot, err:%d\n",
4561 __func__, ret);
4562 goto end;
4563 }
4564
4565 ret = snd_soc_dai_set_channel_map(cpu_dai,
4566 0, NULL, channels, slot_offset);
4567 if (ret < 0) {
4568 pr_err("%s: failed to set channel map, err:%d\n",
4569 __func__, ret);
4570 goto end;
4571 }
4572 } else if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) {
4573 ret = snd_soc_dai_set_tdm_slot(cpu_dai, slot_mask, 0,
4574 slots, slot_width);
4575 if (ret < 0) {
4576 pr_err("%s: failed to set tdm slot, err:%d\n",
4577 __func__, ret);
4578 goto end;
4579 }
4580
4581 ret = snd_soc_dai_set_channel_map(cpu_dai,
4582 channels, slot_offset, 0, NULL);
4583 if (ret < 0) {
4584 pr_err("%s: failed to set channel map, err:%d\n",
4585 __func__, ret);
4586 goto end;
4587 }
4588 } else {
4589 ret = -EINVAL;
4590 pr_err("%s: invalid use case, err:%d\n",
4591 __func__, ret);
4592 goto end;
4593 }
4594
4595 rate = params_rate(params);
4596 clk_freq = rate * slot_width * slots;
4597 ret = snd_soc_dai_set_sysclk(cpu_dai, 0, clk_freq, SND_SOC_CLOCK_OUT);
4598 if (ret < 0)
4599 pr_err("%s: failed to set tdm clk, err:%d\n",
4600 __func__, ret);
4601
4602end:
4603 return ret;
4604}
4605
4606static int sa6155_tdm_snd_startup(struct snd_pcm_substream *substream)
4607{
4608 int ret = 0;
4609 struct snd_soc_pcm_runtime *rtd = substream->private_data;
4610 struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
4611 struct snd_soc_card *card = rtd->card;
4612 struct msm_asoc_mach_data *pdata = snd_soc_card_get_drvdata(card);
4613 struct msm_pinctrl_info *pinctrl_info = &pdata->pinctrl_info;
4614
4615 /* currently only supporting TDM_RX_0 and TDM_TX_0 */
4616 if ((cpu_dai->id == AFE_PORT_ID_QUATERNARY_TDM_RX) ||
4617 (cpu_dai->id == AFE_PORT_ID_QUATERNARY_TDM_TX)) {
4618 ret = msm_set_pinctrl(pinctrl_info, STATE_TDM_ACTIVE);
4619 if (ret)
4620 pr_err("%s: TDM TLMM pinctrl set failed with %d\n",
4621 __func__, ret);
4622 }
4623
4624 return ret;
4625}
4626
4627static void sa6155_tdm_snd_shutdown(struct snd_pcm_substream *substream)
4628{
4629 int ret = 0;
4630 struct snd_soc_pcm_runtime *rtd = substream->private_data;
4631 struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
4632 struct snd_soc_card *card = rtd->card;
4633 struct msm_asoc_mach_data *pdata = snd_soc_card_get_drvdata(card);
4634 struct msm_pinctrl_info *pinctrl_info = &pdata->pinctrl_info;
4635
4636 /* currently only supporting TDM_RX_0 and TDM_TX_0 */
4637 if ((cpu_dai->id == AFE_PORT_ID_QUATERNARY_TDM_RX) ||
4638 (cpu_dai->id == AFE_PORT_ID_QUATERNARY_TDM_TX)) {
4639 ret = msm_set_pinctrl(pinctrl_info, STATE_DISABLE);
4640 if (ret)
4641 pr_err("%s: TDM TLMM pinctrl set failed with %d\n",
4642 __func__, ret);
4643 }
4644}
4645
4646static struct snd_soc_ops sa6155_tdm_be_ops = {
4647 .hw_params = sa6155_tdm_snd_hw_params,
4648 .startup = sa6155_tdm_snd_startup,
4649 .shutdown = sa6155_tdm_snd_shutdown
4650};
4651
4652static int msm_fe_qos_prepare(struct snd_pcm_substream *substream)
4653{
4654 cpumask_t mask;
4655
4656 if (pm_qos_request_active(&substream->latency_pm_qos_req))
4657 pm_qos_remove_request(&substream->latency_pm_qos_req);
4658
4659 cpumask_clear(&mask);
4660 cpumask_set_cpu(1, &mask); /* affine to core 1 */
4661 cpumask_set_cpu(2, &mask); /* affine to core 2 */
4662 cpumask_copy(&substream->latency_pm_qos_req.cpus_affine, &mask);
4663
4664 substream->latency_pm_qos_req.type = PM_QOS_REQ_AFFINE_CORES;
4665
4666 pm_qos_add_request(&substream->latency_pm_qos_req,
4667 PM_QOS_CPU_DMA_LATENCY,
4668 MSM_LL_QOS_VALUE);
4669 return 0;
4670}
4671
4672static struct snd_soc_ops msm_fe_qos_ops = {
4673 .prepare = msm_fe_qos_prepare,
4674};
4675
4676static int msm_mi2s_snd_startup(struct snd_pcm_substream *substream)
4677{
4678 int ret = 0;
4679 struct snd_soc_pcm_runtime *rtd = substream->private_data;
4680 struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
4681 int index = cpu_dai->id;
4682 unsigned int fmt = SND_SOC_DAIFMT_CBS_CFS;
4683 struct snd_soc_card *card = rtd->card;
4684 struct msm_asoc_mach_data *pdata = snd_soc_card_get_drvdata(card);
4685 struct msm_pinctrl_info *pinctrl_info = &pdata->pinctrl_info;
4686 int ret_pinctrl = 0;
4687
4688 dev_dbg(rtd->card->dev,
4689 "%s: substream = %s stream = %d, dai name %s, dai ID %d\n",
4690 __func__, substream->name, substream->stream,
4691 cpu_dai->name, cpu_dai->id);
4692
4693 if (index < PRIM_MI2S || index >= MI2S_MAX) {
4694 ret = -EINVAL;
4695 dev_err(rtd->card->dev,
4696 "%s: CPU DAI id (%d) out of range\n",
4697 __func__, cpu_dai->id);
4698 goto err;
4699 }
4700 /*
4701 * Mutex protection in case the same MI2S
4702 * interface using for both TX and RX so
4703 * that the same clock won't be enable twice.
4704 */
4705 mutex_lock(&mi2s_intf_conf[index].lock);
4706 if (++mi2s_intf_conf[index].ref_cnt == 1) {
4707 /* Check if msm needs to provide the clock to the interface */
4708 if (!mi2s_intf_conf[index].msm_is_mi2s_master) {
4709 mi2s_clk[index].clk_id = mi2s_ebit_clk[index];
4710 fmt = SND_SOC_DAIFMT_CBM_CFM;
4711 }
4712 ret = msm_mi2s_set_sclk(substream, true);
4713 if (ret < 0) {
4714 dev_err(rtd->card->dev,
4715 "%s: afe lpass clock failed to enable MI2S clock, err:%d\n",
4716 __func__, ret);
4717 goto clean_up;
4718 }
4719
4720 ret = snd_soc_dai_set_fmt(cpu_dai, fmt);
4721 if (ret < 0) {
4722 pr_err("%s: set fmt cpu dai failed for MI2S (%d), err:%d\n",
4723 __func__, index, ret);
4724 goto clk_off;
4725 }
4726 if (index == QUAT_MI2S) {
4727 ret_pinctrl = msm_set_pinctrl(pinctrl_info,
4728 STATE_MI2S_ACTIVE);
4729 if (ret_pinctrl)
4730 pr_err("%s: MI2S TLMM pinctrl set failed with %d\n",
4731 __func__, ret_pinctrl);
4732 }
4733 }
4734clk_off:
4735 if (ret < 0)
4736 msm_mi2s_set_sclk(substream, false);
4737clean_up:
4738 if (ret < 0)
4739 mi2s_intf_conf[index].ref_cnt--;
4740 mutex_unlock(&mi2s_intf_conf[index].lock);
4741err:
4742 return ret;
4743}
4744
4745static void msm_mi2s_snd_shutdown(struct snd_pcm_substream *substream)
4746{
4747 int ret;
4748 struct snd_soc_pcm_runtime *rtd = substream->private_data;
4749 int index = rtd->cpu_dai->id;
4750 struct snd_soc_card *card = rtd->card;
4751 struct msm_asoc_mach_data *pdata = snd_soc_card_get_drvdata(card);
4752 struct msm_pinctrl_info *pinctrl_info = &pdata->pinctrl_info;
4753 int ret_pinctrl = 0;
4754
4755 pr_debug("%s(): substream = %s stream = %d\n", __func__,
4756 substream->name, substream->stream);
4757 if (index < PRIM_MI2S || index >= MI2S_MAX) {
4758 pr_err("%s:invalid MI2S DAI(%d)\n", __func__, index);
4759 return;
4760 }
4761
4762 mutex_lock(&mi2s_intf_conf[index].lock);
4763 if (--mi2s_intf_conf[index].ref_cnt == 0) {
4764 ret = msm_mi2s_set_sclk(substream, false);
4765 if (ret < 0)
4766 pr_err("%s:clock disable failed for MI2S (%d); ret=%d\n",
4767 __func__, index, ret);
4768 if (index == QUAT_MI2S) {
4769 ret_pinctrl = msm_set_pinctrl(pinctrl_info,
4770 STATE_DISABLE);
4771 if (ret_pinctrl)
4772 pr_err("%s: MI2S TLMM pinctrl set failed with %d\n",
4773 __func__, ret_pinctrl);
4774 }
4775 }
4776 mutex_unlock(&mi2s_intf_conf[index].lock);
4777}
4778
4779static struct snd_soc_ops msm_mi2s_be_ops = {
4780 .startup = msm_mi2s_snd_startup,
4781 .shutdown = msm_mi2s_snd_shutdown,
4782};
4783
4784
4785/* Digital audio interface glue - connects codec <---> CPU */
4786static struct snd_soc_dai_link msm_common_dai_links[] = {
4787 /* FrontEnd DAI Links */
4788 {
4789 .name = MSM_DAILINK_NAME(Media1),
4790 .stream_name = "MultiMedia1",
4791 .cpu_dai_name = "MultiMedia1",
4792 .platform_name = "msm-pcm-dsp.0",
4793 .dynamic = 1,
4794 .async_ops = ASYNC_DPCM_SND_SOC_PREPARE,
4795 .dpcm_playback = 1,
4796 .dpcm_capture = 1,
4797 .trigger = {SND_SOC_DPCM_TRIGGER_POST,
4798 SND_SOC_DPCM_TRIGGER_POST},
4799 .codec_dai_name = "snd-soc-dummy-dai",
4800 .codec_name = "snd-soc-dummy",
4801 .ignore_suspend = 1,
4802 /* this dainlink has playback support */
4803 .ignore_pmdown_time = 1,
4804 .id = MSM_FRONTEND_DAI_MULTIMEDIA1
4805 },
4806 {
4807 .name = MSM_DAILINK_NAME(Media2),
4808 .stream_name = "MultiMedia2",
4809 .cpu_dai_name = "MultiMedia2",
4810 .platform_name = "msm-pcm-dsp.0",
4811 .dynamic = 1,
4812 .dpcm_playback = 1,
4813 .dpcm_capture = 1,
4814 .codec_dai_name = "snd-soc-dummy-dai",
4815 .codec_name = "snd-soc-dummy",
4816 .trigger = {SND_SOC_DPCM_TRIGGER_POST,
4817 SND_SOC_DPCM_TRIGGER_POST},
4818 .ignore_suspend = 1,
4819 /* this dainlink has playback support */
4820 .ignore_pmdown_time = 1,
4821 .id = MSM_FRONTEND_DAI_MULTIMEDIA2,
4822 },
4823 {
4824 .name = "VoiceMMode1",
4825 .stream_name = "VoiceMMode1",
4826 .cpu_dai_name = "VoiceMMode1",
4827 .platform_name = "msm-pcm-voice",
4828 .dynamic = 1,
4829 .dpcm_playback = 1,
4830 .dpcm_capture = 1,
4831 .trigger = {SND_SOC_DPCM_TRIGGER_POST,
4832 SND_SOC_DPCM_TRIGGER_POST},
4833 .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
4834 .ignore_suspend = 1,
4835 .ignore_pmdown_time = 1,
4836 .codec_dai_name = "snd-soc-dummy-dai",
4837 .codec_name = "snd-soc-dummy",
4838 .id = MSM_FRONTEND_DAI_VOICEMMODE1,
4839 },
4840 {
4841 .name = "MSM VoIP",
4842 .stream_name = "VoIP",
4843 .cpu_dai_name = "VoIP",
4844 .platform_name = "msm-voip-dsp",
4845 .dynamic = 1,
4846 .dpcm_playback = 1,
4847 .dpcm_capture = 1,
4848 .trigger = {SND_SOC_DPCM_TRIGGER_POST,
4849 SND_SOC_DPCM_TRIGGER_POST},
4850 .codec_dai_name = "snd-soc-dummy-dai",
4851 .codec_name = "snd-soc-dummy",
4852 .ignore_suspend = 1,
4853 /* this dainlink has playback support */
4854 .ignore_pmdown_time = 1,
4855 .id = MSM_FRONTEND_DAI_VOIP,
4856 },
4857 {
4858 .name = MSM_DAILINK_NAME(ULL),
4859 .stream_name = "MultiMedia3",
4860 .cpu_dai_name = "MultiMedia3",
4861 .platform_name = "msm-pcm-dsp.2",
4862 .dynamic = 1,
4863 .async_ops = ASYNC_DPCM_SND_SOC_PREPARE,
4864 .dpcm_playback = 1,
4865 .trigger = {SND_SOC_DPCM_TRIGGER_POST,
4866 SND_SOC_DPCM_TRIGGER_POST},
4867 .codec_dai_name = "snd-soc-dummy-dai",
4868 .codec_name = "snd-soc-dummy",
4869 .ignore_suspend = 1,
4870 /* this dainlink has playback support */
4871 .ignore_pmdown_time = 1,
4872 .id = MSM_FRONTEND_DAI_MULTIMEDIA3,
4873 },
4874 /* - SLIMBUS_0 Hostless */
4875 {
4876 .name = "MSM AFE-PCM RX",
4877 .stream_name = "AFE-PROXY RX",
4878 .cpu_dai_name = "msm-dai-q6-dev.241",
4879 .codec_name = "msm-stub-codec.1",
4880 .codec_dai_name = "msm-stub-rx",
4881 .platform_name = "msm-pcm-afe",
4882 .dpcm_playback = 1,
4883 .ignore_suspend = 1,
4884 /* this dainlink has playback support */
4885 .ignore_pmdown_time = 1,
4886 },
4887 {
4888 .name = "MSM AFE-PCM TX",
4889 .stream_name = "AFE-PROXY TX",
4890 .cpu_dai_name = "msm-dai-q6-dev.240",
4891 .codec_name = "msm-stub-codec.1",
4892 .codec_dai_name = "msm-stub-tx",
4893 .platform_name = "msm-pcm-afe",
4894 .dpcm_capture = 1,
4895 .ignore_suspend = 1,
4896 },
4897 {
4898 .name = MSM_DAILINK_NAME(Compress1),
4899 .stream_name = "Compress1",
4900 .cpu_dai_name = "MultiMedia4",
4901 .platform_name = "msm-compress-dsp",
4902 .dynamic = 1,
4903 .async_ops = ASYNC_DPCM_SND_SOC_HW_PARAMS,
4904 .dpcm_playback = 1,
4905 .dpcm_capture = 1,
4906 .trigger = {SND_SOC_DPCM_TRIGGER_POST,
4907 SND_SOC_DPCM_TRIGGER_POST},
4908 .codec_dai_name = "snd-soc-dummy-dai",
4909 .codec_name = "snd-soc-dummy",
4910 .ignore_suspend = 1,
4911 .ignore_pmdown_time = 1,
4912 /* this dainlink has playback support */
4913 .id = MSM_FRONTEND_DAI_MULTIMEDIA4,
4914 },
4915 /* Hostless PCM purpose */
4916 {
4917 .name = "AUXPCM Hostless",
4918 .stream_name = "AUXPCM Hostless",
4919 .cpu_dai_name = "AUXPCM_HOSTLESS",
4920 .platform_name = "msm-pcm-hostless",
4921 .dynamic = 1,
4922 .dpcm_playback = 1,
4923 .dpcm_capture = 1,
4924 .trigger = {SND_SOC_DPCM_TRIGGER_POST,
4925 SND_SOC_DPCM_TRIGGER_POST},
4926 .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
4927 .ignore_suspend = 1,
4928 /* this dainlink has playback support */
4929 .ignore_pmdown_time = 1,
4930 .codec_dai_name = "snd-soc-dummy-dai",
4931 .codec_name = "snd-soc-dummy",
4932 },
4933 /* - SLIMBUS_1 Hostless */
4934 /* - SLIMBUS_3 Hostless */
4935 /* - SLIMBUS_4 Hostless */
4936 {
4937 .name = MSM_DAILINK_NAME(LowLatency),
4938 .stream_name = "MultiMedia5",
4939 .cpu_dai_name = "MultiMedia5",
4940 .platform_name = "msm-pcm-dsp.1",
4941 .dynamic = 1,
4942 .async_ops = ASYNC_DPCM_SND_SOC_PREPARE,
4943 .dpcm_playback = 1,
4944 .dpcm_capture = 1,
4945 .codec_dai_name = "snd-soc-dummy-dai",
4946 .codec_name = "snd-soc-dummy",
4947 .trigger = {SND_SOC_DPCM_TRIGGER_POST,
4948 SND_SOC_DPCM_TRIGGER_POST},
4949 .ignore_suspend = 1,
4950 /* this dainlink has playback support */
4951 .ignore_pmdown_time = 1,
4952 .id = MSM_FRONTEND_DAI_MULTIMEDIA5,
4953 .ops = &msm_fe_qos_ops,
4954 },
4955 {
4956 .name = "Listen 1 Audio Service",
4957 .stream_name = "Listen 1 Audio Service",
4958 .cpu_dai_name = "LSM1",
4959 .platform_name = "msm-lsm-client",
4960 .dynamic = 1,
4961 .dpcm_capture = 1,
4962 .trigger = { SND_SOC_DPCM_TRIGGER_POST,
4963 SND_SOC_DPCM_TRIGGER_POST },
4964 .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
4965 .ignore_suspend = 1,
4966 .codec_dai_name = "snd-soc-dummy-dai",
4967 .codec_name = "snd-soc-dummy",
4968 .id = MSM_FRONTEND_DAI_LSM1,
4969 },
4970 /* Multiple Tunnel instances */
4971 {
4972 .name = MSM_DAILINK_NAME(Compress2),
4973 .stream_name = "Compress2",
4974 .cpu_dai_name = "MultiMedia7",
4975 .platform_name = "msm-compress-dsp",
4976 .dynamic = 1,
4977 .dpcm_playback = 1,
4978 .trigger = {SND_SOC_DPCM_TRIGGER_POST,
4979 SND_SOC_DPCM_TRIGGER_POST},
4980 .codec_dai_name = "snd-soc-dummy-dai",
4981 .codec_name = "snd-soc-dummy",
4982 .ignore_suspend = 1,
4983 .ignore_pmdown_time = 1,
4984 /* this dainlink has playback support */
4985 .id = MSM_FRONTEND_DAI_MULTIMEDIA7,
4986 },
4987 {
4988 .name = MSM_DAILINK_NAME(MultiMedia10),
4989 .stream_name = "MultiMedia10",
4990 .cpu_dai_name = "MultiMedia10",
4991 .platform_name = "msm-pcm-dsp.1",
4992 .dynamic = 1,
4993 .dpcm_playback = 1,
4994 .dpcm_capture = 1,
4995 .trigger = {SND_SOC_DPCM_TRIGGER_POST,
4996 SND_SOC_DPCM_TRIGGER_POST},
4997 .codec_dai_name = "snd-soc-dummy-dai",
4998 .codec_name = "snd-soc-dummy",
4999 .ignore_suspend = 1,
5000 .ignore_pmdown_time = 1,
5001 /* this dainlink has playback support */
5002 .id = MSM_FRONTEND_DAI_MULTIMEDIA10,
5003 },
5004 {
5005 .name = MSM_DAILINK_NAME(ULL_NOIRQ),
5006 .stream_name = "MM_NOIRQ",
5007 .cpu_dai_name = "MultiMedia8",
5008 .platform_name = "msm-pcm-dsp-noirq",
5009 .dynamic = 1,
5010 .dpcm_playback = 1,
5011 .dpcm_capture = 1,
5012 .trigger = {SND_SOC_DPCM_TRIGGER_POST,
5013 SND_SOC_DPCM_TRIGGER_POST},
5014 .codec_dai_name = "snd-soc-dummy-dai",
5015 .codec_name = "snd-soc-dummy",
5016 .ignore_suspend = 1,
5017 .ignore_pmdown_time = 1,
5018 /* this dainlink has playback support */
5019 .id = MSM_FRONTEND_DAI_MULTIMEDIA8,
5020 .ops = &msm_fe_qos_ops,
5021 },
5022 /* HDMI Hostless */
5023 {
5024 .name = "HDMI_RX_HOSTLESS",
5025 .stream_name = "HDMI_RX_HOSTLESS",
5026 .cpu_dai_name = "HDMI_HOSTLESS",
5027 .platform_name = "msm-pcm-hostless",
5028 .dynamic = 1,
5029 .dpcm_playback = 1,
5030 .trigger = {SND_SOC_DPCM_TRIGGER_POST,
5031 SND_SOC_DPCM_TRIGGER_POST},
5032 .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
5033 .ignore_suspend = 1,
5034 .ignore_pmdown_time = 1,
5035 .codec_dai_name = "snd-soc-dummy-dai",
5036 .codec_name = "snd-soc-dummy",
5037 },
5038 {
5039 .name = "VoiceMMode2",
5040 .stream_name = "VoiceMMode2",
5041 .cpu_dai_name = "VoiceMMode2",
5042 .platform_name = "msm-pcm-voice",
5043 .dynamic = 1,
5044 .dpcm_playback = 1,
5045 .dpcm_capture = 1,
5046 .trigger = {SND_SOC_DPCM_TRIGGER_POST,
5047 SND_SOC_DPCM_TRIGGER_POST},
5048 .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
5049 .ignore_suspend = 1,
5050 .ignore_pmdown_time = 1,
5051 .codec_dai_name = "snd-soc-dummy-dai",
5052 .codec_name = "snd-soc-dummy",
5053 .id = MSM_FRONTEND_DAI_VOICEMMODE2,
5054 },
5055 /* LSM FE */
5056 {
5057 .name = "Listen 2 Audio Service",
5058 .stream_name = "Listen 2 Audio Service",
5059 .cpu_dai_name = "LSM2",
5060 .platform_name = "msm-lsm-client",
5061 .dynamic = 1,
5062 .dpcm_capture = 1,
5063 .trigger = { SND_SOC_DPCM_TRIGGER_POST,
5064 SND_SOC_DPCM_TRIGGER_POST },
5065 .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
5066 .ignore_suspend = 1,
5067 .codec_dai_name = "snd-soc-dummy-dai",
5068 .codec_name = "snd-soc-dummy",
5069 .id = MSM_FRONTEND_DAI_LSM2,
5070 },
5071 {
5072 .name = "Listen 3 Audio Service",
5073 .stream_name = "Listen 3 Audio Service",
5074 .cpu_dai_name = "LSM3",
5075 .platform_name = "msm-lsm-client",
5076 .dynamic = 1,
5077 .dpcm_capture = 1,
5078 .trigger = { SND_SOC_DPCM_TRIGGER_POST,
5079 SND_SOC_DPCM_TRIGGER_POST },
5080 .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
5081 .ignore_suspend = 1,
5082 .codec_dai_name = "snd-soc-dummy-dai",
5083 .codec_name = "snd-soc-dummy",
5084 .id = MSM_FRONTEND_DAI_LSM3,
5085 },
5086 {
5087 .name = "Listen 4 Audio Service",
5088 .stream_name = "Listen 4 Audio Service",
5089 .cpu_dai_name = "LSM4",
5090 .platform_name = "msm-lsm-client",
5091 .dynamic = 1,
5092 .dpcm_capture = 1,
5093 .trigger = { SND_SOC_DPCM_TRIGGER_POST,
5094 SND_SOC_DPCM_TRIGGER_POST },
5095 .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
5096 .ignore_suspend = 1,
5097 .codec_dai_name = "snd-soc-dummy-dai",
5098 .codec_name = "snd-soc-dummy",
5099 .id = MSM_FRONTEND_DAI_LSM4,
5100 },
5101 {
5102 .name = "Listen 5 Audio Service",
5103 .stream_name = "Listen 5 Audio Service",
5104 .cpu_dai_name = "LSM5",
5105 .platform_name = "msm-lsm-client",
5106 .dynamic = 1,
5107 .dpcm_capture = 1,
5108 .trigger = { SND_SOC_DPCM_TRIGGER_POST,
5109 SND_SOC_DPCM_TRIGGER_POST },
5110 .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
5111 .ignore_suspend = 1,
5112 .codec_dai_name = "snd-soc-dummy-dai",
5113 .codec_name = "snd-soc-dummy",
5114 .id = MSM_FRONTEND_DAI_LSM5,
5115 },
5116 {
5117 .name = "Listen 6 Audio Service",
5118 .stream_name = "Listen 6 Audio Service",
5119 .cpu_dai_name = "LSM6",
5120 .platform_name = "msm-lsm-client",
5121 .dynamic = 1,
5122 .dpcm_capture = 1,
5123 .trigger = { SND_SOC_DPCM_TRIGGER_POST,
5124 SND_SOC_DPCM_TRIGGER_POST },
5125 .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
5126 .ignore_suspend = 1,
5127 .codec_dai_name = "snd-soc-dummy-dai",
5128 .codec_name = "snd-soc-dummy",
5129 .id = MSM_FRONTEND_DAI_LSM6,
5130 },
5131 {
5132 .name = "Listen 7 Audio Service",
5133 .stream_name = "Listen 7 Audio Service",
5134 .cpu_dai_name = "LSM7",
5135 .platform_name = "msm-lsm-client",
5136 .dynamic = 1,
5137 .dpcm_capture = 1,
5138 .trigger = { SND_SOC_DPCM_TRIGGER_POST,
5139 SND_SOC_DPCM_TRIGGER_POST },
5140 .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
5141 .ignore_suspend = 1,
5142 .codec_dai_name = "snd-soc-dummy-dai",
5143 .codec_name = "snd-soc-dummy",
5144 .id = MSM_FRONTEND_DAI_LSM7,
5145 },
5146 {
5147 .name = "Listen 8 Audio Service",
5148 .stream_name = "Listen 8 Audio Service",
5149 .cpu_dai_name = "LSM8",
5150 .platform_name = "msm-lsm-client",
5151 .dynamic = 1,
5152 .dpcm_capture = 1,
5153 .trigger = { SND_SOC_DPCM_TRIGGER_POST,
5154 SND_SOC_DPCM_TRIGGER_POST },
5155 .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
5156 .ignore_suspend = 1,
5157 .codec_dai_name = "snd-soc-dummy-dai",
5158 .codec_name = "snd-soc-dummy",
5159 .id = MSM_FRONTEND_DAI_LSM8,
5160 },
5161 /* - Multimedia9 */
5162 {
5163 .name = MSM_DAILINK_NAME(Compress4),
5164 .stream_name = "Compress4",
5165 .cpu_dai_name = "MultiMedia11",
5166 .platform_name = "msm-compress-dsp",
5167 .dynamic = 1,
5168 .dpcm_playback = 1,
5169 .trigger = {SND_SOC_DPCM_TRIGGER_POST,
5170 SND_SOC_DPCM_TRIGGER_POST},
5171 .codec_dai_name = "snd-soc-dummy-dai",
5172 .codec_name = "snd-soc-dummy",
5173 .ignore_suspend = 1,
5174 .ignore_pmdown_time = 1,
5175 /* this dainlink has playback support */
5176 .id = MSM_FRONTEND_DAI_MULTIMEDIA11,
5177 },
5178 {
5179 .name = MSM_DAILINK_NAME(Compress5),
5180 .stream_name = "Compress5",
5181 .cpu_dai_name = "MultiMedia12",
5182 .platform_name = "msm-compress-dsp",
5183 .dynamic = 1,
5184 .dpcm_playback = 1,
5185 .trigger = {SND_SOC_DPCM_TRIGGER_POST,
5186 SND_SOC_DPCM_TRIGGER_POST},
5187 .codec_dai_name = "snd-soc-dummy-dai",
5188 .codec_name = "snd-soc-dummy",
5189 .ignore_suspend = 1,
5190 .ignore_pmdown_time = 1,
5191 /* this dainlink has playback support */
5192 .id = MSM_FRONTEND_DAI_MULTIMEDIA12,
5193 },
5194 {
5195 .name = MSM_DAILINK_NAME(Compress6),
5196 .stream_name = "Compress6",
5197 .cpu_dai_name = "MultiMedia13",
5198 .platform_name = "msm-compress-dsp",
5199 .dynamic = 1,
5200 .dpcm_playback = 1,
5201 .trigger = {SND_SOC_DPCM_TRIGGER_POST,
5202 SND_SOC_DPCM_TRIGGER_POST},
5203 .codec_dai_name = "snd-soc-dummy-dai",
5204 .codec_name = "snd-soc-dummy",
5205 .ignore_suspend = 1,
5206 .ignore_pmdown_time = 1,
5207 /* this dainlink has playback support */
5208 .id = MSM_FRONTEND_DAI_MULTIMEDIA13,
5209 },
5210 {
5211 .name = MSM_DAILINK_NAME(Compress7),
5212 .stream_name = "Compress7",
5213 .cpu_dai_name = "MultiMedia14",
5214 .platform_name = "msm-compress-dsp",
5215 .dynamic = 1,
5216 .dpcm_playback = 1,
5217 .trigger = {SND_SOC_DPCM_TRIGGER_POST,
5218 SND_SOC_DPCM_TRIGGER_POST},
5219 .codec_dai_name = "snd-soc-dummy-dai",
5220 .codec_name = "snd-soc-dummy",
5221 .ignore_suspend = 1,
5222 .ignore_pmdown_time = 1,
5223 /* this dainlink has playback support */
5224 .id = MSM_FRONTEND_DAI_MULTIMEDIA14,
5225 },
5226 {
5227 .name = MSM_DAILINK_NAME(Compress8),
5228 .stream_name = "Compress8",
5229 .cpu_dai_name = "MultiMedia15",
5230 .platform_name = "msm-compress-dsp",
5231 .dynamic = 1,
5232 .dpcm_playback = 1,
5233 .trigger = {SND_SOC_DPCM_TRIGGER_POST,
5234 SND_SOC_DPCM_TRIGGER_POST},
5235 .codec_dai_name = "snd-soc-dummy-dai",
5236 .codec_name = "snd-soc-dummy",
5237 .ignore_suspend = 1,
5238 .ignore_pmdown_time = 1,
5239 /* this dainlink has playback support */
5240 .id = MSM_FRONTEND_DAI_MULTIMEDIA15,
5241 },
5242 {
5243 .name = MSM_DAILINK_NAME(ULL_NOIRQ_2),
5244 .stream_name = "MM_NOIRQ_2",
5245 .cpu_dai_name = "MultiMedia16",
5246 .platform_name = "msm-pcm-dsp-noirq",
5247 .dynamic = 1,
5248 .dpcm_playback = 1,
5249 .dpcm_capture = 1,
5250 .trigger = {SND_SOC_DPCM_TRIGGER_POST,
5251 SND_SOC_DPCM_TRIGGER_POST},
5252 .codec_dai_name = "snd-soc-dummy-dai",
5253 .codec_name = "snd-soc-dummy",
5254 .ignore_suspend = 1,
5255 .ignore_pmdown_time = 1,
5256 /* this dainlink has playback support */
5257 .id = MSM_FRONTEND_DAI_MULTIMEDIA16,
5258 },
5259 /* - SLIMBUS_8 Hostless */
5260 /* - Slimbus4 Capture */
5261 /* - SLIMBUS_2 Hostless Playback */
5262 /* - SLIMBUS_2 Hostless Capture */
5263 /* HFP TX */
5264 {
5265 .name = MSM_DAILINK_NAME(ASM Loopback),
5266 .stream_name = "MultiMedia6",
5267 .cpu_dai_name = "MultiMedia6",
5268 .platform_name = "msm-pcm-loopback",
5269 .dynamic = 1,
5270 .dpcm_playback = 1,
5271 .dpcm_capture = 1,
5272 .codec_dai_name = "snd-soc-dummy-dai",
5273 .codec_name = "snd-soc-dummy",
5274 .trigger = {SND_SOC_DPCM_TRIGGER_POST,
5275 SND_SOC_DPCM_TRIGGER_POST},
5276 .ignore_suspend = 1,
5277 .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
5278 .ignore_pmdown_time = 1,
5279 .id = MSM_FRONTEND_DAI_MULTIMEDIA6,
5280 },
5281 {
5282 .name = "USB Audio Hostless",
5283 .stream_name = "USB Audio Hostless",
5284 .cpu_dai_name = "USBAUDIO_HOSTLESS",
5285 .platform_name = "msm-pcm-hostless",
5286 .dynamic = 1,
5287 .dpcm_playback = 1,
5288 .dpcm_capture = 1,
5289 .trigger = {SND_SOC_DPCM_TRIGGER_POST,
5290 SND_SOC_DPCM_TRIGGER_POST},
5291 .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
5292 .ignore_suspend = 1,
5293 .ignore_pmdown_time = 1,
5294 .codec_dai_name = "snd-soc-dummy-dai",
5295 .codec_name = "snd-soc-dummy",
5296 },
5297 /* - SLIMBUS_7 Hostless */
5298 {
5299 .name = "Compress Capture",
5300 .stream_name = "Compress9",
5301 .cpu_dai_name = "MultiMedia17",
5302 .platform_name = "msm-compress-dsp",
5303 .dynamic = 1,
5304 .dpcm_capture = 1,
5305 .trigger = {SND_SOC_DPCM_TRIGGER_POST,
5306 SND_SOC_DPCM_TRIGGER_POST},
5307 .codec_dai_name = "snd-soc-dummy-dai",
5308 .codec_name = "snd-soc-dummy",
5309 .ignore_suspend = 1,
5310 .ignore_pmdown_time = 1,
5311 .id = MSM_FRONTEND_DAI_MULTIMEDIA17,
5312 },
5313};
5314
5315static struct snd_soc_dai_link msm_auto_fe_dai_links[] = {
5316 {
5317 .name = "INT_HFP_BT Hostless",
5318 .stream_name = "INT_HFP_BT Hostless",
5319 .cpu_dai_name = "INT_HFP_BT_HOSTLESS",
5320 .platform_name = "msm-pcm-hostless",
5321 .dynamic = 1,
5322 .dpcm_playback = 1,
5323 .dpcm_capture = 1,
5324 .trigger = {SND_SOC_DPCM_TRIGGER_POST,
5325 SND_SOC_DPCM_TRIGGER_POST},
5326 .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
5327 .ignore_suspend = 1,
5328 /* this dainlink has playback support */
5329 .ignore_pmdown_time = 1,
5330 .codec_dai_name = "snd-soc-dummy-dai",
5331 .codec_name = "snd-soc-dummy",
5332 },
5333 /* Low latency ASM loopback for ICC */
5334 {
5335 .name = MSM_DAILINK_NAME(LowLatency Loopback),
5336 .stream_name = "MultiMedia9",
5337 .cpu_dai_name = "MultiMedia9",
5338 .platform_name = "msm-pcm-loopback.1",
5339 .dynamic = 1,
5340 .dpcm_playback = 1,
5341 .dpcm_capture = 1,
5342 .trigger = {SND_SOC_DPCM_TRIGGER_POST,
5343 SND_SOC_DPCM_TRIGGER_POST},
5344 .codec_dai_name = "snd-soc-dummy-dai",
5345 .codec_name = "snd-soc-dummy",
5346 .ignore_suspend = 1,
5347 .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
5348 /* this dainlink has playback support */
5349 .ignore_pmdown_time = 1,
5350 .id = MSM_FRONTEND_DAI_MULTIMEDIA9,
5351 },
5352 {
5353 .name = "Tertiary MI2S TX_Hostless",
5354 .stream_name = "Tertiary MI2S_TX Hostless Capture",
5355 .cpu_dai_name = "TERT_MI2S_TX_HOSTLESS",
5356 .platform_name = "msm-pcm-hostless",
5357 .dynamic = 1,
5358 .dpcm_capture = 1,
5359 .trigger = {SND_SOC_DPCM_TRIGGER_POST,
5360 SND_SOC_DPCM_TRIGGER_POST},
5361 .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
5362 .ignore_suspend = 1,
5363 .ignore_pmdown_time = 1,
5364 .codec_dai_name = "snd-soc-dummy-dai",
5365 .codec_name = "snd-soc-dummy",
5366 },
5367 {
5368 .name = MSM_DAILINK_NAME(Media20),
5369 .stream_name = "MultiMedia20",
5370 .cpu_dai_name = "MultiMedia20",
5371 .platform_name = "msm-pcm-loopback",
5372 .dynamic = 1,
5373 .dpcm_playback = 1,
5374 .dpcm_capture = 1,
5375 .trigger = {SND_SOC_DPCM_TRIGGER_POST,
5376 SND_SOC_DPCM_TRIGGER_POST},
5377 .codec_dai_name = "snd-soc-dummy-dai",
5378 .codec_name = "snd-soc-dummy",
5379 .ignore_suspend = 1,
5380 .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
5381 /* this dainlink has playback support */
5382 .ignore_pmdown_time = 1,
5383 .id = MSM_FRONTEND_DAI_MULTIMEDIA20,
5384 },
5385 {
5386 .name = MSM_DAILINK_NAME(HFP RX),
5387 .stream_name = "MultiMedia21",
5388 .cpu_dai_name = "MultiMedia21",
5389 .platform_name = "msm-pcm-loopback",
5390 .dynamic = 1,
5391 .dpcm_playback = 1,
5392 .dpcm_capture = 1,
5393 .codec_dai_name = "snd-soc-dummy-dai",
5394 .codec_name = "snd-soc-dummy",
5395 .trigger = {SND_SOC_DPCM_TRIGGER_POST,
5396 SND_SOC_DPCM_TRIGGER_POST},
5397 .ignore_suspend = 1,
5398 .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
5399 .ignore_pmdown_time = 1,
5400 .id = MSM_FRONTEND_DAI_MULTIMEDIA21,
5401 },
5402 /* TDM Hostless */
5403 {
5404 .name = "Primary TDM RX 0 Hostless",
5405 .stream_name = "Primary TDM RX 0 Hostless",
5406 .cpu_dai_name = "PRI_TDM_RX_0_HOSTLESS",
5407 .platform_name = "msm-pcm-hostless",
5408 .dynamic = 1,
5409 .dpcm_playback = 1,
5410 .trigger = {SND_SOC_DPCM_TRIGGER_POST,
5411 SND_SOC_DPCM_TRIGGER_POST},
5412 .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
5413 .ignore_suspend = 1,
5414 .ignore_pmdown_time = 1,
5415 .codec_dai_name = "snd-soc-dummy-dai",
5416 .codec_name = "snd-soc-dummy",
5417 },
5418 {
5419 .name = "Primary TDM TX 0 Hostless",
5420 .stream_name = "Primary TDM TX 0 Hostless",
5421 .cpu_dai_name = "PRI_TDM_TX_0_HOSTLESS",
5422 .platform_name = "msm-pcm-hostless",
5423 .dynamic = 1,
5424 .dpcm_capture = 1,
5425 .trigger = {SND_SOC_DPCM_TRIGGER_POST,
5426 SND_SOC_DPCM_TRIGGER_POST},
5427 .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
5428 .ignore_suspend = 1,
5429 .ignore_pmdown_time = 1,
5430 .codec_dai_name = "snd-soc-dummy-dai",
5431 .codec_name = "snd-soc-dummy",
5432 },
5433 {
5434 .name = "Secondary TDM RX 0 Hostless",
5435 .stream_name = "Secondary TDM RX 0 Hostless",
5436 .cpu_dai_name = "SEC_TDM_RX_0_HOSTLESS",
5437 .platform_name = "msm-pcm-hostless",
5438 .dynamic = 1,
5439 .dpcm_playback = 1,
5440 .trigger = {SND_SOC_DPCM_TRIGGER_POST,
5441 SND_SOC_DPCM_TRIGGER_POST},
5442 .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
5443 .ignore_suspend = 1,
5444 .ignore_pmdown_time = 1,
5445 .codec_dai_name = "snd-soc-dummy-dai",
5446 .codec_name = "snd-soc-dummy",
5447 },
5448 {
5449 .name = "Secondary TDM TX 0 Hostless",
5450 .stream_name = "Secondary TDM TX 0 Hostless",
5451 .cpu_dai_name = "SEC_TDM_TX_0_HOSTLESS",
5452 .platform_name = "msm-pcm-hostless",
5453 .dynamic = 1,
5454 .dpcm_capture = 1,
5455 .trigger = {SND_SOC_DPCM_TRIGGER_POST,
5456 SND_SOC_DPCM_TRIGGER_POST},
5457 .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
5458 .ignore_suspend = 1,
5459 .ignore_pmdown_time = 1,
5460 .codec_dai_name = "snd-soc-dummy-dai",
5461 .codec_name = "snd-soc-dummy",
5462 },
5463 {
5464 .name = "Tertiary TDM RX 0 Hostless",
5465 .stream_name = "Tertiary TDM RX 0 Hostless",
5466 .cpu_dai_name = "TERT_TDM_RX_0_HOSTLESS",
5467 .platform_name = "msm-pcm-hostless",
5468 .dynamic = 1,
5469 .dpcm_playback = 1,
5470 .trigger = {SND_SOC_DPCM_TRIGGER_POST,
5471 SND_SOC_DPCM_TRIGGER_POST},
5472 .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
5473 .ignore_suspend = 1,
5474 .ignore_pmdown_time = 1,
5475 .codec_dai_name = "snd-soc-dummy-dai",
5476 .codec_name = "snd-soc-dummy",
5477 },
5478 {
5479 .name = "Tertiary TDM TX 0 Hostless",
5480 .stream_name = "Tertiary TDM TX 0 Hostless",
5481 .cpu_dai_name = "TERT_TDM_TX_0_HOSTLESS",
5482 .platform_name = "msm-pcm-hostless",
5483 .dynamic = 1,
5484 .dpcm_capture = 1,
5485 .trigger = {SND_SOC_DPCM_TRIGGER_POST,
5486 SND_SOC_DPCM_TRIGGER_POST},
5487 .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
5488 .ignore_suspend = 1,
5489 .ignore_pmdown_time = 1,
5490 .codec_dai_name = "snd-soc-dummy-dai",
5491 .codec_name = "snd-soc-dummy",
5492 },
5493 {
5494 .name = "Quaternary TDM RX 0 Hostless",
5495 .stream_name = "Quaternary TDM RX 0 Hostless",
5496 .cpu_dai_name = "QUAT_TDM_RX_0_HOSTLESS",
5497 .platform_name = "msm-pcm-hostless",
5498 .dynamic = 1,
5499 .dpcm_playback = 1,
5500 .trigger = {SND_SOC_DPCM_TRIGGER_POST,
5501 SND_SOC_DPCM_TRIGGER_POST},
5502 .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
5503 .ignore_suspend = 1,
5504 .ignore_pmdown_time = 1,
5505 .codec_dai_name = "snd-soc-dummy-dai",
5506 .codec_name = "snd-soc-dummy",
5507 },
5508 {
5509 .name = "Quaternary TDM TX 0 Hostless",
5510 .stream_name = "Quaternary TDM TX 0 Hostless",
5511 .cpu_dai_name = "QUAT_TDM_TX_0_HOSTLESS",
5512 .platform_name = "msm-pcm-hostless",
5513 .dynamic = 1,
5514 .dpcm_capture = 1,
5515 .trigger = {SND_SOC_DPCM_TRIGGER_POST,
5516 SND_SOC_DPCM_TRIGGER_POST},
5517 .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
5518 .ignore_suspend = 1,
5519 .ignore_pmdown_time = 1,
5520 .codec_dai_name = "snd-soc-dummy-dai",
5521 .codec_name = "snd-soc-dummy",
5522 },
5523 {
5524 .name = "Quaternary MI2S_RX Hostless Playback",
5525 .stream_name = "Quaternary MI2S_RX Hostless Playback",
5526 .cpu_dai_name = "QUAT_MI2S_RX_HOSTLESS",
5527 .platform_name = "msm-pcm-hostless",
5528 .dynamic = 1,
5529 .dpcm_playback = 1,
5530 .trigger = {SND_SOC_DPCM_TRIGGER_POST,
5531 SND_SOC_DPCM_TRIGGER_POST},
5532 .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
5533 .ignore_suspend = 1,
5534 .ignore_pmdown_time = 1,
5535 .codec_dai_name = "snd-soc-dummy-dai",
5536 .codec_name = "snd-soc-dummy",
5537 },
5538 {
5539 .name = "Secondary MI2S_TX Hostless Capture",
5540 .stream_name = "Secondary MI2S_TX Hostless Capture",
5541 .cpu_dai_name = "SEC_MI2S_TX_HOSTLESS",
5542 .platform_name = "msm-pcm-hostless",
5543 .dynamic = 1,
5544 .dpcm_capture = 1,
5545 .trigger = {SND_SOC_DPCM_TRIGGER_POST,
5546 SND_SOC_DPCM_TRIGGER_POST},
5547 .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
5548 .ignore_suspend = 1,
5549 .ignore_pmdown_time = 1,
5550 .codec_dai_name = "snd-soc-dummy-dai",
5551 .codec_name = "snd-soc-dummy",
5552 },
5553 {
5554 .name = "DTMF RX Hostless",
5555 .stream_name = "DTMF RX Hostless",
5556 .cpu_dai_name = "DTMF_RX_HOSTLESS",
5557 .platform_name = "msm-pcm-dtmf",
5558 .dynamic = 1,
5559 .dpcm_playback = 1,
5560 .trigger = {SND_SOC_DPCM_TRIGGER_POST,
5561 SND_SOC_DPCM_TRIGGER_POST},
5562 .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
5563 .ignore_suspend = 1,
5564 .ignore_pmdown_time = 1,
5565 .codec_dai_name = "snd-soc-dummy-dai",
5566 .codec_name = "snd-soc-dummy",
5567 .id = MSM_FRONTEND_DAI_DTMF_RX,
5568 }
5569};
5570
5571static struct snd_soc_dai_link msm_custom_fe_dai_links[] = {
5572 /* FrontEnd DAI Links */
5573 {
5574 .name = MSM_DAILINK_NAME(Media1),
5575 .stream_name = "MultiMedia1",
5576 .cpu_dai_name = "MultiMedia1",
5577 .platform_name = "msm-pcm-dsp.1",
5578 .dynamic = 1,
5579 .async_ops = ASYNC_DPCM_SND_SOC_PREPARE,
5580 .dpcm_playback = 1,
5581 .dpcm_capture = 1,
5582 .codec_dai_name = "snd-soc-dummy-dai",
5583 .codec_name = "snd-soc-dummy",
5584 .trigger = {SND_SOC_DPCM_TRIGGER_POST,
5585 SND_SOC_DPCM_TRIGGER_POST},
5586 .ignore_suspend = 1,
5587 /* this dainlink has playback support */
5588 .ignore_pmdown_time = 1,
5589 .id = MSM_FRONTEND_DAI_MULTIMEDIA1,
5590 .ops = &msm_fe_qos_ops,
5591 },
5592 {
5593 .name = MSM_DAILINK_NAME(Media2),
5594 .stream_name = "MultiMedia2",
5595 .cpu_dai_name = "MultiMedia2",
5596 .platform_name = "msm-pcm-dsp.1",
5597 .dynamic = 1,
5598 .async_ops = ASYNC_DPCM_SND_SOC_PREPARE,
5599 .dpcm_playback = 1,
5600 .dpcm_capture = 1,
5601 .codec_dai_name = "snd-soc-dummy-dai",
5602 .codec_name = "snd-soc-dummy",
5603 .trigger = {SND_SOC_DPCM_TRIGGER_POST,
5604 SND_SOC_DPCM_TRIGGER_POST},
5605 .ignore_suspend = 1,
5606 /* this dainlink has playback support */
5607 .ignore_pmdown_time = 1,
5608 .id = MSM_FRONTEND_DAI_MULTIMEDIA2,
5609 .ops = &msm_fe_qos_ops,
5610 },
5611 {
5612 .name = MSM_DAILINK_NAME(Media3),
5613 .stream_name = "MultiMedia3",
5614 .cpu_dai_name = "MultiMedia3",
5615 .platform_name = "msm-pcm-dsp.1",
5616 .dynamic = 1,
5617 .async_ops = ASYNC_DPCM_SND_SOC_PREPARE,
5618 .dpcm_playback = 1,
5619 .dpcm_capture = 1,
5620 .codec_dai_name = "snd-soc-dummy-dai",
5621 .codec_name = "snd-soc-dummy",
5622 .trigger = {SND_SOC_DPCM_TRIGGER_POST,
5623 SND_SOC_DPCM_TRIGGER_POST},
5624 .ignore_suspend = 1,
5625 /* this dainlink has playback support */
5626 .ignore_pmdown_time = 1,
5627 .id = MSM_FRONTEND_DAI_MULTIMEDIA3,
5628 .ops = &msm_fe_qos_ops,
5629 },
5630 {
5631 .name = MSM_DAILINK_NAME(Media5),
5632 .stream_name = "MultiMedia5",
5633 .cpu_dai_name = "MultiMedia5",
5634 .platform_name = "msm-pcm-dsp.1",
5635 .dynamic = 1,
5636 .async_ops = ASYNC_DPCM_SND_SOC_PREPARE,
5637 .dpcm_playback = 1,
5638 .dpcm_capture = 1,
5639 .codec_dai_name = "snd-soc-dummy-dai",
5640 .codec_name = "snd-soc-dummy",
5641 .trigger = {SND_SOC_DPCM_TRIGGER_POST,
5642 SND_SOC_DPCM_TRIGGER_POST},
5643 .ignore_suspend = 1,
5644 /* this dainlink has playback support */
5645 .ignore_pmdown_time = 1,
5646 .id = MSM_FRONTEND_DAI_MULTIMEDIA5,
5647 .ops = &msm_fe_qos_ops,
5648 },
5649 {
5650 .name = MSM_DAILINK_NAME(Media6),
5651 .stream_name = "MultiMedia6",
5652 .cpu_dai_name = "MultiMedia6",
5653 .platform_name = "msm-pcm-dsp.1",
5654 .dynamic = 1,
5655 .async_ops = ASYNC_DPCM_SND_SOC_PREPARE,
5656 .dpcm_playback = 1,
5657 .dpcm_capture = 1,
5658 .codec_dai_name = "snd-soc-dummy-dai",
5659 .codec_name = "snd-soc-dummy",
5660 .trigger = {SND_SOC_DPCM_TRIGGER_POST,
5661 SND_SOC_DPCM_TRIGGER_POST},
5662 .ignore_suspend = 1,
5663 /* this dainlink has playback support */
5664 .ignore_pmdown_time = 1,
5665 .id = MSM_FRONTEND_DAI_MULTIMEDIA6,
5666 .ops = &msm_fe_qos_ops,
5667 },
5668 {
5669 .name = MSM_DAILINK_NAME(Media8),
5670 .stream_name = "MultiMedia8",
5671 .cpu_dai_name = "MultiMedia8",
5672 .platform_name = "msm-pcm-dsp.1",
5673 .dynamic = 1,
5674 .async_ops = ASYNC_DPCM_SND_SOC_PREPARE,
5675 .dpcm_playback = 1,
5676 .dpcm_capture = 1,
5677 .codec_dai_name = "snd-soc-dummy-dai",
5678 .codec_name = "snd-soc-dummy",
5679 .trigger = {SND_SOC_DPCM_TRIGGER_POST,
5680 SND_SOC_DPCM_TRIGGER_POST},
5681 .ignore_suspend = 1,
5682 /* this dainlink has playback support */
5683 .ignore_pmdown_time = 1,
5684 .id = MSM_FRONTEND_DAI_MULTIMEDIA8,
5685 .ops = &msm_fe_qos_ops,
5686 },
5687 {
5688 .name = MSM_DAILINK_NAME(Media9),
5689 .stream_name = "MultiMedia9",
5690 .cpu_dai_name = "MultiMedia9",
5691 .platform_name = "msm-pcm-dsp.1",
5692 .dynamic = 1,
5693 .async_ops = ASYNC_DPCM_SND_SOC_PREPARE,
5694 .dpcm_playback = 1,
5695 .dpcm_capture = 1,
5696 .codec_dai_name = "snd-soc-dummy-dai",
5697 .codec_name = "snd-soc-dummy",
5698 .trigger = {SND_SOC_DPCM_TRIGGER_POST,
5699 SND_SOC_DPCM_TRIGGER_POST},
5700 .ignore_suspend = 1,
5701 /* this dainlink has playback support */
5702 .ignore_pmdown_time = 1,
5703 .id = MSM_FRONTEND_DAI_MULTIMEDIA9,
5704 .ops = &msm_fe_qos_ops,
5705 },
5706 {
5707 .name = "INT_HFP_BT Hostless",
5708 .stream_name = "INT_HFP_BT Hostless",
5709 .cpu_dai_name = "INT_HFP_BT_HOSTLESS",
5710 .platform_name = "msm-pcm-hostless",
5711 .dynamic = 1,
5712 .dpcm_playback = 1,
5713 .dpcm_capture = 1,
5714 .trigger = {SND_SOC_DPCM_TRIGGER_POST,
5715 SND_SOC_DPCM_TRIGGER_POST},
5716 .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
5717 .ignore_suspend = 1,
5718 /* this dainlink has playback support */
5719 .ignore_pmdown_time = 1,
5720 .codec_dai_name = "snd-soc-dummy-dai",
5721 .codec_name = "snd-soc-dummy",
5722 },
5723 {
5724 .name = "AUXPCM Hostless",
5725 .stream_name = "AUXPCM Hostless",
5726 .cpu_dai_name = "AUXPCM_HOSTLESS",
5727 .platform_name = "msm-pcm-hostless",
5728 .dynamic = 1,
5729 .dpcm_playback = 1,
5730 .dpcm_capture = 1,
5731 .trigger = {SND_SOC_DPCM_TRIGGER_POST,
5732 SND_SOC_DPCM_TRIGGER_POST},
5733 .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
5734 .ignore_suspend = 1,
5735 /* this dainlink has playback support */
5736 .ignore_pmdown_time = 1,
5737 .codec_dai_name = "snd-soc-dummy-dai",
5738 .codec_name = "snd-soc-dummy",
5739 },
5740 {
5741 .name = MSM_DAILINK_NAME(Media20),
5742 .stream_name = "MultiMedia20",
5743 .cpu_dai_name = "MultiMedia20",
5744 .platform_name = "msm-pcm-loopback",
5745 .dynamic = 1,
5746 .dpcm_playback = 1,
5747 .dpcm_capture = 1,
5748 .codec_dai_name = "snd-soc-dummy-dai",
5749 .codec_name = "snd-soc-dummy",
5750 .trigger = {SND_SOC_DPCM_TRIGGER_POST,
5751 SND_SOC_DPCM_TRIGGER_POST},
5752 .ignore_suspend = 1,
5753 .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
5754 /* this dainlink has playback support */
5755 .ignore_pmdown_time = 1,
5756 .id = MSM_FRONTEND_DAI_MULTIMEDIA20,
5757 },
5758};
5759
5760static struct snd_soc_dai_link msm_common_be_dai_links[] = {
5761 /* Backend AFE DAI Links */
5762 {
5763 .name = LPASS_BE_AFE_PCM_RX,
5764 .stream_name = "AFE Playback",
5765 .cpu_dai_name = "msm-dai-q6-dev.224",
5766 .platform_name = "msm-pcm-routing",
5767 .codec_name = "msm-stub-codec.1",
5768 .codec_dai_name = "msm-stub-rx",
5769 .no_pcm = 1,
5770 .dpcm_playback = 1,
5771 .id = MSM_BACKEND_DAI_AFE_PCM_RX,
5772 .be_hw_params_fixup = msm_be_hw_params_fixup,
5773 /* this dainlink has playback support */
5774 .ignore_pmdown_time = 1,
5775 .ignore_suspend = 1,
5776 },
5777 {
5778 .name = LPASS_BE_AFE_PCM_TX,
5779 .stream_name = "AFE Capture",
5780 .cpu_dai_name = "msm-dai-q6-dev.225",
5781 .platform_name = "msm-pcm-routing",
5782 .codec_name = "msm-stub-codec.1",
5783 .codec_dai_name = "msm-stub-tx",
5784 .no_pcm = 1,
5785 .dpcm_capture = 1,
5786 .id = MSM_BACKEND_DAI_AFE_PCM_TX,
5787 .be_hw_params_fixup = msm_be_hw_params_fixup,
5788 .ignore_suspend = 1,
5789 },
5790 /* Incall Record Uplink BACK END DAI Link */
5791 {
5792 .name = LPASS_BE_INCALL_RECORD_TX,
5793 .stream_name = "Voice Uplink Capture",
5794 .cpu_dai_name = "msm-dai-q6-dev.32772",
5795 .platform_name = "msm-pcm-routing",
5796 .codec_name = "msm-stub-codec.1",
5797 .codec_dai_name = "msm-stub-tx",
5798 .no_pcm = 1,
5799 .dpcm_capture = 1,
5800 .id = MSM_BACKEND_DAI_INCALL_RECORD_TX,
5801 .be_hw_params_fixup = msm_be_hw_params_fixup,
5802 .ignore_suspend = 1,
5803 },
5804 /* Incall Record Downlink BACK END DAI Link */
5805 {
5806 .name = LPASS_BE_INCALL_RECORD_RX,
5807 .stream_name = "Voice Downlink Capture",
5808 .cpu_dai_name = "msm-dai-q6-dev.32771",
5809 .platform_name = "msm-pcm-routing",
5810 .codec_name = "msm-stub-codec.1",
5811 .codec_dai_name = "msm-stub-tx",
5812 .no_pcm = 1,
5813 .dpcm_capture = 1,
5814 .id = MSM_BACKEND_DAI_INCALL_RECORD_RX,
5815 .be_hw_params_fixup = msm_be_hw_params_fixup,
5816 .ignore_suspend = 1,
5817 },
5818 /* Incall Music BACK END DAI Link */
5819 {
5820 .name = LPASS_BE_VOICE_PLAYBACK_TX,
5821 .stream_name = "Voice Farend Playback",
5822 .cpu_dai_name = "msm-dai-q6-dev.32773",
5823 .platform_name = "msm-pcm-routing",
5824 .codec_name = "msm-stub-codec.1",
5825 .codec_dai_name = "msm-stub-rx",
5826 .no_pcm = 1,
5827 .dpcm_playback = 1,
5828 .id = MSM_BACKEND_DAI_VOICE_PLAYBACK_TX,
5829 .be_hw_params_fixup = msm_be_hw_params_fixup,
5830 .ignore_suspend = 1,
5831 .ignore_pmdown_time = 1,
5832 },
5833 /* Incall Music 2 BACK END DAI Link */
5834 {
5835 .name = LPASS_BE_VOICE2_PLAYBACK_TX,
5836 .stream_name = "Voice2 Farend Playback",
5837 .cpu_dai_name = "msm-dai-q6-dev.32770",
5838 .platform_name = "msm-pcm-routing",
5839 .codec_name = "msm-stub-codec.1",
5840 .codec_dai_name = "msm-stub-rx",
5841 .no_pcm = 1,
5842 .dpcm_playback = 1,
5843 .id = MSM_BACKEND_DAI_VOICE2_PLAYBACK_TX,
5844 .be_hw_params_fixup = msm_be_hw_params_fixup,
5845 .ignore_suspend = 1,
5846 .ignore_pmdown_time = 1,
5847 },
5848 {
5849 .name = LPASS_BE_USB_AUDIO_RX,
5850 .stream_name = "USB Audio Playback",
5851 .cpu_dai_name = "msm-dai-q6-dev.28672",
5852 .platform_name = "msm-pcm-routing",
5853 .codec_name = "msm-stub-codec.1",
5854 .codec_dai_name = "msm-stub-rx",
5855 .no_pcm = 1,
5856 .dpcm_playback = 1,
5857 .id = MSM_BACKEND_DAI_USB_RX,
5858 .be_hw_params_fixup = msm_be_hw_params_fixup,
5859 .ignore_pmdown_time = 1,
5860 .ignore_suspend = 1,
5861 },
5862 {
5863 .name = LPASS_BE_USB_AUDIO_TX,
5864 .stream_name = "USB Audio Capture",
5865 .cpu_dai_name = "msm-dai-q6-dev.28673",
5866 .platform_name = "msm-pcm-routing",
5867 .codec_name = "msm-stub-codec.1",
5868 .codec_dai_name = "msm-stub-tx",
5869 .no_pcm = 1,
5870 .dpcm_capture = 1,
5871 .id = MSM_BACKEND_DAI_USB_TX,
5872 .be_hw_params_fixup = msm_be_hw_params_fixup,
5873 .ignore_suspend = 1,
5874 },
5875 {
5876 .name = LPASS_BE_PRI_TDM_RX_0,
5877 .stream_name = "Primary TDM0 Playback",
5878 .cpu_dai_name = "msm-dai-q6-tdm.36864",
5879 .platform_name = "msm-pcm-routing",
5880 .codec_name = "msm-stub-codec.1",
5881 .codec_dai_name = "msm-stub-rx",
5882 .no_pcm = 1,
5883 .dpcm_playback = 1,
5884 .id = MSM_BACKEND_DAI_PRI_TDM_RX_0,
5885 .be_hw_params_fixup = msm_tdm_be_hw_params_fixup,
5886 .ops = &sa6155_tdm_be_ops,
5887 .ignore_suspend = 1,
5888 .ignore_pmdown_time = 1,
5889 },
5890 {
5891 .name = LPASS_BE_PRI_TDM_TX_0,
5892 .stream_name = "Primary TDM0 Capture",
5893 .cpu_dai_name = "msm-dai-q6-tdm.36865",
5894 .platform_name = "msm-pcm-routing",
5895 .codec_name = "msm-stub-codec.1",
5896 .codec_dai_name = "msm-stub-tx",
5897 .no_pcm = 1,
5898 .dpcm_capture = 1,
5899 .id = MSM_BACKEND_DAI_PRI_TDM_TX_0,
5900 .be_hw_params_fixup = msm_tdm_be_hw_params_fixup,
5901 .ops = &sa6155_tdm_be_ops,
5902 .ignore_suspend = 1,
5903 },
5904 {
5905 .name = LPASS_BE_SEC_TDM_RX_0,
5906 .stream_name = "Secondary TDM0 Playback",
5907 .cpu_dai_name = "msm-dai-q6-tdm.36880",
5908 .platform_name = "msm-pcm-routing",
5909 .codec_name = "msm-stub-codec.1",
5910 .codec_dai_name = "msm-stub-rx",
5911 .no_pcm = 1,
5912 .dpcm_playback = 1,
5913 .id = MSM_BACKEND_DAI_SEC_TDM_RX_0,
5914 .be_hw_params_fixup = msm_tdm_be_hw_params_fixup,
5915 .ops = &sa6155_tdm_be_ops,
5916 .ignore_suspend = 1,
5917 .ignore_pmdown_time = 1,
5918 },
5919 {
5920 .name = LPASS_BE_SEC_TDM_TX_0,
5921 .stream_name = "Secondary TDM0 Capture",
5922 .cpu_dai_name = "msm-dai-q6-tdm.36881",
5923 .platform_name = "msm-pcm-routing",
5924 .codec_name = "msm-stub-codec.1",
5925 .codec_dai_name = "msm-stub-tx",
5926 .no_pcm = 1,
5927 .dpcm_capture = 1,
5928 .id = MSM_BACKEND_DAI_SEC_TDM_TX_0,
5929 .be_hw_params_fixup = msm_tdm_be_hw_params_fixup,
5930 .ops = &sa6155_tdm_be_ops,
5931 .ignore_suspend = 1,
5932 },
5933 {
5934 .name = LPASS_BE_TERT_TDM_RX_0,
5935 .stream_name = "Tertiary TDM0 Playback",
5936 .cpu_dai_name = "msm-dai-q6-tdm.36896",
5937 .platform_name = "msm-pcm-routing",
5938 .codec_name = "msm-stub-codec.1",
5939 .codec_dai_name = "msm-stub-rx",
5940 .no_pcm = 1,
5941 .dpcm_playback = 1,
5942 .id = MSM_BACKEND_DAI_TERT_TDM_RX_0,
5943 .be_hw_params_fixup = msm_tdm_be_hw_params_fixup,
5944 .ops = &sa6155_tdm_be_ops,
5945 .ignore_suspend = 1,
5946 .ignore_pmdown_time = 1,
5947 },
5948 {
5949 .name = LPASS_BE_TERT_TDM_TX_0,
5950 .stream_name = "Tertiary TDM0 Capture",
5951 .cpu_dai_name = "msm-dai-q6-tdm.36897",
5952 .platform_name = "msm-pcm-routing",
5953 .codec_name = "msm-stub-codec.1",
5954 .codec_dai_name = "msm-stub-tx",
5955 .no_pcm = 1,
5956 .dpcm_capture = 1,
5957 .id = MSM_BACKEND_DAI_TERT_TDM_TX_0,
5958 .be_hw_params_fixup = msm_tdm_be_hw_params_fixup,
5959 .ops = &sa6155_tdm_be_ops,
5960 .ignore_suspend = 1,
5961 },
5962 {
5963 .name = LPASS_BE_QUAT_TDM_RX_0,
5964 .stream_name = "Quaternary TDM0 Playback",
5965 .cpu_dai_name = "msm-dai-q6-tdm.36912",
5966 .platform_name = "msm-pcm-routing",
5967 .codec_name = "msm-stub-codec.1",
5968 .codec_dai_name = "msm-stub-rx",
5969 .no_pcm = 1,
5970 .dpcm_playback = 1,
5971 .id = MSM_BACKEND_DAI_QUAT_TDM_RX_0,
5972 .be_hw_params_fixup = msm_tdm_be_hw_params_fixup,
5973 .ops = &sa6155_tdm_be_ops,
5974 .ignore_suspend = 1,
5975 .ignore_pmdown_time = 1,
5976 },
5977 {
5978 .name = LPASS_BE_QUAT_TDM_TX_0,
5979 .stream_name = "Quaternary TDM0 Capture",
5980 .cpu_dai_name = "msm-dai-q6-tdm.36913",
5981 .platform_name = "msm-pcm-routing",
5982 .codec_name = "msm-stub-codec.1",
5983 .codec_dai_name = "msm-stub-tx",
5984 .no_pcm = 1,
5985 .dpcm_capture = 1,
5986 .id = MSM_BACKEND_DAI_QUAT_TDM_TX_0,
5987 .be_hw_params_fixup = msm_tdm_be_hw_params_fixup,
5988 .ops = &sa6155_tdm_be_ops,
5989 .ignore_suspend = 1,
5990 },
Rahul Sharma51181d02019-04-12 17:03:01 +0530[diff] [blame]5991 {
5992 .name = LPASS_BE_QUIN_TDM_RX_0,
5993 .stream_name = "Quinary TDM0 Playback",
5994 .cpu_dai_name = "msm-dai-q6-tdm.36928",
5995 .platform_name = "msm-pcm-routing",
5996 .codec_name = "msm-stub-codec.1",
5997 .codec_dai_name = "msm-stub-rx",
5998 .no_pcm = 1,
5999 .dpcm_playback = 1,
6000 .id = MSM_BACKEND_DAI_QUIN_TDM_RX_0,
6001 .be_hw_params_fixup = msm_tdm_be_hw_params_fixup,
6002 .ops = &sa6155_tdm_be_ops,
6003 .ignore_suspend = 1,
6004 .ignore_pmdown_time = 1,
6005 },
6006 {
6007 .name = LPASS_BE_QUIN_TDM_TX_0,
6008 .stream_name = "Quinary TDM0 Capture",
6009 .cpu_dai_name = "msm-dai-q6-tdm.36929",
6010 .platform_name = "msm-pcm-routing",
6011 .codec_name = "msm-stub-codec.1",
6012 .codec_dai_name = "msm-stub-tx",
6013 .no_pcm = 1,
6014 .dpcm_capture = 1,
6015 .id = MSM_BACKEND_DAI_QUIN_TDM_TX_0,
6016 .be_hw_params_fixup = msm_tdm_be_hw_params_fixup,
6017 .ops = &sa6155_tdm_be_ops,
6018 .ignore_suspend = 1,
6019 },
Rahul Sharma02bee732018-12-20 18:48:34 +0530[diff] [blame]6020};
6021
6022static struct snd_soc_dai_link msm_auto_be_dai_links[] = {
6023 /* Backend DAI Links */
6024 {
6025 .name = LPASS_BE_PRI_TDM_RX_1,
6026 .stream_name = "Primary TDM1 Playback",
6027 .cpu_dai_name = "msm-dai-q6-tdm.36866",
6028 .platform_name = "msm-pcm-routing",
6029 .codec_name = "msm-stub-codec.1",
6030 .codec_dai_name = "msm-stub-rx",
6031 .no_pcm = 1,
6032 .dpcm_playback = 1,
6033 .id = MSM_BACKEND_DAI_PRI_TDM_RX_1,
6034 .be_hw_params_fixup = msm_tdm_be_hw_params_fixup,
6035 .ops = &sa6155_tdm_be_ops,
6036 .ignore_suspend = 1,
6037 },
6038 {
6039 .name = LPASS_BE_PRI_TDM_RX_2,
6040 .stream_name = "Primary TDM2 Playback",
6041 .cpu_dai_name = "msm-dai-q6-tdm.36868",
6042 .platform_name = "msm-pcm-routing",
6043 .codec_name = "msm-stub-codec.1",
6044 .codec_dai_name = "msm-stub-rx",
6045 .no_pcm = 1,
6046 .dpcm_playback = 1,
6047 .id = MSM_BACKEND_DAI_PRI_TDM_RX_2,
6048 .be_hw_params_fixup = msm_tdm_be_hw_params_fixup,
6049 .ops = &sa6155_tdm_be_ops,
6050 .ignore_suspend = 1,
6051 },
6052 {
6053 .name = LPASS_BE_PRI_TDM_RX_3,
6054 .stream_name = "Primary TDM3 Playback",
6055 .cpu_dai_name = "msm-dai-q6-tdm.36870",
6056 .platform_name = "msm-pcm-routing",
6057 .codec_name = "msm-stub-codec.1",
6058 .codec_dai_name = "msm-stub-rx",
6059 .no_pcm = 1,
6060 .dpcm_playback = 1,
6061 .id = MSM_BACKEND_DAI_PRI_TDM_RX_3,
6062 .be_hw_params_fixup = msm_tdm_be_hw_params_fixup,
6063 .ops = &sa6155_tdm_be_ops,
6064 .ignore_suspend = 1,
6065 },
6066 {
6067 .name = LPASS_BE_PRI_TDM_TX_1,
6068 .stream_name = "Primary TDM1 Capture",
6069 .cpu_dai_name = "msm-dai-q6-tdm.36867",
6070 .platform_name = "msm-pcm-routing",
6071 .codec_name = "msm-stub-codec.1",
6072 .codec_dai_name = "msm-stub-rx",
6073 .no_pcm = 1,
6074 .dpcm_capture = 1,
6075 .id = MSM_BACKEND_DAI_PRI_TDM_TX_1,
6076 .be_hw_params_fixup = msm_tdm_be_hw_params_fixup,
6077 .ops = &sa6155_tdm_be_ops,
6078 .ignore_suspend = 1,
6079 },
6080 {
6081 .name = LPASS_BE_PRI_TDM_TX_2,
6082 .stream_name = "Primary TDM2 Capture",
6083 .cpu_dai_name = "msm-dai-q6-tdm.36869",
6084 .platform_name = "msm-pcm-routing",
6085 .codec_name = "msm-stub-codec.1",
6086 .codec_dai_name = "msm-stub-rx",
6087 .no_pcm = 1,
6088 .dpcm_capture = 1,
6089 .id = MSM_BACKEND_DAI_PRI_TDM_TX_2,
6090 .be_hw_params_fixup = msm_tdm_be_hw_params_fixup,
6091 .ops = &sa6155_tdm_be_ops,
6092 .ignore_suspend = 1,
6093 },
6094 {
6095 .name = LPASS_BE_PRI_TDM_TX_3,
6096 .stream_name = "Primary TDM3 Capture",
6097 .cpu_dai_name = "msm-dai-q6-tdm.36871",
6098 .platform_name = "msm-pcm-routing",
6099 .codec_name = "msm-stub-codec.1",
6100 .codec_dai_name = "msm-stub-rx",
6101 .no_pcm = 1,
6102 .dpcm_capture = 1,
6103 .id = MSM_BACKEND_DAI_PRI_TDM_TX_3,
6104 .be_hw_params_fixup = msm_tdm_be_hw_params_fixup,
6105 .ops = &sa6155_tdm_be_ops,
6106 .ignore_suspend = 1,
6107 },
6108 {
6109 .name = LPASS_BE_SEC_TDM_RX_1,
6110 .stream_name = "Secondary TDM1 Playback",
6111 .cpu_dai_name = "msm-dai-q6-tdm.36882",
6112 .platform_name = "msm-pcm-routing",
6113 .codec_name = "msm-stub-codec.1",
6114 .codec_dai_name = "msm-stub-rx",
6115 .no_pcm = 1,
6116 .dpcm_playback = 1,
6117 .id = MSM_BACKEND_DAI_SEC_TDM_RX_1,
6118 .be_hw_params_fixup = msm_tdm_be_hw_params_fixup,
6119 .ops = &sa6155_tdm_be_ops,
6120 .ignore_suspend = 1,
6121 },
6122 {
6123 .name = LPASS_BE_SEC_TDM_RX_2,
6124 .stream_name = "Secondary TDM2 Playback",
6125 .cpu_dai_name = "msm-dai-q6-tdm.36884",
6126 .platform_name = "msm-pcm-routing",
6127 .codec_name = "msm-stub-codec.1",
6128 .codec_dai_name = "msm-stub-rx",
6129 .no_pcm = 1,
6130 .dpcm_playback = 1,
6131 .id = MSM_BACKEND_DAI_SEC_TDM_RX_2,
6132 .be_hw_params_fixup = msm_tdm_be_hw_params_fixup,
6133 .ops = &sa6155_tdm_be_ops,
6134 .ignore_suspend = 1,
6135 },
6136 {
6137 .name = LPASS_BE_SEC_TDM_RX_3,
6138 .stream_name = "Secondary TDM3 Playback",
6139 .cpu_dai_name = "msm-dai-q6-tdm.36886",
6140 .platform_name = "msm-pcm-routing",
6141 .codec_name = "msm-stub-codec.1",
6142 .codec_dai_name = "msm-stub-rx",
6143 .no_pcm = 1,
6144 .dpcm_playback = 1,
6145 .id = MSM_BACKEND_DAI_SEC_TDM_RX_3,
6146 .be_hw_params_fixup = msm_tdm_be_hw_params_fixup,
6147 .ops = &sa6155_tdm_be_ops,
6148 .ignore_suspend = 1,
6149 },
6150 {
6151 .name = LPASS_BE_SEC_TDM_TX_1,
6152 .stream_name = "Secondary TDM1 Capture",
6153 .cpu_dai_name = "msm-dai-q6-tdm.36883",
6154 .platform_name = "msm-pcm-routing",
6155 .codec_name = "msm-stub-codec.1",
6156 .codec_dai_name = "msm-stub-rx",
6157 .no_pcm = 1,
6158 .dpcm_capture = 1,
6159 .id = MSM_BACKEND_DAI_SEC_TDM_TX_1,
6160 .be_hw_params_fixup = msm_tdm_be_hw_params_fixup,
6161 .ops = &sa6155_tdm_be_ops,
6162 .ignore_suspend = 1,
6163 },
6164 {
6165 .name = LPASS_BE_SEC_TDM_TX_2,
6166 .stream_name = "Secondary TDM2 Capture",
6167 .cpu_dai_name = "msm-dai-q6-tdm.36885",
6168 .platform_name = "msm-pcm-routing",
6169 .codec_name = "msm-stub-codec.1",
6170 .codec_dai_name = "msm-stub-rx",
6171 .no_pcm = 1,
6172 .dpcm_capture = 1,
6173 .id = MSM_BACKEND_DAI_SEC_TDM_TX_2,
6174 .be_hw_params_fixup = msm_tdm_be_hw_params_fixup,
6175 .ops = &sa6155_tdm_be_ops,
6176 .ignore_suspend = 1,
6177 },
6178 {
6179 .name = LPASS_BE_SEC_TDM_TX_3,
6180 .stream_name = "Secondary TDM3 Capture",
6181 .cpu_dai_name = "msm-dai-q6-tdm.36887",
6182 .platform_name = "msm-pcm-routing",
6183 .codec_name = "msm-stub-codec.1",
6184 .codec_dai_name = "msm-stub-rx",
6185 .no_pcm = 1,
6186 .dpcm_capture = 1,
6187 .id = MSM_BACKEND_DAI_SEC_TDM_TX_3,
6188 .be_hw_params_fixup = msm_tdm_be_hw_params_fixup,
6189 .ops = &sa6155_tdm_be_ops,
6190 .ignore_suspend = 1,
6191 },
6192 {
6193 .name = LPASS_BE_TERT_TDM_RX_1,
6194 .stream_name = "Tertiary TDM1 Playback",
6195 .cpu_dai_name = "msm-dai-q6-tdm.36898",
6196 .platform_name = "msm-pcm-routing",
6197 .codec_name = "msm-stub-codec.1",
6198 .codec_dai_name = "msm-stub-rx",
6199 .no_pcm = 1,
6200 .dpcm_playback = 1,
6201 .id = MSM_BACKEND_DAI_TERT_TDM_RX_1,
6202 .be_hw_params_fixup = msm_tdm_be_hw_params_fixup,
6203 .ops = &sa6155_tdm_be_ops,
6204 .ignore_suspend = 1,
6205 },
6206 {
6207 .name = LPASS_BE_TERT_TDM_RX_2,
6208 .stream_name = "Tertiary TDM2 Playback",
6209 .cpu_dai_name = "msm-dai-q6-tdm.36900",
6210 .platform_name = "msm-pcm-routing",
6211 .codec_name = "msm-stub-codec.1",
6212 .codec_dai_name = "msm-stub-rx",
6213 .no_pcm = 1,
6214 .dpcm_playback = 1,
6215 .id = MSM_BACKEND_DAI_TERT_TDM_RX_2,
6216 .be_hw_params_fixup = msm_tdm_be_hw_params_fixup,
6217 .ops = &sa6155_tdm_be_ops,
6218 .ignore_suspend = 1,
6219 },
6220 {
6221 .name = LPASS_BE_TERT_TDM_RX_3,
6222 .stream_name = "Tertiary TDM3 Playback",
6223 .cpu_dai_name = "msm-dai-q6-tdm.36902",
6224 .platform_name = "msm-pcm-routing",
6225 .codec_name = "msm-stub-codec.1",
6226 .codec_dai_name = "msm-stub-rx",
6227 .no_pcm = 1,
6228 .dpcm_playback = 1,
6229 .id = MSM_BACKEND_DAI_TERT_TDM_RX_3,
6230 .be_hw_params_fixup = msm_tdm_be_hw_params_fixup,
6231 .ops = &sa6155_tdm_be_ops,
6232 .ignore_suspend = 1,
6233 },
6234 {
6235 .name = LPASS_BE_TERT_TDM_RX_4,
6236 .stream_name = "Tertiary TDM4 Playback",
6237 .cpu_dai_name = "msm-dai-q6-tdm.36904",
6238 .platform_name = "msm-pcm-routing",
6239 .codec_name = "msm-stub-codec.1",
6240 .codec_dai_name = "msm-stub-rx",
6241 .no_pcm = 1,
6242 .dpcm_playback = 1,
6243 .id = MSM_BACKEND_DAI_TERT_TDM_RX_4,
6244 .be_hw_params_fixup = msm_tdm_be_hw_params_fixup,
6245 .ops = &sa6155_tdm_be_ops,
6246 .ignore_suspend = 1,
6247 },
6248 {
6249 .name = LPASS_BE_TERT_TDM_TX_1,
6250 .stream_name = "Tertiary TDM1 Capture",
6251 .cpu_dai_name = "msm-dai-q6-tdm.36899",
6252 .platform_name = "msm-pcm-routing",
6253 .codec_name = "msm-stub-codec.1",
6254 .codec_dai_name = "msm-stub-rx",
6255 .no_pcm = 1,
6256 .dpcm_capture = 1,
6257 .id = MSM_BACKEND_DAI_TERT_TDM_TX_1,
6258 .be_hw_params_fixup = msm_tdm_be_hw_params_fixup,
6259 .ops = &sa6155_tdm_be_ops,
6260 .ignore_suspend = 1,
6261 },
6262 {
6263 .name = LPASS_BE_TERT_TDM_TX_2,
6264 .stream_name = "Tertiary TDM2 Capture",
6265 .cpu_dai_name = "msm-dai-q6-tdm.36901",
6266 .platform_name = "msm-pcm-routing",
6267 .codec_name = "msm-stub-codec.1",
6268 .codec_dai_name = "msm-stub-rx",
6269 .no_pcm = 1,
6270 .dpcm_capture = 1,
6271 .id = MSM_BACKEND_DAI_TERT_TDM_TX_2,
6272 .be_hw_params_fixup = msm_tdm_be_hw_params_fixup,
6273 .ops = &sa6155_tdm_be_ops,
6274 .ignore_suspend = 1,
6275 },
6276 {
6277 .name = LPASS_BE_TERT_TDM_TX_3,
6278 .stream_name = "Tertiary TDM3 Capture",
6279 .cpu_dai_name = "msm-dai-q6-tdm.36903",
6280 .platform_name = "msm-pcm-routing",
6281 .codec_name = "msm-stub-codec.1",
6282 .codec_dai_name = "msm-stub-rx",
6283 .no_pcm = 1,
6284 .dpcm_capture = 1,
6285 .id = MSM_BACKEND_DAI_TERT_TDM_TX_3,
6286 .be_hw_params_fixup = msm_tdm_be_hw_params_fixup,
6287 .ops = &sa6155_tdm_be_ops,
6288 .ignore_suspend = 1,
6289 },
6290 {
6291 .name = LPASS_BE_QUAT_TDM_RX_1,
6292 .stream_name = "Quaternary TDM1 Playback",
6293 .cpu_dai_name = "msm-dai-q6-tdm.36914",
6294 .platform_name = "msm-pcm-routing",
6295 .codec_name = "msm-stub-codec.1",
6296 .codec_dai_name = "msm-stub-rx",
6297 .no_pcm = 1,
6298 .dpcm_playback = 1,
6299 .id = MSM_BACKEND_DAI_QUAT_TDM_RX_1,
6300 .be_hw_params_fixup = msm_tdm_be_hw_params_fixup,
6301 .ops = &sa6155_tdm_be_ops,
6302 .ignore_suspend = 1,
6303 },
6304 {
6305 .name = LPASS_BE_QUAT_TDM_RX_2,
6306 .stream_name = "Quaternary TDM2 Playback",
6307 .cpu_dai_name = "msm-dai-q6-tdm.36916",
6308 .platform_name = "msm-pcm-routing",
6309 .codec_name = "msm-stub-codec.1",
6310 .codec_dai_name = "msm-stub-rx",
6311 .no_pcm = 1,
6312 .dpcm_playback = 1,
6313 .id = MSM_BACKEND_DAI_QUAT_TDM_RX_2,
6314 .be_hw_params_fixup = msm_tdm_be_hw_params_fixup,
6315 .ops = &sa6155_tdm_be_ops,
6316 .ignore_suspend = 1,
6317 },
6318 {
6319 .name = LPASS_BE_QUAT_TDM_RX_3,
6320 .stream_name = "Quaternary TDM3 Playback",
6321 .cpu_dai_name = "msm-dai-q6-tdm.36918",
6322 .platform_name = "msm-pcm-routing",
6323 .codec_name = "msm-stub-codec.1",
6324 .codec_dai_name = "msm-stub-rx",
6325 .no_pcm = 1,
6326 .dpcm_playback = 1,
6327 .id = MSM_BACKEND_DAI_QUAT_TDM_RX_3,
6328 .be_hw_params_fixup = msm_tdm_be_hw_params_fixup,
6329 .ops = &sa6155_tdm_be_ops,
6330 .ignore_suspend = 1,
6331 },
6332 {
6333 .name = LPASS_BE_QUAT_TDM_TX_1,
6334 .stream_name = "Quaternary TDM1 Capture",
6335 .cpu_dai_name = "msm-dai-q6-tdm.36915",
6336 .platform_name = "msm-pcm-routing",
6337 .codec_name = "msm-stub-codec.1",
6338 .codec_dai_name = "msm-stub-rx",
6339 .no_pcm = 1,
6340 .dpcm_capture = 1,
6341 .id = MSM_BACKEND_DAI_QUAT_TDM_TX_1,
6342 .be_hw_params_fixup = msm_tdm_be_hw_params_fixup,
6343 .ops = &sa6155_tdm_be_ops,
6344 .ignore_suspend = 1,
6345 },
6346 {
6347 .name = LPASS_BE_QUAT_TDM_TX_2,
6348 .stream_name = "Quaternary TDM2 Capture",
6349 .cpu_dai_name = "msm-dai-q6-tdm.36917",
6350 .platform_name = "msm-pcm-routing",
6351 .codec_name = "msm-stub-codec.1",
6352 .codec_dai_name = "msm-stub-rx",
6353 .no_pcm = 1,
6354 .dpcm_capture = 1,
6355 .id = MSM_BACKEND_DAI_QUAT_TDM_TX_2,
6356 .be_hw_params_fixup = msm_tdm_be_hw_params_fixup,
6357 .ops = &sa6155_tdm_be_ops,
6358 .ignore_suspend = 1,
6359 },
6360 {
6361 .name = LPASS_BE_QUAT_TDM_TX_3,
6362 .stream_name = "Quaternary TDM3 Capture",
6363 .cpu_dai_name = "msm-dai-q6-tdm.36919",
6364 .platform_name = "msm-pcm-routing",
6365 .codec_name = "msm-stub-codec.1",
6366 .codec_dai_name = "msm-stub-rx",
6367 .no_pcm = 1,
6368 .dpcm_capture = 1,
6369 .id = MSM_BACKEND_DAI_QUAT_TDM_TX_3,
6370 .be_hw_params_fixup = msm_tdm_be_hw_params_fixup,
6371 .ops = &sa6155_tdm_be_ops,
6372 .ignore_suspend = 1,
6373 },
6374};
6375
6376static struct snd_soc_dai_link ext_disp_be_dai_link[] = {
6377 /* DISP PORT BACK END DAI Link */
6378 {
6379 .name = LPASS_BE_DISPLAY_PORT,
6380 .stream_name = "Display Port Playback",
6381 .cpu_dai_name = "msm-dai-q6-dp.24608",
6382 .platform_name = "msm-pcm-routing",
6383 .codec_name = "msm-ext-disp-audio-codec-rx",
6384 .codec_dai_name = "msm_dp_audio_codec_rx_dai",
6385 .no_pcm = 1,
6386 .dpcm_playback = 1,
6387 .id = MSM_BACKEND_DAI_DISPLAY_PORT_RX,
6388 .be_hw_params_fixup = msm_be_hw_params_fixup,
6389 .ignore_pmdown_time = 1,
6390 .ignore_suspend = 1,
6391 },
6392};
6393
6394static struct snd_soc_dai_link msm_mi2s_be_dai_links[] = {
6395 {
6396 .name = LPASS_BE_PRI_MI2S_RX,
6397 .stream_name = "Primary MI2S Playback",
6398 .cpu_dai_name = "msm-dai-q6-mi2s.0",
6399 .platform_name = "msm-pcm-routing",
6400 .codec_name = "msm-stub-codec.1",
6401 .codec_dai_name = "msm-stub-rx",
6402 .no_pcm = 1,
6403 .dpcm_playback = 1,
6404 .id = MSM_BACKEND_DAI_PRI_MI2S_RX,
6405 .be_hw_params_fixup = msm_be_hw_params_fixup,
6406 .ops = &msm_mi2s_be_ops,
6407 .ignore_suspend = 1,
6408 .ignore_pmdown_time = 1,
6409 },
6410 {
6411 .name = LPASS_BE_PRI_MI2S_TX,
6412 .stream_name = "Primary MI2S Capture",
6413 .cpu_dai_name = "msm-dai-q6-mi2s.0",
6414 .platform_name = "msm-pcm-routing",
6415 .codec_name = "msm-stub-codec.1",
6416 .codec_dai_name = "msm-stub-tx",
6417 .no_pcm = 1,
6418 .dpcm_capture = 1,
6419 .id = MSM_BACKEND_DAI_PRI_MI2S_TX,
6420 .be_hw_params_fixup = msm_be_hw_params_fixup,
6421 .ops = &msm_mi2s_be_ops,
6422 .ignore_suspend = 1,
6423 },
6424 {
6425 .name = LPASS_BE_SEC_MI2S_RX,
6426 .stream_name = "Secondary MI2S Playback",
6427 .cpu_dai_name = "msm-dai-q6-mi2s.1",
6428 .platform_name = "msm-pcm-routing",
6429 .codec_name = "msm-stub-codec.1",
6430 .codec_dai_name = "msm-stub-rx",
6431 .no_pcm = 1,
6432 .dpcm_playback = 1,
6433 .id = MSM_BACKEND_DAI_SECONDARY_MI2S_RX,
6434 .be_hw_params_fixup = msm_be_hw_params_fixup,
6435 .ops = &msm_mi2s_be_ops,
6436 .ignore_suspend = 1,
6437 .ignore_pmdown_time = 1,
6438 },
6439 {
6440 .name = LPASS_BE_SEC_MI2S_TX,
6441 .stream_name = "Secondary MI2S Capture",
6442 .cpu_dai_name = "msm-dai-q6-mi2s.1",
6443 .platform_name = "msm-pcm-routing",
6444 .codec_name = "msm-stub-codec.1",
6445 .codec_dai_name = "msm-stub-tx",
6446 .no_pcm = 1,
6447 .dpcm_capture = 1,
6448 .id = MSM_BACKEND_DAI_SECONDARY_MI2S_TX,
6449 .be_hw_params_fixup = msm_be_hw_params_fixup,
6450 .ops = &msm_mi2s_be_ops,
6451 .ignore_suspend = 1,
6452 },
6453 {
6454 .name = LPASS_BE_TERT_MI2S_RX,
6455 .stream_name = "Tertiary MI2S Playback",
6456 .cpu_dai_name = "msm-dai-q6-mi2s.2",
6457 .platform_name = "msm-pcm-routing",
6458 .codec_name = "msm-stub-codec.1",
6459 .codec_dai_name = "msm-stub-rx",
6460 .no_pcm = 1,
6461 .dpcm_playback = 1,
6462 .id = MSM_BACKEND_DAI_TERTIARY_MI2S_RX,
6463 .be_hw_params_fixup = msm_be_hw_params_fixup,
6464 .ops = &msm_mi2s_be_ops,
6465 .ignore_suspend = 1,
6466 .ignore_pmdown_time = 1,
6467 },
6468 {
6469 .name = LPASS_BE_TERT_MI2S_TX,
6470 .stream_name = "Tertiary MI2S Capture",
6471 .cpu_dai_name = "msm-dai-q6-mi2s.2",
6472 .platform_name = "msm-pcm-routing",
6473 .codec_name = "msm-stub-codec.1",
6474 .codec_dai_name = "msm-stub-tx",
6475 .no_pcm = 1,
6476 .dpcm_capture = 1,
6477 .id = MSM_BACKEND_DAI_TERTIARY_MI2S_TX,
6478 .be_hw_params_fixup = msm_be_hw_params_fixup,
6479 .ops = &msm_mi2s_be_ops,
6480 .ignore_suspend = 1,
6481 },
6482 {
6483 .name = LPASS_BE_QUAT_MI2S_RX,
6484 .stream_name = "Quaternary MI2S Playback",
6485 .cpu_dai_name = "msm-dai-q6-mi2s.3",
6486 .platform_name = "msm-pcm-routing",
6487 .codec_name = "msm-stub-codec.1",
6488 .codec_dai_name = "msm-stub-rx",
6489 .no_pcm = 1,
6490 .dpcm_playback = 1,
6491 .id = MSM_BACKEND_DAI_QUATERNARY_MI2S_RX,
6492 .be_hw_params_fixup = msm_be_hw_params_fixup,
6493 .ops = &msm_mi2s_be_ops,
6494 .ignore_suspend = 1,
6495 .ignore_pmdown_time = 1,
6496 },
6497 {
6498 .name = LPASS_BE_QUAT_MI2S_TX,
6499 .stream_name = "Quaternary MI2S Capture",
6500 .cpu_dai_name = "msm-dai-q6-mi2s.3",
6501 .platform_name = "msm-pcm-routing",
6502 .codec_name = "msm-stub-codec.1",
6503 .codec_dai_name = "msm-stub-tx",
6504 .no_pcm = 1,
6505 .dpcm_capture = 1,
6506 .id = MSM_BACKEND_DAI_QUATERNARY_MI2S_TX,
6507 .be_hw_params_fixup = msm_be_hw_params_fixup,
6508 .ops = &msm_mi2s_be_ops,
6509 .ignore_suspend = 1,
6510 },
6511 {
6512 .name = LPASS_BE_QUIN_MI2S_RX,
6513 .stream_name = "Quinary MI2S Playback",
6514 .cpu_dai_name = "msm-dai-q6-mi2s.4",
6515 .platform_name = "msm-pcm-routing",
6516 .codec_name = "msm-stub-codec.1",
6517 .codec_dai_name = "msm-stub-rx",
6518 .no_pcm = 1,
6519 .dpcm_playback = 1,
6520 .id = MSM_BACKEND_DAI_QUINARY_MI2S_RX,
6521 .be_hw_params_fixup = msm_be_hw_params_fixup,
6522 .ops = &msm_mi2s_be_ops,
6523 .ignore_suspend = 1,
6524 .ignore_pmdown_time = 1,
6525 },
6526 {
6527 .name = LPASS_BE_QUIN_MI2S_TX,
6528 .stream_name = "Quinary MI2S Capture",
6529 .cpu_dai_name = "msm-dai-q6-mi2s.4",
6530 .platform_name = "msm-pcm-routing",
6531 .codec_name = "msm-stub-codec.1",
6532 .codec_dai_name = "msm-stub-tx",
6533 .no_pcm = 1,
6534 .dpcm_capture = 1,
6535 .id = MSM_BACKEND_DAI_QUINARY_MI2S_TX,
6536 .be_hw_params_fixup = msm_be_hw_params_fixup,
6537 .ops = &msm_mi2s_be_ops,
6538 .ignore_suspend = 1,
6539 },
6540};
6541
6542static struct snd_soc_dai_link msm_auxpcm_be_dai_links[] = {
6543 /* Primary AUX PCM Backend DAI Links */
6544 {
6545 .name = LPASS_BE_AUXPCM_RX,
6546 .stream_name = "AUX PCM Playback",
6547 .cpu_dai_name = "msm-dai-q6-auxpcm.1",
6548 .platform_name = "msm-pcm-routing",
6549 .codec_name = "msm-stub-codec.1",
6550 .codec_dai_name = "msm-stub-rx",
6551 .no_pcm = 1,
6552 .dpcm_playback = 1,
6553 .id = MSM_BACKEND_DAI_AUXPCM_RX,
6554 .be_hw_params_fixup = msm_be_hw_params_fixup,
6555 .ignore_pmdown_time = 1,
6556 .ignore_suspend = 1,
6557 },
6558 {
6559 .name = LPASS_BE_AUXPCM_TX,
6560 .stream_name = "AUX PCM Capture",
6561 .cpu_dai_name = "msm-dai-q6-auxpcm.1",
6562 .platform_name = "msm-pcm-routing",
6563 .codec_name = "msm-stub-codec.1",
6564 .codec_dai_name = "msm-stub-tx",
6565 .no_pcm = 1,
6566 .dpcm_capture = 1,
6567 .id = MSM_BACKEND_DAI_AUXPCM_TX,
6568 .be_hw_params_fixup = msm_be_hw_params_fixup,
6569 .ignore_suspend = 1,
6570 },
6571 /* Secondary AUX PCM Backend DAI Links */
6572 {
6573 .name = LPASS_BE_SEC_AUXPCM_RX,
6574 .stream_name = "Sec AUX PCM Playback",
6575 .cpu_dai_name = "msm-dai-q6-auxpcm.2",
6576 .platform_name = "msm-pcm-routing",
6577 .codec_name = "msm-stub-codec.1",
6578 .codec_dai_name = "msm-stub-rx",
6579 .no_pcm = 1,
6580 .dpcm_playback = 1,
6581 .id = MSM_BACKEND_DAI_SEC_AUXPCM_RX,
6582 .be_hw_params_fixup = msm_be_hw_params_fixup,
6583 .ignore_pmdown_time = 1,
6584 .ignore_suspend = 1,
6585 },
6586 {
6587 .name = LPASS_BE_SEC_AUXPCM_TX,
6588 .stream_name = "Sec AUX PCM Capture",
6589 .cpu_dai_name = "msm-dai-q6-auxpcm.2",
6590 .platform_name = "msm-pcm-routing",
6591 .codec_name = "msm-stub-codec.1",
6592 .codec_dai_name = "msm-stub-tx",
6593 .no_pcm = 1,
6594 .dpcm_capture = 1,
6595 .id = MSM_BACKEND_DAI_SEC_AUXPCM_TX,
6596 .be_hw_params_fixup = msm_be_hw_params_fixup,
6597 .ignore_suspend = 1,
6598 },
6599 /* Tertiary AUX PCM Backend DAI Links */
6600 {
6601 .name = LPASS_BE_TERT_AUXPCM_RX,
6602 .stream_name = "Tert AUX PCM Playback",
6603 .cpu_dai_name = "msm-dai-q6-auxpcm.3",
6604 .platform_name = "msm-pcm-routing",
6605 .codec_name = "msm-stub-codec.1",
6606 .codec_dai_name = "msm-stub-rx",
6607 .no_pcm = 1,
6608 .dpcm_playback = 1,
6609 .id = MSM_BACKEND_DAI_TERT_AUXPCM_RX,
6610 .be_hw_params_fixup = msm_be_hw_params_fixup,
6611 .ignore_suspend = 1,
6612 },
6613 {
6614 .name = LPASS_BE_TERT_AUXPCM_TX,
6615 .stream_name = "Tert AUX PCM Capture",
6616 .cpu_dai_name = "msm-dai-q6-auxpcm.3",
6617 .platform_name = "msm-pcm-routing",
6618 .codec_name = "msm-stub-codec.1",
6619 .codec_dai_name = "msm-stub-tx",
6620 .no_pcm = 1,
6621 .dpcm_capture = 1,
6622 .id = MSM_BACKEND_DAI_TERT_AUXPCM_TX,
6623 .be_hw_params_fixup = msm_be_hw_params_fixup,
6624 .ignore_suspend = 1,
6625 },
6626 /* Quaternary AUX PCM Backend DAI Links */
6627 {
6628 .name = LPASS_BE_QUAT_AUXPCM_RX,
6629 .stream_name = "Quat AUX PCM Playback",
6630 .cpu_dai_name = "msm-dai-q6-auxpcm.4",
6631 .platform_name = "msm-pcm-routing",
6632 .codec_name = "msm-stub-codec.1",
6633 .codec_dai_name = "msm-stub-rx",
6634 .no_pcm = 1,
6635 .dpcm_playback = 1,
6636 .id = MSM_BACKEND_DAI_QUAT_AUXPCM_RX,
6637 .be_hw_params_fixup = msm_be_hw_params_fixup,
6638 .ignore_pmdown_time = 1,
6639 .ignore_suspend = 1,
6640 },
6641 {
6642 .name = LPASS_BE_QUAT_AUXPCM_TX,
6643 .stream_name = "Quat AUX PCM Capture",
6644 .cpu_dai_name = "msm-dai-q6-auxpcm.4",
6645 .platform_name = "msm-pcm-routing",
6646 .codec_name = "msm-stub-codec.1",
6647 .codec_dai_name = "msm-stub-tx",
6648 .no_pcm = 1,
6649 .dpcm_capture = 1,
6650 .id = MSM_BACKEND_DAI_QUAT_AUXPCM_TX,
6651 .be_hw_params_fixup = msm_be_hw_params_fixup,
6652 .ignore_suspend = 1,
6653 },
6654 /* Quinary AUX PCM Backend DAI Links */
6655 {
6656 .name = LPASS_BE_QUIN_AUXPCM_RX,
6657 .stream_name = "Quin AUX PCM Playback",
6658 .cpu_dai_name = "msm-dai-q6-auxpcm.5",
6659 .platform_name = "msm-pcm-routing",
6660 .codec_name = "msm-stub-codec.1",
6661 .codec_dai_name = "msm-stub-rx",
6662 .no_pcm = 1,
6663 .dpcm_playback = 1,
6664 .id = MSM_BACKEND_DAI_QUIN_AUXPCM_RX,
6665 .be_hw_params_fixup = msm_be_hw_params_fixup,
6666 .ignore_pmdown_time = 1,
6667 .ignore_suspend = 1,
6668 },
6669 {
6670 .name = LPASS_BE_QUIN_AUXPCM_TX,
6671 .stream_name = "Quin AUX PCM Capture",
6672 .cpu_dai_name = "msm-dai-q6-auxpcm.5",
6673 .platform_name = "msm-pcm-routing",
6674 .codec_name = "msm-stub-codec.1",
6675 .codec_dai_name = "msm-stub-tx",
6676 .no_pcm = 1,
6677 .dpcm_capture = 1,
6678 .id = MSM_BACKEND_DAI_QUIN_AUXPCM_TX,
6679 .be_hw_params_fixup = msm_be_hw_params_fixup,
6680 .ignore_suspend = 1,
6681 },
6682};
6683
6684static struct snd_soc_dai_link msm_auto_dai_links[
6685 ARRAY_SIZE(msm_common_dai_links) +
6686 ARRAY_SIZE(msm_auto_fe_dai_links) +
6687 ARRAY_SIZE(msm_common_be_dai_links) +
6688 ARRAY_SIZE(msm_auto_be_dai_links) +
6689 ARRAY_SIZE(ext_disp_be_dai_link) +
6690 ARRAY_SIZE(msm_mi2s_be_dai_links) +
6691 ARRAY_SIZE(msm_auxpcm_be_dai_links)];
6692
6693static struct snd_soc_dai_link msm_auto_custom_dai_links[
6694 ARRAY_SIZE(msm_custom_fe_dai_links) +
6695 ARRAY_SIZE(msm_auto_fe_dai_links) +
6696 ARRAY_SIZE(msm_common_be_dai_links) +
6697 ARRAY_SIZE(msm_auto_be_dai_links) +
6698 ARRAY_SIZE(ext_disp_be_dai_link) +
6699 ARRAY_SIZE(msm_mi2s_be_dai_links) +
6700 ARRAY_SIZE(msm_auxpcm_be_dai_links)];
6701
6702struct snd_soc_card snd_soc_card_auto_msm = {
6703 .name = "sa6155-adp-star-snd-card",
6704};
6705
6706struct snd_soc_card snd_soc_card_auto_custom_msm = {
6707 .name = "sa6155-custom-snd-card",
6708};
6709
6710static int msm_populate_dai_link_component_of_node(
6711 struct snd_soc_card *card)
6712{
6713 int i, index, ret = 0;
6714 struct device *cdev = card->dev;
6715 struct snd_soc_dai_link *dai_link = card->dai_link;
6716 struct device_node *np;
6717
6718 if (!cdev) {
6719 pr_err("%s: Sound card device memory NULL\n", __func__);
6720 return -ENODEV;
6721 }
6722
6723 for (i = 0; i < card->num_links; i++) {
6724 if (dai_link[i].platform_of_node && dai_link[i].cpu_of_node)
6725 continue;
6726
6727 /* populate platform_of_node for snd card dai links */
6728 if (dai_link[i].platform_name &&
6729 !dai_link[i].platform_of_node) {
6730 index = of_property_match_string(cdev->of_node,
6731 "asoc-platform-names",
6732 dai_link[i].platform_name);
6733 if (index < 0) {
6734 pr_err("%s: No match found for platform name: %s\n",
6735 __func__, dai_link[i].platform_name);
6736 ret = index;
6737 goto err;
6738 }
6739 np = of_parse_phandle(cdev->of_node, "asoc-platform",
6740 index);
6741 if (!np) {
6742 pr_err("%s: retrieving phandle for platform %s, index %d failed\n",
6743 __func__, dai_link[i].platform_name,
6744 index);
6745 ret = -ENODEV;
6746 goto err;
6747 }
6748 dai_link[i].platform_of_node = np;
6749 dai_link[i].platform_name = NULL;
6750 }
6751
6752 /* populate cpu_of_node for snd card dai links */
6753 if (dai_link[i].cpu_dai_name && !dai_link[i].cpu_of_node) {
6754 index = of_property_match_string(cdev->of_node,
6755 "asoc-cpu-names",
6756 dai_link[i].cpu_dai_name);
6757 if (index >= 0) {
6758 np = of_parse_phandle(cdev->of_node, "asoc-cpu",
6759 index);
6760 if (!np) {
6761 pr_err("%s: retrieving phandle for cpu dai %s failed\n",
6762 __func__,
6763 dai_link[i].cpu_dai_name);
6764 ret = -ENODEV;
6765 goto err;
6766 }
6767 dai_link[i].cpu_of_node = np;
6768 dai_link[i].cpu_dai_name = NULL;
6769 }
6770 }
6771
6772 /* populate codec_of_node for snd card dai links */
6773 if (dai_link[i].codec_name && !dai_link[i].codec_of_node) {
6774 index = of_property_match_string(cdev->of_node,
6775 "asoc-codec-names",
6776 dai_link[i].codec_name);
6777 if (index < 0)
6778 continue;
6779 np = of_parse_phandle(cdev->of_node, "asoc-codec",
6780 index);
6781 if (!np) {
6782 pr_err("%s: retrieving phandle for codec %s failed\n",
6783 __func__, dai_link[i].codec_name);
6784 ret = -ENODEV;
6785 goto err;
6786 }
6787 dai_link[i].codec_of_node = np;
6788 dai_link[i].codec_name = NULL;
6789 }
6790 }
6791
6792err:
6793 return ret;
6794}
6795
6796static const struct of_device_id sa6155_asoc_machine_of_match[] = {
6797 { .compatible = "qcom,sa6155-asoc-snd-adp-star",
6798 .data = "adp_star_codec"},
6799 { .compatible = "qcom,sa6155-asoc-snd-custom",
6800 .data = "custom_codec"},
6801 {},
6802};
6803
6804static struct snd_soc_card *populate_snd_card_dailinks(struct device *dev)
6805{
6806 struct snd_soc_card *card = NULL;
6807 struct snd_soc_dai_link *dailink;
6808 int len_1, len_2, len_3;
6809 int total_links;
6810 const struct of_device_id *match;
6811
6812 match = of_match_node(sa6155_asoc_machine_of_match, dev->of_node);
6813 if (!match) {
6814 dev_err(dev, "%s: No DT match found for sound card\n",
6815 __func__);
6816 return NULL;
6817 }
6818
6819 if (!strcmp(match->data, "adp_star_codec")) {
6820 card = &snd_soc_card_auto_msm;
6821 len_1 = ARRAY_SIZE(msm_common_dai_links);
6822 len_2 = len_1 + ARRAY_SIZE(msm_auto_fe_dai_links);
6823 len_3 = len_2 + ARRAY_SIZE(msm_common_be_dai_links);
6824 total_links = len_3 + ARRAY_SIZE(msm_auto_be_dai_links);
6825 memcpy(msm_auto_dai_links,
6826 msm_common_dai_links,
6827 sizeof(msm_common_dai_links));
6828 memcpy(msm_auto_dai_links + len_1,
6829 msm_auto_fe_dai_links,
6830 sizeof(msm_auto_fe_dai_links));
6831 memcpy(msm_auto_dai_links + len_2,
6832 msm_common_be_dai_links,
6833 sizeof(msm_common_be_dai_links));
6834 memcpy(msm_auto_dai_links + len_3,
6835 msm_auto_be_dai_links,
6836 sizeof(msm_auto_be_dai_links));
6837
6838 if (of_property_read_bool(dev->of_node,
6839 "qcom,ext-disp-audio-rx")) {
6840 dev_dbg(dev, "%s(): ext disp audio support present\n",
6841 __func__);
6842 memcpy(msm_auto_dai_links + total_links,
6843 ext_disp_be_dai_link,
6844 sizeof(ext_disp_be_dai_link));
6845 total_links += ARRAY_SIZE(ext_disp_be_dai_link);
6846 }
6847 if (of_property_read_bool(dev->of_node,
6848 "qcom,mi2s-audio-intf")) {
6849 memcpy(msm_auto_dai_links + total_links,
6850 msm_mi2s_be_dai_links,
6851 sizeof(msm_mi2s_be_dai_links));
6852 total_links += ARRAY_SIZE(msm_mi2s_be_dai_links);
6853 }
6854 if (of_property_read_bool(dev->of_node,
6855 "qcom,auxpcm-audio-intf")) {
6856 memcpy(msm_auto_dai_links + total_links,
6857 msm_auxpcm_be_dai_links,
6858 sizeof(msm_auxpcm_be_dai_links));
6859 total_links += ARRAY_SIZE(msm_auxpcm_be_dai_links);
6860 }
6861
6862 dailink = msm_auto_dai_links;
6863 } else if (!strcmp(match->data, "custom_codec")) {
6864 card = &snd_soc_card_auto_custom_msm;
6865 len_1 = ARRAY_SIZE(msm_custom_fe_dai_links);
6866 len_2 = len_1 + ARRAY_SIZE(msm_auto_fe_dai_links);
6867 len_3 = len_2 + ARRAY_SIZE(msm_common_be_dai_links);
6868 total_links = len_3 + ARRAY_SIZE(msm_auto_be_dai_links);
6869 memcpy(msm_auto_custom_dai_links,
6870 msm_custom_fe_dai_links,
6871 sizeof(msm_custom_fe_dai_links));
6872 memcpy(msm_auto_custom_dai_links + len_1,
6873 msm_auto_fe_dai_links,
6874 sizeof(msm_auto_fe_dai_links));
6875 memcpy(msm_auto_custom_dai_links + len_2,
6876 msm_common_be_dai_links,
6877 sizeof(msm_common_be_dai_links));
6878 memcpy(msm_auto_custom_dai_links + len_3,
6879 msm_auto_be_dai_links,
6880 sizeof(msm_auto_be_dai_links));
6881
6882 if (of_property_read_bool(dev->of_node,
6883 "qcom,ext-disp-audio-rx")) {
6884 dev_dbg(dev, "%s(): ext disp audio support present\n",
6885 __func__);
6886 memcpy(msm_auto_custom_dai_links + total_links,
6887 ext_disp_be_dai_link,
6888 sizeof(ext_disp_be_dai_link));
6889 total_links += ARRAY_SIZE(ext_disp_be_dai_link);
6890 }
6891 if (of_property_read_bool(dev->of_node,
6892 "qcom,mi2s-audio-intf")) {
6893 memcpy(msm_auto_custom_dai_links + total_links,
6894 msm_mi2s_be_dai_links,
6895 sizeof(msm_mi2s_be_dai_links));
6896 total_links += ARRAY_SIZE(msm_mi2s_be_dai_links);
6897 }
6898 if (of_property_read_bool(dev->of_node,
6899 "qcom,auxpcm-audio-intf")) {
6900 memcpy(msm_auto_custom_dai_links + total_links,
6901 msm_auxpcm_be_dai_links,
6902 sizeof(msm_auxpcm_be_dai_links));
6903 total_links += ARRAY_SIZE(msm_auxpcm_be_dai_links);
6904 }
6905 dailink = msm_auto_custom_dai_links;
6906 } else {
6907 dev_err(dev, "%s: Codec not supported\n",
6908 __func__);
6909 return NULL;
6910 }
6911
6912 if (card) {
6913 card->dai_link = dailink;
6914 card->num_links = total_links;
6915 }
6916
6917 return card;
6918}
6919
6920/*****************************************************************************
6921* TO BE UPDATED: Codec/Platform specific tdm slot and offset table selection
6922*****************************************************************************/
6923static int msm_tdm_init(struct device *dev)
6924{
6925 const struct of_device_id *match;
6926
6927 match = of_match_node(sa6155_asoc_machine_of_match, dev->of_node);
6928 if (!match) {
6929 dev_err(dev, "%s: No DT match found for sound card\n",
6930 __func__);
6931 return -EINVAL;
6932 }
6933
6934 if (!strcmp(match->data, "custom_codec")) {
6935 dev_dbg(dev, "%s: custom tdm configuration\n", __func__);
6936
6937 memcpy(tdm_rx_slot_offset,
6938 tdm_rx_slot_offset_custom,
6939 sizeof(tdm_rx_slot_offset_custom));
6940 memcpy(tdm_tx_slot_offset,
6941 tdm_tx_slot_offset_custom,
6942 sizeof(tdm_tx_slot_offset_custom));
6943 memcpy(tdm_slot,
6944 tdm_slot_custom,
6945 sizeof(tdm_slot_custom));
6946 } else {
6947 dev_dbg(dev, "%s: default tdm configuration\n", __func__);
6948 }
6949
6950 return 0;
6951}
6952
6953static void msm_i2s_auxpcm_init(struct platform_device *pdev)
6954{
6955 int count;
6956 u32 mi2s_master_slave[MI2S_MAX];
6957 int ret;
6958
6959 for (count = 0; count < MI2S_MAX; count++) {
6960 mutex_init(&mi2s_intf_conf[count].lock);
6961 mi2s_intf_conf[count].ref_cnt = 0;
6962 }
6963
6964 ret = of_property_read_u32_array(pdev->dev.of_node,
6965 "qcom,msm-mi2s-master",
6966 mi2s_master_slave, MI2S_MAX);
6967 if (ret) {
6968 dev_dbg(&pdev->dev, "%s: no qcom,msm-mi2s-master in DT node\n",
6969 __func__);
6970 } else {
6971 for (count = 0; count < MI2S_MAX; count++) {
6972 mi2s_intf_conf[count].msm_is_mi2s_master =
6973 mi2s_master_slave[count];
6974 }
6975 }
6976}
6977
6978static void msm_i2s_auxpcm_deinit(void)
6979{
6980 int count;
6981
6982 for (count = 0; count < MI2S_MAX; count++) {
6983 mutex_destroy(&mi2s_intf_conf[count].lock);
6984 mi2s_intf_conf[count].ref_cnt = 0;
6985 mi2s_intf_conf[count].msm_is_mi2s_master = 0;
6986 }
6987}
6988static int msm_asoc_machine_probe(struct platform_device *pdev)
6989{
6990 struct snd_soc_card *card;
6991 struct msm_asoc_mach_data *pdata;
6992 int ret;
6993 enum apr_subsys_state q6_state;
6994
6995 if (!pdev->dev.of_node) {
6996 dev_err(&pdev->dev, "No platform supplied from device tree\n");
6997 return -EINVAL;
6998 }
6999
7000 q6_state = apr_get_q6_state();
7001 if (q6_state == APR_SUBSYS_DOWN) {
7002 dev_dbg(&pdev->dev, "deferring %s, adsp_state %d\n",
7003 __func__, q6_state);
7004 return -EPROBE_DEFER;
7005 }
7006
7007 pdata = devm_kzalloc(&pdev->dev,
7008 sizeof(struct msm_asoc_mach_data), GFP_KERNEL);
7009 if (!pdata)
7010 return -ENOMEM;
7011
7012 card = populate_snd_card_dailinks(&pdev->dev);
7013 if (!card) {
7014 dev_err(&pdev->dev, "%s: Card uninitialized\n", __func__);
7015 ret = -EINVAL;
7016 goto err;
7017 }
7018 card->dev = &pdev->dev;
7019 platform_set_drvdata(pdev, card);
7020 snd_soc_card_set_drvdata(card, pdata);
7021
7022 ret = snd_soc_of_parse_card_name(card, "qcom,model");
7023 if (ret) {
7024 dev_err(&pdev->dev, "parse card name failed, err:%d\n",
7025 ret);
7026 goto err;
7027 }
7028
7029 ret = msm_populate_dai_link_component_of_node(card);
7030 if (ret) {
7031 ret = -EPROBE_DEFER;
7032 goto err;
7033 }
7034
7035 /* Populate controls of snd card */
7036 card->controls = msm_snd_controls;
7037 card->num_controls = ARRAY_SIZE(msm_snd_controls);
7038
7039 ret = msm_tdm_init(&pdev->dev);
7040 if (ret) {
7041 ret = -EPROBE_DEFER;
7042 goto err;
7043 }
7044
7045 ret = devm_snd_soc_register_card(&pdev->dev, card);
7046 if (ret == -EPROBE_DEFER) {
7047 goto err;
7048 } else if (ret) {
7049 dev_err(&pdev->dev, "snd_soc_register_card failed (%d)\n",
7050 ret);
7051 goto err;
7052 }
7053 dev_info(&pdev->dev, "Sound card %s registered\n", card->name);
7054
7055 /* Parse pinctrl info from devicetree */
7056 ret = msm_get_pinctrl(pdev);
7057 if (!ret) {
7058 pr_debug("%s: pinctrl parsing successful\n", __func__);
7059 } else {
7060 dev_dbg(&pdev->dev,
7061 "%s: Parsing pinctrl failed with %d. Cannot use Ports\n",
7062 __func__, ret);
7063 ret = 0;
7064 }
7065
7066 msm_i2s_auxpcm_init(pdev);
7067
7068 return 0;
7069err:
7070 msm_release_pinctrl(pdev);
7071 devm_kfree(&pdev->dev, pdata);
7072 return ret;
7073}
7074
7075static int msm_asoc_machine_remove(struct platform_device *pdev)
7076{
7077 msm_i2s_auxpcm_deinit();
7078
7079 msm_release_pinctrl(pdev);
7080 return 0;
7081}
7082
7083static struct platform_driver sa6155_asoc_machine_driver = {
7084 .driver = {
7085 .name = DRV_NAME,
7086 .owner = THIS_MODULE,
7087 .pm = &snd_soc_pm_ops,
7088 .of_match_table = sa6155_asoc_machine_of_match,
7089 },
7090 .probe = msm_asoc_machine_probe,
7091 .remove = msm_asoc_machine_remove,
7092};
7093
7094static int dummy_asoc_machine_probe(struct platform_device *pdev)
7095{
7096 return 0;
7097}
7098
7099static int dummy_asoc_machine_remove(struct platform_device *pdev)
7100{
7101 return 0;
7102}
7103
7104static struct platform_device sa6155_dummy_asoc_machine_device = {
7105 .name = "sa6155-asoc-snd-dummy",
7106};
7107
7108static struct platform_driver sa6155_dummy_asoc_machine_driver = {
7109 .driver = {
7110 .name = "sa6155-asoc-snd-dummy",
7111 .owner = THIS_MODULE,
7112 },
7113 .probe = dummy_asoc_machine_probe,
7114 .remove = dummy_asoc_machine_remove,
7115};
7116
7117static int sa6155_notifier_service_cb(struct notifier_block *this,
7118 unsigned long opcode, void *ptr)
7119{
7120 pr_debug("%s: Service opcode 0x%lx\n", __func__, opcode);
7121
7122 switch (opcode) {
7123 case AUDIO_NOTIFIER_SERVICE_DOWN:
7124 break;
7125 case AUDIO_NOTIFIER_SERVICE_UP:
7126 if (is_initial_boot) {
7127 platform_driver_register(&sa6155_dummy_asoc_machine_driver);
7128 platform_device_register(&sa6155_dummy_asoc_machine_device);
7129 is_initial_boot = false;
7130 }
7131 break;
7132 default:
7133 break;
7134 }
7135
7136 return NOTIFY_OK;
7137}
7138
7139static struct notifier_block service_nb = {
7140 .notifier_call = sa6155_notifier_service_cb,
7141 .priority = -INT_MAX,
7142};
7143
7144int __init sa6155_init(void)
7145{
7146 pr_debug("%s\n", __func__);
7147 audio_notifier_register("sa6155", AUDIO_NOTIFIER_ADSP_DOMAIN,
7148 &service_nb);
7149 return platform_driver_register(&sa6155_asoc_machine_driver);
7150}
7151
7152void sa6155_exit(void)
7153{
7154 pr_debug("%s\n", __func__);
7155 platform_driver_unregister(&sa6155_asoc_machine_driver);
7156 audio_notifier_deregister("sa6155");
7157}
7158
Rahul Sharmaf53de7f2019-03-03 22:30:47 +0530[diff] [blame^]7159module_init(sa6155_init);
7160module_exit(sa6155_exit);
7161
Rahul Sharma02bee732018-12-20 18:48:34 +0530[diff] [blame]7162MODULE_DESCRIPTION("ALSA SoC msm");
7163MODULE_LICENSE("GPL v2");
7164MODULE_ALIAS("platform:" DRV_NAME);
7165MODULE_DEVICE_TABLE(of, sa6155_asoc_machine_of_match);