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Ramjee Singh29973d72020-03-06 09:21:43 +05301/* Copyright (c) 2012-2018, 2020 The Linux Foundation. All rights reserved.
Asish Bhattacharya8e2277f2017-07-20 18:31:55 +05302 *
3 * This program is free software; you can redistribute it and/or modify
4 * it under the terms of the GNU General Public License version 2 and
5 * only version 2 as published by the Free Software Foundation.
6 *
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
11 */
12#ifndef _MSM_PCM_ROUTING_H
13#define _MSM_PCM_ROUTING_H
Laxminath Kasam605b42f2017-08-01 22:02:15 +053014#include <dsp/apr_audio-v2.h>
Asish Bhattacharya8e2277f2017-07-20 18:31:55 +053015
16/*
17 * These names are used by HAL to specify the BE. If any changes are
18 * made to the string names or the max name length corresponding
19 * changes need to be made in the HAL to ensure they still match.
20 */
21#define LPASS_BE_NAME_MAX_LENGTH 24
22#define LPASS_BE_PRI_I2S_RX "PRIMARY_I2S_RX"
23#define LPASS_BE_PRI_I2S_TX "PRIMARY_I2S_TX"
24#define LPASS_BE_SLIMBUS_0_RX "SLIMBUS_0_RX"
25#define LPASS_BE_SLIMBUS_0_TX "SLIMBUS_0_TX"
26#define LPASS_BE_HDMI "HDMI"
27#define LPASS_BE_DISPLAY_PORT "DISPLAY_PORT"
28#define LPASS_BE_INT_BT_SCO_RX "INT_BT_SCO_RX"
29#define LPASS_BE_INT_BT_SCO_TX "INT_BT_SCO_TX"
30#define LPASS_BE_INT_BT_A2DP_RX "INT_BT_A2DP_RX"
31#define LPASS_BE_INT_FM_RX "INT_FM_RX"
32#define LPASS_BE_INT_FM_TX "INT_FM_TX"
33#define LPASS_BE_AFE_PCM_RX "RT_PROXY_DAI_001_RX"
34#define LPASS_BE_AFE_PCM_TX "RT_PROXY_DAI_002_TX"
35#define LPASS_BE_AUXPCM_RX "AUX_PCM_RX"
36#define LPASS_BE_AUXPCM_TX "AUX_PCM_TX"
37#define LPASS_BE_SEC_AUXPCM_RX "SEC_AUX_PCM_RX"
38#define LPASS_BE_SEC_AUXPCM_TX "SEC_AUX_PCM_TX"
39#define LPASS_BE_TERT_AUXPCM_RX "TERT_AUX_PCM_RX"
40#define LPASS_BE_TERT_AUXPCM_TX "TERT_AUX_PCM_TX"
41#define LPASS_BE_QUAT_AUXPCM_RX "QUAT_AUX_PCM_RX"
42#define LPASS_BE_QUAT_AUXPCM_TX "QUAT_AUX_PCM_TX"
Rohit Kumara5077932017-09-10 22:05:05 +053043#define LPASS_BE_QUIN_AUXPCM_RX "QUIN_AUX_PCM_RX"
44#define LPASS_BE_QUIN_AUXPCM_TX "QUIN_AUX_PCM_TX"
Asish Bhattacharya8e2277f2017-07-20 18:31:55 +053045#define LPASS_BE_VOICE_PLAYBACK_TX "VOICE_PLAYBACK_TX"
46#define LPASS_BE_VOICE2_PLAYBACK_TX "VOICE2_PLAYBACK_TX"
47#define LPASS_BE_INCALL_RECORD_RX "INCALL_RECORD_RX"
48#define LPASS_BE_INCALL_RECORD_TX "INCALL_RECORD_TX"
49#define LPASS_BE_SEC_I2S_RX "SECONDARY_I2S_RX"
50#define LPASS_BE_SPDIF_RX "SPDIF_RX"
51
52#define LPASS_BE_MI2S_RX "MI2S_RX"
53#define LPASS_BE_MI2S_TX "MI2S_TX"
54#define LPASS_BE_QUAT_MI2S_RX "QUAT_MI2S_RX"
55#define LPASS_BE_QUAT_MI2S_TX "QUAT_MI2S_TX"
56#define LPASS_BE_SEC_MI2S_RX "SEC_MI2S_RX"
57#define LPASS_BE_SEC_MI2S_RX_SD1 "SEC_MI2S_RX_SD1"
58#define LPASS_BE_SEC_MI2S_TX "SEC_MI2S_TX"
59#define LPASS_BE_PRI_MI2S_RX "PRI_MI2S_RX"
60#define LPASS_BE_PRI_MI2S_TX "PRI_MI2S_TX"
Vatsal Bucha8968c5f2017-09-28 15:49:45 +053061#define LPASS_BE_TERT_MI2S_RX "TERT_MI2S_RX"
62#define LPASS_BE_TERT_MI2S_TX "TERT_MI2S_TX"
Asish Bhattacharya8e2277f2017-07-20 18:31:55 +053063#define LPASS_BE_AUDIO_I2S_RX "AUDIO_I2S_RX"
64#define LPASS_BE_STUB_RX "STUB_RX"
65#define LPASS_BE_STUB_TX "STUB_TX"
66#define LPASS_BE_SLIMBUS_1_RX "SLIMBUS_1_RX"
67#define LPASS_BE_SLIMBUS_1_TX "SLIMBUS_1_TX"
68#define LPASS_BE_STUB_1_TX "STUB_1_TX"
69#define LPASS_BE_SLIMBUS_2_RX "SLIMBUS_2_RX"
70#define LPASS_BE_SLIMBUS_2_TX "SLIMBUS_2_TX"
71#define LPASS_BE_SLIMBUS_3_RX "SLIMBUS_3_RX"
72#define LPASS_BE_SLIMBUS_3_TX "SLIMBUS_3_TX"
73#define LPASS_BE_SLIMBUS_4_RX "SLIMBUS_4_RX"
74#define LPASS_BE_SLIMBUS_4_TX "SLIMBUS_4_TX"
75#define LPASS_BE_SLIMBUS_TX_VI "SLIMBUS_TX_VI"
76#define LPASS_BE_SLIMBUS_5_RX "SLIMBUS_5_RX"
77#define LPASS_BE_SLIMBUS_5_TX "SLIMBUS_5_TX"
78#define LPASS_BE_SLIMBUS_6_RX "SLIMBUS_6_RX"
79#define LPASS_BE_SLIMBUS_6_TX "SLIMBUS_6_TX"
80#define LPASS_BE_QUIN_MI2S_RX "QUIN_MI2S_RX"
81#define LPASS_BE_QUIN_MI2S_TX "QUIN_MI2S_TX"
82#define LPASS_BE_SENARY_MI2S_TX "SENARY_MI2S_TX"
83
84#define LPASS_BE_PRI_TDM_RX_0 "PRI_TDM_RX_0"
85#define LPASS_BE_PRI_TDM_TX_0 "PRI_TDM_TX_0"
86#define LPASS_BE_PRI_TDM_RX_1 "PRI_TDM_RX_1"
87#define LPASS_BE_PRI_TDM_TX_1 "PRI_TDM_TX_1"
88#define LPASS_BE_PRI_TDM_RX_2 "PRI_TDM_RX_2"
89#define LPASS_BE_PRI_TDM_TX_2 "PRI_TDM_TX_2"
90#define LPASS_BE_PRI_TDM_RX_3 "PRI_TDM_RX_3"
91#define LPASS_BE_PRI_TDM_TX_3 "PRI_TDM_TX_3"
92#define LPASS_BE_PRI_TDM_RX_4 "PRI_TDM_RX_4"
93#define LPASS_BE_PRI_TDM_TX_4 "PRI_TDM_TX_4"
94#define LPASS_BE_PRI_TDM_RX_5 "PRI_TDM_RX_5"
95#define LPASS_BE_PRI_TDM_TX_5 "PRI_TDM_TX_5"
96#define LPASS_BE_PRI_TDM_RX_6 "PRI_TDM_RX_6"
97#define LPASS_BE_PRI_TDM_TX_6 "PRI_TDM_TX_6"
98#define LPASS_BE_PRI_TDM_RX_7 "PRI_TDM_RX_7"
99#define LPASS_BE_PRI_TDM_TX_7 "PRI_TDM_TX_7"
100#define LPASS_BE_SEC_TDM_RX_0 "SEC_TDM_RX_0"
101#define LPASS_BE_SEC_TDM_TX_0 "SEC_TDM_TX_0"
102#define LPASS_BE_SEC_TDM_RX_1 "SEC_TDM_RX_1"
103#define LPASS_BE_SEC_TDM_TX_1 "SEC_TDM_TX_1"
104#define LPASS_BE_SEC_TDM_RX_2 "SEC_TDM_RX_2"
105#define LPASS_BE_SEC_TDM_TX_2 "SEC_TDM_TX_2"
106#define LPASS_BE_SEC_TDM_RX_3 "SEC_TDM_RX_3"
107#define LPASS_BE_SEC_TDM_TX_3 "SEC_TDM_TX_3"
108#define LPASS_BE_SEC_TDM_RX_4 "SEC_TDM_RX_4"
109#define LPASS_BE_SEC_TDM_TX_4 "SEC_TDM_TX_4"
110#define LPASS_BE_SEC_TDM_RX_5 "SEC_TDM_RX_5"
111#define LPASS_BE_SEC_TDM_TX_5 "SEC_TDM_TX_5"
112#define LPASS_BE_SEC_TDM_RX_6 "SEC_TDM_RX_6"
113#define LPASS_BE_SEC_TDM_TX_6 "SEC_TDM_TX_6"
114#define LPASS_BE_SEC_TDM_RX_7 "SEC_TDM_RX_7"
115#define LPASS_BE_SEC_TDM_TX_7 "SEC_TDM_TX_7"
116#define LPASS_BE_TERT_TDM_RX_0 "TERT_TDM_RX_0"
117#define LPASS_BE_TERT_TDM_TX_0 "TERT_TDM_TX_0"
118#define LPASS_BE_TERT_TDM_RX_1 "TERT_TDM_RX_1"
119#define LPASS_BE_TERT_TDM_TX_1 "TERT_TDM_TX_1"
120#define LPASS_BE_TERT_TDM_RX_2 "TERT_TDM_RX_2"
121#define LPASS_BE_TERT_TDM_TX_2 "TERT_TDM_TX_2"
122#define LPASS_BE_TERT_TDM_RX_3 "TERT_TDM_RX_3"
123#define LPASS_BE_TERT_TDM_TX_3 "TERT_TDM_TX_3"
124#define LPASS_BE_TERT_TDM_RX_4 "TERT_TDM_RX_4"
125#define LPASS_BE_TERT_TDM_TX_4 "TERT_TDM_TX_4"
126#define LPASS_BE_TERT_TDM_RX_5 "TERT_TDM_RX_5"
127#define LPASS_BE_TERT_TDM_TX_5 "TERT_TDM_TX_5"
128#define LPASS_BE_TERT_TDM_RX_6 "TERT_TDM_RX_6"
129#define LPASS_BE_TERT_TDM_TX_6 "TERT_TDM_TX_6"
130#define LPASS_BE_TERT_TDM_RX_7 "TERT_TDM_RX_7"
131#define LPASS_BE_TERT_TDM_TX_7 "TERT_TDM_TX_7"
132#define LPASS_BE_QUAT_TDM_RX_0 "QUAT_TDM_RX_0"
133#define LPASS_BE_QUAT_TDM_TX_0 "QUAT_TDM_TX_0"
134#define LPASS_BE_QUAT_TDM_RX_1 "QUAT_TDM_RX_1"
135#define LPASS_BE_QUAT_TDM_TX_1 "QUAT_TDM_TX_1"
136#define LPASS_BE_QUAT_TDM_RX_2 "QUAT_TDM_RX_2"
137#define LPASS_BE_QUAT_TDM_TX_2 "QUAT_TDM_TX_2"
138#define LPASS_BE_QUAT_TDM_RX_3 "QUAT_TDM_RX_3"
139#define LPASS_BE_QUAT_TDM_TX_3 "QUAT_TDM_TX_3"
140#define LPASS_BE_QUAT_TDM_RX_4 "QUAT_TDM_RX_4"
141#define LPASS_BE_QUAT_TDM_TX_4 "QUAT_TDM_TX_4"
142#define LPASS_BE_QUAT_TDM_RX_5 "QUAT_TDM_RX_5"
143#define LPASS_BE_QUAT_TDM_TX_5 "QUAT_TDM_TX_5"
144#define LPASS_BE_QUAT_TDM_RX_6 "QUAT_TDM_RX_6"
145#define LPASS_BE_QUAT_TDM_TX_6 "QUAT_TDM_TX_6"
146#define LPASS_BE_QUAT_TDM_RX_7 "QUAT_TDM_RX_7"
147#define LPASS_BE_QUAT_TDM_TX_7 "QUAT_TDM_TX_7"
Raja Mallik425e1d32018-05-20 19:21:10 +0530148#define LPASS_BE_AFE_LOOPBACK_TX "AFE_LOOPBACK_TX"
Rohit Kumara5077932017-09-10 22:05:05 +0530149#define LPASS_BE_QUIN_TDM_RX_0 "QUIN_TDM_RX_0"
150#define LPASS_BE_QUIN_TDM_TX_0 "QUIN_TDM_TX_0"
151#define LPASS_BE_QUIN_TDM_RX_1 "QUIN_TDM_RX_1"
152#define LPASS_BE_QUIN_TDM_TX_1 "QUIN_TDM_TX_1"
153#define LPASS_BE_QUIN_TDM_RX_2 "QUIN_TDM_RX_2"
154#define LPASS_BE_QUIN_TDM_TX_2 "QUIN_TDM_TX_2"
155#define LPASS_BE_QUIN_TDM_RX_3 "QUIN_TDM_RX_3"
156#define LPASS_BE_QUIN_TDM_TX_3 "QUIN_TDM_TX_3"
157#define LPASS_BE_QUIN_TDM_RX_4 "QUIN_TDM_RX_4"
158#define LPASS_BE_QUIN_TDM_TX_4 "QUIN_TDM_TX_4"
159#define LPASS_BE_QUIN_TDM_RX_5 "QUIN_TDM_RX_5"
160#define LPASS_BE_QUIN_TDM_TX_5 "QUIN_TDM_TX_5"
161#define LPASS_BE_QUIN_TDM_RX_6 "QUIN_TDM_RX_6"
162#define LPASS_BE_QUIN_TDM_TX_6 "QUIN_TDM_TX_6"
163#define LPASS_BE_QUIN_TDM_RX_7 "QUIN_TDM_RX_7"
164#define LPASS_BE_QUIN_TDM_TX_7 "QUIN_TDM_TX_7"
Asish Bhattacharya8e2277f2017-07-20 18:31:55 +0530165
166#define LPASS_BE_SLIMBUS_7_RX "SLIMBUS_7_RX"
167#define LPASS_BE_SLIMBUS_7_TX "SLIMBUS_7_TX"
168#define LPASS_BE_SLIMBUS_8_RX "SLIMBUS_8_RX"
169#define LPASS_BE_SLIMBUS_8_TX "SLIMBUS_8_TX"
170
171#define LPASS_BE_USB_AUDIO_RX "USB_AUDIO_RX"
172#define LPASS_BE_USB_AUDIO_TX "USB_AUDIO_TX"
173
174#define LPASS_BE_INT0_MI2S_RX "INT0_MI2S_RX"
175#define LPASS_BE_INT0_MI2S_TX "INT0_MI2S_TX"
176#define LPASS_BE_INT1_MI2S_RX "INT1_MI2S_RX"
177#define LPASS_BE_INT1_MI2S_TX "INT1_MI2S_TX"
178#define LPASS_BE_INT2_MI2S_RX "INT2_MI2S_RX"
179#define LPASS_BE_INT2_MI2S_TX "INT2_MI2S_TX"
180#define LPASS_BE_INT3_MI2S_RX "INT3_MI2S_RX"
181#define LPASS_BE_INT3_MI2S_TX "INT3_MI2S_TX"
182#define LPASS_BE_INT4_MI2S_RX "INT4_MI2S_RX"
183#define LPASS_BE_INT4_MI2S_TX "INT4_MI2S_TX"
184#define LPASS_BE_INT5_MI2S_RX "INT5_MI2S_RX"
185#define LPASS_BE_INT5_MI2S_TX "INT5_MI2S_TX"
186#define LPASS_BE_INT6_MI2S_RX "INT6_MI2S_RX"
187#define LPASS_BE_INT6_MI2S_TX "INT6_MI2S_TX"
188/* For multimedia front-ends, asm session is allocated dynamically.
189 * Hence, asm session/multimedia front-end mapping has to be maintained.
190 * Due to this reason, additional multimedia front-end must be placed before
191 * non-multimedia front-ends.
192 */
193
194enum {
195 MSM_FRONTEND_DAI_MULTIMEDIA1 = 0,
196 MSM_FRONTEND_DAI_MULTIMEDIA2,
197 MSM_FRONTEND_DAI_MULTIMEDIA3,
198 MSM_FRONTEND_DAI_MULTIMEDIA4,
199 MSM_FRONTEND_DAI_MULTIMEDIA5,
200 MSM_FRONTEND_DAI_MULTIMEDIA6,
201 MSM_FRONTEND_DAI_MULTIMEDIA7,
202 MSM_FRONTEND_DAI_MULTIMEDIA8,
203 MSM_FRONTEND_DAI_MULTIMEDIA9,
204 MSM_FRONTEND_DAI_MULTIMEDIA10,
205 MSM_FRONTEND_DAI_MULTIMEDIA11,
206 MSM_FRONTEND_DAI_MULTIMEDIA12,
207 MSM_FRONTEND_DAI_MULTIMEDIA13,
208 MSM_FRONTEND_DAI_MULTIMEDIA14,
209 MSM_FRONTEND_DAI_MULTIMEDIA15,
210 MSM_FRONTEND_DAI_MULTIMEDIA16,
211 MSM_FRONTEND_DAI_MULTIMEDIA17,
212 MSM_FRONTEND_DAI_MULTIMEDIA18,
213 MSM_FRONTEND_DAI_MULTIMEDIA19,
214 MSM_FRONTEND_DAI_MULTIMEDIA20,
Sachin Mohan Gadag265d94d2018-01-04 11:04:00 +0530215 MSM_FRONTEND_DAI_MULTIMEDIA28,
216 MSM_FRONTEND_DAI_MULTIMEDIA29,
Ramjee Singh29973d72020-03-06 09:21:43 +0530217 MSM_FRONTEND_DAI_MULTIMEDIA30,
Asish Bhattacharya8e2277f2017-07-20 18:31:55 +0530218 MSM_FRONTEND_DAI_VOIP,
219 MSM_FRONTEND_DAI_AFE_RX,
220 MSM_FRONTEND_DAI_AFE_TX,
221 MSM_FRONTEND_DAI_VOICE_STUB,
Asish Bhattacharya8e2277f2017-07-20 18:31:55 +0530222 MSM_FRONTEND_DAI_DTMF_RX,
Asish Bhattacharya8e2277f2017-07-20 18:31:55 +0530223 MSM_FRONTEND_DAI_QCHAT,
224 MSM_FRONTEND_DAI_VOLTE_STUB,
225 MSM_FRONTEND_DAI_LSM1,
226 MSM_FRONTEND_DAI_LSM2,
227 MSM_FRONTEND_DAI_LSM3,
228 MSM_FRONTEND_DAI_LSM4,
229 MSM_FRONTEND_DAI_LSM5,
230 MSM_FRONTEND_DAI_LSM6,
231 MSM_FRONTEND_DAI_LSM7,
232 MSM_FRONTEND_DAI_LSM8,
233 MSM_FRONTEND_DAI_VOICE2_STUB,
Asish Bhattacharya8e2277f2017-07-20 18:31:55 +0530234 MSM_FRONTEND_DAI_VOICEMMODE1,
235 MSM_FRONTEND_DAI_VOICEMMODE2,
236 MSM_FRONTEND_DAI_MAX,
237};
238
Ramjee Singh29973d72020-03-06 09:21:43 +0530239#define MSM_FRONTEND_DAI_MM_SIZE (MSM_FRONTEND_DAI_MULTIMEDIA30 + 1)
240#define MSM_FRONTEND_DAI_MM_MAX_ID MSM_FRONTEND_DAI_MULTIMEDIA30
Asish Bhattacharya8e2277f2017-07-20 18:31:55 +0530241
242enum {
243 MSM_BACKEND_DAI_PRI_I2S_RX = 0,
244 MSM_BACKEND_DAI_PRI_I2S_TX,
245 MSM_BACKEND_DAI_SLIMBUS_0_RX,
246 MSM_BACKEND_DAI_SLIMBUS_0_TX,
247 MSM_BACKEND_DAI_HDMI_RX,
248 MSM_BACKEND_DAI_INT_BT_SCO_RX,
249 MSM_BACKEND_DAI_INT_BT_SCO_TX,
250 MSM_BACKEND_DAI_INT_FM_RX,
251 MSM_BACKEND_DAI_INT_FM_TX,
252 MSM_BACKEND_DAI_AFE_PCM_RX,
253 MSM_BACKEND_DAI_AFE_PCM_TX,
254 MSM_BACKEND_DAI_AUXPCM_RX,
255 MSM_BACKEND_DAI_AUXPCM_TX,
256 MSM_BACKEND_DAI_VOICE_PLAYBACK_TX,
257 MSM_BACKEND_DAI_VOICE2_PLAYBACK_TX,
258 MSM_BACKEND_DAI_INCALL_RECORD_RX,
259 MSM_BACKEND_DAI_INCALL_RECORD_TX,
260 MSM_BACKEND_DAI_MI2S_RX,
261 MSM_BACKEND_DAI_MI2S_TX,
262 MSM_BACKEND_DAI_SEC_I2S_RX,
263 MSM_BACKEND_DAI_SLIMBUS_1_RX,
264 MSM_BACKEND_DAI_SLIMBUS_1_TX,
265 MSM_BACKEND_DAI_SLIMBUS_2_RX,
266 MSM_BACKEND_DAI_SLIMBUS_2_TX,
267 MSM_BACKEND_DAI_SLIMBUS_3_RX,
268 MSM_BACKEND_DAI_SLIMBUS_3_TX,
269 MSM_BACKEND_DAI_SLIMBUS_4_RX,
270 MSM_BACKEND_DAI_SLIMBUS_4_TX,
271 MSM_BACKEND_DAI_SLIMBUS_5_RX,
272 MSM_BACKEND_DAI_SLIMBUS_5_TX,
273 MSM_BACKEND_DAI_SLIMBUS_6_RX,
274 MSM_BACKEND_DAI_SLIMBUS_6_TX,
275 MSM_BACKEND_DAI_SLIMBUS_7_RX,
276 MSM_BACKEND_DAI_SLIMBUS_7_TX,
277 MSM_BACKEND_DAI_SLIMBUS_8_RX,
278 MSM_BACKEND_DAI_SLIMBUS_8_TX,
279 MSM_BACKEND_DAI_EXTPROC_RX,
280 MSM_BACKEND_DAI_EXTPROC_TX,
281 MSM_BACKEND_DAI_EXTPROC_EC_TX,
282 MSM_BACKEND_DAI_QUATERNARY_MI2S_RX,
283 MSM_BACKEND_DAI_QUATERNARY_MI2S_TX,
284 MSM_BACKEND_DAI_SECONDARY_MI2S_RX,
285 MSM_BACKEND_DAI_SECONDARY_MI2S_TX,
286 MSM_BACKEND_DAI_PRI_MI2S_RX,
287 MSM_BACKEND_DAI_PRI_MI2S_TX,
288 MSM_BACKEND_DAI_TERTIARY_MI2S_RX,
289 MSM_BACKEND_DAI_TERTIARY_MI2S_TX,
290 MSM_BACKEND_DAI_AUDIO_I2S_RX,
291 MSM_BACKEND_DAI_SEC_AUXPCM_RX,
292 MSM_BACKEND_DAI_SEC_AUXPCM_TX,
293 MSM_BACKEND_DAI_SPDIF_RX,
294 MSM_BACKEND_DAI_SECONDARY_MI2S_RX_SD1,
295 MSM_BACKEND_DAI_QUINARY_MI2S_RX,
296 MSM_BACKEND_DAI_QUINARY_MI2S_TX,
297 MSM_BACKEND_DAI_SENARY_MI2S_TX,
298 MSM_BACKEND_DAI_PRI_TDM_RX_0,
299 MSM_BACKEND_DAI_PRI_TDM_TX_0,
300 MSM_BACKEND_DAI_PRI_TDM_RX_1,
301 MSM_BACKEND_DAI_PRI_TDM_TX_1,
302 MSM_BACKEND_DAI_PRI_TDM_RX_2,
303 MSM_BACKEND_DAI_PRI_TDM_TX_2,
304 MSM_BACKEND_DAI_PRI_TDM_RX_3,
305 MSM_BACKEND_DAI_PRI_TDM_TX_3,
306 MSM_BACKEND_DAI_PRI_TDM_RX_4,
307 MSM_BACKEND_DAI_PRI_TDM_TX_4,
308 MSM_BACKEND_DAI_PRI_TDM_RX_5,
309 MSM_BACKEND_DAI_PRI_TDM_TX_5,
310 MSM_BACKEND_DAI_PRI_TDM_RX_6,
311 MSM_BACKEND_DAI_PRI_TDM_TX_6,
312 MSM_BACKEND_DAI_PRI_TDM_RX_7,
313 MSM_BACKEND_DAI_PRI_TDM_TX_7,
314 MSM_BACKEND_DAI_SEC_TDM_RX_0,
315 MSM_BACKEND_DAI_SEC_TDM_TX_0,
316 MSM_BACKEND_DAI_SEC_TDM_RX_1,
317 MSM_BACKEND_DAI_SEC_TDM_TX_1,
318 MSM_BACKEND_DAI_SEC_TDM_RX_2,
319 MSM_BACKEND_DAI_SEC_TDM_TX_2,
320 MSM_BACKEND_DAI_SEC_TDM_RX_3,
321 MSM_BACKEND_DAI_SEC_TDM_TX_3,
322 MSM_BACKEND_DAI_SEC_TDM_RX_4,
323 MSM_BACKEND_DAI_SEC_TDM_TX_4,
324 MSM_BACKEND_DAI_SEC_TDM_RX_5,
325 MSM_BACKEND_DAI_SEC_TDM_TX_5,
326 MSM_BACKEND_DAI_SEC_TDM_RX_6,
327 MSM_BACKEND_DAI_SEC_TDM_TX_6,
328 MSM_BACKEND_DAI_SEC_TDM_RX_7,
329 MSM_BACKEND_DAI_SEC_TDM_TX_7,
330 MSM_BACKEND_DAI_TERT_TDM_RX_0,
331 MSM_BACKEND_DAI_TERT_TDM_TX_0,
332 MSM_BACKEND_DAI_TERT_TDM_RX_1,
333 MSM_BACKEND_DAI_TERT_TDM_TX_1,
334 MSM_BACKEND_DAI_TERT_TDM_RX_2,
335 MSM_BACKEND_DAI_TERT_TDM_TX_2,
336 MSM_BACKEND_DAI_TERT_TDM_RX_3,
337 MSM_BACKEND_DAI_TERT_TDM_TX_3,
338 MSM_BACKEND_DAI_TERT_TDM_RX_4,
339 MSM_BACKEND_DAI_TERT_TDM_TX_4,
340 MSM_BACKEND_DAI_TERT_TDM_RX_5,
341 MSM_BACKEND_DAI_TERT_TDM_TX_5,
342 MSM_BACKEND_DAI_TERT_TDM_RX_6,
343 MSM_BACKEND_DAI_TERT_TDM_TX_6,
344 MSM_BACKEND_DAI_TERT_TDM_RX_7,
345 MSM_BACKEND_DAI_TERT_TDM_TX_7,
346 MSM_BACKEND_DAI_QUAT_TDM_RX_0,
347 MSM_BACKEND_DAI_QUAT_TDM_TX_0,
348 MSM_BACKEND_DAI_QUAT_TDM_RX_1,
349 MSM_BACKEND_DAI_QUAT_TDM_TX_1,
350 MSM_BACKEND_DAI_QUAT_TDM_RX_2,
351 MSM_BACKEND_DAI_QUAT_TDM_TX_2,
352 MSM_BACKEND_DAI_QUAT_TDM_RX_3,
353 MSM_BACKEND_DAI_QUAT_TDM_TX_3,
354 MSM_BACKEND_DAI_QUAT_TDM_RX_4,
355 MSM_BACKEND_DAI_QUAT_TDM_TX_4,
356 MSM_BACKEND_DAI_QUAT_TDM_RX_5,
357 MSM_BACKEND_DAI_QUAT_TDM_TX_5,
358 MSM_BACKEND_DAI_QUAT_TDM_RX_6,
359 MSM_BACKEND_DAI_QUAT_TDM_TX_6,
360 MSM_BACKEND_DAI_QUAT_TDM_RX_7,
361 MSM_BACKEND_DAI_QUAT_TDM_TX_7,
Rohit Kumara5077932017-09-10 22:05:05 +0530362 MSM_BACKEND_DAI_QUIN_TDM_RX_0,
363 MSM_BACKEND_DAI_QUIN_TDM_TX_0,
364 MSM_BACKEND_DAI_QUIN_TDM_RX_1,
365 MSM_BACKEND_DAI_QUIN_TDM_TX_1,
366 MSM_BACKEND_DAI_QUIN_TDM_RX_2,
367 MSM_BACKEND_DAI_QUIN_TDM_TX_2,
368 MSM_BACKEND_DAI_QUIN_TDM_RX_3,
369 MSM_BACKEND_DAI_QUIN_TDM_TX_3,
370 MSM_BACKEND_DAI_QUIN_TDM_RX_4,
371 MSM_BACKEND_DAI_QUIN_TDM_TX_4,
372 MSM_BACKEND_DAI_QUIN_TDM_RX_5,
373 MSM_BACKEND_DAI_QUIN_TDM_TX_5,
374 MSM_BACKEND_DAI_QUIN_TDM_RX_6,
375 MSM_BACKEND_DAI_QUIN_TDM_TX_6,
376 MSM_BACKEND_DAI_QUIN_TDM_RX_7,
377 MSM_BACKEND_DAI_QUIN_TDM_TX_7,
Asish Bhattacharya8e2277f2017-07-20 18:31:55 +0530378 MSM_BACKEND_DAI_INT_BT_A2DP_RX,
379 MSM_BACKEND_DAI_USB_RX,
380 MSM_BACKEND_DAI_USB_TX,
381 MSM_BACKEND_DAI_DISPLAY_PORT_RX,
382 MSM_BACKEND_DAI_TERT_AUXPCM_RX,
383 MSM_BACKEND_DAI_TERT_AUXPCM_TX,
384 MSM_BACKEND_DAI_QUAT_AUXPCM_RX,
385 MSM_BACKEND_DAI_QUAT_AUXPCM_TX,
Rohit Kumara5077932017-09-10 22:05:05 +0530386 MSM_BACKEND_DAI_QUIN_AUXPCM_RX,
387 MSM_BACKEND_DAI_QUIN_AUXPCM_TX,
Asish Bhattacharya8e2277f2017-07-20 18:31:55 +0530388 MSM_BACKEND_DAI_INT0_MI2S_RX,
389 MSM_BACKEND_DAI_INT0_MI2S_TX,
390 MSM_BACKEND_DAI_INT1_MI2S_RX,
391 MSM_BACKEND_DAI_INT1_MI2S_TX,
392 MSM_BACKEND_DAI_INT2_MI2S_RX,
393 MSM_BACKEND_DAI_INT2_MI2S_TX,
394 MSM_BACKEND_DAI_INT3_MI2S_RX,
395 MSM_BACKEND_DAI_INT3_MI2S_TX,
396 MSM_BACKEND_DAI_INT4_MI2S_RX,
397 MSM_BACKEND_DAI_INT4_MI2S_TX,
398 MSM_BACKEND_DAI_INT5_MI2S_RX,
399 MSM_BACKEND_DAI_INT5_MI2S_TX,
400 MSM_BACKEND_DAI_INT6_MI2S_RX,
401 MSM_BACKEND_DAI_INT6_MI2S_TX,
Raja Mallik425e1d32018-05-20 19:21:10 +0530402 MSM_BACKEND_DAI_AFE_LOOPBACK_TX,
Asish Bhattacharya8e2277f2017-07-20 18:31:55 +0530403 MSM_BACKEND_DAI_MAX,
404};
405
406enum msm_pcm_routing_event {
407 MSM_PCM_RT_EVT_BUF_RECFG,
408 MSM_PCM_RT_EVT_DEVSWITCH,
409 MSM_PCM_RT_EVT_MAX,
410};
411
412enum {
413 EXT_EC_REF_NONE = 0,
414 EXT_EC_REF_PRI_MI2S_TX,
415 EXT_EC_REF_SEC_MI2S_TX,
416 EXT_EC_REF_TERT_MI2S_TX,
417 EXT_EC_REF_QUAT_MI2S_TX,
418 EXT_EC_REF_QUIN_MI2S_TX,
419 EXT_EC_REF_SLIM_1_TX,
420};
421
422#define INVALID_SESSION -1
423#define SESSION_TYPE_RX 0
424#define SESSION_TYPE_TX 1
425#define MAX_SESSION_TYPES 2
426#define INT_RX_VOL_MAX_STEPS 0x2000
427#define INT_RX_VOL_GAIN 0x2000
428
429#define RELEASE_LOCK 0
430#define ACQUIRE_LOCK 1
431
432#define MSM_BACKEND_DAI_PP_PARAMS_REQ_MAX 2
433#define HDMI_RX_ID 0x8001
434#define ADM_PP_PARAM_MUTE_ID 0
435#define ADM_PP_PARAM_MUTE_BIT 1
436#define ADM_PP_PARAM_LATENCY_ID 1
437#define ADM_PP_PARAM_LATENCY_BIT 2
438#define BE_DAI_PORT_SESSIONS_IDX_MAX 4
439#define BE_DAI_FE_SESSIONS_IDX_MAX 2
440
Aditya Bavanari2a627ae2017-11-21 20:24:53 +0530441enum {
442 ADM_TOPOLOGY_CAL_TYPE_IDX = 0,
443 ADM_LSM_TOPOLOGY_CAL_TYPE_IDX,
444 MAX_ROUTING_CAL_TYPES
445};
446
Asish Bhattacharya8e2277f2017-07-20 18:31:55 +0530447struct msm_pcm_routing_evt {
448 void (*event_func)(enum msm_pcm_routing_event, void *);
449 void *priv_data;
450};
451
452struct msm_pcm_routing_bdai_data {
453 u16 port_id; /* AFE port ID */
454 u8 active; /* track if this backend is enabled */
455
456 /* Front-end sessions */
457 unsigned long fe_sessions[BE_DAI_FE_SESSIONS_IDX_MAX];
458 /*
459 * Track Tx BE ports -> Rx BE ports.
460 * port_sessions[0] used to track BE 0 to BE 63.
461 * port_sessions[1] used to track BE 64 to BE 127.
462 * port_sessions[2] used to track BE 128 to BE 191.
463 * port_sessions[3] used to track BE 192 to BE 255.
464 */
465 u64 port_sessions[BE_DAI_PORT_SESSIONS_IDX_MAX];
466
467 unsigned int sample_rate;
468 unsigned int channel;
469 unsigned int format;
470 unsigned int adm_override_ch;
471 u32 passthr_mode[MSM_FRONTEND_DAI_MAX];
472 char *name;
473};
474
475struct msm_pcm_routing_fdai_data {
476 u16 be_srate; /* track prior backend sample rate for flushing purpose */
477 int strm_id; /* ASM stream ID */
478 int perf_mode;
479 struct msm_pcm_routing_evt event_info;
480};
481
482#define MAX_APP_TYPES 16
483struct msm_pcm_routing_app_type_data {
484 int app_type;
485 u32 sample_rate;
486 int bit_width;
487};
488
489struct msm_pcm_stream_app_type_cfg {
490 int app_type;
491 int acdb_dev_id;
492 int sample_rate;
493};
494
495/* dai_id: front-end ID,
496 * dspst_id: DSP audio stream ID
497 * stream_type: playback or capture
498 */
499int msm_pcm_routing_reg_phy_stream(int fedai_id, int perf_mode, int dspst_id,
500 int stream_type);
501void msm_pcm_routing_reg_psthr_stream(int fedai_id, int dspst_id,
502 int stream_type);
503int msm_pcm_routing_reg_phy_compr_stream(int fedai_id, int perf_mode,
504 int dspst_id, int stream_type,
505 uint32_t compr_passthr);
506
507int msm_pcm_routing_reg_phy_stream_v2(int fedai_id, int perf_mode,
508 int dspst_id, int stream_type,
509 struct msm_pcm_routing_evt event_info);
510
511void msm_pcm_routing_dereg_phy_stream(int fedai_id, int stream_type);
512
513int msm_routing_check_backend_enabled(int fedai_id);
514
515
516void msm_pcm_routing_get_bedai_info(int be_idx,
517 struct msm_pcm_routing_bdai_data *bedai);
518void msm_pcm_routing_get_fedai_info(int fe_idx, int sess_type,
519 struct msm_pcm_routing_fdai_data *fe_dai);
520void msm_pcm_routing_acquire_lock(void);
521void msm_pcm_routing_release_lock(void);
522
523int msm_pcm_routing_reg_stream_app_type_cfg(
524 int fedai_id, int session_type, int be_id,
525 struct msm_pcm_stream_app_type_cfg *cfg_data);
526int msm_pcm_routing_get_stream_app_type_cfg(
527 int fedai_id, int session_type, int *be_id,
528 struct msm_pcm_stream_app_type_cfg *cfg_data);
Dhanalakshmi Siddani040e0262018-11-26 23:01:26 +0530529int msm_pcm_routing_send_chmix_cfg(int fe_id, int ip_channel_cnt,
530 int op_channel_cnt, int *ch_wght_coeff,
531 int session_type, bool use_default_chmap,
532 char *channel_map);
Asish Bhattacharya8e2277f2017-07-20 18:31:55 +0530533#endif /*_MSM_PCM_H*/