commit 09d5dd08f397baa35c40ae933d6c49e1d85979af
author Karthick S <skarthic@qti.qualcomm.com> Wed May 27 16:58:32 2015 +0530
committer Satyanarayana Dash <c_sadash@qti.qualcomm.com> Wed Jun 03 18:56:23 2015 +0530
tree c82689be3cdaacd14c4fef2f2467a86c2f72ea55
parent 19bbdbad2f9bbb217868052bc492fe73c1250e92

DXE Sync: Use PMU SPARE register bit 26 for sync

The host and firmware will use the PMU SPARE OUT register for
synchronization instead of DXE global CSR register when mgmt frame
logging is enabled.

Change-Id: I4fb68a95268f80976cab8a9850c880ed63df3317
CRs-Fixed: 843058

CORE/DXE/src/wlan_qct_dxe.c

diff --git a/CORE/DXE/src/wlan_qct_dxe.c b/CORE/DXE/src/wlan_qct_dxe.c
index d4d2696..1bcfaf5 100644
--- a/CORE/DXE/src/wlan_qct_dxe.c
+++ b/CORE/DXE/src/wlan_qct_dxe.c
@@ -2748,9 +2748,9 @@
    }
    else
    {
-      wpalReadRegister(WALNDEX_DMA_CSR_ADDRESS, &regValue);
-      regValue &= ~WLANDXE_RX_INTERRUPT_HANDLE_MASK;
-      wpalWriteRegister(WALNDEX_DMA_CSR_ADDRESS, regValue);
+      wpalReadRegister(WLAN_PMU_SPARE_OUT_ADDRESS, &regValue);
+      regValue &= (~WLAN_PMU_POWER_DOWN_MASK);
+      wpalWriteRegister(WLAN_PMU_SPARE_OUT_ADDRESS, regValue);
    }
 
    /* Enable system level ISR */
@@ -2897,9 +2897,9 @@
    }
    else
    {
-      wpalReadRegister(WALNDEX_DMA_CSR_ADDRESS, &regValue);
-      regValue |= WLANDXE_RX_INTERRUPT_HANDLE_MASK;
-      wpalWriteRegister(WALNDEX_DMA_CSR_ADDRESS, regValue);
+      wpalReadRegister(WLAN_PMU_SPARE_OUT_ADDRESS, &regValue);
+      regValue |= WLAN_PMU_POWER_DOWN_MASK;
+      wpalWriteRegister(WLAN_PMU_SPARE_OUT_ADDRESS, regValue);
    }
 
    /* Disable interrupt at here

CORE/DXE/src/wlan_qct_dxe_i.h

diff --git a/CORE/DXE/src/wlan_qct_dxe_i.h b/CORE/DXE/src/wlan_qct_dxe_i.h
index d4753dd..dacc1e1 100644
--- a/CORE/DXE/src/wlan_qct_dxe_i.h
+++ b/CORE/DXE/src/wlan_qct_dxe_i.h
@@ -103,6 +103,9 @@
 
 #define WLANDXE_REGISTER_BASE_ADDRESS     0x202000
 
+#define WLAN_PMU_SPARE_OUT_ADDRESS        0x21c088
+#define WLAN_PMU_POWER_DOWN_MASK          0x04000000
+
 /* Common over the channels register addresses */
 #define WALNDEX_DMA_CSR_ADDRESS          (WLANDXE_REGISTER_BASE_ADDRESS + 0x00)
 #define WALNDEX_DMA_ENCH_ADDRESS         (WLANDXE_REGISTER_BASE_ADDRESS + 0x04)
@@ -171,7 +174,6 @@
 #define WLANDXE_DMA_CSR_RESERVED_OFFSET       0x10
 #define WLANDXE_DMA_CSR_RESERVED_DEFAULT      0x0
 
-#define WLANDXE_RX_INTERRUPT_HANDLE_MASK      0x80000
 
 #define WLANDXE_DMA_CSR_H2H_SYNC_EN_MASK      0x8000
 #define WLANDXE_DMA_CSR_H2H_SYNC_EN_OFFSET    0x0F