Jeff Johnson | 295189b | 2012-06-20 16:38:30 -0700 | [diff] [blame] | 1 | /* |
Mihir Shete | 96cd190 | 2015-03-04 15:47:31 +0530 | [diff] [blame] | 2 | * Copyright (c) 2012-2015 The Linux Foundation. All rights reserved. |
Kiet Lam | 842dad0 | 2014-02-18 18:44:02 -0800 | [diff] [blame] | 3 | * |
| 4 | * Previously licensed under the ISC license by Qualcomm Atheros, Inc. |
| 5 | * |
| 6 | * |
| 7 | * Permission to use, copy, modify, and/or distribute this software for |
| 8 | * any purpose with or without fee is hereby granted, provided that the |
| 9 | * above copyright notice and this permission notice appear in all |
| 10 | * copies. |
| 11 | * |
| 12 | * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL |
| 13 | * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED |
| 14 | * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE |
| 15 | * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL |
| 16 | * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR |
| 17 | * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER |
| 18 | * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR |
| 19 | * PERFORMANCE OF THIS SOFTWARE. |
Gopichand Nakkala | 92f07d8 | 2013-01-08 21:16:34 -0800 | [diff] [blame] | 20 | */ |
Kiet Lam | 842dad0 | 2014-02-18 18:44:02 -0800 | [diff] [blame] | 21 | |
| 22 | /* |
| 23 | * This file was originally distributed by Qualcomm Atheros, Inc. |
| 24 | * under proprietary terms before Copyright ownership was assigned |
| 25 | * to the Linux Foundation. |
| 26 | */ |
| 27 | |
Jeff Johnson | 295189b | 2012-06-20 16:38:30 -0700 | [diff] [blame] | 28 | /**========================================================================= |
| 29 | |
| 30 | @file wlan_qct_dxe_cfg_i.c |
| 31 | |
| 32 | @brief |
| 33 | |
| 34 | This file contains the external API exposed by the wlan data transfer abstraction layer module. |
Jeff Johnson | 295189b | 2012-06-20 16:38:30 -0700 | [diff] [blame] | 35 | ========================================================================*/ |
| 36 | |
| 37 | /*=========================================================================== |
| 38 | |
| 39 | EDIT HISTORY FOR FILE |
| 40 | |
| 41 | |
| 42 | This section contains comments describing changes made to the module. |
| 43 | Notice that changes are listed in reverse chronological order. |
| 44 | |
| 45 | |
| 46 | $Header:$ $DateTime: $ $Author: $ |
| 47 | |
| 48 | |
| 49 | when who what, where, why |
| 50 | -------- --- ---------------------------------------------------------- |
| 51 | 08/03/10 schang Created module. |
| 52 | |
| 53 | ===========================================================================*/ |
| 54 | |
| 55 | /*=========================================================================== |
| 56 | |
| 57 | INCLUDE FILES FOR MODULE |
| 58 | |
| 59 | ===========================================================================*/ |
| 60 | |
| 61 | /*---------------------------------------------------------------------------- |
| 62 | * Include Files |
| 63 | * -------------------------------------------------------------------------*/ |
| 64 | #include "wlan_qct_dxe_i.h" |
| 65 | |
| 66 | /*---------------------------------------------------------------------------- |
| 67 | * Preprocessor Definitions and Constants |
| 68 | * -------------------------------------------------------------------------*/ |
| 69 | typedef struct |
| 70 | { |
| 71 | WDTS_ChannelType wlanChannel; |
| 72 | WLANDXE_DMAChannelType DMAChannel; |
| 73 | WLANDXE_ChannelConfigType *channelConfig; |
| 74 | } WLANDXE_ChannelMappingType; |
| 75 | |
| 76 | wpt_uint32 channelBaseAddressList[WLANDXE_DMA_CHANNEL_MAX] = |
| 77 | { |
| 78 | WLANDXE_DMA_CHAN0_BASE_ADDRESS, |
| 79 | WLANDXE_DMA_CHAN1_BASE_ADDRESS, |
| 80 | WLANDXE_DMA_CHAN2_BASE_ADDRESS, |
| 81 | WLANDXE_DMA_CHAN3_BASE_ADDRESS, |
| 82 | WLANDXE_DMA_CHAN4_BASE_ADDRESS, |
| 83 | WLANDXE_DMA_CHAN5_BASE_ADDRESS, |
| 84 | WLANDXE_DMA_CHAN6_BASE_ADDRESS |
| 85 | }; |
| 86 | |
| 87 | wpt_uint32 channelInterruptMask[WLANDXE_DMA_CHANNEL_MAX] = |
| 88 | { |
| 89 | WLANDXE_INT_MASK_CHAN_0, |
| 90 | WLANDXE_INT_MASK_CHAN_1, |
| 91 | WLANDXE_INT_MASK_CHAN_2, |
| 92 | WLANDXE_INT_MASK_CHAN_3, |
| 93 | WLANDXE_INT_MASK_CHAN_4, |
| 94 | WLANDXE_INT_MASK_CHAN_5, |
| 95 | WLANDXE_INT_MASK_CHAN_6 |
| 96 | }; |
| 97 | |
| 98 | WLANDXE_ChannelConfigType chanTXLowPriConfig = |
| 99 | { |
| 100 | /* Q handle type, Circular */ |
| 101 | WLANDXE_CHANNEL_HANDLE_CIRCULA, |
| 102 | |
| 103 | /* Number of Descriptor, NOT CLEAR YET !!! */ |
| 104 | WLANDXE_LO_PRI_RES_NUM , |
| 105 | |
| 106 | /* MAX num RX Buffer */ |
| 107 | 0, |
| 108 | |
| 109 | /* Reference WQ, TX23 */ |
| 110 | 23, |
| 111 | |
| 112 | /* USB Only, End point info */ |
| 113 | 0, |
| 114 | |
| 115 | /* Transfer Type */ |
| 116 | WLANDXE_DESC_CTRL_XTYPE_H2B, |
| 117 | |
| 118 | /* Channel Priority 7(Highest) - 0(Lowest) NOT CLEAR YET !!! */ |
| 119 | 4, |
| 120 | |
| 121 | /* BD attached to frames for this pipe */ |
| 122 | eWLAN_PAL_TRUE, |
| 123 | |
| 124 | /* chk_size, NOT CLEAR YET !!!*/ |
| 125 | 0, |
| 126 | |
| 127 | /* bmuThdSel, NOT CLEAR YET !!! */ |
| 128 | 5, |
| 129 | |
| 130 | /* Added in Gen5 for Prefetch, NOT CLEAR YET !!! */ |
| 131 | eWLAN_PAL_TRUE, |
| 132 | |
| 133 | /* Use short Descriptor */ |
| 134 | eWLAN_PAL_TRUE |
| 135 | }; |
| 136 | |
| 137 | WLANDXE_ChannelConfigType chanTXHighPriConfig = |
| 138 | { |
| 139 | /* Q handle type, Circular */ |
| 140 | WLANDXE_CHANNEL_HANDLE_CIRCULA, |
| 141 | |
| 142 | /* Number of Descriptor, NOT CLEAR YET !!! */ |
| 143 | WLANDXE_HI_PRI_RES_NUM , |
| 144 | |
| 145 | /* MAX num RX Buffer */ |
| 146 | 0, |
| 147 | |
| 148 | /* Reference WQ, TX23 */ |
| 149 | 23, |
| 150 | |
| 151 | /* USB Only, End point info */ |
| 152 | 0, |
| 153 | |
| 154 | /* Transfer Type */ |
| 155 | WLANDXE_DESC_CTRL_XTYPE_H2B, |
| 156 | |
| 157 | /* Channel Priority 7(Highest) - 0(Lowest), NOT CLEAR YET !!! */ |
| 158 | 6, |
| 159 | |
| 160 | /* BD attached to frames for this pipe */ |
| 161 | eWLAN_PAL_TRUE, |
| 162 | |
| 163 | /* chk_size, NOT CLEAR YET !!!*/ |
| 164 | 0, |
| 165 | |
| 166 | /* bmuThdSel, NOT CLEAR YET !!! */ |
| 167 | 7, |
| 168 | |
| 169 | /* Added in Gen5 for Prefetch, NOT CLEAR YET !!!*/ |
| 170 | eWLAN_PAL_TRUE, |
| 171 | |
| 172 | /* Use short Descriptor */ |
| 173 | eWLAN_PAL_TRUE |
| 174 | }; |
| 175 | |
| 176 | WLANDXE_ChannelConfigType chanRXLowPriConfig = |
| 177 | { |
| 178 | /* Q handle type, Circular */ |
| 179 | WLANDXE_CHANNEL_HANDLE_CIRCULA, |
| 180 | |
| 181 | /* Number of Descriptor, NOT CLEAR YET !!! */ |
Mohit Khanna | 5ef35f4 | 2012-09-11 15:58:51 -0700 | [diff] [blame] | 182 | 256, |
Jeff Johnson | 295189b | 2012-06-20 16:38:30 -0700 | [diff] [blame] | 183 | |
| 184 | /* MAX num RX Buffer, NOT CLEAR YET !!! */ |
| 185 | 1, |
| 186 | |
| 187 | /* Reference WQ, NOT CLEAR YET !!! */ |
| 188 | /* Temporary BMU Work Q 4 */ |
| 189 | 11, |
| 190 | |
| 191 | /* USB Only, End point info */ |
| 192 | 0, |
| 193 | |
| 194 | /* Transfer Type */ |
| 195 | WLANDXE_DESC_CTRL_XTYPE_B2H, |
| 196 | |
| 197 | /* Channel Priority 7(Highest) - 0(Lowest), NOT CLEAR YET !!! */ |
| 198 | 5, |
| 199 | |
| 200 | /* BD attached to frames for this pipe */ |
| 201 | eWLAN_PAL_TRUE, |
| 202 | |
| 203 | /* chk_size, NOT CLEAR YET !!!*/ |
| 204 | 0, |
| 205 | |
| 206 | /* bmuThdSel, NOT CLEAR YET !!! */ |
| 207 | 6, |
| 208 | |
| 209 | /* Added in Gen5 for Prefetch, NOT CLEAR YET !!!*/ |
| 210 | eWLAN_PAL_TRUE, |
| 211 | |
| 212 | /* Use short Descriptor */ |
| 213 | eWLAN_PAL_TRUE |
| 214 | }; |
| 215 | |
| 216 | WLANDXE_ChannelConfigType chanRXHighPriConfig = |
| 217 | { |
| 218 | /* Q handle type, Circular */ |
| 219 | WLANDXE_CHANNEL_HANDLE_CIRCULA, |
| 220 | |
| 221 | /* Number of Descriptor, NOT CLEAR YET !!! */ |
Mohit Khanna | 5ef35f4 | 2012-09-11 15:58:51 -0700 | [diff] [blame] | 222 | 256, |
Jeff Johnson | 295189b | 2012-06-20 16:38:30 -0700 | [diff] [blame] | 223 | |
| 224 | /* MAX num RX Buffer, NOT CLEAR YET !!! */ |
| 225 | 1, |
| 226 | |
| 227 | /* Reference WQ, RX11 */ |
| 228 | 4, |
| 229 | |
| 230 | /* USB Only, End point info */ |
| 231 | 0, |
| 232 | |
| 233 | /* Transfer Type */ |
| 234 | WLANDXE_DESC_CTRL_XTYPE_B2H, |
| 235 | |
| 236 | /* Channel Priority 7(Highest) - 0(Lowest), NOT CLEAR YET !!! */ |
| 237 | 6, |
| 238 | |
| 239 | /* BD attached to frames for this pipe */ |
| 240 | eWLAN_PAL_TRUE, |
| 241 | |
| 242 | /* chk_size, NOT CLEAR YET !!!*/ |
| 243 | 0, |
| 244 | |
| 245 | /* bmuThdSel, NOT CLEAR YET !!! */ |
| 246 | 8, |
| 247 | |
| 248 | /* Added in Gen5 for Prefetch, NOT CLEAR YET !!!*/ |
| 249 | eWLAN_PAL_TRUE, |
| 250 | |
| 251 | /* Use short Descriptor */ |
| 252 | eWLAN_PAL_TRUE |
| 253 | }; |
| 254 | |
Mihir Shete | e661816 | 2015-03-16 14:48:42 +0530 | [diff] [blame^] | 255 | WLANDXE_ChannelConfigType chanRXLogConfig = |
| 256 | { |
| 257 | /* Q handle type, Circular */ |
| 258 | WLANDXE_CHANNEL_HANDLE_CIRCULA, |
| 259 | |
| 260 | /* Number of Descriptors*/ |
| 261 | 8, |
| 262 | |
| 263 | /* MAX num RX Buffer*/ |
| 264 | 1, |
| 265 | |
| 266 | /* Reference WQ, RX23 */ |
| 267 | 23, |
| 268 | |
| 269 | /* USB Only, End point info */ |
| 270 | 0, |
| 271 | |
| 272 | /* Transfer Type */ |
| 273 | WLANDXE_DESC_CTRL_XTYPE_B2H, |
| 274 | |
| 275 | /* Channel Priority 7(Highest) - 0(Lowest)*/ |
| 276 | 0, |
| 277 | |
| 278 | /* BD attached to frames for this pipe */ |
| 279 | eWLAN_PAL_TRUE, |
| 280 | |
| 281 | /* chk_size*/ |
| 282 | 0, |
| 283 | |
| 284 | /* bmuThdSel*/ |
| 285 | 8, |
| 286 | |
| 287 | /* Added in Gen5 for Prefetch*/ |
| 288 | eWLAN_PAL_TRUE, |
| 289 | |
| 290 | /* Use short Descriptor */ |
| 291 | eWLAN_PAL_TRUE |
| 292 | }; |
| 293 | |
Jeff Johnson | 295189b | 2012-06-20 16:38:30 -0700 | [diff] [blame] | 294 | WLANDXE_ChannelMappingType channelList[WDTS_CHANNEL_MAX] = |
| 295 | { |
| 296 | {WDTS_CHANNEL_TX_LOW_PRI, WLANDXE_DMA_CHANNEL_0, &chanTXLowPriConfig}, |
| 297 | {WDTS_CHANNEL_TX_HIGH_PRI, WLANDXE_DMA_CHANNEL_4, &chanTXHighPriConfig}, |
| 298 | {WDTS_CHANNEL_RX_LOW_PRI, WLANDXE_DMA_CHANNEL_1, &chanRXLowPriConfig}, |
Jeff Johnson | 295189b | 2012-06-20 16:38:30 -0700 | [diff] [blame] | 299 | {WDTS_CHANNEL_RX_HIGH_PRI, WLANDXE_DMA_CHANNEL_3, &chanRXHighPriConfig}, |
Mihir Shete | e661816 | 2015-03-16 14:48:42 +0530 | [diff] [blame^] | 300 | {WDTS_CHANNEL_RX_LOG, WLANDXE_DMA_CHANNEL_5, &chanRXLogConfig}, |
Jeff Johnson | 295189b | 2012-06-20 16:38:30 -0700 | [diff] [blame] | 301 | }; |
| 302 | |
| 303 | WLANDXE_TxCompIntConfigType txCompInt = |
| 304 | { |
| 305 | /* TX Complete Interrupt enable method */ |
| 306 | WLANDXE_TX_COMP_INT_PER_K_FRAMES, |
| 307 | |
| 308 | /* TX Low Resource remaining resource threshold for Low Pri Ch */ |
| 309 | WLANDXE_TX_LOW_RES_THRESHOLD, |
| 310 | |
| 311 | /* TX Low Resource remaining resource threshold for High Pri Ch */ |
| 312 | WLANDXE_TX_LOW_RES_THRESHOLD, |
| 313 | |
| 314 | /* RX Low Resource remaining resource threshold */ |
| 315 | 5, |
| 316 | |
| 317 | /* Per K frame enable Interrupt */ |
| 318 | /*WLANDXE_HI_PRI_RES_NUM*/ 5, |
| 319 | |
| 320 | /* Periodic timer msec */ |
| 321 | 10 |
| 322 | }; |
| 323 | |
Mihir Shete | e661816 | 2015-03-16 14:48:42 +0530 | [diff] [blame^] | 324 | // Indicates the DXE channels being used in the current run. |
| 325 | static wpt_uint8 dxeEnabledChannels; |
| 326 | |
| 327 | /*========================================================================== |
| 328 | @ Function Name |
| 329 | dxeSetEnabledChannels |
| 330 | |
| 331 | @ Description |
| 332 | |
| 333 | @ Parameters |
| 334 | |
| 335 | @ Return |
| 336 | void |
| 337 | |
| 338 | ===========================================================================*/ |
| 339 | void dxeSetEnabledChannels |
| 340 | ( |
| 341 | wpt_uint8 enabledChannels |
| 342 | ) |
| 343 | { |
| 344 | dxeEnabledChannels = enabledChannels; |
| 345 | } |
| 346 | |
| 347 | /*========================================================================== |
| 348 | @ Function Name |
| 349 | dxeGetEnabledChannels |
| 350 | |
| 351 | @ Description |
| 352 | |
| 353 | @ Parameters |
| 354 | |
| 355 | @ Return |
| 356 | wpt_uint8 |
| 357 | |
| 358 | ===========================================================================*/ |
| 359 | wpt_uint8 dxeGetEnabledChannels |
| 360 | ( |
| 361 | void |
| 362 | ) |
| 363 | { |
| 364 | return dxeEnabledChannels; |
| 365 | } |
| 366 | |
Jeff Johnson | 295189b | 2012-06-20 16:38:30 -0700 | [diff] [blame] | 367 | /*========================================================================== |
| 368 | @ Function Name |
| 369 | dxeCommonDefaultConfig |
| 370 | |
| 371 | @ Description |
| 372 | |
| 373 | @ Parameters |
| 374 | WLANDXE_CtrlBlkType *dxeCtrlBlk, |
| 375 | DXE host driver main control block |
| 376 | |
| 377 | @ Return |
| 378 | wpt_status |
| 379 | |
| 380 | ===========================================================================*/ |
| 381 | wpt_status dxeCommonDefaultConfig |
| 382 | ( |
| 383 | WLANDXE_CtrlBlkType *dxeCtrlBlk |
| 384 | ) |
| 385 | { |
| 386 | wpt_status status = eWLAN_PAL_STATUS_SUCCESS; |
| 387 | |
| 388 | dxeCtrlBlk->rxReadyCB = NULL; |
| 389 | dxeCtrlBlk->txCompCB = NULL; |
| 390 | dxeCtrlBlk->lowResourceCB = NULL; |
| 391 | |
| 392 | wpalMemoryCopy(&dxeCtrlBlk->txCompInt, |
| 393 | &txCompInt, |
| 394 | sizeof(WLANDXE_TxCompIntConfigType)); |
| 395 | |
| 396 | return status; |
| 397 | } |
| 398 | |
| 399 | /*========================================================================== |
| 400 | @ Function Name |
| 401 | dxeChannelDefaultConfig |
| 402 | |
| 403 | @ Description |
| 404 | Get defualt configuration values from pre defined structure |
| 405 | All the channels must have it's own configurations |
| 406 | |
| 407 | @ Parameters |
Gopichand Nakkala | a2cb10c | 2013-05-03 17:48:29 -0700 | [diff] [blame] | 408 | WLANDXE_CtrlBlkType: *dxeCtrlBlk, |
Jeff Johnson | 295189b | 2012-06-20 16:38:30 -0700 | [diff] [blame] | 409 | DXE host driver main control block |
| 410 | WLANDXE_ChannelCBType *channelEntry |
| 411 | Channel specific control block |
| 412 | |
| 413 | @ Return |
| 414 | wpt_status |
| 415 | |
| 416 | ===========================================================================*/ |
| 417 | wpt_status dxeChannelDefaultConfig |
| 418 | ( |
| 419 | WLANDXE_CtrlBlkType *dxeCtrlBlk, |
| 420 | WLANDXE_ChannelCBType *channelEntry |
| 421 | ) |
| 422 | { |
| 423 | wpt_status status = eWLAN_PAL_STATUS_SUCCESS; |
| 424 | wpt_uint32 baseAddress; |
| 425 | wpt_uint32 dxeControlRead = 0; |
| 426 | wpt_uint32 dxeControlWrite = 0; |
| 427 | wpt_uint32 dxeControlWriteValid = 0; |
| 428 | wpt_uint32 dxeControlWriteEop = 0; |
| 429 | wpt_uint32 dxeControlWriteEopInt = 0; |
| 430 | wpt_uint32 idx; |
Gopichand Nakkala | a2cb10c | 2013-05-03 17:48:29 -0700 | [diff] [blame] | 431 | wpt_uint32 rxResourceCount = 0; |
Jeff Johnson | 295189b | 2012-06-20 16:38:30 -0700 | [diff] [blame] | 432 | WLANDXE_ChannelMappingType *mappedChannel = NULL; |
| 433 | |
| 434 | /* Sanity Check */ |
| 435 | if((NULL == dxeCtrlBlk) || (NULL == channelEntry)) |
| 436 | { |
| 437 | HDXE_MSG(eWLAN_MODULE_DAL_DATA, eWLAN_PAL_TRACE_LEVEL_ERROR, |
| 438 | "dxeLinkDescAndCtrlBlk Channel Entry is not valid"); |
| 439 | return eWLAN_PAL_STATUS_E_INVAL; |
| 440 | } |
| 441 | |
| 442 | for(idx = 0; idx < WDTS_CHANNEL_MAX; idx++) |
| 443 | { |
| 444 | if(channelEntry->channelType == channelList[idx].wlanChannel) |
| 445 | { |
| 446 | mappedChannel = &channelList[idx]; |
| 447 | break; |
| 448 | } |
| 449 | } |
| 450 | |
| 451 | if((NULL == mappedChannel) || (WDTS_CHANNEL_MAX == idx)) |
| 452 | { |
| 453 | HDXE_MSG(eWLAN_MODULE_DAL_DATA, eWLAN_PAL_TRACE_LEVEL_ERROR, |
Madan Mohan Koyyalamudi | 87054ba | 2012-11-02 13:24:12 -0700 | [diff] [blame] | 454 | "%s Failed to map channel", __func__); |
Jeff Johnson | 295189b | 2012-06-20 16:38:30 -0700 | [diff] [blame] | 455 | return eWLAN_PAL_STATUS_E_INVAL; |
| 456 | } |
| 457 | |
| 458 | wpalMemoryCopy(&channelEntry->channelConfig, |
| 459 | mappedChannel->channelConfig, |
| 460 | sizeof(WLANDXE_ChannelConfigType)); |
| 461 | |
| 462 | baseAddress = channelBaseAddressList[mappedChannel->DMAChannel]; |
| 463 | channelEntry->channelRegister.chDXEBaseAddr = baseAddress; |
| 464 | channelEntry->channelRegister.chDXEStatusRegAddr = baseAddress + WLANDXE_DMA_CH_STATUS_REG; |
| 465 | channelEntry->channelRegister.chDXEDesclRegAddr = baseAddress + WLANDXE_DMA_CH_DESCL_REG; |
| 466 | channelEntry->channelRegister.chDXEDeschRegAddr = baseAddress + WLANDXE_DMA_CH_DESCH_REG; |
| 467 | channelEntry->channelRegister.chDXELstDesclRegAddr = baseAddress + WLANDXE_DMA_CH_LST_DESCL_REG; |
| 468 | channelEntry->channelRegister.chDXECtrlRegAddr = baseAddress + WLANDXE_DMA_CH_CTRL_REG; |
| 469 | channelEntry->channelRegister.chDXESzRegAddr = baseAddress + WLANDXE_DMA_CH_SZ_REG; |
| 470 | channelEntry->channelRegister.chDXEDadrlRegAddr = baseAddress + WLANDXE_DMA_CH_DADRL_REG; |
| 471 | channelEntry->channelRegister.chDXEDadrhRegAddr = baseAddress + WLANDXE_DMA_CH_DADRH_REG; |
| 472 | channelEntry->channelRegister.chDXESadrlRegAddr = baseAddress + WLANDXE_DMA_CH_SADRL_REG; |
| 473 | channelEntry->channelRegister.chDXESadrhRegAddr = baseAddress + WLANDXE_DMA_CH_SADRH_REG; |
| 474 | |
| 475 | /* Channel Mask? |
| 476 | * This value will control channel control register. |
| 477 | * This register will be set to trigger actual DMA transfer activate |
| 478 | * CH_N_CTRL */ |
| 479 | channelEntry->extraConfig.chan_mask = 0; |
| 480 | /* Check VAL bit before processing descriptor */ |
| 481 | channelEntry->extraConfig.chan_mask |= WLANDXE_CH_CTRL_EDVEN_MASK; |
| 482 | /* Use External Descriptor Linked List */ |
| 483 | channelEntry->extraConfig.chan_mask |= WLANDXE_CH_CTRL_EDEN_MASK; |
| 484 | /* Enable Channel Interrupt on error */ |
| 485 | channelEntry->extraConfig.chan_mask |= WLANDXE_CH_CTRL_INE_ERR_MASK; |
| 486 | /* Enable INT after XFER done */ |
| 487 | channelEntry->extraConfig.chan_mask |= WLANDXE_CH_CTRL_INE_DONE_MASK; |
| 488 | /* Enable INT External Descriptor */ |
| 489 | channelEntry->extraConfig.chan_mask |= WLANDXE_CH_CTRL_INE_ED_MASK; |
| 490 | /* Set Channel This is not channel, event counter, somthing wrong */ |
| 491 | channelEntry->extraConfig.chan_mask |= |
| 492 | mappedChannel->DMAChannel << WLANDXE_CH_CTRL_CTR_SEL_OFFSET; |
| 493 | /* Transfer Type */ |
| 494 | channelEntry->extraConfig.chan_mask |= mappedChannel->channelConfig->xfrType; |
| 495 | /* Use Short Descriptor, THIS LOOKS SOME WIERD, REVISIT */ |
| 496 | if(!channelEntry->channelConfig.useShortDescFmt) |
| 497 | { |
| 498 | channelEntry->extraConfig.chan_mask |= WLANDXE_DESC_CTRL_DFMT; |
| 499 | } |
| 500 | /* TX Channel, Set DIQ bit, Clear SIQ bit since source is not WQ */ |
| 501 | if((WDTS_CHANNEL_TX_LOW_PRI == channelEntry->channelType) || |
| 502 | (WDTS_CHANNEL_TX_HIGH_PRI == channelEntry->channelType)) |
| 503 | { |
| 504 | channelEntry->extraConfig.chan_mask |= WLANDXE_CH_CTRL_DIQ_MASK; |
Siddharth Bhal | b7e8e88 | 2014-10-10 16:27:47 +0530 | [diff] [blame] | 505 | if (wpalWcnssIsProntoHwVer3()) |
| 506 | { |
| 507 | HDXE_MSG(eWLAN_MODULE_DAL_DATA, eWLAN_PAL_TRACE_LEVEL_ERROR, |
| 508 | "Using WQ 6 for TX Low/High PRI Channel"); |
| 509 | channelEntry->channelConfig.refWQ = WLANDXE_PRONTO_TX_WQ; |
| 510 | } |
Jeff Johnson | 295189b | 2012-06-20 16:38:30 -0700 | [diff] [blame] | 511 | } |
| 512 | /* RX Channel, Set SIQ bit, Clear DIQ bit since source is not WQ */ |
| 513 | else if((WDTS_CHANNEL_RX_LOW_PRI == channelEntry->channelType) || |
Mihir Shete | e661816 | 2015-03-16 14:48:42 +0530 | [diff] [blame^] | 514 | (WDTS_CHANNEL_RX_HIGH_PRI == channelEntry->channelType) || |
| 515 | (WDTS_CHANNEL_RX_LOG == channelEntry->channelType)) |
Jeff Johnson | 295189b | 2012-06-20 16:38:30 -0700 | [diff] [blame] | 516 | { |
| 517 | channelEntry->extraConfig.chan_mask |= WLANDXE_CH_CTRL_SIQ_MASK; |
| 518 | } |
| 519 | else |
| 520 | { |
| 521 | /* This is test H2H channel, TX, RX not use work Q |
| 522 | * Do Nothing */ |
| 523 | } |
| 524 | /* Frame Contents Swap */ |
| 525 | channelEntry->extraConfig.chan_mask |= WLANDXE_CH_CTRL_SWAP_MASK; |
| 526 | /* Host System Using Little Endian */ |
| 527 | channelEntry->extraConfig.chan_mask |= WLANDXE_CH_CTRL_ENDIAN_MASK; |
| 528 | /* BMU Threshold select */ |
| 529 | channelEntry->extraConfig.chan_mask |= |
| 530 | channelEntry->channelConfig.bmuThdSel << WLANDXE_CH_CTRL_BTHLD_SEL_OFFSET; |
| 531 | /* EOP for control register ??? */ |
| 532 | channelEntry->extraConfig.chan_mask |= WLANDXE_CH_CTRL_EOP_MASK; |
| 533 | /* Channel Priority */ |
| 534 | channelEntry->extraConfig.chan_mask |= channelEntry->channelConfig.chPriority << WLANDXE_CH_CTRL_PRIO_OFFSET; |
| 535 | /* PDU REL */ |
| 536 | channelEntry->extraConfig.chan_mask |= WLANDXE_DESC_CTRL_PDU_REL; |
| 537 | /* Disable DMA transfer on this channel */ |
| 538 | channelEntry->extraConfig.chan_mask_read_disable = channelEntry->extraConfig.chan_mask; |
| 539 | /* Enable DMA transfer on this channel */ |
| 540 | channelEntry->extraConfig.chan_mask |= WLANDXE_CH_CTRL_EN_MASK; |
| 541 | /* Channel Mask done */ |
| 542 | |
| 543 | /* Control Read |
| 544 | * Default Descriptor control Word value for RX ready DXE descriptor |
| 545 | * DXE engine will reference this value before DMA transfer */ |
| 546 | dxeControlRead = 0; |
| 547 | /* Source is a Queue ID, not flat memory address */ |
| 548 | dxeControlRead |= WLANDXE_DESC_CTRL_SIQ; |
| 549 | /* Transfer direction is BMU 2 Host */ |
| 550 | dxeControlRead |= WLANDXE_DESC_CTRL_XTYPE_B2H; |
| 551 | /* End of Packet, RX is single fragment */ |
| 552 | dxeControlRead |= WLANDXE_DESC_CTRL_EOP; |
| 553 | /* BD Present, default YES, B2H case it must be 0 to insert BD */ |
| 554 | if(!channelEntry->channelConfig.bdPresent) |
| 555 | { |
| 556 | dxeControlRead |= WLANDXE_DESC_CTRL_BDH; |
| 557 | } |
| 558 | /* Channel Priority */ |
| 559 | dxeControlRead |= channelEntry->channelConfig.chPriority << WLANDXE_CH_CTRL_PRIO_OFFSET; |
| 560 | /* BMU Threshold select, only used H2B, not this case??? */ |
| 561 | dxeControlRead |= channelEntry->channelConfig.bmuThdSel << WLANDXE_CH_CTRL_BTHLD_SEL_OFFSET; |
| 562 | /* PDU Release, Release BD/PDU when DMA done */ |
| 563 | dxeControlRead |= WLANDXE_DESC_CTRL_PDU_REL; |
| 564 | /* Use Short Descriptor, THIS LOOKS SOME WIERD, REVISIT */ |
| 565 | if(!channelEntry->channelConfig.useShortDescFmt) |
| 566 | { |
| 567 | dxeControlRead |= WLANDXE_DESC_CTRL_DFMT; |
| 568 | } |
| 569 | /* Interrupt on Descriptor done */ |
| 570 | dxeControlRead |= WLANDXE_DESC_CTRL_INT; |
| 571 | /* For ready status, this Control WORD must be VALID */ |
| 572 | dxeControlRead |= WLANDXE_DESC_CTRL_VALID; |
| 573 | /* Frame Contents Swap */ |
| 574 | dxeControlRead |= WLANDXE_DESC_CTRL_BDT_SWAP; |
| 575 | /* Host Little Endian */ |
| 576 | if((WDTS_CHANNEL_TX_LOW_PRI == channelEntry->channelType) || |
| 577 | (WDTS_CHANNEL_TX_HIGH_PRI == channelEntry->channelType)) |
| 578 | { |
| 579 | dxeControlRead |= WLANDXE_DESC_CTRL_ENDIANNESS; |
| 580 | } |
| 581 | |
| 582 | /* SWAP if needed */ |
| 583 | channelEntry->extraConfig.cw_ctrl_read = WLANDXE_U32_SWAP_ENDIAN(dxeControlRead); |
| 584 | /* Control Read Done */ |
| 585 | |
| 586 | /* Control Write |
| 587 | * Write into DXE descriptor control word to TX frame |
| 588 | * DXE engine will reference this word to contorl TX DMA channel */ |
| 589 | channelEntry->extraConfig.cw_ctrl_write = 0; |
| 590 | /* Transfer type, from Host 2 BMU */ |
| 591 | dxeControlWrite |= mappedChannel->channelConfig->xfrType; |
| 592 | /* BD Present, this looks some weird ??? */ |
| 593 | if(!channelEntry->channelConfig.bdPresent) |
| 594 | { |
| 595 | dxeControlWrite |= WLANDXE_DESC_CTRL_BDH; |
| 596 | } |
| 597 | /* Channel Priority */ |
| 598 | dxeControlWrite |= channelEntry->channelConfig.chPriority << WLANDXE_CH_CTRL_PRIO_OFFSET; |
| 599 | /* Use Short Descriptor, THIS LOOKS SOME WIERD, REVISIT */ |
| 600 | if(!channelEntry->channelConfig.useShortDescFmt) |
| 601 | { |
| 602 | dxeControlWrite |= WLANDXE_DESC_CTRL_DFMT; |
| 603 | } |
| 604 | /* BMU Threshold select, only used H2B, not this case??? */ |
| 605 | dxeControlWrite |= channelEntry->channelConfig.bmuThdSel << WLANDXE_CH_CTRL_BTHLD_SEL_OFFSET; |
| 606 | /* Destination is WQ */ |
| 607 | dxeControlWrite |= WLANDXE_DESC_CTRL_DIQ; |
| 608 | /* Frame Contents Swap */ |
| 609 | dxeControlWrite |= WLANDXE_DESC_CTRL_BDT_SWAP; |
| 610 | /* Host Little Endian */ |
| 611 | dxeControlWrite |= WLANDXE_DESC_CTRL_ENDIANNESS; |
| 612 | /* Interrupt Enable */ |
| 613 | dxeControlWrite |= WLANDXE_DESC_CTRL_INT; |
| 614 | |
| 615 | dxeControlWriteValid = dxeControlWrite | WLANDXE_DESC_CTRL_VALID; |
| 616 | dxeControlWriteEop = dxeControlWriteValid | WLANDXE_DESC_CTRL_EOP; |
| 617 | dxeControlWriteEopInt = dxeControlWriteEop | WLANDXE_DESC_CTRL_INT; |
| 618 | |
| 619 | /* DXE Descriptor must has Endian swapped value */ |
| 620 | channelEntry->extraConfig.cw_ctrl_write = WLANDXE_U32_SWAP_ENDIAN(dxeControlWrite); |
| 621 | /* Control Write DONE */ |
| 622 | |
| 623 | /* Control Write include VAL bit |
| 624 | * This Control word used to set valid bit and |
| 625 | * trigger DMA transfer for specific descriptor */ |
| 626 | channelEntry->extraConfig.cw_ctrl_write_valid = |
| 627 | WLANDXE_U32_SWAP_ENDIAN(dxeControlWriteValid); |
| 628 | |
| 629 | /* Control Write include EOP |
| 630 | * End of Packet */ |
| 631 | channelEntry->extraConfig.cw_ctrl_write_eop = |
| 632 | WLANDXE_U32_SWAP_ENDIAN(dxeControlWriteEop); |
| 633 | |
| 634 | /* Control Write include EOP and INT |
| 635 | * indicate End Of Packet and generate interrupt on descriptor Done */ |
| 636 | channelEntry->extraConfig.cw_ctrl_write_eop_int = |
| 637 | WLANDXE_U32_SWAP_ENDIAN(dxeControlWriteEopInt); |
| 638 | |
| 639 | |
| 640 | /* size mask???? */ |
| 641 | channelEntry->extraConfig.chk_size_mask = |
| 642 | mappedChannel->channelConfig->chk_size << 10; |
| 643 | |
| 644 | channelEntry->extraConfig.refWQ_swapped = |
| 645 | WLANDXE_U32_SWAP_ENDIAN(channelEntry->channelConfig.refWQ); |
| 646 | |
| 647 | /* Set Channel specific Interrupt mask */ |
| 648 | channelEntry->extraConfig.intMask = channelInterruptMask[mappedChannel->DMAChannel]; |
| 649 | |
| 650 | |
Gopichand Nakkala | a2cb10c | 2013-05-03 17:48:29 -0700 | [diff] [blame] | 651 | wpalGetNumRxRawPacket(&rxResourceCount); |
| 652 | if((WDTS_CHANNEL_TX_LOW_PRI == channelEntry->channelType) || |
| 653 | (0 == rxResourceCount)) |
| 654 | { |
| 655 | channelEntry->numDesc = mappedChannel->channelConfig->nDescs; |
| 656 | } |
Mihir Shete | e661816 | 2015-03-16 14:48:42 +0530 | [diff] [blame^] | 657 | else if(WDTS_CHANNEL_RX_LOG == channelEntry->channelType) |
| 658 | { |
| 659 | channelEntry->numDesc = mappedChannel->channelConfig->nDescs; |
| 660 | } |
Gopichand Nakkala | a2cb10c | 2013-05-03 17:48:29 -0700 | [diff] [blame] | 661 | else |
| 662 | { |
| 663 | channelEntry->numDesc = rxResourceCount / 4; |
| 664 | } |
Jeff Johnson | 295189b | 2012-06-20 16:38:30 -0700 | [diff] [blame] | 665 | channelEntry->assignedDMAChannel = mappedChannel->DMAChannel; |
| 666 | channelEntry->numFreeDesc = 0; |
| 667 | channelEntry->numRsvdDesc = 0; |
| 668 | channelEntry->numFragmentCurrentChain = 0; |
| 669 | channelEntry->numTotalFrame = 0; |
| 670 | channelEntry->hitLowResource = eWLAN_PAL_FALSE; |
| 671 | |
| 672 | return status; |
| 673 | } |