Prakash Dhavali | 7090c5f | 2015-11-02 17:55:19 -0800 | [diff] [blame] | 1 | /* |
Komal Seelam | 644263d | 2016-02-22 20:45:49 +0530 | [diff] [blame] | 2 | * Copyright (c) 2015-2016 The Linux Foundation. All rights reserved. |
Prakash Dhavali | 7090c5f | 2015-11-02 17:55:19 -0800 | [diff] [blame] | 3 | * |
| 4 | * Previously licensed under the ISC license by Qualcomm Atheros, Inc. |
| 5 | * |
| 6 | * |
| 7 | * Permission to use, copy, modify, and/or distribute this software for |
| 8 | * any purpose with or without fee is hereby granted, provided that the |
| 9 | * above copyright notice and this permission notice appear in all |
| 10 | * copies. |
| 11 | * |
| 12 | * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL |
| 13 | * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED |
| 14 | * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE |
| 15 | * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL |
| 16 | * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR |
| 17 | * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER |
| 18 | * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR |
| 19 | * PERFORMANCE OF THIS SOFTWARE. |
| 20 | */ |
| 21 | |
| 22 | /* |
| 23 | * This file was originally distributed by Qualcomm Atheros, Inc. |
| 24 | * under proprietary terms before Copyright ownership was assigned |
| 25 | * to the Linux Foundation. |
| 26 | */ |
| 27 | |
| 28 | #ifndef __CE_REG_H__ |
| 29 | #define __CE_REG_H__ |
| 30 | |
Sanjay Devnani | cdab59e | 2015-11-12 14:43:58 -0800 | [diff] [blame] | 31 | #define COPY_ENGINE_ID(COPY_ENGINE_BASE_ADDRESS) ((COPY_ENGINE_BASE_ADDRESS \ |
| 32 | - CE0_BASE_ADDRESS)/(CE1_BASE_ADDRESS - CE0_BASE_ADDRESS)) |
| 33 | |
Prakash Dhavali | 7090c5f | 2015-11-02 17:55:19 -0800 | [diff] [blame] | 34 | #define DST_WR_INDEX_ADDRESS (scn->target_ce_def->d_DST_WR_INDEX_ADDRESS) |
| 35 | #define SRC_WATERMARK_ADDRESS (scn->target_ce_def->d_SRC_WATERMARK_ADDRESS) |
| 36 | #define SRC_WATERMARK_LOW_MASK (scn->target_ce_def->d_SRC_WATERMARK_LOW_MASK) |
| 37 | #define SRC_WATERMARK_HIGH_MASK (scn->target_ce_def->d_SRC_WATERMARK_HIGH_MASK) |
| 38 | #define DST_WATERMARK_LOW_MASK (scn->target_ce_def->d_DST_WATERMARK_LOW_MASK) |
| 39 | #define DST_WATERMARK_HIGH_MASK (scn->target_ce_def->d_DST_WATERMARK_HIGH_MASK) |
| 40 | #define CURRENT_SRRI_ADDRESS (scn->target_ce_def->d_CURRENT_SRRI_ADDRESS) |
| 41 | #define CURRENT_DRRI_ADDRESS (scn->target_ce_def->d_CURRENT_DRRI_ADDRESS) |
| 42 | |
| 43 | #define SHADOW_VALUE0 (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_VALUE_0) |
| 44 | #define SHADOW_VALUE1 (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_VALUE_1) |
| 45 | #define SHADOW_VALUE2 (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_VALUE_2) |
| 46 | #define SHADOW_VALUE3 (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_VALUE_3) |
| 47 | #define SHADOW_VALUE4 (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_VALUE_4) |
| 48 | #define SHADOW_VALUE5 (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_VALUE_5) |
| 49 | #define SHADOW_VALUE6 (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_VALUE_6) |
| 50 | #define SHADOW_VALUE7 (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_VALUE_7) |
| 51 | #define SHADOW_VALUE8 (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_VALUE_8) |
| 52 | #define SHADOW_VALUE9 (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_VALUE_9) |
| 53 | #define SHADOW_VALUE10 (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_VALUE_10) |
| 54 | #define SHADOW_VALUE11 (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_VALUE_11) |
| 55 | #define SHADOW_VALUE12 (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_VALUE_12) |
| 56 | #define SHADOW_VALUE13 (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_VALUE_13) |
| 57 | #define SHADOW_VALUE14 (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_VALUE_14) |
| 58 | #define SHADOW_VALUE15 (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_VALUE_15) |
| 59 | #define SHADOW_VALUE16 (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_VALUE_16) |
| 60 | #define SHADOW_VALUE17 (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_VALUE_17) |
| 61 | #define SHADOW_VALUE18 (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_VALUE_18) |
| 62 | #define SHADOW_VALUE19 (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_VALUE_19) |
| 63 | #define SHADOW_VALUE20 (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_VALUE_20) |
| 64 | #define SHADOW_VALUE21 (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_VALUE_21) |
| 65 | #define SHADOW_VALUE22 (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_VALUE_22) |
| 66 | #define SHADOW_VALUE23 (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_VALUE_23) |
| 67 | #define SHADOW_ADDRESS0 (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_ADDRESS_0) |
| 68 | #define SHADOW_ADDRESS1 (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_ADDRESS_1) |
| 69 | #define SHADOW_ADDRESS2 (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_ADDRESS_2) |
| 70 | #define SHADOW_ADDRESS3 (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_ADDRESS_3) |
| 71 | #define SHADOW_ADDRESS4 (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_ADDRESS_4) |
| 72 | #define SHADOW_ADDRESS5 (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_ADDRESS_5) |
| 73 | #define SHADOW_ADDRESS6 (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_ADDRESS_6) |
| 74 | #define SHADOW_ADDRESS7 (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_ADDRESS_7) |
| 75 | #define SHADOW_ADDRESS8 (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_ADDRESS_8) |
| 76 | #define SHADOW_ADDRESS9 (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_ADDRESS_9) |
| 77 | #define SHADOW_ADDRESS10 (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_ADDRESS_10) |
| 78 | #define SHADOW_ADDRESS11 (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_ADDRESS_11) |
| 79 | #define SHADOW_ADDRESS12 (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_ADDRESS_12) |
| 80 | #define SHADOW_ADDRESS13 (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_ADDRESS_13) |
| 81 | #define SHADOW_ADDRESS14 (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_ADDRESS_14) |
| 82 | #define SHADOW_ADDRESS15 (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_ADDRESS_15) |
| 83 | #define SHADOW_ADDRESS16 (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_ADDRESS_16) |
| 84 | #define SHADOW_ADDRESS17 (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_ADDRESS_17) |
| 85 | #define SHADOW_ADDRESS18 (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_ADDRESS_18) |
| 86 | #define SHADOW_ADDRESS19 (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_ADDRESS_19) |
| 87 | #define SHADOW_ADDRESS20 (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_ADDRESS_20) |
| 88 | #define SHADOW_ADDRESS21 (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_ADDRESS_21) |
| 89 | #define SHADOW_ADDRESS22 (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_ADDRESS_22) |
| 90 | #define SHADOW_ADDRESS23 (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_ADDRESS_23) |
| 91 | |
| 92 | #define SHADOW_ADDRESS(i) (SHADOW_ADDRESS0 + i*(SHADOW_ADDRESS1-SHADOW_ADDRESS0)) |
| 93 | |
| 94 | #define HOST_IS_SRC_RING_HIGH_WATERMARK_MASK \ |
| 95 | (scn->target_ce_def->d_HOST_IS_SRC_RING_HIGH_WATERMARK_MASK) |
| 96 | #define HOST_IS_SRC_RING_LOW_WATERMARK_MASK \ |
| 97 | (scn->target_ce_def->d_HOST_IS_SRC_RING_LOW_WATERMARK_MASK) |
| 98 | #define HOST_IS_DST_RING_HIGH_WATERMARK_MASK \ |
| 99 | (scn->target_ce_def->d_HOST_IS_DST_RING_HIGH_WATERMARK_MASK) |
| 100 | #define HOST_IS_DST_RING_LOW_WATERMARK_MASK \ |
| 101 | (scn->target_ce_def->d_HOST_IS_DST_RING_LOW_WATERMARK_MASK) |
| 102 | #define MISC_IS_ADDRESS (scn->target_ce_def->d_MISC_IS_ADDRESS) |
| 103 | #define HOST_IS_COPY_COMPLETE_MASK \ |
| 104 | (scn->target_ce_def->d_HOST_IS_COPY_COMPLETE_MASK) |
| 105 | #define CE_WRAPPER_BASE_ADDRESS (scn->target_ce_def->d_CE_WRAPPER_BASE_ADDRESS) |
| 106 | #define CE_WRAPPER_INTERRUPT_SUMMARY_ADDRESS \ |
| 107 | (scn->target_ce_def->d_CE_WRAPPER_INTERRUPT_SUMMARY_ADDRESS) |
Sanjay Devnani | cdab59e | 2015-11-12 14:43:58 -0800 | [diff] [blame] | 108 | #define CE_DDR_ADDRESS_FOR_RRI_LOW \ |
| 109 | (scn->target_ce_def->d_CE_DDR_ADDRESS_FOR_RRI_LOW) |
| 110 | #define CE_DDR_ADDRESS_FOR_RRI_HIGH \ |
| 111 | (scn->target_ce_def->d_CE_DDR_ADDRESS_FOR_RRI_HIGH) |
Prakash Dhavali | 7090c5f | 2015-11-02 17:55:19 -0800 | [diff] [blame] | 112 | #define HOST_IE_COPY_COMPLETE_MASK \ |
| 113 | (scn->target_ce_def->d_HOST_IE_COPY_COMPLETE_MASK) |
| 114 | #define SR_BA_ADDRESS (scn->target_ce_def->d_SR_BA_ADDRESS) |
| 115 | #define SR_BA_ADDRESS_HIGH (scn->target_ce_def->d_SR_BA_ADDRESS_HIGH) |
| 116 | #define SR_SIZE_ADDRESS (scn->target_ce_def->d_SR_SIZE_ADDRESS) |
| 117 | #define CE_CTRL1_ADDRESS (scn->target_ce_def->d_CE_CTRL1_ADDRESS) |
| 118 | #define CE_CTRL1_DMAX_LENGTH_MASK \ |
| 119 | (scn->target_ce_def->d_CE_CTRL1_DMAX_LENGTH_MASK) |
| 120 | #define DR_BA_ADDRESS (scn->target_ce_def->d_DR_BA_ADDRESS) |
| 121 | #define DR_BA_ADDRESS_HIGH (scn->target_ce_def->d_DR_BA_ADDRESS_HIGH) |
| 122 | #define DR_SIZE_ADDRESS (scn->target_ce_def->d_DR_SIZE_ADDRESS) |
| 123 | #define CE_CMD_REGISTER (scn->target_ce_def->d_CE_CMD_REGISTER) |
| 124 | #define CE_MSI_ADDRESS (scn->target_ce_def->d_CE_MSI_ADDRESS) |
| 125 | #define CE_MSI_ADDRESS_HIGH (scn->target_ce_def->d_CE_MSI_ADDRESS_HIGH) |
| 126 | #define CE_MSI_DATA (scn->target_ce_def->d_CE_MSI_DATA) |
| 127 | #define CE_MSI_ENABLE_BIT (scn->target_ce_def->d_CE_MSI_ENABLE_BIT) |
| 128 | #define MISC_IE_ADDRESS (scn->target_ce_def->d_MISC_IE_ADDRESS) |
| 129 | #define MISC_IS_AXI_ERR_MASK (scn->target_ce_def->d_MISC_IS_AXI_ERR_MASK) |
| 130 | #define MISC_IS_DST_ADDR_ERR_MASK \ |
| 131 | (scn->target_ce_def->d_MISC_IS_DST_ADDR_ERR_MASK) |
| 132 | #define MISC_IS_SRC_LEN_ERR_MASK \ |
| 133 | (scn->target_ce_def->d_MISC_IS_SRC_LEN_ERR_MASK) |
| 134 | #define MISC_IS_DST_MAX_LEN_VIO_MASK \ |
| 135 | (scn->target_ce_def->d_MISC_IS_DST_MAX_LEN_VIO_MASK) |
| 136 | #define MISC_IS_DST_RING_OVERFLOW_MASK \ |
| 137 | (scn->target_ce_def->d_MISC_IS_DST_RING_OVERFLOW_MASK) |
| 138 | #define MISC_IS_SRC_RING_OVERFLOW_MASK \ |
| 139 | (scn->target_ce_def->d_MISC_IS_SRC_RING_OVERFLOW_MASK) |
| 140 | #define SRC_WATERMARK_LOW_LSB (scn->target_ce_def->d_SRC_WATERMARK_LOW_LSB) |
| 141 | #define SRC_WATERMARK_HIGH_LSB (scn->target_ce_def->d_SRC_WATERMARK_HIGH_LSB) |
| 142 | #define DST_WATERMARK_LOW_LSB (scn->target_ce_def->d_DST_WATERMARK_LOW_LSB) |
| 143 | #define DST_WATERMARK_HIGH_LSB (scn->target_ce_def->d_DST_WATERMARK_HIGH_LSB) |
| 144 | #define CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_MASK \ |
| 145 | (scn->target_ce_def->d_CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_MASK) |
| 146 | #define CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_LSB \ |
| 147 | (scn->target_ce_def->d_CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_LSB) |
| 148 | #define CE_CTRL1_DMAX_LENGTH_LSB (scn->target_ce_def->d_CE_CTRL1_DMAX_LENGTH_LSB) |
Sanjay Devnani | cdab59e | 2015-11-12 14:43:58 -0800 | [diff] [blame] | 149 | #define CE_CTRL1_IDX_UPD_EN (scn->target_ce_def->d_CE_CTRL1_IDX_UPD_EN_MASK) |
Prakash Dhavali | 7090c5f | 2015-11-02 17:55:19 -0800 | [diff] [blame] | 150 | #define CE_CTRL1_SRC_RING_BYTE_SWAP_EN_MASK \ |
| 151 | (scn->target_ce_def->d_CE_CTRL1_SRC_RING_BYTE_SWAP_EN_MASK) |
| 152 | #define CE_CTRL1_DST_RING_BYTE_SWAP_EN_MASK \ |
| 153 | (scn->target_ce_def->d_CE_CTRL1_DST_RING_BYTE_SWAP_EN_MASK) |
| 154 | #define CE_CTRL1_SRC_RING_BYTE_SWAP_EN_LSB \ |
| 155 | (scn->target_ce_def->d_CE_CTRL1_SRC_RING_BYTE_SWAP_EN_LSB) |
| 156 | #define CE_CTRL1_DST_RING_BYTE_SWAP_EN_LSB \ |
| 157 | (scn->target_ce_def->d_CE_CTRL1_DST_RING_BYTE_SWAP_EN_LSB) |
| 158 | #define WLAN_DEBUG_INPUT_SEL_OFFSET \ |
| 159 | (scn->targetdef->d_WLAN_DEBUG_INPUT_SEL_OFFSET) |
| 160 | #define WLAN_DEBUG_INPUT_SEL_SRC_MSB \ |
| 161 | (scn->targetdef->d_WLAN_DEBUG_INPUT_SEL_SRC_MSB) |
| 162 | #define WLAN_DEBUG_INPUT_SEL_SRC_LSB \ |
| 163 | (scn->targetdef->d_WLAN_DEBUG_INPUT_SEL_SRC_LSB) |
| 164 | #define WLAN_DEBUG_INPUT_SEL_SRC_MASK \ |
| 165 | (scn->targetdef->d_WLAN_DEBUG_INPUT_SEL_SRC_MASK) |
| 166 | #define WLAN_DEBUG_CONTROL_OFFSET (scn->targetdef->d_WLAN_DEBUG_CONTROL_OFFSET) |
| 167 | #define WLAN_DEBUG_CONTROL_ENABLE_MSB \ |
| 168 | (scn->targetdef->d_WLAN_DEBUG_CONTROL_ENABLE_MSB) |
| 169 | #define WLAN_DEBUG_CONTROL_ENABLE_LSB \ |
| 170 | (scn->targetdef->d_WLAN_DEBUG_CONTROL_ENABLE_LSB) |
| 171 | #define WLAN_DEBUG_CONTROL_ENABLE_MASK \ |
| 172 | (scn->targetdef->d_WLAN_DEBUG_CONTROL_ENABLE_MASK) |
| 173 | #define WLAN_DEBUG_OUT_OFFSET (scn->targetdef->d_WLAN_DEBUG_OUT_OFFSET) |
| 174 | #define WLAN_DEBUG_OUT_DATA_MSB (scn->targetdef->d_WLAN_DEBUG_OUT_DATA_MSB) |
| 175 | #define WLAN_DEBUG_OUT_DATA_LSB (scn->targetdef->d_WLAN_DEBUG_OUT_DATA_LSB) |
| 176 | #define WLAN_DEBUG_OUT_DATA_MASK (scn->targetdef->d_WLAN_DEBUG_OUT_DATA_MASK) |
| 177 | #define AMBA_DEBUG_BUS_OFFSET (scn->targetdef->d_AMBA_DEBUG_BUS_OFFSET) |
| 178 | #define AMBA_DEBUG_BUS_PCIE_DEBUG_SEL_MSB \ |
| 179 | (scn->targetdef->d_AMBA_DEBUG_BUS_PCIE_DEBUG_SEL_MSB) |
| 180 | #define AMBA_DEBUG_BUS_PCIE_DEBUG_SEL_LSB \ |
| 181 | (scn->targetdef->d_AMBA_DEBUG_BUS_PCIE_DEBUG_SEL_LSB) |
| 182 | #define AMBA_DEBUG_BUS_PCIE_DEBUG_SEL_MASK \ |
| 183 | (scn->targetdef->d_AMBA_DEBUG_BUS_PCIE_DEBUG_SEL_MASK) |
| 184 | #define AMBA_DEBUG_BUS_SEL_MSB (scn->targetdef->d_AMBA_DEBUG_BUS_SEL_MSB) |
| 185 | #define AMBA_DEBUG_BUS_SEL_LSB (scn->targetdef->d_AMBA_DEBUG_BUS_SEL_LSB) |
| 186 | #define AMBA_DEBUG_BUS_SEL_MASK (scn->targetdef->d_AMBA_DEBUG_BUS_SEL_MASK) |
| 187 | #define CE_WRAPPER_DEBUG_OFFSET (scn->target_ce_def->d_CE_WRAPPER_DEBUG_OFFSET) |
| 188 | #define CE_WRAPPER_DEBUG_SEL_MSB (scn->target_ce_def->d_CE_WRAPPER_DEBUG_SEL_MSB) |
| 189 | #define CE_WRAPPER_DEBUG_SEL_LSB (scn->target_ce_def->d_CE_WRAPPER_DEBUG_SEL_LSB) |
| 190 | #define CE_WRAPPER_DEBUG_SEL_MASK (scn->target_ce_def->d_CE_WRAPPER_DEBUG_SEL_MASK) |
| 191 | #define CE_DEBUG_OFFSET (scn->target_ce_def->d_CE_DEBUG_OFFSET) |
| 192 | #define CE_DEBUG_SEL_MSB (scn->target_ce_def->d_CE_DEBUG_SEL_MSB) |
| 193 | #define CE_DEBUG_SEL_LSB (scn->target_ce_def->d_CE_DEBUG_SEL_LSB) |
| 194 | #define CE_DEBUG_SEL_MASK (scn->target_ce_def->d_CE_DEBUG_SEL_MASK) |
| 195 | #define HOST_IE_ADDRESS (scn->target_ce_def->d_HOST_IE_ADDRESS) |
| 196 | #define HOST_IS_ADDRESS (scn->target_ce_def->d_HOST_IS_ADDRESS) |
| 197 | |
| 198 | #define SRC_WATERMARK_LOW_SET(x) \ |
| 199 | (((x) << SRC_WATERMARK_LOW_LSB) & SRC_WATERMARK_LOW_MASK) |
| 200 | #define SRC_WATERMARK_HIGH_SET(x) \ |
| 201 | (((x) << SRC_WATERMARK_HIGH_LSB) & SRC_WATERMARK_HIGH_MASK) |
| 202 | #define DST_WATERMARK_LOW_SET(x) \ |
| 203 | (((x) << DST_WATERMARK_LOW_LSB) & DST_WATERMARK_LOW_MASK) |
| 204 | #define DST_WATERMARK_HIGH_SET(x) \ |
| 205 | (((x) << DST_WATERMARK_HIGH_LSB) & DST_WATERMARK_HIGH_MASK) |
| 206 | #define CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_GET(x) \ |
| 207 | (((x) & CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_MASK) >> \ |
| 208 | CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_LSB) |
| 209 | #define CE_CTRL1_DMAX_LENGTH_SET(x) \ |
| 210 | (((x) << CE_CTRL1_DMAX_LENGTH_LSB) & CE_CTRL1_DMAX_LENGTH_MASK) |
| 211 | #define CE_CTRL1_SRC_RING_BYTE_SWAP_EN_SET(x) \ |
| 212 | (((x) << CE_CTRL1_SRC_RING_BYTE_SWAP_EN_LSB) & \ |
| 213 | CE_CTRL1_SRC_RING_BYTE_SWAP_EN_MASK) |
| 214 | #define CE_CTRL1_DST_RING_BYTE_SWAP_EN_SET(x) \ |
| 215 | (((x) << CE_CTRL1_DST_RING_BYTE_SWAP_EN_LSB) & \ |
| 216 | CE_CTRL1_DST_RING_BYTE_SWAP_EN_MASK) |
| 217 | #define WLAN_DEBUG_INPUT_SEL_SRC_GET(x) \ |
| 218 | (((x) & WLAN_DEBUG_INPUT_SEL_SRC_MASK) >> \ |
| 219 | WLAN_DEBUG_INPUT_SEL_SRC_LSB) |
| 220 | #define WLAN_DEBUG_INPUT_SEL_SRC_SET(x) \ |
| 221 | (((x) << WLAN_DEBUG_INPUT_SEL_SRC_LSB) & \ |
| 222 | WLAN_DEBUG_INPUT_SEL_SRC_MASK) |
| 223 | #define WLAN_DEBUG_CONTROL_ENABLE_GET(x) \ |
| 224 | (((x) & WLAN_DEBUG_CONTROL_ENABLE_MASK) >> \ |
| 225 | WLAN_DEBUG_CONTROL_ENABLE_LSB) |
| 226 | #define WLAN_DEBUG_CONTROL_ENABLE_SET(x) \ |
| 227 | (((x) << WLAN_DEBUG_CONTROL_ENABLE_LSB) & \ |
| 228 | WLAN_DEBUG_CONTROL_ENABLE_MASK) |
| 229 | #define WLAN_DEBUG_OUT_DATA_GET(x) \ |
| 230 | (((x) & WLAN_DEBUG_OUT_DATA_MASK) >> WLAN_DEBUG_OUT_DATA_LSB) |
| 231 | #define WLAN_DEBUG_OUT_DATA_SET(x) \ |
| 232 | (((x) << WLAN_DEBUG_OUT_DATA_LSB) & WLAN_DEBUG_OUT_DATA_MASK) |
| 233 | #define AMBA_DEBUG_BUS_PCIE_DEBUG_SEL_GET(x) \ |
| 234 | (((x) & AMBA_DEBUG_BUS_PCIE_DEBUG_SEL_MASK) >> \ |
| 235 | AMBA_DEBUG_BUS_PCIE_DEBUG_SEL_LSB) |
| 236 | #define AMBA_DEBUG_BUS_PCIE_DEBUG_SEL_SET(x) \ |
| 237 | (((x) << AMBA_DEBUG_BUS_PCIE_DEBUG_SEL_LSB) & \ |
| 238 | AMBA_DEBUG_BUS_PCIE_DEBUG_SEL_MASK) |
| 239 | #define AMBA_DEBUG_BUS_SEL_GET(x) \ |
| 240 | (((x) & AMBA_DEBUG_BUS_SEL_MASK) >> AMBA_DEBUG_BUS_SEL_LSB) |
| 241 | #define AMBA_DEBUG_BUS_SEL_SET(x) \ |
| 242 | (((x) << AMBA_DEBUG_BUS_SEL_LSB) & AMBA_DEBUG_BUS_SEL_MASK) |
| 243 | #define CE_WRAPPER_DEBUG_SEL_GET(x) \ |
| 244 | (((x) & CE_WRAPPER_DEBUG_SEL_MASK) >> CE_WRAPPER_DEBUG_SEL_LSB) |
| 245 | #define CE_WRAPPER_DEBUG_SEL_SET(x) \ |
| 246 | (((x) << CE_WRAPPER_DEBUG_SEL_LSB) & CE_WRAPPER_DEBUG_SEL_MASK) |
| 247 | #define CE_DEBUG_SEL_GET(x) (((x) & CE_DEBUG_SEL_MASK) >> CE_DEBUG_SEL_LSB) |
| 248 | #define CE_DEBUG_SEL_SET(x) (((x) << CE_DEBUG_SEL_LSB) & CE_DEBUG_SEL_MASK) |
| 249 | |
Komal Seelam | 644263d | 2016-02-22 20:45:49 +0530 | [diff] [blame] | 250 | uint32_t DEBUG_CE_SRC_RING_READ_IDX_GET(struct hif_softc *scn, |
Sanjay Devnani | cdab59e | 2015-11-12 14:43:58 -0800 | [diff] [blame] | 251 | uint32_t CE_ctrl_addr); |
Komal Seelam | 644263d | 2016-02-22 20:45:49 +0530 | [diff] [blame] | 252 | uint32_t DEBUG_CE_DEST_RING_READ_IDX_GET(struct hif_softc *scn, |
Sanjay Devnani | cdab59e | 2015-11-12 14:43:58 -0800 | [diff] [blame] | 253 | uint32_t CE_ctrl_addr); |
| 254 | |
| 255 | #define BITS0_TO_31(val) ((uint32_t)((uint64_t)(paddr_rri_on_ddr)\ |
| 256 | & (uint64_t)(0xFFFFFFFF))) |
| 257 | #define BITS32_TO_35(val) ((uint32_t)(((uint64_t)(paddr_rri_on_ddr)\ |
| 258 | & (uint64_t)(0xF00000000))>>32)) |
| 259 | |
| 260 | #define VADDR_FOR_CE(scn, CE_ctrl_addr)\ |
Hardik Kantilal Patel | 3437392 | 2016-07-13 22:14:14 +0530 | [diff] [blame^] | 261 | ((scn->vaddr_rri_on_ddr) + COPY_ENGINE_ID(CE_ctrl_addr)) |
Sanjay Devnani | cdab59e | 2015-11-12 14:43:58 -0800 | [diff] [blame] | 262 | |
| 263 | #define SRRI_FROM_DDR_ADDR(addr) ((*(addr)) & 0xFFFF) |
| 264 | #define DRRI_FROM_DDR_ADDR(addr) (((*(addr))>>16) & 0xFFFF) |
| 265 | |
Houston Hoffman | 4780817 | 2016-05-06 10:04:21 -0700 | [diff] [blame] | 266 | #define CE_SRC_RING_READ_IDX_GET_FROM_REGISTER(scn, CE_ctrl_addr) \ |
| 267 | A_TARGET_READ(scn, (CE_ctrl_addr) + CURRENT_SRRI_ADDRESS) |
| 268 | #define CE_DEST_RING_READ_IDX_GET_FROM_REGISTER(scn, CE_ctrl_addr) \ |
| 269 | A_TARGET_READ(scn, (CE_ctrl_addr) + CURRENT_DRRI_ADDRESS) |
| 270 | |
Houston Hoffman | 5998d5f | 2015-12-03 13:25:05 -0800 | [diff] [blame] | 271 | #ifdef ADRASTEA_RRI_ON_DDR |
Sanjay Devnani | cdab59e | 2015-11-12 14:43:58 -0800 | [diff] [blame] | 272 | #ifdef SHADOW_REG_DEBUG |
| 273 | #define CE_SRC_RING_READ_IDX_GET_FROM_DDR(scn, CE_ctrl_addr)\ |
| 274 | DEBUG_CE_SRC_RING_READ_IDX_GET(scn, CE_ctrl_addr) |
| 275 | #define CE_DEST_RING_READ_IDX_GET_FROM_DDR(scn, CE_ctrl_addr)\ |
| 276 | DEBUG_CE_DEST_RING_READ_IDX_GET(scn, CE_ctrl_addr) |
| 277 | #else |
| 278 | #define CE_SRC_RING_READ_IDX_GET_FROM_DDR(scn, CE_ctrl_addr)\ |
| 279 | SRRI_FROM_DDR_ADDR(VADDR_FOR_CE(scn, CE_ctrl_addr)) |
| 280 | #define CE_DEST_RING_READ_IDX_GET_FROM_DDR(scn, CE_ctrl_addr)\ |
| 281 | DRRI_FROM_DDR_ADDR(VADDR_FOR_CE(scn, CE_ctrl_addr)) |
| 282 | #endif |
| 283 | |
Komal Seelam | 644263d | 2016-02-22 20:45:49 +0530 | [diff] [blame] | 284 | unsigned int hif_get_src_ring_read_index(struct hif_softc *scn, |
Sanjay Devnani | cdab59e | 2015-11-12 14:43:58 -0800 | [diff] [blame] | 285 | uint32_t CE_ctrl_addr); |
Komal Seelam | 644263d | 2016-02-22 20:45:49 +0530 | [diff] [blame] | 286 | unsigned int hif_get_dst_ring_read_index(struct hif_softc *scn, |
Sanjay Devnani | cdab59e | 2015-11-12 14:43:58 -0800 | [diff] [blame] | 287 | uint32_t CE_ctrl_addr); |
| 288 | |
Sanjay Devnani | cdab59e | 2015-11-12 14:43:58 -0800 | [diff] [blame] | 289 | #define CE_SRC_RING_READ_IDX_GET(scn, CE_ctrl_addr)\ |
| 290 | hif_get_src_ring_read_index(scn, CE_ctrl_addr) |
| 291 | #define CE_DEST_RING_READ_IDX_GET(scn, CE_ctrl_addr)\ |
| 292 | hif_get_dst_ring_read_index(scn, CE_ctrl_addr) |
| 293 | #else |
Prakash Dhavali | 7090c5f | 2015-11-02 17:55:19 -0800 | [diff] [blame] | 294 | #define CE_SRC_RING_READ_IDX_GET(scn, CE_ctrl_addr) \ |
Houston Hoffman | 4780817 | 2016-05-06 10:04:21 -0700 | [diff] [blame] | 295 | CE_SRC_RING_READ_IDX_GET_FROM_REGISTER(scn, CE_ctrl_addr) |
Sanjay Devnani | cdab59e | 2015-11-12 14:43:58 -0800 | [diff] [blame] | 296 | #define CE_DEST_RING_READ_IDX_GET(scn, CE_ctrl_addr)\ |
Houston Hoffman | 4780817 | 2016-05-06 10:04:21 -0700 | [diff] [blame] | 297 | CE_DEST_RING_READ_IDX_GET_FROM_REGISTER(scn, CE_ctrl_addr) |
Houston Hoffman | 5998d5f | 2015-12-03 13:25:05 -0800 | [diff] [blame] | 298 | |
| 299 | /** |
| 300 | * if RRI on DDR is not enabled, get idx from ddr defaults to |
| 301 | * using the register value & force wake must be used for |
| 302 | * non interrupt processing. |
| 303 | */ |
| 304 | #define CE_SRC_RING_READ_IDX_GET_FROM_DDR(scn, CE_ctrl_addr)\ |
| 305 | A_TARGET_READ(scn, (CE_ctrl_addr) + CURRENT_SRRI_ADDRESS) |
Sanjay Devnani | cdab59e | 2015-11-12 14:43:58 -0800 | [diff] [blame] | 306 | #endif |
Prakash Dhavali | 7090c5f | 2015-11-02 17:55:19 -0800 | [diff] [blame] | 307 | |
| 308 | #define CE_SRC_RING_BASE_ADDR_SET(scn, CE_ctrl_addr, addr) \ |
| 309 | A_TARGET_WRITE(scn, (CE_ctrl_addr) + SR_BA_ADDRESS, (addr)) |
| 310 | |
| 311 | #define CE_SRC_RING_BASE_ADDR_HIGH_SET(scn, CE_ctrl_addr, addr) \ |
| 312 | A_TARGET_WRITE(scn, (CE_ctrl_addr) + SR_BA_ADDRESS_HIGH, (addr)) |
| 313 | |
| 314 | #define CE_SRC_RING_BASE_ADDR_HIGH_GET(scn, CE_ctrl_addr) \ |
| 315 | A_TARGET_READ(scn, (CE_ctrl_addr) + SR_BA_ADDRESS_HIGH) |
| 316 | |
| 317 | #define CE_SRC_RING_SZ_SET(scn, CE_ctrl_addr, n) \ |
| 318 | A_TARGET_WRITE(scn, (CE_ctrl_addr) + SR_SIZE_ADDRESS, (n)) |
| 319 | |
| 320 | #define CE_SRC_RING_DMAX_SET(scn, CE_ctrl_addr, n) \ |
| 321 | A_TARGET_WRITE(scn, (CE_ctrl_addr) + CE_CTRL1_ADDRESS, \ |
| 322 | (A_TARGET_READ(scn, (CE_ctrl_addr) + \ |
| 323 | CE_CTRL1_ADDRESS) & ~CE_CTRL1_DMAX_LENGTH_MASK) | \ |
| 324 | CE_CTRL1_DMAX_LENGTH_SET(n)) |
| 325 | |
Sanjay Devnani | cdab59e | 2015-11-12 14:43:58 -0800 | [diff] [blame] | 326 | #define CE_IDX_UPD_EN_SET(scn, CE_ctrl_addr) \ |
| 327 | A_TARGET_WRITE(scn, (CE_ctrl_addr) + CE_CTRL1_ADDRESS, \ |
| 328 | (A_TARGET_READ(scn, (CE_ctrl_addr) + CE_CTRL1_ADDRESS) \ |
| 329 | | CE_CTRL1_IDX_UPD_EN)) |
| 330 | |
Prakash Dhavali | 7090c5f | 2015-11-02 17:55:19 -0800 | [diff] [blame] | 331 | #define CE_CMD_REGISTER_GET(scn, CE_ctrl_addr) \ |
| 332 | A_TARGET_READ(scn, (CE_ctrl_addr) + CE_CMD_REGISTER) |
| 333 | |
| 334 | #define CE_CMD_REGISTER_SET(scn, CE_ctrl_addr, n) \ |
| 335 | A_TARGET_WRITE(scn, (CE_ctrl_addr) + CE_CMD_REGISTER, n) |
| 336 | |
| 337 | #define CE_MSI_ADDR_LOW_SET(scn, CE_ctrl_addr, addr) \ |
| 338 | A_TARGET_WRITE(scn, (CE_ctrl_addr) + CE_MSI_ADDRESS, (addr)) |
| 339 | |
| 340 | #define CE_MSI_ADDR_HIGH_SET(scn, CE_ctrl_addr, addr) \ |
| 341 | A_TARGET_WRITE(scn, (CE_ctrl_addr) + CE_MSI_ADDRESS_HIGH, (addr)) |
| 342 | |
| 343 | #define CE_MSI_DATA_SET(scn, CE_ctrl_addr, data) \ |
| 344 | A_TARGET_WRITE(scn, (CE_ctrl_addr) + CE_MSI_DATA, (data)) |
| 345 | |
| 346 | #define CE_CTRL_REGISTER1_SET(scn, CE_ctrl_addr, val) \ |
| 347 | A_TARGET_WRITE(scn, (CE_ctrl_addr) + CE_CTRL1_ADDRESS, val) |
| 348 | |
| 349 | #define CE_CTRL_REGISTER1_GET(scn, CE_ctrl_addr) \ |
| 350 | A_TARGET_READ(scn, (CE_ctrl_addr) + CE_CTRL1_ADDRESS) |
| 351 | |
| 352 | #define CE_SRC_RING_BYTE_SWAP_SET(scn, CE_ctrl_addr, n) \ |
| 353 | A_TARGET_WRITE(scn, (CE_ctrl_addr) + CE_CTRL1_ADDRESS, \ |
| 354 | (A_TARGET_READ((targid), \ |
| 355 | (CE_ctrl_addr) + CE_CTRL1_ADDRESS) \ |
| 356 | & ~CE_CTRL1_SRC_RING_BYTE_SWAP_EN_MASK) | \ |
| 357 | CE_CTRL1_SRC_RING_BYTE_SWAP_EN_SET(n)) |
| 358 | |
| 359 | #define CE_DEST_RING_BYTE_SWAP_SET(scn, CE_ctrl_addr, n) \ |
| 360 | A_TARGET_WRITE(scn, (CE_ctrl_addr)+CE_CTRL1_ADDRESS, \ |
| 361 | (A_TARGET_READ((targid), \ |
| 362 | (CE_ctrl_addr) + CE_CTRL1_ADDRESS) \ |
| 363 | & ~CE_CTRL1_DST_RING_BYTE_SWAP_EN_MASK) | \ |
| 364 | CE_CTRL1_DST_RING_BYTE_SWAP_EN_SET(n)) |
| 365 | |
Prakash Dhavali | 7090c5f | 2015-11-02 17:55:19 -0800 | [diff] [blame] | 366 | |
| 367 | #define CE_DEST_RING_BASE_ADDR_SET(scn, CE_ctrl_addr, addr) \ |
| 368 | A_TARGET_WRITE(scn, (CE_ctrl_addr) + DR_BA_ADDRESS, (addr)) |
| 369 | |
| 370 | #define CE_DEST_RING_BASE_ADDR_HIGH_SET(scn, CE_ctrl_addr, addr) \ |
| 371 | A_TARGET_WRITE(scn, (CE_ctrl_addr) + DR_BA_ADDRESS_HIGH, (addr)) |
| 372 | |
| 373 | #define CE_DEST_RING_BASE_ADDR_HIGH_GET(scn, CE_ctrl_addr) \ |
| 374 | A_TARGET_READ(scn, (CE_ctrl_addr) + DR_BA_ADDRESS_HIGH) |
| 375 | |
| 376 | #define CE_DEST_RING_SZ_SET(scn, CE_ctrl_addr, n) \ |
| 377 | A_TARGET_WRITE(scn, (CE_ctrl_addr) + DR_SIZE_ADDRESS, (n)) |
| 378 | |
| 379 | #define CE_SRC_RING_HIGHMARK_SET(scn, CE_ctrl_addr, n) \ |
| 380 | A_TARGET_WRITE(scn, (CE_ctrl_addr) + SRC_WATERMARK_ADDRESS, \ |
| 381 | (A_TARGET_READ(scn, \ |
| 382 | (CE_ctrl_addr) + SRC_WATERMARK_ADDRESS) \ |
| 383 | & ~SRC_WATERMARK_HIGH_MASK) | \ |
| 384 | SRC_WATERMARK_HIGH_SET(n)) |
| 385 | |
| 386 | #define CE_SRC_RING_LOWMARK_SET(scn, CE_ctrl_addr, n) \ |
| 387 | A_TARGET_WRITE(scn, (CE_ctrl_addr) + SRC_WATERMARK_ADDRESS, \ |
| 388 | (A_TARGET_READ(scn, \ |
| 389 | (CE_ctrl_addr) + SRC_WATERMARK_ADDRESS) \ |
| 390 | & ~SRC_WATERMARK_LOW_MASK) | \ |
| 391 | SRC_WATERMARK_LOW_SET(n)) |
| 392 | |
| 393 | #define CE_DEST_RING_HIGHMARK_SET(scn, CE_ctrl_addr, n) \ |
| 394 | A_TARGET_WRITE(scn, (CE_ctrl_addr) + DST_WATERMARK_ADDRESS, \ |
| 395 | (A_TARGET_READ(scn, \ |
| 396 | (CE_ctrl_addr) + DST_WATERMARK_ADDRESS) \ |
| 397 | & ~DST_WATERMARK_HIGH_MASK) | \ |
| 398 | DST_WATERMARK_HIGH_SET(n)) |
| 399 | |
| 400 | #define CE_DEST_RING_LOWMARK_SET(scn, CE_ctrl_addr, n) \ |
| 401 | A_TARGET_WRITE(scn, (CE_ctrl_addr) + DST_WATERMARK_ADDRESS, \ |
| 402 | (A_TARGET_READ(scn, \ |
| 403 | (CE_ctrl_addr) + DST_WATERMARK_ADDRESS) \ |
| 404 | & ~DST_WATERMARK_LOW_MASK) | \ |
| 405 | DST_WATERMARK_LOW_SET(n)) |
| 406 | |
| 407 | #define CE_COPY_COMPLETE_INTR_ENABLE(scn, CE_ctrl_addr) \ |
| 408 | A_TARGET_WRITE(scn, (CE_ctrl_addr) + HOST_IE_ADDRESS, \ |
| 409 | A_TARGET_READ(scn, \ |
| 410 | (CE_ctrl_addr) + HOST_IE_ADDRESS) | \ |
| 411 | HOST_IE_COPY_COMPLETE_MASK) |
| 412 | |
| 413 | #define CE_COPY_COMPLETE_INTR_DISABLE(scn, CE_ctrl_addr) \ |
| 414 | A_TARGET_WRITE(scn, (CE_ctrl_addr) + HOST_IE_ADDRESS, \ |
| 415 | A_TARGET_READ(scn, \ |
| 416 | (CE_ctrl_addr) + HOST_IE_ADDRESS) \ |
| 417 | & ~HOST_IE_COPY_COMPLETE_MASK) |
| 418 | |
| 419 | #define CE_BASE_ADDRESS(CE_id) \ |
| 420 | CE0_BASE_ADDRESS + ((CE1_BASE_ADDRESS - \ |
| 421 | CE0_BASE_ADDRESS)*(CE_id)) |
| 422 | |
| 423 | #define CE_WATERMARK_INTR_ENABLE(scn, CE_ctrl_addr) \ |
| 424 | A_TARGET_WRITE(scn, (CE_ctrl_addr) + HOST_IE_ADDRESS, \ |
| 425 | A_TARGET_READ(scn, \ |
| 426 | (CE_ctrl_addr) + HOST_IE_ADDRESS) | \ |
| 427 | CE_WATERMARK_MASK) |
| 428 | |
| 429 | #define CE_WATERMARK_INTR_DISABLE(scn, CE_ctrl_addr) \ |
| 430 | A_TARGET_WRITE(scn, (CE_ctrl_addr) + HOST_IE_ADDRESS, \ |
| 431 | A_TARGET_READ(scn, \ |
| 432 | (CE_ctrl_addr) + HOST_IE_ADDRESS) \ |
| 433 | & ~CE_WATERMARK_MASK) |
| 434 | |
| 435 | #define CE_ERROR_INTR_ENABLE(scn, CE_ctrl_addr) \ |
| 436 | A_TARGET_WRITE(scn, (CE_ctrl_addr) + MISC_IE_ADDRESS, \ |
| 437 | A_TARGET_READ(scn, \ |
| 438 | (CE_ctrl_addr) + MISC_IE_ADDRESS) | CE_ERROR_MASK) |
| 439 | |
| 440 | #define CE_MISC_INT_STATUS_GET(scn, CE_ctrl_addr) \ |
| 441 | A_TARGET_READ(scn, (CE_ctrl_addr) + MISC_IS_ADDRESS) |
| 442 | |
| 443 | #define CE_ENGINE_INT_STATUS_GET(scn, CE_ctrl_addr) \ |
| 444 | A_TARGET_READ(scn, (CE_ctrl_addr) + HOST_IS_ADDRESS) |
| 445 | |
| 446 | #define CE_ENGINE_INT_STATUS_CLEAR(scn, CE_ctrl_addr, mask) \ |
| 447 | A_TARGET_WRITE(scn, (CE_ctrl_addr) + HOST_IS_ADDRESS, (mask)) |
| 448 | |
Prakash Dhavali | 7090c5f | 2015-11-02 17:55:19 -0800 | [diff] [blame] | 449 | #define CE_WATERMARK_MASK (HOST_IS_SRC_RING_LOW_WATERMARK_MASK | \ |
| 450 | HOST_IS_SRC_RING_HIGH_WATERMARK_MASK | \ |
| 451 | HOST_IS_DST_RING_LOW_WATERMARK_MASK | \ |
| 452 | HOST_IS_DST_RING_HIGH_WATERMARK_MASK) |
| 453 | |
| 454 | #define CE_ERROR_MASK (MISC_IS_AXI_ERR_MASK | \ |
| 455 | MISC_IS_DST_ADDR_ERR_MASK | \ |
| 456 | MISC_IS_SRC_LEN_ERR_MASK | \ |
| 457 | MISC_IS_DST_MAX_LEN_VIO_MASK | \ |
| 458 | MISC_IS_DST_RING_OVERFLOW_MASK | \ |
| 459 | MISC_IS_SRC_RING_OVERFLOW_MASK) |
| 460 | |
| 461 | #define CE_SRC_RING_TO_DESC(baddr, idx) \ |
| 462 | (&(((struct CE_src_desc *)baddr)[idx])) |
| 463 | #define CE_DEST_RING_TO_DESC(baddr, idx) \ |
| 464 | (&(((struct CE_dest_desc *)baddr)[idx])) |
| 465 | |
| 466 | /* Ring arithmetic (modulus number of entries in ring, which is a pwr of 2). */ |
| 467 | #define CE_RING_DELTA(nentries_mask, fromidx, toidx) \ |
| 468 | (((int)(toidx)-(int)(fromidx)) & (nentries_mask)) |
| 469 | |
| 470 | #define CE_RING_IDX_INCR(nentries_mask, idx) \ |
| 471 | (((idx) + 1) & (nentries_mask)) |
| 472 | |
| 473 | #define CE_RING_IDX_ADD(nentries_mask, idx, num) \ |
| 474 | (((idx) + (num)) & (nentries_mask)) |
| 475 | |
| 476 | #define CE_INTERRUPT_SUMMARY(scn) \ |
| 477 | CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_GET( \ |
| 478 | A_TARGET_READ(scn, CE_WRAPPER_BASE_ADDRESS + \ |
| 479 | CE_WRAPPER_INTERRUPT_SUMMARY_ADDRESS)) |
| 480 | |
Sanjay Devnani | cdab59e | 2015-11-12 14:43:58 -0800 | [diff] [blame] | 481 | #define READ_CE_DDR_ADDRESS_FOR_RRI_LOW(scn) \ |
| 482 | (A_TARGET_READ(scn, \ |
| 483 | CE_WRAPPER_BASE_ADDRESS + CE_DDR_ADDRESS_FOR_RRI_LOW)) |
| 484 | |
| 485 | #define READ_CE_DDR_ADDRESS_FOR_RRI_HIGH(scn) \ |
| 486 | (A_TARGET_READ(scn, \ |
| 487 | CE_WRAPPER_BASE_ADDRESS + CE_DDR_ADDRESS_FOR_RRI_HIGH)) |
| 488 | |
| 489 | #define WRITE_CE_DDR_ADDRESS_FOR_RRI_LOW(scn, val) \ |
| 490 | (A_TARGET_WRITE(scn, \ |
| 491 | CE_WRAPPER_BASE_ADDRESS + CE_DDR_ADDRESS_FOR_RRI_LOW, \ |
| 492 | val)) |
| 493 | |
| 494 | #define WRITE_CE_DDR_ADDRESS_FOR_RRI_HIGH(scn, val) \ |
| 495 | (A_TARGET_WRITE(scn, \ |
| 496 | CE_WRAPPER_BASE_ADDRESS + CE_DDR_ADDRESS_FOR_RRI_HIGH, \ |
| 497 | val)) |
| 498 | |
Prakash Dhavali | 7090c5f | 2015-11-02 17:55:19 -0800 | [diff] [blame] | 499 | /*Macro to increment CE packet errors*/ |
| 500 | #define OL_ATH_CE_PKT_ERROR_COUNT_INCR(_scn, _ce_ecode) \ |
| 501 | do { if (_ce_ecode == CE_RING_DELTA_FAIL) \ |
| 502 | (_scn->pkt_stats.ce_ring_delta_fail_count) \ |
| 503 | += 1; } while (0) |
| 504 | |
| 505 | /* Given a Copy Engine's ID, determine the interrupt number for that |
| 506 | * copy engine's interrupts. |
| 507 | */ |
| 508 | #define CE_ID_TO_INUM(id) (A_INUM_CE0_COPY_COMP_BASE + (id)) |
| 509 | #define CE_INUM_TO_ID(inum) ((inum) - A_INUM_CE0_COPY_COMP_BASE) |
| 510 | #define CE0_BASE_ADDRESS (scn->target_ce_def->d_CE0_BASE_ADDRESS) |
| 511 | #define CE1_BASE_ADDRESS (scn->target_ce_def->d_CE1_BASE_ADDRESS) |
| 512 | |
Houston Hoffman | 4780817 | 2016-05-06 10:04:21 -0700 | [diff] [blame] | 513 | |
Prakash Dhavali | 7090c5f | 2015-11-02 17:55:19 -0800 | [diff] [blame] | 514 | #ifdef ADRASTEA_SHADOW_REGISTERS |
Prakash Dhavali | 7090c5f | 2015-11-02 17:55:19 -0800 | [diff] [blame] | 515 | #define NUM_SHADOW_REGISTERS 24 |
Komal Seelam | 644263d | 2016-02-22 20:45:49 +0530 | [diff] [blame] | 516 | u32 shadow_sr_wr_ind_addr(struct hif_softc *scn, u32 ctrl_addr); |
| 517 | u32 shadow_dst_wr_ind_addr(struct hif_softc *scn, u32 ctrl_addr); |
Houston Hoffman | 4780817 | 2016-05-06 10:04:21 -0700 | [diff] [blame] | 518 | #endif |
| 519 | |
| 520 | |
| 521 | #ifdef ADRASTEA_SHADOW_REGISTERS |
Prakash Dhavali | 7090c5f | 2015-11-02 17:55:19 -0800 | [diff] [blame] | 522 | #define CE_SRC_RING_WRITE_IDX_SET(scn, CE_ctrl_addr, n) \ |
| 523 | A_TARGET_WRITE(scn, shadow_sr_wr_ind_addr(scn, CE_ctrl_addr), n) |
Prakash Dhavali | 7090c5f | 2015-11-02 17:55:19 -0800 | [diff] [blame] | 524 | #define CE_DEST_RING_WRITE_IDX_SET(scn, CE_ctrl_addr, n) \ |
| 525 | A_TARGET_WRITE(scn, shadow_dst_wr_ind_addr(scn, CE_ctrl_addr), n) |
| 526 | |
Prakash Dhavali | 7090c5f | 2015-11-02 17:55:19 -0800 | [diff] [blame] | 527 | #else |
| 528 | |
| 529 | #define CE_SRC_RING_WRITE_IDX_SET(scn, CE_ctrl_addr, n) \ |
| 530 | A_TARGET_WRITE(scn, (CE_ctrl_addr) + SR_WR_INDEX_ADDRESS, (n)) |
Prakash Dhavali | 7090c5f | 2015-11-02 17:55:19 -0800 | [diff] [blame] | 531 | #define CE_DEST_RING_WRITE_IDX_SET(scn, CE_ctrl_addr, n) \ |
| 532 | A_TARGET_WRITE(scn, (CE_ctrl_addr) + DST_WR_INDEX_ADDRESS, (n)) |
Prakash Dhavali | 7090c5f | 2015-11-02 17:55:19 -0800 | [diff] [blame] | 533 | #endif |
| 534 | |
Houston Hoffman | 4780817 | 2016-05-06 10:04:21 -0700 | [diff] [blame] | 535 | /* The write index read is only needed durring initialization because |
| 536 | * we keep track of the index that was last written. Thus the register |
| 537 | * is the only hardware supported location to read the initial value from. |
| 538 | */ |
| 539 | #define CE_SRC_RING_WRITE_IDX_GET_FROM_REGISTER(scn, CE_ctrl_addr) \ |
| 540 | A_TARGET_READ(scn, (CE_ctrl_addr) + SR_WR_INDEX_ADDRESS) |
| 541 | #define CE_DEST_RING_WRITE_IDX_GET_FROM_REGISTER(scn, CE_ctrl_addr) \ |
| 542 | A_TARGET_READ(scn, (CE_ctrl_addr) + DST_WR_INDEX_ADDRESS) |
| 543 | |
Prakash Dhavali | 7090c5f | 2015-11-02 17:55:19 -0800 | [diff] [blame] | 544 | #endif /* __CE_REG_H__ */ |