Balamurugan Mahalingam | d015964 | 2018-07-11 15:02:29 +0530 | [diff] [blame] | 1 | /* |
Padma Raghunathan | 5cd2e56 | 2019-12-18 21:32:58 +0530 | [diff] [blame] | 2 | * Copyright (c) 2016-2020 The Linux Foundation. All rights reserved. |
Balamurugan Mahalingam | d015964 | 2018-07-11 15:02:29 +0530 | [diff] [blame] | 3 | * |
Balamurugan Mahalingam | 5d80641 | 2018-07-30 18:04:15 +0530 | [diff] [blame] | 4 | * Permission to use, copy, modify, and/or distribute this software for |
| 5 | * any purpose with or without fee is hereby granted, provided that the |
| 6 | * above copyright notice and this permission notice appear in all |
| 7 | * copies. |
Balamurugan Mahalingam | d015964 | 2018-07-11 15:02:29 +0530 | [diff] [blame] | 8 | * |
Balamurugan Mahalingam | 5d80641 | 2018-07-30 18:04:15 +0530 | [diff] [blame] | 9 | * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL |
| 10 | * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED |
| 11 | * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE |
| 12 | * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL |
| 13 | * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR |
| 14 | * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER |
| 15 | * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR |
| 16 | * PERFORMANCE OF THIS SOFTWARE. |
Balamurugan Mahalingam | d015964 | 2018-07-11 15:02:29 +0530 | [diff] [blame] | 17 | */ |
Balamurugan Mahalingam | d015964 | 2018-07-11 15:02:29 +0530 | [diff] [blame] | 18 | #include "hal_hw_headers.h" |
| 19 | #include "hal_internal.h" |
| 20 | #include "hal_api.h" |
| 21 | #include "target_type.h" |
| 22 | #include "wcss_version.h" |
| 23 | #include "qdf_module.h" |
Balamurugan Mahalingam | d015964 | 2018-07-11 15:02:29 +0530 | [diff] [blame] | 24 | |
Balamurugan Mahalingam | 5d80641 | 2018-07-30 18:04:15 +0530 | [diff] [blame] | 25 | #define UNIFIED_RXPCU_PPDU_END_INFO_8_RX_PPDU_DURATION_OFFSET \ |
| 26 | RXPCU_PPDU_END_INFO_9_RX_PPDU_DURATION_OFFSET |
| 27 | #define UNIFIED_RXPCU_PPDU_END_INFO_8_RX_PPDU_DURATION_MASK \ |
| 28 | RXPCU_PPDU_END_INFO_9_RX_PPDU_DURATION_MASK |
| 29 | #define UNIFIED_RXPCU_PPDU_END_INFO_8_RX_PPDU_DURATION_LSB \ |
| 30 | RXPCU_PPDU_END_INFO_9_RX_PPDU_DURATION_LSB |
| 31 | #define UNIFIED_PHYRX_HT_SIG_0_HT_SIG_INFO_PHYRX_HT_SIG_INFO_DETAILS_OFFSET \ |
| 32 | PHYRX_HT_SIG_0_PHYRX_HT_SIG_INFO_DETAILS_MCS_OFFSET |
| 33 | #define UNIFIED_PHYRX_L_SIG_B_0_L_SIG_B_INFO_PHYRX_L_SIG_B_INFO_DETAILS_OFFSET \ |
| 34 | PHYRX_L_SIG_B_0_PHYRX_L_SIG_B_INFO_DETAILS_RATE_OFFSET |
| 35 | #define UNIFIED_PHYRX_L_SIG_A_0_L_SIG_A_INFO_PHYRX_L_SIG_A_INFO_DETAILS_OFFSET \ |
| 36 | PHYRX_L_SIG_A_0_PHYRX_L_SIG_A_INFO_DETAILS_RATE_OFFSET |
| 37 | #define UNIFIED_PHYRX_VHT_SIG_A_0_VHT_SIG_A_INFO_PHYRX_VHT_SIG_A_INFO_DETAILS_OFFSET \ |
| 38 | PHYRX_VHT_SIG_A_0_PHYRX_VHT_SIG_A_INFO_DETAILS_BANDWIDTH_OFFSET |
| 39 | #define UNIFIED_PHYRX_HE_SIG_A_SU_0_HE_SIG_A_SU_INFO_PHYRX_HE_SIG_A_SU_INFO_DETAILS_OFFSET \ |
| 40 | PHYRX_HE_SIG_A_SU_0_PHYRX_HE_SIG_A_SU_INFO_DETAILS_FORMAT_INDICATION_OFFSET |
| 41 | #define UNIFIED_PHYRX_HE_SIG_A_MU_DL_0_HE_SIG_A_MU_DL_INFO_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_OFFSET \ |
| 42 | PHYRX_HE_SIG_A_MU_DL_0_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_DL_UL_FLAG_OFFSET |
| 43 | #define UNIFIED_PHYRX_HE_SIG_B1_MU_0_HE_SIG_B1_MU_INFO_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_OFFSET \ |
| 44 | PHYRX_HE_SIG_B1_MU_0_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_RU_ALLOCATION_OFFSET |
| 45 | #define UNIFIED_PHYRX_HE_SIG_B2_MU_0_HE_SIG_B2_MU_INFO_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_OFFSET \ |
| 46 | PHYRX_HE_SIG_B2_MU_0_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_ID_OFFSET |
| 47 | #define UNIFIED_PHYRX_HE_SIG_B2_OFDMA_0_HE_SIG_B2_OFDMA_INFO_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_OFFSET \ |
| 48 | PHYRX_HE_SIG_B2_OFDMA_0_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_ID_OFFSET |
| 49 | #define UNIFIED_PHYRX_RSSI_LEGACY_3_RECEIVE_RSSI_INFO_PRE_RSSI_INFO_DETAILS_OFFSET \ |
| 50 | PHYRX_RSSI_LEGACY_3_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_OFFSET |
Kai Chen | 52ef33f | 2019-03-05 18:33:40 -0800 | [diff] [blame] | 51 | #define UNIFIED_PHYRX_RSSI_LEGACY_19_RECEIVE_RSSI_INFO_PREAMBLE_RSSI_INFO_DETAILS_OFFSET \ |
| 52 | PHYRX_RSSI_LEGACY_19_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_OFFSET |
Balamurugan Mahalingam | 5d80641 | 2018-07-30 18:04:15 +0530 | [diff] [blame] | 53 | #define UNIFIED_RX_MPDU_START_0_RX_MPDU_INFO_RX_MPDU_INFO_DETAILS_OFFSET \ |
| 54 | RX_MPDU_START_0_RX_MPDU_INFO_DETAILS_RXPCU_MPDU_FILTER_IN_CATEGORY_OFFSET |
| 55 | #define UNIFIED_RX_MSDU_LINK_8_RX_MSDU_DETAILS_MSDU_0_OFFSET \ |
| 56 | RX_MSDU_LINK_8_MSDU_0_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET |
| 57 | #define UNIFIED_RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_OFFSET \ |
| 58 | RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET |
| 59 | #define UNIFIED_RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_RX_MPDU_DESC_INFO_DETAILS_OFFSET \ |
| 60 | RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_OFFSET |
| 61 | #define UNIFIED_REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_RX_MPDU_DESC_INFO_DETAILS_OFFSET \ |
| 62 | REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_OFFSET |
| 63 | #define UNIFORM_REO_STATUS_HEADER_STATUS_HEADER \ |
| 64 | STATUS_HEADER_REO_STATUS_NUMBER |
| 65 | #define UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC \ |
| 66 | STATUS_HEADER_TIMESTAMP |
| 67 | #define UNIFIED_RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_OFFSET \ |
| 68 | RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET |
| 69 | #define UNIFIED_RX_MSDU_LINK_8_RX_MSDU_DETAILS_MSDU_0_OFFSET \ |
| 70 | RX_MSDU_LINK_8_MSDU_0_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET |
| 71 | #define UNIFIED_TCL_DATA_CMD_0_BUFFER_ADDR_INFO_BUF_ADDR_INFO_OFFSET \ |
| 72 | TCL_DATA_CMD_0_BUF_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET |
| 73 | #define UNIFIED_TCL_DATA_CMD_1_BUFFER_ADDR_INFO_BUF_ADDR_INFO_OFFSET \ |
| 74 | TCL_DATA_CMD_1_BUF_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET |
| 75 | #define UNIFIED_TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_OFFSET \ |
| 76 | TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_OFFSET |
| 77 | #define UNIFIED_BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_LSB \ |
| 78 | BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_LSB |
| 79 | #define UNIFIED_BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_MASK \ |
| 80 | BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_MASK |
| 81 | #define UNIFIED_BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_LSB \ |
| 82 | BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_LSB |
| 83 | #define UNIFIED_BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_MASK \ |
| 84 | BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_MASK |
| 85 | #define UNIFIED_BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_LSB \ |
| 86 | BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_LSB |
| 87 | #define UNIFIED_BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_MASK \ |
| 88 | BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_MASK |
| 89 | #define UNIFIED_BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_LSB \ |
| 90 | BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_LSB |
| 91 | #define UNIFIED_BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_MASK \ |
| 92 | BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_MASK |
| 93 | #define UNIFIED_TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_LSB \ |
| 94 | TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_LSB |
| 95 | #define UNIFIED_TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_MASK \ |
| 96 | TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_MASK |
| 97 | #define UNIFIED_WBM_RELEASE_RING_6_TX_RATE_STATS_INFO_TX_RATE_STATS_MASK \ |
| 98 | WBM_RELEASE_RING_6_TX_RATE_STATS_PPDU_TRANSMISSION_TSF_MASK |
| 99 | #define UNIFIED_WBM_RELEASE_RING_6_TX_RATE_STATS_INFO_TX_RATE_STATS_OFFSET \ |
| 100 | WBM_RELEASE_RING_6_TX_RATE_STATS_PPDU_TRANSMISSION_TSF_OFFSET |
| 101 | #define UNIFIED_WBM_RELEASE_RING_6_TX_RATE_STATS_INFO_TX_RATE_STATS_LSB \ |
| 102 | WBM_RELEASE_RING_6_TX_RATE_STATS_PPDU_TRANSMISSION_TSF_LSB |
| 103 | #include "hal_8074v2_tx.h" |
| 104 | #include "hal_8074v2_rx.h" |
| 105 | #include <hal_generic_api.h> |
| 106 | #include <hal_wbm.h> |
| 107 | |
Venkata Sharath Chandra Manchala | d1b7e4c | 2019-09-20 10:01:21 -0700 | [diff] [blame] | 108 | /** |
| 109 | * hal_rx_get_rx_fragment_number_8074v2(): Function to retrieve |
| 110 | * rx fragment number |
| 111 | * |
| 112 | * @nbuf: Network buffer |
| 113 | * Returns: rx fragment number |
| 114 | */ |
| 115 | static |
| 116 | uint8_t hal_rx_get_rx_fragment_number_8074v2(uint8_t *buf) |
| 117 | { |
| 118 | struct rx_pkt_tlvs *pkt_tlvs = hal_rx_get_pkt_tlvs(buf); |
| 119 | struct rx_mpdu_info *rx_mpdu_info = hal_rx_get_mpdu_info(pkt_tlvs); |
| 120 | |
| 121 | /* Return first 4 bits as fragment number */ |
| 122 | return HAL_RX_MPDU_GET_SEQUENCE_NUMBER(rx_mpdu_info) & |
| 123 | DOT11_SEQ_FRAG_MASK; |
| 124 | } |
Venkata Sharath Chandra Manchala | ee90938 | 2019-09-20 10:52:37 -0700 | [diff] [blame] | 125 | |
| 126 | /** |
| 127 | * hal_rx_msdu_end_da_is_mcbc_get_8074v2: API to check if pkt is MCBC |
| 128 | * from rx_msdu_end TLV |
| 129 | * |
| 130 | * @ buf: pointer to the start of RX PKT TLV headers |
| 131 | * Return: da_is_mcbc |
| 132 | */ |
| 133 | static uint8_t |
| 134 | hal_rx_msdu_end_da_is_mcbc_get_8074v2(uint8_t *buf) |
| 135 | { |
| 136 | struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; |
| 137 | struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; |
| 138 | |
| 139 | return HAL_RX_MSDU_END_DA_IS_MCBC_GET(msdu_end); |
| 140 | } |
| 141 | |
Venkata Sharath Chandra Manchala | 59ebd5e | 2019-09-20 15:52:55 -0700 | [diff] [blame] | 142 | /** |
| 143 | * hal_rx_msdu_end_sa_is_valid_get_8074v2(): API to get_8074v2 the |
| 144 | * sa_is_valid bit from rx_msdu_end TLV |
| 145 | * |
| 146 | * @ buf: pointer to the start of RX PKT TLV headers |
| 147 | * Return: sa_is_valid bit |
| 148 | */ |
| 149 | static uint8_t |
| 150 | hal_rx_msdu_end_sa_is_valid_get_8074v2(uint8_t *buf) |
| 151 | { |
| 152 | struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; |
| 153 | struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; |
| 154 | uint8_t sa_is_valid; |
| 155 | |
| 156 | sa_is_valid = HAL_RX_MSDU_END_SA_IS_VALID_GET(msdu_end); |
| 157 | |
| 158 | return sa_is_valid; |
| 159 | } |
| 160 | |
Venkata Sharath Chandra Manchala | 5bf1e5a | 2019-09-20 16:18:42 -0700 | [diff] [blame] | 161 | /** |
| 162 | * hal_rx_msdu_end_sa_idx_get_8074v2(): API to get_8074v2 the |
| 163 | * sa_idx from rx_msdu_end TLV |
| 164 | * |
| 165 | * @ buf: pointer to the start of RX PKT TLV headers |
| 166 | * Return: sa_idx (SA AST index) |
| 167 | */ |
| 168 | static uint16_t hal_rx_msdu_end_sa_idx_get_8074v2(uint8_t *buf) |
| 169 | { |
| 170 | struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; |
| 171 | struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; |
| 172 | uint16_t sa_idx; |
| 173 | |
| 174 | sa_idx = HAL_RX_MSDU_END_SA_IDX_GET(msdu_end); |
| 175 | |
| 176 | return sa_idx; |
| 177 | } |
| 178 | |
Venkata Sharath Chandra Manchala | 43d5632 | 2019-09-20 16:51:48 -0700 | [diff] [blame] | 179 | /** |
| 180 | * hal_rx_desc_is_first_msdu_8074v2() - Check if first msdu |
| 181 | * |
| 182 | * @hal_soc_hdl: hal_soc handle |
| 183 | * @hw_desc_addr: hardware descriptor address |
| 184 | * |
| 185 | * Return: 0 - success/ non-zero failure |
| 186 | */ |
| 187 | static uint32_t hal_rx_desc_is_first_msdu_8074v2(void *hw_desc_addr) |
| 188 | { |
| 189 | struct rx_pkt_tlvs *rx_tlvs = (struct rx_pkt_tlvs *)hw_desc_addr; |
| 190 | struct rx_msdu_end *msdu_end = &rx_tlvs->msdu_end_tlv.rx_msdu_end; |
| 191 | |
| 192 | return HAL_RX_GET(msdu_end, RX_MSDU_END_5, FIRST_MSDU); |
| 193 | } |
| 194 | |
Venkata Sharath Chandra Manchala | f05b2ae | 2019-09-20 17:25:21 -0700 | [diff] [blame] | 195 | /** |
| 196 | * hal_rx_msdu_end_l3_hdr_padding_get_8074v2(): API to get_8074v2 the |
| 197 | * l3_header padding from rx_msdu_end TLV |
| 198 | * |
| 199 | * @ buf: pointer to the start of RX PKT TLV headers |
| 200 | * Return: number of l3 header padding bytes |
| 201 | */ |
| 202 | static uint32_t hal_rx_msdu_end_l3_hdr_padding_get_8074v2(uint8_t *buf) |
| 203 | { |
| 204 | struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; |
| 205 | struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; |
| 206 | uint32_t l3_header_padding; |
| 207 | |
| 208 | l3_header_padding = HAL_RX_MSDU_END_L3_HEADER_PADDING_GET(msdu_end); |
| 209 | |
| 210 | return l3_header_padding; |
| 211 | } |
| 212 | |
Venkata Sharath Chandra Manchala | c1a4c8b | 2019-09-20 17:42:07 -0700 | [diff] [blame] | 213 | /* |
| 214 | * @ hal_rx_encryption_info_valid_8074v2: Returns encryption type. |
| 215 | * |
| 216 | * @ buf: rx_tlv_hdr of the received packet |
| 217 | * @ Return: encryption type |
| 218 | */ |
| 219 | static uint32_t hal_rx_encryption_info_valid_8074v2(uint8_t *buf) |
| 220 | { |
| 221 | struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; |
| 222 | struct rx_mpdu_start *mpdu_start = |
| 223 | &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; |
| 224 | struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; |
| 225 | uint32_t encryption_info = HAL_RX_MPDU_ENCRYPTION_INFO_VALID(mpdu_info); |
| 226 | |
| 227 | return encryption_info; |
| 228 | } |
| 229 | |
Venkata Sharath Chandra Manchala | a2d7497 | 2019-09-20 18:02:57 -0700 | [diff] [blame] | 230 | /* |
| 231 | * @ hal_rx_print_pn_8074v2: Prints the PN of rx packet. |
| 232 | * |
| 233 | * @ buf: rx_tlv_hdr of the received packet |
| 234 | * @ Return: void |
| 235 | */ |
| 236 | static void hal_rx_print_pn_8074v2(uint8_t *buf) |
| 237 | { |
| 238 | struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; |
| 239 | struct rx_mpdu_start *mpdu_start = |
| 240 | &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; |
| 241 | struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; |
| 242 | |
| 243 | uint32_t pn_31_0 = HAL_RX_MPDU_PN_31_0_GET(mpdu_info); |
| 244 | uint32_t pn_63_32 = HAL_RX_MPDU_PN_63_32_GET(mpdu_info); |
| 245 | uint32_t pn_95_64 = HAL_RX_MPDU_PN_95_64_GET(mpdu_info); |
| 246 | uint32_t pn_127_96 = HAL_RX_MPDU_PN_127_96_GET(mpdu_info); |
| 247 | |
| 248 | hal_debug("PN number pn_127_96 0x%x pn_95_64 0x%x pn_63_32 0x%x pn_31_0 0x%x ", |
| 249 | pn_127_96, pn_95_64, pn_63_32, pn_31_0); |
| 250 | } |
| 251 | |
Venkata Sharath Chandra Manchala | cb255b4 | 2019-09-21 11:03:38 -0700 | [diff] [blame] | 252 | /** |
| 253 | * hal_rx_msdu_end_first_msdu_get_8074v2: API to get first msdu status |
| 254 | * from rx_msdu_end TLV |
| 255 | * |
| 256 | * @ buf: pointer to the start of RX PKT TLV headers |
| 257 | * Return: first_msdu |
| 258 | */ |
| 259 | static uint8_t hal_rx_msdu_end_first_msdu_get_8074v2(uint8_t *buf) |
| 260 | { |
| 261 | struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; |
| 262 | struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; |
| 263 | uint8_t first_msdu; |
| 264 | |
| 265 | first_msdu = HAL_RX_MSDU_END_FIRST_MSDU_GET(msdu_end); |
| 266 | |
| 267 | return first_msdu; |
| 268 | } |
| 269 | |
Venkata Sharath Chandra Manchala | 7905538 | 2019-09-21 11:22:30 -0700 | [diff] [blame] | 270 | /** |
| 271 | * hal_rx_msdu_end_da_is_valid_get_8074v2: API to check if da is valid |
| 272 | * from rx_msdu_end TLV |
| 273 | * |
| 274 | * @ buf: pointer to the start of RX PKT TLV headers |
| 275 | * Return: da_is_valid |
| 276 | */ |
| 277 | static uint8_t hal_rx_msdu_end_da_is_valid_get_8074v2(uint8_t *buf) |
| 278 | { |
| 279 | struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; |
| 280 | struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; |
| 281 | uint8_t da_is_valid; |
| 282 | |
| 283 | da_is_valid = HAL_RX_MSDU_END_DA_IS_VALID_GET(msdu_end); |
| 284 | |
| 285 | return da_is_valid; |
| 286 | } |
| 287 | |
Venkata Sharath Chandra Manchala | 55f2d92 | 2019-09-21 11:37:01 -0700 | [diff] [blame] | 288 | /** |
| 289 | * hal_rx_msdu_end_last_msdu_get_8074v2: API to get last msdu status |
| 290 | * from rx_msdu_end TLV |
| 291 | * |
| 292 | * @ buf: pointer to the start of RX PKT TLV headers |
| 293 | * Return: last_msdu |
| 294 | */ |
| 295 | static uint8_t hal_rx_msdu_end_last_msdu_get_8074v2(uint8_t *buf) |
| 296 | { |
| 297 | struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; |
| 298 | struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; |
| 299 | uint8_t last_msdu; |
| 300 | |
| 301 | last_msdu = HAL_RX_MSDU_END_LAST_MSDU_GET(msdu_end); |
| 302 | |
| 303 | return last_msdu; |
| 304 | } |
| 305 | |
Venkata Sharath Chandra Manchala | 2a52d34 | 2019-09-21 11:52:54 -0700 | [diff] [blame] | 306 | /* |
| 307 | * hal_rx_get_mpdu_mac_ad4_valid_8074v2(): Retrieves if mpdu 4th addr is valid |
| 308 | * |
| 309 | * @nbuf: Network buffer |
| 310 | * Returns: value of mpdu 4th address valid field |
| 311 | */ |
| 312 | static bool hal_rx_get_mpdu_mac_ad4_valid_8074v2(uint8_t *buf) |
| 313 | { |
| 314 | struct rx_pkt_tlvs *pkt_tlvs = hal_rx_get_pkt_tlvs(buf); |
| 315 | struct rx_mpdu_info *rx_mpdu_info = hal_rx_get_mpdu_info(pkt_tlvs); |
| 316 | bool ad4_valid = 0; |
| 317 | |
| 318 | ad4_valid = HAL_RX_MPDU_GET_MAC_AD4_VALID(rx_mpdu_info); |
| 319 | |
| 320 | return ad4_valid; |
| 321 | } |
| 322 | |
Venkata Sharath Chandra Manchala | 96ed623 | 2019-09-21 12:11:19 -0700 | [diff] [blame] | 323 | /** |
| 324 | * hal_rx_mpdu_start_sw_peer_id_get_8074v2: Retrieve sw peer_id |
| 325 | * @buf: network buffer |
| 326 | * |
| 327 | * Return: sw peer_id |
| 328 | */ |
| 329 | static uint32_t hal_rx_mpdu_start_sw_peer_id_get_8074v2(uint8_t *buf) |
| 330 | { |
| 331 | struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; |
| 332 | struct rx_mpdu_start *mpdu_start = |
| 333 | &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; |
| 334 | |
| 335 | return HAL_RX_MPDU_INFO_SW_PEER_ID_GET( |
| 336 | &mpdu_start->rx_mpdu_info_details); |
| 337 | } |
| 338 | |
Venkata Sharath Chandra Manchala | e7924fd | 2019-09-21 12:44:52 -0700 | [diff] [blame] | 339 | /* |
| 340 | * hal_rx_mpdu_get_to_ds_8074v2(): API to get the tods info |
| 341 | * from rx_mpdu_start |
| 342 | * |
| 343 | * @buf: pointer to the start of RX PKT TLV header |
| 344 | * Return: uint32_t(to_ds) |
| 345 | */ |
| 346 | static uint32_t hal_rx_mpdu_get_to_ds_8074v2(uint8_t *buf) |
| 347 | { |
| 348 | struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; |
| 349 | struct rx_mpdu_start *mpdu_start = |
| 350 | &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; |
| 351 | |
| 352 | struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; |
| 353 | |
| 354 | return HAL_RX_MPDU_GET_TODS(mpdu_info); |
| 355 | } |
Venkata Sharath Chandra Manchala | 1e3a479 | 2019-09-21 13:15:09 -0700 | [diff] [blame] | 356 | |
| 357 | /* |
| 358 | * hal_rx_mpdu_get_fr_ds_8074v2(): API to get the from ds info |
| 359 | * from rx_mpdu_start |
| 360 | * |
| 361 | * @buf: pointer to the start of RX PKT TLV header |
| 362 | * Return: uint32_t(fr_ds) |
| 363 | */ |
| 364 | static uint32_t hal_rx_mpdu_get_fr_ds_8074v2(uint8_t *buf) |
| 365 | { |
| 366 | struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; |
| 367 | struct rx_mpdu_start *mpdu_start = |
| 368 | &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; |
| 369 | |
| 370 | struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; |
| 371 | |
| 372 | return HAL_RX_MPDU_GET_FROMDS(mpdu_info); |
| 373 | } |
Venkata Sharath Chandra Manchala | 25ba7b8 | 2019-09-21 13:31:30 -0700 | [diff] [blame] | 374 | |
| 375 | /* |
| 376 | * hal_rx_get_mpdu_frame_control_valid_8074v2(): Retrieves mpdu |
| 377 | * frame control valid |
| 378 | * |
| 379 | * @nbuf: Network buffer |
| 380 | * Returns: value of frame control valid field |
| 381 | */ |
| 382 | static uint8_t hal_rx_get_mpdu_frame_control_valid_8074v2(uint8_t *buf) |
| 383 | { |
| 384 | struct rx_pkt_tlvs *pkt_tlvs = hal_rx_get_pkt_tlvs(buf); |
| 385 | struct rx_mpdu_info *rx_mpdu_info = hal_rx_get_mpdu_info(pkt_tlvs); |
| 386 | |
| 387 | return HAL_RX_MPDU_GET_FRAME_CONTROL_VALID(rx_mpdu_info); |
| 388 | } |
Venkata Sharath Chandra Manchala | e3ae319 | 2019-09-21 13:59:46 -0700 | [diff] [blame] | 389 | |
| 390 | /* |
| 391 | * hal_rx_mpdu_get_addr1_8074v2(): API to check get address1 of the mpdu |
| 392 | * |
| 393 | * @buf: pointer to the start of RX PKT TLV headera |
| 394 | * @mac_addr: pointer to mac address |
| 395 | * Return: success/failure |
| 396 | */ |
| 397 | static QDF_STATUS hal_rx_mpdu_get_addr1_8074v2(uint8_t *buf, uint8_t *mac_addr) |
| 398 | { |
| 399 | struct __attribute__((__packed__)) hal_addr1 { |
| 400 | uint32_t ad1_31_0; |
| 401 | uint16_t ad1_47_32; |
| 402 | }; |
| 403 | |
| 404 | struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; |
| 405 | struct rx_mpdu_start *mpdu_start = |
| 406 | &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; |
| 407 | |
| 408 | struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; |
| 409 | struct hal_addr1 *addr = (struct hal_addr1 *)mac_addr; |
| 410 | uint32_t mac_addr_ad1_valid; |
| 411 | |
| 412 | mac_addr_ad1_valid = HAL_RX_MPDU_MAC_ADDR_AD1_VALID_GET(mpdu_info); |
| 413 | |
| 414 | if (mac_addr_ad1_valid) { |
| 415 | addr->ad1_31_0 = HAL_RX_MPDU_AD1_31_0_GET(mpdu_info); |
| 416 | addr->ad1_47_32 = HAL_RX_MPDU_AD1_47_32_GET(mpdu_info); |
| 417 | return QDF_STATUS_SUCCESS; |
| 418 | } |
| 419 | |
| 420 | return QDF_STATUS_E_FAILURE; |
| 421 | } |
| 422 | |
Venkata Sharath Chandra Manchala | a81a2fe | 2019-09-21 14:29:40 -0700 | [diff] [blame] | 423 | /* |
| 424 | * hal_rx_mpdu_get_addr2_8074v2(): API to check get address2 of the mpdu |
| 425 | * in the packet |
| 426 | * |
| 427 | * @buf: pointer to the start of RX PKT TLV header |
| 428 | * @mac_addr: pointer to mac address |
| 429 | * Return: success/failure |
| 430 | */ |
| 431 | static QDF_STATUS hal_rx_mpdu_get_addr2_8074v2(uint8_t *buf, uint8_t *mac_addr) |
| 432 | { |
| 433 | struct __attribute__((__packed__)) hal_addr2 { |
| 434 | uint16_t ad2_15_0; |
| 435 | uint32_t ad2_47_16; |
| 436 | }; |
| 437 | |
| 438 | struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; |
| 439 | struct rx_mpdu_start *mpdu_start = |
| 440 | &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; |
| 441 | |
| 442 | struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; |
| 443 | struct hal_addr2 *addr = (struct hal_addr2 *)mac_addr; |
| 444 | uint32_t mac_addr_ad2_valid; |
| 445 | |
| 446 | mac_addr_ad2_valid = HAL_RX_MPDU_MAC_ADDR_AD2_VALID_GET(mpdu_info); |
| 447 | |
| 448 | if (mac_addr_ad2_valid) { |
| 449 | addr->ad2_15_0 = HAL_RX_MPDU_AD2_15_0_GET(mpdu_info); |
| 450 | addr->ad2_47_16 = HAL_RX_MPDU_AD2_47_16_GET(mpdu_info); |
| 451 | return QDF_STATUS_SUCCESS; |
| 452 | } |
| 453 | |
| 454 | return QDF_STATUS_E_FAILURE; |
| 455 | } |
Venkata Sharath Chandra Manchala | 7c86825 | 2019-09-21 14:58:34 -0700 | [diff] [blame] | 456 | |
| 457 | /* |
| 458 | * hal_rx_mpdu_get_addr3_8074v2(): API to get address3 of the mpdu |
| 459 | * in the packet |
| 460 | * |
| 461 | * @buf: pointer to the start of RX PKT TLV header |
| 462 | * @mac_addr: pointer to mac address |
| 463 | * Return: success/failure |
| 464 | */ |
| 465 | static QDF_STATUS hal_rx_mpdu_get_addr3_8074v2(uint8_t *buf, uint8_t *mac_addr) |
| 466 | { |
| 467 | struct __attribute__((__packed__)) hal_addr3 { |
| 468 | uint32_t ad3_31_0; |
| 469 | uint16_t ad3_47_32; |
| 470 | }; |
| 471 | |
| 472 | struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; |
| 473 | struct rx_mpdu_start *mpdu_start = |
| 474 | &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; |
| 475 | |
| 476 | struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; |
| 477 | struct hal_addr3 *addr = (struct hal_addr3 *)mac_addr; |
| 478 | uint32_t mac_addr_ad3_valid; |
| 479 | |
| 480 | mac_addr_ad3_valid = HAL_RX_MPDU_MAC_ADDR_AD3_VALID_GET(mpdu_info); |
| 481 | |
| 482 | if (mac_addr_ad3_valid) { |
| 483 | addr->ad3_31_0 = HAL_RX_MPDU_AD3_31_0_GET(mpdu_info); |
| 484 | addr->ad3_47_32 = HAL_RX_MPDU_AD3_47_32_GET(mpdu_info); |
| 485 | return QDF_STATUS_SUCCESS; |
| 486 | } |
| 487 | |
| 488 | return QDF_STATUS_E_FAILURE; |
| 489 | } |
| 490 | |
Venkata Sharath Chandra Manchala | aa76283 | 2019-09-21 15:13:47 -0700 | [diff] [blame] | 491 | /* |
| 492 | * hal_rx_mpdu_get_addr4_8074v2(): API to get address4 of the mpdu |
| 493 | * in the packet |
| 494 | * |
| 495 | * @buf: pointer to the start of RX PKT TLV header |
| 496 | * @mac_addr: pointer to mac address |
| 497 | * Return: success/failure |
| 498 | */ |
| 499 | static QDF_STATUS hal_rx_mpdu_get_addr4_8074v2(uint8_t *buf, uint8_t *mac_addr) |
| 500 | { |
| 501 | struct __attribute__((__packed__)) hal_addr4 { |
| 502 | uint32_t ad4_31_0; |
| 503 | uint16_t ad4_47_32; |
| 504 | }; |
| 505 | |
| 506 | struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; |
| 507 | struct rx_mpdu_start *mpdu_start = |
| 508 | &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; |
| 509 | |
| 510 | struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; |
| 511 | struct hal_addr4 *addr = (struct hal_addr4 *)mac_addr; |
| 512 | uint32_t mac_addr_ad4_valid; |
| 513 | |
| 514 | mac_addr_ad4_valid = HAL_RX_MPDU_MAC_ADDR_AD4_VALID_GET(mpdu_info); |
| 515 | |
| 516 | if (mac_addr_ad4_valid) { |
| 517 | addr->ad4_31_0 = HAL_RX_MPDU_AD4_31_0_GET(mpdu_info); |
| 518 | addr->ad4_47_32 = HAL_RX_MPDU_AD4_47_32_GET(mpdu_info); |
| 519 | return QDF_STATUS_SUCCESS; |
| 520 | } |
| 521 | |
| 522 | return QDF_STATUS_E_FAILURE; |
| 523 | } |
| 524 | |
Venkata Sharath Chandra Manchala | 68d6f0d | 2019-09-21 15:33:47 -0700 | [diff] [blame] | 525 | /* |
| 526 | * hal_rx_get_mpdu_sequence_control_valid_8074v2(): Get mpdu |
| 527 | * sequence control valid |
| 528 | * |
| 529 | * @nbuf: Network buffer |
| 530 | * Returns: value of sequence control valid field |
| 531 | */ |
| 532 | static uint8_t hal_rx_get_mpdu_sequence_control_valid_8074v2(uint8_t *buf) |
| 533 | { |
| 534 | struct rx_pkt_tlvs *pkt_tlvs = hal_rx_get_pkt_tlvs(buf); |
| 535 | struct rx_mpdu_info *rx_mpdu_info = hal_rx_get_mpdu_info(pkt_tlvs); |
| 536 | |
| 537 | return HAL_RX_MPDU_GET_SEQUENCE_CONTROL_VALID(rx_mpdu_info); |
| 538 | } |
Venkata Sharath Chandra Manchala | 5ddc518 | 2019-09-21 15:53:03 -0700 | [diff] [blame] | 539 | |
| 540 | /** |
| 541 | * hal_rx_is_unicast_8074v2: check packet is unicast frame or not. |
| 542 | * |
| 543 | * @ buf: pointer to rx pkt TLV. |
| 544 | * |
| 545 | * Return: true on unicast. |
| 546 | */ |
| 547 | static bool hal_rx_is_unicast_8074v2(uint8_t *buf) |
| 548 | { |
| 549 | struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; |
| 550 | struct rx_mpdu_start *mpdu_start = |
| 551 | &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; |
| 552 | uint32_t grp_id; |
| 553 | uint8_t *rx_mpdu_info = (uint8_t *)&mpdu_start->rx_mpdu_info_details; |
| 554 | |
| 555 | grp_id = (_HAL_MS((*_OFFSET_TO_WORD_PTR((rx_mpdu_info), |
| 556 | RX_MPDU_INFO_0_SW_FRAME_GROUP_ID_OFFSET)), |
| 557 | RX_MPDU_INFO_0_SW_FRAME_GROUP_ID_MASK, |
| 558 | RX_MPDU_INFO_0_SW_FRAME_GROUP_ID_LSB)); |
| 559 | |
| 560 | return (HAL_MPDU_SW_FRAME_GROUP_UNICAST_DATA == grp_id) ? true : false; |
| 561 | } |
Venkata Sharath Chandra Manchala | 8513048 | 2019-09-21 16:17:01 -0700 | [diff] [blame] | 562 | |
| 563 | /** |
| 564 | * hal_rx_tid_get_8074v2: get tid based on qos control valid. |
| 565 | * @hal_soc_hdl: hal soc handle |
| 566 | * @buf: pointer to rx pkt TLV. |
| 567 | * |
| 568 | * Return: tid |
| 569 | */ |
| 570 | static uint32_t hal_rx_tid_get_8074v2(hal_soc_handle_t hal_soc_hdl, |
| 571 | uint8_t *buf) |
| 572 | { |
| 573 | struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; |
| 574 | struct rx_mpdu_start *mpdu_start = |
| 575 | &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; |
| 576 | uint8_t *rx_mpdu_info = (uint8_t *)&mpdu_start->rx_mpdu_info_details; |
| 577 | uint8_t qos_control_valid = |
| 578 | (_HAL_MS((*_OFFSET_TO_WORD_PTR((rx_mpdu_info), |
| 579 | RX_MPDU_INFO_2_MPDU_QOS_CONTROL_VALID_OFFSET)), |
| 580 | RX_MPDU_INFO_2_MPDU_QOS_CONTROL_VALID_MASK, |
| 581 | RX_MPDU_INFO_2_MPDU_QOS_CONTROL_VALID_LSB)); |
| 582 | |
| 583 | if (qos_control_valid) |
| 584 | return hal_rx_mpdu_start_tid_get_8074v2(buf); |
| 585 | |
| 586 | return HAL_RX_NON_QOS_TID; |
| 587 | } |
Venkata Sharath Chandra Manchala | 84d5092 | 2019-09-21 16:48:04 -0700 | [diff] [blame] | 588 | |
| 589 | /** |
| 590 | * hal_rx_hw_desc_get_ppduid_get_8074v2(): retrieve ppdu id |
| 591 | * @hw_desc_addr: hw addr |
| 592 | * |
| 593 | * Return: ppdu id |
| 594 | */ |
| 595 | static uint32_t hal_rx_hw_desc_get_ppduid_get_8074v2(void *hw_desc_addr) |
| 596 | { |
| 597 | struct rx_mpdu_info *rx_mpdu_info; |
| 598 | struct rx_pkt_tlvs *rx_desc = (struct rx_pkt_tlvs *)hw_desc_addr; |
| 599 | |
| 600 | rx_mpdu_info = |
| 601 | &rx_desc->mpdu_start_tlv.rx_mpdu_start.rx_mpdu_info_details; |
| 602 | |
| 603 | return HAL_RX_GET(rx_mpdu_info, RX_MPDU_INFO_0, PHY_PPDU_ID); |
| 604 | } |
Venkata Sharath Chandra Manchala | 25d7dbc | 2019-09-21 17:56:41 -0700 | [diff] [blame] | 605 | |
| 606 | /** |
| 607 | * hal_reo_status_get_header_8074v2 - Process reo desc info |
| 608 | * @d - Pointer to reo descriptior |
| 609 | * @b - tlv type info |
| 610 | * @h1 - Pointer to hal_reo_status_header where info to be stored |
| 611 | * |
| 612 | * Return - none. |
| 613 | * |
| 614 | */ |
| 615 | static void hal_reo_status_get_header_8074v2(uint32_t *d, int b, void *h1) |
| 616 | { |
| 617 | uint32_t val1 = 0; |
| 618 | struct hal_reo_status_header *h = |
| 619 | (struct hal_reo_status_header *)h1; |
| 620 | |
| 621 | switch (b) { |
| 622 | case HAL_REO_QUEUE_STATS_STATUS_TLV: |
| 623 | val1 = d[HAL_OFFSET_DW(REO_GET_QUEUE_STATS_STATUS_0, |
| 624 | UNIFORM_REO_STATUS_HEADER_STATUS_HEADER)]; |
| 625 | break; |
| 626 | case HAL_REO_FLUSH_QUEUE_STATUS_TLV: |
| 627 | val1 = d[HAL_OFFSET_DW(REO_FLUSH_QUEUE_STATUS_0, |
| 628 | UNIFORM_REO_STATUS_HEADER_STATUS_HEADER)]; |
| 629 | break; |
| 630 | case HAL_REO_FLUSH_CACHE_STATUS_TLV: |
| 631 | val1 = d[HAL_OFFSET_DW(REO_FLUSH_CACHE_STATUS_0, |
| 632 | UNIFORM_REO_STATUS_HEADER_STATUS_HEADER)]; |
| 633 | break; |
| 634 | case HAL_REO_UNBLK_CACHE_STATUS_TLV: |
| 635 | val1 = d[HAL_OFFSET_DW(REO_UNBLOCK_CACHE_STATUS_0, |
| 636 | UNIFORM_REO_STATUS_HEADER_STATUS_HEADER)]; |
| 637 | break; |
| 638 | case HAL_REO_TIMOUT_LIST_STATUS_TLV: |
| 639 | val1 = d[HAL_OFFSET_DW(REO_FLUSH_TIMEOUT_LIST_STATUS_0, |
| 640 | UNIFORM_REO_STATUS_HEADER_STATUS_HEADER)]; |
| 641 | break; |
| 642 | case HAL_REO_DESC_THRES_STATUS_TLV: |
| 643 | val1 = |
| 644 | d[HAL_OFFSET_DW(REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_0, |
| 645 | UNIFORM_REO_STATUS_HEADER_STATUS_HEADER)]; |
| 646 | break; |
| 647 | case HAL_REO_UPDATE_RX_QUEUE_STATUS_TLV: |
| 648 | val1 = d[HAL_OFFSET_DW(REO_UPDATE_RX_REO_QUEUE_STATUS_0, |
| 649 | UNIFORM_REO_STATUS_HEADER_STATUS_HEADER)]; |
| 650 | break; |
| 651 | default: |
| 652 | qdf_nofl_err("ERROR: Unknown tlv\n"); |
| 653 | break; |
| 654 | } |
| 655 | h->cmd_num = |
| 656 | HAL_GET_FIELD( |
| 657 | UNIFORM_REO_STATUS_HEADER_0, REO_STATUS_NUMBER, |
| 658 | val1); |
| 659 | h->exec_time = |
| 660 | HAL_GET_FIELD(UNIFORM_REO_STATUS_HEADER_0, |
| 661 | CMD_EXECUTION_TIME, val1); |
| 662 | h->status = |
| 663 | HAL_GET_FIELD(UNIFORM_REO_STATUS_HEADER_0, |
| 664 | REO_CMD_EXECUTION_STATUS, val1); |
| 665 | switch (b) { |
| 666 | case HAL_REO_QUEUE_STATS_STATUS_TLV: |
| 667 | val1 = d[HAL_OFFSET_DW(REO_GET_QUEUE_STATS_STATUS_1, |
| 668 | UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC)]; |
| 669 | break; |
| 670 | case HAL_REO_FLUSH_QUEUE_STATUS_TLV: |
| 671 | val1 = d[HAL_OFFSET_DW(REO_FLUSH_QUEUE_STATUS_1, |
| 672 | UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC)]; |
| 673 | break; |
| 674 | case HAL_REO_FLUSH_CACHE_STATUS_TLV: |
| 675 | val1 = d[HAL_OFFSET_DW(REO_FLUSH_CACHE_STATUS_1, |
| 676 | UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC)]; |
| 677 | break; |
| 678 | case HAL_REO_UNBLK_CACHE_STATUS_TLV: |
| 679 | val1 = d[HAL_OFFSET_DW(REO_UNBLOCK_CACHE_STATUS_1, |
| 680 | UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC)]; |
| 681 | break; |
| 682 | case HAL_REO_TIMOUT_LIST_STATUS_TLV: |
| 683 | val1 = d[HAL_OFFSET_DW(REO_FLUSH_TIMEOUT_LIST_STATUS_1, |
| 684 | UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC)]; |
| 685 | break; |
| 686 | case HAL_REO_DESC_THRES_STATUS_TLV: |
| 687 | val1 = |
| 688 | d[HAL_OFFSET_DW(REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_1, |
| 689 | UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC)]; |
| 690 | break; |
| 691 | case HAL_REO_UPDATE_RX_QUEUE_STATUS_TLV: |
| 692 | val1 = d[HAL_OFFSET_DW(REO_UPDATE_RX_REO_QUEUE_STATUS_1, |
| 693 | UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC)]; |
| 694 | break; |
| 695 | default: |
| 696 | qdf_nofl_err("ERROR: Unknown tlv\n"); |
| 697 | break; |
| 698 | } |
| 699 | h->tstamp = |
| 700 | HAL_GET_FIELD(UNIFORM_REO_STATUS_HEADER_1, TIMESTAMP, val1); |
| 701 | } |
Venkata Sharath Chandra Manchala | 56022cb | 2019-09-21 18:17:21 -0700 | [diff] [blame] | 702 | |
| 703 | /** |
| 704 | * hal_rx_mpdu_start_mpdu_qos_control_valid_get_8074v2(): |
| 705 | * Retrieve qos control valid bit from the tlv. |
| 706 | * @buf: pointer to rx pkt TLV. |
| 707 | * |
| 708 | * Return: qos control value. |
| 709 | */ |
| 710 | static inline uint32_t |
| 711 | hal_rx_mpdu_start_mpdu_qos_control_valid_get_8074v2(uint8_t *buf) |
| 712 | { |
| 713 | struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; |
| 714 | struct rx_mpdu_start *mpdu_start = |
| 715 | &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; |
| 716 | |
| 717 | return HAL_RX_MPDU_INFO_QOS_CONTROL_VALID_GET( |
| 718 | &mpdu_start->rx_mpdu_info_details); |
| 719 | } |
| 720 | |
Venkata Sharath Chandra Manchala | 685045e | 2019-09-21 18:32:51 -0700 | [diff] [blame] | 721 | /** |
| 722 | * hal_rx_msdu_end_sa_sw_peer_id_get_8074v2(): API to get the |
| 723 | * sa_sw_peer_id from rx_msdu_end TLV |
| 724 | * @buf: pointer to the start of RX PKT TLV headers |
| 725 | * |
| 726 | * Return: sa_sw_peer_id index |
| 727 | */ |
| 728 | static inline uint32_t |
| 729 | hal_rx_msdu_end_sa_sw_peer_id_get_8074v2(uint8_t *buf) |
| 730 | { |
| 731 | struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; |
| 732 | struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; |
| 733 | |
| 734 | return HAL_RX_MSDU_END_SA_SW_PEER_ID_GET(msdu_end); |
| 735 | } |
| 736 | |
Venkata Sharath Chandra Manchala | 38e84d2 | 2019-09-21 18:59:21 -0700 | [diff] [blame] | 737 | /** |
| 738 | * hal_tx_desc_set_mesh_en_8074v2 - Set mesh_enable flag in Tx descriptor |
| 739 | * @desc: Handle to Tx Descriptor |
| 740 | * @en: For raw WiFi frames, this indicates transmission to a mesh STA, |
| 741 | * enabling the interpretation of the 'Mesh Control Present' bit |
| 742 | * (bit 8) of QoS Control (otherwise this bit is ignored), |
| 743 | * For native WiFi frames, this indicates that a 'Mesh Control' field |
| 744 | * is present between the header and the LLC. |
| 745 | * |
| 746 | * Return: void |
| 747 | */ |
| 748 | static inline |
| 749 | void hal_tx_desc_set_mesh_en_8074v2(void *desc, uint8_t en) |
| 750 | { |
| 751 | HAL_SET_FLD(desc, TCL_DATA_CMD_4, MESH_ENABLE) |= |
| 752 | HAL_TX_SM(TCL_DATA_CMD_4, MESH_ENABLE, en); |
| 753 | } |
| 754 | |
Venkata Sharath Chandra Manchala | 8227240 | 2019-09-23 14:16:41 -0700 | [diff] [blame] | 755 | static |
| 756 | void *hal_rx_msdu0_buffer_addr_lsb_8074v2(void *link_desc_va) |
| 757 | { |
| 758 | return (void *)HAL_RX_MSDU0_BUFFER_ADDR_LSB(link_desc_va); |
| 759 | } |
| 760 | |
| 761 | static |
| 762 | void *hal_rx_msdu_desc_info_ptr_get_8074v2(void *msdu0) |
| 763 | { |
| 764 | return (void *)HAL_RX_MSDU_DESC_INFO_PTR_GET(msdu0); |
| 765 | } |
| 766 | |
| 767 | static |
| 768 | void *hal_ent_mpdu_desc_info_8074v2(void *ent_ring_desc) |
| 769 | { |
| 770 | return (void *)HAL_ENT_MPDU_DESC_INFO(ent_ring_desc); |
| 771 | } |
| 772 | |
| 773 | static |
| 774 | void *hal_dst_mpdu_desc_info_8074v2(void *dst_ring_desc) |
| 775 | { |
| 776 | return (void *)HAL_DST_MPDU_DESC_INFO(dst_ring_desc); |
| 777 | } |
| 778 | |
Venkata Sharath Chandra Manchala | b7d2df1 | 2019-09-23 15:20:06 -0700 | [diff] [blame] | 779 | static |
| 780 | uint8_t hal_rx_get_fc_valid_8074v2(uint8_t *buf) |
| 781 | { |
| 782 | return HAL_RX_GET_FC_VALID(buf); |
| 783 | } |
| 784 | |
| 785 | static uint8_t hal_rx_get_to_ds_flag_8074v2(uint8_t *buf) |
| 786 | { |
| 787 | return HAL_RX_GET_TO_DS_FLAG(buf); |
| 788 | } |
| 789 | |
| 790 | static uint8_t hal_rx_get_mac_addr2_valid_8074v2(uint8_t *buf) |
| 791 | { |
| 792 | return HAL_RX_GET_MAC_ADDR2_VALID(buf); |
| 793 | } |
| 794 | |
| 795 | static uint8_t hal_rx_get_filter_category_8074v2(uint8_t *buf) |
| 796 | { |
| 797 | return HAL_RX_GET_FILTER_CATEGORY(buf); |
| 798 | } |
| 799 | |
| 800 | static uint32_t |
| 801 | hal_rx_get_ppdu_id_8074v2(uint8_t *buf) |
| 802 | { |
| 803 | return HAL_RX_GET_PPDU_ID(buf); |
| 804 | } |
| 805 | |
Venkata Sharath Chandra Manchala | 222b253 | 2019-09-23 17:16:51 -0700 | [diff] [blame] | 806 | /** |
| 807 | * hal_reo_config_8074v2(): Set reo config parameters |
| 808 | * @soc: hal soc handle |
| 809 | * @reg_val: value to be set |
| 810 | * @reo_params: reo parameters |
| 811 | * |
| 812 | * Return: void |
| 813 | */ |
| 814 | static void |
| 815 | hal_reo_config_8074v2(struct hal_soc *soc, |
| 816 | uint32_t reg_val, |
| 817 | struct hal_reo_params *reo_params) |
| 818 | { |
| 819 | HAL_REO_R0_CONFIG(soc, reg_val, reo_params); |
| 820 | } |
| 821 | |
| 822 | /** |
| 823 | * hal_rx_msdu_desc_info_get_ptr_8074v2() - Get msdu desc info ptr |
| 824 | * @msdu_details_ptr - Pointer to msdu_details_ptr |
| 825 | * |
| 826 | * Return - Pointer to rx_msdu_desc_info structure. |
| 827 | * |
| 828 | */ |
| 829 | static void *hal_rx_msdu_desc_info_get_ptr_8074v2(void *msdu_details_ptr) |
| 830 | { |
| 831 | return HAL_RX_MSDU_DESC_INFO_GET(msdu_details_ptr); |
| 832 | } |
| 833 | |
| 834 | /** |
| 835 | * hal_rx_link_desc_msdu0_ptr_8074v2 - Get pointer to rx_msdu details |
| 836 | * @link_desc - Pointer to link desc |
| 837 | * |
| 838 | * Return - Pointer to rx_msdu_details structure |
| 839 | * |
| 840 | */ |
| 841 | static void *hal_rx_link_desc_msdu0_ptr_8074v2(void *link_desc) |
| 842 | { |
| 843 | return HAL_RX_LINK_DESC_MSDU0_PTR(link_desc); |
| 844 | } |
| 845 | |
Venkata Sharath Chandra Manchala | c9a4e14 | 2019-09-25 11:20:23 -0700 | [diff] [blame] | 846 | /** |
| 847 | * hal_rx_msdu_flow_idx_get_8074v2: API to get flow index |
| 848 | * from rx_msdu_end TLV |
| 849 | * @buf: pointer to the start of RX PKT TLV headers |
| 850 | * |
| 851 | * Return: flow index value from MSDU END TLV |
| 852 | */ |
| 853 | static inline uint32_t hal_rx_msdu_flow_idx_get_8074v2(uint8_t *buf) |
| 854 | { |
| 855 | struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; |
| 856 | struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; |
| 857 | |
| 858 | return HAL_RX_MSDU_END_FLOW_IDX_GET(msdu_end); |
| 859 | } |
| 860 | |
Venkata Sharath Chandra Manchala | b9a8536 | 2019-09-25 11:42:07 -0700 | [diff] [blame] | 861 | /** |
| 862 | * hal_rx_msdu_flow_idx_invalid_8074v2: API to get flow index invalid |
| 863 | * from rx_msdu_end TLV |
| 864 | * @buf: pointer to the start of RX PKT TLV headers |
| 865 | * |
| 866 | * Return: flow index invalid value from MSDU END TLV |
| 867 | */ |
| 868 | static bool hal_rx_msdu_flow_idx_invalid_8074v2(uint8_t *buf) |
| 869 | { |
| 870 | struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; |
| 871 | struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; |
| 872 | |
| 873 | return HAL_RX_MSDU_END_FLOW_IDX_INVALID_GET(msdu_end); |
| 874 | } |
| 875 | |
Venkata Sharath Chandra Manchala | b5ec9d2 | 2019-09-25 12:07:09 -0700 | [diff] [blame] | 876 | /** |
| 877 | * hal_rx_msdu_flow_idx_timeout_8074v2: API to get flow index timeout |
| 878 | * from rx_msdu_end TLV |
| 879 | * @buf: pointer to the start of RX PKT TLV headers |
| 880 | * |
| 881 | * Return: flow index timeout value from MSDU END TLV |
| 882 | */ |
| 883 | static bool hal_rx_msdu_flow_idx_timeout_8074v2(uint8_t *buf) |
| 884 | { |
| 885 | struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; |
| 886 | struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; |
| 887 | |
| 888 | return HAL_RX_MSDU_END_FLOW_IDX_TIMEOUT_GET(msdu_end); |
| 889 | } |
| 890 | |
Venkata Sharath Chandra Manchala | 905312e | 2019-09-25 12:30:34 -0700 | [diff] [blame] | 891 | /** |
| 892 | * hal_rx_msdu_fse_metadata_get_8074v2: API to get FSE metadata |
| 893 | * from rx_msdu_end TLV |
| 894 | * @buf: pointer to the start of RX PKT TLV headers |
| 895 | * |
| 896 | * Return: fse metadata value from MSDU END TLV |
| 897 | */ |
| 898 | static uint32_t hal_rx_msdu_fse_metadata_get_8074v2(uint8_t *buf) |
| 899 | { |
| 900 | struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; |
| 901 | struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; |
| 902 | |
| 903 | return HAL_RX_MSDU_END_FSE_METADATA_GET(msdu_end); |
| 904 | } |
| 905 | |
Venkata Sharath Chandra Manchala | 8fc894a | 2019-09-25 12:50:14 -0700 | [diff] [blame] | 906 | /** |
| 907 | * hal_rx_msdu_cce_metadata_get_8074v2: API to get CCE metadata |
| 908 | * from rx_msdu_end TLV |
| 909 | * @buf: pointer to the start of RX PKT TLV headers |
| 910 | * |
| 911 | * Return: cce_metadata |
| 912 | */ |
| 913 | static uint16_t |
| 914 | hal_rx_msdu_cce_metadata_get_8074v2(uint8_t *buf) |
| 915 | { |
| 916 | struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; |
| 917 | struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; |
| 918 | |
| 919 | return HAL_RX_MSDU_END_CCE_METADATA_GET(msdu_end); |
| 920 | } |
| 921 | |
Venkata Sharath Chandra Manchala | 1059fae | 2019-09-25 13:00:36 -0700 | [diff] [blame] | 922 | /** |
| 923 | * hal_rx_msdu_get_flow_params_8074v2: API to get flow index, flow index invalid |
| 924 | * and flow index timeout from rx_msdu_end TLV |
| 925 | * @buf: pointer to the start of RX PKT TLV headers |
| 926 | * @flow_invalid: pointer to return value of flow_idx_valid |
| 927 | * @flow_timeout: pointer to return value of flow_idx_timeout |
| 928 | * @flow_index: pointer to return value of flow_idx |
| 929 | * |
| 930 | * Return: none |
| 931 | */ |
| 932 | static inline void |
| 933 | hal_rx_msdu_get_flow_params_8074v2(uint8_t *buf, |
| 934 | bool *flow_invalid, |
| 935 | bool *flow_timeout, |
| 936 | uint32_t *flow_index) |
| 937 | { |
| 938 | struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; |
| 939 | struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; |
| 940 | |
| 941 | *flow_invalid = HAL_RX_MSDU_END_FLOW_IDX_INVALID_GET(msdu_end); |
| 942 | *flow_timeout = HAL_RX_MSDU_END_FLOW_IDX_TIMEOUT_GET(msdu_end); |
| 943 | *flow_index = HAL_RX_MSDU_END_FLOW_IDX_GET(msdu_end); |
| 944 | } |
| 945 | |
Venkata Sharath Chandra Manchala | 5c5d409 | 2019-09-25 13:31:51 -0700 | [diff] [blame] | 946 | /** |
| 947 | * hal_rx_tlv_get_tcp_chksum_8074v2() - API to get tcp checksum |
| 948 | * @buf: rx_tlv_hdr |
| 949 | * |
| 950 | * Return: tcp checksum |
| 951 | */ |
| 952 | static uint16_t |
| 953 | hal_rx_tlv_get_tcp_chksum_8074v2(uint8_t *buf) |
| 954 | { |
| 955 | return HAL_RX_TLV_GET_TCP_CHKSUM(buf); |
| 956 | } |
| 957 | |
Venkata Sharath Chandra Manchala | 36fd40a | 2019-09-25 19:00:14 -0700 | [diff] [blame] | 958 | /** |
| 959 | * hal_rx_get_rx_sequence_8074v2(): Function to retrieve rx sequence number |
| 960 | * |
| 961 | * @nbuf: Network buffer |
| 962 | * Returns: rx sequence number |
| 963 | */ |
| 964 | static |
| 965 | uint16_t hal_rx_get_rx_sequence_8074v2(uint8_t *buf) |
| 966 | { |
| 967 | struct rx_pkt_tlvs *pkt_tlvs = hal_rx_get_pkt_tlvs(buf); |
| 968 | struct rx_mpdu_info *rx_mpdu_info = hal_rx_get_mpdu_info(pkt_tlvs); |
| 969 | |
| 970 | return HAL_RX_MPDU_GET_SEQUENCE_NUMBER(rx_mpdu_info); |
| 971 | } |
| 972 | |
Nandha Kishore Easwaran | bcf9535 | 2019-11-05 11:44:46 +0530 | [diff] [blame] | 973 | /** |
| 974 | * hal_get_window_address_8074v2(): Function to get hp/tp address |
| 975 | * @hal_soc: Pointer to hal_soc |
| 976 | * @addr: address offset of register |
| 977 | * |
| 978 | * Return: modified address offset of register |
| 979 | */ |
| 980 | static inline qdf_iomem_t hal_get_window_address_8074v2(struct hal_soc *hal_soc, |
| 981 | qdf_iomem_t addr) |
| 982 | { |
| 983 | return addr; |
| 984 | } |
| 985 | |
Balamurugan Mahalingam | 5d80641 | 2018-07-30 18:04:15 +0530 | [diff] [blame] | 986 | struct hal_hw_txrx_ops qca8074v2_hal_hw_txrx_ops = { |
| 987 | |
| 988 | /* init and setup */ |
| 989 | hal_srng_dst_hw_init_generic, |
| 990 | hal_srng_src_hw_init_generic, |
Venkata Sharath Chandra Manchala | 443b9b4 | 2018-10-10 12:04:54 -0700 | [diff] [blame] | 991 | hal_get_hw_hptp_generic, |
Balamurugan Mahalingam | 5d80641 | 2018-07-30 18:04:15 +0530 | [diff] [blame] | 992 | hal_reo_setup_generic, |
| 993 | hal_setup_link_idle_list_generic, |
Nandha Kishore Easwaran | bcf9535 | 2019-11-05 11:44:46 +0530 | [diff] [blame] | 994 | hal_get_window_address_8074v2, |
Balamurugan Mahalingam | 5d80641 | 2018-07-30 18:04:15 +0530 | [diff] [blame] | 995 | |
Balamurugan Mahalingam | d015964 | 2018-07-11 15:02:29 +0530 | [diff] [blame] | 996 | /* tx */ |
Balamurugan Mahalingam | 5d80641 | 2018-07-30 18:04:15 +0530 | [diff] [blame] | 997 | hal_tx_desc_set_dscp_tid_table_id_8074v2, |
| 998 | hal_tx_set_dscp_tid_map_8074v2, |
| 999 | hal_tx_update_dscp_tid_8074v2, |
| 1000 | hal_tx_desc_set_lmac_id_8074v2, |
| 1001 | hal_tx_desc_set_buf_addr_generic, |
Balamurugan Mahalingam | fa1d9c7 | 2018-09-25 12:13:34 +0530 | [diff] [blame] | 1002 | hal_tx_desc_set_search_type_generic, |
| 1003 | hal_tx_desc_set_search_index_generic, |
Subhranil Choudhury | 4ee1b5e | 2019-08-20 18:20:47 +0530 | [diff] [blame] | 1004 | hal_tx_desc_set_cache_set_num_generic, |
Balamurugan Mahalingam | 764219e | 2018-09-17 15:34:25 +0530 | [diff] [blame] | 1005 | hal_tx_comp_get_status_generic, |
| 1006 | hal_tx_comp_get_release_reason_generic, |
Tallapragada Kalyan | fa6f80f | 2019-12-12 19:38:16 +0530 | [diff] [blame] | 1007 | hal_get_wbm_internal_error_generic, |
Venkata Sharath Chandra Manchala | 38e84d2 | 2019-09-21 18:59:21 -0700 | [diff] [blame] | 1008 | hal_tx_desc_set_mesh_en_8074v2, |
Balamurugan Mahalingam | d015964 | 2018-07-11 15:02:29 +0530 | [diff] [blame] | 1009 | |
| 1010 | /* rx */ |
Balamurugan Mahalingam | 5d80641 | 2018-07-30 18:04:15 +0530 | [diff] [blame] | 1011 | hal_rx_msdu_start_nss_get_8074v2, |
| 1012 | hal_rx_mon_hw_desc_get_mpdu_status_8074v2, |
| 1013 | hal_rx_get_tlv_8074v2, |
| 1014 | hal_rx_proc_phyrx_other_receive_info_tlv_8074v2, |
| 1015 | hal_rx_dump_msdu_start_tlv_8074v2, |
| 1016 | hal_rx_dump_msdu_end_tlv_8074v2, |
| 1017 | hal_get_link_desc_size_8074v2, |
| 1018 | hal_rx_mpdu_start_tid_get_8074v2, |
| 1019 | hal_rx_msdu_start_reception_type_get_8074v2, |
| 1020 | hal_rx_msdu_end_da_idx_get_8074v2, |
Venkata Sharath Chandra Manchala | 222b253 | 2019-09-23 17:16:51 -0700 | [diff] [blame] | 1021 | hal_rx_msdu_desc_info_get_ptr_8074v2, |
| 1022 | hal_rx_link_desc_msdu0_ptr_8074v2, |
Venkata Sharath Chandra Manchala | 25d7dbc | 2019-09-21 17:56:41 -0700 | [diff] [blame] | 1023 | hal_reo_status_get_header_8074v2, |
Balamurugan Mahalingam | 5d80641 | 2018-07-30 18:04:15 +0530 | [diff] [blame] | 1024 | hal_rx_status_get_tlv_info_generic, |
Balamurugan Mahalingam | 764219e | 2018-09-17 15:34:25 +0530 | [diff] [blame] | 1025 | hal_rx_wbm_err_info_get_generic, |
| 1026 | hal_rx_dump_mpdu_start_tlv_generic, |
Debasis Das | c39a68d | 2019-01-28 17:02:06 +0530 | [diff] [blame] | 1027 | |
| 1028 | hal_tx_set_pcp_tid_map_generic, |
| 1029 | hal_tx_update_pcp_tid_generic, |
| 1030 | hal_tx_update_tidmap_prty_generic, |
Venkata Sharath Chandra Manchala | d1b7e4c | 2019-09-20 10:01:21 -0700 | [diff] [blame] | 1031 | hal_rx_get_rx_fragment_number_8074v2, |
Venkata Sharath Chandra Manchala | ee90938 | 2019-09-20 10:52:37 -0700 | [diff] [blame] | 1032 | hal_rx_msdu_end_da_is_mcbc_get_8074v2, |
Venkata Sharath Chandra Manchala | 59ebd5e | 2019-09-20 15:52:55 -0700 | [diff] [blame] | 1033 | hal_rx_msdu_end_sa_is_valid_get_8074v2, |
Venkata Sharath Chandra Manchala | 5bf1e5a | 2019-09-20 16:18:42 -0700 | [diff] [blame] | 1034 | hal_rx_msdu_end_sa_idx_get_8074v2, |
Venkata Sharath Chandra Manchala | 43d5632 | 2019-09-20 16:51:48 -0700 | [diff] [blame] | 1035 | hal_rx_desc_is_first_msdu_8074v2, |
Venkata Sharath Chandra Manchala | f05b2ae | 2019-09-20 17:25:21 -0700 | [diff] [blame] | 1036 | hal_rx_msdu_end_l3_hdr_padding_get_8074v2, |
Venkata Sharath Chandra Manchala | c1a4c8b | 2019-09-20 17:42:07 -0700 | [diff] [blame] | 1037 | hal_rx_encryption_info_valid_8074v2, |
Venkata Sharath Chandra Manchala | a2d7497 | 2019-09-20 18:02:57 -0700 | [diff] [blame] | 1038 | hal_rx_print_pn_8074v2, |
Venkata Sharath Chandra Manchala | cb255b4 | 2019-09-21 11:03:38 -0700 | [diff] [blame] | 1039 | hal_rx_msdu_end_first_msdu_get_8074v2, |
Venkata Sharath Chandra Manchala | 7905538 | 2019-09-21 11:22:30 -0700 | [diff] [blame] | 1040 | hal_rx_msdu_end_da_is_valid_get_8074v2, |
Venkata Sharath Chandra Manchala | 55f2d92 | 2019-09-21 11:37:01 -0700 | [diff] [blame] | 1041 | hal_rx_msdu_end_last_msdu_get_8074v2, |
Venkata Sharath Chandra Manchala | 2a52d34 | 2019-09-21 11:52:54 -0700 | [diff] [blame] | 1042 | hal_rx_get_mpdu_mac_ad4_valid_8074v2, |
Venkata Sharath Chandra Manchala | 96ed623 | 2019-09-21 12:11:19 -0700 | [diff] [blame] | 1043 | hal_rx_mpdu_start_sw_peer_id_get_8074v2, |
Venkata Sharath Chandra Manchala | e7924fd | 2019-09-21 12:44:52 -0700 | [diff] [blame] | 1044 | hal_rx_mpdu_get_to_ds_8074v2, |
Venkata Sharath Chandra Manchala | 1e3a479 | 2019-09-21 13:15:09 -0700 | [diff] [blame] | 1045 | hal_rx_mpdu_get_fr_ds_8074v2, |
Venkata Sharath Chandra Manchala | 25ba7b8 | 2019-09-21 13:31:30 -0700 | [diff] [blame] | 1046 | hal_rx_get_mpdu_frame_control_valid_8074v2, |
Venkata Sharath Chandra Manchala | e3ae319 | 2019-09-21 13:59:46 -0700 | [diff] [blame] | 1047 | hal_rx_mpdu_get_addr1_8074v2, |
Venkata Sharath Chandra Manchala | a81a2fe | 2019-09-21 14:29:40 -0700 | [diff] [blame] | 1048 | hal_rx_mpdu_get_addr2_8074v2, |
Venkata Sharath Chandra Manchala | 7c86825 | 2019-09-21 14:58:34 -0700 | [diff] [blame] | 1049 | hal_rx_mpdu_get_addr3_8074v2, |
Venkata Sharath Chandra Manchala | aa76283 | 2019-09-21 15:13:47 -0700 | [diff] [blame] | 1050 | hal_rx_mpdu_get_addr4_8074v2, |
Venkata Sharath Chandra Manchala | 68d6f0d | 2019-09-21 15:33:47 -0700 | [diff] [blame] | 1051 | hal_rx_get_mpdu_sequence_control_valid_8074v2, |
Venkata Sharath Chandra Manchala | 5ddc518 | 2019-09-21 15:53:03 -0700 | [diff] [blame] | 1052 | hal_rx_is_unicast_8074v2, |
Venkata Sharath Chandra Manchala | 8513048 | 2019-09-21 16:17:01 -0700 | [diff] [blame] | 1053 | hal_rx_tid_get_8074v2, |
Venkata Sharath Chandra Manchala | 84d5092 | 2019-09-21 16:48:04 -0700 | [diff] [blame] | 1054 | hal_rx_hw_desc_get_ppduid_get_8074v2, |
Venkata Sharath Chandra Manchala | 56022cb | 2019-09-21 18:17:21 -0700 | [diff] [blame] | 1055 | hal_rx_mpdu_start_mpdu_qos_control_valid_get_8074v2, |
Venkata Sharath Chandra Manchala | 685045e | 2019-09-21 18:32:51 -0700 | [diff] [blame] | 1056 | hal_rx_msdu_end_sa_sw_peer_id_get_8074v2, |
Venkata Sharath Chandra Manchala | 8227240 | 2019-09-23 14:16:41 -0700 | [diff] [blame] | 1057 | hal_rx_msdu0_buffer_addr_lsb_8074v2, |
| 1058 | hal_rx_msdu_desc_info_ptr_get_8074v2, |
| 1059 | hal_ent_mpdu_desc_info_8074v2, |
| 1060 | hal_dst_mpdu_desc_info_8074v2, |
Venkata Sharath Chandra Manchala | b7d2df1 | 2019-09-23 15:20:06 -0700 | [diff] [blame] | 1061 | hal_rx_get_fc_valid_8074v2, |
| 1062 | hal_rx_get_to_ds_flag_8074v2, |
| 1063 | hal_rx_get_mac_addr2_valid_8074v2, |
| 1064 | hal_rx_get_filter_category_8074v2, |
| 1065 | hal_rx_get_ppdu_id_8074v2, |
Venkata Sharath Chandra Manchala | 222b253 | 2019-09-23 17:16:51 -0700 | [diff] [blame] | 1066 | hal_reo_config_8074v2, |
Venkata Sharath Chandra Manchala | c9a4e14 | 2019-09-25 11:20:23 -0700 | [diff] [blame] | 1067 | hal_rx_msdu_flow_idx_get_8074v2, |
Venkata Sharath Chandra Manchala | b9a8536 | 2019-09-25 11:42:07 -0700 | [diff] [blame] | 1068 | hal_rx_msdu_flow_idx_invalid_8074v2, |
Venkata Sharath Chandra Manchala | b5ec9d2 | 2019-09-25 12:07:09 -0700 | [diff] [blame] | 1069 | hal_rx_msdu_flow_idx_timeout_8074v2, |
Venkata Sharath Chandra Manchala | 905312e | 2019-09-25 12:30:34 -0700 | [diff] [blame] | 1070 | hal_rx_msdu_fse_metadata_get_8074v2, |
Venkata Sharath Chandra Manchala | 8fc894a | 2019-09-25 12:50:14 -0700 | [diff] [blame] | 1071 | hal_rx_msdu_cce_metadata_get_8074v2, |
Venkata Sharath Chandra Manchala | 1059fae | 2019-09-25 13:00:36 -0700 | [diff] [blame] | 1072 | hal_rx_msdu_get_flow_params_8074v2, |
Venkata Sharath Chandra Manchala | 5c5d409 | 2019-09-25 13:31:51 -0700 | [diff] [blame] | 1073 | hal_rx_tlv_get_tcp_chksum_8074v2, |
Venkata Sharath Chandra Manchala | 36fd40a | 2019-09-25 19:00:14 -0700 | [diff] [blame] | 1074 | hal_rx_get_rx_sequence_8074v2, |
Padma Raghunathan | 5cd2e56 | 2019-12-18 21:32:58 +0530 | [diff] [blame] | 1075 | #if defined(QCA_WIFI_QCA6018) && defined(WLAN_CFR_ENABLE) && \ |
| 1076 | defined(WLAN_ENH_CFR_ENABLE) |
| 1077 | hal_rx_get_bb_info_8074v2, |
| 1078 | hal_rx_get_rtt_info_8074v2, |
| 1079 | #else |
| 1080 | NULL, |
| 1081 | NULL, |
| 1082 | #endif |
syed touqeer pasha | 6997a37 | 2019-12-31 15:45:55 +0530 | [diff] [blame] | 1083 | /* rx - msdu fast path info fields */ |
| 1084 | hal_rx_msdu_packet_metadata_get_generic, |
Venkata Sharath Chandra Manchala | d2ceaf4 | 2020-01-09 19:57:42 -0800 | [diff] [blame] | 1085 | NULL, |
| 1086 | NULL, |
| 1087 | NULL, |
| 1088 | NULL, |
| 1089 | NULL, |
| 1090 | NULL, |
Balamurugan Mahalingam | d015964 | 2018-07-11 15:02:29 +0530 | [diff] [blame] | 1091 | }; |
| 1092 | |
Balamurugan Mahalingam | 5d80641 | 2018-07-30 18:04:15 +0530 | [diff] [blame] | 1093 | struct hal_hw_srng_config hw_srng_table_8074v2[] = { |
Balamurugan Mahalingam | d015964 | 2018-07-11 15:02:29 +0530 | [diff] [blame] | 1094 | /* TODO: max_rings can populated by querying HW capabilities */ |
| 1095 | { /* REO_DST */ |
| 1096 | .start_ring_id = HAL_SRNG_REO2SW1, |
| 1097 | .max_rings = 4, |
| 1098 | .entry_size = sizeof(struct reo_destination_ring) >> 2, |
| 1099 | .lmac_ring = FALSE, |
| 1100 | .ring_dir = HAL_SRNG_DST_RING, |
| 1101 | .reg_start = { |
| 1102 | HWIO_REO_R0_REO2SW1_RING_BASE_LSB_ADDR( |
| 1103 | SEQ_WCSS_UMAC_REO_REG_OFFSET), |
| 1104 | HWIO_REO_R2_REO2SW1_RING_HP_ADDR( |
| 1105 | SEQ_WCSS_UMAC_REO_REG_OFFSET) |
| 1106 | }, |
| 1107 | .reg_size = { |
| 1108 | HWIO_REO_R0_REO2SW2_RING_BASE_LSB_ADDR(0) - |
| 1109 | HWIO_REO_R0_REO2SW1_RING_BASE_LSB_ADDR(0), |
| 1110 | HWIO_REO_R2_REO2SW2_RING_HP_ADDR(0) - |
| 1111 | HWIO_REO_R2_REO2SW1_RING_HP_ADDR(0), |
| 1112 | }, |
| 1113 | .max_size = |
| 1114 | HWIO_REO_R0_REO2SW1_RING_BASE_MSB_RING_SIZE_BMSK >> |
| 1115 | HWIO_REO_R0_REO2SW1_RING_BASE_MSB_RING_SIZE_SHFT, |
| 1116 | }, |
| 1117 | { /* REO_EXCEPTION */ |
| 1118 | /* Designating REO2TCL ring as exception ring. This ring is |
| 1119 | * similar to other REO2SW rings though it is named as REO2TCL. |
| 1120 | * Any of theREO2SW rings can be used as exception ring. |
| 1121 | */ |
| 1122 | .start_ring_id = HAL_SRNG_REO2TCL, |
| 1123 | .max_rings = 1, |
| 1124 | .entry_size = sizeof(struct reo_destination_ring) >> 2, |
| 1125 | .lmac_ring = FALSE, |
| 1126 | .ring_dir = HAL_SRNG_DST_RING, |
| 1127 | .reg_start = { |
| 1128 | HWIO_REO_R0_REO2TCL_RING_BASE_LSB_ADDR( |
| 1129 | SEQ_WCSS_UMAC_REO_REG_OFFSET), |
| 1130 | HWIO_REO_R2_REO2TCL_RING_HP_ADDR( |
| 1131 | SEQ_WCSS_UMAC_REO_REG_OFFSET) |
| 1132 | }, |
| 1133 | /* Single ring - provide ring size if multiple rings of this |
| 1134 | * type are supported |
| 1135 | */ |
| 1136 | .reg_size = {}, |
| 1137 | .max_size = |
| 1138 | HWIO_REO_R0_REO2TCL_RING_BASE_MSB_RING_SIZE_BMSK >> |
| 1139 | HWIO_REO_R0_REO2TCL_RING_BASE_MSB_RING_SIZE_SHFT, |
| 1140 | }, |
| 1141 | { /* REO_REINJECT */ |
| 1142 | .start_ring_id = HAL_SRNG_SW2REO, |
| 1143 | .max_rings = 1, |
| 1144 | .entry_size = sizeof(struct reo_entrance_ring) >> 2, |
| 1145 | .lmac_ring = FALSE, |
| 1146 | .ring_dir = HAL_SRNG_SRC_RING, |
| 1147 | .reg_start = { |
| 1148 | HWIO_REO_R0_SW2REO_RING_BASE_LSB_ADDR( |
| 1149 | SEQ_WCSS_UMAC_REO_REG_OFFSET), |
| 1150 | HWIO_REO_R2_SW2REO_RING_HP_ADDR( |
| 1151 | SEQ_WCSS_UMAC_REO_REG_OFFSET) |
| 1152 | }, |
| 1153 | /* Single ring - provide ring size if multiple rings of this |
| 1154 | * type are supported |
| 1155 | */ |
| 1156 | .reg_size = {}, |
| 1157 | .max_size = HWIO_REO_R0_SW2REO_RING_BASE_MSB_RING_SIZE_BMSK >> |
| 1158 | HWIO_REO_R0_SW2REO_RING_BASE_MSB_RING_SIZE_SHFT, |
| 1159 | }, |
| 1160 | { /* REO_CMD */ |
| 1161 | .start_ring_id = HAL_SRNG_REO_CMD, |
| 1162 | .max_rings = 1, |
| 1163 | .entry_size = (sizeof(struct tlv_32_hdr) + |
| 1164 | sizeof(struct reo_get_queue_stats)) >> 2, |
| 1165 | .lmac_ring = FALSE, |
| 1166 | .ring_dir = HAL_SRNG_SRC_RING, |
| 1167 | .reg_start = { |
| 1168 | HWIO_REO_R0_REO_CMD_RING_BASE_LSB_ADDR( |
| 1169 | SEQ_WCSS_UMAC_REO_REG_OFFSET), |
| 1170 | HWIO_REO_R2_REO_CMD_RING_HP_ADDR( |
| 1171 | SEQ_WCSS_UMAC_REO_REG_OFFSET), |
| 1172 | }, |
| 1173 | /* Single ring - provide ring size if multiple rings of this |
| 1174 | * type are supported |
| 1175 | */ |
| 1176 | .reg_size = {}, |
| 1177 | .max_size = HWIO_REO_R0_REO_CMD_RING_BASE_MSB_RING_SIZE_BMSK >> |
| 1178 | HWIO_REO_R0_REO_CMD_RING_BASE_MSB_RING_SIZE_SHFT, |
| 1179 | }, |
| 1180 | { /* REO_STATUS */ |
| 1181 | .start_ring_id = HAL_SRNG_REO_STATUS, |
| 1182 | .max_rings = 1, |
| 1183 | .entry_size = (sizeof(struct tlv_32_hdr) + |
| 1184 | sizeof(struct reo_get_queue_stats_status)) >> 2, |
| 1185 | .lmac_ring = FALSE, |
| 1186 | .ring_dir = HAL_SRNG_DST_RING, |
| 1187 | .reg_start = { |
| 1188 | HWIO_REO_R0_REO_STATUS_RING_BASE_LSB_ADDR( |
| 1189 | SEQ_WCSS_UMAC_REO_REG_OFFSET), |
| 1190 | HWIO_REO_R2_REO_STATUS_RING_HP_ADDR( |
| 1191 | SEQ_WCSS_UMAC_REO_REG_OFFSET), |
| 1192 | }, |
| 1193 | /* Single ring - provide ring size if multiple rings of this |
| 1194 | * type are supported |
| 1195 | */ |
| 1196 | .reg_size = {}, |
| 1197 | .max_size = |
| 1198 | HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_RING_SIZE_BMSK >> |
| 1199 | HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_RING_SIZE_SHFT, |
| 1200 | }, |
| 1201 | { /* TCL_DATA */ |
| 1202 | .start_ring_id = HAL_SRNG_SW2TCL1, |
| 1203 | .max_rings = 3, |
| 1204 | .entry_size = (sizeof(struct tlv_32_hdr) + |
| 1205 | sizeof(struct tcl_data_cmd)) >> 2, |
| 1206 | .lmac_ring = FALSE, |
| 1207 | .ring_dir = HAL_SRNG_SRC_RING, |
| 1208 | .reg_start = { |
| 1209 | HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_ADDR( |
| 1210 | SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET), |
| 1211 | HWIO_TCL_R2_SW2TCL1_RING_HP_ADDR( |
| 1212 | SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET), |
| 1213 | }, |
| 1214 | .reg_size = { |
| 1215 | HWIO_TCL_R0_SW2TCL2_RING_BASE_LSB_ADDR(0) - |
| 1216 | HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_ADDR(0), |
| 1217 | HWIO_TCL_R2_SW2TCL2_RING_HP_ADDR(0) - |
| 1218 | HWIO_TCL_R2_SW2TCL1_RING_HP_ADDR(0), |
| 1219 | }, |
| 1220 | .max_size = |
| 1221 | HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_RING_SIZE_BMSK >> |
| 1222 | HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_RING_SIZE_SHFT, |
| 1223 | }, |
| 1224 | { /* TCL_CMD */ |
| 1225 | .start_ring_id = HAL_SRNG_SW2TCL_CMD, |
| 1226 | .max_rings = 1, |
| 1227 | .entry_size = (sizeof(struct tlv_32_hdr) + |
| 1228 | sizeof(struct tcl_gse_cmd)) >> 2, |
| 1229 | .lmac_ring = FALSE, |
| 1230 | .ring_dir = HAL_SRNG_SRC_RING, |
| 1231 | .reg_start = { |
| 1232 | HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_LSB_ADDR( |
| 1233 | SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET), |
| 1234 | HWIO_TCL_R2_SW2TCL_CMD_RING_HP_ADDR( |
| 1235 | SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET), |
| 1236 | }, |
| 1237 | /* Single ring - provide ring size if multiple rings of this |
| 1238 | * type are supported |
| 1239 | */ |
| 1240 | .reg_size = {}, |
| 1241 | .max_size = |
| 1242 | HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_MSB_RING_SIZE_BMSK >> |
| 1243 | HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_MSB_RING_SIZE_SHFT, |
| 1244 | }, |
| 1245 | { /* TCL_STATUS */ |
| 1246 | .start_ring_id = HAL_SRNG_TCL_STATUS, |
| 1247 | .max_rings = 1, |
| 1248 | .entry_size = (sizeof(struct tlv_32_hdr) + |
| 1249 | sizeof(struct tcl_status_ring)) >> 2, |
| 1250 | .lmac_ring = FALSE, |
| 1251 | .ring_dir = HAL_SRNG_DST_RING, |
| 1252 | .reg_start = { |
| 1253 | HWIO_TCL_R0_TCL_STATUS1_RING_BASE_LSB_ADDR( |
| 1254 | SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET), |
| 1255 | HWIO_TCL_R2_TCL_STATUS1_RING_HP_ADDR( |
| 1256 | SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET), |
| 1257 | }, |
| 1258 | /* Single ring - provide ring size if multiple rings of this |
| 1259 | * type are supported |
| 1260 | */ |
| 1261 | .reg_size = {}, |
| 1262 | .max_size = |
| 1263 | HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_RING_SIZE_BMSK >> |
| 1264 | HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_RING_SIZE_SHFT, |
| 1265 | }, |
| 1266 | { /* CE_SRC */ |
| 1267 | .start_ring_id = HAL_SRNG_CE_0_SRC, |
| 1268 | .max_rings = 12, |
| 1269 | .entry_size = sizeof(struct ce_src_desc) >> 2, |
| 1270 | .lmac_ring = FALSE, |
| 1271 | .ring_dir = HAL_SRNG_SRC_RING, |
| 1272 | .reg_start = { |
| 1273 | HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR( |
| 1274 | SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_SRC_REG_OFFSET), |
| 1275 | HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR( |
| 1276 | SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_SRC_REG_OFFSET), |
| 1277 | }, |
| 1278 | .reg_size = { |
| 1279 | SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_SRC_REG_OFFSET - |
| 1280 | SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_SRC_REG_OFFSET, |
| 1281 | SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_SRC_REG_OFFSET - |
| 1282 | SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_SRC_REG_OFFSET, |
| 1283 | }, |
| 1284 | .max_size = |
| 1285 | HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_BMSK >> |
| 1286 | HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_SHFT, |
| 1287 | }, |
| 1288 | { /* CE_DST */ |
| 1289 | .start_ring_id = HAL_SRNG_CE_0_DST, |
| 1290 | .max_rings = 12, |
| 1291 | .entry_size = 8 >> 2, |
| 1292 | /*TODO: entry_size above should actually be |
| 1293 | * sizeof(struct ce_dst_desc) >> 2, but couldn't find definition |
| 1294 | * of struct ce_dst_desc in HW header files |
| 1295 | */ |
| 1296 | .lmac_ring = FALSE, |
| 1297 | .ring_dir = HAL_SRNG_SRC_RING, |
| 1298 | .reg_start = { |
| 1299 | HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR( |
| 1300 | SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET), |
| 1301 | HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR( |
| 1302 | SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET), |
| 1303 | }, |
| 1304 | .reg_size = { |
| 1305 | SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_DST_REG_OFFSET - |
| 1306 | SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET, |
| 1307 | SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_DST_REG_OFFSET - |
| 1308 | SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET, |
| 1309 | }, |
| 1310 | .max_size = |
| 1311 | HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_BMSK >> |
| 1312 | HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_SHFT, |
| 1313 | }, |
| 1314 | { /* CE_DST_STATUS */ |
| 1315 | .start_ring_id = HAL_SRNG_CE_0_DST_STATUS, |
| 1316 | .max_rings = 12, |
| 1317 | .entry_size = sizeof(struct ce_stat_desc) >> 2, |
| 1318 | .lmac_ring = FALSE, |
| 1319 | .ring_dir = HAL_SRNG_DST_RING, |
| 1320 | .reg_start = { |
| 1321 | HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR( |
| 1322 | SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET), |
| 1323 | HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR( |
| 1324 | SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET), |
| 1325 | }, |
| 1326 | /* TODO: check destination status ring registers */ |
| 1327 | .reg_size = { |
| 1328 | SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_DST_REG_OFFSET - |
| 1329 | SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET, |
| 1330 | SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_DST_REG_OFFSET - |
| 1331 | SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET, |
| 1332 | }, |
| 1333 | .max_size = |
| 1334 | HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_BMSK >> |
| 1335 | HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_SHFT, |
| 1336 | }, |
| 1337 | { /* WBM_IDLE_LINK */ |
| 1338 | .start_ring_id = HAL_SRNG_WBM_IDLE_LINK, |
| 1339 | .max_rings = 1, |
| 1340 | .entry_size = sizeof(struct wbm_link_descriptor_ring) >> 2, |
| 1341 | .lmac_ring = FALSE, |
| 1342 | .ring_dir = HAL_SRNG_SRC_RING, |
| 1343 | .reg_start = { |
| 1344 | HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_LSB_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), |
| 1345 | HWIO_WBM_R2_WBM_IDLE_LINK_RING_HP_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), |
| 1346 | }, |
| 1347 | /* Single ring - provide ring size if multiple rings of this |
| 1348 | * type are supported |
| 1349 | */ |
| 1350 | .reg_size = {}, |
| 1351 | .max_size = |
| 1352 | HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_MSB_RING_SIZE_BMSK >> |
| 1353 | HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_MSB_RING_SIZE_SHFT, |
| 1354 | }, |
| 1355 | { /* SW2WBM_RELEASE */ |
| 1356 | .start_ring_id = HAL_SRNG_WBM_SW_RELEASE, |
| 1357 | .max_rings = 1, |
| 1358 | .entry_size = sizeof(struct wbm_release_ring) >> 2, |
| 1359 | .lmac_ring = FALSE, |
| 1360 | .ring_dir = HAL_SRNG_SRC_RING, |
| 1361 | .reg_start = { |
| 1362 | HWIO_WBM_R0_SW_RELEASE_RING_BASE_LSB_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), |
| 1363 | HWIO_WBM_R2_SW_RELEASE_RING_HP_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), |
| 1364 | }, |
| 1365 | /* Single ring - provide ring size if multiple rings of this |
| 1366 | * type are supported |
| 1367 | */ |
| 1368 | .reg_size = {}, |
| 1369 | .max_size = |
| 1370 | HWIO_WBM_R0_SW_RELEASE_RING_BASE_MSB_RING_SIZE_BMSK >> |
| 1371 | HWIO_WBM_R0_SW_RELEASE_RING_BASE_MSB_RING_SIZE_SHFT, |
| 1372 | }, |
| 1373 | { /* WBM2SW_RELEASE */ |
| 1374 | .start_ring_id = HAL_SRNG_WBM2SW0_RELEASE, |
| 1375 | .max_rings = 4, |
| 1376 | .entry_size = sizeof(struct wbm_release_ring) >> 2, |
| 1377 | .lmac_ring = FALSE, |
| 1378 | .ring_dir = HAL_SRNG_DST_RING, |
| 1379 | .reg_start = { |
| 1380 | HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_LSB_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), |
| 1381 | HWIO_WBM_R2_WBM2SW0_RELEASE_RING_HP_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), |
| 1382 | }, |
| 1383 | .reg_size = { |
| 1384 | HWIO_WBM_R0_WBM2SW1_RELEASE_RING_BASE_LSB_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET) - |
| 1385 | HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_LSB_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), |
| 1386 | HWIO_WBM_R2_WBM2SW1_RELEASE_RING_HP_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET) - |
| 1387 | HWIO_WBM_R2_WBM2SW0_RELEASE_RING_HP_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), |
| 1388 | }, |
| 1389 | .max_size = |
| 1390 | HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_MSB_RING_SIZE_BMSK >> |
| 1391 | HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_MSB_RING_SIZE_SHFT, |
| 1392 | }, |
| 1393 | { /* RXDMA_BUF */ |
| 1394 | .start_ring_id = HAL_SRNG_WMAC1_SW2RXDMA0_BUF0, |
| 1395 | #ifdef IPA_OFFLOAD |
| 1396 | .max_rings = 3, |
| 1397 | #else |
| 1398 | .max_rings = 2, |
| 1399 | #endif |
| 1400 | .entry_size = sizeof(struct wbm_buffer_ring) >> 2, |
| 1401 | .lmac_ring = TRUE, |
| 1402 | .ring_dir = HAL_SRNG_SRC_RING, |
| 1403 | /* reg_start is not set because LMAC rings are not accessed |
| 1404 | * from host |
| 1405 | */ |
| 1406 | .reg_start = {}, |
| 1407 | .reg_size = {}, |
| 1408 | .max_size = HAL_RXDMA_MAX_RING_SIZE, |
| 1409 | }, |
| 1410 | { /* RXDMA_DST */ |
| 1411 | .start_ring_id = HAL_SRNG_WMAC1_RXDMA2SW0, |
| 1412 | .max_rings = 1, |
| 1413 | .entry_size = sizeof(struct reo_entrance_ring) >> 2, |
| 1414 | .lmac_ring = TRUE, |
| 1415 | .ring_dir = HAL_SRNG_DST_RING, |
| 1416 | /* reg_start is not set because LMAC rings are not accessed |
| 1417 | * from host |
| 1418 | */ |
| 1419 | .reg_start = {}, |
| 1420 | .reg_size = {}, |
| 1421 | .max_size = HAL_RXDMA_MAX_RING_SIZE, |
| 1422 | }, |
| 1423 | { /* RXDMA_MONITOR_BUF */ |
| 1424 | .start_ring_id = HAL_SRNG_WMAC1_SW2RXDMA2_BUF, |
| 1425 | .max_rings = 1, |
| 1426 | .entry_size = sizeof(struct wbm_buffer_ring) >> 2, |
| 1427 | .lmac_ring = TRUE, |
| 1428 | .ring_dir = HAL_SRNG_SRC_RING, |
| 1429 | /* reg_start is not set because LMAC rings are not accessed |
| 1430 | * from host |
| 1431 | */ |
| 1432 | .reg_start = {}, |
| 1433 | .reg_size = {}, |
| 1434 | .max_size = HAL_RXDMA_MAX_RING_SIZE, |
| 1435 | }, |
| 1436 | { /* RXDMA_MONITOR_STATUS */ |
| 1437 | .start_ring_id = HAL_SRNG_WMAC1_SW2RXDMA1_STATBUF, |
| 1438 | .max_rings = 1, |
| 1439 | .entry_size = sizeof(struct wbm_buffer_ring) >> 2, |
| 1440 | .lmac_ring = TRUE, |
| 1441 | .ring_dir = HAL_SRNG_SRC_RING, |
| 1442 | /* reg_start is not set because LMAC rings are not accessed |
| 1443 | * from host |
| 1444 | */ |
| 1445 | .reg_start = {}, |
| 1446 | .reg_size = {}, |
| 1447 | .max_size = HAL_RXDMA_MAX_RING_SIZE, |
| 1448 | }, |
| 1449 | { /* RXDMA_MONITOR_DST */ |
| 1450 | .start_ring_id = HAL_SRNG_WMAC1_RXDMA2SW1, |
| 1451 | .max_rings = 1, |
| 1452 | .entry_size = sizeof(struct reo_entrance_ring) >> 2, |
| 1453 | .lmac_ring = TRUE, |
| 1454 | .ring_dir = HAL_SRNG_DST_RING, |
| 1455 | /* reg_start is not set because LMAC rings are not accessed |
| 1456 | * from host |
| 1457 | */ |
| 1458 | .reg_start = {}, |
| 1459 | .reg_size = {}, |
| 1460 | .max_size = HAL_RXDMA_MAX_RING_SIZE, |
| 1461 | }, |
| 1462 | { /* RXDMA_MONITOR_DESC */ |
| 1463 | .start_ring_id = HAL_SRNG_WMAC1_SW2RXDMA1_DESC, |
| 1464 | .max_rings = 1, |
| 1465 | .entry_size = sizeof(struct wbm_buffer_ring) >> 2, |
| 1466 | .lmac_ring = TRUE, |
| 1467 | .ring_dir = HAL_SRNG_SRC_RING, |
| 1468 | /* reg_start is not set because LMAC rings are not accessed |
| 1469 | * from host |
| 1470 | */ |
| 1471 | .reg_start = {}, |
| 1472 | .reg_size = {}, |
| 1473 | .max_size = HAL_RXDMA_MAX_RING_SIZE, |
| 1474 | }, |
| 1475 | { /* DIR_BUF_RX_DMA_SRC */ |
| 1476 | .start_ring_id = HAL_SRNG_DIR_BUF_RX_SRC_DMA_RING, |
Abhiram Jogadenu | d81f5b1 | 2019-02-12 12:05:59 +0530 | [diff] [blame] | 1477 | /* one ring for spectral and one ring for cfr */ |
| 1478 | .max_rings = 2, |
Balamurugan Mahalingam | d015964 | 2018-07-11 15:02:29 +0530 | [diff] [blame] | 1479 | .entry_size = 2, |
| 1480 | .lmac_ring = TRUE, |
| 1481 | .ring_dir = HAL_SRNG_SRC_RING, |
| 1482 | /* reg_start is not set because LMAC rings are not accessed |
| 1483 | * from host |
| 1484 | */ |
| 1485 | .reg_start = {}, |
| 1486 | .reg_size = {}, |
| 1487 | .max_size = HAL_RXDMA_MAX_RING_SIZE, |
| 1488 | }, |
| 1489 | #ifdef WLAN_FEATURE_CIF_CFR |
| 1490 | { /* WIFI_POS_SRC */ |
| 1491 | .start_ring_id = HAL_SRNG_WIFI_POS_SRC_DMA_RING, |
| 1492 | .max_rings = 1, |
| 1493 | .entry_size = sizeof(wmi_oem_dma_buf_release_entry) >> 2, |
| 1494 | .lmac_ring = TRUE, |
| 1495 | .ring_dir = HAL_SRNG_SRC_RING, |
| 1496 | /* reg_start is not set because LMAC rings are not accessed |
| 1497 | * from host |
| 1498 | */ |
| 1499 | .reg_start = {}, |
| 1500 | .reg_size = {}, |
| 1501 | .max_size = HAL_RXDMA_MAX_RING_SIZE, |
| 1502 | }, |
| 1503 | #endif |
| 1504 | }; |
| 1505 | |
Balamurugan Mahalingam | 5d80641 | 2018-07-30 18:04:15 +0530 | [diff] [blame] | 1506 | int32_t hal_hw_reg_offset_qca8074v2[] = { |
Balamurugan Mahalingam | d015964 | 2018-07-11 15:02:29 +0530 | [diff] [blame] | 1507 | /* dst */ |
| 1508 | REG_OFFSET(DST, HP), |
| 1509 | REG_OFFSET(DST, TP), |
| 1510 | REG_OFFSET(DST, ID), |
| 1511 | REG_OFFSET(DST, MISC), |
| 1512 | REG_OFFSET(DST, HP_ADDR_LSB), |
| 1513 | REG_OFFSET(DST, HP_ADDR_MSB), |
| 1514 | REG_OFFSET(DST, MSI1_BASE_LSB), |
| 1515 | REG_OFFSET(DST, MSI1_BASE_MSB), |
| 1516 | REG_OFFSET(DST, MSI1_DATA), |
| 1517 | REG_OFFSET(DST, BASE_LSB), |
| 1518 | REG_OFFSET(DST, BASE_MSB), |
| 1519 | REG_OFFSET(DST, PRODUCER_INT_SETUP), |
| 1520 | /* src */ |
| 1521 | REG_OFFSET(SRC, HP), |
| 1522 | REG_OFFSET(SRC, TP), |
| 1523 | REG_OFFSET(SRC, ID), |
| 1524 | REG_OFFSET(SRC, MISC), |
| 1525 | REG_OFFSET(SRC, TP_ADDR_LSB), |
| 1526 | REG_OFFSET(SRC, TP_ADDR_MSB), |
| 1527 | REG_OFFSET(SRC, MSI1_BASE_LSB), |
| 1528 | REG_OFFSET(SRC, MSI1_BASE_MSB), |
| 1529 | REG_OFFSET(SRC, MSI1_DATA), |
| 1530 | REG_OFFSET(SRC, BASE_LSB), |
| 1531 | REG_OFFSET(SRC, BASE_MSB), |
| 1532 | REG_OFFSET(SRC, CONSUMER_INT_SETUP_IX0), |
| 1533 | REG_OFFSET(SRC, CONSUMER_INT_SETUP_IX1), |
| 1534 | }; |
| 1535 | |
Balamurugan Mahalingam | 5d80641 | 2018-07-30 18:04:15 +0530 | [diff] [blame] | 1536 | |
| 1537 | /** |
| 1538 | * hal_qca8074v2_attach() - Attach 8074v2 target specific hal_soc ops, |
| 1539 | * offset and srng table |
| 1540 | */ |
| 1541 | void hal_qca8074v2_attach(struct hal_soc *hal_soc) |
Balamurugan Mahalingam | d015964 | 2018-07-11 15:02:29 +0530 | [diff] [blame] | 1542 | { |
Balamurugan Mahalingam | 5d80641 | 2018-07-30 18:04:15 +0530 | [diff] [blame] | 1543 | hal_soc->hw_srng_table = hw_srng_table_8074v2; |
| 1544 | hal_soc->hal_hw_reg_offset = hal_hw_reg_offset_qca8074v2; |
| 1545 | hal_soc->ops = &qca8074v2_hal_hw_txrx_ops; |
Balamurugan Mahalingam | d015964 | 2018-07-11 15:02:29 +0530 | [diff] [blame] | 1546 | } |