Balamurugan Mahalingam | d015964 | 2018-07-11 15:02:29 +0530 | [diff] [blame] | 1 | /* |
sumedh baikady | 3ee6100 | 2019-03-12 10:50:37 -0700 | [diff] [blame] | 2 | * Copyright (c) 2016-2019 The Linux Foundation. All rights reserved. |
Balamurugan Mahalingam | d015964 | 2018-07-11 15:02:29 +0530 | [diff] [blame] | 3 | * |
Balamurugan Mahalingam | 5d80641 | 2018-07-30 18:04:15 +0530 | [diff] [blame] | 4 | * Permission to use, copy, modify, and/or distribute this software for |
| 5 | * any purpose with or without fee is hereby granted, provided that the |
| 6 | * above copyright notice and this permission notice appear in all |
| 7 | * copies. |
Balamurugan Mahalingam | d015964 | 2018-07-11 15:02:29 +0530 | [diff] [blame] | 8 | * |
Balamurugan Mahalingam | 5d80641 | 2018-07-30 18:04:15 +0530 | [diff] [blame] | 9 | * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL |
| 10 | * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED |
| 11 | * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE |
| 12 | * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL |
| 13 | * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR |
| 14 | * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER |
| 15 | * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR |
| 16 | * PERFORMANCE OF THIS SOFTWARE. |
Balamurugan Mahalingam | d015964 | 2018-07-11 15:02:29 +0530 | [diff] [blame] | 17 | */ |
| 18 | |
| 19 | #ifndef _HAL_HW_INTERNAL_H_ |
| 20 | #define _HAL_HW_INTERNAL_H_ |
| 21 | #include "qdf_types.h" |
| 22 | #include "qdf_lock.h" |
| 23 | #include "qdf_mem.h" |
| 24 | #include "rx_msdu_link.h" |
| 25 | #include "rx_reo_queue.h" |
| 26 | #include "rx_reo_queue_ext.h" |
| 27 | #include "wcss_seq_hwiobase.h" |
| 28 | #include "tlv_hdr.h" |
| 29 | #include "tlv_tag_def.h" |
| 30 | #include "reo_destination_ring.h" |
| 31 | #include "reo_reg_seq_hwioreg.h" |
| 32 | #include "reo_entrance_ring.h" |
| 33 | #include "reo_get_queue_stats.h" |
| 34 | #include "reo_get_queue_stats_status.h" |
| 35 | #include "tcl_data_cmd.h" |
| 36 | #include "tcl_gse_cmd.h" |
| 37 | #include "tcl_status_ring.h" |
| 38 | #include "mac_tcl_reg_seq_hwioreg.h" |
| 39 | #include "ce_src_desc.h" |
| 40 | #include "ce_stat_desc.h" |
| 41 | #include "wfss_ce_reg_seq_hwioreg.h" |
| 42 | #include "wbm_link_descriptor_ring.h" |
| 43 | #include "wbm_reg_seq_hwioreg.h" |
| 44 | #include "wbm_buffer_ring.h" |
| 45 | #include "wbm_release_ring.h" |
| 46 | #include "rx_msdu_desc_info.h" |
| 47 | #include "rx_mpdu_start.h" |
| 48 | #include "rx_mpdu_end.h" |
| 49 | #include "rx_msdu_start.h" |
| 50 | #include "rx_msdu_end.h" |
| 51 | #include "rx_attention.h" |
| 52 | #include "rx_ppdu_start.h" |
| 53 | #include "rx_ppdu_start_user_info.h" |
| 54 | #include "rx_ppdu_end_user_stats.h" |
| 55 | #include "rx_ppdu_end_user_stats_ext.h" |
| 56 | #include "rx_mpdu_desc_info.h" |
| 57 | #include "rxpcu_ppdu_end_info.h" |
| 58 | #include "phyrx_he_sig_a_su.h" |
| 59 | #include "phyrx_he_sig_a_mu_dl.h" |
Vevek Venkatesan | 735d9fe | 2019-06-06 19:21:25 +0530 | [diff] [blame] | 60 | #if defined(QCA_WIFI_QCA6290_11AX_MU_UL) && defined(QCA_WIFI_QCA6290_11AX) |
chenguo | f51e922 | 2018-04-20 14:34:25 +0800 | [diff] [blame] | 61 | #include "phyrx_he_sig_a_mu_ul.h" |
| 62 | #endif |
Balamurugan Mahalingam | d015964 | 2018-07-11 15:02:29 +0530 | [diff] [blame] | 63 | #include "phyrx_he_sig_b1_mu.h" |
| 64 | #include "phyrx_he_sig_b2_mu.h" |
| 65 | #include "phyrx_he_sig_b2_ofdma.h" |
| 66 | #include "phyrx_l_sig_a.h" |
| 67 | #include "phyrx_l_sig_b.h" |
| 68 | #include "phyrx_vht_sig_a.h" |
| 69 | #include "phyrx_ht_sig.h" |
| 70 | #include "tx_msdu_extension.h" |
| 71 | #include "receive_rssi_info.h" |
| 72 | #include "phyrx_pkt_end.h" |
| 73 | #include "phyrx_rssi_legacy.h" |
| 74 | #include "wcss_version.h" |
| 75 | #include "rx_msdu_link.h" |
| 76 | |
| 77 | #define HAL_SRNG_REO_EXCEPTION HAL_SRNG_REO2SW1 |
| 78 | #define HAL_SRNG_REO_ALTERNATE_SELECT 0x7 |
Karunakar Dasineni | 26ebbe4 | 2018-05-31 07:59:10 -0700 | [diff] [blame] | 79 | #define HAL_NON_QOS_TID 16 |
Balamurugan Mahalingam | d015964 | 2018-07-11 15:02:29 +0530 | [diff] [blame] | 80 | |
| 81 | /* calculate the register address offset from bar0 of shadow register x */ |
Pramod Simha | 627278c | 2018-08-14 11:58:29 -0700 | [diff] [blame] | 82 | #ifdef QCA_WIFI_QCA6390 |
| 83 | #define SHADOW_REGISTER(x) (0x000008FC + (4 * (x))) |
| 84 | #else |
Balamurugan Mahalingam | d015964 | 2018-07-11 15:02:29 +0530 | [diff] [blame] | 85 | #define SHADOW_REGISTER(x) (0x00003024 + (4 * (x))) |
Pramod Simha | 627278c | 2018-08-14 11:58:29 -0700 | [diff] [blame] | 86 | #endif |
Balamurugan Mahalingam | d015964 | 2018-07-11 15:02:29 +0530 | [diff] [blame] | 87 | |
| 88 | /* TODO: Check if the following can be provided directly by HW headers */ |
| 89 | #define SRNG_LOOP_CNT_MASK REO_DESTINATION_RING_15_LOOPING_COUNT_MASK |
| 90 | #define SRNG_LOOP_CNT_LSB REO_DESTINATION_RING_15_LOOPING_COUNT_LSB |
| 91 | |
sumedh baikady | 3ee6100 | 2019-03-12 10:50:37 -0700 | [diff] [blame] | 92 | #define HAL_DEFAULT_BE_BK_VI_REO_TIMEOUT_MS 100 /* milliseconds */ |
| 93 | #define HAL_DEFAULT_VO_REO_TIMEOUT_MS 40 /* milliseconds */ |
Balamurugan Mahalingam | d015964 | 2018-07-11 15:02:29 +0530 | [diff] [blame] | 94 | |
| 95 | #define HAL_DESC_SET_FIELD(_desc, _word, _fld, _value) do { \ |
| 96 | ((uint32_t *)(_desc))[(_word ## _ ## _fld ## _OFFSET) >> 2] &= \ |
| 97 | ~(_word ## _ ## _fld ## _MASK); \ |
| 98 | ((uint32_t *)(_desc))[(_word ## _ ## _fld ## _OFFSET) >> 2] |= \ |
| 99 | ((_value) << _word ## _ ## _fld ## _LSB); \ |
| 100 | } while (0) |
| 101 | |
| 102 | #define HAL_SM(_reg, _fld, _val) \ |
| 103 | (((_val) << (_reg ## _ ## _fld ## _SHFT)) & \ |
| 104 | (_reg ## _ ## _fld ## _BMSK)) |
| 105 | |
| 106 | #define HAL_MS(_reg, _fld, _val) \ |
| 107 | (((_val) & (_reg ## _ ## _fld ## _BMSK)) >> \ |
| 108 | (_reg ## _ ## _fld ## _SHFT)) |
| 109 | |
| 110 | #define HAL_REG_WRITE(_soc, _reg, _value) \ |
| 111 | hal_write32_mb(_soc, (_reg), (_value)) |
| 112 | |
| 113 | #define HAL_REG_READ(_soc, _offset) \ |
| 114 | hal_read32_mb(_soc, (_offset)) |
| 115 | |
| 116 | #define WBM_IDLE_DESC_LIST 1 |
| 117 | |
| 118 | /** |
| 119 | * Common SRNG register access macros: |
| 120 | * The SRNG registers are distributed across various UMAC and LMAC HW blocks, |
| 121 | * but the register group and format is exactly same for all rings, with some |
| 122 | * difference between producer rings (these are 'producer rings' with respect |
| 123 | * to HW and referred as 'destination rings' in SW) and consumer rings (these |
| 124 | * are 'consumer rings' with respect to HW and |
| 125 | * referred as 'source rings' in SW). |
| 126 | * The following macros provide uniform access to all SRNG rings. |
| 127 | */ |
| 128 | |
| 129 | /* SRNG registers are split among two groups R0 and R2 and following |
| 130 | * definitions identify the group to which each register belongs to |
| 131 | */ |
| 132 | #define R0_INDEX 0 |
| 133 | #define R2_INDEX 1 |
| 134 | |
| 135 | #define HWREG_INDEX(_reg_group) _reg_group ## _ ## INDEX |
| 136 | |
| 137 | /* Registers in R0 group */ |
| 138 | #define BASE_LSB_GROUP R0 |
| 139 | #define BASE_MSB_GROUP R0 |
| 140 | #define ID_GROUP R0 |
| 141 | #define STATUS_GROUP R0 |
| 142 | #define MISC_GROUP R0 |
| 143 | #define HP_ADDR_LSB_GROUP R0 |
| 144 | #define HP_ADDR_MSB_GROUP R0 |
| 145 | #define PRODUCER_INT_SETUP_GROUP R0 |
| 146 | #define PRODUCER_INT_STATUS_GROUP R0 |
| 147 | #define PRODUCER_FULL_COUNTER_GROUP R0 |
| 148 | #define MSI1_BASE_LSB_GROUP R0 |
| 149 | #define MSI1_BASE_MSB_GROUP R0 |
| 150 | #define MSI1_DATA_GROUP R0 |
| 151 | #define HP_TP_SW_OFFSET_GROUP R0 |
| 152 | #define TP_ADDR_LSB_GROUP R0 |
| 153 | #define TP_ADDR_MSB_GROUP R0 |
| 154 | #define CONSUMER_INT_SETUP_IX0_GROUP R0 |
| 155 | #define CONSUMER_INT_SETUP_IX1_GROUP R0 |
| 156 | #define CONSUMER_INT_STATUS_GROUP R0 |
| 157 | #define CONSUMER_EMPTY_COUNTER_GROUP R0 |
| 158 | #define CONSUMER_PREFETCH_TIMER_GROUP R0 |
| 159 | #define CONSUMER_PREFETCH_STATUS_GROUP R0 |
| 160 | |
| 161 | /* Registers in R2 group */ |
| 162 | #define HP_GROUP R2 |
| 163 | #define TP_GROUP R2 |
| 164 | |
| 165 | /** |
| 166 | * Register definitions for all SRNG based rings are same, except few |
| 167 | * differences between source (HW consumer) and destination (HW producer) |
| 168 | * registers. Following macros definitions provide generic access to all |
| 169 | * SRNG based rings. |
| 170 | * For source rings, we will use the register/field definitions of SW2TCL1 |
| 171 | * ring defined in the HW header file mac_tcl_reg_seq_hwioreg.h. To setup |
| 172 | * individual fields, SRNG_SM macros should be used with fields specified |
| 173 | * using SRNG_SRC_FLD(<register>, <field>), Register writes should be done |
| 174 | * using SRNG_SRC_REG_WRITE(<hal_srng>, <register>, <value>). |
| 175 | * Similarly for destination rings we will use definitions of REO2SW1 ring |
| 176 | * defined in the register reo_destination_ring.h. To setup individual |
| 177 | * fields SRNG_SM macros should be used with fields specified using |
| 178 | * SRNG_DST_FLD(<register>, <field>). Register writes should be done using |
| 179 | * SRNG_DST_REG_WRITE(<hal_srng>, <register>, <value>). |
| 180 | */ |
| 181 | |
| 182 | #define SRNG_DST_REG_OFFSET(_reg, _reg_group) \ |
| 183 | HWIO_REO_ ## _reg_group ## _REO2SW1_RING_ ## _reg##_ADDR(0) |
| 184 | |
| 185 | #define SRNG_SRC_REG_OFFSET(_reg, _reg_group) \ |
| 186 | HWIO_TCL_ ## _reg_group ## _SW2TCL1_RING_ ## _reg ## _ADDR(0) |
| 187 | |
| 188 | #define _SRNG_DST_FLD(_reg_group, _reg_fld) \ |
| 189 | HWIO_REO_ ## _reg_group ## _REO2SW1_RING_ ## _reg_fld |
| 190 | #define _SRNG_SRC_FLD(_reg_group, _reg_fld) \ |
| 191 | HWIO_TCL_ ## _reg_group ## _SW2TCL1_RING_ ## _reg_fld |
| 192 | |
| 193 | #define _SRNG_FLD(_reg_group, _reg_fld, _dir) \ |
| 194 | _SRNG_ ## _dir ## _FLD(_reg_group, _reg_fld) |
| 195 | |
| 196 | #define SRNG_DST_FLD(_reg, _f) _SRNG_FLD(_reg ## _GROUP, _reg ## _ ## _f, DST) |
| 197 | #define SRNG_SRC_FLD(_reg, _f) _SRNG_FLD(_reg ## _GROUP, _reg ## _ ## _f, SRC) |
| 198 | |
| 199 | #define SRNG_SRC_R0_START_OFFSET SRNG_SRC_REG_OFFSET(BASE_LSB, R0) |
| 200 | #define SRNG_DST_R0_START_OFFSET SRNG_DST_REG_OFFSET(BASE_LSB, R0) |
| 201 | |
| 202 | #define SRNG_SRC_R2_START_OFFSET SRNG_SRC_REG_OFFSET(HP, R2) |
| 203 | #define SRNG_DST_R2_START_OFFSET SRNG_DST_REG_OFFSET(HP, R2) |
| 204 | |
| 205 | #define SRNG_SRC_START_OFFSET(_reg_group) \ |
| 206 | SRNG_SRC_ ## _reg_group ## _START_OFFSET |
| 207 | #define SRNG_DST_START_OFFSET(_reg_group) \ |
| 208 | SRNG_DST_ ## _reg_group ## _START_OFFSET |
| 209 | #define SRNG_REG_ADDR(_srng, _reg, _reg_group, _dir) \ |
| 210 | ((_srng)->hwreg_base[HWREG_INDEX(_reg_group)] + \ |
| 211 | ((_srng)->hal_soc->hal_hw_reg_offset[_dir ## _ ##_reg])) |
| 212 | |
| 213 | #define CALCULATE_REG_OFFSET(_dir, _reg, _reg_group) \ |
| 214 | (SRNG_ ## _dir ## _REG_OFFSET(_reg, _reg_group) - \ |
| 215 | SRNG_ ## _dir ## _START_OFFSET(_reg_group)) |
| 216 | |
| 217 | #define REG_OFFSET(_dir, _reg) \ |
| 218 | CALCULATE_REG_OFFSET(_dir, _reg, _reg ## _GROUP) |
| 219 | |
| 220 | #define SRNG_DST_ADDR(_srng, _reg) \ |
| 221 | SRNG_REG_ADDR(_srng, _reg, _reg ## _GROUP, DST) |
| 222 | |
| 223 | #define SRNG_SRC_ADDR(_srng, _reg) \ |
| 224 | SRNG_REG_ADDR(_srng, _reg, _reg ## _GROUP, SRC) |
| 225 | |
| 226 | #define SRNG_REG_WRITE(_srng, _reg, _value, _dir) \ |
| 227 | hal_write_address_32_mb(_srng->hal_soc, \ |
| 228 | SRNG_ ## _dir ## _ADDR(_srng, _reg), (_value)) |
| 229 | |
| 230 | #define SRNG_REG_READ(_srng, _reg, _dir) \ |
| 231 | hal_read_address_32_mb(_srng->hal_soc, \ |
| 232 | SRNG_ ## _dir ## _ADDR(_srng, _reg)) |
| 233 | |
| 234 | #define SRNG_SRC_REG_WRITE(_srng, _reg, _value) \ |
| 235 | SRNG_REG_WRITE(_srng, _reg, _value, SRC) |
| 236 | |
| 237 | #define SRNG_DST_REG_WRITE(_srng, _reg, _value) \ |
| 238 | SRNG_REG_WRITE(_srng, _reg, _value, DST) |
| 239 | |
| 240 | #define SRNG_SRC_REG_READ(_srng, _reg) \ |
| 241 | SRNG_REG_READ(_srng, _reg, SRC) |
| 242 | |
Venkata Sharath Chandra Manchala | 443b9b4 | 2018-10-10 12:04:54 -0700 | [diff] [blame] | 243 | #define SRNG_DST_REG_READ(_srng, _reg) \ |
| 244 | SRNG_REG_READ(_srng, _reg, DST) |
| 245 | |
Balamurugan Mahalingam | d015964 | 2018-07-11 15:02:29 +0530 | [diff] [blame] | 246 | #define _SRNG_FM(_reg_fld) _reg_fld ## _BMSK |
| 247 | #define _SRNG_FS(_reg_fld) _reg_fld ## _SHFT |
| 248 | |
| 249 | #define SRNG_SM(_reg_fld, _val) \ |
| 250 | (((_val) << _SRNG_FS(_reg_fld)) & _SRNG_FM(_reg_fld)) |
| 251 | |
| 252 | #define SRNG_MS(_reg_fld, _val) \ |
| 253 | (((_val) & _SRNG_FM(_reg_fld)) >> _SRNG_FS(_reg_fld)) |
| 254 | |
| 255 | #define SRNG_MAX_SIZE_DWORDS \ |
| 256 | (SRNG_MS(SRNG_SRC_FLD(BASE_MSB, RING_SIZE), 0xffffffff)) |
| 257 | |
| 258 | /** |
| 259 | * HW ring configuration table to identify hardware ring attributes like |
| 260 | * register addresses, number of rings, ring entry size etc., for each type |
| 261 | * of SRNG ring. |
| 262 | * |
| 263 | * Currently there is just one HW ring table, but there could be multiple |
| 264 | * configurations in future based on HW variants from the same wifi3.0 family |
| 265 | * and hence need to be attached with hal_soc based on HW type |
| 266 | */ |
| 267 | #define HAL_SRNG_CONFIG(_hal_soc, _ring_type) \ |
| 268 | (&_hal_soc->hw_srng_table[_ring_type]) |
| 269 | |
| 270 | enum SRNG_REGISTERS { |
| 271 | DST_HP = 0, |
| 272 | DST_TP, |
| 273 | DST_ID, |
| 274 | DST_MISC, |
| 275 | DST_HP_ADDR_LSB, |
| 276 | DST_HP_ADDR_MSB, |
| 277 | DST_MSI1_BASE_LSB, |
| 278 | DST_MSI1_BASE_MSB, |
| 279 | DST_MSI1_DATA, |
| 280 | DST_BASE_LSB, |
| 281 | DST_BASE_MSB, |
| 282 | DST_PRODUCER_INT_SETUP, |
| 283 | |
| 284 | SRC_HP, |
| 285 | SRC_TP, |
| 286 | SRC_ID, |
| 287 | SRC_MISC, |
| 288 | SRC_TP_ADDR_LSB, |
| 289 | SRC_TP_ADDR_MSB, |
| 290 | SRC_MSI1_BASE_LSB, |
| 291 | SRC_MSI1_BASE_MSB, |
| 292 | SRC_MSI1_DATA, |
| 293 | SRC_BASE_LSB, |
| 294 | SRC_BASE_MSB, |
| 295 | SRC_CONSUMER_INT_SETUP_IX0, |
| 296 | SRC_CONSUMER_INT_SETUP_IX1, |
| 297 | }; |
| 298 | |
| 299 | /** |
| 300 | * hal_set_link_desc_addr - Setup link descriptor in a buffer_addr_info |
| 301 | * HW structure |
| 302 | * |
| 303 | * @desc: Descriptor entry (from WBM_IDLE_LINK ring) |
| 304 | * @cookie: SW cookie for the buffer/descriptor |
| 305 | * @link_desc_paddr: Physical address of link descriptor entry |
| 306 | * |
| 307 | */ |
| 308 | static inline void hal_set_link_desc_addr(void *desc, uint32_t cookie, |
| 309 | qdf_dma_addr_t link_desc_paddr) |
| 310 | { |
| 311 | uint32_t *buf_addr = (uint32_t *)desc; |
| 312 | |
| 313 | HAL_DESC_SET_FIELD(buf_addr, BUFFER_ADDR_INFO_0, BUFFER_ADDR_31_0, |
| 314 | link_desc_paddr & 0xffffffff); |
| 315 | HAL_DESC_SET_FIELD(buf_addr, BUFFER_ADDR_INFO_1, BUFFER_ADDR_39_32, |
| 316 | (uint64_t)link_desc_paddr >> 32); |
| 317 | HAL_DESC_SET_FIELD(buf_addr, BUFFER_ADDR_INFO_1, RETURN_BUFFER_MANAGER, |
| 318 | WBM_IDLE_DESC_LIST); |
| 319 | HAL_DESC_SET_FIELD(buf_addr, BUFFER_ADDR_INFO_1, SW_BUFFER_COOKIE, |
| 320 | cookie); |
| 321 | } |
| 322 | |
| 323 | /** |
| 324 | * hal_get_reo_qdesc_size - Get size of reo queue descriptor |
| 325 | * |
| 326 | * @hal_soc: Opaque HAL SOC handle |
| 327 | * @ba_window_size: BlockAck window size |
Karunakar Dasineni | 26ebbe4 | 2018-05-31 07:59:10 -0700 | [diff] [blame] | 328 | * @tid: TID number |
Balamurugan Mahalingam | d015964 | 2018-07-11 15:02:29 +0530 | [diff] [blame] | 329 | * |
| 330 | */ |
| 331 | static inline uint32_t hal_get_reo_qdesc_size(void *hal_soc, |
Karunakar Dasineni | 26ebbe4 | 2018-05-31 07:59:10 -0700 | [diff] [blame] | 332 | uint32_t ba_window_size, int tid) |
Balamurugan Mahalingam | d015964 | 2018-07-11 15:02:29 +0530 | [diff] [blame] | 333 | { |
Karunakar Dasineni | 26ebbe4 | 2018-05-31 07:59:10 -0700 | [diff] [blame] | 334 | /* Return descriptor size corresponding to window size of 2 since |
| 335 | * we set ba_window_size to 2 while setting up REO descriptors as |
| 336 | * a WAR to get 2k jump exception aggregates are received without |
| 337 | * a BA session. |
| 338 | */ |
| 339 | if (ba_window_size <= 1) { |
| 340 | if (tid != HAL_NON_QOS_TID) |
| 341 | return sizeof(struct rx_reo_queue) + |
| 342 | sizeof(struct rx_reo_queue_ext); |
| 343 | else |
| 344 | return sizeof(struct rx_reo_queue); |
| 345 | } |
Balamurugan Mahalingam | d015964 | 2018-07-11 15:02:29 +0530 | [diff] [blame] | 346 | |
| 347 | if (ba_window_size <= 105) |
| 348 | return sizeof(struct rx_reo_queue) + |
| 349 | sizeof(struct rx_reo_queue_ext); |
| 350 | |
| 351 | if (ba_window_size <= 210) |
| 352 | return sizeof(struct rx_reo_queue) + |
| 353 | (2 * sizeof(struct rx_reo_queue_ext)); |
| 354 | |
| 355 | return sizeof(struct rx_reo_queue) + |
| 356 | (3 * sizeof(struct rx_reo_queue_ext)); |
| 357 | } |
| 358 | |
| 359 | #endif /* _HAL_HW_INTERNAL_H_ */ |